1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qapi/error.h" 30 #include "qapi/visitor.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/hostmem.h" 33 #include "sysemu/numa.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/runstate.h" 37 #include "qemu/log.h" 38 #include "hw/fw-path-provider.h" 39 #include "elf.h" 40 #include "net/net.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/cpus.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_ppc.h" 45 #include "migration/misc.h" 46 #include "migration/qemu-file-types.h" 47 #include "migration/global_state.h" 48 #include "migration/register.h" 49 #include "migration/blocker.h" 50 #include "mmu-hash64.h" 51 #include "mmu-book3s-v3.h" 52 #include "cpu-models.h" 53 #include "hw/core/cpu.h" 54 55 #include "hw/boards.h" 56 #include "hw/ppc/ppc.h" 57 #include "hw/loader.h" 58 59 #include "hw/ppc/fdt.h" 60 #include "hw/ppc/spapr.h" 61 #include "hw/ppc/spapr_vio.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/pci-host/spapr.h" 64 #include "hw/pci/msi.h" 65 66 #include "hw/pci/pci.h" 67 #include "hw/scsi/scsi.h" 68 #include "hw/virtio/virtio-scsi.h" 69 #include "hw/virtio/vhost-scsi-common.h" 70 71 #include "exec/address-spaces.h" 72 #include "exec/ram_addr.h" 73 #include "hw/usb.h" 74 #include "qemu/config-file.h" 75 #include "qemu/error-report.h" 76 #include "trace.h" 77 #include "hw/nmi.h" 78 #include "hw/intc/intc.h" 79 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 #include "hw/ppc/spapr_nvdimm.h" 84 85 #include "monitor/monitor.h" 86 87 #include <libfdt.h> 88 89 /* SLOF memory layout: 90 * 91 * SLOF raw image loaded at 0, copies its romfs right below the flat 92 * device-tree, then position SLOF itself 31M below that 93 * 94 * So we set FW_OVERHEAD to 40MB which should account for all of that 95 * and more 96 * 97 * We load our kernel at 4M, leaving space for SLOF initial image 98 */ 99 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 100 #define FW_MAX_SIZE 0x400000 101 #define FW_FILE_NAME "slof.bin" 102 #define FW_OVERHEAD 0x2800000 103 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 104 105 #define MIN_RMA_SLOF (128 * MiB) 106 107 #define PHANDLE_INTC 0x00001111 108 109 /* These two functions implement the VCPU id numbering: one to compute them 110 * all and one to identify thread 0 of a VCORE. Any change to the first one 111 * is likely to have an impact on the second one, so let's keep them close. 112 */ 113 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 114 { 115 MachineState *ms = MACHINE(spapr); 116 unsigned int smp_threads = ms->smp.threads; 117 118 assert(spapr->vsmt); 119 return 120 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 121 } 122 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 123 PowerPCCPU *cpu) 124 { 125 assert(spapr->vsmt); 126 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 127 } 128 129 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 130 { 131 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 132 * and newer QEMUs don't even have them. In both cases, we don't want 133 * to send anything on the wire. 134 */ 135 return false; 136 } 137 138 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 139 .name = "icp/server", 140 .version_id = 1, 141 .minimum_version_id = 1, 142 .needed = pre_2_10_vmstate_dummy_icp_needed, 143 .fields = (VMStateField[]) { 144 VMSTATE_UNUSED(4), /* uint32_t xirr */ 145 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 146 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 147 VMSTATE_END_OF_LIST() 148 }, 149 }; 150 151 static void pre_2_10_vmstate_register_dummy_icp(int i) 152 { 153 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 154 (void *)(uintptr_t) i); 155 } 156 157 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 158 { 159 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 160 (void *)(uintptr_t) i); 161 } 162 163 int spapr_max_server_number(SpaprMachineState *spapr) 164 { 165 MachineState *ms = MACHINE(spapr); 166 167 assert(spapr->vsmt); 168 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 169 } 170 171 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 172 int smt_threads) 173 { 174 int i, ret = 0; 175 uint32_t servers_prop[smt_threads]; 176 uint32_t gservers_prop[smt_threads * 2]; 177 int index = spapr_get_vcpu_id(cpu); 178 179 if (cpu->compat_pvr) { 180 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 181 if (ret < 0) { 182 return ret; 183 } 184 } 185 186 /* Build interrupt servers and gservers properties */ 187 for (i = 0; i < smt_threads; i++) { 188 servers_prop[i] = cpu_to_be32(index + i); 189 /* Hack, direct the group queues back to cpu 0 */ 190 gservers_prop[i*2] = cpu_to_be32(index + i); 191 gservers_prop[i*2 + 1] = 0; 192 } 193 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 194 servers_prop, sizeof(servers_prop)); 195 if (ret < 0) { 196 return ret; 197 } 198 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 199 gservers_prop, sizeof(gservers_prop)); 200 201 return ret; 202 } 203 204 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 205 { 206 int index = spapr_get_vcpu_id(cpu); 207 uint32_t associativity[] = {cpu_to_be32(0x5), 208 cpu_to_be32(0x0), 209 cpu_to_be32(0x0), 210 cpu_to_be32(0x0), 211 cpu_to_be32(cpu->node_id), 212 cpu_to_be32(index)}; 213 214 /* Advertise NUMA via ibm,associativity */ 215 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 216 sizeof(associativity)); 217 } 218 219 static void spapr_dt_pa_features(SpaprMachineState *spapr, 220 PowerPCCPU *cpu, 221 void *fdt, int offset) 222 { 223 uint8_t pa_features_206[] = { 6, 0, 224 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 225 uint8_t pa_features_207[] = { 24, 0, 226 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 227 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 228 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 229 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 230 uint8_t pa_features_300[] = { 66, 0, 231 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 232 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 233 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 234 /* 6: DS207 */ 235 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 236 /* 16: Vector */ 237 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 238 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 239 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 240 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 241 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 242 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 243 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 244 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 245 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 246 /* 42: PM, 44: PC RA, 46: SC vec'd */ 247 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 248 /* 48: SIMD, 50: QP BFP, 52: String */ 249 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 250 /* 54: DecFP, 56: DecI, 58: SHA */ 251 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 252 /* 60: NM atomic, 62: RNG */ 253 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 254 }; 255 uint8_t *pa_features = NULL; 256 size_t pa_size; 257 258 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 259 pa_features = pa_features_206; 260 pa_size = sizeof(pa_features_206); 261 } 262 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 263 pa_features = pa_features_207; 264 pa_size = sizeof(pa_features_207); 265 } 266 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 267 pa_features = pa_features_300; 268 pa_size = sizeof(pa_features_300); 269 } 270 if (!pa_features) { 271 return; 272 } 273 274 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 275 /* 276 * Note: we keep CI large pages off by default because a 64K capable 277 * guest provisioned with large pages might otherwise try to map a qemu 278 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 279 * even if that qemu runs on a 4k host. 280 * We dd this bit back here if we are confident this is not an issue 281 */ 282 pa_features[3] |= 0x20; 283 } 284 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 285 pa_features[24] |= 0x80; /* Transactional memory support */ 286 } 287 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 288 /* Workaround for broken kernels that attempt (guest) radix 289 * mode when they can't handle it, if they see the radix bit set 290 * in pa-features. So hide it from them. */ 291 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 292 } 293 294 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 295 } 296 297 static hwaddr spapr_node0_size(MachineState *machine) 298 { 299 if (machine->numa_state->num_nodes) { 300 int i; 301 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 302 if (machine->numa_state->nodes[i].node_mem) { 303 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 304 machine->ram_size); 305 } 306 } 307 } 308 return machine->ram_size; 309 } 310 311 static void add_str(GString *s, const gchar *s1) 312 { 313 g_string_append_len(s, s1, strlen(s1) + 1); 314 } 315 316 static int spapr_dt_memory_node(void *fdt, int nodeid, hwaddr start, 317 hwaddr size) 318 { 319 uint32_t associativity[] = { 320 cpu_to_be32(0x4), /* length */ 321 cpu_to_be32(0x0), cpu_to_be32(0x0), 322 cpu_to_be32(0x0), cpu_to_be32(nodeid) 323 }; 324 char mem_name[32]; 325 uint64_t mem_reg_property[2]; 326 int off; 327 328 mem_reg_property[0] = cpu_to_be64(start); 329 mem_reg_property[1] = cpu_to_be64(size); 330 331 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 332 off = fdt_add_subnode(fdt, 0, mem_name); 333 _FDT(off); 334 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 335 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 336 sizeof(mem_reg_property)))); 337 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 338 sizeof(associativity)))); 339 return off; 340 } 341 342 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 343 { 344 MemoryDeviceInfoList *info; 345 346 for (info = list; info; info = info->next) { 347 MemoryDeviceInfo *value = info->value; 348 349 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 350 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 351 352 if (addr >= pcdimm_info->addr && 353 addr < (pcdimm_info->addr + pcdimm_info->size)) { 354 return pcdimm_info->node; 355 } 356 } 357 } 358 359 return -1; 360 } 361 362 struct sPAPRDrconfCellV2 { 363 uint32_t seq_lmbs; 364 uint64_t base_addr; 365 uint32_t drc_index; 366 uint32_t aa_index; 367 uint32_t flags; 368 } QEMU_PACKED; 369 370 typedef struct DrconfCellQueue { 371 struct sPAPRDrconfCellV2 cell; 372 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 373 } DrconfCellQueue; 374 375 static DrconfCellQueue * 376 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 377 uint32_t drc_index, uint32_t aa_index, 378 uint32_t flags) 379 { 380 DrconfCellQueue *elem; 381 382 elem = g_malloc0(sizeof(*elem)); 383 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 384 elem->cell.base_addr = cpu_to_be64(base_addr); 385 elem->cell.drc_index = cpu_to_be32(drc_index); 386 elem->cell.aa_index = cpu_to_be32(aa_index); 387 elem->cell.flags = cpu_to_be32(flags); 388 389 return elem; 390 } 391 392 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 393 int offset, MemoryDeviceInfoList *dimms) 394 { 395 MachineState *machine = MACHINE(spapr); 396 uint8_t *int_buf, *cur_index; 397 int ret; 398 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 399 uint64_t addr, cur_addr, size; 400 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 401 uint64_t mem_end = machine->device_memory->base + 402 memory_region_size(&machine->device_memory->mr); 403 uint32_t node, buf_len, nr_entries = 0; 404 SpaprDrc *drc; 405 DrconfCellQueue *elem, *next; 406 MemoryDeviceInfoList *info; 407 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 408 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 409 410 /* Entry to cover RAM and the gap area */ 411 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 412 SPAPR_LMB_FLAGS_RESERVED | 413 SPAPR_LMB_FLAGS_DRC_INVALID); 414 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 415 nr_entries++; 416 417 cur_addr = machine->device_memory->base; 418 for (info = dimms; info; info = info->next) { 419 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 420 421 addr = di->addr; 422 size = di->size; 423 node = di->node; 424 425 /* 426 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 427 * area is marked hotpluggable in the next iteration for the bigger 428 * chunk including the NVDIMM occupied area. 429 */ 430 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 431 continue; 432 433 /* Entry for hot-pluggable area */ 434 if (cur_addr < addr) { 435 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 436 g_assert(drc); 437 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 438 cur_addr, spapr_drc_index(drc), -1, 0); 439 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 440 nr_entries++; 441 } 442 443 /* Entry for DIMM */ 444 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 445 g_assert(drc); 446 elem = spapr_get_drconf_cell(size / lmb_size, addr, 447 spapr_drc_index(drc), node, 448 SPAPR_LMB_FLAGS_ASSIGNED); 449 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 450 nr_entries++; 451 cur_addr = addr + size; 452 } 453 454 /* Entry for remaining hotpluggable area */ 455 if (cur_addr < mem_end) { 456 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 457 g_assert(drc); 458 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 459 cur_addr, spapr_drc_index(drc), -1, 0); 460 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 461 nr_entries++; 462 } 463 464 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 465 int_buf = cur_index = g_malloc0(buf_len); 466 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 467 cur_index += sizeof(nr_entries); 468 469 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 470 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 471 cur_index += sizeof(elem->cell); 472 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 473 g_free(elem); 474 } 475 476 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 477 g_free(int_buf); 478 if (ret < 0) { 479 return -1; 480 } 481 return 0; 482 } 483 484 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 485 int offset, MemoryDeviceInfoList *dimms) 486 { 487 MachineState *machine = MACHINE(spapr); 488 int i, ret; 489 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 490 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 491 uint32_t nr_lmbs = (machine->device_memory->base + 492 memory_region_size(&machine->device_memory->mr)) / 493 lmb_size; 494 uint32_t *int_buf, *cur_index, buf_len; 495 496 /* 497 * Allocate enough buffer size to fit in ibm,dynamic-memory 498 */ 499 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 500 cur_index = int_buf = g_malloc0(buf_len); 501 int_buf[0] = cpu_to_be32(nr_lmbs); 502 cur_index++; 503 for (i = 0; i < nr_lmbs; i++) { 504 uint64_t addr = i * lmb_size; 505 uint32_t *dynamic_memory = cur_index; 506 507 if (i >= device_lmb_start) { 508 SpaprDrc *drc; 509 510 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 511 g_assert(drc); 512 513 dynamic_memory[0] = cpu_to_be32(addr >> 32); 514 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 515 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 516 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 517 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 518 if (memory_region_present(get_system_memory(), addr)) { 519 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 520 } else { 521 dynamic_memory[5] = cpu_to_be32(0); 522 } 523 } else { 524 /* 525 * LMB information for RMA, boot time RAM and gap b/n RAM and 526 * device memory region -- all these are marked as reserved 527 * and as having no valid DRC. 528 */ 529 dynamic_memory[0] = cpu_to_be32(addr >> 32); 530 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 531 dynamic_memory[2] = cpu_to_be32(0); 532 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 533 dynamic_memory[4] = cpu_to_be32(-1); 534 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 535 SPAPR_LMB_FLAGS_DRC_INVALID); 536 } 537 538 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 539 } 540 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 541 g_free(int_buf); 542 if (ret < 0) { 543 return -1; 544 } 545 return 0; 546 } 547 548 /* 549 * Adds ibm,dynamic-reconfiguration-memory node. 550 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 551 * of this device tree node. 552 */ 553 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 554 void *fdt) 555 { 556 MachineState *machine = MACHINE(spapr); 557 int nb_numa_nodes = machine->numa_state->num_nodes; 558 int ret, i, offset; 559 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 560 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 561 uint32_t *int_buf, *cur_index, buf_len; 562 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 563 MemoryDeviceInfoList *dimms = NULL; 564 565 /* 566 * Don't create the node if there is no device memory 567 */ 568 if (machine->ram_size == machine->maxram_size) { 569 return 0; 570 } 571 572 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 573 574 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 575 sizeof(prop_lmb_size)); 576 if (ret < 0) { 577 return ret; 578 } 579 580 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 581 if (ret < 0) { 582 return ret; 583 } 584 585 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 586 if (ret < 0) { 587 return ret; 588 } 589 590 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 591 dimms = qmp_memory_device_list(); 592 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 593 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 594 } else { 595 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 596 } 597 qapi_free_MemoryDeviceInfoList(dimms); 598 599 if (ret < 0) { 600 return ret; 601 } 602 603 /* ibm,associativity-lookup-arrays */ 604 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 605 cur_index = int_buf = g_malloc0(buf_len); 606 int_buf[0] = cpu_to_be32(nr_nodes); 607 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 608 cur_index += 2; 609 for (i = 0; i < nr_nodes; i++) { 610 uint32_t associativity[] = { 611 cpu_to_be32(0x0), 612 cpu_to_be32(0x0), 613 cpu_to_be32(0x0), 614 cpu_to_be32(i) 615 }; 616 memcpy(cur_index, associativity, sizeof(associativity)); 617 cur_index += 4; 618 } 619 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 620 (cur_index - int_buf) * sizeof(uint32_t)); 621 g_free(int_buf); 622 623 return ret; 624 } 625 626 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 627 { 628 MachineState *machine = MACHINE(spapr); 629 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 630 hwaddr mem_start, node_size; 631 int i, nb_nodes = machine->numa_state->num_nodes; 632 NodeInfo *nodes = machine->numa_state->nodes; 633 634 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 635 if (!nodes[i].node_mem) { 636 continue; 637 } 638 if (mem_start >= machine->ram_size) { 639 node_size = 0; 640 } else { 641 node_size = nodes[i].node_mem; 642 if (node_size > machine->ram_size - mem_start) { 643 node_size = machine->ram_size - mem_start; 644 } 645 } 646 if (!mem_start) { 647 /* spapr_machine_init() checks for rma_size <= node0_size 648 * already */ 649 spapr_dt_memory_node(fdt, i, 0, spapr->rma_size); 650 mem_start += spapr->rma_size; 651 node_size -= spapr->rma_size; 652 } 653 for ( ; node_size; ) { 654 hwaddr sizetmp = pow2floor(node_size); 655 656 /* mem_start != 0 here */ 657 if (ctzl(mem_start) < ctzl(sizetmp)) { 658 sizetmp = 1ULL << ctzl(mem_start); 659 } 660 661 spapr_dt_memory_node(fdt, i, mem_start, sizetmp); 662 node_size -= sizetmp; 663 mem_start += sizetmp; 664 } 665 } 666 667 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 668 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 669 int ret; 670 671 g_assert(smc->dr_lmb_enabled); 672 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 673 if (ret) { 674 return ret; 675 } 676 } 677 678 return 0; 679 } 680 681 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 682 SpaprMachineState *spapr) 683 { 684 MachineState *ms = MACHINE(spapr); 685 PowerPCCPU *cpu = POWERPC_CPU(cs); 686 CPUPPCState *env = &cpu->env; 687 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 688 int index = spapr_get_vcpu_id(cpu); 689 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 690 0xffffffff, 0xffffffff}; 691 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 692 : SPAPR_TIMEBASE_FREQ; 693 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 694 uint32_t page_sizes_prop[64]; 695 size_t page_sizes_prop_size; 696 unsigned int smp_threads = ms->smp.threads; 697 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 698 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 699 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 700 SpaprDrc *drc; 701 int drc_index; 702 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 703 int i; 704 705 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 706 if (drc) { 707 drc_index = spapr_drc_index(drc); 708 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 709 } 710 711 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 712 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 713 714 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 715 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 716 env->dcache_line_size))); 717 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 718 env->dcache_line_size))); 719 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 720 env->icache_line_size))); 721 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 722 env->icache_line_size))); 723 724 if (pcc->l1_dcache_size) { 725 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 726 pcc->l1_dcache_size))); 727 } else { 728 warn_report("Unknown L1 dcache size for cpu"); 729 } 730 if (pcc->l1_icache_size) { 731 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 732 pcc->l1_icache_size))); 733 } else { 734 warn_report("Unknown L1 icache size for cpu"); 735 } 736 737 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 738 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 739 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 740 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 741 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 742 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 743 744 if (env->spr_cb[SPR_PURR].oea_read) { 745 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 746 } 747 if (env->spr_cb[SPR_SPURR].oea_read) { 748 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 749 } 750 751 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 752 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 753 segs, sizeof(segs)))); 754 } 755 756 /* Advertise VSX (vector extensions) if available 757 * 1 == VMX / Altivec available 758 * 2 == VSX available 759 * 760 * Only CPUs for which we create core types in spapr_cpu_core.c 761 * are possible, and all of those have VMX */ 762 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 763 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 764 } else { 765 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 766 } 767 768 /* Advertise DFP (Decimal Floating Point) if available 769 * 0 / no property == no DFP 770 * 1 == DFP available */ 771 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 772 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 773 } 774 775 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 776 sizeof(page_sizes_prop)); 777 if (page_sizes_prop_size) { 778 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 779 page_sizes_prop, page_sizes_prop_size))); 780 } 781 782 spapr_dt_pa_features(spapr, cpu, fdt, offset); 783 784 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 785 cs->cpu_index / vcpus_per_socket))); 786 787 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 788 pft_size_prop, sizeof(pft_size_prop)))); 789 790 if (ms->numa_state->num_nodes > 1) { 791 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 792 } 793 794 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 795 796 if (pcc->radix_page_info) { 797 for (i = 0; i < pcc->radix_page_info->count; i++) { 798 radix_AP_encodings[i] = 799 cpu_to_be32(pcc->radix_page_info->entries[i]); 800 } 801 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 802 radix_AP_encodings, 803 pcc->radix_page_info->count * 804 sizeof(radix_AP_encodings[0])))); 805 } 806 807 /* 808 * We set this property to let the guest know that it can use the large 809 * decrementer and its width in bits. 810 */ 811 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 812 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 813 pcc->lrg_decr_bits))); 814 } 815 816 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 817 { 818 CPUState **rev; 819 CPUState *cs; 820 int n_cpus; 821 int cpus_offset; 822 char *nodename; 823 int i; 824 825 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 826 _FDT(cpus_offset); 827 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 828 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 829 830 /* 831 * We walk the CPUs in reverse order to ensure that CPU DT nodes 832 * created by fdt_add_subnode() end up in the right order in FDT 833 * for the guest kernel the enumerate the CPUs correctly. 834 * 835 * The CPU list cannot be traversed in reverse order, so we need 836 * to do extra work. 837 */ 838 n_cpus = 0; 839 rev = NULL; 840 CPU_FOREACH(cs) { 841 rev = g_renew(CPUState *, rev, n_cpus + 1); 842 rev[n_cpus++] = cs; 843 } 844 845 for (i = n_cpus - 1; i >= 0; i--) { 846 CPUState *cs = rev[i]; 847 PowerPCCPU *cpu = POWERPC_CPU(cs); 848 int index = spapr_get_vcpu_id(cpu); 849 DeviceClass *dc = DEVICE_GET_CLASS(cs); 850 int offset; 851 852 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 853 continue; 854 } 855 856 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 857 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 858 g_free(nodename); 859 _FDT(offset); 860 spapr_dt_cpu(cs, fdt, offset, spapr); 861 } 862 863 g_free(rev); 864 } 865 866 static int spapr_dt_rng(void *fdt) 867 { 868 int node; 869 int ret; 870 871 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 872 if (node <= 0) { 873 return -1; 874 } 875 ret = fdt_setprop_string(fdt, node, "device_type", 876 "ibm,platform-facilities"); 877 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 878 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 879 880 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 881 if (node <= 0) { 882 return -1; 883 } 884 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 885 886 return ret ? -1 : 0; 887 } 888 889 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 890 { 891 MachineState *ms = MACHINE(spapr); 892 int rtas; 893 GString *hypertas = g_string_sized_new(256); 894 GString *qemu_hypertas = g_string_sized_new(256); 895 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 896 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 897 memory_region_size(&MACHINE(spapr)->device_memory->mr); 898 uint32_t lrdr_capacity[] = { 899 cpu_to_be32(max_device_addr >> 32), 900 cpu_to_be32(max_device_addr & 0xffffffff), 901 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 902 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 903 }; 904 uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0); 905 uint32_t maxdomains[] = { 906 cpu_to_be32(4), 907 maxdomain, 908 maxdomain, 909 maxdomain, 910 cpu_to_be32(spapr->gpu_numa_id), 911 }; 912 913 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 914 915 /* hypertas */ 916 add_str(hypertas, "hcall-pft"); 917 add_str(hypertas, "hcall-term"); 918 add_str(hypertas, "hcall-dabr"); 919 add_str(hypertas, "hcall-interrupt"); 920 add_str(hypertas, "hcall-tce"); 921 add_str(hypertas, "hcall-vio"); 922 add_str(hypertas, "hcall-splpar"); 923 add_str(hypertas, "hcall-join"); 924 add_str(hypertas, "hcall-bulk"); 925 add_str(hypertas, "hcall-set-mode"); 926 add_str(hypertas, "hcall-sprg0"); 927 add_str(hypertas, "hcall-copy"); 928 add_str(hypertas, "hcall-debug"); 929 add_str(hypertas, "hcall-vphn"); 930 add_str(qemu_hypertas, "hcall-memop1"); 931 932 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 933 add_str(hypertas, "hcall-multi-tce"); 934 } 935 936 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 937 add_str(hypertas, "hcall-hpt-resize"); 938 } 939 940 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 941 hypertas->str, hypertas->len)); 942 g_string_free(hypertas, TRUE); 943 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 944 qemu_hypertas->str, qemu_hypertas->len)); 945 g_string_free(qemu_hypertas, TRUE); 946 947 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 948 refpoints, sizeof(refpoints))); 949 950 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 951 maxdomains, sizeof(maxdomains))); 952 953 /* 954 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 955 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 956 * 957 * The system reset requirements are driven by existing Linux and PowerVM 958 * implementation which (contrary to PAPR) saves r3 in the error log 959 * structure like machine check, so Linux expects to find the saved r3 960 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 961 * does not look at the error value). 962 * 963 * System reset interrupts are not subject to interlock like machine 964 * check, so this memory area could be corrupted if the sreset is 965 * interrupted by a machine check (or vice versa) if it was shared. To 966 * prevent this, system reset uses per-CPU areas for the sreset save 967 * area. A system reset that interrupts a system reset handler could 968 * still overwrite this area, but Linux doesn't try to recover in that 969 * case anyway. 970 * 971 * The extra 8 bytes is required because Linux's FWNMI error log check 972 * is off-by-one. 973 */ 974 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX + 975 ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t))); 976 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 977 RTAS_ERROR_LOG_MAX)); 978 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 979 RTAS_EVENT_SCAN_RATE)); 980 981 g_assert(msi_nonbroken); 982 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 983 984 /* 985 * According to PAPR, rtas ibm,os-term does not guarantee a return 986 * back to the guest cpu. 987 * 988 * While an additional ibm,extended-os-term property indicates 989 * that rtas call return will always occur. Set this property. 990 */ 991 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 992 993 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 994 lrdr_capacity, sizeof(lrdr_capacity))); 995 996 spapr_dt_rtas_tokens(fdt, rtas); 997 } 998 999 /* 1000 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 1001 * and the XIVE features that the guest may request and thus the valid 1002 * values for bytes 23..26 of option vector 5: 1003 */ 1004 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 1005 int chosen) 1006 { 1007 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1008 1009 char val[2 * 4] = { 1010 23, 0x00, /* XICS / XIVE mode */ 1011 24, 0x00, /* Hash/Radix, filled in below. */ 1012 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1013 26, 0x40, /* Radix options: GTSE == yes. */ 1014 }; 1015 1016 if (spapr->irq->xics && spapr->irq->xive) { 1017 val[1] = SPAPR_OV5_XIVE_BOTH; 1018 } else if (spapr->irq->xive) { 1019 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1020 } else { 1021 assert(spapr->irq->xics); 1022 val[1] = SPAPR_OV5_XIVE_LEGACY; 1023 } 1024 1025 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1026 first_ppc_cpu->compat_pvr)) { 1027 /* 1028 * If we're in a pre POWER9 compat mode then the guest should 1029 * do hash and use the legacy interrupt mode 1030 */ 1031 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1032 val[3] = 0x00; /* Hash */ 1033 } else if (kvm_enabled()) { 1034 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1035 val[3] = 0x80; /* OV5_MMU_BOTH */ 1036 } else if (kvmppc_has_cap_mmu_radix()) { 1037 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1038 } else { 1039 val[3] = 0x00; /* Hash */ 1040 } 1041 } else { 1042 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1043 val[3] = 0xC0; 1044 } 1045 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1046 val, sizeof(val))); 1047 } 1048 1049 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1050 { 1051 MachineState *machine = MACHINE(spapr); 1052 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1053 int chosen; 1054 1055 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1056 1057 if (reset) { 1058 const char *boot_device = machine->boot_order; 1059 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1060 size_t cb = 0; 1061 char *bootlist = get_boot_devices_list(&cb); 1062 1063 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1064 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1065 machine->kernel_cmdline)); 1066 } 1067 1068 if (spapr->initrd_size) { 1069 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1070 spapr->initrd_base)); 1071 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1072 spapr->initrd_base + spapr->initrd_size)); 1073 } 1074 1075 if (spapr->kernel_size) { 1076 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1077 cpu_to_be64(spapr->kernel_size) }; 1078 1079 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1080 &kprop, sizeof(kprop))); 1081 if (spapr->kernel_le) { 1082 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1083 } 1084 } 1085 if (boot_menu) { 1086 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1087 } 1088 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1089 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1090 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1091 1092 if (cb && bootlist) { 1093 int i; 1094 1095 for (i = 0; i < cb; i++) { 1096 if (bootlist[i] == '\n') { 1097 bootlist[i] = ' '; 1098 } 1099 } 1100 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1101 } 1102 1103 if (boot_device && strlen(boot_device)) { 1104 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1105 } 1106 1107 if (!spapr->has_graphics && stdout_path) { 1108 /* 1109 * "linux,stdout-path" and "stdout" properties are 1110 * deprecated by linux kernel. New platforms should only 1111 * use the "stdout-path" property. Set the new property 1112 * and continue using older property to remain compatible 1113 * with the existing firmware. 1114 */ 1115 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1116 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1117 } 1118 1119 /* 1120 * We can deal with BAR reallocation just fine, advertise it 1121 * to the guest 1122 */ 1123 if (smc->linux_pci_probe) { 1124 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1125 } 1126 1127 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1128 1129 g_free(stdout_path); 1130 g_free(bootlist); 1131 } 1132 1133 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1134 } 1135 1136 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1137 { 1138 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1139 * KVM to work under pHyp with some guest co-operation */ 1140 int hypervisor; 1141 uint8_t hypercall[16]; 1142 1143 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1144 /* indicate KVM hypercall interface */ 1145 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1146 if (kvmppc_has_cap_fixup_hcalls()) { 1147 /* 1148 * Older KVM versions with older guest kernels were broken 1149 * with the magic page, don't allow the guest to map it. 1150 */ 1151 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1152 sizeof(hypercall))) { 1153 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1154 hypercall, sizeof(hypercall))); 1155 } 1156 } 1157 } 1158 1159 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1160 { 1161 MachineState *machine = MACHINE(spapr); 1162 MachineClass *mc = MACHINE_GET_CLASS(machine); 1163 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1164 int ret; 1165 void *fdt; 1166 SpaprPhbState *phb; 1167 char *buf; 1168 1169 fdt = g_malloc0(space); 1170 _FDT((fdt_create_empty_tree(fdt, space))); 1171 1172 /* Root node */ 1173 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1174 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1175 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1176 1177 /* Guest UUID & Name*/ 1178 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1179 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1180 if (qemu_uuid_set) { 1181 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1182 } 1183 g_free(buf); 1184 1185 if (qemu_get_vm_name()) { 1186 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1187 qemu_get_vm_name())); 1188 } 1189 1190 /* Host Model & Serial Number */ 1191 if (spapr->host_model) { 1192 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1193 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1194 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1195 g_free(buf); 1196 } 1197 1198 if (spapr->host_serial) { 1199 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1200 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1201 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1202 g_free(buf); 1203 } 1204 1205 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1206 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1207 1208 /* /interrupt controller */ 1209 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1210 1211 ret = spapr_dt_memory(spapr, fdt); 1212 if (ret < 0) { 1213 error_report("couldn't setup memory nodes in fdt"); 1214 exit(1); 1215 } 1216 1217 /* /vdevice */ 1218 spapr_dt_vdevice(spapr->vio_bus, fdt); 1219 1220 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1221 ret = spapr_dt_rng(fdt); 1222 if (ret < 0) { 1223 error_report("could not set up rng device in the fdt"); 1224 exit(1); 1225 } 1226 } 1227 1228 QLIST_FOREACH(phb, &spapr->phbs, list) { 1229 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1230 if (ret < 0) { 1231 error_report("couldn't setup PCI devices in fdt"); 1232 exit(1); 1233 } 1234 } 1235 1236 spapr_dt_cpus(fdt, spapr); 1237 1238 if (smc->dr_lmb_enabled) { 1239 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1240 } 1241 1242 if (mc->has_hotpluggable_cpus) { 1243 int offset = fdt_path_offset(fdt, "/cpus"); 1244 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1245 if (ret < 0) { 1246 error_report("Couldn't set up CPU DR device tree properties"); 1247 exit(1); 1248 } 1249 } 1250 1251 /* /event-sources */ 1252 spapr_dt_events(spapr, fdt); 1253 1254 /* /rtas */ 1255 spapr_dt_rtas(spapr, fdt); 1256 1257 /* /chosen */ 1258 spapr_dt_chosen(spapr, fdt, reset); 1259 1260 /* /hypervisor */ 1261 if (kvm_enabled()) { 1262 spapr_dt_hypervisor(spapr, fdt); 1263 } 1264 1265 /* Build memory reserve map */ 1266 if (reset) { 1267 if (spapr->kernel_size) { 1268 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1269 spapr->kernel_size))); 1270 } 1271 if (spapr->initrd_size) { 1272 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1273 spapr->initrd_size))); 1274 } 1275 } 1276 1277 if (smc->dr_phb_enabled) { 1278 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); 1279 if (ret < 0) { 1280 error_report("Couldn't set up PHB DR device tree properties"); 1281 exit(1); 1282 } 1283 } 1284 1285 /* NVDIMM devices */ 1286 if (mc->nvdimm_supported) { 1287 spapr_dt_persistent_memory(fdt); 1288 } 1289 1290 return fdt; 1291 } 1292 1293 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1294 { 1295 SpaprMachineState *spapr = opaque; 1296 1297 return (addr & 0x0fffffff) + spapr->kernel_addr; 1298 } 1299 1300 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1301 PowerPCCPU *cpu) 1302 { 1303 CPUPPCState *env = &cpu->env; 1304 1305 /* The TCG path should also be holding the BQL at this point */ 1306 g_assert(qemu_mutex_iothread_locked()); 1307 1308 if (msr_pr) { 1309 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1310 env->gpr[3] = H_PRIVILEGE; 1311 } else { 1312 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1313 } 1314 } 1315 1316 struct LPCRSyncState { 1317 target_ulong value; 1318 target_ulong mask; 1319 }; 1320 1321 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1322 { 1323 struct LPCRSyncState *s = arg.host_ptr; 1324 PowerPCCPU *cpu = POWERPC_CPU(cs); 1325 CPUPPCState *env = &cpu->env; 1326 target_ulong lpcr; 1327 1328 cpu_synchronize_state(cs); 1329 lpcr = env->spr[SPR_LPCR]; 1330 lpcr &= ~s->mask; 1331 lpcr |= s->value; 1332 ppc_store_lpcr(cpu, lpcr); 1333 } 1334 1335 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1336 { 1337 CPUState *cs; 1338 struct LPCRSyncState s = { 1339 .value = value, 1340 .mask = mask 1341 }; 1342 CPU_FOREACH(cs) { 1343 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1344 } 1345 } 1346 1347 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1348 { 1349 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1350 1351 /* Copy PATE1:GR into PATE0:HR */ 1352 entry->dw0 = spapr->patb_entry & PATE0_HR; 1353 entry->dw1 = spapr->patb_entry; 1354 } 1355 1356 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1357 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1358 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1359 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1360 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1361 1362 /* 1363 * Get the fd to access the kernel htab, re-opening it if necessary 1364 */ 1365 static int get_htab_fd(SpaprMachineState *spapr) 1366 { 1367 Error *local_err = NULL; 1368 1369 if (spapr->htab_fd >= 0) { 1370 return spapr->htab_fd; 1371 } 1372 1373 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1374 if (spapr->htab_fd < 0) { 1375 error_report_err(local_err); 1376 } 1377 1378 return spapr->htab_fd; 1379 } 1380 1381 void close_htab_fd(SpaprMachineState *spapr) 1382 { 1383 if (spapr->htab_fd >= 0) { 1384 close(spapr->htab_fd); 1385 } 1386 spapr->htab_fd = -1; 1387 } 1388 1389 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1390 { 1391 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1392 1393 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1394 } 1395 1396 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1397 { 1398 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1399 1400 assert(kvm_enabled()); 1401 1402 if (!spapr->htab) { 1403 return 0; 1404 } 1405 1406 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1407 } 1408 1409 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1410 hwaddr ptex, int n) 1411 { 1412 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1413 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1414 1415 if (!spapr->htab) { 1416 /* 1417 * HTAB is controlled by KVM. Fetch into temporary buffer 1418 */ 1419 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1420 kvmppc_read_hptes(hptes, ptex, n); 1421 return hptes; 1422 } 1423 1424 /* 1425 * HTAB is controlled by QEMU. Just point to the internally 1426 * accessible PTEG. 1427 */ 1428 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1429 } 1430 1431 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1432 const ppc_hash_pte64_t *hptes, 1433 hwaddr ptex, int n) 1434 { 1435 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1436 1437 if (!spapr->htab) { 1438 g_free((void *)hptes); 1439 } 1440 1441 /* Nothing to do for qemu managed HPT */ 1442 } 1443 1444 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1445 uint64_t pte0, uint64_t pte1) 1446 { 1447 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1448 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1449 1450 if (!spapr->htab) { 1451 kvmppc_write_hpte(ptex, pte0, pte1); 1452 } else { 1453 if (pte0 & HPTE64_V_VALID) { 1454 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1455 /* 1456 * When setting valid, we write PTE1 first. This ensures 1457 * proper synchronization with the reading code in 1458 * ppc_hash64_pteg_search() 1459 */ 1460 smp_wmb(); 1461 stq_p(spapr->htab + offset, pte0); 1462 } else { 1463 stq_p(spapr->htab + offset, pte0); 1464 /* 1465 * When clearing it we set PTE0 first. This ensures proper 1466 * synchronization with the reading code in 1467 * ppc_hash64_pteg_search() 1468 */ 1469 smp_wmb(); 1470 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1471 } 1472 } 1473 } 1474 1475 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1476 uint64_t pte1) 1477 { 1478 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1479 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1480 1481 if (!spapr->htab) { 1482 /* There should always be a hash table when this is called */ 1483 error_report("spapr_hpte_set_c called with no hash table !"); 1484 return; 1485 } 1486 1487 /* The HW performs a non-atomic byte update */ 1488 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1489 } 1490 1491 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1492 uint64_t pte1) 1493 { 1494 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1495 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1496 1497 if (!spapr->htab) { 1498 /* There should always be a hash table when this is called */ 1499 error_report("spapr_hpte_set_r called with no hash table !"); 1500 return; 1501 } 1502 1503 /* The HW performs a non-atomic byte update */ 1504 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1505 } 1506 1507 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1508 { 1509 int shift; 1510 1511 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1512 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1513 * that's much more than is needed for Linux guests */ 1514 shift = ctz64(pow2ceil(ramsize)) - 7; 1515 shift = MAX(shift, 18); /* Minimum architected size */ 1516 shift = MIN(shift, 46); /* Maximum architected size */ 1517 return shift; 1518 } 1519 1520 void spapr_free_hpt(SpaprMachineState *spapr) 1521 { 1522 g_free(spapr->htab); 1523 spapr->htab = NULL; 1524 spapr->htab_shift = 0; 1525 close_htab_fd(spapr); 1526 } 1527 1528 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 1529 Error **errp) 1530 { 1531 long rc; 1532 1533 /* Clean up any HPT info from a previous boot */ 1534 spapr_free_hpt(spapr); 1535 1536 rc = kvmppc_reset_htab(shift); 1537 if (rc < 0) { 1538 /* kernel-side HPT needed, but couldn't allocate one */ 1539 error_setg_errno(errp, errno, 1540 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1541 shift); 1542 /* This is almost certainly fatal, but if the caller really 1543 * wants to carry on with shift == 0, it's welcome to try */ 1544 } else if (rc > 0) { 1545 /* kernel-side HPT allocated */ 1546 if (rc != shift) { 1547 error_setg(errp, 1548 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1549 shift, rc); 1550 } 1551 1552 spapr->htab_shift = shift; 1553 spapr->htab = NULL; 1554 } else { 1555 /* kernel-side HPT not needed, allocate in userspace instead */ 1556 size_t size = 1ULL << shift; 1557 int i; 1558 1559 spapr->htab = qemu_memalign(size, size); 1560 if (!spapr->htab) { 1561 error_setg_errno(errp, errno, 1562 "Could not allocate HPT of order %d", shift); 1563 return; 1564 } 1565 1566 memset(spapr->htab, 0, size); 1567 spapr->htab_shift = shift; 1568 1569 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1570 DIRTY_HPTE(HPTE(spapr->htab, i)); 1571 } 1572 } 1573 /* We're setting up a hash table, so that means we're not radix */ 1574 spapr->patb_entry = 0; 1575 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1576 } 1577 1578 void spapr_setup_hpt(SpaprMachineState *spapr) 1579 { 1580 int hpt_shift; 1581 1582 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1583 || (spapr->cas_reboot 1584 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1585 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1586 } else { 1587 uint64_t current_ram_size; 1588 1589 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1590 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1591 } 1592 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1593 1594 if (kvm_enabled()) { 1595 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1596 1597 /* Check our RMA fits in the possible VRMA */ 1598 if (vrma_limit < spapr->rma_size) { 1599 error_report("Unable to create %" HWADDR_PRIu 1600 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1601 spapr->rma_size / MiB, vrma_limit / MiB); 1602 exit(EXIT_FAILURE); 1603 } 1604 } 1605 } 1606 1607 static int spapr_reset_drcs(Object *child, void *opaque) 1608 { 1609 SpaprDrc *drc = 1610 (SpaprDrc *) object_dynamic_cast(child, 1611 TYPE_SPAPR_DR_CONNECTOR); 1612 1613 if (drc) { 1614 spapr_drc_reset(drc); 1615 } 1616 1617 return 0; 1618 } 1619 1620 static void spapr_machine_reset(MachineState *machine) 1621 { 1622 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1623 PowerPCCPU *first_ppc_cpu; 1624 hwaddr fdt_addr; 1625 void *fdt; 1626 int rc; 1627 1628 kvmppc_svm_off(&error_fatal); 1629 spapr_caps_apply(spapr); 1630 1631 first_ppc_cpu = POWERPC_CPU(first_cpu); 1632 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1633 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1634 spapr->max_compat_pvr)) { 1635 /* 1636 * If using KVM with radix mode available, VCPUs can be started 1637 * without a HPT because KVM will start them in radix mode. 1638 * Set the GR bit in PATE so that we know there is no HPT. 1639 */ 1640 spapr->patb_entry = PATE1_GR; 1641 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1642 } else { 1643 spapr_setup_hpt(spapr); 1644 } 1645 1646 qemu_devices_reset(); 1647 1648 /* 1649 * If this reset wasn't generated by CAS, we should reset our 1650 * negotiated options and start from scratch 1651 */ 1652 if (!spapr->cas_reboot) { 1653 spapr_ovec_cleanup(spapr->ov5_cas); 1654 spapr->ov5_cas = spapr_ovec_new(); 1655 1656 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1657 } 1658 1659 /* 1660 * This is fixing some of the default configuration of the XIVE 1661 * devices. To be called after the reset of the machine devices. 1662 */ 1663 spapr_irq_reset(spapr, &error_fatal); 1664 1665 /* 1666 * There is no CAS under qtest. Simulate one to please the code that 1667 * depends on spapr->ov5_cas. This is especially needed to test device 1668 * unplug, so we do that before resetting the DRCs. 1669 */ 1670 if (qtest_enabled()) { 1671 spapr_ovec_cleanup(spapr->ov5_cas); 1672 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1673 } 1674 1675 /* DRC reset may cause a device to be unplugged. This will cause troubles 1676 * if this device is used by another device (eg, a running vhost backend 1677 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1678 * situations, we reset DRCs after all devices have been reset. 1679 */ 1680 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1681 1682 spapr_clear_pending_events(spapr); 1683 1684 /* 1685 * We place the device tree and RTAS just below either the top of the RMA, 1686 * or just below 2GB, whichever is lower, so that it can be 1687 * processed with 32-bit real mode code if necessary 1688 */ 1689 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1690 1691 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1692 1693 rc = fdt_pack(fdt); 1694 1695 /* Should only fail if we've built a corrupted tree */ 1696 assert(rc == 0); 1697 1698 /* Load the fdt */ 1699 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1700 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1701 g_free(spapr->fdt_blob); 1702 spapr->fdt_size = fdt_totalsize(fdt); 1703 spapr->fdt_initial_size = spapr->fdt_size; 1704 spapr->fdt_blob = fdt; 1705 1706 /* Set up the entry state */ 1707 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); 1708 first_ppc_cpu->env.gpr[5] = 0; 1709 1710 spapr->cas_reboot = false; 1711 1712 spapr->fwnmi_system_reset_addr = -1; 1713 spapr->fwnmi_machine_check_addr = -1; 1714 spapr->fwnmi_machine_check_interlock = -1; 1715 1716 /* Signal all vCPUs waiting on this condition */ 1717 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1718 1719 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1720 } 1721 1722 static void spapr_create_nvram(SpaprMachineState *spapr) 1723 { 1724 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1725 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1726 1727 if (dinfo) { 1728 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1729 &error_fatal); 1730 } 1731 1732 qdev_init_nofail(dev); 1733 1734 spapr->nvram = (struct SpaprNvram *)dev; 1735 } 1736 1737 static void spapr_rtc_create(SpaprMachineState *spapr) 1738 { 1739 object_initialize_child(OBJECT(spapr), "rtc", 1740 &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1741 &error_fatal, NULL); 1742 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1743 &error_fatal); 1744 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1745 "date", &error_fatal); 1746 } 1747 1748 /* Returns whether we want to use VGA or not */ 1749 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1750 { 1751 switch (vga_interface_type) { 1752 case VGA_NONE: 1753 return false; 1754 case VGA_DEVICE: 1755 return true; 1756 case VGA_STD: 1757 case VGA_VIRTIO: 1758 case VGA_CIRRUS: 1759 return pci_vga_init(pci_bus) != NULL; 1760 default: 1761 error_setg(errp, 1762 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1763 return false; 1764 } 1765 } 1766 1767 static int spapr_pre_load(void *opaque) 1768 { 1769 int rc; 1770 1771 rc = spapr_caps_pre_load(opaque); 1772 if (rc) { 1773 return rc; 1774 } 1775 1776 return 0; 1777 } 1778 1779 static int spapr_post_load(void *opaque, int version_id) 1780 { 1781 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1782 int err = 0; 1783 1784 err = spapr_caps_post_migration(spapr); 1785 if (err) { 1786 return err; 1787 } 1788 1789 /* 1790 * In earlier versions, there was no separate qdev for the PAPR 1791 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1792 * So when migrating from those versions, poke the incoming offset 1793 * value into the RTC device 1794 */ 1795 if (version_id < 3) { 1796 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1797 if (err) { 1798 return err; 1799 } 1800 } 1801 1802 if (kvm_enabled() && spapr->patb_entry) { 1803 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1804 bool radix = !!(spapr->patb_entry & PATE1_GR); 1805 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1806 1807 /* 1808 * Update LPCR:HR and UPRT as they may not be set properly in 1809 * the stream 1810 */ 1811 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1812 LPCR_HR | LPCR_UPRT); 1813 1814 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1815 if (err) { 1816 error_report("Process table config unsupported by the host"); 1817 return -EINVAL; 1818 } 1819 } 1820 1821 err = spapr_irq_post_load(spapr, version_id); 1822 if (err) { 1823 return err; 1824 } 1825 1826 return err; 1827 } 1828 1829 static int spapr_pre_save(void *opaque) 1830 { 1831 int rc; 1832 1833 rc = spapr_caps_pre_save(opaque); 1834 if (rc) { 1835 return rc; 1836 } 1837 1838 return 0; 1839 } 1840 1841 static bool version_before_3(void *opaque, int version_id) 1842 { 1843 return version_id < 3; 1844 } 1845 1846 static bool spapr_pending_events_needed(void *opaque) 1847 { 1848 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1849 return !QTAILQ_EMPTY(&spapr->pending_events); 1850 } 1851 1852 static const VMStateDescription vmstate_spapr_event_entry = { 1853 .name = "spapr_event_log_entry", 1854 .version_id = 1, 1855 .minimum_version_id = 1, 1856 .fields = (VMStateField[]) { 1857 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1858 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1859 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1860 NULL, extended_length), 1861 VMSTATE_END_OF_LIST() 1862 }, 1863 }; 1864 1865 static const VMStateDescription vmstate_spapr_pending_events = { 1866 .name = "spapr_pending_events", 1867 .version_id = 1, 1868 .minimum_version_id = 1, 1869 .needed = spapr_pending_events_needed, 1870 .fields = (VMStateField[]) { 1871 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1872 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1873 VMSTATE_END_OF_LIST() 1874 }, 1875 }; 1876 1877 static bool spapr_ov5_cas_needed(void *opaque) 1878 { 1879 SpaprMachineState *spapr = opaque; 1880 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1881 bool cas_needed; 1882 1883 /* Prior to the introduction of SpaprOptionVector, we had two option 1884 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1885 * Both of these options encode machine topology into the device-tree 1886 * in such a way that the now-booted OS should still be able to interact 1887 * appropriately with QEMU regardless of what options were actually 1888 * negotiatied on the source side. 1889 * 1890 * As such, we can avoid migrating the CAS-negotiated options if these 1891 * are the only options available on the current machine/platform. 1892 * Since these are the only options available for pseries-2.7 and 1893 * earlier, this allows us to maintain old->new/new->old migration 1894 * compatibility. 1895 * 1896 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1897 * via default pseries-2.8 machines and explicit command-line parameters. 1898 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1899 * of the actual CAS-negotiated values to continue working properly. For 1900 * example, availability of memory unplug depends on knowing whether 1901 * OV5_HP_EVT was negotiated via CAS. 1902 * 1903 * Thus, for any cases where the set of available CAS-negotiatable 1904 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1905 * include the CAS-negotiated options in the migration stream, unless 1906 * if they affect boot time behaviour only. 1907 */ 1908 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1909 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1910 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1911 1912 /* We need extra information if we have any bits outside the mask 1913 * defined above */ 1914 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1915 1916 spapr_ovec_cleanup(ov5_mask); 1917 1918 return cas_needed; 1919 } 1920 1921 static const VMStateDescription vmstate_spapr_ov5_cas = { 1922 .name = "spapr_option_vector_ov5_cas", 1923 .version_id = 1, 1924 .minimum_version_id = 1, 1925 .needed = spapr_ov5_cas_needed, 1926 .fields = (VMStateField[]) { 1927 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1928 vmstate_spapr_ovec, SpaprOptionVector), 1929 VMSTATE_END_OF_LIST() 1930 }, 1931 }; 1932 1933 static bool spapr_patb_entry_needed(void *opaque) 1934 { 1935 SpaprMachineState *spapr = opaque; 1936 1937 return !!spapr->patb_entry; 1938 } 1939 1940 static const VMStateDescription vmstate_spapr_patb_entry = { 1941 .name = "spapr_patb_entry", 1942 .version_id = 1, 1943 .minimum_version_id = 1, 1944 .needed = spapr_patb_entry_needed, 1945 .fields = (VMStateField[]) { 1946 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1947 VMSTATE_END_OF_LIST() 1948 }, 1949 }; 1950 1951 static bool spapr_irq_map_needed(void *opaque) 1952 { 1953 SpaprMachineState *spapr = opaque; 1954 1955 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1956 } 1957 1958 static const VMStateDescription vmstate_spapr_irq_map = { 1959 .name = "spapr_irq_map", 1960 .version_id = 1, 1961 .minimum_version_id = 1, 1962 .needed = spapr_irq_map_needed, 1963 .fields = (VMStateField[]) { 1964 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1965 VMSTATE_END_OF_LIST() 1966 }, 1967 }; 1968 1969 static bool spapr_dtb_needed(void *opaque) 1970 { 1971 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1972 1973 return smc->update_dt_enabled; 1974 } 1975 1976 static int spapr_dtb_pre_load(void *opaque) 1977 { 1978 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1979 1980 g_free(spapr->fdt_blob); 1981 spapr->fdt_blob = NULL; 1982 spapr->fdt_size = 0; 1983 1984 return 0; 1985 } 1986 1987 static const VMStateDescription vmstate_spapr_dtb = { 1988 .name = "spapr_dtb", 1989 .version_id = 1, 1990 .minimum_version_id = 1, 1991 .needed = spapr_dtb_needed, 1992 .pre_load = spapr_dtb_pre_load, 1993 .fields = (VMStateField[]) { 1994 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1995 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1996 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1997 fdt_size), 1998 VMSTATE_END_OF_LIST() 1999 }, 2000 }; 2001 2002 static bool spapr_fwnmi_needed(void *opaque) 2003 { 2004 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2005 2006 return spapr->fwnmi_machine_check_addr != -1; 2007 } 2008 2009 static int spapr_fwnmi_pre_save(void *opaque) 2010 { 2011 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2012 2013 /* 2014 * Check if machine check handling is in progress and print a 2015 * warning message. 2016 */ 2017 if (spapr->fwnmi_machine_check_interlock != -1) { 2018 warn_report("A machine check is being handled during migration. The" 2019 "handler may run and log hardware error on the destination"); 2020 } 2021 2022 return 0; 2023 } 2024 2025 static const VMStateDescription vmstate_spapr_fwnmi = { 2026 .name = "spapr_fwnmi", 2027 .version_id = 1, 2028 .minimum_version_id = 1, 2029 .needed = spapr_fwnmi_needed, 2030 .pre_save = spapr_fwnmi_pre_save, 2031 .fields = (VMStateField[]) { 2032 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 2033 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 2034 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 2035 VMSTATE_END_OF_LIST() 2036 }, 2037 }; 2038 2039 static const VMStateDescription vmstate_spapr = { 2040 .name = "spapr", 2041 .version_id = 3, 2042 .minimum_version_id = 1, 2043 .pre_load = spapr_pre_load, 2044 .post_load = spapr_post_load, 2045 .pre_save = spapr_pre_save, 2046 .fields = (VMStateField[]) { 2047 /* used to be @next_irq */ 2048 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2049 2050 /* RTC offset */ 2051 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2052 2053 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2054 VMSTATE_END_OF_LIST() 2055 }, 2056 .subsections = (const VMStateDescription*[]) { 2057 &vmstate_spapr_ov5_cas, 2058 &vmstate_spapr_patb_entry, 2059 &vmstate_spapr_pending_events, 2060 &vmstate_spapr_cap_htm, 2061 &vmstate_spapr_cap_vsx, 2062 &vmstate_spapr_cap_dfp, 2063 &vmstate_spapr_cap_cfpc, 2064 &vmstate_spapr_cap_sbbc, 2065 &vmstate_spapr_cap_ibs, 2066 &vmstate_spapr_cap_hpt_maxpagesize, 2067 &vmstate_spapr_irq_map, 2068 &vmstate_spapr_cap_nested_kvm_hv, 2069 &vmstate_spapr_dtb, 2070 &vmstate_spapr_cap_large_decr, 2071 &vmstate_spapr_cap_ccf_assist, 2072 &vmstate_spapr_cap_fwnmi, 2073 &vmstate_spapr_fwnmi, 2074 NULL 2075 } 2076 }; 2077 2078 static int htab_save_setup(QEMUFile *f, void *opaque) 2079 { 2080 SpaprMachineState *spapr = opaque; 2081 2082 /* "Iteration" header */ 2083 if (!spapr->htab_shift) { 2084 qemu_put_be32(f, -1); 2085 } else { 2086 qemu_put_be32(f, spapr->htab_shift); 2087 } 2088 2089 if (spapr->htab) { 2090 spapr->htab_save_index = 0; 2091 spapr->htab_first_pass = true; 2092 } else { 2093 if (spapr->htab_shift) { 2094 assert(kvm_enabled()); 2095 } 2096 } 2097 2098 2099 return 0; 2100 } 2101 2102 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2103 int chunkstart, int n_valid, int n_invalid) 2104 { 2105 qemu_put_be32(f, chunkstart); 2106 qemu_put_be16(f, n_valid); 2107 qemu_put_be16(f, n_invalid); 2108 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2109 HASH_PTE_SIZE_64 * n_valid); 2110 } 2111 2112 static void htab_save_end_marker(QEMUFile *f) 2113 { 2114 qemu_put_be32(f, 0); 2115 qemu_put_be16(f, 0); 2116 qemu_put_be16(f, 0); 2117 } 2118 2119 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2120 int64_t max_ns) 2121 { 2122 bool has_timeout = max_ns != -1; 2123 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2124 int index = spapr->htab_save_index; 2125 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2126 2127 assert(spapr->htab_first_pass); 2128 2129 do { 2130 int chunkstart; 2131 2132 /* Consume invalid HPTEs */ 2133 while ((index < htabslots) 2134 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2135 CLEAN_HPTE(HPTE(spapr->htab, index)); 2136 index++; 2137 } 2138 2139 /* Consume valid HPTEs */ 2140 chunkstart = index; 2141 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2142 && HPTE_VALID(HPTE(spapr->htab, index))) { 2143 CLEAN_HPTE(HPTE(spapr->htab, index)); 2144 index++; 2145 } 2146 2147 if (index > chunkstart) { 2148 int n_valid = index - chunkstart; 2149 2150 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2151 2152 if (has_timeout && 2153 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2154 break; 2155 } 2156 } 2157 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2158 2159 if (index >= htabslots) { 2160 assert(index == htabslots); 2161 index = 0; 2162 spapr->htab_first_pass = false; 2163 } 2164 spapr->htab_save_index = index; 2165 } 2166 2167 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2168 int64_t max_ns) 2169 { 2170 bool final = max_ns < 0; 2171 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2172 int examined = 0, sent = 0; 2173 int index = spapr->htab_save_index; 2174 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2175 2176 assert(!spapr->htab_first_pass); 2177 2178 do { 2179 int chunkstart, invalidstart; 2180 2181 /* Consume non-dirty HPTEs */ 2182 while ((index < htabslots) 2183 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2184 index++; 2185 examined++; 2186 } 2187 2188 chunkstart = index; 2189 /* Consume valid dirty HPTEs */ 2190 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2191 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2192 && HPTE_VALID(HPTE(spapr->htab, index))) { 2193 CLEAN_HPTE(HPTE(spapr->htab, index)); 2194 index++; 2195 examined++; 2196 } 2197 2198 invalidstart = index; 2199 /* Consume invalid dirty HPTEs */ 2200 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2201 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2202 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2203 CLEAN_HPTE(HPTE(spapr->htab, index)); 2204 index++; 2205 examined++; 2206 } 2207 2208 if (index > chunkstart) { 2209 int n_valid = invalidstart - chunkstart; 2210 int n_invalid = index - invalidstart; 2211 2212 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2213 sent += index - chunkstart; 2214 2215 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2216 break; 2217 } 2218 } 2219 2220 if (examined >= htabslots) { 2221 break; 2222 } 2223 2224 if (index >= htabslots) { 2225 assert(index == htabslots); 2226 index = 0; 2227 } 2228 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2229 2230 if (index >= htabslots) { 2231 assert(index == htabslots); 2232 index = 0; 2233 } 2234 2235 spapr->htab_save_index = index; 2236 2237 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2238 } 2239 2240 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2241 #define MAX_KVM_BUF_SIZE 2048 2242 2243 static int htab_save_iterate(QEMUFile *f, void *opaque) 2244 { 2245 SpaprMachineState *spapr = opaque; 2246 int fd; 2247 int rc = 0; 2248 2249 /* Iteration header */ 2250 if (!spapr->htab_shift) { 2251 qemu_put_be32(f, -1); 2252 return 1; 2253 } else { 2254 qemu_put_be32(f, 0); 2255 } 2256 2257 if (!spapr->htab) { 2258 assert(kvm_enabled()); 2259 2260 fd = get_htab_fd(spapr); 2261 if (fd < 0) { 2262 return fd; 2263 } 2264 2265 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2266 if (rc < 0) { 2267 return rc; 2268 } 2269 } else if (spapr->htab_first_pass) { 2270 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2271 } else { 2272 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2273 } 2274 2275 htab_save_end_marker(f); 2276 2277 return rc; 2278 } 2279 2280 static int htab_save_complete(QEMUFile *f, void *opaque) 2281 { 2282 SpaprMachineState *spapr = opaque; 2283 int fd; 2284 2285 /* Iteration header */ 2286 if (!spapr->htab_shift) { 2287 qemu_put_be32(f, -1); 2288 return 0; 2289 } else { 2290 qemu_put_be32(f, 0); 2291 } 2292 2293 if (!spapr->htab) { 2294 int rc; 2295 2296 assert(kvm_enabled()); 2297 2298 fd = get_htab_fd(spapr); 2299 if (fd < 0) { 2300 return fd; 2301 } 2302 2303 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2304 if (rc < 0) { 2305 return rc; 2306 } 2307 } else { 2308 if (spapr->htab_first_pass) { 2309 htab_save_first_pass(f, spapr, -1); 2310 } 2311 htab_save_later_pass(f, spapr, -1); 2312 } 2313 2314 /* End marker */ 2315 htab_save_end_marker(f); 2316 2317 return 0; 2318 } 2319 2320 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2321 { 2322 SpaprMachineState *spapr = opaque; 2323 uint32_t section_hdr; 2324 int fd = -1; 2325 Error *local_err = NULL; 2326 2327 if (version_id < 1 || version_id > 1) { 2328 error_report("htab_load() bad version"); 2329 return -EINVAL; 2330 } 2331 2332 section_hdr = qemu_get_be32(f); 2333 2334 if (section_hdr == -1) { 2335 spapr_free_hpt(spapr); 2336 return 0; 2337 } 2338 2339 if (section_hdr) { 2340 /* First section gives the htab size */ 2341 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2342 if (local_err) { 2343 error_report_err(local_err); 2344 return -EINVAL; 2345 } 2346 return 0; 2347 } 2348 2349 if (!spapr->htab) { 2350 assert(kvm_enabled()); 2351 2352 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2353 if (fd < 0) { 2354 error_report_err(local_err); 2355 return fd; 2356 } 2357 } 2358 2359 while (true) { 2360 uint32_t index; 2361 uint16_t n_valid, n_invalid; 2362 2363 index = qemu_get_be32(f); 2364 n_valid = qemu_get_be16(f); 2365 n_invalid = qemu_get_be16(f); 2366 2367 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2368 /* End of Stream */ 2369 break; 2370 } 2371 2372 if ((index + n_valid + n_invalid) > 2373 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2374 /* Bad index in stream */ 2375 error_report( 2376 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2377 index, n_valid, n_invalid, spapr->htab_shift); 2378 return -EINVAL; 2379 } 2380 2381 if (spapr->htab) { 2382 if (n_valid) { 2383 qemu_get_buffer(f, HPTE(spapr->htab, index), 2384 HASH_PTE_SIZE_64 * n_valid); 2385 } 2386 if (n_invalid) { 2387 memset(HPTE(spapr->htab, index + n_valid), 0, 2388 HASH_PTE_SIZE_64 * n_invalid); 2389 } 2390 } else { 2391 int rc; 2392 2393 assert(fd >= 0); 2394 2395 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2396 if (rc < 0) { 2397 return rc; 2398 } 2399 } 2400 } 2401 2402 if (!spapr->htab) { 2403 assert(fd >= 0); 2404 close(fd); 2405 } 2406 2407 return 0; 2408 } 2409 2410 static void htab_save_cleanup(void *opaque) 2411 { 2412 SpaprMachineState *spapr = opaque; 2413 2414 close_htab_fd(spapr); 2415 } 2416 2417 static SaveVMHandlers savevm_htab_handlers = { 2418 .save_setup = htab_save_setup, 2419 .save_live_iterate = htab_save_iterate, 2420 .save_live_complete_precopy = htab_save_complete, 2421 .save_cleanup = htab_save_cleanup, 2422 .load_state = htab_load, 2423 }; 2424 2425 static void spapr_boot_set(void *opaque, const char *boot_device, 2426 Error **errp) 2427 { 2428 MachineState *machine = MACHINE(opaque); 2429 machine->boot_order = g_strdup(boot_device); 2430 } 2431 2432 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2433 { 2434 MachineState *machine = MACHINE(spapr); 2435 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2436 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2437 int i; 2438 2439 for (i = 0; i < nr_lmbs; i++) { 2440 uint64_t addr; 2441 2442 addr = i * lmb_size + machine->device_memory->base; 2443 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2444 addr / lmb_size); 2445 } 2446 } 2447 2448 /* 2449 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2450 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2451 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2452 */ 2453 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2454 { 2455 int i; 2456 2457 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2458 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2459 " is not aligned to %" PRIu64 " MiB", 2460 machine->ram_size, 2461 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2462 return; 2463 } 2464 2465 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2466 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2467 " is not aligned to %" PRIu64 " MiB", 2468 machine->ram_size, 2469 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2470 return; 2471 } 2472 2473 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2474 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2475 error_setg(errp, 2476 "Node %d memory size 0x%" PRIx64 2477 " is not aligned to %" PRIu64 " MiB", 2478 i, machine->numa_state->nodes[i].node_mem, 2479 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2480 return; 2481 } 2482 } 2483 } 2484 2485 /* find cpu slot in machine->possible_cpus by core_id */ 2486 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2487 { 2488 int index = id / ms->smp.threads; 2489 2490 if (index >= ms->possible_cpus->len) { 2491 return NULL; 2492 } 2493 if (idx) { 2494 *idx = index; 2495 } 2496 return &ms->possible_cpus->cpus[index]; 2497 } 2498 2499 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2500 { 2501 MachineState *ms = MACHINE(spapr); 2502 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2503 Error *local_err = NULL; 2504 bool vsmt_user = !!spapr->vsmt; 2505 int kvm_smt = kvmppc_smt_threads(); 2506 int ret; 2507 unsigned int smp_threads = ms->smp.threads; 2508 2509 if (!kvm_enabled() && (smp_threads > 1)) { 2510 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2511 "on a pseries machine"); 2512 goto out; 2513 } 2514 if (!is_power_of_2(smp_threads)) { 2515 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2516 "machine because it must be a power of 2", smp_threads); 2517 goto out; 2518 } 2519 2520 /* Detemine the VSMT mode to use: */ 2521 if (vsmt_user) { 2522 if (spapr->vsmt < smp_threads) { 2523 error_setg(&local_err, "Cannot support VSMT mode %d" 2524 " because it must be >= threads/core (%d)", 2525 spapr->vsmt, smp_threads); 2526 goto out; 2527 } 2528 /* In this case, spapr->vsmt has been set by the command line */ 2529 } else if (!smc->smp_threads_vsmt) { 2530 /* 2531 * Default VSMT value is tricky, because we need it to be as 2532 * consistent as possible (for migration), but this requires 2533 * changing it for at least some existing cases. We pick 8 as 2534 * the value that we'd get with KVM on POWER8, the 2535 * overwhelmingly common case in production systems. 2536 */ 2537 spapr->vsmt = MAX(8, smp_threads); 2538 } else { 2539 spapr->vsmt = smp_threads; 2540 } 2541 2542 /* KVM: If necessary, set the SMT mode: */ 2543 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2544 ret = kvmppc_set_smt_threads(spapr->vsmt); 2545 if (ret) { 2546 /* Looks like KVM isn't able to change VSMT mode */ 2547 error_setg(&local_err, 2548 "Failed to set KVM's VSMT mode to %d (errno %d)", 2549 spapr->vsmt, ret); 2550 /* We can live with that if the default one is big enough 2551 * for the number of threads, and a submultiple of the one 2552 * we want. In this case we'll waste some vcpu ids, but 2553 * behaviour will be correct */ 2554 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2555 warn_report_err(local_err); 2556 local_err = NULL; 2557 goto out; 2558 } else { 2559 if (!vsmt_user) { 2560 error_append_hint(&local_err, 2561 "On PPC, a VM with %d threads/core" 2562 " on a host with %d threads/core" 2563 " requires the use of VSMT mode %d.\n", 2564 smp_threads, kvm_smt, spapr->vsmt); 2565 } 2566 kvmppc_error_append_smt_possible_hint(&local_err); 2567 goto out; 2568 } 2569 } 2570 } 2571 /* else TCG: nothing to do currently */ 2572 out: 2573 error_propagate(errp, local_err); 2574 } 2575 2576 static void spapr_init_cpus(SpaprMachineState *spapr) 2577 { 2578 MachineState *machine = MACHINE(spapr); 2579 MachineClass *mc = MACHINE_GET_CLASS(machine); 2580 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2581 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2582 const CPUArchIdList *possible_cpus; 2583 unsigned int smp_cpus = machine->smp.cpus; 2584 unsigned int smp_threads = machine->smp.threads; 2585 unsigned int max_cpus = machine->smp.max_cpus; 2586 int boot_cores_nr = smp_cpus / smp_threads; 2587 int i; 2588 2589 possible_cpus = mc->possible_cpu_arch_ids(machine); 2590 if (mc->has_hotpluggable_cpus) { 2591 if (smp_cpus % smp_threads) { 2592 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2593 smp_cpus, smp_threads); 2594 exit(1); 2595 } 2596 if (max_cpus % smp_threads) { 2597 error_report("max_cpus (%u) must be multiple of threads (%u)", 2598 max_cpus, smp_threads); 2599 exit(1); 2600 } 2601 } else { 2602 if (max_cpus != smp_cpus) { 2603 error_report("This machine version does not support CPU hotplug"); 2604 exit(1); 2605 } 2606 boot_cores_nr = possible_cpus->len; 2607 } 2608 2609 if (smc->pre_2_10_has_unused_icps) { 2610 int i; 2611 2612 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2613 /* Dummy entries get deregistered when real ICPState objects 2614 * are registered during CPU core hotplug. 2615 */ 2616 pre_2_10_vmstate_register_dummy_icp(i); 2617 } 2618 } 2619 2620 for (i = 0; i < possible_cpus->len; i++) { 2621 int core_id = i * smp_threads; 2622 2623 if (mc->has_hotpluggable_cpus) { 2624 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2625 spapr_vcpu_id(spapr, core_id)); 2626 } 2627 2628 if (i < boot_cores_nr) { 2629 Object *core = object_new(type); 2630 int nr_threads = smp_threads; 2631 2632 /* Handle the partially filled core for older machine types */ 2633 if ((i + 1) * smp_threads >= smp_cpus) { 2634 nr_threads = smp_cpus - i * smp_threads; 2635 } 2636 2637 object_property_set_int(core, nr_threads, "nr-threads", 2638 &error_fatal); 2639 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2640 &error_fatal); 2641 object_property_set_bool(core, true, "realized", &error_fatal); 2642 2643 object_unref(core); 2644 } 2645 } 2646 } 2647 2648 static PCIHostState *spapr_create_default_phb(void) 2649 { 2650 DeviceState *dev; 2651 2652 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 2653 qdev_prop_set_uint32(dev, "index", 0); 2654 qdev_init_nofail(dev); 2655 2656 return PCI_HOST_BRIDGE(dev); 2657 } 2658 2659 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2660 { 2661 MachineState *machine = MACHINE(spapr); 2662 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2663 hwaddr rma_size = machine->ram_size; 2664 hwaddr node0_size = spapr_node0_size(machine); 2665 2666 /* RMA has to fit in the first NUMA node */ 2667 rma_size = MIN(rma_size, node0_size); 2668 2669 /* 2670 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2671 * never exceed that 2672 */ 2673 rma_size = MIN(rma_size, 1 * TiB); 2674 2675 /* 2676 * Clamp the RMA size based on machine type. This is for 2677 * migration compatibility with older qemu versions, which limited 2678 * the RMA size for complicated and mostly bad reasons. 2679 */ 2680 if (smc->rma_limit) { 2681 rma_size = MIN(rma_size, smc->rma_limit); 2682 } 2683 2684 if (rma_size < MIN_RMA_SLOF) { 2685 error_setg(errp, 2686 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2687 "ldMiB guest RMA (Real Mode Area memory)", 2688 MIN_RMA_SLOF / MiB); 2689 return 0; 2690 } 2691 2692 return rma_size; 2693 } 2694 2695 /* pSeries LPAR / sPAPR hardware init */ 2696 static void spapr_machine_init(MachineState *machine) 2697 { 2698 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2699 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2700 MachineClass *mc = MACHINE_GET_CLASS(machine); 2701 const char *kernel_filename = machine->kernel_filename; 2702 const char *initrd_filename = machine->initrd_filename; 2703 PCIHostState *phb; 2704 int i; 2705 MemoryRegion *sysmem = get_system_memory(); 2706 long load_limit, fw_size; 2707 char *filename; 2708 Error *resize_hpt_err = NULL; 2709 2710 msi_nonbroken = true; 2711 2712 QLIST_INIT(&spapr->phbs); 2713 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2714 2715 /* Determine capabilities to run with */ 2716 spapr_caps_init(spapr); 2717 2718 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2719 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2720 /* 2721 * If the user explicitly requested a mode we should either 2722 * supply it, or fail completely (which we do below). But if 2723 * it's not set explicitly, we reset our mode to something 2724 * that works 2725 */ 2726 if (resize_hpt_err) { 2727 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2728 error_free(resize_hpt_err); 2729 resize_hpt_err = NULL; 2730 } else { 2731 spapr->resize_hpt = smc->resize_hpt_default; 2732 } 2733 } 2734 2735 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2736 2737 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2738 /* 2739 * User requested HPT resize, but this host can't supply it. Bail out 2740 */ 2741 error_report_err(resize_hpt_err); 2742 exit(1); 2743 } 2744 2745 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2746 2747 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2748 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2749 2750 /* 2751 * VSMT must be set in order to be able to compute VCPU ids, ie to 2752 * call spapr_max_server_number() or spapr_vcpu_id(). 2753 */ 2754 spapr_set_vsmt_mode(spapr, &error_fatal); 2755 2756 /* Set up Interrupt Controller before we create the VCPUs */ 2757 spapr_irq_init(spapr, &error_fatal); 2758 2759 /* Set up containers for ibm,client-architecture-support negotiated options 2760 */ 2761 spapr->ov5 = spapr_ovec_new(); 2762 spapr->ov5_cas = spapr_ovec_new(); 2763 2764 if (smc->dr_lmb_enabled) { 2765 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2766 spapr_validate_node_memory(machine, &error_fatal); 2767 } 2768 2769 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2770 2771 /* advertise support for dedicated HP event source to guests */ 2772 if (spapr->use_hotplug_event_source) { 2773 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2774 } 2775 2776 /* advertise support for HPT resizing */ 2777 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2778 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2779 } 2780 2781 /* advertise support for ibm,dyamic-memory-v2 */ 2782 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2783 2784 /* advertise XIVE on POWER9 machines */ 2785 if (spapr->irq->xive) { 2786 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2787 } 2788 2789 /* init CPUs */ 2790 spapr_init_cpus(spapr); 2791 2792 /* 2793 * check we don't have a memory-less/cpu-less NUMA node 2794 * Firmware relies on the existing memory/cpu topology to provide the 2795 * NUMA topology to the kernel. 2796 * And the linux kernel needs to know the NUMA topology at start 2797 * to be able to hotplug CPUs later. 2798 */ 2799 if (machine->numa_state->num_nodes) { 2800 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2801 /* check for memory-less node */ 2802 if (machine->numa_state->nodes[i].node_mem == 0) { 2803 CPUState *cs; 2804 int found = 0; 2805 /* check for cpu-less node */ 2806 CPU_FOREACH(cs) { 2807 PowerPCCPU *cpu = POWERPC_CPU(cs); 2808 if (cpu->node_id == i) { 2809 found = 1; 2810 break; 2811 } 2812 } 2813 /* memory-less and cpu-less node */ 2814 if (!found) { 2815 error_report( 2816 "Memory-less/cpu-less nodes are not supported (node %d)", 2817 i); 2818 exit(1); 2819 } 2820 } 2821 } 2822 2823 } 2824 2825 /* 2826 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2827 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2828 * called from vPHB reset handler so we initialize the counter here. 2829 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2830 * must be equally distant from any other node. 2831 * The final value of spapr->gpu_numa_id is going to be written to 2832 * max-associativity-domains in spapr_build_fdt(). 2833 */ 2834 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2835 2836 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2837 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2838 spapr->max_compat_pvr)) { 2839 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2840 /* KVM and TCG always allow GTSE with radix... */ 2841 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2842 } 2843 /* ... but not with hash (currently). */ 2844 2845 if (kvm_enabled()) { 2846 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2847 kvmppc_enable_logical_ci_hcalls(); 2848 kvmppc_enable_set_mode_hcall(); 2849 2850 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2851 kvmppc_enable_clear_ref_mod_hcalls(); 2852 2853 /* Enable H_PAGE_INIT */ 2854 kvmppc_enable_h_page_init(); 2855 } 2856 2857 /* map RAM */ 2858 memory_region_add_subregion(sysmem, 0, machine->ram); 2859 2860 /* always allocate the device memory information */ 2861 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2862 2863 /* initialize hotplug memory address space */ 2864 if (machine->ram_size < machine->maxram_size) { 2865 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2866 /* 2867 * Limit the number of hotpluggable memory slots to half the number 2868 * slots that KVM supports, leaving the other half for PCI and other 2869 * devices. However ensure that number of slots doesn't drop below 32. 2870 */ 2871 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2872 SPAPR_MAX_RAM_SLOTS; 2873 2874 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2875 max_memslots = SPAPR_MAX_RAM_SLOTS; 2876 } 2877 if (machine->ram_slots > max_memslots) { 2878 error_report("Specified number of memory slots %" 2879 PRIu64" exceeds max supported %d", 2880 machine->ram_slots, max_memslots); 2881 exit(1); 2882 } 2883 2884 machine->device_memory->base = ROUND_UP(machine->ram_size, 2885 SPAPR_DEVICE_MEM_ALIGN); 2886 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2887 "device-memory", device_mem_size); 2888 memory_region_add_subregion(sysmem, machine->device_memory->base, 2889 &machine->device_memory->mr); 2890 } 2891 2892 if (smc->dr_lmb_enabled) { 2893 spapr_create_lmb_dr_connectors(spapr); 2894 } 2895 2896 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2897 /* Create the error string for live migration blocker */ 2898 error_setg(&spapr->fwnmi_migration_blocker, 2899 "A machine check is being handled during migration. The handler" 2900 "may run and log hardware error on the destination"); 2901 } 2902 2903 if (mc->nvdimm_supported) { 2904 spapr_create_nvdimm_dr_connectors(spapr); 2905 } 2906 2907 /* Set up RTAS event infrastructure */ 2908 spapr_events_init(spapr); 2909 2910 /* Set up the RTC RTAS interfaces */ 2911 spapr_rtc_create(spapr); 2912 2913 /* Set up VIO bus */ 2914 spapr->vio_bus = spapr_vio_bus_init(); 2915 2916 for (i = 0; i < serial_max_hds(); i++) { 2917 if (serial_hd(i)) { 2918 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2919 } 2920 } 2921 2922 /* We always have at least the nvram device on VIO */ 2923 spapr_create_nvram(spapr); 2924 2925 /* 2926 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2927 * connectors (described in root DT node's "ibm,drc-types" property) 2928 * are pre-initialized here. additional child connectors (such as 2929 * connectors for a PHBs PCI slots) are added as needed during their 2930 * parent's realization. 2931 */ 2932 if (smc->dr_phb_enabled) { 2933 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2934 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2935 } 2936 } 2937 2938 /* Set up PCI */ 2939 spapr_pci_rtas_init(); 2940 2941 phb = spapr_create_default_phb(); 2942 2943 for (i = 0; i < nb_nics; i++) { 2944 NICInfo *nd = &nd_table[i]; 2945 2946 if (!nd->model) { 2947 nd->model = g_strdup("spapr-vlan"); 2948 } 2949 2950 if (g_str_equal(nd->model, "spapr-vlan") || 2951 g_str_equal(nd->model, "ibmveth")) { 2952 spapr_vlan_create(spapr->vio_bus, nd); 2953 } else { 2954 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2955 } 2956 } 2957 2958 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2959 spapr_vscsi_create(spapr->vio_bus); 2960 } 2961 2962 /* Graphics */ 2963 if (spapr_vga_init(phb->bus, &error_fatal)) { 2964 spapr->has_graphics = true; 2965 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2966 } 2967 2968 if (machine->usb) { 2969 if (smc->use_ohci_by_default) { 2970 pci_create_simple(phb->bus, -1, "pci-ohci"); 2971 } else { 2972 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2973 } 2974 2975 if (spapr->has_graphics) { 2976 USBBus *usb_bus = usb_bus_find(-1); 2977 2978 usb_create_simple(usb_bus, "usb-kbd"); 2979 usb_create_simple(usb_bus, "usb-mouse"); 2980 } 2981 } 2982 2983 if (kernel_filename) { 2984 uint64_t lowaddr = 0; 2985 2986 spapr->kernel_size = load_elf(kernel_filename, NULL, 2987 translate_kernel_address, spapr, 2988 NULL, &lowaddr, NULL, NULL, 1, 2989 PPC_ELF_MACHINE, 0, 0); 2990 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2991 spapr->kernel_size = load_elf(kernel_filename, NULL, 2992 translate_kernel_address, spapr, NULL, 2993 &lowaddr, NULL, NULL, 0, 2994 PPC_ELF_MACHINE, 2995 0, 0); 2996 spapr->kernel_le = spapr->kernel_size > 0; 2997 } 2998 if (spapr->kernel_size < 0) { 2999 error_report("error loading %s: %s", kernel_filename, 3000 load_elf_strerror(spapr->kernel_size)); 3001 exit(1); 3002 } 3003 3004 /* load initrd */ 3005 if (initrd_filename) { 3006 /* Try to locate the initrd in the gap between the kernel 3007 * and the firmware. Add a bit of space just in case 3008 */ 3009 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 3010 + 0x1ffff) & ~0xffff; 3011 spapr->initrd_size = load_image_targphys(initrd_filename, 3012 spapr->initrd_base, 3013 load_limit 3014 - spapr->initrd_base); 3015 if (spapr->initrd_size < 0) { 3016 error_report("could not load initial ram disk '%s'", 3017 initrd_filename); 3018 exit(1); 3019 } 3020 } 3021 } 3022 3023 if (bios_name == NULL) { 3024 bios_name = FW_FILE_NAME; 3025 } 3026 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 3027 if (!filename) { 3028 error_report("Could not find LPAR firmware '%s'", bios_name); 3029 exit(1); 3030 } 3031 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 3032 if (fw_size <= 0) { 3033 error_report("Could not load LPAR firmware '%s'", filename); 3034 exit(1); 3035 } 3036 g_free(filename); 3037 3038 /* FIXME: Should register things through the MachineState's qdev 3039 * interface, this is a legacy from the sPAPREnvironment structure 3040 * which predated MachineState but had a similar function */ 3041 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3042 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3043 &savevm_htab_handlers, spapr); 3044 3045 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine), 3046 &error_fatal); 3047 3048 qemu_register_boot_set(spapr_boot_set, spapr); 3049 3050 /* 3051 * Nothing needs to be done to resume a suspended guest because 3052 * suspending does not change the machine state, so no need for 3053 * a ->wakeup method. 3054 */ 3055 qemu_register_wakeup_support(); 3056 3057 if (kvm_enabled()) { 3058 /* to stop and start vmclock */ 3059 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3060 &spapr->tb); 3061 3062 kvmppc_spapr_enable_inkernel_multitce(); 3063 } 3064 3065 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3066 } 3067 3068 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3069 { 3070 if (!vm_type) { 3071 return 0; 3072 } 3073 3074 if (!strcmp(vm_type, "HV")) { 3075 return 1; 3076 } 3077 3078 if (!strcmp(vm_type, "PR")) { 3079 return 2; 3080 } 3081 3082 error_report("Unknown kvm-type specified '%s'", vm_type); 3083 exit(1); 3084 } 3085 3086 /* 3087 * Implementation of an interface to adjust firmware path 3088 * for the bootindex property handling. 3089 */ 3090 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3091 DeviceState *dev) 3092 { 3093 #define CAST(type, obj, name) \ 3094 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3095 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3096 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3097 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3098 3099 if (d) { 3100 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3101 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3102 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3103 3104 if (spapr) { 3105 /* 3106 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3107 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3108 * 0x8000 | (target << 8) | (bus << 5) | lun 3109 * (see the "Logical unit addressing format" table in SAM5) 3110 */ 3111 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3112 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3113 (uint64_t)id << 48); 3114 } else if (virtio) { 3115 /* 3116 * We use SRP luns of the form 01000000 | (target << 8) | lun 3117 * in the top 32 bits of the 64-bit LUN 3118 * Note: the quote above is from SLOF and it is wrong, 3119 * the actual binding is: 3120 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3121 */ 3122 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3123 if (d->lun >= 256) { 3124 /* Use the LUN "flat space addressing method" */ 3125 id |= 0x4000; 3126 } 3127 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3128 (uint64_t)id << 32); 3129 } else if (usb) { 3130 /* 3131 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3132 * in the top 32 bits of the 64-bit LUN 3133 */ 3134 unsigned usb_port = atoi(usb->port->path); 3135 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3136 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3137 (uint64_t)id << 32); 3138 } 3139 } 3140 3141 /* 3142 * SLOF probes the USB devices, and if it recognizes that the device is a 3143 * storage device, it changes its name to "storage" instead of "usb-host", 3144 * and additionally adds a child node for the SCSI LUN, so the correct 3145 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3146 */ 3147 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3148 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3149 if (usb_host_dev_is_scsi_storage(usbdev)) { 3150 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3151 } 3152 } 3153 3154 if (phb) { 3155 /* Replace "pci" with "pci@800000020000000" */ 3156 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3157 } 3158 3159 if (vsc) { 3160 /* Same logic as virtio above */ 3161 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3162 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3163 } 3164 3165 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3166 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3167 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3168 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3169 } 3170 3171 return NULL; 3172 } 3173 3174 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3175 { 3176 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3177 3178 return g_strdup(spapr->kvm_type); 3179 } 3180 3181 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3182 { 3183 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3184 3185 g_free(spapr->kvm_type); 3186 spapr->kvm_type = g_strdup(value); 3187 } 3188 3189 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3190 { 3191 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3192 3193 return spapr->use_hotplug_event_source; 3194 } 3195 3196 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3197 Error **errp) 3198 { 3199 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3200 3201 spapr->use_hotplug_event_source = value; 3202 } 3203 3204 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3205 { 3206 return true; 3207 } 3208 3209 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3210 { 3211 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3212 3213 switch (spapr->resize_hpt) { 3214 case SPAPR_RESIZE_HPT_DEFAULT: 3215 return g_strdup("default"); 3216 case SPAPR_RESIZE_HPT_DISABLED: 3217 return g_strdup("disabled"); 3218 case SPAPR_RESIZE_HPT_ENABLED: 3219 return g_strdup("enabled"); 3220 case SPAPR_RESIZE_HPT_REQUIRED: 3221 return g_strdup("required"); 3222 } 3223 g_assert_not_reached(); 3224 } 3225 3226 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3227 { 3228 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3229 3230 if (strcmp(value, "default") == 0) { 3231 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3232 } else if (strcmp(value, "disabled") == 0) { 3233 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3234 } else if (strcmp(value, "enabled") == 0) { 3235 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3236 } else if (strcmp(value, "required") == 0) { 3237 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3238 } else { 3239 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3240 } 3241 } 3242 3243 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3244 { 3245 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3246 3247 if (spapr->irq == &spapr_irq_xics_legacy) { 3248 return g_strdup("legacy"); 3249 } else if (spapr->irq == &spapr_irq_xics) { 3250 return g_strdup("xics"); 3251 } else if (spapr->irq == &spapr_irq_xive) { 3252 return g_strdup("xive"); 3253 } else if (spapr->irq == &spapr_irq_dual) { 3254 return g_strdup("dual"); 3255 } 3256 g_assert_not_reached(); 3257 } 3258 3259 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3260 { 3261 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3262 3263 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3264 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3265 return; 3266 } 3267 3268 /* The legacy IRQ backend can not be set */ 3269 if (strcmp(value, "xics") == 0) { 3270 spapr->irq = &spapr_irq_xics; 3271 } else if (strcmp(value, "xive") == 0) { 3272 spapr->irq = &spapr_irq_xive; 3273 } else if (strcmp(value, "dual") == 0) { 3274 spapr->irq = &spapr_irq_dual; 3275 } else { 3276 error_setg(errp, "Bad value for \"ic-mode\" property"); 3277 } 3278 } 3279 3280 static char *spapr_get_host_model(Object *obj, Error **errp) 3281 { 3282 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3283 3284 return g_strdup(spapr->host_model); 3285 } 3286 3287 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3288 { 3289 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3290 3291 g_free(spapr->host_model); 3292 spapr->host_model = g_strdup(value); 3293 } 3294 3295 static char *spapr_get_host_serial(Object *obj, Error **errp) 3296 { 3297 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3298 3299 return g_strdup(spapr->host_serial); 3300 } 3301 3302 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3303 { 3304 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3305 3306 g_free(spapr->host_serial); 3307 spapr->host_serial = g_strdup(value); 3308 } 3309 3310 static void spapr_instance_init(Object *obj) 3311 { 3312 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3313 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3314 3315 spapr->htab_fd = -1; 3316 spapr->use_hotplug_event_source = true; 3317 object_property_add_str(obj, "kvm-type", 3318 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3319 object_property_set_description(obj, "kvm-type", 3320 "Specifies the KVM virtualization mode (HV, PR)", 3321 NULL); 3322 object_property_add_bool(obj, "modern-hotplug-events", 3323 spapr_get_modern_hotplug_events, 3324 spapr_set_modern_hotplug_events, 3325 NULL); 3326 object_property_set_description(obj, "modern-hotplug-events", 3327 "Use dedicated hotplug event mechanism in" 3328 " place of standard EPOW events when possible" 3329 " (required for memory hot-unplug support)", 3330 NULL); 3331 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3332 "Maximum permitted CPU compatibility mode", 3333 &error_fatal); 3334 3335 object_property_add_str(obj, "resize-hpt", 3336 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3337 object_property_set_description(obj, "resize-hpt", 3338 "Resizing of the Hash Page Table (enabled, disabled, required)", 3339 NULL); 3340 object_property_add_uint32_ptr(obj, "vsmt", 3341 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE, 3342 &error_abort); 3343 object_property_set_description(obj, "vsmt", 3344 "Virtual SMT: KVM behaves as if this were" 3345 " the host's SMT mode", &error_abort); 3346 3347 object_property_add_bool(obj, "vfio-no-msix-emulation", 3348 spapr_get_msix_emulation, NULL, NULL); 3349 3350 object_property_add_uint64_ptr(obj, "kernel-addr", 3351 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE, 3352 &error_abort); 3353 object_property_set_description(obj, "kernel-addr", 3354 stringify(KERNEL_LOAD_ADDR) 3355 " for -kernel is the default", 3356 NULL); 3357 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3358 /* The machine class defines the default interrupt controller mode */ 3359 spapr->irq = smc->irq; 3360 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3361 spapr_set_ic_mode, NULL); 3362 object_property_set_description(obj, "ic-mode", 3363 "Specifies the interrupt controller mode (xics, xive, dual)", 3364 NULL); 3365 3366 object_property_add_str(obj, "host-model", 3367 spapr_get_host_model, spapr_set_host_model, 3368 &error_abort); 3369 object_property_set_description(obj, "host-model", 3370 "Host model to advertise in guest device tree", &error_abort); 3371 object_property_add_str(obj, "host-serial", 3372 spapr_get_host_serial, spapr_set_host_serial, 3373 &error_abort); 3374 object_property_set_description(obj, "host-serial", 3375 "Host serial number to advertise in guest device tree", &error_abort); 3376 } 3377 3378 static void spapr_machine_finalizefn(Object *obj) 3379 { 3380 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3381 3382 g_free(spapr->kvm_type); 3383 } 3384 3385 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3386 { 3387 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3388 PowerPCCPU *cpu = POWERPC_CPU(cs); 3389 CPUPPCState *env = &cpu->env; 3390 3391 cpu_synchronize_state(cs); 3392 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3393 if (spapr->fwnmi_system_reset_addr != -1) { 3394 uint64_t rtas_addr, addr; 3395 3396 /* get rtas addr from fdt */ 3397 rtas_addr = spapr_get_rtas_addr(); 3398 if (!rtas_addr) { 3399 qemu_system_guest_panicked(NULL); 3400 return; 3401 } 3402 3403 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3404 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3405 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3406 env->gpr[3] = addr; 3407 } 3408 ppc_cpu_do_system_reset(cs); 3409 if (spapr->fwnmi_system_reset_addr != -1) { 3410 env->nip = spapr->fwnmi_system_reset_addr; 3411 } 3412 } 3413 3414 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3415 { 3416 CPUState *cs; 3417 3418 CPU_FOREACH(cs) { 3419 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3420 } 3421 } 3422 3423 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3424 void *fdt, int *fdt_start_offset, Error **errp) 3425 { 3426 uint64_t addr; 3427 uint32_t node; 3428 3429 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3430 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3431 &error_abort); 3432 *fdt_start_offset = spapr_dt_memory_node(fdt, node, addr, 3433 SPAPR_MEMORY_BLOCK_SIZE); 3434 return 0; 3435 } 3436 3437 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3438 bool dedicated_hp_event_source, Error **errp) 3439 { 3440 SpaprDrc *drc; 3441 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3442 int i; 3443 uint64_t addr = addr_start; 3444 bool hotplugged = spapr_drc_hotplugged(dev); 3445 Error *local_err = NULL; 3446 3447 for (i = 0; i < nr_lmbs; i++) { 3448 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3449 addr / SPAPR_MEMORY_BLOCK_SIZE); 3450 g_assert(drc); 3451 3452 spapr_drc_attach(drc, dev, &local_err); 3453 if (local_err) { 3454 while (addr > addr_start) { 3455 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3456 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3457 addr / SPAPR_MEMORY_BLOCK_SIZE); 3458 spapr_drc_detach(drc); 3459 } 3460 error_propagate(errp, local_err); 3461 return; 3462 } 3463 if (!hotplugged) { 3464 spapr_drc_reset(drc); 3465 } 3466 addr += SPAPR_MEMORY_BLOCK_SIZE; 3467 } 3468 /* send hotplug notification to the 3469 * guest only in case of hotplugged memory 3470 */ 3471 if (hotplugged) { 3472 if (dedicated_hp_event_source) { 3473 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3474 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3475 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3476 nr_lmbs, 3477 spapr_drc_index(drc)); 3478 } else { 3479 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3480 nr_lmbs); 3481 } 3482 } 3483 } 3484 3485 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3486 Error **errp) 3487 { 3488 Error *local_err = NULL; 3489 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3490 PCDIMMDevice *dimm = PC_DIMM(dev); 3491 uint64_t size, addr, slot; 3492 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3493 3494 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3495 3496 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3497 if (local_err) { 3498 goto out; 3499 } 3500 3501 if (!is_nvdimm) { 3502 addr = object_property_get_uint(OBJECT(dimm), 3503 PC_DIMM_ADDR_PROP, &local_err); 3504 if (local_err) { 3505 goto out_unplug; 3506 } 3507 spapr_add_lmbs(dev, addr, size, 3508 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3509 &local_err); 3510 } else { 3511 slot = object_property_get_uint(OBJECT(dimm), 3512 PC_DIMM_SLOT_PROP, &local_err); 3513 if (local_err) { 3514 goto out_unplug; 3515 } 3516 spapr_add_nvdimm(dev, slot, &local_err); 3517 } 3518 3519 if (local_err) { 3520 goto out_unplug; 3521 } 3522 3523 return; 3524 3525 out_unplug: 3526 pc_dimm_unplug(dimm, MACHINE(ms)); 3527 out: 3528 error_propagate(errp, local_err); 3529 } 3530 3531 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3532 Error **errp) 3533 { 3534 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3535 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3536 const MachineClass *mc = MACHINE_CLASS(smc); 3537 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3538 PCDIMMDevice *dimm = PC_DIMM(dev); 3539 Error *local_err = NULL; 3540 uint64_t size; 3541 Object *memdev; 3542 hwaddr pagesize; 3543 3544 if (!smc->dr_lmb_enabled) { 3545 error_setg(errp, "Memory hotplug not supported for this machine"); 3546 return; 3547 } 3548 3549 if (is_nvdimm && !mc->nvdimm_supported) { 3550 error_setg(errp, "NVDIMM hotplug not supported for this machine"); 3551 return; 3552 } 3553 3554 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3555 if (local_err) { 3556 error_propagate(errp, local_err); 3557 return; 3558 } 3559 3560 if (!is_nvdimm && size % SPAPR_MEMORY_BLOCK_SIZE) { 3561 error_setg(errp, "Hotplugged memory size must be a multiple of " 3562 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3563 return; 3564 } else if (is_nvdimm) { 3565 spapr_nvdimm_validate_opts(NVDIMM(dev), size, &local_err); 3566 if (local_err) { 3567 error_propagate(errp, local_err); 3568 return; 3569 } 3570 } 3571 3572 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3573 &error_abort); 3574 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3575 spapr_check_pagesize(spapr, pagesize, &local_err); 3576 if (local_err) { 3577 error_propagate(errp, local_err); 3578 return; 3579 } 3580 3581 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3582 } 3583 3584 struct SpaprDimmState { 3585 PCDIMMDevice *dimm; 3586 uint32_t nr_lmbs; 3587 QTAILQ_ENTRY(SpaprDimmState) next; 3588 }; 3589 3590 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3591 PCDIMMDevice *dimm) 3592 { 3593 SpaprDimmState *dimm_state = NULL; 3594 3595 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3596 if (dimm_state->dimm == dimm) { 3597 break; 3598 } 3599 } 3600 return dimm_state; 3601 } 3602 3603 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3604 uint32_t nr_lmbs, 3605 PCDIMMDevice *dimm) 3606 { 3607 SpaprDimmState *ds = NULL; 3608 3609 /* 3610 * If this request is for a DIMM whose removal had failed earlier 3611 * (due to guest's refusal to remove the LMBs), we would have this 3612 * dimm already in the pending_dimm_unplugs list. In that 3613 * case don't add again. 3614 */ 3615 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3616 if (!ds) { 3617 ds = g_malloc0(sizeof(SpaprDimmState)); 3618 ds->nr_lmbs = nr_lmbs; 3619 ds->dimm = dimm; 3620 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3621 } 3622 return ds; 3623 } 3624 3625 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3626 SpaprDimmState *dimm_state) 3627 { 3628 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3629 g_free(dimm_state); 3630 } 3631 3632 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3633 PCDIMMDevice *dimm) 3634 { 3635 SpaprDrc *drc; 3636 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3637 &error_abort); 3638 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3639 uint32_t avail_lmbs = 0; 3640 uint64_t addr_start, addr; 3641 int i; 3642 3643 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3644 &error_abort); 3645 3646 addr = addr_start; 3647 for (i = 0; i < nr_lmbs; i++) { 3648 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3649 addr / SPAPR_MEMORY_BLOCK_SIZE); 3650 g_assert(drc); 3651 if (drc->dev) { 3652 avail_lmbs++; 3653 } 3654 addr += SPAPR_MEMORY_BLOCK_SIZE; 3655 } 3656 3657 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3658 } 3659 3660 /* Callback to be called during DRC release. */ 3661 void spapr_lmb_release(DeviceState *dev) 3662 { 3663 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3664 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3665 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3666 3667 /* This information will get lost if a migration occurs 3668 * during the unplug process. In this case recover it. */ 3669 if (ds == NULL) { 3670 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3671 g_assert(ds); 3672 /* The DRC being examined by the caller at least must be counted */ 3673 g_assert(ds->nr_lmbs); 3674 } 3675 3676 if (--ds->nr_lmbs) { 3677 return; 3678 } 3679 3680 /* 3681 * Now that all the LMBs have been removed by the guest, call the 3682 * unplug handler chain. This can never fail. 3683 */ 3684 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3685 object_unparent(OBJECT(dev)); 3686 } 3687 3688 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3689 { 3690 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3691 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3692 3693 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3694 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3695 spapr_pending_dimm_unplugs_remove(spapr, ds); 3696 } 3697 3698 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3699 DeviceState *dev, Error **errp) 3700 { 3701 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3702 Error *local_err = NULL; 3703 PCDIMMDevice *dimm = PC_DIMM(dev); 3704 uint32_t nr_lmbs; 3705 uint64_t size, addr_start, addr; 3706 int i; 3707 SpaprDrc *drc; 3708 3709 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3710 error_setg(&local_err, 3711 "nvdimm device hot unplug is not supported yet."); 3712 goto out; 3713 } 3714 3715 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3716 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3717 3718 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3719 &local_err); 3720 if (local_err) { 3721 goto out; 3722 } 3723 3724 /* 3725 * An existing pending dimm state for this DIMM means that there is an 3726 * unplug operation in progress, waiting for the spapr_lmb_release 3727 * callback to complete the job (BQL can't cover that far). In this case, 3728 * bail out to avoid detaching DRCs that were already released. 3729 */ 3730 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3731 error_setg(&local_err, 3732 "Memory unplug already in progress for device %s", 3733 dev->id); 3734 goto out; 3735 } 3736 3737 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3738 3739 addr = addr_start; 3740 for (i = 0; i < nr_lmbs; i++) { 3741 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3742 addr / SPAPR_MEMORY_BLOCK_SIZE); 3743 g_assert(drc); 3744 3745 spapr_drc_detach(drc); 3746 addr += SPAPR_MEMORY_BLOCK_SIZE; 3747 } 3748 3749 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3750 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3751 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3752 nr_lmbs, spapr_drc_index(drc)); 3753 out: 3754 error_propagate(errp, local_err); 3755 } 3756 3757 /* Callback to be called during DRC release. */ 3758 void spapr_core_release(DeviceState *dev) 3759 { 3760 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3761 3762 /* Call the unplug handler chain. This can never fail. */ 3763 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3764 object_unparent(OBJECT(dev)); 3765 } 3766 3767 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3768 { 3769 MachineState *ms = MACHINE(hotplug_dev); 3770 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3771 CPUCore *cc = CPU_CORE(dev); 3772 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3773 3774 if (smc->pre_2_10_has_unused_icps) { 3775 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3776 int i; 3777 3778 for (i = 0; i < cc->nr_threads; i++) { 3779 CPUState *cs = CPU(sc->threads[i]); 3780 3781 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3782 } 3783 } 3784 3785 assert(core_slot); 3786 core_slot->cpu = NULL; 3787 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3788 } 3789 3790 static 3791 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3792 Error **errp) 3793 { 3794 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3795 int index; 3796 SpaprDrc *drc; 3797 CPUCore *cc = CPU_CORE(dev); 3798 3799 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3800 error_setg(errp, "Unable to find CPU core with core-id: %d", 3801 cc->core_id); 3802 return; 3803 } 3804 if (index == 0) { 3805 error_setg(errp, "Boot CPU core may not be unplugged"); 3806 return; 3807 } 3808 3809 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3810 spapr_vcpu_id(spapr, cc->core_id)); 3811 g_assert(drc); 3812 3813 if (!spapr_drc_unplug_requested(drc)) { 3814 spapr_drc_detach(drc); 3815 spapr_hotplug_req_remove_by_index(drc); 3816 } 3817 } 3818 3819 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3820 void *fdt, int *fdt_start_offset, Error **errp) 3821 { 3822 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3823 CPUState *cs = CPU(core->threads[0]); 3824 PowerPCCPU *cpu = POWERPC_CPU(cs); 3825 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3826 int id = spapr_get_vcpu_id(cpu); 3827 char *nodename; 3828 int offset; 3829 3830 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3831 offset = fdt_add_subnode(fdt, 0, nodename); 3832 g_free(nodename); 3833 3834 spapr_dt_cpu(cs, fdt, offset, spapr); 3835 3836 *fdt_start_offset = offset; 3837 return 0; 3838 } 3839 3840 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3841 Error **errp) 3842 { 3843 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3844 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3845 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3846 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3847 CPUCore *cc = CPU_CORE(dev); 3848 CPUState *cs; 3849 SpaprDrc *drc; 3850 Error *local_err = NULL; 3851 CPUArchId *core_slot; 3852 int index; 3853 bool hotplugged = spapr_drc_hotplugged(dev); 3854 int i; 3855 3856 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3857 if (!core_slot) { 3858 error_setg(errp, "Unable to find CPU core with core-id: %d", 3859 cc->core_id); 3860 return; 3861 } 3862 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3863 spapr_vcpu_id(spapr, cc->core_id)); 3864 3865 g_assert(drc || !mc->has_hotpluggable_cpus); 3866 3867 if (drc) { 3868 spapr_drc_attach(drc, dev, &local_err); 3869 if (local_err) { 3870 error_propagate(errp, local_err); 3871 return; 3872 } 3873 3874 if (hotplugged) { 3875 /* 3876 * Send hotplug notification interrupt to the guest only 3877 * in case of hotplugged CPUs. 3878 */ 3879 spapr_hotplug_req_add_by_index(drc); 3880 } else { 3881 spapr_drc_reset(drc); 3882 } 3883 } 3884 3885 core_slot->cpu = OBJECT(dev); 3886 3887 if (smc->pre_2_10_has_unused_icps) { 3888 for (i = 0; i < cc->nr_threads; i++) { 3889 cs = CPU(core->threads[i]); 3890 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3891 } 3892 } 3893 3894 /* 3895 * Set compatibility mode to match the boot CPU, which was either set 3896 * by the machine reset code or by CAS. 3897 */ 3898 if (hotplugged) { 3899 for (i = 0; i < cc->nr_threads; i++) { 3900 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3901 &local_err); 3902 if (local_err) { 3903 error_propagate(errp, local_err); 3904 return; 3905 } 3906 } 3907 } 3908 } 3909 3910 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3911 Error **errp) 3912 { 3913 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3914 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3915 Error *local_err = NULL; 3916 CPUCore *cc = CPU_CORE(dev); 3917 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3918 const char *type = object_get_typename(OBJECT(dev)); 3919 CPUArchId *core_slot; 3920 int index; 3921 unsigned int smp_threads = machine->smp.threads; 3922 3923 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3924 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3925 goto out; 3926 } 3927 3928 if (strcmp(base_core_type, type)) { 3929 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3930 goto out; 3931 } 3932 3933 if (cc->core_id % smp_threads) { 3934 error_setg(&local_err, "invalid core id %d", cc->core_id); 3935 goto out; 3936 } 3937 3938 /* 3939 * In general we should have homogeneous threads-per-core, but old 3940 * (pre hotplug support) machine types allow the last core to have 3941 * reduced threads as a compatibility hack for when we allowed 3942 * total vcpus not a multiple of threads-per-core. 3943 */ 3944 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3945 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3946 cc->nr_threads, smp_threads); 3947 goto out; 3948 } 3949 3950 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3951 if (!core_slot) { 3952 error_setg(&local_err, "core id %d out of range", cc->core_id); 3953 goto out; 3954 } 3955 3956 if (core_slot->cpu) { 3957 error_setg(&local_err, "core %d already populated", cc->core_id); 3958 goto out; 3959 } 3960 3961 numa_cpu_pre_plug(core_slot, dev, &local_err); 3962 3963 out: 3964 error_propagate(errp, local_err); 3965 } 3966 3967 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3968 void *fdt, int *fdt_start_offset, Error **errp) 3969 { 3970 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3971 int intc_phandle; 3972 3973 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3974 if (intc_phandle <= 0) { 3975 return -1; 3976 } 3977 3978 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3979 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3980 return -1; 3981 } 3982 3983 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3984 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3985 3986 return 0; 3987 } 3988 3989 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3990 Error **errp) 3991 { 3992 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3993 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3994 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3995 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3996 3997 if (dev->hotplugged && !smc->dr_phb_enabled) { 3998 error_setg(errp, "PHB hotplug not supported for this machine"); 3999 return; 4000 } 4001 4002 if (sphb->index == (uint32_t)-1) { 4003 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 4004 return; 4005 } 4006 4007 /* 4008 * This will check that sphb->index doesn't exceed the maximum number of 4009 * PHBs for the current machine type. 4010 */ 4011 smc->phb_placement(spapr, sphb->index, 4012 &sphb->buid, &sphb->io_win_addr, 4013 &sphb->mem_win_addr, &sphb->mem64_win_addr, 4014 windows_supported, sphb->dma_liobn, 4015 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 4016 errp); 4017 } 4018 4019 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4020 Error **errp) 4021 { 4022 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4023 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4024 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4025 SpaprDrc *drc; 4026 bool hotplugged = spapr_drc_hotplugged(dev); 4027 Error *local_err = NULL; 4028 4029 if (!smc->dr_phb_enabled) { 4030 return; 4031 } 4032 4033 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4034 /* hotplug hooks should check it's enabled before getting this far */ 4035 assert(drc); 4036 4037 spapr_drc_attach(drc, DEVICE(dev), &local_err); 4038 if (local_err) { 4039 error_propagate(errp, local_err); 4040 return; 4041 } 4042 4043 if (hotplugged) { 4044 spapr_hotplug_req_add_by_index(drc); 4045 } else { 4046 spapr_drc_reset(drc); 4047 } 4048 } 4049 4050 void spapr_phb_release(DeviceState *dev) 4051 { 4052 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4053 4054 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4055 object_unparent(OBJECT(dev)); 4056 } 4057 4058 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4059 { 4060 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 4061 } 4062 4063 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4064 DeviceState *dev, Error **errp) 4065 { 4066 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4067 SpaprDrc *drc; 4068 4069 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4070 assert(drc); 4071 4072 if (!spapr_drc_unplug_requested(drc)) { 4073 spapr_drc_detach(drc); 4074 spapr_hotplug_req_remove_by_index(drc); 4075 } 4076 } 4077 4078 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4079 Error **errp) 4080 { 4081 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4082 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4083 4084 if (spapr->tpm_proxy != NULL) { 4085 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4086 return; 4087 } 4088 4089 spapr->tpm_proxy = tpm_proxy; 4090 } 4091 4092 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4093 { 4094 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4095 4096 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 4097 object_unparent(OBJECT(dev)); 4098 spapr->tpm_proxy = NULL; 4099 } 4100 4101 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4102 DeviceState *dev, Error **errp) 4103 { 4104 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4105 spapr_memory_plug(hotplug_dev, dev, errp); 4106 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4107 spapr_core_plug(hotplug_dev, dev, errp); 4108 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4109 spapr_phb_plug(hotplug_dev, dev, errp); 4110 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4111 spapr_tpm_proxy_plug(hotplug_dev, dev, errp); 4112 } 4113 } 4114 4115 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4116 DeviceState *dev, Error **errp) 4117 { 4118 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4119 spapr_memory_unplug(hotplug_dev, dev); 4120 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4121 spapr_core_unplug(hotplug_dev, dev); 4122 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4123 spapr_phb_unplug(hotplug_dev, dev); 4124 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4125 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4126 } 4127 } 4128 4129 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4130 DeviceState *dev, Error **errp) 4131 { 4132 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4133 MachineClass *mc = MACHINE_GET_CLASS(sms); 4134 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4135 4136 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4137 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 4138 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4139 } else { 4140 /* NOTE: this means there is a window after guest reset, prior to 4141 * CAS negotiation, where unplug requests will fail due to the 4142 * capability not being detected yet. This is a bit different than 4143 * the case with PCI unplug, where the events will be queued and 4144 * eventually handled by the guest after boot 4145 */ 4146 error_setg(errp, "Memory hot unplug not supported for this guest"); 4147 } 4148 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4149 if (!mc->has_hotpluggable_cpus) { 4150 error_setg(errp, "CPU hot unplug not supported on this machine"); 4151 return; 4152 } 4153 spapr_core_unplug_request(hotplug_dev, dev, errp); 4154 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4155 if (!smc->dr_phb_enabled) { 4156 error_setg(errp, "PHB hot unplug not supported on this machine"); 4157 return; 4158 } 4159 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4160 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4161 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4162 } 4163 } 4164 4165 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4166 DeviceState *dev, Error **errp) 4167 { 4168 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4169 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4170 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4171 spapr_core_pre_plug(hotplug_dev, dev, errp); 4172 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4173 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4174 } 4175 } 4176 4177 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4178 DeviceState *dev) 4179 { 4180 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4181 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4182 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4183 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4184 return HOTPLUG_HANDLER(machine); 4185 } 4186 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4187 PCIDevice *pcidev = PCI_DEVICE(dev); 4188 PCIBus *root = pci_device_root_bus(pcidev); 4189 SpaprPhbState *phb = 4190 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4191 TYPE_SPAPR_PCI_HOST_BRIDGE); 4192 4193 if (phb) { 4194 return HOTPLUG_HANDLER(phb); 4195 } 4196 } 4197 return NULL; 4198 } 4199 4200 static CpuInstanceProperties 4201 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4202 { 4203 CPUArchId *core_slot; 4204 MachineClass *mc = MACHINE_GET_CLASS(machine); 4205 4206 /* make sure possible_cpu are intialized */ 4207 mc->possible_cpu_arch_ids(machine); 4208 /* get CPU core slot containing thread that matches cpu_index */ 4209 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4210 assert(core_slot); 4211 return core_slot->props; 4212 } 4213 4214 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4215 { 4216 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4217 } 4218 4219 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4220 { 4221 int i; 4222 unsigned int smp_threads = machine->smp.threads; 4223 unsigned int smp_cpus = machine->smp.cpus; 4224 const char *core_type; 4225 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4226 MachineClass *mc = MACHINE_GET_CLASS(machine); 4227 4228 if (!mc->has_hotpluggable_cpus) { 4229 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4230 } 4231 if (machine->possible_cpus) { 4232 assert(machine->possible_cpus->len == spapr_max_cores); 4233 return machine->possible_cpus; 4234 } 4235 4236 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4237 if (!core_type) { 4238 error_report("Unable to find sPAPR CPU Core definition"); 4239 exit(1); 4240 } 4241 4242 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4243 sizeof(CPUArchId) * spapr_max_cores); 4244 machine->possible_cpus->len = spapr_max_cores; 4245 for (i = 0; i < machine->possible_cpus->len; i++) { 4246 int core_id = i * smp_threads; 4247 4248 machine->possible_cpus->cpus[i].type = core_type; 4249 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4250 machine->possible_cpus->cpus[i].arch_id = core_id; 4251 machine->possible_cpus->cpus[i].props.has_core_id = true; 4252 machine->possible_cpus->cpus[i].props.core_id = core_id; 4253 } 4254 return machine->possible_cpus; 4255 } 4256 4257 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4258 uint64_t *buid, hwaddr *pio, 4259 hwaddr *mmio32, hwaddr *mmio64, 4260 unsigned n_dma, uint32_t *liobns, 4261 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4262 { 4263 /* 4264 * New-style PHB window placement. 4265 * 4266 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4267 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4268 * windows. 4269 * 4270 * Some guest kernels can't work with MMIO windows above 1<<46 4271 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4272 * 4273 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4274 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4275 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4276 * 1TiB 64-bit MMIO windows for each PHB. 4277 */ 4278 const uint64_t base_buid = 0x800000020000000ULL; 4279 int i; 4280 4281 /* Sanity check natural alignments */ 4282 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4283 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4284 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4285 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4286 /* Sanity check bounds */ 4287 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4288 SPAPR_PCI_MEM32_WIN_SIZE); 4289 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4290 SPAPR_PCI_MEM64_WIN_SIZE); 4291 4292 if (index >= SPAPR_MAX_PHBS) { 4293 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4294 SPAPR_MAX_PHBS - 1); 4295 return; 4296 } 4297 4298 *buid = base_buid + index; 4299 for (i = 0; i < n_dma; ++i) { 4300 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4301 } 4302 4303 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4304 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4305 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4306 4307 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4308 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4309 } 4310 4311 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4312 { 4313 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4314 4315 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4316 } 4317 4318 static void spapr_ics_resend(XICSFabric *dev) 4319 { 4320 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4321 4322 ics_resend(spapr->ics); 4323 } 4324 4325 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4326 { 4327 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4328 4329 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4330 } 4331 4332 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4333 Monitor *mon) 4334 { 4335 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4336 4337 spapr_irq_print_info(spapr, mon); 4338 monitor_printf(mon, "irqchip: %s\n", 4339 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4340 } 4341 4342 /* 4343 * This is a XIVE only operation 4344 */ 4345 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4346 uint8_t nvt_blk, uint32_t nvt_idx, 4347 bool cam_ignore, uint8_t priority, 4348 uint32_t logic_serv, XiveTCTXMatch *match) 4349 { 4350 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4351 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4352 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4353 int count; 4354 4355 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4356 priority, logic_serv, match); 4357 if (count < 0) { 4358 return count; 4359 } 4360 4361 /* 4362 * When we implement the save and restore of the thread interrupt 4363 * contexts in the enter/exit CPU handlers of the machine and the 4364 * escalations in QEMU, we should be able to handle non dispatched 4365 * vCPUs. 4366 * 4367 * Until this is done, the sPAPR machine should find at least one 4368 * matching context always. 4369 */ 4370 if (count == 0) { 4371 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4372 nvt_blk, nvt_idx); 4373 } 4374 4375 return count; 4376 } 4377 4378 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4379 { 4380 return cpu->vcpu_id; 4381 } 4382 4383 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4384 { 4385 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4386 MachineState *ms = MACHINE(spapr); 4387 int vcpu_id; 4388 4389 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4390 4391 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4392 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4393 error_append_hint(errp, "Adjust the number of cpus to %d " 4394 "or try to raise the number of threads per core\n", 4395 vcpu_id * ms->smp.threads / spapr->vsmt); 4396 return; 4397 } 4398 4399 cpu->vcpu_id = vcpu_id; 4400 } 4401 4402 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4403 { 4404 CPUState *cs; 4405 4406 CPU_FOREACH(cs) { 4407 PowerPCCPU *cpu = POWERPC_CPU(cs); 4408 4409 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4410 return cpu; 4411 } 4412 } 4413 4414 return NULL; 4415 } 4416 4417 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4418 { 4419 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4420 4421 /* These are only called by TCG, KVM maintains dispatch state */ 4422 4423 spapr_cpu->prod = false; 4424 if (spapr_cpu->vpa_addr) { 4425 CPUState *cs = CPU(cpu); 4426 uint32_t dispatch; 4427 4428 dispatch = ldl_be_phys(cs->as, 4429 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4430 dispatch++; 4431 if ((dispatch & 1) != 0) { 4432 qemu_log_mask(LOG_GUEST_ERROR, 4433 "VPA: incorrect dispatch counter value for " 4434 "dispatched partition %u, correcting.\n", dispatch); 4435 dispatch++; 4436 } 4437 stl_be_phys(cs->as, 4438 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4439 } 4440 } 4441 4442 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4443 { 4444 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4445 4446 if (spapr_cpu->vpa_addr) { 4447 CPUState *cs = CPU(cpu); 4448 uint32_t dispatch; 4449 4450 dispatch = ldl_be_phys(cs->as, 4451 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4452 dispatch++; 4453 if ((dispatch & 1) != 1) { 4454 qemu_log_mask(LOG_GUEST_ERROR, 4455 "VPA: incorrect dispatch counter value for " 4456 "preempted partition %u, correcting.\n", dispatch); 4457 dispatch++; 4458 } 4459 stl_be_phys(cs->as, 4460 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4461 } 4462 } 4463 4464 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4465 { 4466 MachineClass *mc = MACHINE_CLASS(oc); 4467 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4468 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4469 NMIClass *nc = NMI_CLASS(oc); 4470 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4471 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4472 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4473 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4474 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4475 4476 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4477 mc->ignore_boot_device_suffixes = true; 4478 4479 /* 4480 * We set up the default / latest behaviour here. The class_init 4481 * functions for the specific versioned machine types can override 4482 * these details for backwards compatibility 4483 */ 4484 mc->init = spapr_machine_init; 4485 mc->reset = spapr_machine_reset; 4486 mc->block_default_type = IF_SCSI; 4487 mc->max_cpus = 1024; 4488 mc->no_parallel = 1; 4489 mc->default_boot_order = ""; 4490 mc->default_ram_size = 512 * MiB; 4491 mc->default_ram_id = "ppc_spapr.ram"; 4492 mc->default_display = "std"; 4493 mc->kvm_type = spapr_kvm_type; 4494 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4495 mc->pci_allow_0_address = true; 4496 assert(!mc->get_hotplug_handler); 4497 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4498 hc->pre_plug = spapr_machine_device_pre_plug; 4499 hc->plug = spapr_machine_device_plug; 4500 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4501 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4502 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4503 hc->unplug_request = spapr_machine_device_unplug_request; 4504 hc->unplug = spapr_machine_device_unplug; 4505 4506 smc->dr_lmb_enabled = true; 4507 smc->update_dt_enabled = true; 4508 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4509 mc->has_hotpluggable_cpus = true; 4510 mc->nvdimm_supported = true; 4511 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4512 fwc->get_dev_path = spapr_get_fw_dev_path; 4513 nc->nmi_monitor_handler = spapr_nmi; 4514 smc->phb_placement = spapr_phb_placement; 4515 vhc->hypercall = emulate_spapr_hypercall; 4516 vhc->hpt_mask = spapr_hpt_mask; 4517 vhc->map_hptes = spapr_map_hptes; 4518 vhc->unmap_hptes = spapr_unmap_hptes; 4519 vhc->hpte_set_c = spapr_hpte_set_c; 4520 vhc->hpte_set_r = spapr_hpte_set_r; 4521 vhc->get_pate = spapr_get_pate; 4522 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4523 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4524 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4525 xic->ics_get = spapr_ics_get; 4526 xic->ics_resend = spapr_ics_resend; 4527 xic->icp_get = spapr_icp_get; 4528 ispc->print_info = spapr_pic_print_info; 4529 /* Force NUMA node memory size to be a multiple of 4530 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4531 * in which LMBs are represented and hot-added 4532 */ 4533 mc->numa_mem_align_shift = 28; 4534 mc->numa_mem_supported = true; 4535 mc->auto_enable_numa = true; 4536 4537 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4538 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4539 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4540 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4541 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4542 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4543 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4544 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4545 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4546 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4547 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4548 spapr_caps_add_properties(smc, &error_abort); 4549 smc->irq = &spapr_irq_dual; 4550 smc->dr_phb_enabled = true; 4551 smc->linux_pci_probe = true; 4552 smc->smp_threads_vsmt = true; 4553 smc->nr_xirqs = SPAPR_NR_XIRQS; 4554 xfc->match_nvt = spapr_match_nvt; 4555 } 4556 4557 static const TypeInfo spapr_machine_info = { 4558 .name = TYPE_SPAPR_MACHINE, 4559 .parent = TYPE_MACHINE, 4560 .abstract = true, 4561 .instance_size = sizeof(SpaprMachineState), 4562 .instance_init = spapr_instance_init, 4563 .instance_finalize = spapr_machine_finalizefn, 4564 .class_size = sizeof(SpaprMachineClass), 4565 .class_init = spapr_machine_class_init, 4566 .interfaces = (InterfaceInfo[]) { 4567 { TYPE_FW_PATH_PROVIDER }, 4568 { TYPE_NMI }, 4569 { TYPE_HOTPLUG_HANDLER }, 4570 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4571 { TYPE_XICS_FABRIC }, 4572 { TYPE_INTERRUPT_STATS_PROVIDER }, 4573 { TYPE_XIVE_FABRIC }, 4574 { } 4575 }, 4576 }; 4577 4578 static void spapr_machine_latest_class_options(MachineClass *mc) 4579 { 4580 mc->alias = "pseries"; 4581 mc->is_default = true; 4582 } 4583 4584 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4585 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4586 void *data) \ 4587 { \ 4588 MachineClass *mc = MACHINE_CLASS(oc); \ 4589 spapr_machine_##suffix##_class_options(mc); \ 4590 if (latest) { \ 4591 spapr_machine_latest_class_options(mc); \ 4592 } \ 4593 } \ 4594 static const TypeInfo spapr_machine_##suffix##_info = { \ 4595 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4596 .parent = TYPE_SPAPR_MACHINE, \ 4597 .class_init = spapr_machine_##suffix##_class_init, \ 4598 }; \ 4599 static void spapr_machine_register_##suffix(void) \ 4600 { \ 4601 type_register(&spapr_machine_##suffix##_info); \ 4602 } \ 4603 type_init(spapr_machine_register_##suffix) 4604 4605 /* 4606 * pseries-5.0 4607 */ 4608 static void spapr_machine_5_0_class_options(MachineClass *mc) 4609 { 4610 /* Defaults for the latest behaviour inherited from the base class */ 4611 } 4612 4613 DEFINE_SPAPR_MACHINE(5_0, "5.0", true); 4614 4615 /* 4616 * pseries-4.2 4617 */ 4618 static void spapr_machine_4_2_class_options(MachineClass *mc) 4619 { 4620 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4621 4622 spapr_machine_5_0_class_options(mc); 4623 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4624 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4625 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4626 smc->rma_limit = 16 * GiB; 4627 mc->nvdimm_supported = false; 4628 } 4629 4630 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4631 4632 /* 4633 * pseries-4.1 4634 */ 4635 static void spapr_machine_4_1_class_options(MachineClass *mc) 4636 { 4637 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4638 static GlobalProperty compat[] = { 4639 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4640 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4641 }; 4642 4643 spapr_machine_4_2_class_options(mc); 4644 smc->linux_pci_probe = false; 4645 smc->smp_threads_vsmt = false; 4646 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4647 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4648 } 4649 4650 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4651 4652 /* 4653 * pseries-4.0 4654 */ 4655 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4656 uint64_t *buid, hwaddr *pio, 4657 hwaddr *mmio32, hwaddr *mmio64, 4658 unsigned n_dma, uint32_t *liobns, 4659 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4660 { 4661 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, 4662 nv2gpa, nv2atsd, errp); 4663 *nv2gpa = 0; 4664 *nv2atsd = 0; 4665 } 4666 4667 static void spapr_machine_4_0_class_options(MachineClass *mc) 4668 { 4669 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4670 4671 spapr_machine_4_1_class_options(mc); 4672 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4673 smc->phb_placement = phb_placement_4_0; 4674 smc->irq = &spapr_irq_xics; 4675 smc->pre_4_1_migration = true; 4676 } 4677 4678 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4679 4680 /* 4681 * pseries-3.1 4682 */ 4683 static void spapr_machine_3_1_class_options(MachineClass *mc) 4684 { 4685 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4686 4687 spapr_machine_4_0_class_options(mc); 4688 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4689 4690 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4691 smc->update_dt_enabled = false; 4692 smc->dr_phb_enabled = false; 4693 smc->broken_host_serial_model = true; 4694 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4695 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4696 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4697 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4698 } 4699 4700 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4701 4702 /* 4703 * pseries-3.0 4704 */ 4705 4706 static void spapr_machine_3_0_class_options(MachineClass *mc) 4707 { 4708 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4709 4710 spapr_machine_3_1_class_options(mc); 4711 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4712 4713 smc->legacy_irq_allocation = true; 4714 smc->nr_xirqs = 0x400; 4715 smc->irq = &spapr_irq_xics_legacy; 4716 } 4717 4718 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4719 4720 /* 4721 * pseries-2.12 4722 */ 4723 static void spapr_machine_2_12_class_options(MachineClass *mc) 4724 { 4725 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4726 static GlobalProperty compat[] = { 4727 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4728 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4729 }; 4730 4731 spapr_machine_3_0_class_options(mc); 4732 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4733 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4734 4735 /* We depend on kvm_enabled() to choose a default value for the 4736 * hpt-max-page-size capability. Of course we can't do it here 4737 * because this is too early and the HW accelerator isn't initialzed 4738 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4739 */ 4740 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4741 } 4742 4743 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4744 4745 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4746 { 4747 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4748 4749 spapr_machine_2_12_class_options(mc); 4750 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4751 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4752 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4753 } 4754 4755 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4756 4757 /* 4758 * pseries-2.11 4759 */ 4760 4761 static void spapr_machine_2_11_class_options(MachineClass *mc) 4762 { 4763 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4764 4765 spapr_machine_2_12_class_options(mc); 4766 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4767 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4768 } 4769 4770 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4771 4772 /* 4773 * pseries-2.10 4774 */ 4775 4776 static void spapr_machine_2_10_class_options(MachineClass *mc) 4777 { 4778 spapr_machine_2_11_class_options(mc); 4779 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4780 } 4781 4782 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4783 4784 /* 4785 * pseries-2.9 4786 */ 4787 4788 static void spapr_machine_2_9_class_options(MachineClass *mc) 4789 { 4790 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4791 static GlobalProperty compat[] = { 4792 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4793 }; 4794 4795 spapr_machine_2_10_class_options(mc); 4796 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4797 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4798 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4799 smc->pre_2_10_has_unused_icps = true; 4800 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4801 } 4802 4803 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4804 4805 /* 4806 * pseries-2.8 4807 */ 4808 4809 static void spapr_machine_2_8_class_options(MachineClass *mc) 4810 { 4811 static GlobalProperty compat[] = { 4812 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4813 }; 4814 4815 spapr_machine_2_9_class_options(mc); 4816 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4817 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4818 mc->numa_mem_align_shift = 23; 4819 } 4820 4821 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4822 4823 /* 4824 * pseries-2.7 4825 */ 4826 4827 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4828 uint64_t *buid, hwaddr *pio, 4829 hwaddr *mmio32, hwaddr *mmio64, 4830 unsigned n_dma, uint32_t *liobns, 4831 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4832 { 4833 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4834 const uint64_t base_buid = 0x800000020000000ULL; 4835 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4836 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4837 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4838 const uint32_t max_index = 255; 4839 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4840 4841 uint64_t ram_top = MACHINE(spapr)->ram_size; 4842 hwaddr phb0_base, phb_base; 4843 int i; 4844 4845 /* Do we have device memory? */ 4846 if (MACHINE(spapr)->maxram_size > ram_top) { 4847 /* Can't just use maxram_size, because there may be an 4848 * alignment gap between normal and device memory regions 4849 */ 4850 ram_top = MACHINE(spapr)->device_memory->base + 4851 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4852 } 4853 4854 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4855 4856 if (index > max_index) { 4857 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4858 max_index); 4859 return; 4860 } 4861 4862 *buid = base_buid + index; 4863 for (i = 0; i < n_dma; ++i) { 4864 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4865 } 4866 4867 phb_base = phb0_base + index * phb_spacing; 4868 *pio = phb_base + pio_offset; 4869 *mmio32 = phb_base + mmio_offset; 4870 /* 4871 * We don't set the 64-bit MMIO window, relying on the PHB's 4872 * fallback behaviour of automatically splitting a large "32-bit" 4873 * window into contiguous 32-bit and 64-bit windows 4874 */ 4875 4876 *nv2gpa = 0; 4877 *nv2atsd = 0; 4878 } 4879 4880 static void spapr_machine_2_7_class_options(MachineClass *mc) 4881 { 4882 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4883 static GlobalProperty compat[] = { 4884 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4885 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4886 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4887 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4888 }; 4889 4890 spapr_machine_2_8_class_options(mc); 4891 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4892 mc->default_machine_opts = "modern-hotplug-events=off"; 4893 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4894 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4895 smc->phb_placement = phb_placement_2_7; 4896 } 4897 4898 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4899 4900 /* 4901 * pseries-2.6 4902 */ 4903 4904 static void spapr_machine_2_6_class_options(MachineClass *mc) 4905 { 4906 static GlobalProperty compat[] = { 4907 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4908 }; 4909 4910 spapr_machine_2_7_class_options(mc); 4911 mc->has_hotpluggable_cpus = false; 4912 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4913 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4914 } 4915 4916 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4917 4918 /* 4919 * pseries-2.5 4920 */ 4921 4922 static void spapr_machine_2_5_class_options(MachineClass *mc) 4923 { 4924 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4925 static GlobalProperty compat[] = { 4926 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4927 }; 4928 4929 spapr_machine_2_6_class_options(mc); 4930 smc->use_ohci_by_default = true; 4931 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4932 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4933 } 4934 4935 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4936 4937 /* 4938 * pseries-2.4 4939 */ 4940 4941 static void spapr_machine_2_4_class_options(MachineClass *mc) 4942 { 4943 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4944 4945 spapr_machine_2_5_class_options(mc); 4946 smc->dr_lmb_enabled = false; 4947 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4948 } 4949 4950 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4951 4952 /* 4953 * pseries-2.3 4954 */ 4955 4956 static void spapr_machine_2_3_class_options(MachineClass *mc) 4957 { 4958 static GlobalProperty compat[] = { 4959 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4960 }; 4961 spapr_machine_2_4_class_options(mc); 4962 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4963 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4964 } 4965 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4966 4967 /* 4968 * pseries-2.2 4969 */ 4970 4971 static void spapr_machine_2_2_class_options(MachineClass *mc) 4972 { 4973 static GlobalProperty compat[] = { 4974 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4975 }; 4976 4977 spapr_machine_2_3_class_options(mc); 4978 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4979 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4980 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4981 } 4982 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4983 4984 /* 4985 * pseries-2.1 4986 */ 4987 4988 static void spapr_machine_2_1_class_options(MachineClass *mc) 4989 { 4990 spapr_machine_2_2_class_options(mc); 4991 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4992 } 4993 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4994 4995 static void spapr_machine_register_types(void) 4996 { 4997 type_register_static(&spapr_machine_info); 4998 } 4999 5000 type_init(spapr_machine_register_types) 5001