1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qapi/error.h" 30 #include "qapi/visitor.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/hostmem.h" 33 #include "sysemu/numa.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/runstate.h" 37 #include "qemu/log.h" 38 #include "hw/fw-path-provider.h" 39 #include "elf.h" 40 #include "net/net.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/cpus.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_ppc.h" 45 #include "migration/misc.h" 46 #include "migration/qemu-file-types.h" 47 #include "migration/global_state.h" 48 #include "migration/register.h" 49 #include "migration/blocker.h" 50 #include "mmu-hash64.h" 51 #include "mmu-book3s-v3.h" 52 #include "cpu-models.h" 53 #include "hw/core/cpu.h" 54 55 #include "hw/boards.h" 56 #include "hw/ppc/ppc.h" 57 #include "hw/loader.h" 58 59 #include "hw/ppc/fdt.h" 60 #include "hw/ppc/spapr.h" 61 #include "hw/ppc/spapr_vio.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/pci-host/spapr.h" 64 #include "hw/pci/msi.h" 65 66 #include "hw/pci/pci.h" 67 #include "hw/scsi/scsi.h" 68 #include "hw/virtio/virtio-scsi.h" 69 #include "hw/virtio/vhost-scsi-common.h" 70 71 #include "exec/address-spaces.h" 72 #include "exec/ram_addr.h" 73 #include "hw/usb.h" 74 #include "qemu/config-file.h" 75 #include "qemu/error-report.h" 76 #include "trace.h" 77 #include "hw/nmi.h" 78 #include "hw/intc/intc.h" 79 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 #include "hw/ppc/spapr_nvdimm.h" 84 #include "hw/ppc/spapr_numa.h" 85 86 #include "monitor/monitor.h" 87 88 #include <libfdt.h> 89 90 /* SLOF memory layout: 91 * 92 * SLOF raw image loaded at 0, copies its romfs right below the flat 93 * device-tree, then position SLOF itself 31M below that 94 * 95 * So we set FW_OVERHEAD to 40MB which should account for all of that 96 * and more 97 * 98 * We load our kernel at 4M, leaving space for SLOF initial image 99 */ 100 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 101 #define FW_MAX_SIZE 0x400000 102 #define FW_FILE_NAME "slof.bin" 103 #define FW_OVERHEAD 0x2800000 104 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 105 106 #define MIN_RMA_SLOF (128 * MiB) 107 108 #define PHANDLE_INTC 0x00001111 109 110 /* These two functions implement the VCPU id numbering: one to compute them 111 * all and one to identify thread 0 of a VCORE. Any change to the first one 112 * is likely to have an impact on the second one, so let's keep them close. 113 */ 114 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 115 { 116 MachineState *ms = MACHINE(spapr); 117 unsigned int smp_threads = ms->smp.threads; 118 119 assert(spapr->vsmt); 120 return 121 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 122 } 123 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 124 PowerPCCPU *cpu) 125 { 126 assert(spapr->vsmt); 127 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 128 } 129 130 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 131 { 132 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 133 * and newer QEMUs don't even have them. In both cases, we don't want 134 * to send anything on the wire. 135 */ 136 return false; 137 } 138 139 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 140 .name = "icp/server", 141 .version_id = 1, 142 .minimum_version_id = 1, 143 .needed = pre_2_10_vmstate_dummy_icp_needed, 144 .fields = (VMStateField[]) { 145 VMSTATE_UNUSED(4), /* uint32_t xirr */ 146 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 147 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 148 VMSTATE_END_OF_LIST() 149 }, 150 }; 151 152 static void pre_2_10_vmstate_register_dummy_icp(int i) 153 { 154 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 155 (void *)(uintptr_t) i); 156 } 157 158 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 159 { 160 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 161 (void *)(uintptr_t) i); 162 } 163 164 int spapr_max_server_number(SpaprMachineState *spapr) 165 { 166 MachineState *ms = MACHINE(spapr); 167 168 assert(spapr->vsmt); 169 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 170 } 171 172 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 173 int smt_threads) 174 { 175 int i, ret = 0; 176 uint32_t servers_prop[smt_threads]; 177 uint32_t gservers_prop[smt_threads * 2]; 178 int index = spapr_get_vcpu_id(cpu); 179 180 if (cpu->compat_pvr) { 181 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 182 if (ret < 0) { 183 return ret; 184 } 185 } 186 187 /* Build interrupt servers and gservers properties */ 188 for (i = 0; i < smt_threads; i++) { 189 servers_prop[i] = cpu_to_be32(index + i); 190 /* Hack, direct the group queues back to cpu 0 */ 191 gservers_prop[i*2] = cpu_to_be32(index + i); 192 gservers_prop[i*2 + 1] = 0; 193 } 194 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 195 servers_prop, sizeof(servers_prop)); 196 if (ret < 0) { 197 return ret; 198 } 199 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 200 gservers_prop, sizeof(gservers_prop)); 201 202 return ret; 203 } 204 205 static void spapr_dt_pa_features(SpaprMachineState *spapr, 206 PowerPCCPU *cpu, 207 void *fdt, int offset) 208 { 209 uint8_t pa_features_206[] = { 6, 0, 210 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 211 uint8_t pa_features_207[] = { 24, 0, 212 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 213 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 214 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 215 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 216 uint8_t pa_features_300[] = { 66, 0, 217 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 218 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 219 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 220 /* 6: DS207 */ 221 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 222 /* 16: Vector */ 223 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 224 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 225 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 226 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 227 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 228 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 229 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 230 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 231 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 232 /* 42: PM, 44: PC RA, 46: SC vec'd */ 233 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 234 /* 48: SIMD, 50: QP BFP, 52: String */ 235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 236 /* 54: DecFP, 56: DecI, 58: SHA */ 237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 238 /* 60: NM atomic, 62: RNG */ 239 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 240 }; 241 uint8_t *pa_features = NULL; 242 size_t pa_size; 243 244 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 245 pa_features = pa_features_206; 246 pa_size = sizeof(pa_features_206); 247 } 248 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 249 pa_features = pa_features_207; 250 pa_size = sizeof(pa_features_207); 251 } 252 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 253 pa_features = pa_features_300; 254 pa_size = sizeof(pa_features_300); 255 } 256 if (!pa_features) { 257 return; 258 } 259 260 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 261 /* 262 * Note: we keep CI large pages off by default because a 64K capable 263 * guest provisioned with large pages might otherwise try to map a qemu 264 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 265 * even if that qemu runs on a 4k host. 266 * We dd this bit back here if we are confident this is not an issue 267 */ 268 pa_features[3] |= 0x20; 269 } 270 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 271 pa_features[24] |= 0x80; /* Transactional memory support */ 272 } 273 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 274 /* Workaround for broken kernels that attempt (guest) radix 275 * mode when they can't handle it, if they see the radix bit set 276 * in pa-features. So hide it from them. */ 277 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 278 } 279 280 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 281 } 282 283 static hwaddr spapr_node0_size(MachineState *machine) 284 { 285 if (machine->numa_state->num_nodes) { 286 int i; 287 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 288 if (machine->numa_state->nodes[i].node_mem) { 289 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 290 machine->ram_size); 291 } 292 } 293 } 294 return machine->ram_size; 295 } 296 297 static void add_str(GString *s, const gchar *s1) 298 { 299 g_string_append_len(s, s1, strlen(s1) + 1); 300 } 301 302 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 303 hwaddr start, hwaddr size) 304 { 305 char mem_name[32]; 306 uint64_t mem_reg_property[2]; 307 int off; 308 309 mem_reg_property[0] = cpu_to_be64(start); 310 mem_reg_property[1] = cpu_to_be64(size); 311 312 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 313 off = fdt_add_subnode(fdt, 0, mem_name); 314 _FDT(off); 315 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 316 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 317 sizeof(mem_reg_property)))); 318 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 319 return off; 320 } 321 322 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 323 { 324 MemoryDeviceInfoList *info; 325 326 for (info = list; info; info = info->next) { 327 MemoryDeviceInfo *value = info->value; 328 329 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 330 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 331 332 if (addr >= pcdimm_info->addr && 333 addr < (pcdimm_info->addr + pcdimm_info->size)) { 334 return pcdimm_info->node; 335 } 336 } 337 } 338 339 return -1; 340 } 341 342 struct sPAPRDrconfCellV2 { 343 uint32_t seq_lmbs; 344 uint64_t base_addr; 345 uint32_t drc_index; 346 uint32_t aa_index; 347 uint32_t flags; 348 } QEMU_PACKED; 349 350 typedef struct DrconfCellQueue { 351 struct sPAPRDrconfCellV2 cell; 352 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 353 } DrconfCellQueue; 354 355 static DrconfCellQueue * 356 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 357 uint32_t drc_index, uint32_t aa_index, 358 uint32_t flags) 359 { 360 DrconfCellQueue *elem; 361 362 elem = g_malloc0(sizeof(*elem)); 363 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 364 elem->cell.base_addr = cpu_to_be64(base_addr); 365 elem->cell.drc_index = cpu_to_be32(drc_index); 366 elem->cell.aa_index = cpu_to_be32(aa_index); 367 elem->cell.flags = cpu_to_be32(flags); 368 369 return elem; 370 } 371 372 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 373 int offset, MemoryDeviceInfoList *dimms) 374 { 375 MachineState *machine = MACHINE(spapr); 376 uint8_t *int_buf, *cur_index; 377 int ret; 378 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 379 uint64_t addr, cur_addr, size; 380 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 381 uint64_t mem_end = machine->device_memory->base + 382 memory_region_size(&machine->device_memory->mr); 383 uint32_t node, buf_len, nr_entries = 0; 384 SpaprDrc *drc; 385 DrconfCellQueue *elem, *next; 386 MemoryDeviceInfoList *info; 387 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 388 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 389 390 /* Entry to cover RAM and the gap area */ 391 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 392 SPAPR_LMB_FLAGS_RESERVED | 393 SPAPR_LMB_FLAGS_DRC_INVALID); 394 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 395 nr_entries++; 396 397 cur_addr = machine->device_memory->base; 398 for (info = dimms; info; info = info->next) { 399 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 400 401 addr = di->addr; 402 size = di->size; 403 node = di->node; 404 405 /* 406 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 407 * area is marked hotpluggable in the next iteration for the bigger 408 * chunk including the NVDIMM occupied area. 409 */ 410 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 411 continue; 412 413 /* Entry for hot-pluggable area */ 414 if (cur_addr < addr) { 415 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 416 g_assert(drc); 417 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 418 cur_addr, spapr_drc_index(drc), -1, 0); 419 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 420 nr_entries++; 421 } 422 423 /* Entry for DIMM */ 424 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 425 g_assert(drc); 426 elem = spapr_get_drconf_cell(size / lmb_size, addr, 427 spapr_drc_index(drc), node, 428 (SPAPR_LMB_FLAGS_ASSIGNED | 429 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 430 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 431 nr_entries++; 432 cur_addr = addr + size; 433 } 434 435 /* Entry for remaining hotpluggable area */ 436 if (cur_addr < mem_end) { 437 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 438 g_assert(drc); 439 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 440 cur_addr, spapr_drc_index(drc), -1, 0); 441 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 442 nr_entries++; 443 } 444 445 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 446 int_buf = cur_index = g_malloc0(buf_len); 447 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 448 cur_index += sizeof(nr_entries); 449 450 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 451 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 452 cur_index += sizeof(elem->cell); 453 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 454 g_free(elem); 455 } 456 457 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 458 g_free(int_buf); 459 if (ret < 0) { 460 return -1; 461 } 462 return 0; 463 } 464 465 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 466 int offset, MemoryDeviceInfoList *dimms) 467 { 468 MachineState *machine = MACHINE(spapr); 469 int i, ret; 470 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 471 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 472 uint32_t nr_lmbs = (machine->device_memory->base + 473 memory_region_size(&machine->device_memory->mr)) / 474 lmb_size; 475 uint32_t *int_buf, *cur_index, buf_len; 476 477 /* 478 * Allocate enough buffer size to fit in ibm,dynamic-memory 479 */ 480 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 481 cur_index = int_buf = g_malloc0(buf_len); 482 int_buf[0] = cpu_to_be32(nr_lmbs); 483 cur_index++; 484 for (i = 0; i < nr_lmbs; i++) { 485 uint64_t addr = i * lmb_size; 486 uint32_t *dynamic_memory = cur_index; 487 488 if (i >= device_lmb_start) { 489 SpaprDrc *drc; 490 491 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 492 g_assert(drc); 493 494 dynamic_memory[0] = cpu_to_be32(addr >> 32); 495 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 496 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 497 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 498 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 499 if (memory_region_present(get_system_memory(), addr)) { 500 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 501 } else { 502 dynamic_memory[5] = cpu_to_be32(0); 503 } 504 } else { 505 /* 506 * LMB information for RMA, boot time RAM and gap b/n RAM and 507 * device memory region -- all these are marked as reserved 508 * and as having no valid DRC. 509 */ 510 dynamic_memory[0] = cpu_to_be32(addr >> 32); 511 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 512 dynamic_memory[2] = cpu_to_be32(0); 513 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 514 dynamic_memory[4] = cpu_to_be32(-1); 515 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 516 SPAPR_LMB_FLAGS_DRC_INVALID); 517 } 518 519 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 520 } 521 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 522 g_free(int_buf); 523 if (ret < 0) { 524 return -1; 525 } 526 return 0; 527 } 528 529 /* 530 * Adds ibm,dynamic-reconfiguration-memory node. 531 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 532 * of this device tree node. 533 */ 534 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 535 void *fdt) 536 { 537 MachineState *machine = MACHINE(spapr); 538 int nb_numa_nodes = machine->numa_state->num_nodes; 539 int ret, i, offset; 540 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 541 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 542 cpu_to_be32(lmb_size & 0xffffffff)}; 543 uint32_t *int_buf, *cur_index, buf_len; 544 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 545 MemoryDeviceInfoList *dimms = NULL; 546 547 /* 548 * Don't create the node if there is no device memory 549 */ 550 if (machine->ram_size == machine->maxram_size) { 551 return 0; 552 } 553 554 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 555 556 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 557 sizeof(prop_lmb_size)); 558 if (ret < 0) { 559 return ret; 560 } 561 562 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 563 if (ret < 0) { 564 return ret; 565 } 566 567 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 568 if (ret < 0) { 569 return ret; 570 } 571 572 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 573 dimms = qmp_memory_device_list(); 574 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 575 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 576 } else { 577 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 578 } 579 qapi_free_MemoryDeviceInfoList(dimms); 580 581 if (ret < 0) { 582 return ret; 583 } 584 585 /* ibm,associativity-lookup-arrays */ 586 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 587 cur_index = int_buf = g_malloc0(buf_len); 588 int_buf[0] = cpu_to_be32(nr_nodes); 589 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 590 cur_index += 2; 591 for (i = 0; i < nr_nodes; i++) { 592 uint32_t associativity[] = { 593 cpu_to_be32(0x0), 594 cpu_to_be32(0x0), 595 cpu_to_be32(0x0), 596 cpu_to_be32(i) 597 }; 598 memcpy(cur_index, associativity, sizeof(associativity)); 599 cur_index += 4; 600 } 601 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 602 (cur_index - int_buf) * sizeof(uint32_t)); 603 g_free(int_buf); 604 605 return ret; 606 } 607 608 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 609 { 610 MachineState *machine = MACHINE(spapr); 611 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 612 hwaddr mem_start, node_size; 613 int i, nb_nodes = machine->numa_state->num_nodes; 614 NodeInfo *nodes = machine->numa_state->nodes; 615 616 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 617 if (!nodes[i].node_mem) { 618 continue; 619 } 620 if (mem_start >= machine->ram_size) { 621 node_size = 0; 622 } else { 623 node_size = nodes[i].node_mem; 624 if (node_size > machine->ram_size - mem_start) { 625 node_size = machine->ram_size - mem_start; 626 } 627 } 628 if (!mem_start) { 629 /* spapr_machine_init() checks for rma_size <= node0_size 630 * already */ 631 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 632 mem_start += spapr->rma_size; 633 node_size -= spapr->rma_size; 634 } 635 for ( ; node_size; ) { 636 hwaddr sizetmp = pow2floor(node_size); 637 638 /* mem_start != 0 here */ 639 if (ctzl(mem_start) < ctzl(sizetmp)) { 640 sizetmp = 1ULL << ctzl(mem_start); 641 } 642 643 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 644 node_size -= sizetmp; 645 mem_start += sizetmp; 646 } 647 } 648 649 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 650 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 651 int ret; 652 653 g_assert(smc->dr_lmb_enabled); 654 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 655 if (ret) { 656 return ret; 657 } 658 } 659 660 return 0; 661 } 662 663 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 664 SpaprMachineState *spapr) 665 { 666 MachineState *ms = MACHINE(spapr); 667 PowerPCCPU *cpu = POWERPC_CPU(cs); 668 CPUPPCState *env = &cpu->env; 669 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 670 int index = spapr_get_vcpu_id(cpu); 671 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 672 0xffffffff, 0xffffffff}; 673 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 674 : SPAPR_TIMEBASE_FREQ; 675 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 676 uint32_t page_sizes_prop[64]; 677 size_t page_sizes_prop_size; 678 unsigned int smp_threads = ms->smp.threads; 679 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 680 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 681 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 682 SpaprDrc *drc; 683 int drc_index; 684 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 685 int i; 686 687 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 688 if (drc) { 689 drc_index = spapr_drc_index(drc); 690 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 691 } 692 693 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 694 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 695 696 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 697 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 698 env->dcache_line_size))); 699 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 700 env->dcache_line_size))); 701 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 702 env->icache_line_size))); 703 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 704 env->icache_line_size))); 705 706 if (pcc->l1_dcache_size) { 707 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 708 pcc->l1_dcache_size))); 709 } else { 710 warn_report("Unknown L1 dcache size for cpu"); 711 } 712 if (pcc->l1_icache_size) { 713 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 714 pcc->l1_icache_size))); 715 } else { 716 warn_report("Unknown L1 icache size for cpu"); 717 } 718 719 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 720 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 721 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 722 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 723 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 724 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 725 726 if (env->spr_cb[SPR_PURR].oea_read) { 727 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 728 } 729 if (env->spr_cb[SPR_SPURR].oea_read) { 730 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 731 } 732 733 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 734 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 735 segs, sizeof(segs)))); 736 } 737 738 /* Advertise VSX (vector extensions) if available 739 * 1 == VMX / Altivec available 740 * 2 == VSX available 741 * 742 * Only CPUs for which we create core types in spapr_cpu_core.c 743 * are possible, and all of those have VMX */ 744 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 745 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 746 } else { 747 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 748 } 749 750 /* Advertise DFP (Decimal Floating Point) if available 751 * 0 / no property == no DFP 752 * 1 == DFP available */ 753 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 754 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 755 } 756 757 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 758 sizeof(page_sizes_prop)); 759 if (page_sizes_prop_size) { 760 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 761 page_sizes_prop, page_sizes_prop_size))); 762 } 763 764 spapr_dt_pa_features(spapr, cpu, fdt, offset); 765 766 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 767 cs->cpu_index / vcpus_per_socket))); 768 769 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 770 pft_size_prop, sizeof(pft_size_prop)))); 771 772 if (ms->numa_state->num_nodes > 1) { 773 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 774 } 775 776 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 777 778 if (pcc->radix_page_info) { 779 for (i = 0; i < pcc->radix_page_info->count; i++) { 780 radix_AP_encodings[i] = 781 cpu_to_be32(pcc->radix_page_info->entries[i]); 782 } 783 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 784 radix_AP_encodings, 785 pcc->radix_page_info->count * 786 sizeof(radix_AP_encodings[0])))); 787 } 788 789 /* 790 * We set this property to let the guest know that it can use the large 791 * decrementer and its width in bits. 792 */ 793 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 794 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 795 pcc->lrg_decr_bits))); 796 } 797 798 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 799 { 800 CPUState **rev; 801 CPUState *cs; 802 int n_cpus; 803 int cpus_offset; 804 char *nodename; 805 int i; 806 807 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 808 _FDT(cpus_offset); 809 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 810 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 811 812 /* 813 * We walk the CPUs in reverse order to ensure that CPU DT nodes 814 * created by fdt_add_subnode() end up in the right order in FDT 815 * for the guest kernel the enumerate the CPUs correctly. 816 * 817 * The CPU list cannot be traversed in reverse order, so we need 818 * to do extra work. 819 */ 820 n_cpus = 0; 821 rev = NULL; 822 CPU_FOREACH(cs) { 823 rev = g_renew(CPUState *, rev, n_cpus + 1); 824 rev[n_cpus++] = cs; 825 } 826 827 for (i = n_cpus - 1; i >= 0; i--) { 828 CPUState *cs = rev[i]; 829 PowerPCCPU *cpu = POWERPC_CPU(cs); 830 int index = spapr_get_vcpu_id(cpu); 831 DeviceClass *dc = DEVICE_GET_CLASS(cs); 832 int offset; 833 834 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 835 continue; 836 } 837 838 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 839 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 840 g_free(nodename); 841 _FDT(offset); 842 spapr_dt_cpu(cs, fdt, offset, spapr); 843 } 844 845 g_free(rev); 846 } 847 848 static int spapr_dt_rng(void *fdt) 849 { 850 int node; 851 int ret; 852 853 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 854 if (node <= 0) { 855 return -1; 856 } 857 ret = fdt_setprop_string(fdt, node, "device_type", 858 "ibm,platform-facilities"); 859 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 860 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 861 862 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 863 if (node <= 0) { 864 return -1; 865 } 866 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 867 868 return ret ? -1 : 0; 869 } 870 871 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 872 { 873 MachineState *ms = MACHINE(spapr); 874 int rtas; 875 GString *hypertas = g_string_sized_new(256); 876 GString *qemu_hypertas = g_string_sized_new(256); 877 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 878 memory_region_size(&MACHINE(spapr)->device_memory->mr); 879 uint32_t lrdr_capacity[] = { 880 cpu_to_be32(max_device_addr >> 32), 881 cpu_to_be32(max_device_addr & 0xffffffff), 882 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 883 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 884 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 885 }; 886 887 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 888 889 /* hypertas */ 890 add_str(hypertas, "hcall-pft"); 891 add_str(hypertas, "hcall-term"); 892 add_str(hypertas, "hcall-dabr"); 893 add_str(hypertas, "hcall-interrupt"); 894 add_str(hypertas, "hcall-tce"); 895 add_str(hypertas, "hcall-vio"); 896 add_str(hypertas, "hcall-splpar"); 897 add_str(hypertas, "hcall-join"); 898 add_str(hypertas, "hcall-bulk"); 899 add_str(hypertas, "hcall-set-mode"); 900 add_str(hypertas, "hcall-sprg0"); 901 add_str(hypertas, "hcall-copy"); 902 add_str(hypertas, "hcall-debug"); 903 add_str(hypertas, "hcall-vphn"); 904 add_str(qemu_hypertas, "hcall-memop1"); 905 906 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 907 add_str(hypertas, "hcall-multi-tce"); 908 } 909 910 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 911 add_str(hypertas, "hcall-hpt-resize"); 912 } 913 914 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 915 hypertas->str, hypertas->len)); 916 g_string_free(hypertas, TRUE); 917 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 918 qemu_hypertas->str, qemu_hypertas->len)); 919 g_string_free(qemu_hypertas, TRUE); 920 921 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 922 923 /* 924 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 925 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 926 * 927 * The system reset requirements are driven by existing Linux and PowerVM 928 * implementation which (contrary to PAPR) saves r3 in the error log 929 * structure like machine check, so Linux expects to find the saved r3 930 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 931 * does not look at the error value). 932 * 933 * System reset interrupts are not subject to interlock like machine 934 * check, so this memory area could be corrupted if the sreset is 935 * interrupted by a machine check (or vice versa) if it was shared. To 936 * prevent this, system reset uses per-CPU areas for the sreset save 937 * area. A system reset that interrupts a system reset handler could 938 * still overwrite this area, but Linux doesn't try to recover in that 939 * case anyway. 940 * 941 * The extra 8 bytes is required because Linux's FWNMI error log check 942 * is off-by-one. 943 */ 944 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX + 945 ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t))); 946 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 947 RTAS_ERROR_LOG_MAX)); 948 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 949 RTAS_EVENT_SCAN_RATE)); 950 951 g_assert(msi_nonbroken); 952 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 953 954 /* 955 * According to PAPR, rtas ibm,os-term does not guarantee a return 956 * back to the guest cpu. 957 * 958 * While an additional ibm,extended-os-term property indicates 959 * that rtas call return will always occur. Set this property. 960 */ 961 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 962 963 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 964 lrdr_capacity, sizeof(lrdr_capacity))); 965 966 spapr_dt_rtas_tokens(fdt, rtas); 967 } 968 969 /* 970 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 971 * and the XIVE features that the guest may request and thus the valid 972 * values for bytes 23..26 of option vector 5: 973 */ 974 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 975 int chosen) 976 { 977 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 978 979 char val[2 * 4] = { 980 23, 0x00, /* XICS / XIVE mode */ 981 24, 0x00, /* Hash/Radix, filled in below. */ 982 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 983 26, 0x40, /* Radix options: GTSE == yes. */ 984 }; 985 986 if (spapr->irq->xics && spapr->irq->xive) { 987 val[1] = SPAPR_OV5_XIVE_BOTH; 988 } else if (spapr->irq->xive) { 989 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 990 } else { 991 assert(spapr->irq->xics); 992 val[1] = SPAPR_OV5_XIVE_LEGACY; 993 } 994 995 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 996 first_ppc_cpu->compat_pvr)) { 997 /* 998 * If we're in a pre POWER9 compat mode then the guest should 999 * do hash and use the legacy interrupt mode 1000 */ 1001 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1002 val[3] = 0x00; /* Hash */ 1003 } else if (kvm_enabled()) { 1004 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1005 val[3] = 0x80; /* OV5_MMU_BOTH */ 1006 } else if (kvmppc_has_cap_mmu_radix()) { 1007 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1008 } else { 1009 val[3] = 0x00; /* Hash */ 1010 } 1011 } else { 1012 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1013 val[3] = 0xC0; 1014 } 1015 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1016 val, sizeof(val))); 1017 } 1018 1019 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1020 { 1021 MachineState *machine = MACHINE(spapr); 1022 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1023 int chosen; 1024 1025 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1026 1027 if (reset) { 1028 const char *boot_device = machine->boot_order; 1029 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1030 size_t cb = 0; 1031 char *bootlist = get_boot_devices_list(&cb); 1032 1033 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1034 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1035 machine->kernel_cmdline)); 1036 } 1037 1038 if (spapr->initrd_size) { 1039 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1040 spapr->initrd_base)); 1041 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1042 spapr->initrd_base + spapr->initrd_size)); 1043 } 1044 1045 if (spapr->kernel_size) { 1046 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1047 cpu_to_be64(spapr->kernel_size) }; 1048 1049 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1050 &kprop, sizeof(kprop))); 1051 if (spapr->kernel_le) { 1052 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1053 } 1054 } 1055 if (boot_menu) { 1056 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1057 } 1058 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1059 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1060 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1061 1062 if (cb && bootlist) { 1063 int i; 1064 1065 for (i = 0; i < cb; i++) { 1066 if (bootlist[i] == '\n') { 1067 bootlist[i] = ' '; 1068 } 1069 } 1070 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1071 } 1072 1073 if (boot_device && strlen(boot_device)) { 1074 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1075 } 1076 1077 if (!spapr->has_graphics && stdout_path) { 1078 /* 1079 * "linux,stdout-path" and "stdout" properties are 1080 * deprecated by linux kernel. New platforms should only 1081 * use the "stdout-path" property. Set the new property 1082 * and continue using older property to remain compatible 1083 * with the existing firmware. 1084 */ 1085 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1086 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1087 } 1088 1089 /* 1090 * We can deal with BAR reallocation just fine, advertise it 1091 * to the guest 1092 */ 1093 if (smc->linux_pci_probe) { 1094 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1095 } 1096 1097 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1098 1099 g_free(stdout_path); 1100 g_free(bootlist); 1101 } 1102 1103 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1104 } 1105 1106 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1107 { 1108 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1109 * KVM to work under pHyp with some guest co-operation */ 1110 int hypervisor; 1111 uint8_t hypercall[16]; 1112 1113 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1114 /* indicate KVM hypercall interface */ 1115 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1116 if (kvmppc_has_cap_fixup_hcalls()) { 1117 /* 1118 * Older KVM versions with older guest kernels were broken 1119 * with the magic page, don't allow the guest to map it. 1120 */ 1121 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1122 sizeof(hypercall))) { 1123 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1124 hypercall, sizeof(hypercall))); 1125 } 1126 } 1127 } 1128 1129 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1130 { 1131 MachineState *machine = MACHINE(spapr); 1132 MachineClass *mc = MACHINE_GET_CLASS(machine); 1133 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1134 int ret; 1135 void *fdt; 1136 SpaprPhbState *phb; 1137 char *buf; 1138 1139 fdt = g_malloc0(space); 1140 _FDT((fdt_create_empty_tree(fdt, space))); 1141 1142 /* Root node */ 1143 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1144 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1145 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1146 1147 /* Guest UUID & Name*/ 1148 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1149 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1150 if (qemu_uuid_set) { 1151 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1152 } 1153 g_free(buf); 1154 1155 if (qemu_get_vm_name()) { 1156 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1157 qemu_get_vm_name())); 1158 } 1159 1160 /* Host Model & Serial Number */ 1161 if (spapr->host_model) { 1162 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1163 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1164 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1165 g_free(buf); 1166 } 1167 1168 if (spapr->host_serial) { 1169 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1170 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1171 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1172 g_free(buf); 1173 } 1174 1175 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1176 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1177 1178 /* /interrupt controller */ 1179 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1180 1181 ret = spapr_dt_memory(spapr, fdt); 1182 if (ret < 0) { 1183 error_report("couldn't setup memory nodes in fdt"); 1184 exit(1); 1185 } 1186 1187 /* /vdevice */ 1188 spapr_dt_vdevice(spapr->vio_bus, fdt); 1189 1190 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1191 ret = spapr_dt_rng(fdt); 1192 if (ret < 0) { 1193 error_report("could not set up rng device in the fdt"); 1194 exit(1); 1195 } 1196 } 1197 1198 QLIST_FOREACH(phb, &spapr->phbs, list) { 1199 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1200 if (ret < 0) { 1201 error_report("couldn't setup PCI devices in fdt"); 1202 exit(1); 1203 } 1204 } 1205 1206 spapr_dt_cpus(fdt, spapr); 1207 1208 if (smc->dr_lmb_enabled) { 1209 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1210 } 1211 1212 if (mc->has_hotpluggable_cpus) { 1213 int offset = fdt_path_offset(fdt, "/cpus"); 1214 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1215 if (ret < 0) { 1216 error_report("Couldn't set up CPU DR device tree properties"); 1217 exit(1); 1218 } 1219 } 1220 1221 /* /event-sources */ 1222 spapr_dt_events(spapr, fdt); 1223 1224 /* /rtas */ 1225 spapr_dt_rtas(spapr, fdt); 1226 1227 /* /chosen */ 1228 spapr_dt_chosen(spapr, fdt, reset); 1229 1230 /* /hypervisor */ 1231 if (kvm_enabled()) { 1232 spapr_dt_hypervisor(spapr, fdt); 1233 } 1234 1235 /* Build memory reserve map */ 1236 if (reset) { 1237 if (spapr->kernel_size) { 1238 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1239 spapr->kernel_size))); 1240 } 1241 if (spapr->initrd_size) { 1242 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1243 spapr->initrd_size))); 1244 } 1245 } 1246 1247 if (smc->dr_phb_enabled) { 1248 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); 1249 if (ret < 0) { 1250 error_report("Couldn't set up PHB DR device tree properties"); 1251 exit(1); 1252 } 1253 } 1254 1255 /* NVDIMM devices */ 1256 if (mc->nvdimm_supported) { 1257 spapr_dt_persistent_memory(spapr, fdt); 1258 } 1259 1260 return fdt; 1261 } 1262 1263 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1264 { 1265 SpaprMachineState *spapr = opaque; 1266 1267 return (addr & 0x0fffffff) + spapr->kernel_addr; 1268 } 1269 1270 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1271 PowerPCCPU *cpu) 1272 { 1273 CPUPPCState *env = &cpu->env; 1274 1275 /* The TCG path should also be holding the BQL at this point */ 1276 g_assert(qemu_mutex_iothread_locked()); 1277 1278 if (msr_pr) { 1279 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1280 env->gpr[3] = H_PRIVILEGE; 1281 } else { 1282 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1283 } 1284 } 1285 1286 struct LPCRSyncState { 1287 target_ulong value; 1288 target_ulong mask; 1289 }; 1290 1291 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1292 { 1293 struct LPCRSyncState *s = arg.host_ptr; 1294 PowerPCCPU *cpu = POWERPC_CPU(cs); 1295 CPUPPCState *env = &cpu->env; 1296 target_ulong lpcr; 1297 1298 cpu_synchronize_state(cs); 1299 lpcr = env->spr[SPR_LPCR]; 1300 lpcr &= ~s->mask; 1301 lpcr |= s->value; 1302 ppc_store_lpcr(cpu, lpcr); 1303 } 1304 1305 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1306 { 1307 CPUState *cs; 1308 struct LPCRSyncState s = { 1309 .value = value, 1310 .mask = mask 1311 }; 1312 CPU_FOREACH(cs) { 1313 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1314 } 1315 } 1316 1317 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1318 { 1319 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1320 1321 /* Copy PATE1:GR into PATE0:HR */ 1322 entry->dw0 = spapr->patb_entry & PATE0_HR; 1323 entry->dw1 = spapr->patb_entry; 1324 } 1325 1326 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1327 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1328 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1329 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1330 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1331 1332 /* 1333 * Get the fd to access the kernel htab, re-opening it if necessary 1334 */ 1335 static int get_htab_fd(SpaprMachineState *spapr) 1336 { 1337 Error *local_err = NULL; 1338 1339 if (spapr->htab_fd >= 0) { 1340 return spapr->htab_fd; 1341 } 1342 1343 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1344 if (spapr->htab_fd < 0) { 1345 error_report_err(local_err); 1346 } 1347 1348 return spapr->htab_fd; 1349 } 1350 1351 void close_htab_fd(SpaprMachineState *spapr) 1352 { 1353 if (spapr->htab_fd >= 0) { 1354 close(spapr->htab_fd); 1355 } 1356 spapr->htab_fd = -1; 1357 } 1358 1359 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1360 { 1361 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1362 1363 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1364 } 1365 1366 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1367 { 1368 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1369 1370 assert(kvm_enabled()); 1371 1372 if (!spapr->htab) { 1373 return 0; 1374 } 1375 1376 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1377 } 1378 1379 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1380 hwaddr ptex, int n) 1381 { 1382 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1383 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1384 1385 if (!spapr->htab) { 1386 /* 1387 * HTAB is controlled by KVM. Fetch into temporary buffer 1388 */ 1389 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1390 kvmppc_read_hptes(hptes, ptex, n); 1391 return hptes; 1392 } 1393 1394 /* 1395 * HTAB is controlled by QEMU. Just point to the internally 1396 * accessible PTEG. 1397 */ 1398 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1399 } 1400 1401 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1402 const ppc_hash_pte64_t *hptes, 1403 hwaddr ptex, int n) 1404 { 1405 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1406 1407 if (!spapr->htab) { 1408 g_free((void *)hptes); 1409 } 1410 1411 /* Nothing to do for qemu managed HPT */ 1412 } 1413 1414 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1415 uint64_t pte0, uint64_t pte1) 1416 { 1417 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1418 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1419 1420 if (!spapr->htab) { 1421 kvmppc_write_hpte(ptex, pte0, pte1); 1422 } else { 1423 if (pte0 & HPTE64_V_VALID) { 1424 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1425 /* 1426 * When setting valid, we write PTE1 first. This ensures 1427 * proper synchronization with the reading code in 1428 * ppc_hash64_pteg_search() 1429 */ 1430 smp_wmb(); 1431 stq_p(spapr->htab + offset, pte0); 1432 } else { 1433 stq_p(spapr->htab + offset, pte0); 1434 /* 1435 * When clearing it we set PTE0 first. This ensures proper 1436 * synchronization with the reading code in 1437 * ppc_hash64_pteg_search() 1438 */ 1439 smp_wmb(); 1440 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1441 } 1442 } 1443 } 1444 1445 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1446 uint64_t pte1) 1447 { 1448 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1449 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1450 1451 if (!spapr->htab) { 1452 /* There should always be a hash table when this is called */ 1453 error_report("spapr_hpte_set_c called with no hash table !"); 1454 return; 1455 } 1456 1457 /* The HW performs a non-atomic byte update */ 1458 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1459 } 1460 1461 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1462 uint64_t pte1) 1463 { 1464 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1465 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1466 1467 if (!spapr->htab) { 1468 /* There should always be a hash table when this is called */ 1469 error_report("spapr_hpte_set_r called with no hash table !"); 1470 return; 1471 } 1472 1473 /* The HW performs a non-atomic byte update */ 1474 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1475 } 1476 1477 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1478 { 1479 int shift; 1480 1481 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1482 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1483 * that's much more than is needed for Linux guests */ 1484 shift = ctz64(pow2ceil(ramsize)) - 7; 1485 shift = MAX(shift, 18); /* Minimum architected size */ 1486 shift = MIN(shift, 46); /* Maximum architected size */ 1487 return shift; 1488 } 1489 1490 void spapr_free_hpt(SpaprMachineState *spapr) 1491 { 1492 g_free(spapr->htab); 1493 spapr->htab = NULL; 1494 spapr->htab_shift = 0; 1495 close_htab_fd(spapr); 1496 } 1497 1498 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 1499 Error **errp) 1500 { 1501 long rc; 1502 1503 /* Clean up any HPT info from a previous boot */ 1504 spapr_free_hpt(spapr); 1505 1506 rc = kvmppc_reset_htab(shift); 1507 if (rc < 0) { 1508 /* kernel-side HPT needed, but couldn't allocate one */ 1509 error_setg_errno(errp, errno, 1510 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1511 shift); 1512 /* This is almost certainly fatal, but if the caller really 1513 * wants to carry on with shift == 0, it's welcome to try */ 1514 } else if (rc > 0) { 1515 /* kernel-side HPT allocated */ 1516 if (rc != shift) { 1517 error_setg(errp, 1518 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1519 shift, rc); 1520 } 1521 1522 spapr->htab_shift = shift; 1523 spapr->htab = NULL; 1524 } else { 1525 /* kernel-side HPT not needed, allocate in userspace instead */ 1526 size_t size = 1ULL << shift; 1527 int i; 1528 1529 spapr->htab = qemu_memalign(size, size); 1530 if (!spapr->htab) { 1531 error_setg_errno(errp, errno, 1532 "Could not allocate HPT of order %d", shift); 1533 return; 1534 } 1535 1536 memset(spapr->htab, 0, size); 1537 spapr->htab_shift = shift; 1538 1539 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1540 DIRTY_HPTE(HPTE(spapr->htab, i)); 1541 } 1542 } 1543 /* We're setting up a hash table, so that means we're not radix */ 1544 spapr->patb_entry = 0; 1545 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1546 } 1547 1548 void spapr_setup_hpt(SpaprMachineState *spapr) 1549 { 1550 int hpt_shift; 1551 1552 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1553 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1554 } else { 1555 uint64_t current_ram_size; 1556 1557 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1558 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1559 } 1560 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1561 1562 if (kvm_enabled()) { 1563 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1564 1565 /* Check our RMA fits in the possible VRMA */ 1566 if (vrma_limit < spapr->rma_size) { 1567 error_report("Unable to create %" HWADDR_PRIu 1568 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1569 spapr->rma_size / MiB, vrma_limit / MiB); 1570 exit(EXIT_FAILURE); 1571 } 1572 } 1573 } 1574 1575 static int spapr_reset_drcs(Object *child, void *opaque) 1576 { 1577 SpaprDrc *drc = 1578 (SpaprDrc *) object_dynamic_cast(child, 1579 TYPE_SPAPR_DR_CONNECTOR); 1580 1581 if (drc) { 1582 spapr_drc_reset(drc); 1583 } 1584 1585 return 0; 1586 } 1587 1588 static void spapr_machine_reset(MachineState *machine) 1589 { 1590 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1591 PowerPCCPU *first_ppc_cpu; 1592 hwaddr fdt_addr; 1593 void *fdt; 1594 int rc; 1595 1596 kvmppc_svm_off(&error_fatal); 1597 spapr_caps_apply(spapr); 1598 1599 first_ppc_cpu = POWERPC_CPU(first_cpu); 1600 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1601 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1602 spapr->max_compat_pvr)) { 1603 /* 1604 * If using KVM with radix mode available, VCPUs can be started 1605 * without a HPT because KVM will start them in radix mode. 1606 * Set the GR bit in PATE so that we know there is no HPT. 1607 */ 1608 spapr->patb_entry = PATE1_GR; 1609 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1610 } else { 1611 spapr_setup_hpt(spapr); 1612 } 1613 1614 qemu_devices_reset(); 1615 1616 spapr_ovec_cleanup(spapr->ov5_cas); 1617 spapr->ov5_cas = spapr_ovec_new(); 1618 1619 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1620 1621 /* 1622 * This is fixing some of the default configuration of the XIVE 1623 * devices. To be called after the reset of the machine devices. 1624 */ 1625 spapr_irq_reset(spapr, &error_fatal); 1626 1627 /* 1628 * There is no CAS under qtest. Simulate one to please the code that 1629 * depends on spapr->ov5_cas. This is especially needed to test device 1630 * unplug, so we do that before resetting the DRCs. 1631 */ 1632 if (qtest_enabled()) { 1633 spapr_ovec_cleanup(spapr->ov5_cas); 1634 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1635 } 1636 1637 /* DRC reset may cause a device to be unplugged. This will cause troubles 1638 * if this device is used by another device (eg, a running vhost backend 1639 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1640 * situations, we reset DRCs after all devices have been reset. 1641 */ 1642 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1643 1644 spapr_clear_pending_events(spapr); 1645 1646 /* 1647 * We place the device tree and RTAS just below either the top of the RMA, 1648 * or just below 2GB, whichever is lower, so that it can be 1649 * processed with 32-bit real mode code if necessary 1650 */ 1651 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1652 1653 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1654 1655 rc = fdt_pack(fdt); 1656 1657 /* Should only fail if we've built a corrupted tree */ 1658 assert(rc == 0); 1659 1660 /* Load the fdt */ 1661 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1662 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1663 g_free(spapr->fdt_blob); 1664 spapr->fdt_size = fdt_totalsize(fdt); 1665 spapr->fdt_initial_size = spapr->fdt_size; 1666 spapr->fdt_blob = fdt; 1667 1668 /* Set up the entry state */ 1669 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); 1670 first_ppc_cpu->env.gpr[5] = 0; 1671 1672 spapr->fwnmi_system_reset_addr = -1; 1673 spapr->fwnmi_machine_check_addr = -1; 1674 spapr->fwnmi_machine_check_interlock = -1; 1675 1676 /* Signal all vCPUs waiting on this condition */ 1677 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1678 1679 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1680 } 1681 1682 static void spapr_create_nvram(SpaprMachineState *spapr) 1683 { 1684 DeviceState *dev = qdev_new("spapr-nvram"); 1685 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1686 1687 if (dinfo) { 1688 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1689 &error_fatal); 1690 } 1691 1692 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1693 1694 spapr->nvram = (struct SpaprNvram *)dev; 1695 } 1696 1697 static void spapr_rtc_create(SpaprMachineState *spapr) 1698 { 1699 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1700 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1701 &error_fatal, NULL); 1702 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1703 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1704 "date"); 1705 } 1706 1707 /* Returns whether we want to use VGA or not */ 1708 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1709 { 1710 switch (vga_interface_type) { 1711 case VGA_NONE: 1712 return false; 1713 case VGA_DEVICE: 1714 return true; 1715 case VGA_STD: 1716 case VGA_VIRTIO: 1717 case VGA_CIRRUS: 1718 return pci_vga_init(pci_bus) != NULL; 1719 default: 1720 error_setg(errp, 1721 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1722 return false; 1723 } 1724 } 1725 1726 static int spapr_pre_load(void *opaque) 1727 { 1728 int rc; 1729 1730 rc = spapr_caps_pre_load(opaque); 1731 if (rc) { 1732 return rc; 1733 } 1734 1735 return 0; 1736 } 1737 1738 static int spapr_post_load(void *opaque, int version_id) 1739 { 1740 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1741 int err = 0; 1742 1743 err = spapr_caps_post_migration(spapr); 1744 if (err) { 1745 return err; 1746 } 1747 1748 /* 1749 * In earlier versions, there was no separate qdev for the PAPR 1750 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1751 * So when migrating from those versions, poke the incoming offset 1752 * value into the RTC device 1753 */ 1754 if (version_id < 3) { 1755 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1756 if (err) { 1757 return err; 1758 } 1759 } 1760 1761 if (kvm_enabled() && spapr->patb_entry) { 1762 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1763 bool radix = !!(spapr->patb_entry & PATE1_GR); 1764 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1765 1766 /* 1767 * Update LPCR:HR and UPRT as they may not be set properly in 1768 * the stream 1769 */ 1770 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1771 LPCR_HR | LPCR_UPRT); 1772 1773 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1774 if (err) { 1775 error_report("Process table config unsupported by the host"); 1776 return -EINVAL; 1777 } 1778 } 1779 1780 err = spapr_irq_post_load(spapr, version_id); 1781 if (err) { 1782 return err; 1783 } 1784 1785 return err; 1786 } 1787 1788 static int spapr_pre_save(void *opaque) 1789 { 1790 int rc; 1791 1792 rc = spapr_caps_pre_save(opaque); 1793 if (rc) { 1794 return rc; 1795 } 1796 1797 return 0; 1798 } 1799 1800 static bool version_before_3(void *opaque, int version_id) 1801 { 1802 return version_id < 3; 1803 } 1804 1805 static bool spapr_pending_events_needed(void *opaque) 1806 { 1807 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1808 return !QTAILQ_EMPTY(&spapr->pending_events); 1809 } 1810 1811 static const VMStateDescription vmstate_spapr_event_entry = { 1812 .name = "spapr_event_log_entry", 1813 .version_id = 1, 1814 .minimum_version_id = 1, 1815 .fields = (VMStateField[]) { 1816 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1817 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1818 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1819 NULL, extended_length), 1820 VMSTATE_END_OF_LIST() 1821 }, 1822 }; 1823 1824 static const VMStateDescription vmstate_spapr_pending_events = { 1825 .name = "spapr_pending_events", 1826 .version_id = 1, 1827 .minimum_version_id = 1, 1828 .needed = spapr_pending_events_needed, 1829 .fields = (VMStateField[]) { 1830 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1831 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1832 VMSTATE_END_OF_LIST() 1833 }, 1834 }; 1835 1836 static bool spapr_ov5_cas_needed(void *opaque) 1837 { 1838 SpaprMachineState *spapr = opaque; 1839 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1840 bool cas_needed; 1841 1842 /* Prior to the introduction of SpaprOptionVector, we had two option 1843 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1844 * Both of these options encode machine topology into the device-tree 1845 * in such a way that the now-booted OS should still be able to interact 1846 * appropriately with QEMU regardless of what options were actually 1847 * negotiatied on the source side. 1848 * 1849 * As such, we can avoid migrating the CAS-negotiated options if these 1850 * are the only options available on the current machine/platform. 1851 * Since these are the only options available for pseries-2.7 and 1852 * earlier, this allows us to maintain old->new/new->old migration 1853 * compatibility. 1854 * 1855 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1856 * via default pseries-2.8 machines and explicit command-line parameters. 1857 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1858 * of the actual CAS-negotiated values to continue working properly. For 1859 * example, availability of memory unplug depends on knowing whether 1860 * OV5_HP_EVT was negotiated via CAS. 1861 * 1862 * Thus, for any cases where the set of available CAS-negotiatable 1863 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1864 * include the CAS-negotiated options in the migration stream, unless 1865 * if they affect boot time behaviour only. 1866 */ 1867 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1868 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1869 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1870 1871 /* We need extra information if we have any bits outside the mask 1872 * defined above */ 1873 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1874 1875 spapr_ovec_cleanup(ov5_mask); 1876 1877 return cas_needed; 1878 } 1879 1880 static const VMStateDescription vmstate_spapr_ov5_cas = { 1881 .name = "spapr_option_vector_ov5_cas", 1882 .version_id = 1, 1883 .minimum_version_id = 1, 1884 .needed = spapr_ov5_cas_needed, 1885 .fields = (VMStateField[]) { 1886 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1887 vmstate_spapr_ovec, SpaprOptionVector), 1888 VMSTATE_END_OF_LIST() 1889 }, 1890 }; 1891 1892 static bool spapr_patb_entry_needed(void *opaque) 1893 { 1894 SpaprMachineState *spapr = opaque; 1895 1896 return !!spapr->patb_entry; 1897 } 1898 1899 static const VMStateDescription vmstate_spapr_patb_entry = { 1900 .name = "spapr_patb_entry", 1901 .version_id = 1, 1902 .minimum_version_id = 1, 1903 .needed = spapr_patb_entry_needed, 1904 .fields = (VMStateField[]) { 1905 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1906 VMSTATE_END_OF_LIST() 1907 }, 1908 }; 1909 1910 static bool spapr_irq_map_needed(void *opaque) 1911 { 1912 SpaprMachineState *spapr = opaque; 1913 1914 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1915 } 1916 1917 static const VMStateDescription vmstate_spapr_irq_map = { 1918 .name = "spapr_irq_map", 1919 .version_id = 1, 1920 .minimum_version_id = 1, 1921 .needed = spapr_irq_map_needed, 1922 .fields = (VMStateField[]) { 1923 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1924 VMSTATE_END_OF_LIST() 1925 }, 1926 }; 1927 1928 static bool spapr_dtb_needed(void *opaque) 1929 { 1930 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1931 1932 return smc->update_dt_enabled; 1933 } 1934 1935 static int spapr_dtb_pre_load(void *opaque) 1936 { 1937 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1938 1939 g_free(spapr->fdt_blob); 1940 spapr->fdt_blob = NULL; 1941 spapr->fdt_size = 0; 1942 1943 return 0; 1944 } 1945 1946 static const VMStateDescription vmstate_spapr_dtb = { 1947 .name = "spapr_dtb", 1948 .version_id = 1, 1949 .minimum_version_id = 1, 1950 .needed = spapr_dtb_needed, 1951 .pre_load = spapr_dtb_pre_load, 1952 .fields = (VMStateField[]) { 1953 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1954 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1955 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1956 fdt_size), 1957 VMSTATE_END_OF_LIST() 1958 }, 1959 }; 1960 1961 static bool spapr_fwnmi_needed(void *opaque) 1962 { 1963 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1964 1965 return spapr->fwnmi_machine_check_addr != -1; 1966 } 1967 1968 static int spapr_fwnmi_pre_save(void *opaque) 1969 { 1970 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1971 1972 /* 1973 * Check if machine check handling is in progress and print a 1974 * warning message. 1975 */ 1976 if (spapr->fwnmi_machine_check_interlock != -1) { 1977 warn_report("A machine check is being handled during migration. The" 1978 "handler may run and log hardware error on the destination"); 1979 } 1980 1981 return 0; 1982 } 1983 1984 static const VMStateDescription vmstate_spapr_fwnmi = { 1985 .name = "spapr_fwnmi", 1986 .version_id = 1, 1987 .minimum_version_id = 1, 1988 .needed = spapr_fwnmi_needed, 1989 .pre_save = spapr_fwnmi_pre_save, 1990 .fields = (VMStateField[]) { 1991 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 1992 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 1993 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 1994 VMSTATE_END_OF_LIST() 1995 }, 1996 }; 1997 1998 static const VMStateDescription vmstate_spapr = { 1999 .name = "spapr", 2000 .version_id = 3, 2001 .minimum_version_id = 1, 2002 .pre_load = spapr_pre_load, 2003 .post_load = spapr_post_load, 2004 .pre_save = spapr_pre_save, 2005 .fields = (VMStateField[]) { 2006 /* used to be @next_irq */ 2007 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2008 2009 /* RTC offset */ 2010 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2011 2012 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2013 VMSTATE_END_OF_LIST() 2014 }, 2015 .subsections = (const VMStateDescription*[]) { 2016 &vmstate_spapr_ov5_cas, 2017 &vmstate_spapr_patb_entry, 2018 &vmstate_spapr_pending_events, 2019 &vmstate_spapr_cap_htm, 2020 &vmstate_spapr_cap_vsx, 2021 &vmstate_spapr_cap_dfp, 2022 &vmstate_spapr_cap_cfpc, 2023 &vmstate_spapr_cap_sbbc, 2024 &vmstate_spapr_cap_ibs, 2025 &vmstate_spapr_cap_hpt_maxpagesize, 2026 &vmstate_spapr_irq_map, 2027 &vmstate_spapr_cap_nested_kvm_hv, 2028 &vmstate_spapr_dtb, 2029 &vmstate_spapr_cap_large_decr, 2030 &vmstate_spapr_cap_ccf_assist, 2031 &vmstate_spapr_cap_fwnmi, 2032 &vmstate_spapr_fwnmi, 2033 NULL 2034 } 2035 }; 2036 2037 static int htab_save_setup(QEMUFile *f, void *opaque) 2038 { 2039 SpaprMachineState *spapr = opaque; 2040 2041 /* "Iteration" header */ 2042 if (!spapr->htab_shift) { 2043 qemu_put_be32(f, -1); 2044 } else { 2045 qemu_put_be32(f, spapr->htab_shift); 2046 } 2047 2048 if (spapr->htab) { 2049 spapr->htab_save_index = 0; 2050 spapr->htab_first_pass = true; 2051 } else { 2052 if (spapr->htab_shift) { 2053 assert(kvm_enabled()); 2054 } 2055 } 2056 2057 2058 return 0; 2059 } 2060 2061 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2062 int chunkstart, int n_valid, int n_invalid) 2063 { 2064 qemu_put_be32(f, chunkstart); 2065 qemu_put_be16(f, n_valid); 2066 qemu_put_be16(f, n_invalid); 2067 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2068 HASH_PTE_SIZE_64 * n_valid); 2069 } 2070 2071 static void htab_save_end_marker(QEMUFile *f) 2072 { 2073 qemu_put_be32(f, 0); 2074 qemu_put_be16(f, 0); 2075 qemu_put_be16(f, 0); 2076 } 2077 2078 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2079 int64_t max_ns) 2080 { 2081 bool has_timeout = max_ns != -1; 2082 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2083 int index = spapr->htab_save_index; 2084 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2085 2086 assert(spapr->htab_first_pass); 2087 2088 do { 2089 int chunkstart; 2090 2091 /* Consume invalid HPTEs */ 2092 while ((index < htabslots) 2093 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2094 CLEAN_HPTE(HPTE(spapr->htab, index)); 2095 index++; 2096 } 2097 2098 /* Consume valid HPTEs */ 2099 chunkstart = index; 2100 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2101 && HPTE_VALID(HPTE(spapr->htab, index))) { 2102 CLEAN_HPTE(HPTE(spapr->htab, index)); 2103 index++; 2104 } 2105 2106 if (index > chunkstart) { 2107 int n_valid = index - chunkstart; 2108 2109 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2110 2111 if (has_timeout && 2112 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2113 break; 2114 } 2115 } 2116 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2117 2118 if (index >= htabslots) { 2119 assert(index == htabslots); 2120 index = 0; 2121 spapr->htab_first_pass = false; 2122 } 2123 spapr->htab_save_index = index; 2124 } 2125 2126 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2127 int64_t max_ns) 2128 { 2129 bool final = max_ns < 0; 2130 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2131 int examined = 0, sent = 0; 2132 int index = spapr->htab_save_index; 2133 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2134 2135 assert(!spapr->htab_first_pass); 2136 2137 do { 2138 int chunkstart, invalidstart; 2139 2140 /* Consume non-dirty HPTEs */ 2141 while ((index < htabslots) 2142 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2143 index++; 2144 examined++; 2145 } 2146 2147 chunkstart = index; 2148 /* Consume valid dirty HPTEs */ 2149 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2150 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2151 && HPTE_VALID(HPTE(spapr->htab, index))) { 2152 CLEAN_HPTE(HPTE(spapr->htab, index)); 2153 index++; 2154 examined++; 2155 } 2156 2157 invalidstart = index; 2158 /* Consume invalid dirty HPTEs */ 2159 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2160 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2161 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2162 CLEAN_HPTE(HPTE(spapr->htab, index)); 2163 index++; 2164 examined++; 2165 } 2166 2167 if (index > chunkstart) { 2168 int n_valid = invalidstart - chunkstart; 2169 int n_invalid = index - invalidstart; 2170 2171 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2172 sent += index - chunkstart; 2173 2174 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2175 break; 2176 } 2177 } 2178 2179 if (examined >= htabslots) { 2180 break; 2181 } 2182 2183 if (index >= htabslots) { 2184 assert(index == htabslots); 2185 index = 0; 2186 } 2187 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2188 2189 if (index >= htabslots) { 2190 assert(index == htabslots); 2191 index = 0; 2192 } 2193 2194 spapr->htab_save_index = index; 2195 2196 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2197 } 2198 2199 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2200 #define MAX_KVM_BUF_SIZE 2048 2201 2202 static int htab_save_iterate(QEMUFile *f, void *opaque) 2203 { 2204 SpaprMachineState *spapr = opaque; 2205 int fd; 2206 int rc = 0; 2207 2208 /* Iteration header */ 2209 if (!spapr->htab_shift) { 2210 qemu_put_be32(f, -1); 2211 return 1; 2212 } else { 2213 qemu_put_be32(f, 0); 2214 } 2215 2216 if (!spapr->htab) { 2217 assert(kvm_enabled()); 2218 2219 fd = get_htab_fd(spapr); 2220 if (fd < 0) { 2221 return fd; 2222 } 2223 2224 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2225 if (rc < 0) { 2226 return rc; 2227 } 2228 } else if (spapr->htab_first_pass) { 2229 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2230 } else { 2231 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2232 } 2233 2234 htab_save_end_marker(f); 2235 2236 return rc; 2237 } 2238 2239 static int htab_save_complete(QEMUFile *f, void *opaque) 2240 { 2241 SpaprMachineState *spapr = opaque; 2242 int fd; 2243 2244 /* Iteration header */ 2245 if (!spapr->htab_shift) { 2246 qemu_put_be32(f, -1); 2247 return 0; 2248 } else { 2249 qemu_put_be32(f, 0); 2250 } 2251 2252 if (!spapr->htab) { 2253 int rc; 2254 2255 assert(kvm_enabled()); 2256 2257 fd = get_htab_fd(spapr); 2258 if (fd < 0) { 2259 return fd; 2260 } 2261 2262 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2263 if (rc < 0) { 2264 return rc; 2265 } 2266 } else { 2267 if (spapr->htab_first_pass) { 2268 htab_save_first_pass(f, spapr, -1); 2269 } 2270 htab_save_later_pass(f, spapr, -1); 2271 } 2272 2273 /* End marker */ 2274 htab_save_end_marker(f); 2275 2276 return 0; 2277 } 2278 2279 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2280 { 2281 SpaprMachineState *spapr = opaque; 2282 uint32_t section_hdr; 2283 int fd = -1; 2284 Error *local_err = NULL; 2285 2286 if (version_id < 1 || version_id > 1) { 2287 error_report("htab_load() bad version"); 2288 return -EINVAL; 2289 } 2290 2291 section_hdr = qemu_get_be32(f); 2292 2293 if (section_hdr == -1) { 2294 spapr_free_hpt(spapr); 2295 return 0; 2296 } 2297 2298 if (section_hdr) { 2299 /* First section gives the htab size */ 2300 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2301 if (local_err) { 2302 error_report_err(local_err); 2303 return -EINVAL; 2304 } 2305 return 0; 2306 } 2307 2308 if (!spapr->htab) { 2309 assert(kvm_enabled()); 2310 2311 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2312 if (fd < 0) { 2313 error_report_err(local_err); 2314 return fd; 2315 } 2316 } 2317 2318 while (true) { 2319 uint32_t index; 2320 uint16_t n_valid, n_invalid; 2321 2322 index = qemu_get_be32(f); 2323 n_valid = qemu_get_be16(f); 2324 n_invalid = qemu_get_be16(f); 2325 2326 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2327 /* End of Stream */ 2328 break; 2329 } 2330 2331 if ((index + n_valid + n_invalid) > 2332 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2333 /* Bad index in stream */ 2334 error_report( 2335 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2336 index, n_valid, n_invalid, spapr->htab_shift); 2337 return -EINVAL; 2338 } 2339 2340 if (spapr->htab) { 2341 if (n_valid) { 2342 qemu_get_buffer(f, HPTE(spapr->htab, index), 2343 HASH_PTE_SIZE_64 * n_valid); 2344 } 2345 if (n_invalid) { 2346 memset(HPTE(spapr->htab, index + n_valid), 0, 2347 HASH_PTE_SIZE_64 * n_invalid); 2348 } 2349 } else { 2350 int rc; 2351 2352 assert(fd >= 0); 2353 2354 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2355 if (rc < 0) { 2356 return rc; 2357 } 2358 } 2359 } 2360 2361 if (!spapr->htab) { 2362 assert(fd >= 0); 2363 close(fd); 2364 } 2365 2366 return 0; 2367 } 2368 2369 static void htab_save_cleanup(void *opaque) 2370 { 2371 SpaprMachineState *spapr = opaque; 2372 2373 close_htab_fd(spapr); 2374 } 2375 2376 static SaveVMHandlers savevm_htab_handlers = { 2377 .save_setup = htab_save_setup, 2378 .save_live_iterate = htab_save_iterate, 2379 .save_live_complete_precopy = htab_save_complete, 2380 .save_cleanup = htab_save_cleanup, 2381 .load_state = htab_load, 2382 }; 2383 2384 static void spapr_boot_set(void *opaque, const char *boot_device, 2385 Error **errp) 2386 { 2387 MachineState *machine = MACHINE(opaque); 2388 machine->boot_order = g_strdup(boot_device); 2389 } 2390 2391 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2392 { 2393 MachineState *machine = MACHINE(spapr); 2394 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2395 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2396 int i; 2397 2398 for (i = 0; i < nr_lmbs; i++) { 2399 uint64_t addr; 2400 2401 addr = i * lmb_size + machine->device_memory->base; 2402 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2403 addr / lmb_size); 2404 } 2405 } 2406 2407 /* 2408 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2409 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2410 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2411 */ 2412 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2413 { 2414 int i; 2415 2416 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2417 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2418 " is not aligned to %" PRIu64 " MiB", 2419 machine->ram_size, 2420 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2421 return; 2422 } 2423 2424 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2425 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2426 " is not aligned to %" PRIu64 " MiB", 2427 machine->ram_size, 2428 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2429 return; 2430 } 2431 2432 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2433 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2434 error_setg(errp, 2435 "Node %d memory size 0x%" PRIx64 2436 " is not aligned to %" PRIu64 " MiB", 2437 i, machine->numa_state->nodes[i].node_mem, 2438 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2439 return; 2440 } 2441 } 2442 } 2443 2444 /* find cpu slot in machine->possible_cpus by core_id */ 2445 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2446 { 2447 int index = id / ms->smp.threads; 2448 2449 if (index >= ms->possible_cpus->len) { 2450 return NULL; 2451 } 2452 if (idx) { 2453 *idx = index; 2454 } 2455 return &ms->possible_cpus->cpus[index]; 2456 } 2457 2458 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2459 { 2460 MachineState *ms = MACHINE(spapr); 2461 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2462 Error *local_err = NULL; 2463 bool vsmt_user = !!spapr->vsmt; 2464 int kvm_smt = kvmppc_smt_threads(); 2465 int ret; 2466 unsigned int smp_threads = ms->smp.threads; 2467 2468 if (!kvm_enabled() && (smp_threads > 1)) { 2469 error_setg(errp, "TCG cannot support more than 1 thread/core " 2470 "on a pseries machine"); 2471 return; 2472 } 2473 if (!is_power_of_2(smp_threads)) { 2474 error_setg(errp, "Cannot support %d threads/core on a pseries " 2475 "machine because it must be a power of 2", smp_threads); 2476 return; 2477 } 2478 2479 /* Detemine the VSMT mode to use: */ 2480 if (vsmt_user) { 2481 if (spapr->vsmt < smp_threads) { 2482 error_setg(errp, "Cannot support VSMT mode %d" 2483 " because it must be >= threads/core (%d)", 2484 spapr->vsmt, smp_threads); 2485 return; 2486 } 2487 /* In this case, spapr->vsmt has been set by the command line */ 2488 } else if (!smc->smp_threads_vsmt) { 2489 /* 2490 * Default VSMT value is tricky, because we need it to be as 2491 * consistent as possible (for migration), but this requires 2492 * changing it for at least some existing cases. We pick 8 as 2493 * the value that we'd get with KVM on POWER8, the 2494 * overwhelmingly common case in production systems. 2495 */ 2496 spapr->vsmt = MAX(8, smp_threads); 2497 } else { 2498 spapr->vsmt = smp_threads; 2499 } 2500 2501 /* KVM: If necessary, set the SMT mode: */ 2502 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2503 ret = kvmppc_set_smt_threads(spapr->vsmt); 2504 if (ret) { 2505 /* Looks like KVM isn't able to change VSMT mode */ 2506 error_setg(&local_err, 2507 "Failed to set KVM's VSMT mode to %d (errno %d)", 2508 spapr->vsmt, ret); 2509 /* We can live with that if the default one is big enough 2510 * for the number of threads, and a submultiple of the one 2511 * we want. In this case we'll waste some vcpu ids, but 2512 * behaviour will be correct */ 2513 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2514 warn_report_err(local_err); 2515 } else { 2516 if (!vsmt_user) { 2517 error_append_hint(&local_err, 2518 "On PPC, a VM with %d threads/core" 2519 " on a host with %d threads/core" 2520 " requires the use of VSMT mode %d.\n", 2521 smp_threads, kvm_smt, spapr->vsmt); 2522 } 2523 kvmppc_error_append_smt_possible_hint(&local_err); 2524 error_propagate(errp, local_err); 2525 } 2526 } 2527 } 2528 /* else TCG: nothing to do currently */ 2529 } 2530 2531 static void spapr_init_cpus(SpaprMachineState *spapr) 2532 { 2533 MachineState *machine = MACHINE(spapr); 2534 MachineClass *mc = MACHINE_GET_CLASS(machine); 2535 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2536 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2537 const CPUArchIdList *possible_cpus; 2538 unsigned int smp_cpus = machine->smp.cpus; 2539 unsigned int smp_threads = machine->smp.threads; 2540 unsigned int max_cpus = machine->smp.max_cpus; 2541 int boot_cores_nr = smp_cpus / smp_threads; 2542 int i; 2543 2544 possible_cpus = mc->possible_cpu_arch_ids(machine); 2545 if (mc->has_hotpluggable_cpus) { 2546 if (smp_cpus % smp_threads) { 2547 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2548 smp_cpus, smp_threads); 2549 exit(1); 2550 } 2551 if (max_cpus % smp_threads) { 2552 error_report("max_cpus (%u) must be multiple of threads (%u)", 2553 max_cpus, smp_threads); 2554 exit(1); 2555 } 2556 } else { 2557 if (max_cpus != smp_cpus) { 2558 error_report("This machine version does not support CPU hotplug"); 2559 exit(1); 2560 } 2561 boot_cores_nr = possible_cpus->len; 2562 } 2563 2564 if (smc->pre_2_10_has_unused_icps) { 2565 int i; 2566 2567 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2568 /* Dummy entries get deregistered when real ICPState objects 2569 * are registered during CPU core hotplug. 2570 */ 2571 pre_2_10_vmstate_register_dummy_icp(i); 2572 } 2573 } 2574 2575 for (i = 0; i < possible_cpus->len; i++) { 2576 int core_id = i * smp_threads; 2577 2578 if (mc->has_hotpluggable_cpus) { 2579 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2580 spapr_vcpu_id(spapr, core_id)); 2581 } 2582 2583 if (i < boot_cores_nr) { 2584 Object *core = object_new(type); 2585 int nr_threads = smp_threads; 2586 2587 /* Handle the partially filled core for older machine types */ 2588 if ((i + 1) * smp_threads >= smp_cpus) { 2589 nr_threads = smp_cpus - i * smp_threads; 2590 } 2591 2592 object_property_set_int(core, "nr-threads", nr_threads, 2593 &error_fatal); 2594 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2595 &error_fatal); 2596 qdev_realize(DEVICE(core), NULL, &error_fatal); 2597 2598 object_unref(core); 2599 } 2600 } 2601 } 2602 2603 static PCIHostState *spapr_create_default_phb(void) 2604 { 2605 DeviceState *dev; 2606 2607 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2608 qdev_prop_set_uint32(dev, "index", 0); 2609 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2610 2611 return PCI_HOST_BRIDGE(dev); 2612 } 2613 2614 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2615 { 2616 MachineState *machine = MACHINE(spapr); 2617 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2618 hwaddr rma_size = machine->ram_size; 2619 hwaddr node0_size = spapr_node0_size(machine); 2620 2621 /* RMA has to fit in the first NUMA node */ 2622 rma_size = MIN(rma_size, node0_size); 2623 2624 /* 2625 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2626 * never exceed that 2627 */ 2628 rma_size = MIN(rma_size, 1 * TiB); 2629 2630 /* 2631 * Clamp the RMA size based on machine type. This is for 2632 * migration compatibility with older qemu versions, which limited 2633 * the RMA size for complicated and mostly bad reasons. 2634 */ 2635 if (smc->rma_limit) { 2636 rma_size = MIN(rma_size, smc->rma_limit); 2637 } 2638 2639 if (rma_size < MIN_RMA_SLOF) { 2640 error_setg(errp, 2641 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2642 "ldMiB guest RMA (Real Mode Area memory)", 2643 MIN_RMA_SLOF / MiB); 2644 return 0; 2645 } 2646 2647 return rma_size; 2648 } 2649 2650 /* pSeries LPAR / sPAPR hardware init */ 2651 static void spapr_machine_init(MachineState *machine) 2652 { 2653 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2654 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2655 MachineClass *mc = MACHINE_GET_CLASS(machine); 2656 const char *kernel_filename = machine->kernel_filename; 2657 const char *initrd_filename = machine->initrd_filename; 2658 PCIHostState *phb; 2659 int i; 2660 MemoryRegion *sysmem = get_system_memory(); 2661 long load_limit, fw_size; 2662 char *filename; 2663 Error *resize_hpt_err = NULL; 2664 2665 msi_nonbroken = true; 2666 2667 QLIST_INIT(&spapr->phbs); 2668 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2669 2670 /* Determine capabilities to run with */ 2671 spapr_caps_init(spapr); 2672 2673 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2674 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2675 /* 2676 * If the user explicitly requested a mode we should either 2677 * supply it, or fail completely (which we do below). But if 2678 * it's not set explicitly, we reset our mode to something 2679 * that works 2680 */ 2681 if (resize_hpt_err) { 2682 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2683 error_free(resize_hpt_err); 2684 resize_hpt_err = NULL; 2685 } else { 2686 spapr->resize_hpt = smc->resize_hpt_default; 2687 } 2688 } 2689 2690 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2691 2692 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2693 /* 2694 * User requested HPT resize, but this host can't supply it. Bail out 2695 */ 2696 error_report_err(resize_hpt_err); 2697 exit(1); 2698 } 2699 error_free(resize_hpt_err); 2700 2701 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2702 2703 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2704 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2705 2706 /* 2707 * VSMT must be set in order to be able to compute VCPU ids, ie to 2708 * call spapr_max_server_number() or spapr_vcpu_id(). 2709 */ 2710 spapr_set_vsmt_mode(spapr, &error_fatal); 2711 2712 /* Set up Interrupt Controller before we create the VCPUs */ 2713 spapr_irq_init(spapr, &error_fatal); 2714 2715 /* Set up containers for ibm,client-architecture-support negotiated options 2716 */ 2717 spapr->ov5 = spapr_ovec_new(); 2718 spapr->ov5_cas = spapr_ovec_new(); 2719 2720 if (smc->dr_lmb_enabled) { 2721 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2722 spapr_validate_node_memory(machine, &error_fatal); 2723 } 2724 2725 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2726 2727 /* advertise support for dedicated HP event source to guests */ 2728 if (spapr->use_hotplug_event_source) { 2729 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2730 } 2731 2732 /* advertise support for HPT resizing */ 2733 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2734 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2735 } 2736 2737 /* advertise support for ibm,dyamic-memory-v2 */ 2738 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2739 2740 /* advertise XIVE on POWER9 machines */ 2741 if (spapr->irq->xive) { 2742 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2743 } 2744 2745 /* init CPUs */ 2746 spapr_init_cpus(spapr); 2747 2748 /* 2749 * check we don't have a memory-less/cpu-less NUMA node 2750 * Firmware relies on the existing memory/cpu topology to provide the 2751 * NUMA topology to the kernel. 2752 * And the linux kernel needs to know the NUMA topology at start 2753 * to be able to hotplug CPUs later. 2754 */ 2755 if (machine->numa_state->num_nodes) { 2756 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2757 /* check for memory-less node */ 2758 if (machine->numa_state->nodes[i].node_mem == 0) { 2759 CPUState *cs; 2760 int found = 0; 2761 /* check for cpu-less node */ 2762 CPU_FOREACH(cs) { 2763 PowerPCCPU *cpu = POWERPC_CPU(cs); 2764 if (cpu->node_id == i) { 2765 found = 1; 2766 break; 2767 } 2768 } 2769 /* memory-less and cpu-less node */ 2770 if (!found) { 2771 error_report( 2772 "Memory-less/cpu-less nodes are not supported (node %d)", 2773 i); 2774 exit(1); 2775 } 2776 } 2777 } 2778 2779 } 2780 2781 /* 2782 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2783 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2784 * called from vPHB reset handler so we initialize the counter here. 2785 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2786 * must be equally distant from any other node. 2787 * The final value of spapr->gpu_numa_id is going to be written to 2788 * max-associativity-domains in spapr_build_fdt(). 2789 */ 2790 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2791 2792 /* Init numa_assoc_array */ 2793 spapr_numa_associativity_init(spapr, machine); 2794 2795 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2796 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2797 spapr->max_compat_pvr)) { 2798 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2799 /* KVM and TCG always allow GTSE with radix... */ 2800 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2801 } 2802 /* ... but not with hash (currently). */ 2803 2804 if (kvm_enabled()) { 2805 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2806 kvmppc_enable_logical_ci_hcalls(); 2807 kvmppc_enable_set_mode_hcall(); 2808 2809 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2810 kvmppc_enable_clear_ref_mod_hcalls(); 2811 2812 /* Enable H_PAGE_INIT */ 2813 kvmppc_enable_h_page_init(); 2814 } 2815 2816 /* map RAM */ 2817 memory_region_add_subregion(sysmem, 0, machine->ram); 2818 2819 /* always allocate the device memory information */ 2820 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2821 2822 /* initialize hotplug memory address space */ 2823 if (machine->ram_size < machine->maxram_size) { 2824 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2825 /* 2826 * Limit the number of hotpluggable memory slots to half the number 2827 * slots that KVM supports, leaving the other half for PCI and other 2828 * devices. However ensure that number of slots doesn't drop below 32. 2829 */ 2830 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2831 SPAPR_MAX_RAM_SLOTS; 2832 2833 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2834 max_memslots = SPAPR_MAX_RAM_SLOTS; 2835 } 2836 if (machine->ram_slots > max_memslots) { 2837 error_report("Specified number of memory slots %" 2838 PRIu64" exceeds max supported %d", 2839 machine->ram_slots, max_memslots); 2840 exit(1); 2841 } 2842 2843 machine->device_memory->base = ROUND_UP(machine->ram_size, 2844 SPAPR_DEVICE_MEM_ALIGN); 2845 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2846 "device-memory", device_mem_size); 2847 memory_region_add_subregion(sysmem, machine->device_memory->base, 2848 &machine->device_memory->mr); 2849 } 2850 2851 if (smc->dr_lmb_enabled) { 2852 spapr_create_lmb_dr_connectors(spapr); 2853 } 2854 2855 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2856 /* Create the error string for live migration blocker */ 2857 error_setg(&spapr->fwnmi_migration_blocker, 2858 "A machine check is being handled during migration. The handler" 2859 "may run and log hardware error on the destination"); 2860 } 2861 2862 if (mc->nvdimm_supported) { 2863 spapr_create_nvdimm_dr_connectors(spapr); 2864 } 2865 2866 /* Set up RTAS event infrastructure */ 2867 spapr_events_init(spapr); 2868 2869 /* Set up the RTC RTAS interfaces */ 2870 spapr_rtc_create(spapr); 2871 2872 /* Set up VIO bus */ 2873 spapr->vio_bus = spapr_vio_bus_init(); 2874 2875 for (i = 0; i < serial_max_hds(); i++) { 2876 if (serial_hd(i)) { 2877 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2878 } 2879 } 2880 2881 /* We always have at least the nvram device on VIO */ 2882 spapr_create_nvram(spapr); 2883 2884 /* 2885 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2886 * connectors (described in root DT node's "ibm,drc-types" property) 2887 * are pre-initialized here. additional child connectors (such as 2888 * connectors for a PHBs PCI slots) are added as needed during their 2889 * parent's realization. 2890 */ 2891 if (smc->dr_phb_enabled) { 2892 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2893 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2894 } 2895 } 2896 2897 /* Set up PCI */ 2898 spapr_pci_rtas_init(); 2899 2900 phb = spapr_create_default_phb(); 2901 2902 for (i = 0; i < nb_nics; i++) { 2903 NICInfo *nd = &nd_table[i]; 2904 2905 if (!nd->model) { 2906 nd->model = g_strdup("spapr-vlan"); 2907 } 2908 2909 if (g_str_equal(nd->model, "spapr-vlan") || 2910 g_str_equal(nd->model, "ibmveth")) { 2911 spapr_vlan_create(spapr->vio_bus, nd); 2912 } else { 2913 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2914 } 2915 } 2916 2917 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2918 spapr_vscsi_create(spapr->vio_bus); 2919 } 2920 2921 /* Graphics */ 2922 if (spapr_vga_init(phb->bus, &error_fatal)) { 2923 spapr->has_graphics = true; 2924 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2925 } 2926 2927 if (machine->usb) { 2928 if (smc->use_ohci_by_default) { 2929 pci_create_simple(phb->bus, -1, "pci-ohci"); 2930 } else { 2931 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2932 } 2933 2934 if (spapr->has_graphics) { 2935 USBBus *usb_bus = usb_bus_find(-1); 2936 2937 usb_create_simple(usb_bus, "usb-kbd"); 2938 usb_create_simple(usb_bus, "usb-mouse"); 2939 } 2940 } 2941 2942 if (kernel_filename) { 2943 uint64_t lowaddr = 0; 2944 2945 spapr->kernel_size = load_elf(kernel_filename, NULL, 2946 translate_kernel_address, spapr, 2947 NULL, &lowaddr, NULL, NULL, 1, 2948 PPC_ELF_MACHINE, 0, 0); 2949 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2950 spapr->kernel_size = load_elf(kernel_filename, NULL, 2951 translate_kernel_address, spapr, NULL, 2952 &lowaddr, NULL, NULL, 0, 2953 PPC_ELF_MACHINE, 2954 0, 0); 2955 spapr->kernel_le = spapr->kernel_size > 0; 2956 } 2957 if (spapr->kernel_size < 0) { 2958 error_report("error loading %s: %s", kernel_filename, 2959 load_elf_strerror(spapr->kernel_size)); 2960 exit(1); 2961 } 2962 2963 /* load initrd */ 2964 if (initrd_filename) { 2965 /* Try to locate the initrd in the gap between the kernel 2966 * and the firmware. Add a bit of space just in case 2967 */ 2968 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2969 + 0x1ffff) & ~0xffff; 2970 spapr->initrd_size = load_image_targphys(initrd_filename, 2971 spapr->initrd_base, 2972 load_limit 2973 - spapr->initrd_base); 2974 if (spapr->initrd_size < 0) { 2975 error_report("could not load initial ram disk '%s'", 2976 initrd_filename); 2977 exit(1); 2978 } 2979 } 2980 } 2981 2982 if (bios_name == NULL) { 2983 bios_name = FW_FILE_NAME; 2984 } 2985 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2986 if (!filename) { 2987 error_report("Could not find LPAR firmware '%s'", bios_name); 2988 exit(1); 2989 } 2990 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2991 if (fw_size <= 0) { 2992 error_report("Could not load LPAR firmware '%s'", filename); 2993 exit(1); 2994 } 2995 g_free(filename); 2996 2997 /* FIXME: Should register things through the MachineState's qdev 2998 * interface, this is a legacy from the sPAPREnvironment structure 2999 * which predated MachineState but had a similar function */ 3000 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3001 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3002 &savevm_htab_handlers, spapr); 3003 3004 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 3005 3006 qemu_register_boot_set(spapr_boot_set, spapr); 3007 3008 /* 3009 * Nothing needs to be done to resume a suspended guest because 3010 * suspending does not change the machine state, so no need for 3011 * a ->wakeup method. 3012 */ 3013 qemu_register_wakeup_support(); 3014 3015 if (kvm_enabled()) { 3016 /* to stop and start vmclock */ 3017 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3018 &spapr->tb); 3019 3020 kvmppc_spapr_enable_inkernel_multitce(); 3021 } 3022 3023 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3024 } 3025 3026 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3027 { 3028 if (!vm_type) { 3029 return 0; 3030 } 3031 3032 if (!strcmp(vm_type, "HV")) { 3033 return 1; 3034 } 3035 3036 if (!strcmp(vm_type, "PR")) { 3037 return 2; 3038 } 3039 3040 error_report("Unknown kvm-type specified '%s'", vm_type); 3041 exit(1); 3042 } 3043 3044 /* 3045 * Implementation of an interface to adjust firmware path 3046 * for the bootindex property handling. 3047 */ 3048 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3049 DeviceState *dev) 3050 { 3051 #define CAST(type, obj, name) \ 3052 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3053 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3054 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3055 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3056 3057 if (d) { 3058 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3059 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3060 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3061 3062 if (spapr) { 3063 /* 3064 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3065 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3066 * 0x8000 | (target << 8) | (bus << 5) | lun 3067 * (see the "Logical unit addressing format" table in SAM5) 3068 */ 3069 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3070 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3071 (uint64_t)id << 48); 3072 } else if (virtio) { 3073 /* 3074 * We use SRP luns of the form 01000000 | (target << 8) | lun 3075 * in the top 32 bits of the 64-bit LUN 3076 * Note: the quote above is from SLOF and it is wrong, 3077 * the actual binding is: 3078 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3079 */ 3080 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3081 if (d->lun >= 256) { 3082 /* Use the LUN "flat space addressing method" */ 3083 id |= 0x4000; 3084 } 3085 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3086 (uint64_t)id << 32); 3087 } else if (usb) { 3088 /* 3089 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3090 * in the top 32 bits of the 64-bit LUN 3091 */ 3092 unsigned usb_port = atoi(usb->port->path); 3093 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3094 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3095 (uint64_t)id << 32); 3096 } 3097 } 3098 3099 /* 3100 * SLOF probes the USB devices, and if it recognizes that the device is a 3101 * storage device, it changes its name to "storage" instead of "usb-host", 3102 * and additionally adds a child node for the SCSI LUN, so the correct 3103 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3104 */ 3105 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3106 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3107 if (usb_host_dev_is_scsi_storage(usbdev)) { 3108 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3109 } 3110 } 3111 3112 if (phb) { 3113 /* Replace "pci" with "pci@800000020000000" */ 3114 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3115 } 3116 3117 if (vsc) { 3118 /* Same logic as virtio above */ 3119 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3120 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3121 } 3122 3123 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3124 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3125 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3126 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3127 } 3128 3129 return NULL; 3130 } 3131 3132 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3133 { 3134 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3135 3136 return g_strdup(spapr->kvm_type); 3137 } 3138 3139 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3140 { 3141 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3142 3143 g_free(spapr->kvm_type); 3144 spapr->kvm_type = g_strdup(value); 3145 } 3146 3147 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3148 { 3149 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3150 3151 return spapr->use_hotplug_event_source; 3152 } 3153 3154 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3155 Error **errp) 3156 { 3157 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3158 3159 spapr->use_hotplug_event_source = value; 3160 } 3161 3162 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3163 { 3164 return true; 3165 } 3166 3167 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3168 { 3169 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3170 3171 switch (spapr->resize_hpt) { 3172 case SPAPR_RESIZE_HPT_DEFAULT: 3173 return g_strdup("default"); 3174 case SPAPR_RESIZE_HPT_DISABLED: 3175 return g_strdup("disabled"); 3176 case SPAPR_RESIZE_HPT_ENABLED: 3177 return g_strdup("enabled"); 3178 case SPAPR_RESIZE_HPT_REQUIRED: 3179 return g_strdup("required"); 3180 } 3181 g_assert_not_reached(); 3182 } 3183 3184 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3185 { 3186 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3187 3188 if (strcmp(value, "default") == 0) { 3189 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3190 } else if (strcmp(value, "disabled") == 0) { 3191 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3192 } else if (strcmp(value, "enabled") == 0) { 3193 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3194 } else if (strcmp(value, "required") == 0) { 3195 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3196 } else { 3197 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3198 } 3199 } 3200 3201 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3202 { 3203 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3204 3205 if (spapr->irq == &spapr_irq_xics_legacy) { 3206 return g_strdup("legacy"); 3207 } else if (spapr->irq == &spapr_irq_xics) { 3208 return g_strdup("xics"); 3209 } else if (spapr->irq == &spapr_irq_xive) { 3210 return g_strdup("xive"); 3211 } else if (spapr->irq == &spapr_irq_dual) { 3212 return g_strdup("dual"); 3213 } 3214 g_assert_not_reached(); 3215 } 3216 3217 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3218 { 3219 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3220 3221 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3222 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3223 return; 3224 } 3225 3226 /* The legacy IRQ backend can not be set */ 3227 if (strcmp(value, "xics") == 0) { 3228 spapr->irq = &spapr_irq_xics; 3229 } else if (strcmp(value, "xive") == 0) { 3230 spapr->irq = &spapr_irq_xive; 3231 } else if (strcmp(value, "dual") == 0) { 3232 spapr->irq = &spapr_irq_dual; 3233 } else { 3234 error_setg(errp, "Bad value for \"ic-mode\" property"); 3235 } 3236 } 3237 3238 static char *spapr_get_host_model(Object *obj, Error **errp) 3239 { 3240 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3241 3242 return g_strdup(spapr->host_model); 3243 } 3244 3245 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3246 { 3247 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3248 3249 g_free(spapr->host_model); 3250 spapr->host_model = g_strdup(value); 3251 } 3252 3253 static char *spapr_get_host_serial(Object *obj, Error **errp) 3254 { 3255 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3256 3257 return g_strdup(spapr->host_serial); 3258 } 3259 3260 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3261 { 3262 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3263 3264 g_free(spapr->host_serial); 3265 spapr->host_serial = g_strdup(value); 3266 } 3267 3268 static void spapr_instance_init(Object *obj) 3269 { 3270 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3271 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3272 3273 spapr->htab_fd = -1; 3274 spapr->use_hotplug_event_source = true; 3275 object_property_add_str(obj, "kvm-type", 3276 spapr_get_kvm_type, spapr_set_kvm_type); 3277 object_property_set_description(obj, "kvm-type", 3278 "Specifies the KVM virtualization mode (HV, PR)"); 3279 object_property_add_bool(obj, "modern-hotplug-events", 3280 spapr_get_modern_hotplug_events, 3281 spapr_set_modern_hotplug_events); 3282 object_property_set_description(obj, "modern-hotplug-events", 3283 "Use dedicated hotplug event mechanism in" 3284 " place of standard EPOW events when possible" 3285 " (required for memory hot-unplug support)"); 3286 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3287 "Maximum permitted CPU compatibility mode"); 3288 3289 object_property_add_str(obj, "resize-hpt", 3290 spapr_get_resize_hpt, spapr_set_resize_hpt); 3291 object_property_set_description(obj, "resize-hpt", 3292 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3293 object_property_add_uint32_ptr(obj, "vsmt", 3294 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3295 object_property_set_description(obj, "vsmt", 3296 "Virtual SMT: KVM behaves as if this were" 3297 " the host's SMT mode"); 3298 3299 object_property_add_bool(obj, "vfio-no-msix-emulation", 3300 spapr_get_msix_emulation, NULL); 3301 3302 object_property_add_uint64_ptr(obj, "kernel-addr", 3303 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3304 object_property_set_description(obj, "kernel-addr", 3305 stringify(KERNEL_LOAD_ADDR) 3306 " for -kernel is the default"); 3307 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3308 /* The machine class defines the default interrupt controller mode */ 3309 spapr->irq = smc->irq; 3310 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3311 spapr_set_ic_mode); 3312 object_property_set_description(obj, "ic-mode", 3313 "Specifies the interrupt controller mode (xics, xive, dual)"); 3314 3315 object_property_add_str(obj, "host-model", 3316 spapr_get_host_model, spapr_set_host_model); 3317 object_property_set_description(obj, "host-model", 3318 "Host model to advertise in guest device tree"); 3319 object_property_add_str(obj, "host-serial", 3320 spapr_get_host_serial, spapr_set_host_serial); 3321 object_property_set_description(obj, "host-serial", 3322 "Host serial number to advertise in guest device tree"); 3323 } 3324 3325 static void spapr_machine_finalizefn(Object *obj) 3326 { 3327 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3328 3329 g_free(spapr->kvm_type); 3330 } 3331 3332 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3333 { 3334 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3335 PowerPCCPU *cpu = POWERPC_CPU(cs); 3336 CPUPPCState *env = &cpu->env; 3337 3338 cpu_synchronize_state(cs); 3339 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3340 if (spapr->fwnmi_system_reset_addr != -1) { 3341 uint64_t rtas_addr, addr; 3342 3343 /* get rtas addr from fdt */ 3344 rtas_addr = spapr_get_rtas_addr(); 3345 if (!rtas_addr) { 3346 qemu_system_guest_panicked(NULL); 3347 return; 3348 } 3349 3350 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3351 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3352 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3353 env->gpr[3] = addr; 3354 } 3355 ppc_cpu_do_system_reset(cs); 3356 if (spapr->fwnmi_system_reset_addr != -1) { 3357 env->nip = spapr->fwnmi_system_reset_addr; 3358 } 3359 } 3360 3361 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3362 { 3363 CPUState *cs; 3364 3365 CPU_FOREACH(cs) { 3366 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3367 } 3368 } 3369 3370 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3371 void *fdt, int *fdt_start_offset, Error **errp) 3372 { 3373 uint64_t addr; 3374 uint32_t node; 3375 3376 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3377 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3378 &error_abort); 3379 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3380 SPAPR_MEMORY_BLOCK_SIZE); 3381 return 0; 3382 } 3383 3384 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3385 bool dedicated_hp_event_source, Error **errp) 3386 { 3387 SpaprDrc *drc; 3388 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3389 int i; 3390 uint64_t addr = addr_start; 3391 bool hotplugged = spapr_drc_hotplugged(dev); 3392 Error *local_err = NULL; 3393 3394 for (i = 0; i < nr_lmbs; i++) { 3395 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3396 addr / SPAPR_MEMORY_BLOCK_SIZE); 3397 g_assert(drc); 3398 3399 spapr_drc_attach(drc, dev, &local_err); 3400 if (local_err) { 3401 while (addr > addr_start) { 3402 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3403 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3404 addr / SPAPR_MEMORY_BLOCK_SIZE); 3405 spapr_drc_detach(drc); 3406 } 3407 error_propagate(errp, local_err); 3408 return; 3409 } 3410 if (!hotplugged) { 3411 spapr_drc_reset(drc); 3412 } 3413 addr += SPAPR_MEMORY_BLOCK_SIZE; 3414 } 3415 /* send hotplug notification to the 3416 * guest only in case of hotplugged memory 3417 */ 3418 if (hotplugged) { 3419 if (dedicated_hp_event_source) { 3420 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3421 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3422 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3423 nr_lmbs, 3424 spapr_drc_index(drc)); 3425 } else { 3426 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3427 nr_lmbs); 3428 } 3429 } 3430 } 3431 3432 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3433 Error **errp) 3434 { 3435 Error *local_err = NULL; 3436 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3437 PCDIMMDevice *dimm = PC_DIMM(dev); 3438 uint64_t size, addr, slot; 3439 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3440 3441 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3442 3443 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3444 if (local_err) { 3445 goto out; 3446 } 3447 3448 if (!is_nvdimm) { 3449 addr = object_property_get_uint(OBJECT(dimm), 3450 PC_DIMM_ADDR_PROP, &local_err); 3451 if (local_err) { 3452 goto out_unplug; 3453 } 3454 spapr_add_lmbs(dev, addr, size, 3455 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3456 &local_err); 3457 } else { 3458 slot = object_property_get_uint(OBJECT(dimm), 3459 PC_DIMM_SLOT_PROP, &local_err); 3460 if (local_err) { 3461 goto out_unplug; 3462 } 3463 spapr_add_nvdimm(dev, slot, &local_err); 3464 } 3465 3466 if (local_err) { 3467 goto out_unplug; 3468 } 3469 3470 return; 3471 3472 out_unplug: 3473 pc_dimm_unplug(dimm, MACHINE(ms)); 3474 out: 3475 error_propagate(errp, local_err); 3476 } 3477 3478 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3479 Error **errp) 3480 { 3481 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3482 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3483 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3484 PCDIMMDevice *dimm = PC_DIMM(dev); 3485 Error *local_err = NULL; 3486 uint64_t size; 3487 Object *memdev; 3488 hwaddr pagesize; 3489 3490 if (!smc->dr_lmb_enabled) { 3491 error_setg(errp, "Memory hotplug not supported for this machine"); 3492 return; 3493 } 3494 3495 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3496 if (local_err) { 3497 error_propagate(errp, local_err); 3498 return; 3499 } 3500 3501 if (is_nvdimm) { 3502 spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, &local_err); 3503 if (local_err) { 3504 error_propagate(errp, local_err); 3505 return; 3506 } 3507 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3508 error_setg(errp, "Hotplugged memory size must be a multiple of " 3509 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3510 return; 3511 } 3512 3513 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3514 &error_abort); 3515 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3516 spapr_check_pagesize(spapr, pagesize, &local_err); 3517 if (local_err) { 3518 error_propagate(errp, local_err); 3519 return; 3520 } 3521 3522 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3523 } 3524 3525 struct SpaprDimmState { 3526 PCDIMMDevice *dimm; 3527 uint32_t nr_lmbs; 3528 QTAILQ_ENTRY(SpaprDimmState) next; 3529 }; 3530 3531 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3532 PCDIMMDevice *dimm) 3533 { 3534 SpaprDimmState *dimm_state = NULL; 3535 3536 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3537 if (dimm_state->dimm == dimm) { 3538 break; 3539 } 3540 } 3541 return dimm_state; 3542 } 3543 3544 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3545 uint32_t nr_lmbs, 3546 PCDIMMDevice *dimm) 3547 { 3548 SpaprDimmState *ds = NULL; 3549 3550 /* 3551 * If this request is for a DIMM whose removal had failed earlier 3552 * (due to guest's refusal to remove the LMBs), we would have this 3553 * dimm already in the pending_dimm_unplugs list. In that 3554 * case don't add again. 3555 */ 3556 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3557 if (!ds) { 3558 ds = g_malloc0(sizeof(SpaprDimmState)); 3559 ds->nr_lmbs = nr_lmbs; 3560 ds->dimm = dimm; 3561 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3562 } 3563 return ds; 3564 } 3565 3566 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3567 SpaprDimmState *dimm_state) 3568 { 3569 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3570 g_free(dimm_state); 3571 } 3572 3573 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3574 PCDIMMDevice *dimm) 3575 { 3576 SpaprDrc *drc; 3577 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3578 &error_abort); 3579 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3580 uint32_t avail_lmbs = 0; 3581 uint64_t addr_start, addr; 3582 int i; 3583 3584 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3585 &error_abort); 3586 3587 addr = addr_start; 3588 for (i = 0; i < nr_lmbs; i++) { 3589 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3590 addr / SPAPR_MEMORY_BLOCK_SIZE); 3591 g_assert(drc); 3592 if (drc->dev) { 3593 avail_lmbs++; 3594 } 3595 addr += SPAPR_MEMORY_BLOCK_SIZE; 3596 } 3597 3598 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3599 } 3600 3601 /* Callback to be called during DRC release. */ 3602 void spapr_lmb_release(DeviceState *dev) 3603 { 3604 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3605 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3606 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3607 3608 /* This information will get lost if a migration occurs 3609 * during the unplug process. In this case recover it. */ 3610 if (ds == NULL) { 3611 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3612 g_assert(ds); 3613 /* The DRC being examined by the caller at least must be counted */ 3614 g_assert(ds->nr_lmbs); 3615 } 3616 3617 if (--ds->nr_lmbs) { 3618 return; 3619 } 3620 3621 /* 3622 * Now that all the LMBs have been removed by the guest, call the 3623 * unplug handler chain. This can never fail. 3624 */ 3625 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3626 object_unparent(OBJECT(dev)); 3627 } 3628 3629 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3630 { 3631 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3632 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3633 3634 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3635 qdev_unrealize(dev); 3636 spapr_pending_dimm_unplugs_remove(spapr, ds); 3637 } 3638 3639 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3640 DeviceState *dev, Error **errp) 3641 { 3642 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3643 Error *local_err = NULL; 3644 PCDIMMDevice *dimm = PC_DIMM(dev); 3645 uint32_t nr_lmbs; 3646 uint64_t size, addr_start, addr; 3647 int i; 3648 SpaprDrc *drc; 3649 3650 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3651 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3652 return; 3653 } 3654 3655 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3656 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3657 3658 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3659 &local_err); 3660 if (local_err) { 3661 error_propagate(errp, local_err); 3662 return; 3663 } 3664 3665 /* 3666 * An existing pending dimm state for this DIMM means that there is an 3667 * unplug operation in progress, waiting for the spapr_lmb_release 3668 * callback to complete the job (BQL can't cover that far). In this case, 3669 * bail out to avoid detaching DRCs that were already released. 3670 */ 3671 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3672 error_setg(errp, "Memory unplug already in progress for device %s", 3673 dev->id); 3674 return; 3675 } 3676 3677 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3678 3679 addr = addr_start; 3680 for (i = 0; i < nr_lmbs; i++) { 3681 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3682 addr / SPAPR_MEMORY_BLOCK_SIZE); 3683 g_assert(drc); 3684 3685 spapr_drc_detach(drc); 3686 addr += SPAPR_MEMORY_BLOCK_SIZE; 3687 } 3688 3689 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3690 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3691 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3692 nr_lmbs, spapr_drc_index(drc)); 3693 } 3694 3695 /* Callback to be called during DRC release. */ 3696 void spapr_core_release(DeviceState *dev) 3697 { 3698 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3699 3700 /* Call the unplug handler chain. This can never fail. */ 3701 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3702 object_unparent(OBJECT(dev)); 3703 } 3704 3705 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3706 { 3707 MachineState *ms = MACHINE(hotplug_dev); 3708 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3709 CPUCore *cc = CPU_CORE(dev); 3710 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3711 3712 if (smc->pre_2_10_has_unused_icps) { 3713 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3714 int i; 3715 3716 for (i = 0; i < cc->nr_threads; i++) { 3717 CPUState *cs = CPU(sc->threads[i]); 3718 3719 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3720 } 3721 } 3722 3723 assert(core_slot); 3724 core_slot->cpu = NULL; 3725 qdev_unrealize(dev); 3726 } 3727 3728 static 3729 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3730 Error **errp) 3731 { 3732 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3733 int index; 3734 SpaprDrc *drc; 3735 CPUCore *cc = CPU_CORE(dev); 3736 3737 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3738 error_setg(errp, "Unable to find CPU core with core-id: %d", 3739 cc->core_id); 3740 return; 3741 } 3742 if (index == 0) { 3743 error_setg(errp, "Boot CPU core may not be unplugged"); 3744 return; 3745 } 3746 3747 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3748 spapr_vcpu_id(spapr, cc->core_id)); 3749 g_assert(drc); 3750 3751 if (!spapr_drc_unplug_requested(drc)) { 3752 spapr_drc_detach(drc); 3753 spapr_hotplug_req_remove_by_index(drc); 3754 } 3755 } 3756 3757 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3758 void *fdt, int *fdt_start_offset, Error **errp) 3759 { 3760 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3761 CPUState *cs = CPU(core->threads[0]); 3762 PowerPCCPU *cpu = POWERPC_CPU(cs); 3763 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3764 int id = spapr_get_vcpu_id(cpu); 3765 char *nodename; 3766 int offset; 3767 3768 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3769 offset = fdt_add_subnode(fdt, 0, nodename); 3770 g_free(nodename); 3771 3772 spapr_dt_cpu(cs, fdt, offset, spapr); 3773 3774 *fdt_start_offset = offset; 3775 return 0; 3776 } 3777 3778 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3779 Error **errp) 3780 { 3781 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3782 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3783 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3784 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3785 CPUCore *cc = CPU_CORE(dev); 3786 CPUState *cs; 3787 SpaprDrc *drc; 3788 Error *local_err = NULL; 3789 CPUArchId *core_slot; 3790 int index; 3791 bool hotplugged = spapr_drc_hotplugged(dev); 3792 int i; 3793 3794 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3795 if (!core_slot) { 3796 error_setg(errp, "Unable to find CPU core with core-id: %d", 3797 cc->core_id); 3798 return; 3799 } 3800 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3801 spapr_vcpu_id(spapr, cc->core_id)); 3802 3803 g_assert(drc || !mc->has_hotpluggable_cpus); 3804 3805 if (drc) { 3806 spapr_drc_attach(drc, dev, &local_err); 3807 if (local_err) { 3808 error_propagate(errp, local_err); 3809 return; 3810 } 3811 3812 if (hotplugged) { 3813 /* 3814 * Send hotplug notification interrupt to the guest only 3815 * in case of hotplugged CPUs. 3816 */ 3817 spapr_hotplug_req_add_by_index(drc); 3818 } else { 3819 spapr_drc_reset(drc); 3820 } 3821 } 3822 3823 core_slot->cpu = OBJECT(dev); 3824 3825 if (smc->pre_2_10_has_unused_icps) { 3826 for (i = 0; i < cc->nr_threads; i++) { 3827 cs = CPU(core->threads[i]); 3828 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3829 } 3830 } 3831 3832 /* 3833 * Set compatibility mode to match the boot CPU, which was either set 3834 * by the machine reset code or by CAS. 3835 */ 3836 if (hotplugged) { 3837 for (i = 0; i < cc->nr_threads; i++) { 3838 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3839 &local_err); 3840 if (local_err) { 3841 error_propagate(errp, local_err); 3842 return; 3843 } 3844 } 3845 } 3846 } 3847 3848 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3849 Error **errp) 3850 { 3851 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3852 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3853 CPUCore *cc = CPU_CORE(dev); 3854 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3855 const char *type = object_get_typename(OBJECT(dev)); 3856 CPUArchId *core_slot; 3857 int index; 3858 unsigned int smp_threads = machine->smp.threads; 3859 3860 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3861 error_setg(errp, "CPU hotplug not supported for this machine"); 3862 return; 3863 } 3864 3865 if (strcmp(base_core_type, type)) { 3866 error_setg(errp, "CPU core type should be %s", base_core_type); 3867 return; 3868 } 3869 3870 if (cc->core_id % smp_threads) { 3871 error_setg(errp, "invalid core id %d", cc->core_id); 3872 return; 3873 } 3874 3875 /* 3876 * In general we should have homogeneous threads-per-core, but old 3877 * (pre hotplug support) machine types allow the last core to have 3878 * reduced threads as a compatibility hack for when we allowed 3879 * total vcpus not a multiple of threads-per-core. 3880 */ 3881 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3882 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 3883 smp_threads); 3884 return; 3885 } 3886 3887 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3888 if (!core_slot) { 3889 error_setg(errp, "core id %d out of range", cc->core_id); 3890 return; 3891 } 3892 3893 if (core_slot->cpu) { 3894 error_setg(errp, "core %d already populated", cc->core_id); 3895 return; 3896 } 3897 3898 numa_cpu_pre_plug(core_slot, dev, errp); 3899 } 3900 3901 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3902 void *fdt, int *fdt_start_offset, Error **errp) 3903 { 3904 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3905 int intc_phandle; 3906 3907 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3908 if (intc_phandle <= 0) { 3909 return -1; 3910 } 3911 3912 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3913 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3914 return -1; 3915 } 3916 3917 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3918 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3919 3920 return 0; 3921 } 3922 3923 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3924 Error **errp) 3925 { 3926 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3927 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3928 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3929 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3930 3931 if (dev->hotplugged && !smc->dr_phb_enabled) { 3932 error_setg(errp, "PHB hotplug not supported for this machine"); 3933 return; 3934 } 3935 3936 if (sphb->index == (uint32_t)-1) { 3937 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3938 return; 3939 } 3940 3941 /* 3942 * This will check that sphb->index doesn't exceed the maximum number of 3943 * PHBs for the current machine type. 3944 */ 3945 smc->phb_placement(spapr, sphb->index, 3946 &sphb->buid, &sphb->io_win_addr, 3947 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3948 windows_supported, sphb->dma_liobn, 3949 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3950 errp); 3951 } 3952 3953 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3954 Error **errp) 3955 { 3956 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3957 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3958 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3959 SpaprDrc *drc; 3960 bool hotplugged = spapr_drc_hotplugged(dev); 3961 Error *local_err = NULL; 3962 3963 if (!smc->dr_phb_enabled) { 3964 return; 3965 } 3966 3967 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3968 /* hotplug hooks should check it's enabled before getting this far */ 3969 assert(drc); 3970 3971 spapr_drc_attach(drc, dev, &local_err); 3972 if (local_err) { 3973 error_propagate(errp, local_err); 3974 return; 3975 } 3976 3977 if (hotplugged) { 3978 spapr_hotplug_req_add_by_index(drc); 3979 } else { 3980 spapr_drc_reset(drc); 3981 } 3982 } 3983 3984 void spapr_phb_release(DeviceState *dev) 3985 { 3986 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3987 3988 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3989 object_unparent(OBJECT(dev)); 3990 } 3991 3992 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3993 { 3994 qdev_unrealize(dev); 3995 } 3996 3997 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 3998 DeviceState *dev, Error **errp) 3999 { 4000 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4001 SpaprDrc *drc; 4002 4003 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4004 assert(drc); 4005 4006 if (!spapr_drc_unplug_requested(drc)) { 4007 spapr_drc_detach(drc); 4008 spapr_hotplug_req_remove_by_index(drc); 4009 } 4010 } 4011 4012 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4013 Error **errp) 4014 { 4015 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4016 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4017 4018 if (spapr->tpm_proxy != NULL) { 4019 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4020 return; 4021 } 4022 4023 spapr->tpm_proxy = tpm_proxy; 4024 } 4025 4026 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4027 { 4028 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4029 4030 qdev_unrealize(dev); 4031 object_unparent(OBJECT(dev)); 4032 spapr->tpm_proxy = NULL; 4033 } 4034 4035 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4036 DeviceState *dev, Error **errp) 4037 { 4038 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4039 spapr_memory_plug(hotplug_dev, dev, errp); 4040 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4041 spapr_core_plug(hotplug_dev, dev, errp); 4042 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4043 spapr_phb_plug(hotplug_dev, dev, errp); 4044 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4045 spapr_tpm_proxy_plug(hotplug_dev, dev, errp); 4046 } 4047 } 4048 4049 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4050 DeviceState *dev, Error **errp) 4051 { 4052 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4053 spapr_memory_unplug(hotplug_dev, dev); 4054 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4055 spapr_core_unplug(hotplug_dev, dev); 4056 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4057 spapr_phb_unplug(hotplug_dev, dev); 4058 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4059 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4060 } 4061 } 4062 4063 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4064 DeviceState *dev, Error **errp) 4065 { 4066 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4067 MachineClass *mc = MACHINE_GET_CLASS(sms); 4068 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4069 4070 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4071 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 4072 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4073 } else { 4074 /* NOTE: this means there is a window after guest reset, prior to 4075 * CAS negotiation, where unplug requests will fail due to the 4076 * capability not being detected yet. This is a bit different than 4077 * the case with PCI unplug, where the events will be queued and 4078 * eventually handled by the guest after boot 4079 */ 4080 error_setg(errp, "Memory hot unplug not supported for this guest"); 4081 } 4082 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4083 if (!mc->has_hotpluggable_cpus) { 4084 error_setg(errp, "CPU hot unplug not supported on this machine"); 4085 return; 4086 } 4087 spapr_core_unplug_request(hotplug_dev, dev, errp); 4088 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4089 if (!smc->dr_phb_enabled) { 4090 error_setg(errp, "PHB hot unplug not supported on this machine"); 4091 return; 4092 } 4093 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4094 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4095 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4096 } 4097 } 4098 4099 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4100 DeviceState *dev, Error **errp) 4101 { 4102 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4103 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4104 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4105 spapr_core_pre_plug(hotplug_dev, dev, errp); 4106 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4107 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4108 } 4109 } 4110 4111 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4112 DeviceState *dev) 4113 { 4114 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4115 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4116 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4117 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4118 return HOTPLUG_HANDLER(machine); 4119 } 4120 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4121 PCIDevice *pcidev = PCI_DEVICE(dev); 4122 PCIBus *root = pci_device_root_bus(pcidev); 4123 SpaprPhbState *phb = 4124 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4125 TYPE_SPAPR_PCI_HOST_BRIDGE); 4126 4127 if (phb) { 4128 return HOTPLUG_HANDLER(phb); 4129 } 4130 } 4131 return NULL; 4132 } 4133 4134 static CpuInstanceProperties 4135 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4136 { 4137 CPUArchId *core_slot; 4138 MachineClass *mc = MACHINE_GET_CLASS(machine); 4139 4140 /* make sure possible_cpu are intialized */ 4141 mc->possible_cpu_arch_ids(machine); 4142 /* get CPU core slot containing thread that matches cpu_index */ 4143 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4144 assert(core_slot); 4145 return core_slot->props; 4146 } 4147 4148 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4149 { 4150 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4151 } 4152 4153 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4154 { 4155 int i; 4156 unsigned int smp_threads = machine->smp.threads; 4157 unsigned int smp_cpus = machine->smp.cpus; 4158 const char *core_type; 4159 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4160 MachineClass *mc = MACHINE_GET_CLASS(machine); 4161 4162 if (!mc->has_hotpluggable_cpus) { 4163 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4164 } 4165 if (machine->possible_cpus) { 4166 assert(machine->possible_cpus->len == spapr_max_cores); 4167 return machine->possible_cpus; 4168 } 4169 4170 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4171 if (!core_type) { 4172 error_report("Unable to find sPAPR CPU Core definition"); 4173 exit(1); 4174 } 4175 4176 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4177 sizeof(CPUArchId) * spapr_max_cores); 4178 machine->possible_cpus->len = spapr_max_cores; 4179 for (i = 0; i < machine->possible_cpus->len; i++) { 4180 int core_id = i * smp_threads; 4181 4182 machine->possible_cpus->cpus[i].type = core_type; 4183 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4184 machine->possible_cpus->cpus[i].arch_id = core_id; 4185 machine->possible_cpus->cpus[i].props.has_core_id = true; 4186 machine->possible_cpus->cpus[i].props.core_id = core_id; 4187 } 4188 return machine->possible_cpus; 4189 } 4190 4191 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4192 uint64_t *buid, hwaddr *pio, 4193 hwaddr *mmio32, hwaddr *mmio64, 4194 unsigned n_dma, uint32_t *liobns, 4195 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4196 { 4197 /* 4198 * New-style PHB window placement. 4199 * 4200 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4201 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4202 * windows. 4203 * 4204 * Some guest kernels can't work with MMIO windows above 1<<46 4205 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4206 * 4207 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4208 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4209 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4210 * 1TiB 64-bit MMIO windows for each PHB. 4211 */ 4212 const uint64_t base_buid = 0x800000020000000ULL; 4213 int i; 4214 4215 /* Sanity check natural alignments */ 4216 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4217 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4218 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4219 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4220 /* Sanity check bounds */ 4221 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4222 SPAPR_PCI_MEM32_WIN_SIZE); 4223 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4224 SPAPR_PCI_MEM64_WIN_SIZE); 4225 4226 if (index >= SPAPR_MAX_PHBS) { 4227 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4228 SPAPR_MAX_PHBS - 1); 4229 return; 4230 } 4231 4232 *buid = base_buid + index; 4233 for (i = 0; i < n_dma; ++i) { 4234 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4235 } 4236 4237 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4238 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4239 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4240 4241 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4242 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4243 } 4244 4245 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4246 { 4247 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4248 4249 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4250 } 4251 4252 static void spapr_ics_resend(XICSFabric *dev) 4253 { 4254 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4255 4256 ics_resend(spapr->ics); 4257 } 4258 4259 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4260 { 4261 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4262 4263 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4264 } 4265 4266 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4267 Monitor *mon) 4268 { 4269 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4270 4271 spapr_irq_print_info(spapr, mon); 4272 monitor_printf(mon, "irqchip: %s\n", 4273 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4274 } 4275 4276 /* 4277 * This is a XIVE only operation 4278 */ 4279 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4280 uint8_t nvt_blk, uint32_t nvt_idx, 4281 bool cam_ignore, uint8_t priority, 4282 uint32_t logic_serv, XiveTCTXMatch *match) 4283 { 4284 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4285 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4286 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4287 int count; 4288 4289 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4290 priority, logic_serv, match); 4291 if (count < 0) { 4292 return count; 4293 } 4294 4295 /* 4296 * When we implement the save and restore of the thread interrupt 4297 * contexts in the enter/exit CPU handlers of the machine and the 4298 * escalations in QEMU, we should be able to handle non dispatched 4299 * vCPUs. 4300 * 4301 * Until this is done, the sPAPR machine should find at least one 4302 * matching context always. 4303 */ 4304 if (count == 0) { 4305 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4306 nvt_blk, nvt_idx); 4307 } 4308 4309 return count; 4310 } 4311 4312 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4313 { 4314 return cpu->vcpu_id; 4315 } 4316 4317 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4318 { 4319 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4320 MachineState *ms = MACHINE(spapr); 4321 int vcpu_id; 4322 4323 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4324 4325 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4326 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4327 error_append_hint(errp, "Adjust the number of cpus to %d " 4328 "or try to raise the number of threads per core\n", 4329 vcpu_id * ms->smp.threads / spapr->vsmt); 4330 return; 4331 } 4332 4333 cpu->vcpu_id = vcpu_id; 4334 } 4335 4336 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4337 { 4338 CPUState *cs; 4339 4340 CPU_FOREACH(cs) { 4341 PowerPCCPU *cpu = POWERPC_CPU(cs); 4342 4343 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4344 return cpu; 4345 } 4346 } 4347 4348 return NULL; 4349 } 4350 4351 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4352 { 4353 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4354 4355 /* These are only called by TCG, KVM maintains dispatch state */ 4356 4357 spapr_cpu->prod = false; 4358 if (spapr_cpu->vpa_addr) { 4359 CPUState *cs = CPU(cpu); 4360 uint32_t dispatch; 4361 4362 dispatch = ldl_be_phys(cs->as, 4363 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4364 dispatch++; 4365 if ((dispatch & 1) != 0) { 4366 qemu_log_mask(LOG_GUEST_ERROR, 4367 "VPA: incorrect dispatch counter value for " 4368 "dispatched partition %u, correcting.\n", dispatch); 4369 dispatch++; 4370 } 4371 stl_be_phys(cs->as, 4372 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4373 } 4374 } 4375 4376 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4377 { 4378 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4379 4380 if (spapr_cpu->vpa_addr) { 4381 CPUState *cs = CPU(cpu); 4382 uint32_t dispatch; 4383 4384 dispatch = ldl_be_phys(cs->as, 4385 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4386 dispatch++; 4387 if ((dispatch & 1) != 1) { 4388 qemu_log_mask(LOG_GUEST_ERROR, 4389 "VPA: incorrect dispatch counter value for " 4390 "preempted partition %u, correcting.\n", dispatch); 4391 dispatch++; 4392 } 4393 stl_be_phys(cs->as, 4394 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4395 } 4396 } 4397 4398 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4399 { 4400 MachineClass *mc = MACHINE_CLASS(oc); 4401 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4402 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4403 NMIClass *nc = NMI_CLASS(oc); 4404 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4405 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4406 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4407 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4408 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4409 4410 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4411 mc->ignore_boot_device_suffixes = true; 4412 4413 /* 4414 * We set up the default / latest behaviour here. The class_init 4415 * functions for the specific versioned machine types can override 4416 * these details for backwards compatibility 4417 */ 4418 mc->init = spapr_machine_init; 4419 mc->reset = spapr_machine_reset; 4420 mc->block_default_type = IF_SCSI; 4421 mc->max_cpus = 1024; 4422 mc->no_parallel = 1; 4423 mc->default_boot_order = ""; 4424 mc->default_ram_size = 512 * MiB; 4425 mc->default_ram_id = "ppc_spapr.ram"; 4426 mc->default_display = "std"; 4427 mc->kvm_type = spapr_kvm_type; 4428 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4429 mc->pci_allow_0_address = true; 4430 assert(!mc->get_hotplug_handler); 4431 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4432 hc->pre_plug = spapr_machine_device_pre_plug; 4433 hc->plug = spapr_machine_device_plug; 4434 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4435 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4436 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4437 hc->unplug_request = spapr_machine_device_unplug_request; 4438 hc->unplug = spapr_machine_device_unplug; 4439 4440 smc->dr_lmb_enabled = true; 4441 smc->update_dt_enabled = true; 4442 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4443 mc->has_hotpluggable_cpus = true; 4444 mc->nvdimm_supported = true; 4445 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4446 fwc->get_dev_path = spapr_get_fw_dev_path; 4447 nc->nmi_monitor_handler = spapr_nmi; 4448 smc->phb_placement = spapr_phb_placement; 4449 vhc->hypercall = emulate_spapr_hypercall; 4450 vhc->hpt_mask = spapr_hpt_mask; 4451 vhc->map_hptes = spapr_map_hptes; 4452 vhc->unmap_hptes = spapr_unmap_hptes; 4453 vhc->hpte_set_c = spapr_hpte_set_c; 4454 vhc->hpte_set_r = spapr_hpte_set_r; 4455 vhc->get_pate = spapr_get_pate; 4456 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4457 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4458 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4459 xic->ics_get = spapr_ics_get; 4460 xic->ics_resend = spapr_ics_resend; 4461 xic->icp_get = spapr_icp_get; 4462 ispc->print_info = spapr_pic_print_info; 4463 /* Force NUMA node memory size to be a multiple of 4464 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4465 * in which LMBs are represented and hot-added 4466 */ 4467 mc->numa_mem_align_shift = 28; 4468 mc->auto_enable_numa = true; 4469 4470 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4471 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4472 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4473 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4474 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4475 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4476 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4477 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4478 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4479 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4480 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4481 spapr_caps_add_properties(smc); 4482 smc->irq = &spapr_irq_dual; 4483 smc->dr_phb_enabled = true; 4484 smc->linux_pci_probe = true; 4485 smc->smp_threads_vsmt = true; 4486 smc->nr_xirqs = SPAPR_NR_XIRQS; 4487 xfc->match_nvt = spapr_match_nvt; 4488 } 4489 4490 static const TypeInfo spapr_machine_info = { 4491 .name = TYPE_SPAPR_MACHINE, 4492 .parent = TYPE_MACHINE, 4493 .abstract = true, 4494 .instance_size = sizeof(SpaprMachineState), 4495 .instance_init = spapr_instance_init, 4496 .instance_finalize = spapr_machine_finalizefn, 4497 .class_size = sizeof(SpaprMachineClass), 4498 .class_init = spapr_machine_class_init, 4499 .interfaces = (InterfaceInfo[]) { 4500 { TYPE_FW_PATH_PROVIDER }, 4501 { TYPE_NMI }, 4502 { TYPE_HOTPLUG_HANDLER }, 4503 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4504 { TYPE_XICS_FABRIC }, 4505 { TYPE_INTERRUPT_STATS_PROVIDER }, 4506 { TYPE_XIVE_FABRIC }, 4507 { } 4508 }, 4509 }; 4510 4511 static void spapr_machine_latest_class_options(MachineClass *mc) 4512 { 4513 mc->alias = "pseries"; 4514 mc->is_default = true; 4515 } 4516 4517 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4518 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4519 void *data) \ 4520 { \ 4521 MachineClass *mc = MACHINE_CLASS(oc); \ 4522 spapr_machine_##suffix##_class_options(mc); \ 4523 if (latest) { \ 4524 spapr_machine_latest_class_options(mc); \ 4525 } \ 4526 } \ 4527 static const TypeInfo spapr_machine_##suffix##_info = { \ 4528 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4529 .parent = TYPE_SPAPR_MACHINE, \ 4530 .class_init = spapr_machine_##suffix##_class_init, \ 4531 }; \ 4532 static void spapr_machine_register_##suffix(void) \ 4533 { \ 4534 type_register(&spapr_machine_##suffix##_info); \ 4535 } \ 4536 type_init(spapr_machine_register_##suffix) 4537 4538 /* 4539 * pseries-5.2 4540 */ 4541 static void spapr_machine_5_2_class_options(MachineClass *mc) 4542 { 4543 /* Defaults for the latest behaviour inherited from the base class */ 4544 } 4545 4546 DEFINE_SPAPR_MACHINE(5_2, "5.2", true); 4547 4548 /* 4549 * pseries-5.1 4550 */ 4551 static void spapr_machine_5_1_class_options(MachineClass *mc) 4552 { 4553 spapr_machine_5_2_class_options(mc); 4554 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4555 } 4556 4557 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4558 4559 /* 4560 * pseries-5.0 4561 */ 4562 static void spapr_machine_5_0_class_options(MachineClass *mc) 4563 { 4564 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4565 static GlobalProperty compat[] = { 4566 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4567 }; 4568 4569 spapr_machine_5_1_class_options(mc); 4570 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4571 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4572 mc->numa_mem_supported = true; 4573 smc->pre_5_1_assoc_refpoints = true; 4574 } 4575 4576 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4577 4578 /* 4579 * pseries-4.2 4580 */ 4581 static void spapr_machine_4_2_class_options(MachineClass *mc) 4582 { 4583 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4584 4585 spapr_machine_5_0_class_options(mc); 4586 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4587 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4588 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4589 smc->rma_limit = 16 * GiB; 4590 mc->nvdimm_supported = false; 4591 } 4592 4593 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4594 4595 /* 4596 * pseries-4.1 4597 */ 4598 static void spapr_machine_4_1_class_options(MachineClass *mc) 4599 { 4600 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4601 static GlobalProperty compat[] = { 4602 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4603 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4604 }; 4605 4606 spapr_machine_4_2_class_options(mc); 4607 smc->linux_pci_probe = false; 4608 smc->smp_threads_vsmt = false; 4609 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4610 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4611 } 4612 4613 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4614 4615 /* 4616 * pseries-4.0 4617 */ 4618 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4619 uint64_t *buid, hwaddr *pio, 4620 hwaddr *mmio32, hwaddr *mmio64, 4621 unsigned n_dma, uint32_t *liobns, 4622 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4623 { 4624 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, 4625 nv2gpa, nv2atsd, errp); 4626 *nv2gpa = 0; 4627 *nv2atsd = 0; 4628 } 4629 4630 static void spapr_machine_4_0_class_options(MachineClass *mc) 4631 { 4632 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4633 4634 spapr_machine_4_1_class_options(mc); 4635 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4636 smc->phb_placement = phb_placement_4_0; 4637 smc->irq = &spapr_irq_xics; 4638 smc->pre_4_1_migration = true; 4639 } 4640 4641 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4642 4643 /* 4644 * pseries-3.1 4645 */ 4646 static void spapr_machine_3_1_class_options(MachineClass *mc) 4647 { 4648 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4649 4650 spapr_machine_4_0_class_options(mc); 4651 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4652 4653 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4654 smc->update_dt_enabled = false; 4655 smc->dr_phb_enabled = false; 4656 smc->broken_host_serial_model = true; 4657 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4658 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4659 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4660 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4661 } 4662 4663 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4664 4665 /* 4666 * pseries-3.0 4667 */ 4668 4669 static void spapr_machine_3_0_class_options(MachineClass *mc) 4670 { 4671 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4672 4673 spapr_machine_3_1_class_options(mc); 4674 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4675 4676 smc->legacy_irq_allocation = true; 4677 smc->nr_xirqs = 0x400; 4678 smc->irq = &spapr_irq_xics_legacy; 4679 } 4680 4681 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4682 4683 /* 4684 * pseries-2.12 4685 */ 4686 static void spapr_machine_2_12_class_options(MachineClass *mc) 4687 { 4688 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4689 static GlobalProperty compat[] = { 4690 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4691 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4692 }; 4693 4694 spapr_machine_3_0_class_options(mc); 4695 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4696 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4697 4698 /* We depend on kvm_enabled() to choose a default value for the 4699 * hpt-max-page-size capability. Of course we can't do it here 4700 * because this is too early and the HW accelerator isn't initialzed 4701 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4702 */ 4703 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4704 } 4705 4706 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4707 4708 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4709 { 4710 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4711 4712 spapr_machine_2_12_class_options(mc); 4713 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4714 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4715 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4716 } 4717 4718 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4719 4720 /* 4721 * pseries-2.11 4722 */ 4723 4724 static void spapr_machine_2_11_class_options(MachineClass *mc) 4725 { 4726 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4727 4728 spapr_machine_2_12_class_options(mc); 4729 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4730 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4731 } 4732 4733 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4734 4735 /* 4736 * pseries-2.10 4737 */ 4738 4739 static void spapr_machine_2_10_class_options(MachineClass *mc) 4740 { 4741 spapr_machine_2_11_class_options(mc); 4742 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4743 } 4744 4745 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4746 4747 /* 4748 * pseries-2.9 4749 */ 4750 4751 static void spapr_machine_2_9_class_options(MachineClass *mc) 4752 { 4753 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4754 static GlobalProperty compat[] = { 4755 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4756 }; 4757 4758 spapr_machine_2_10_class_options(mc); 4759 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4760 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4761 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4762 smc->pre_2_10_has_unused_icps = true; 4763 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4764 } 4765 4766 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4767 4768 /* 4769 * pseries-2.8 4770 */ 4771 4772 static void spapr_machine_2_8_class_options(MachineClass *mc) 4773 { 4774 static GlobalProperty compat[] = { 4775 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4776 }; 4777 4778 spapr_machine_2_9_class_options(mc); 4779 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4780 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4781 mc->numa_mem_align_shift = 23; 4782 } 4783 4784 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4785 4786 /* 4787 * pseries-2.7 4788 */ 4789 4790 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4791 uint64_t *buid, hwaddr *pio, 4792 hwaddr *mmio32, hwaddr *mmio64, 4793 unsigned n_dma, uint32_t *liobns, 4794 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4795 { 4796 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4797 const uint64_t base_buid = 0x800000020000000ULL; 4798 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4799 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4800 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4801 const uint32_t max_index = 255; 4802 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4803 4804 uint64_t ram_top = MACHINE(spapr)->ram_size; 4805 hwaddr phb0_base, phb_base; 4806 int i; 4807 4808 /* Do we have device memory? */ 4809 if (MACHINE(spapr)->maxram_size > ram_top) { 4810 /* Can't just use maxram_size, because there may be an 4811 * alignment gap between normal and device memory regions 4812 */ 4813 ram_top = MACHINE(spapr)->device_memory->base + 4814 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4815 } 4816 4817 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4818 4819 if (index > max_index) { 4820 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4821 max_index); 4822 return; 4823 } 4824 4825 *buid = base_buid + index; 4826 for (i = 0; i < n_dma; ++i) { 4827 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4828 } 4829 4830 phb_base = phb0_base + index * phb_spacing; 4831 *pio = phb_base + pio_offset; 4832 *mmio32 = phb_base + mmio_offset; 4833 /* 4834 * We don't set the 64-bit MMIO window, relying on the PHB's 4835 * fallback behaviour of automatically splitting a large "32-bit" 4836 * window into contiguous 32-bit and 64-bit windows 4837 */ 4838 4839 *nv2gpa = 0; 4840 *nv2atsd = 0; 4841 } 4842 4843 static void spapr_machine_2_7_class_options(MachineClass *mc) 4844 { 4845 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4846 static GlobalProperty compat[] = { 4847 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4848 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4849 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4850 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4851 }; 4852 4853 spapr_machine_2_8_class_options(mc); 4854 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4855 mc->default_machine_opts = "modern-hotplug-events=off"; 4856 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4857 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4858 smc->phb_placement = phb_placement_2_7; 4859 } 4860 4861 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4862 4863 /* 4864 * pseries-2.6 4865 */ 4866 4867 static void spapr_machine_2_6_class_options(MachineClass *mc) 4868 { 4869 static GlobalProperty compat[] = { 4870 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4871 }; 4872 4873 spapr_machine_2_7_class_options(mc); 4874 mc->has_hotpluggable_cpus = false; 4875 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4876 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4877 } 4878 4879 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4880 4881 /* 4882 * pseries-2.5 4883 */ 4884 4885 static void spapr_machine_2_5_class_options(MachineClass *mc) 4886 { 4887 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4888 static GlobalProperty compat[] = { 4889 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4890 }; 4891 4892 spapr_machine_2_6_class_options(mc); 4893 smc->use_ohci_by_default = true; 4894 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4895 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4896 } 4897 4898 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4899 4900 /* 4901 * pseries-2.4 4902 */ 4903 4904 static void spapr_machine_2_4_class_options(MachineClass *mc) 4905 { 4906 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4907 4908 spapr_machine_2_5_class_options(mc); 4909 smc->dr_lmb_enabled = false; 4910 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4911 } 4912 4913 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4914 4915 /* 4916 * pseries-2.3 4917 */ 4918 4919 static void spapr_machine_2_3_class_options(MachineClass *mc) 4920 { 4921 static GlobalProperty compat[] = { 4922 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4923 }; 4924 spapr_machine_2_4_class_options(mc); 4925 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4926 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4927 } 4928 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4929 4930 /* 4931 * pseries-2.2 4932 */ 4933 4934 static void spapr_machine_2_2_class_options(MachineClass *mc) 4935 { 4936 static GlobalProperty compat[] = { 4937 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4938 }; 4939 4940 spapr_machine_2_3_class_options(mc); 4941 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4942 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4943 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4944 } 4945 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4946 4947 /* 4948 * pseries-2.1 4949 */ 4950 4951 static void spapr_machine_2_1_class_options(MachineClass *mc) 4952 { 4953 spapr_machine_2_2_class_options(mc); 4954 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4955 } 4956 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4957 4958 static void spapr_machine_register_types(void) 4959 { 4960 type_register_static(&spapr_machine_info); 4961 } 4962 4963 type_init(spapr_machine_register_types) 4964