1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "sysemu/sysemu.h" 28 #include "hw/hw.h" 29 #include "hw/fw-path-provider.h" 30 #include "elf.h" 31 #include "net/net.h" 32 #include "sysemu/blockdev.h" 33 #include "sysemu/cpus.h" 34 #include "sysemu/kvm.h" 35 #include "kvm_ppc.h" 36 #include "mmu-hash64.h" 37 #include "qom/cpu.h" 38 39 #include "hw/boards.h" 40 #include "hw/ppc/ppc.h" 41 #include "hw/loader.h" 42 43 #include "hw/ppc/spapr.h" 44 #include "hw/ppc/spapr_vio.h" 45 #include "hw/pci-host/spapr.h" 46 #include "hw/ppc/xics.h" 47 #include "hw/pci/msi.h" 48 49 #include "hw/pci/pci.h" 50 #include "hw/scsi/scsi.h" 51 #include "hw/virtio/virtio-scsi.h" 52 53 #include "exec/address-spaces.h" 54 #include "hw/usb.h" 55 #include "qemu/config-file.h" 56 #include "qemu/error-report.h" 57 #include "trace.h" 58 #include "hw/nmi.h" 59 60 #include <libfdt.h> 61 62 /* SLOF memory layout: 63 * 64 * SLOF raw image loaded at 0, copies its romfs right below the flat 65 * device-tree, then position SLOF itself 31M below that 66 * 67 * So we set FW_OVERHEAD to 40MB which should account for all of that 68 * and more 69 * 70 * We load our kernel at 4M, leaving space for SLOF initial image 71 */ 72 #define FDT_MAX_SIZE 0x40000 73 #define RTAS_MAX_SIZE 0x10000 74 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 75 #define FW_MAX_SIZE 0x400000 76 #define FW_FILE_NAME "slof.bin" 77 #define FW_OVERHEAD 0x2800000 78 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 79 80 #define MIN_RMA_SLOF 128UL 81 82 #define TIMEBASE_FREQ 512000000ULL 83 84 #define MAX_CPUS 255 85 86 #define PHANDLE_XICP 0x00001111 87 88 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 89 90 typedef struct sPAPRMachineState sPAPRMachineState; 91 92 #define TYPE_SPAPR_MACHINE "spapr-machine" 93 #define SPAPR_MACHINE(obj) \ 94 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 95 96 /** 97 * sPAPRMachineState: 98 */ 99 struct sPAPRMachineState { 100 /*< private >*/ 101 MachineState parent_obj; 102 103 /*< public >*/ 104 char *kvm_type; 105 }; 106 107 sPAPREnvironment *spapr; 108 109 static XICSState *try_create_xics(const char *type, int nr_servers, 110 int nr_irqs) 111 { 112 DeviceState *dev; 113 114 dev = qdev_create(NULL, type); 115 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 116 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 117 if (qdev_init(dev) < 0) { 118 return NULL; 119 } 120 121 return XICS_COMMON(dev); 122 } 123 124 static XICSState *xics_system_init(int nr_servers, int nr_irqs) 125 { 126 XICSState *icp = NULL; 127 128 if (kvm_enabled()) { 129 QemuOpts *machine_opts = qemu_get_machine_opts(); 130 bool irqchip_allowed = qemu_opt_get_bool(machine_opts, 131 "kernel_irqchip", true); 132 bool irqchip_required = qemu_opt_get_bool(machine_opts, 133 "kernel_irqchip", false); 134 if (irqchip_allowed) { 135 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs); 136 } 137 138 if (irqchip_required && !icp) { 139 perror("Failed to create in-kernel XICS\n"); 140 abort(); 141 } 142 } 143 144 if (!icp) { 145 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs); 146 } 147 148 if (!icp) { 149 perror("Failed to create XICS\n"); 150 abort(); 151 } 152 153 return icp; 154 } 155 156 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 157 int smt_threads) 158 { 159 int i, ret = 0; 160 uint32_t servers_prop[smt_threads]; 161 uint32_t gservers_prop[smt_threads * 2]; 162 int index = ppc_get_vcpu_dt_id(cpu); 163 164 if (cpu->cpu_version) { 165 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); 166 if (ret < 0) { 167 return ret; 168 } 169 } 170 171 /* Build interrupt servers and gservers properties */ 172 for (i = 0; i < smt_threads; i++) { 173 servers_prop[i] = cpu_to_be32(index + i); 174 /* Hack, direct the group queues back to cpu 0 */ 175 gservers_prop[i*2] = cpu_to_be32(index + i); 176 gservers_prop[i*2 + 1] = 0; 177 } 178 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 179 servers_prop, sizeof(servers_prop)); 180 if (ret < 0) { 181 return ret; 182 } 183 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 184 gservers_prop, sizeof(gservers_prop)); 185 186 return ret; 187 } 188 189 static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) 190 { 191 int ret = 0, offset, cpus_offset; 192 CPUState *cs; 193 char cpu_model[32]; 194 int smt = kvmppc_smt_threads(); 195 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 196 197 CPU_FOREACH(cs) { 198 PowerPCCPU *cpu = POWERPC_CPU(cs); 199 DeviceClass *dc = DEVICE_GET_CLASS(cs); 200 int index = ppc_get_vcpu_dt_id(cpu); 201 uint32_t associativity[] = {cpu_to_be32(0x5), 202 cpu_to_be32(0x0), 203 cpu_to_be32(0x0), 204 cpu_to_be32(0x0), 205 cpu_to_be32(cs->numa_node), 206 cpu_to_be32(index)}; 207 208 if ((index % smt) != 0) { 209 continue; 210 } 211 212 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 213 214 cpus_offset = fdt_path_offset(fdt, "/cpus"); 215 if (cpus_offset < 0) { 216 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 217 "cpus"); 218 if (cpus_offset < 0) { 219 return cpus_offset; 220 } 221 } 222 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 223 if (offset < 0) { 224 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 225 if (offset < 0) { 226 return offset; 227 } 228 } 229 230 if (nb_numa_nodes > 1) { 231 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 232 sizeof(associativity)); 233 if (ret < 0) { 234 return ret; 235 } 236 } 237 238 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 239 pft_size_prop, sizeof(pft_size_prop)); 240 if (ret < 0) { 241 return ret; 242 } 243 244 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 245 ppc_get_compat_smt_threads(cpu)); 246 if (ret < 0) { 247 return ret; 248 } 249 } 250 return ret; 251 } 252 253 254 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 255 size_t maxsize) 256 { 257 size_t maxcells = maxsize / sizeof(uint32_t); 258 int i, j, count; 259 uint32_t *p = prop; 260 261 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 262 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 263 264 if (!sps->page_shift) { 265 break; 266 } 267 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 268 if (sps->enc[count].page_shift == 0) { 269 break; 270 } 271 } 272 if ((p - prop) >= (maxcells - 3 - count * 2)) { 273 break; 274 } 275 *(p++) = cpu_to_be32(sps->page_shift); 276 *(p++) = cpu_to_be32(sps->slb_enc); 277 *(p++) = cpu_to_be32(count); 278 for (j = 0; j < count; j++) { 279 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 280 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 281 } 282 } 283 284 return (p - prop) * sizeof(uint32_t); 285 } 286 287 static hwaddr spapr_node0_size(void) 288 { 289 if (nb_numa_nodes) { 290 int i; 291 for (i = 0; i < nb_numa_nodes; ++i) { 292 if (numa_info[i].node_mem) { 293 return MIN(pow2floor(numa_info[i].node_mem), ram_size); 294 } 295 } 296 } 297 return ram_size; 298 } 299 300 #define _FDT(exp) \ 301 do { \ 302 int ret = (exp); \ 303 if (ret < 0) { \ 304 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 305 #exp, fdt_strerror(ret)); \ 306 exit(1); \ 307 } \ 308 } while (0) 309 310 static void add_str(GString *s, const gchar *s1) 311 { 312 g_string_append_len(s, s1, strlen(s1) + 1); 313 } 314 315 static void *spapr_create_fdt_skel(hwaddr initrd_base, 316 hwaddr initrd_size, 317 hwaddr kernel_size, 318 bool little_endian, 319 const char *boot_device, 320 const char *kernel_cmdline, 321 uint32_t epow_irq) 322 { 323 void *fdt; 324 CPUState *cs; 325 uint32_t start_prop = cpu_to_be32(initrd_base); 326 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 327 GString *hypertas = g_string_sized_new(256); 328 GString *qemu_hypertas = g_string_sized_new(256); 329 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 330 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; 331 int smt = kvmppc_smt_threads(); 332 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 333 QemuOpts *opts = qemu_opts_find(qemu_find_opts("smp-opts"), NULL); 334 unsigned sockets = opts ? qemu_opt_get_number(opts, "sockets", 0) : 0; 335 uint32_t cpus_per_socket = sockets ? (smp_cpus / sockets) : 1; 336 char *buf; 337 338 add_str(hypertas, "hcall-pft"); 339 add_str(hypertas, "hcall-term"); 340 add_str(hypertas, "hcall-dabr"); 341 add_str(hypertas, "hcall-interrupt"); 342 add_str(hypertas, "hcall-tce"); 343 add_str(hypertas, "hcall-vio"); 344 add_str(hypertas, "hcall-splpar"); 345 add_str(hypertas, "hcall-bulk"); 346 add_str(hypertas, "hcall-set-mode"); 347 add_str(qemu_hypertas, "hcall-memop1"); 348 349 fdt = g_malloc0(FDT_MAX_SIZE); 350 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 351 352 if (kernel_size) { 353 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 354 } 355 if (initrd_size) { 356 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 357 } 358 _FDT((fdt_finish_reservemap(fdt))); 359 360 /* Root node */ 361 _FDT((fdt_begin_node(fdt, ""))); 362 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 363 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 364 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 365 366 if (kvm_enabled()) { 367 _FDT((fdt_property_string(fdt, "hypervisor", "kvm"))); 368 } 369 370 /* 371 * Add info to guest to indentify which host is it being run on 372 * and what is the uuid of the guest 373 */ 374 if (kvmppc_get_host_model(&buf)) { 375 _FDT((fdt_property_string(fdt, "host-model", buf))); 376 g_free(buf); 377 } 378 if (kvmppc_get_host_serial(&buf)) { 379 _FDT((fdt_property_string(fdt, "host-serial", buf))); 380 g_free(buf); 381 } 382 383 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1], 384 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4], 385 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7], 386 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10], 387 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13], 388 qemu_uuid[14], qemu_uuid[15]); 389 390 _FDT((fdt_property_string(fdt, "vm,uuid", buf))); 391 g_free(buf); 392 393 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 394 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 395 396 /* /chosen */ 397 _FDT((fdt_begin_node(fdt, "chosen"))); 398 399 /* Set Form1_affinity */ 400 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 401 402 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 403 _FDT((fdt_property(fdt, "linux,initrd-start", 404 &start_prop, sizeof(start_prop)))); 405 _FDT((fdt_property(fdt, "linux,initrd-end", 406 &end_prop, sizeof(end_prop)))); 407 if (kernel_size) { 408 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 409 cpu_to_be64(kernel_size) }; 410 411 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 412 if (little_endian) { 413 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 414 } 415 } 416 if (boot_device) { 417 _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device))); 418 } 419 if (boot_menu) { 420 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); 421 } 422 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 423 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 424 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 425 426 _FDT((fdt_end_node(fdt))); 427 428 /* cpus */ 429 _FDT((fdt_begin_node(fdt, "cpus"))); 430 431 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 432 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 433 434 CPU_FOREACH(cs) { 435 PowerPCCPU *cpu = POWERPC_CPU(cs); 436 CPUPPCState *env = &cpu->env; 437 DeviceClass *dc = DEVICE_GET_CLASS(cs); 438 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 439 int index = ppc_get_vcpu_dt_id(cpu); 440 char *nodename; 441 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 442 0xffffffff, 0xffffffff}; 443 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 444 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 445 uint32_t page_sizes_prop[64]; 446 size_t page_sizes_prop_size; 447 448 if ((index % smt) != 0) { 449 continue; 450 } 451 452 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 453 454 _FDT((fdt_begin_node(fdt, nodename))); 455 456 g_free(nodename); 457 458 _FDT((fdt_property_cell(fdt, "reg", index))); 459 _FDT((fdt_property_string(fdt, "device_type", "cpu"))); 460 461 _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); 462 _FDT((fdt_property_cell(fdt, "d-cache-block-size", 463 env->dcache_line_size))); 464 _FDT((fdt_property_cell(fdt, "d-cache-line-size", 465 env->dcache_line_size))); 466 _FDT((fdt_property_cell(fdt, "i-cache-block-size", 467 env->icache_line_size))); 468 _FDT((fdt_property_cell(fdt, "i-cache-line-size", 469 env->icache_line_size))); 470 471 if (pcc->l1_dcache_size) { 472 _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size))); 473 } else { 474 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 475 } 476 if (pcc->l1_icache_size) { 477 _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size))); 478 } else { 479 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 480 } 481 482 _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq))); 483 _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq))); 484 _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); 485 _FDT((fdt_property_string(fdt, "status", "okay"))); 486 _FDT((fdt_property(fdt, "64-bit", NULL, 0))); 487 488 if (env->spr_cb[SPR_PURR].oea_read) { 489 _FDT((fdt_property(fdt, "ibm,purr", NULL, 0))); 490 } 491 492 if (env->mmu_model & POWERPC_MMU_1TSEG) { 493 _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", 494 segs, sizeof(segs)))); 495 } 496 497 /* Advertise VMX/VSX (vector extensions) if available 498 * 0 / no property == no vector extensions 499 * 1 == VMX / Altivec available 500 * 2 == VSX available */ 501 if (env->insns_flags & PPC_ALTIVEC) { 502 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 503 504 _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx))); 505 } 506 507 /* Advertise DFP (Decimal Floating Point) if available 508 * 0 / no property == no DFP 509 * 1 == DFP available */ 510 if (env->insns_flags2 & PPC2_DFP) { 511 _FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); 512 } 513 514 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 515 sizeof(page_sizes_prop)); 516 if (page_sizes_prop_size) { 517 _FDT((fdt_property(fdt, "ibm,segment-page-sizes", 518 page_sizes_prop, page_sizes_prop_size))); 519 } 520 521 _FDT((fdt_property_cell(fdt, "ibm,chip-id", 522 cs->cpu_index / cpus_per_socket))); 523 524 _FDT((fdt_end_node(fdt))); 525 } 526 527 _FDT((fdt_end_node(fdt))); 528 529 /* RTAS */ 530 _FDT((fdt_begin_node(fdt, "rtas"))); 531 532 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 533 add_str(hypertas, "hcall-multi-tce"); 534 } 535 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, 536 hypertas->len))); 537 g_string_free(hypertas, TRUE); 538 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, 539 qemu_hypertas->len))); 540 g_string_free(qemu_hypertas, TRUE); 541 542 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 543 refpoints, sizeof(refpoints)))); 544 545 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 546 547 /* 548 * According to PAPR, rtas ibm,os-term, does not gaurantee a return 549 * back to the guest cpu. 550 * 551 * While an additional ibm,extended-os-term property indicates that 552 * rtas call return will always occur. Set this property. 553 */ 554 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0))); 555 556 _FDT((fdt_end_node(fdt))); 557 558 /* interrupt controller */ 559 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 560 561 _FDT((fdt_property_string(fdt, "device_type", 562 "PowerPC-External-Interrupt-Presentation"))); 563 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 564 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 565 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 566 interrupt_server_ranges_prop, 567 sizeof(interrupt_server_ranges_prop)))); 568 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 569 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 570 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 571 572 _FDT((fdt_end_node(fdt))); 573 574 /* vdevice */ 575 _FDT((fdt_begin_node(fdt, "vdevice"))); 576 577 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 578 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 579 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 580 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 581 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 582 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 583 584 _FDT((fdt_end_node(fdt))); 585 586 /* event-sources */ 587 spapr_events_fdt_skel(fdt, epow_irq); 588 589 /* /hypervisor node */ 590 if (kvm_enabled()) { 591 uint8_t hypercall[16]; 592 593 /* indicate KVM hypercall interface */ 594 _FDT((fdt_begin_node(fdt, "hypervisor"))); 595 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); 596 if (kvmppc_has_cap_fixup_hcalls()) { 597 /* 598 * Older KVM versions with older guest kernels were broken with the 599 * magic page, don't allow the guest to map it. 600 */ 601 kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 602 sizeof(hypercall)); 603 _FDT((fdt_property(fdt, "hcall-instructions", hypercall, 604 sizeof(hypercall)))); 605 } 606 _FDT((fdt_end_node(fdt))); 607 } 608 609 _FDT((fdt_end_node(fdt))); /* close root node */ 610 _FDT((fdt_finish(fdt))); 611 612 return fdt; 613 } 614 615 int spapr_h_cas_compose_response(target_ulong addr, target_ulong size) 616 { 617 void *fdt, *fdt_skel; 618 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 619 620 size -= sizeof(hdr); 621 622 /* Create sceleton */ 623 fdt_skel = g_malloc0(size); 624 _FDT((fdt_create(fdt_skel, size))); 625 _FDT((fdt_begin_node(fdt_skel, ""))); 626 _FDT((fdt_end_node(fdt_skel))); 627 _FDT((fdt_finish(fdt_skel))); 628 fdt = g_malloc0(size); 629 _FDT((fdt_open_into(fdt_skel, fdt, size))); 630 g_free(fdt_skel); 631 632 /* Fix skeleton up */ 633 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 634 635 /* Pack resulting tree */ 636 _FDT((fdt_pack(fdt))); 637 638 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 639 trace_spapr_cas_failed(size); 640 return -1; 641 } 642 643 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 644 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 645 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 646 g_free(fdt); 647 648 return 0; 649 } 650 651 static void spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 652 hwaddr size) 653 { 654 uint32_t associativity[] = { 655 cpu_to_be32(0x4), /* length */ 656 cpu_to_be32(0x0), cpu_to_be32(0x0), 657 cpu_to_be32(0x0), cpu_to_be32(nodeid) 658 }; 659 char mem_name[32]; 660 uint64_t mem_reg_property[2]; 661 int off; 662 663 mem_reg_property[0] = cpu_to_be64(start); 664 mem_reg_property[1] = cpu_to_be64(size); 665 666 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 667 off = fdt_add_subnode(fdt, 0, mem_name); 668 _FDT(off); 669 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 670 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 671 sizeof(mem_reg_property)))); 672 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 673 sizeof(associativity)))); 674 } 675 676 static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt) 677 { 678 hwaddr mem_start, node_size; 679 int i, nb_nodes = nb_numa_nodes; 680 NodeInfo *nodes = numa_info; 681 NodeInfo ramnode; 682 683 /* No NUMA nodes, assume there is just one node with whole RAM */ 684 if (!nb_numa_nodes) { 685 nb_nodes = 1; 686 ramnode.node_mem = ram_size; 687 nodes = &ramnode; 688 } 689 690 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 691 if (!nodes[i].node_mem) { 692 continue; 693 } 694 if (mem_start >= ram_size) { 695 node_size = 0; 696 } else { 697 node_size = nodes[i].node_mem; 698 if (node_size > ram_size - mem_start) { 699 node_size = ram_size - mem_start; 700 } 701 } 702 if (!mem_start) { 703 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 704 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 705 mem_start += spapr->rma_size; 706 node_size -= spapr->rma_size; 707 } 708 for ( ; node_size; ) { 709 hwaddr sizetmp = pow2floor(node_size); 710 711 /* mem_start != 0 here */ 712 if (ctzl(mem_start) < ctzl(sizetmp)) { 713 sizetmp = 1ULL << ctzl(mem_start); 714 } 715 716 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 717 node_size -= sizetmp; 718 mem_start += sizetmp; 719 } 720 } 721 722 return 0; 723 } 724 725 static void spapr_finalize_fdt(sPAPREnvironment *spapr, 726 hwaddr fdt_addr, 727 hwaddr rtas_addr, 728 hwaddr rtas_size) 729 { 730 int ret, i; 731 size_t cb = 0; 732 char *bootlist; 733 void *fdt; 734 sPAPRPHBState *phb; 735 736 fdt = g_malloc(FDT_MAX_SIZE); 737 738 /* open out the base tree into a temp buffer for the final tweaks */ 739 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 740 741 ret = spapr_populate_memory(spapr, fdt); 742 if (ret < 0) { 743 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 744 exit(1); 745 } 746 747 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 748 if (ret < 0) { 749 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 750 exit(1); 751 } 752 753 QLIST_FOREACH(phb, &spapr->phbs, list) { 754 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 755 } 756 757 if (ret < 0) { 758 fprintf(stderr, "couldn't setup PCI devices in fdt\n"); 759 exit(1); 760 } 761 762 /* RTAS */ 763 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 764 if (ret < 0) { 765 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 766 } 767 768 /* Advertise NUMA via ibm,associativity */ 769 ret = spapr_fixup_cpu_dt(fdt, spapr); 770 if (ret < 0) { 771 fprintf(stderr, "Couldn't finalize CPU device tree properties\n"); 772 } 773 774 bootlist = get_boot_devices_list(&cb, true); 775 if (cb && bootlist) { 776 int offset = fdt_path_offset(fdt, "/chosen"); 777 if (offset < 0) { 778 exit(1); 779 } 780 for (i = 0; i < cb; i++) { 781 if (bootlist[i] == '\n') { 782 bootlist[i] = ' '; 783 } 784 785 } 786 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); 787 } 788 789 if (!spapr->has_graphics) { 790 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 791 } 792 793 _FDT((fdt_pack(fdt))); 794 795 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 796 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n", 797 fdt_totalsize(fdt), FDT_MAX_SIZE); 798 exit(1); 799 } 800 801 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 802 803 g_free(bootlist); 804 g_free(fdt); 805 } 806 807 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 808 { 809 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 810 } 811 812 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 813 { 814 CPUPPCState *env = &cpu->env; 815 816 if (msr_pr) { 817 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 818 env->gpr[3] = H_PRIVILEGE; 819 } else { 820 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 821 } 822 } 823 824 static void spapr_reset_htab(sPAPREnvironment *spapr) 825 { 826 long shift; 827 828 /* allocate hash page table. For now we always make this 16mb, 829 * later we should probably make it scale to the size of guest 830 * RAM */ 831 832 shift = kvmppc_reset_htab(spapr->htab_shift); 833 834 if (shift > 0) { 835 /* Kernel handles htab, we don't need to allocate one */ 836 spapr->htab_shift = shift; 837 kvmppc_kern_htab = true; 838 } else { 839 if (!spapr->htab) { 840 /* Allocate an htab if we don't yet have one */ 841 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); 842 } 843 844 /* And clear it */ 845 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 846 } 847 848 /* Update the RMA size if necessary */ 849 if (spapr->vrma_adjust) { 850 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 851 spapr->htab_shift); 852 } 853 } 854 855 static void ppc_spapr_reset(void) 856 { 857 PowerPCCPU *first_ppc_cpu; 858 uint32_t rtas_limit; 859 860 /* Reset the hash table & recalc the RMA */ 861 spapr_reset_htab(spapr); 862 863 qemu_devices_reset(); 864 865 /* 866 * We place the device tree and RTAS just below either the top of the RMA, 867 * or just below 2GB, whichever is lowere, so that it can be 868 * processed with 32-bit real mode code if necessary 869 */ 870 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 871 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 872 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 873 874 /* Load the fdt */ 875 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 876 spapr->rtas_size); 877 878 /* Copy RTAS over */ 879 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob, 880 spapr->rtas_size); 881 882 /* Set up the entry state */ 883 first_ppc_cpu = POWERPC_CPU(first_cpu); 884 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 885 first_ppc_cpu->env.gpr[5] = 0; 886 first_cpu->halted = 0; 887 first_ppc_cpu->env.nip = spapr->entry_point; 888 889 } 890 891 static void spapr_cpu_reset(void *opaque) 892 { 893 PowerPCCPU *cpu = opaque; 894 CPUState *cs = CPU(cpu); 895 CPUPPCState *env = &cpu->env; 896 897 cpu_reset(cs); 898 899 /* All CPUs start halted. CPU0 is unhalted from the machine level 900 * reset code and the rest are explicitly started up by the guest 901 * using an RTAS call */ 902 cs->halted = 1; 903 904 env->spr[SPR_HIOR] = 0; 905 906 env->external_htab = (uint8_t *)spapr->htab; 907 if (kvm_enabled() && !env->external_htab) { 908 /* 909 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte* 910 * functions do the right thing. 911 */ 912 env->external_htab = (void *)1; 913 } 914 env->htab_base = -1; 915 /* 916 * htab_mask is the mask used to normalize hash value to PTEG index. 917 * htab_shift is log2 of hash table size. 918 * We have 8 hpte per group, and each hpte is 16 bytes. 919 * ie have 128 bytes per hpte entry. 920 */ 921 env->htab_mask = (1ULL << ((spapr)->htab_shift - 7)) - 1; 922 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | 923 (spapr->htab_shift - 18); 924 } 925 926 static void spapr_create_nvram(sPAPREnvironment *spapr) 927 { 928 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 929 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 930 931 if (dinfo) { 932 qdev_prop_set_drive_nofail(dev, "drive", dinfo->bdrv); 933 } 934 935 qdev_init_nofail(dev); 936 937 spapr->nvram = (struct sPAPRNVRAM *)dev; 938 } 939 940 /* Returns whether we want to use VGA or not */ 941 static int spapr_vga_init(PCIBus *pci_bus) 942 { 943 switch (vga_interface_type) { 944 case VGA_NONE: 945 return false; 946 case VGA_DEVICE: 947 return true; 948 case VGA_STD: 949 return pci_vga_init(pci_bus) != NULL; 950 default: 951 fprintf(stderr, "This vga model is not supported," 952 "currently it only supports -vga std\n"); 953 exit(0); 954 } 955 } 956 957 static const VMStateDescription vmstate_spapr = { 958 .name = "spapr", 959 .version_id = 2, 960 .minimum_version_id = 1, 961 .fields = (VMStateField[]) { 962 VMSTATE_UNUSED(4), /* used to be @next_irq */ 963 964 /* RTC offset */ 965 VMSTATE_UINT64(rtc_offset, sPAPREnvironment), 966 VMSTATE_PPC_TIMEBASE_V(tb, sPAPREnvironment, 2), 967 VMSTATE_END_OF_LIST() 968 }, 969 }; 970 971 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 972 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 973 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 974 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 975 976 static int htab_save_setup(QEMUFile *f, void *opaque) 977 { 978 sPAPREnvironment *spapr = opaque; 979 980 /* "Iteration" header */ 981 qemu_put_be32(f, spapr->htab_shift); 982 983 if (spapr->htab) { 984 spapr->htab_save_index = 0; 985 spapr->htab_first_pass = true; 986 } else { 987 assert(kvm_enabled()); 988 989 spapr->htab_fd = kvmppc_get_htab_fd(false); 990 if (spapr->htab_fd < 0) { 991 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", 992 strerror(errno)); 993 return -1; 994 } 995 } 996 997 998 return 0; 999 } 1000 1001 static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr, 1002 int64_t max_ns) 1003 { 1004 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1005 int index = spapr->htab_save_index; 1006 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1007 1008 assert(spapr->htab_first_pass); 1009 1010 do { 1011 int chunkstart; 1012 1013 /* Consume invalid HPTEs */ 1014 while ((index < htabslots) 1015 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1016 index++; 1017 CLEAN_HPTE(HPTE(spapr->htab, index)); 1018 } 1019 1020 /* Consume valid HPTEs */ 1021 chunkstart = index; 1022 while ((index < htabslots) 1023 && HPTE_VALID(HPTE(spapr->htab, index))) { 1024 index++; 1025 CLEAN_HPTE(HPTE(spapr->htab, index)); 1026 } 1027 1028 if (index > chunkstart) { 1029 int n_valid = index - chunkstart; 1030 1031 qemu_put_be32(f, chunkstart); 1032 qemu_put_be16(f, n_valid); 1033 qemu_put_be16(f, 0); 1034 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1035 HASH_PTE_SIZE_64 * n_valid); 1036 1037 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1038 break; 1039 } 1040 } 1041 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1042 1043 if (index >= htabslots) { 1044 assert(index == htabslots); 1045 index = 0; 1046 spapr->htab_first_pass = false; 1047 } 1048 spapr->htab_save_index = index; 1049 } 1050 1051 static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, 1052 int64_t max_ns) 1053 { 1054 bool final = max_ns < 0; 1055 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1056 int examined = 0, sent = 0; 1057 int index = spapr->htab_save_index; 1058 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1059 1060 assert(!spapr->htab_first_pass); 1061 1062 do { 1063 int chunkstart, invalidstart; 1064 1065 /* Consume non-dirty HPTEs */ 1066 while ((index < htabslots) 1067 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1068 index++; 1069 examined++; 1070 } 1071 1072 chunkstart = index; 1073 /* Consume valid dirty HPTEs */ 1074 while ((index < htabslots) 1075 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1076 && HPTE_VALID(HPTE(spapr->htab, index))) { 1077 CLEAN_HPTE(HPTE(spapr->htab, index)); 1078 index++; 1079 examined++; 1080 } 1081 1082 invalidstart = index; 1083 /* Consume invalid dirty HPTEs */ 1084 while ((index < htabslots) 1085 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1086 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1087 CLEAN_HPTE(HPTE(spapr->htab, index)); 1088 index++; 1089 examined++; 1090 } 1091 1092 if (index > chunkstart) { 1093 int n_valid = invalidstart - chunkstart; 1094 int n_invalid = index - invalidstart; 1095 1096 qemu_put_be32(f, chunkstart); 1097 qemu_put_be16(f, n_valid); 1098 qemu_put_be16(f, n_invalid); 1099 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1100 HASH_PTE_SIZE_64 * n_valid); 1101 sent += index - chunkstart; 1102 1103 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1104 break; 1105 } 1106 } 1107 1108 if (examined >= htabslots) { 1109 break; 1110 } 1111 1112 if (index >= htabslots) { 1113 assert(index == htabslots); 1114 index = 0; 1115 } 1116 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1117 1118 if (index >= htabslots) { 1119 assert(index == htabslots); 1120 index = 0; 1121 } 1122 1123 spapr->htab_save_index = index; 1124 1125 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1126 } 1127 1128 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1129 #define MAX_KVM_BUF_SIZE 2048 1130 1131 static int htab_save_iterate(QEMUFile *f, void *opaque) 1132 { 1133 sPAPREnvironment *spapr = opaque; 1134 int rc = 0; 1135 1136 /* Iteration header */ 1137 qemu_put_be32(f, 0); 1138 1139 if (!spapr->htab) { 1140 assert(kvm_enabled()); 1141 1142 rc = kvmppc_save_htab(f, spapr->htab_fd, 1143 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1144 if (rc < 0) { 1145 return rc; 1146 } 1147 } else if (spapr->htab_first_pass) { 1148 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1149 } else { 1150 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1151 } 1152 1153 /* End marker */ 1154 qemu_put_be32(f, 0); 1155 qemu_put_be16(f, 0); 1156 qemu_put_be16(f, 0); 1157 1158 return rc; 1159 } 1160 1161 static int htab_save_complete(QEMUFile *f, void *opaque) 1162 { 1163 sPAPREnvironment *spapr = opaque; 1164 1165 /* Iteration header */ 1166 qemu_put_be32(f, 0); 1167 1168 if (!spapr->htab) { 1169 int rc; 1170 1171 assert(kvm_enabled()); 1172 1173 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); 1174 if (rc < 0) { 1175 return rc; 1176 } 1177 close(spapr->htab_fd); 1178 spapr->htab_fd = -1; 1179 } else { 1180 htab_save_later_pass(f, spapr, -1); 1181 } 1182 1183 /* End marker */ 1184 qemu_put_be32(f, 0); 1185 qemu_put_be16(f, 0); 1186 qemu_put_be16(f, 0); 1187 1188 return 0; 1189 } 1190 1191 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1192 { 1193 sPAPREnvironment *spapr = opaque; 1194 uint32_t section_hdr; 1195 int fd = -1; 1196 1197 if (version_id < 1 || version_id > 1) { 1198 fprintf(stderr, "htab_load() bad version\n"); 1199 return -EINVAL; 1200 } 1201 1202 section_hdr = qemu_get_be32(f); 1203 1204 if (section_hdr) { 1205 /* First section, just the hash shift */ 1206 if (spapr->htab_shift != section_hdr) { 1207 return -EINVAL; 1208 } 1209 return 0; 1210 } 1211 1212 if (!spapr->htab) { 1213 assert(kvm_enabled()); 1214 1215 fd = kvmppc_get_htab_fd(true); 1216 if (fd < 0) { 1217 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", 1218 strerror(errno)); 1219 } 1220 } 1221 1222 while (true) { 1223 uint32_t index; 1224 uint16_t n_valid, n_invalid; 1225 1226 index = qemu_get_be32(f); 1227 n_valid = qemu_get_be16(f); 1228 n_invalid = qemu_get_be16(f); 1229 1230 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1231 /* End of Stream */ 1232 break; 1233 } 1234 1235 if ((index + n_valid + n_invalid) > 1236 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1237 /* Bad index in stream */ 1238 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " 1239 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, 1240 spapr->htab_shift); 1241 return -EINVAL; 1242 } 1243 1244 if (spapr->htab) { 1245 if (n_valid) { 1246 qemu_get_buffer(f, HPTE(spapr->htab, index), 1247 HASH_PTE_SIZE_64 * n_valid); 1248 } 1249 if (n_invalid) { 1250 memset(HPTE(spapr->htab, index + n_valid), 0, 1251 HASH_PTE_SIZE_64 * n_invalid); 1252 } 1253 } else { 1254 int rc; 1255 1256 assert(fd >= 0); 1257 1258 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1259 if (rc < 0) { 1260 return rc; 1261 } 1262 } 1263 } 1264 1265 if (!spapr->htab) { 1266 assert(fd >= 0); 1267 close(fd); 1268 } 1269 1270 return 0; 1271 } 1272 1273 static SaveVMHandlers savevm_htab_handlers = { 1274 .save_live_setup = htab_save_setup, 1275 .save_live_iterate = htab_save_iterate, 1276 .save_live_complete = htab_save_complete, 1277 .load_state = htab_load, 1278 }; 1279 1280 /* pSeries LPAR / sPAPR hardware init */ 1281 static void ppc_spapr_init(MachineState *machine) 1282 { 1283 ram_addr_t ram_size = machine->ram_size; 1284 const char *cpu_model = machine->cpu_model; 1285 const char *kernel_filename = machine->kernel_filename; 1286 const char *kernel_cmdline = machine->kernel_cmdline; 1287 const char *initrd_filename = machine->initrd_filename; 1288 const char *boot_device = machine->boot_order; 1289 PowerPCCPU *cpu; 1290 CPUPPCState *env; 1291 PCIHostState *phb; 1292 int i; 1293 MemoryRegion *sysmem = get_system_memory(); 1294 MemoryRegion *ram = g_new(MemoryRegion, 1); 1295 MemoryRegion *rma_region; 1296 void *rma = NULL; 1297 hwaddr rma_alloc_size; 1298 hwaddr node0_size = spapr_node0_size(); 1299 uint32_t initrd_base = 0; 1300 long kernel_size = 0, initrd_size = 0; 1301 long load_limit, fw_size; 1302 bool kernel_le = false; 1303 char *filename; 1304 1305 msi_supported = true; 1306 1307 spapr = g_malloc0(sizeof(*spapr)); 1308 QLIST_INIT(&spapr->phbs); 1309 1310 cpu_ppc_hypercall = emulate_spapr_hypercall; 1311 1312 /* Allocate RMA if necessary */ 1313 rma_alloc_size = kvmppc_alloc_rma(&rma); 1314 1315 if (rma_alloc_size == -1) { 1316 hw_error("qemu: Unable to create RMA\n"); 1317 exit(1); 1318 } 1319 1320 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1321 spapr->rma_size = rma_alloc_size; 1322 } else { 1323 spapr->rma_size = node0_size; 1324 1325 /* With KVM, we don't actually know whether KVM supports an 1326 * unbounded RMA (PR KVM) or is limited by the hash table size 1327 * (HV KVM using VRMA), so we always assume the latter 1328 * 1329 * In that case, we also limit the initial allocations for RTAS 1330 * etc... to 256M since we have no way to know what the VRMA size 1331 * is going to be as it depends on the size of the hash table 1332 * isn't determined yet. 1333 */ 1334 if (kvm_enabled()) { 1335 spapr->vrma_adjust = 1; 1336 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1337 } 1338 } 1339 1340 if (spapr->rma_size > node0_size) { 1341 fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n", 1342 spapr->rma_size); 1343 exit(1); 1344 } 1345 1346 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 1347 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 1348 1349 /* We aim for a hash table of size 1/128 the size of RAM. The 1350 * normal rule of thumb is 1/64 the size of RAM, but that's much 1351 * more than needed for the Linux guests we support. */ 1352 spapr->htab_shift = 18; /* Minimum architected size */ 1353 while (spapr->htab_shift <= 46) { 1354 if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) { 1355 break; 1356 } 1357 spapr->htab_shift++; 1358 } 1359 1360 /* Set up Interrupt Controller before we create the VCPUs */ 1361 spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads, 1362 XICS_IRQS); 1363 1364 /* init CPUs */ 1365 if (cpu_model == NULL) { 1366 cpu_model = kvm_enabled() ? "host" : "POWER7"; 1367 } 1368 for (i = 0; i < smp_cpus; i++) { 1369 cpu = cpu_ppc_init(cpu_model); 1370 if (cpu == NULL) { 1371 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 1372 exit(1); 1373 } 1374 env = &cpu->env; 1375 1376 /* Set time-base frequency to 512 MHz */ 1377 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 1378 1379 /* PAPR always has exception vectors in RAM not ROM. To ensure this, 1380 * MSR[IP] should never be set. 1381 */ 1382 env->msr_mask &= ~(1 << 6); 1383 1384 /* Tell KVM that we're in PAPR mode */ 1385 if (kvm_enabled()) { 1386 kvmppc_set_papr(cpu); 1387 } 1388 1389 if (cpu->max_compat) { 1390 if (ppc_set_compat(cpu, cpu->max_compat) < 0) { 1391 exit(1); 1392 } 1393 } 1394 1395 xics_cpu_setup(spapr->icp, cpu); 1396 1397 qemu_register_reset(spapr_cpu_reset, cpu); 1398 } 1399 1400 /* allocate RAM */ 1401 spapr->ram_limit = ram_size; 1402 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 1403 spapr->ram_limit); 1404 memory_region_add_subregion(sysmem, 0, ram); 1405 1406 if (rma_alloc_size && rma) { 1407 rma_region = g_new(MemoryRegion, 1); 1408 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 1409 rma_alloc_size, rma); 1410 vmstate_register_ram_global(rma_region); 1411 memory_region_add_subregion(sysmem, 0, rma_region); 1412 } 1413 1414 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1415 spapr->rtas_size = get_image_size(filename); 1416 spapr->rtas_blob = g_malloc(spapr->rtas_size); 1417 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 1418 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1419 exit(1); 1420 } 1421 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1422 hw_error("RTAS too big ! 0x%zx bytes (max is 0x%x)\n", 1423 spapr->rtas_size, RTAS_MAX_SIZE); 1424 exit(1); 1425 } 1426 g_free(filename); 1427 1428 /* Set up EPOW events infrastructure */ 1429 spapr_events_init(spapr); 1430 1431 /* Set up VIO bus */ 1432 spapr->vio_bus = spapr_vio_bus_init(); 1433 1434 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1435 if (serial_hds[i]) { 1436 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1437 } 1438 } 1439 1440 /* We always have at least the nvram device on VIO */ 1441 spapr_create_nvram(spapr); 1442 1443 /* Set up PCI */ 1444 spapr_pci_rtas_init(); 1445 1446 phb = spapr_create_phb(spapr, 0); 1447 1448 for (i = 0; i < nb_nics; i++) { 1449 NICInfo *nd = &nd_table[i]; 1450 1451 if (!nd->model) { 1452 nd->model = g_strdup("ibmveth"); 1453 } 1454 1455 if (strcmp(nd->model, "ibmveth") == 0) { 1456 spapr_vlan_create(spapr->vio_bus, nd); 1457 } else { 1458 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1459 } 1460 } 1461 1462 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1463 spapr_vscsi_create(spapr->vio_bus); 1464 } 1465 1466 /* Graphics */ 1467 if (spapr_vga_init(phb->bus)) { 1468 spapr->has_graphics = true; 1469 } 1470 1471 if (usb_enabled(spapr->has_graphics)) { 1472 pci_create_simple(phb->bus, -1, "pci-ohci"); 1473 if (spapr->has_graphics) { 1474 usbdevice_create("keyboard"); 1475 usbdevice_create("mouse"); 1476 } 1477 } 1478 1479 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1480 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " 1481 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); 1482 exit(1); 1483 } 1484 1485 if (kernel_filename) { 1486 uint64_t lowaddr = 0; 1487 1488 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1489 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); 1490 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { 1491 kernel_size = load_elf(kernel_filename, 1492 translate_kernel_address, NULL, 1493 NULL, &lowaddr, NULL, 0, ELF_MACHINE, 0); 1494 kernel_le = kernel_size > 0; 1495 } 1496 if (kernel_size < 0) { 1497 fprintf(stderr, "qemu: error loading %s: %s\n", 1498 kernel_filename, load_elf_strerror(kernel_size)); 1499 exit(1); 1500 } 1501 1502 /* load initrd */ 1503 if (initrd_filename) { 1504 /* Try to locate the initrd in the gap between the kernel 1505 * and the firmware. Add a bit of space just in case 1506 */ 1507 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1508 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1509 load_limit - initrd_base); 1510 if (initrd_size < 0) { 1511 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 1512 initrd_filename); 1513 exit(1); 1514 } 1515 } else { 1516 initrd_base = 0; 1517 initrd_size = 0; 1518 } 1519 } 1520 1521 if (bios_name == NULL) { 1522 bios_name = FW_FILE_NAME; 1523 } 1524 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1525 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 1526 if (fw_size < 0) { 1527 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1528 exit(1); 1529 } 1530 g_free(filename); 1531 1532 spapr->entry_point = 0x100; 1533 1534 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 1535 register_savevm_live(NULL, "spapr/htab", -1, 1, 1536 &savevm_htab_handlers, spapr); 1537 1538 /* Prepare the device tree */ 1539 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 1540 kernel_size, kernel_le, 1541 boot_device, kernel_cmdline, 1542 spapr->epow_irq); 1543 assert(spapr->fdt_skel != NULL); 1544 } 1545 1546 static int spapr_kvm_type(const char *vm_type) 1547 { 1548 if (!vm_type) { 1549 return 0; 1550 } 1551 1552 if (!strcmp(vm_type, "HV")) { 1553 return 1; 1554 } 1555 1556 if (!strcmp(vm_type, "PR")) { 1557 return 2; 1558 } 1559 1560 error_report("Unknown kvm-type specified '%s'", vm_type); 1561 exit(1); 1562 } 1563 1564 /* 1565 * Implementation of an interface to adjust firmware patch 1566 * for the bootindex property handling. 1567 */ 1568 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 1569 DeviceState *dev) 1570 { 1571 #define CAST(type, obj, name) \ 1572 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 1573 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 1574 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 1575 1576 if (d) { 1577 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 1578 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 1579 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 1580 1581 if (spapr) { 1582 /* 1583 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 1584 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 1585 * in the top 16 bits of the 64-bit LUN 1586 */ 1587 unsigned id = 0x8000 | (d->id << 8) | d->lun; 1588 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1589 (uint64_t)id << 48); 1590 } else if (virtio) { 1591 /* 1592 * We use SRP luns of the form 01000000 | (target << 8) | lun 1593 * in the top 32 bits of the 64-bit LUN 1594 * Note: the quote above is from SLOF and it is wrong, 1595 * the actual binding is: 1596 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 1597 */ 1598 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 1599 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1600 (uint64_t)id << 32); 1601 } else if (usb) { 1602 /* 1603 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 1604 * in the top 32 bits of the 64-bit LUN 1605 */ 1606 unsigned usb_port = atoi(usb->port->path); 1607 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 1608 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1609 (uint64_t)id << 32); 1610 } 1611 } 1612 1613 if (phb) { 1614 /* Replace "pci" with "pci@800000020000000" */ 1615 return g_strdup_printf("pci@%"PRIX64, phb->buid); 1616 } 1617 1618 return NULL; 1619 } 1620 1621 static char *spapr_get_kvm_type(Object *obj, Error **errp) 1622 { 1623 sPAPRMachineState *sm = SPAPR_MACHINE(obj); 1624 1625 return g_strdup(sm->kvm_type); 1626 } 1627 1628 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 1629 { 1630 sPAPRMachineState *sm = SPAPR_MACHINE(obj); 1631 1632 g_free(sm->kvm_type); 1633 sm->kvm_type = g_strdup(value); 1634 } 1635 1636 static void spapr_machine_initfn(Object *obj) 1637 { 1638 object_property_add_str(obj, "kvm-type", 1639 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 1640 } 1641 1642 static void ppc_cpu_do_nmi_on_cpu(void *arg) 1643 { 1644 CPUState *cs = arg; 1645 1646 cpu_synchronize_state(cs); 1647 ppc_cpu_do_system_reset(cs); 1648 } 1649 1650 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 1651 { 1652 CPUState *cs; 1653 1654 CPU_FOREACH(cs) { 1655 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs); 1656 } 1657 } 1658 1659 static void spapr_machine_class_init(ObjectClass *oc, void *data) 1660 { 1661 MachineClass *mc = MACHINE_CLASS(oc); 1662 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 1663 NMIClass *nc = NMI_CLASS(oc); 1664 1665 mc->name = "pseries"; 1666 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 1667 mc->is_default = 1; 1668 mc->init = ppc_spapr_init; 1669 mc->reset = ppc_spapr_reset; 1670 mc->block_default_type = IF_SCSI; 1671 mc->max_cpus = MAX_CPUS; 1672 mc->no_parallel = 1; 1673 mc->default_boot_order = NULL; 1674 mc->kvm_type = spapr_kvm_type; 1675 1676 fwc->get_dev_path = spapr_get_fw_dev_path; 1677 nc->nmi_monitor_handler = spapr_nmi; 1678 } 1679 1680 static const TypeInfo spapr_machine_info = { 1681 .name = TYPE_SPAPR_MACHINE, 1682 .parent = TYPE_MACHINE, 1683 .instance_size = sizeof(sPAPRMachineState), 1684 .instance_init = spapr_machine_initfn, 1685 .class_init = spapr_machine_class_init, 1686 .interfaces = (InterfaceInfo[]) { 1687 { TYPE_FW_PATH_PROVIDER }, 1688 { TYPE_NMI }, 1689 { } 1690 }, 1691 }; 1692 1693 static void spapr_machine_2_1_class_init(ObjectClass *oc, void *data) 1694 { 1695 MachineClass *mc = MACHINE_CLASS(oc); 1696 1697 mc->name = "pseries-2.1"; 1698 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.1"; 1699 mc->is_default = 0; 1700 } 1701 1702 static const TypeInfo spapr_machine_2_1_info = { 1703 .name = TYPE_SPAPR_MACHINE "2.1", 1704 .parent = TYPE_SPAPR_MACHINE, 1705 .class_init = spapr_machine_2_1_class_init, 1706 }; 1707 1708 static void spapr_machine_register_types(void) 1709 { 1710 type_register_static(&spapr_machine_info); 1711 type_register_static(&spapr_machine_2_1_info); 1712 } 1713 1714 type_init(spapr_machine_register_types) 1715