1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/numa.h" 31 #include "hw/hw.h" 32 #include "qemu/log.h" 33 #include "hw/fw-path-provider.h" 34 #include "elf.h" 35 #include "net/net.h" 36 #include "sysemu/device_tree.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/misc.h" 42 #include "migration/global_state.h" 43 #include "migration/register.h" 44 #include "mmu-hash64.h" 45 #include "mmu-book3s-v3.h" 46 #include "qom/cpu.h" 47 48 #include "hw/boards.h" 49 #include "hw/ppc/ppc.h" 50 #include "hw/loader.h" 51 52 #include "hw/ppc/fdt.h" 53 #include "hw/ppc/spapr.h" 54 #include "hw/ppc/spapr_vio.h" 55 #include "hw/pci-host/spapr.h" 56 #include "hw/ppc/xics.h" 57 #include "hw/pci/msi.h" 58 59 #include "hw/pci/pci.h" 60 #include "hw/scsi/scsi.h" 61 #include "hw/virtio/virtio-scsi.h" 62 #include "hw/virtio/vhost-scsi-common.h" 63 64 #include "exec/address-spaces.h" 65 #include "hw/usb.h" 66 #include "qemu/config-file.h" 67 #include "qemu/error-report.h" 68 #include "trace.h" 69 #include "hw/nmi.h" 70 #include "hw/intc/intc.h" 71 72 #include "hw/compat.h" 73 #include "qemu/cutils.h" 74 #include "hw/ppc/spapr_cpu_core.h" 75 #include "qmp-commands.h" 76 77 #include <libfdt.h> 78 79 /* SLOF memory layout: 80 * 81 * SLOF raw image loaded at 0, copies its romfs right below the flat 82 * device-tree, then position SLOF itself 31M below that 83 * 84 * So we set FW_OVERHEAD to 40MB which should account for all of that 85 * and more 86 * 87 * We load our kernel at 4M, leaving space for SLOF initial image 88 */ 89 #define FDT_MAX_SIZE 0x100000 90 #define RTAS_MAX_SIZE 0x10000 91 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 92 #define FW_MAX_SIZE 0x400000 93 #define FW_FILE_NAME "slof.bin" 94 #define FW_OVERHEAD 0x2800000 95 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 96 97 #define MIN_RMA_SLOF 128UL 98 99 #define PHANDLE_XICP 0x00001111 100 101 static ICSState *spapr_ics_create(sPAPRMachineState *spapr, 102 const char *type_ics, 103 int nr_irqs, Error **errp) 104 { 105 Error *local_err = NULL; 106 Object *obj; 107 108 obj = object_new(type_ics); 109 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); 110 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), 111 &error_abort); 112 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); 113 if (local_err) { 114 goto error; 115 } 116 object_property_set_bool(obj, true, "realized", &local_err); 117 if (local_err) { 118 goto error; 119 } 120 121 return ICS_SIMPLE(obj); 122 123 error: 124 error_propagate(errp, local_err); 125 return NULL; 126 } 127 128 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 129 { 130 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 131 * and newer QEMUs don't even have them. In both cases, we don't want 132 * to send anything on the wire. 133 */ 134 return false; 135 } 136 137 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 138 .name = "icp/server", 139 .version_id = 1, 140 .minimum_version_id = 1, 141 .needed = pre_2_10_vmstate_dummy_icp_needed, 142 .fields = (VMStateField[]) { 143 VMSTATE_UNUSED(4), /* uint32_t xirr */ 144 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 145 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 146 VMSTATE_END_OF_LIST() 147 }, 148 }; 149 150 static void pre_2_10_vmstate_register_dummy_icp(int i) 151 { 152 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 153 (void *)(uintptr_t) i); 154 } 155 156 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 157 { 158 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 159 (void *)(uintptr_t) i); 160 } 161 162 static inline int xics_max_server_number(void) 163 { 164 return DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), smp_threads); 165 } 166 167 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) 168 { 169 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 170 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 171 172 if (kvm_enabled()) { 173 if (machine_kernel_irqchip_allowed(machine) && 174 !xics_kvm_init(spapr, errp)) { 175 spapr->icp_type = TYPE_KVM_ICP; 176 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp); 177 } 178 if (machine_kernel_irqchip_required(machine) && !spapr->ics) { 179 error_prepend(errp, "kernel_irqchip requested but unavailable: "); 180 return; 181 } 182 } 183 184 if (!spapr->ics) { 185 xics_spapr_init(spapr); 186 spapr->icp_type = TYPE_ICP; 187 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp); 188 if (!spapr->ics) { 189 return; 190 } 191 } 192 193 if (smc->pre_2_10_has_unused_icps) { 194 int i; 195 196 for (i = 0; i < xics_max_server_number(); i++) { 197 /* Dummy entries get deregistered when real ICPState objects 198 * are registered during CPU core hotplug. 199 */ 200 pre_2_10_vmstate_register_dummy_icp(i); 201 } 202 } 203 } 204 205 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 206 int smt_threads) 207 { 208 int i, ret = 0; 209 uint32_t servers_prop[smt_threads]; 210 uint32_t gservers_prop[smt_threads * 2]; 211 int index = ppc_get_vcpu_dt_id(cpu); 212 213 if (cpu->compat_pvr) { 214 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 215 if (ret < 0) { 216 return ret; 217 } 218 } 219 220 /* Build interrupt servers and gservers properties */ 221 for (i = 0; i < smt_threads; i++) { 222 servers_prop[i] = cpu_to_be32(index + i); 223 /* Hack, direct the group queues back to cpu 0 */ 224 gservers_prop[i*2] = cpu_to_be32(index + i); 225 gservers_prop[i*2 + 1] = 0; 226 } 227 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 228 servers_prop, sizeof(servers_prop)); 229 if (ret < 0) { 230 return ret; 231 } 232 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 233 gservers_prop, sizeof(gservers_prop)); 234 235 return ret; 236 } 237 238 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 239 { 240 int index = ppc_get_vcpu_dt_id(cpu); 241 uint32_t associativity[] = {cpu_to_be32(0x5), 242 cpu_to_be32(0x0), 243 cpu_to_be32(0x0), 244 cpu_to_be32(0x0), 245 cpu_to_be32(cpu->node_id), 246 cpu_to_be32(index)}; 247 248 /* Advertise NUMA via ibm,associativity */ 249 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 250 sizeof(associativity)); 251 } 252 253 /* Populate the "ibm,pa-features" property */ 254 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset, 255 bool legacy_guest) 256 { 257 uint8_t pa_features_206[] = { 6, 0, 258 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 259 uint8_t pa_features_207[] = { 24, 0, 260 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 261 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 262 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 263 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 264 uint8_t pa_features_300[] = { 66, 0, 265 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 266 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 267 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 268 /* 6: DS207 */ 269 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 270 /* 16: Vector */ 271 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 272 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 273 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 274 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 275 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 276 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 277 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 278 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 279 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 280 /* 42: PM, 44: PC RA, 46: SC vec'd */ 281 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 282 /* 48: SIMD, 50: QP BFP, 52: String */ 283 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 284 /* 54: DecFP, 56: DecI, 58: SHA */ 285 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 286 /* 60: NM atomic, 62: RNG */ 287 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 288 }; 289 uint8_t *pa_features; 290 size_t pa_size; 291 292 switch (POWERPC_MMU_VER(env->mmu_model)) { 293 case POWERPC_MMU_VER_2_06: 294 pa_features = pa_features_206; 295 pa_size = sizeof(pa_features_206); 296 break; 297 case POWERPC_MMU_VER_2_07: 298 pa_features = pa_features_207; 299 pa_size = sizeof(pa_features_207); 300 break; 301 case POWERPC_MMU_VER_3_00: 302 pa_features = pa_features_300; 303 pa_size = sizeof(pa_features_300); 304 break; 305 default: 306 return; 307 } 308 309 if (env->ci_large_pages) { 310 /* 311 * Note: we keep CI large pages off by default because a 64K capable 312 * guest provisioned with large pages might otherwise try to map a qemu 313 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 314 * even if that qemu runs on a 4k host. 315 * We dd this bit back here if we are confident this is not an issue 316 */ 317 pa_features[3] |= 0x20; 318 } 319 if (kvmppc_has_cap_htm() && pa_size > 24) { 320 pa_features[24] |= 0x80; /* Transactional memory support */ 321 } 322 if (legacy_guest && pa_size > 40) { 323 /* Workaround for broken kernels that attempt (guest) radix 324 * mode when they can't handle it, if they see the radix bit set 325 * in pa-features. So hide it from them. */ 326 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 327 } 328 329 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 330 } 331 332 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 333 { 334 int ret = 0, offset, cpus_offset; 335 CPUState *cs; 336 char cpu_model[32]; 337 int smt = kvmppc_smt_threads(); 338 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 339 340 CPU_FOREACH(cs) { 341 PowerPCCPU *cpu = POWERPC_CPU(cs); 342 CPUPPCState *env = &cpu->env; 343 DeviceClass *dc = DEVICE_GET_CLASS(cs); 344 int index = ppc_get_vcpu_dt_id(cpu); 345 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 346 347 if ((index % smt) != 0) { 348 continue; 349 } 350 351 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 352 353 cpus_offset = fdt_path_offset(fdt, "/cpus"); 354 if (cpus_offset < 0) { 355 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 356 "cpus"); 357 if (cpus_offset < 0) { 358 return cpus_offset; 359 } 360 } 361 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 362 if (offset < 0) { 363 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 364 if (offset < 0) { 365 return offset; 366 } 367 } 368 369 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 370 pft_size_prop, sizeof(pft_size_prop)); 371 if (ret < 0) { 372 return ret; 373 } 374 375 if (nb_numa_nodes > 1) { 376 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 377 if (ret < 0) { 378 return ret; 379 } 380 } 381 382 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 383 if (ret < 0) { 384 return ret; 385 } 386 387 spapr_populate_pa_features(env, fdt, offset, 388 spapr->cas_legacy_guest_workaround); 389 } 390 return ret; 391 } 392 393 static hwaddr spapr_node0_size(void) 394 { 395 MachineState *machine = MACHINE(qdev_get_machine()); 396 397 if (nb_numa_nodes) { 398 int i; 399 for (i = 0; i < nb_numa_nodes; ++i) { 400 if (numa_info[i].node_mem) { 401 return MIN(pow2floor(numa_info[i].node_mem), 402 machine->ram_size); 403 } 404 } 405 } 406 return machine->ram_size; 407 } 408 409 static void add_str(GString *s, const gchar *s1) 410 { 411 g_string_append_len(s, s1, strlen(s1) + 1); 412 } 413 414 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 415 hwaddr size) 416 { 417 uint32_t associativity[] = { 418 cpu_to_be32(0x4), /* length */ 419 cpu_to_be32(0x0), cpu_to_be32(0x0), 420 cpu_to_be32(0x0), cpu_to_be32(nodeid) 421 }; 422 char mem_name[32]; 423 uint64_t mem_reg_property[2]; 424 int off; 425 426 mem_reg_property[0] = cpu_to_be64(start); 427 mem_reg_property[1] = cpu_to_be64(size); 428 429 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 430 off = fdt_add_subnode(fdt, 0, mem_name); 431 _FDT(off); 432 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 433 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 434 sizeof(mem_reg_property)))); 435 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 436 sizeof(associativity)))); 437 return off; 438 } 439 440 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 441 { 442 MachineState *machine = MACHINE(spapr); 443 hwaddr mem_start, node_size; 444 int i, nb_nodes = nb_numa_nodes; 445 NodeInfo *nodes = numa_info; 446 NodeInfo ramnode; 447 448 /* No NUMA nodes, assume there is just one node with whole RAM */ 449 if (!nb_numa_nodes) { 450 nb_nodes = 1; 451 ramnode.node_mem = machine->ram_size; 452 nodes = &ramnode; 453 } 454 455 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 456 if (!nodes[i].node_mem) { 457 continue; 458 } 459 if (mem_start >= machine->ram_size) { 460 node_size = 0; 461 } else { 462 node_size = nodes[i].node_mem; 463 if (node_size > machine->ram_size - mem_start) { 464 node_size = machine->ram_size - mem_start; 465 } 466 } 467 if (!mem_start) { 468 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 469 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 470 mem_start += spapr->rma_size; 471 node_size -= spapr->rma_size; 472 } 473 for ( ; node_size; ) { 474 hwaddr sizetmp = pow2floor(node_size); 475 476 /* mem_start != 0 here */ 477 if (ctzl(mem_start) < ctzl(sizetmp)) { 478 sizetmp = 1ULL << ctzl(mem_start); 479 } 480 481 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 482 node_size -= sizetmp; 483 mem_start += sizetmp; 484 } 485 } 486 487 return 0; 488 } 489 490 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 491 sPAPRMachineState *spapr) 492 { 493 PowerPCCPU *cpu = POWERPC_CPU(cs); 494 CPUPPCState *env = &cpu->env; 495 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 496 int index = ppc_get_vcpu_dt_id(cpu); 497 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 498 0xffffffff, 0xffffffff}; 499 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 500 : SPAPR_TIMEBASE_FREQ; 501 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 502 uint32_t page_sizes_prop[64]; 503 size_t page_sizes_prop_size; 504 uint32_t vcpus_per_socket = smp_threads * smp_cores; 505 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 506 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 507 sPAPRDRConnector *drc; 508 int drc_index; 509 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 510 int i; 511 512 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 513 if (drc) { 514 drc_index = spapr_drc_index(drc); 515 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 516 } 517 518 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 519 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 520 521 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 522 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 523 env->dcache_line_size))); 524 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 525 env->dcache_line_size))); 526 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 527 env->icache_line_size))); 528 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 529 env->icache_line_size))); 530 531 if (pcc->l1_dcache_size) { 532 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 533 pcc->l1_dcache_size))); 534 } else { 535 warn_report("Unknown L1 dcache size for cpu"); 536 } 537 if (pcc->l1_icache_size) { 538 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 539 pcc->l1_icache_size))); 540 } else { 541 warn_report("Unknown L1 icache size for cpu"); 542 } 543 544 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 545 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 546 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 547 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 548 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 549 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 550 551 if (env->spr_cb[SPR_PURR].oea_read) { 552 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 553 } 554 555 if (env->mmu_model & POWERPC_MMU_1TSEG) { 556 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 557 segs, sizeof(segs)))); 558 } 559 560 /* Advertise VMX/VSX (vector extensions) if available 561 * 0 / no property == no vector extensions 562 * 1 == VMX / Altivec available 563 * 2 == VSX available */ 564 if (env->insns_flags & PPC_ALTIVEC) { 565 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 566 567 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 568 } 569 570 /* Advertise DFP (Decimal Floating Point) if available 571 * 0 / no property == no DFP 572 * 1 == DFP available */ 573 if (env->insns_flags2 & PPC2_DFP) { 574 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 575 } 576 577 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 578 sizeof(page_sizes_prop)); 579 if (page_sizes_prop_size) { 580 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 581 page_sizes_prop, page_sizes_prop_size))); 582 } 583 584 spapr_populate_pa_features(env, fdt, offset, false); 585 586 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 587 cs->cpu_index / vcpus_per_socket))); 588 589 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 590 pft_size_prop, sizeof(pft_size_prop)))); 591 592 if (nb_numa_nodes > 1) { 593 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 594 } 595 596 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 597 598 if (pcc->radix_page_info) { 599 for (i = 0; i < pcc->radix_page_info->count; i++) { 600 radix_AP_encodings[i] = 601 cpu_to_be32(pcc->radix_page_info->entries[i]); 602 } 603 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 604 radix_AP_encodings, 605 pcc->radix_page_info->count * 606 sizeof(radix_AP_encodings[0])))); 607 } 608 } 609 610 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 611 { 612 CPUState *cs; 613 int cpus_offset; 614 char *nodename; 615 int smt = kvmppc_smt_threads(); 616 617 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 618 _FDT(cpus_offset); 619 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 620 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 621 622 /* 623 * We walk the CPUs in reverse order to ensure that CPU DT nodes 624 * created by fdt_add_subnode() end up in the right order in FDT 625 * for the guest kernel the enumerate the CPUs correctly. 626 */ 627 CPU_FOREACH_REVERSE(cs) { 628 PowerPCCPU *cpu = POWERPC_CPU(cs); 629 int index = ppc_get_vcpu_dt_id(cpu); 630 DeviceClass *dc = DEVICE_GET_CLASS(cs); 631 int offset; 632 633 if ((index % smt) != 0) { 634 continue; 635 } 636 637 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 638 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 639 g_free(nodename); 640 _FDT(offset); 641 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 642 } 643 644 } 645 646 /* 647 * Adds ibm,dynamic-reconfiguration-memory node. 648 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 649 * of this device tree node. 650 */ 651 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 652 { 653 MachineState *machine = MACHINE(spapr); 654 int ret, i, offset; 655 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 656 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 657 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 658 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 659 memory_region_size(&spapr->hotplug_memory.mr)) / 660 lmb_size; 661 uint32_t *int_buf, *cur_index, buf_len; 662 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 663 664 /* 665 * Don't create the node if there is no hotpluggable memory 666 */ 667 if (machine->ram_size == machine->maxram_size) { 668 return 0; 669 } 670 671 /* 672 * Allocate enough buffer size to fit in ibm,dynamic-memory 673 * or ibm,associativity-lookup-arrays 674 */ 675 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 676 * sizeof(uint32_t); 677 cur_index = int_buf = g_malloc0(buf_len); 678 679 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 680 681 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 682 sizeof(prop_lmb_size)); 683 if (ret < 0) { 684 goto out; 685 } 686 687 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 688 if (ret < 0) { 689 goto out; 690 } 691 692 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 693 if (ret < 0) { 694 goto out; 695 } 696 697 /* ibm,dynamic-memory */ 698 int_buf[0] = cpu_to_be32(nr_lmbs); 699 cur_index++; 700 for (i = 0; i < nr_lmbs; i++) { 701 uint64_t addr = i * lmb_size; 702 uint32_t *dynamic_memory = cur_index; 703 704 if (i >= hotplug_lmb_start) { 705 sPAPRDRConnector *drc; 706 707 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 708 g_assert(drc); 709 710 dynamic_memory[0] = cpu_to_be32(addr >> 32); 711 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 712 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 713 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 714 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 715 if (memory_region_present(get_system_memory(), addr)) { 716 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 717 } else { 718 dynamic_memory[5] = cpu_to_be32(0); 719 } 720 } else { 721 /* 722 * LMB information for RMA, boot time RAM and gap b/n RAM and 723 * hotplug memory region -- all these are marked as reserved 724 * and as having no valid DRC. 725 */ 726 dynamic_memory[0] = cpu_to_be32(addr >> 32); 727 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 728 dynamic_memory[2] = cpu_to_be32(0); 729 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 730 dynamic_memory[4] = cpu_to_be32(-1); 731 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 732 SPAPR_LMB_FLAGS_DRC_INVALID); 733 } 734 735 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 736 } 737 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 738 if (ret < 0) { 739 goto out; 740 } 741 742 /* ibm,associativity-lookup-arrays */ 743 cur_index = int_buf; 744 int_buf[0] = cpu_to_be32(nr_nodes); 745 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 746 cur_index += 2; 747 for (i = 0; i < nr_nodes; i++) { 748 uint32_t associativity[] = { 749 cpu_to_be32(0x0), 750 cpu_to_be32(0x0), 751 cpu_to_be32(0x0), 752 cpu_to_be32(i) 753 }; 754 memcpy(cur_index, associativity, sizeof(associativity)); 755 cur_index += 4; 756 } 757 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 758 (cur_index - int_buf) * sizeof(uint32_t)); 759 out: 760 g_free(int_buf); 761 return ret; 762 } 763 764 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 765 sPAPROptionVector *ov5_updates) 766 { 767 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 768 int ret = 0, offset; 769 770 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 771 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 772 g_assert(smc->dr_lmb_enabled); 773 ret = spapr_populate_drconf_memory(spapr, fdt); 774 if (ret) { 775 goto out; 776 } 777 } 778 779 offset = fdt_path_offset(fdt, "/chosen"); 780 if (offset < 0) { 781 offset = fdt_add_subnode(fdt, 0, "chosen"); 782 if (offset < 0) { 783 return offset; 784 } 785 } 786 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 787 "ibm,architecture-vec-5"); 788 789 out: 790 return ret; 791 } 792 793 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 794 target_ulong addr, target_ulong size, 795 sPAPROptionVector *ov5_updates) 796 { 797 void *fdt, *fdt_skel; 798 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 799 800 size -= sizeof(hdr); 801 802 /* Create sceleton */ 803 fdt_skel = g_malloc0(size); 804 _FDT((fdt_create(fdt_skel, size))); 805 _FDT((fdt_begin_node(fdt_skel, ""))); 806 _FDT((fdt_end_node(fdt_skel))); 807 _FDT((fdt_finish(fdt_skel))); 808 fdt = g_malloc0(size); 809 _FDT((fdt_open_into(fdt_skel, fdt, size))); 810 g_free(fdt_skel); 811 812 /* Fixup cpu nodes */ 813 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 814 815 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 816 return -1; 817 } 818 819 /* Pack resulting tree */ 820 _FDT((fdt_pack(fdt))); 821 822 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 823 trace_spapr_cas_failed(size); 824 return -1; 825 } 826 827 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 828 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 829 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 830 g_free(fdt); 831 832 return 0; 833 } 834 835 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 836 { 837 int rtas; 838 GString *hypertas = g_string_sized_new(256); 839 GString *qemu_hypertas = g_string_sized_new(256); 840 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 841 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 842 memory_region_size(&spapr->hotplug_memory.mr); 843 uint32_t lrdr_capacity[] = { 844 cpu_to_be32(max_hotplug_addr >> 32), 845 cpu_to_be32(max_hotplug_addr & 0xffffffff), 846 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 847 cpu_to_be32(max_cpus / smp_threads), 848 }; 849 850 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 851 852 /* hypertas */ 853 add_str(hypertas, "hcall-pft"); 854 add_str(hypertas, "hcall-term"); 855 add_str(hypertas, "hcall-dabr"); 856 add_str(hypertas, "hcall-interrupt"); 857 add_str(hypertas, "hcall-tce"); 858 add_str(hypertas, "hcall-vio"); 859 add_str(hypertas, "hcall-splpar"); 860 add_str(hypertas, "hcall-bulk"); 861 add_str(hypertas, "hcall-set-mode"); 862 add_str(hypertas, "hcall-sprg0"); 863 add_str(hypertas, "hcall-copy"); 864 add_str(hypertas, "hcall-debug"); 865 add_str(qemu_hypertas, "hcall-memop1"); 866 867 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 868 add_str(hypertas, "hcall-multi-tce"); 869 } 870 871 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 872 add_str(hypertas, "hcall-hpt-resize"); 873 } 874 875 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 876 hypertas->str, hypertas->len)); 877 g_string_free(hypertas, TRUE); 878 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 879 qemu_hypertas->str, qemu_hypertas->len)); 880 g_string_free(qemu_hypertas, TRUE); 881 882 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 883 refpoints, sizeof(refpoints))); 884 885 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 886 RTAS_ERROR_LOG_MAX)); 887 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 888 RTAS_EVENT_SCAN_RATE)); 889 890 if (msi_nonbroken) { 891 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 892 } 893 894 /* 895 * According to PAPR, rtas ibm,os-term does not guarantee a return 896 * back to the guest cpu. 897 * 898 * While an additional ibm,extended-os-term property indicates 899 * that rtas call return will always occur. Set this property. 900 */ 901 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 902 903 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 904 lrdr_capacity, sizeof(lrdr_capacity))); 905 906 spapr_dt_rtas_tokens(fdt, rtas); 907 } 908 909 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features 910 * that the guest may request and thus the valid values for bytes 24..26 of 911 * option vector 5: */ 912 static void spapr_dt_ov5_platform_support(void *fdt, int chosen) 913 { 914 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 915 916 char val[2 * 4] = { 917 23, 0x00, /* Xive mode: 0 = legacy (as in ISA 2.7), 1 = Exploitation */ 918 24, 0x00, /* Hash/Radix, filled in below. */ 919 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 920 26, 0x40, /* Radix options: GTSE == yes. */ 921 }; 922 923 if (kvm_enabled()) { 924 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 925 val[3] = 0x80; /* OV5_MMU_BOTH */ 926 } else if (kvmppc_has_cap_mmu_radix()) { 927 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 928 } else { 929 val[3] = 0x00; /* Hash */ 930 } 931 } else { 932 if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) { 933 /* V3 MMU supports both hash and radix (with dynamic switching) */ 934 val[3] = 0xC0; 935 } else { 936 /* Otherwise we can only do hash */ 937 val[3] = 0x00; 938 } 939 } 940 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 941 val, sizeof(val))); 942 } 943 944 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 945 { 946 MachineState *machine = MACHINE(spapr); 947 int chosen; 948 const char *boot_device = machine->boot_order; 949 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 950 size_t cb = 0; 951 char *bootlist = get_boot_devices_list(&cb, true); 952 953 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 954 955 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 956 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 957 spapr->initrd_base)); 958 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 959 spapr->initrd_base + spapr->initrd_size)); 960 961 if (spapr->kernel_size) { 962 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 963 cpu_to_be64(spapr->kernel_size) }; 964 965 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 966 &kprop, sizeof(kprop))); 967 if (spapr->kernel_le) { 968 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 969 } 970 } 971 if (boot_menu) { 972 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 973 } 974 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 975 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 976 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 977 978 if (cb && bootlist) { 979 int i; 980 981 for (i = 0; i < cb; i++) { 982 if (bootlist[i] == '\n') { 983 bootlist[i] = ' '; 984 } 985 } 986 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 987 } 988 989 if (boot_device && strlen(boot_device)) { 990 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 991 } 992 993 if (!spapr->has_graphics && stdout_path) { 994 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 995 } 996 997 spapr_dt_ov5_platform_support(fdt, chosen); 998 999 g_free(stdout_path); 1000 g_free(bootlist); 1001 } 1002 1003 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 1004 { 1005 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1006 * KVM to work under pHyp with some guest co-operation */ 1007 int hypervisor; 1008 uint8_t hypercall[16]; 1009 1010 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1011 /* indicate KVM hypercall interface */ 1012 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1013 if (kvmppc_has_cap_fixup_hcalls()) { 1014 /* 1015 * Older KVM versions with older guest kernels were broken 1016 * with the magic page, don't allow the guest to map it. 1017 */ 1018 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1019 sizeof(hypercall))) { 1020 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1021 hypercall, sizeof(hypercall))); 1022 } 1023 } 1024 } 1025 1026 static void *spapr_build_fdt(sPAPRMachineState *spapr, 1027 hwaddr rtas_addr, 1028 hwaddr rtas_size) 1029 { 1030 MachineState *machine = MACHINE(qdev_get_machine()); 1031 MachineClass *mc = MACHINE_GET_CLASS(machine); 1032 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1033 int ret; 1034 void *fdt; 1035 sPAPRPHBState *phb; 1036 char *buf; 1037 1038 fdt = g_malloc0(FDT_MAX_SIZE); 1039 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1040 1041 /* Root node */ 1042 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1043 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1044 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1045 1046 /* 1047 * Add info to guest to indentify which host is it being run on 1048 * and what is the uuid of the guest 1049 */ 1050 if (kvmppc_get_host_model(&buf)) { 1051 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1052 g_free(buf); 1053 } 1054 if (kvmppc_get_host_serial(&buf)) { 1055 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1056 g_free(buf); 1057 } 1058 1059 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1060 1061 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1062 if (qemu_uuid_set) { 1063 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1064 } 1065 g_free(buf); 1066 1067 if (qemu_get_vm_name()) { 1068 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1069 qemu_get_vm_name())); 1070 } 1071 1072 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1073 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1074 1075 /* /interrupt controller */ 1076 spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP); 1077 1078 ret = spapr_populate_memory(spapr, fdt); 1079 if (ret < 0) { 1080 error_report("couldn't setup memory nodes in fdt"); 1081 exit(1); 1082 } 1083 1084 /* /vdevice */ 1085 spapr_dt_vdevice(spapr->vio_bus, fdt); 1086 1087 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1088 ret = spapr_rng_populate_dt(fdt); 1089 if (ret < 0) { 1090 error_report("could not set up rng device in the fdt"); 1091 exit(1); 1092 } 1093 } 1094 1095 QLIST_FOREACH(phb, &spapr->phbs, list) { 1096 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 1097 if (ret < 0) { 1098 error_report("couldn't setup PCI devices in fdt"); 1099 exit(1); 1100 } 1101 } 1102 1103 /* cpus */ 1104 spapr_populate_cpus_dt_node(fdt, spapr); 1105 1106 if (smc->dr_lmb_enabled) { 1107 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1108 } 1109 1110 if (mc->has_hotpluggable_cpus) { 1111 int offset = fdt_path_offset(fdt, "/cpus"); 1112 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1113 SPAPR_DR_CONNECTOR_TYPE_CPU); 1114 if (ret < 0) { 1115 error_report("Couldn't set up CPU DR device tree properties"); 1116 exit(1); 1117 } 1118 } 1119 1120 /* /event-sources */ 1121 spapr_dt_events(spapr, fdt); 1122 1123 /* /rtas */ 1124 spapr_dt_rtas(spapr, fdt); 1125 1126 /* /chosen */ 1127 spapr_dt_chosen(spapr, fdt); 1128 1129 /* /hypervisor */ 1130 if (kvm_enabled()) { 1131 spapr_dt_hypervisor(spapr, fdt); 1132 } 1133 1134 /* Build memory reserve map */ 1135 if (spapr->kernel_size) { 1136 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1137 } 1138 if (spapr->initrd_size) { 1139 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1140 } 1141 1142 /* ibm,client-architecture-support updates */ 1143 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1144 if (ret < 0) { 1145 error_report("couldn't setup CAS properties fdt"); 1146 exit(1); 1147 } 1148 1149 return fdt; 1150 } 1151 1152 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1153 { 1154 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1155 } 1156 1157 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1158 PowerPCCPU *cpu) 1159 { 1160 CPUPPCState *env = &cpu->env; 1161 1162 /* The TCG path should also be holding the BQL at this point */ 1163 g_assert(qemu_mutex_iothread_locked()); 1164 1165 if (msr_pr) { 1166 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1167 env->gpr[3] = H_PRIVILEGE; 1168 } else { 1169 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1170 } 1171 } 1172 1173 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1174 { 1175 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1176 1177 return spapr->patb_entry; 1178 } 1179 1180 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1181 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1182 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1183 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1184 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1185 1186 /* 1187 * Get the fd to access the kernel htab, re-opening it if necessary 1188 */ 1189 static int get_htab_fd(sPAPRMachineState *spapr) 1190 { 1191 if (spapr->htab_fd >= 0) { 1192 return spapr->htab_fd; 1193 } 1194 1195 spapr->htab_fd = kvmppc_get_htab_fd(false); 1196 if (spapr->htab_fd < 0) { 1197 error_report("Unable to open fd for reading hash table from KVM: %s", 1198 strerror(errno)); 1199 } 1200 1201 return spapr->htab_fd; 1202 } 1203 1204 void close_htab_fd(sPAPRMachineState *spapr) 1205 { 1206 if (spapr->htab_fd >= 0) { 1207 close(spapr->htab_fd); 1208 } 1209 spapr->htab_fd = -1; 1210 } 1211 1212 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1213 { 1214 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1215 1216 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1217 } 1218 1219 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1220 hwaddr ptex, int n) 1221 { 1222 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1223 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1224 1225 if (!spapr->htab) { 1226 /* 1227 * HTAB is controlled by KVM. Fetch into temporary buffer 1228 */ 1229 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1230 kvmppc_read_hptes(hptes, ptex, n); 1231 return hptes; 1232 } 1233 1234 /* 1235 * HTAB is controlled by QEMU. Just point to the internally 1236 * accessible PTEG. 1237 */ 1238 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1239 } 1240 1241 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1242 const ppc_hash_pte64_t *hptes, 1243 hwaddr ptex, int n) 1244 { 1245 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1246 1247 if (!spapr->htab) { 1248 g_free((void *)hptes); 1249 } 1250 1251 /* Nothing to do for qemu managed HPT */ 1252 } 1253 1254 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1255 uint64_t pte0, uint64_t pte1) 1256 { 1257 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1258 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1259 1260 if (!spapr->htab) { 1261 kvmppc_write_hpte(ptex, pte0, pte1); 1262 } else { 1263 stq_p(spapr->htab + offset, pte0); 1264 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1265 } 1266 } 1267 1268 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1269 { 1270 int shift; 1271 1272 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1273 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1274 * that's much more than is needed for Linux guests */ 1275 shift = ctz64(pow2ceil(ramsize)) - 7; 1276 shift = MAX(shift, 18); /* Minimum architected size */ 1277 shift = MIN(shift, 46); /* Maximum architected size */ 1278 return shift; 1279 } 1280 1281 void spapr_free_hpt(sPAPRMachineState *spapr) 1282 { 1283 g_free(spapr->htab); 1284 spapr->htab = NULL; 1285 spapr->htab_shift = 0; 1286 close_htab_fd(spapr); 1287 } 1288 1289 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1290 Error **errp) 1291 { 1292 long rc; 1293 1294 /* Clean up any HPT info from a previous boot */ 1295 spapr_free_hpt(spapr); 1296 1297 rc = kvmppc_reset_htab(shift); 1298 if (rc < 0) { 1299 /* kernel-side HPT needed, but couldn't allocate one */ 1300 error_setg_errno(errp, errno, 1301 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1302 shift); 1303 /* This is almost certainly fatal, but if the caller really 1304 * wants to carry on with shift == 0, it's welcome to try */ 1305 } else if (rc > 0) { 1306 /* kernel-side HPT allocated */ 1307 if (rc != shift) { 1308 error_setg(errp, 1309 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1310 shift, rc); 1311 } 1312 1313 spapr->htab_shift = shift; 1314 spapr->htab = NULL; 1315 } else { 1316 /* kernel-side HPT not needed, allocate in userspace instead */ 1317 size_t size = 1ULL << shift; 1318 int i; 1319 1320 spapr->htab = qemu_memalign(size, size); 1321 if (!spapr->htab) { 1322 error_setg_errno(errp, errno, 1323 "Could not allocate HPT of order %d", shift); 1324 return; 1325 } 1326 1327 memset(spapr->htab, 0, size); 1328 spapr->htab_shift = shift; 1329 1330 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1331 DIRTY_HPTE(HPTE(spapr->htab, i)); 1332 } 1333 } 1334 } 1335 1336 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1337 { 1338 int hpt_shift; 1339 1340 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1341 || (spapr->cas_reboot 1342 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1343 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1344 } else { 1345 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->ram_size); 1346 } 1347 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1348 1349 if (spapr->vrma_adjust) { 1350 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1351 spapr->htab_shift); 1352 } 1353 /* We're setting up a hash table, so that means we're not radix */ 1354 spapr->patb_entry = 0; 1355 } 1356 1357 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1358 { 1359 bool matched = false; 1360 1361 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1362 matched = true; 1363 } 1364 1365 if (!matched) { 1366 error_report("Device %s is not supported by this machine yet.", 1367 qdev_fw_name(DEVICE(sbdev))); 1368 exit(1); 1369 } 1370 } 1371 1372 static void ppc_spapr_reset(void) 1373 { 1374 MachineState *machine = MACHINE(qdev_get_machine()); 1375 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1376 PowerPCCPU *first_ppc_cpu; 1377 uint32_t rtas_limit; 1378 hwaddr rtas_addr, fdt_addr; 1379 void *fdt; 1380 int rc; 1381 1382 /* Check for unknown sysbus devices */ 1383 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1384 1385 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()) { 1386 /* If using KVM with radix mode available, VCPUs can be started 1387 * without a HPT because KVM will start them in radix mode. 1388 * Set the GR bit in PATB so that we know there is no HPT. */ 1389 spapr->patb_entry = PATBE1_GR; 1390 } else { 1391 spapr_setup_hpt_and_vrma(spapr); 1392 } 1393 1394 qemu_devices_reset(); 1395 1396 /* 1397 * We place the device tree and RTAS just below either the top of the RMA, 1398 * or just below 2GB, whichever is lowere, so that it can be 1399 * processed with 32-bit real mode code if necessary 1400 */ 1401 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1402 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1403 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1404 1405 /* if this reset wasn't generated by CAS, we should reset our 1406 * negotiated options and start from scratch */ 1407 if (!spapr->cas_reboot) { 1408 spapr_ovec_cleanup(spapr->ov5_cas); 1409 spapr->ov5_cas = spapr_ovec_new(); 1410 1411 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1412 } 1413 1414 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1415 1416 spapr_load_rtas(spapr, fdt, rtas_addr); 1417 1418 rc = fdt_pack(fdt); 1419 1420 /* Should only fail if we've built a corrupted tree */ 1421 assert(rc == 0); 1422 1423 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1424 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1425 fdt_totalsize(fdt), FDT_MAX_SIZE); 1426 exit(1); 1427 } 1428 1429 /* Load the fdt */ 1430 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1431 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1432 g_free(fdt); 1433 1434 /* Set up the entry state */ 1435 first_ppc_cpu = POWERPC_CPU(first_cpu); 1436 first_ppc_cpu->env.gpr[3] = fdt_addr; 1437 first_ppc_cpu->env.gpr[5] = 0; 1438 first_cpu->halted = 0; 1439 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1440 1441 spapr->cas_reboot = false; 1442 } 1443 1444 static void spapr_create_nvram(sPAPRMachineState *spapr) 1445 { 1446 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1447 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1448 1449 if (dinfo) { 1450 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1451 &error_fatal); 1452 } 1453 1454 qdev_init_nofail(dev); 1455 1456 spapr->nvram = (struct sPAPRNVRAM *)dev; 1457 } 1458 1459 static void spapr_rtc_create(sPAPRMachineState *spapr) 1460 { 1461 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1462 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1463 &error_fatal); 1464 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1465 &error_fatal); 1466 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1467 "date", &error_fatal); 1468 } 1469 1470 /* Returns whether we want to use VGA or not */ 1471 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1472 { 1473 switch (vga_interface_type) { 1474 case VGA_NONE: 1475 return false; 1476 case VGA_DEVICE: 1477 return true; 1478 case VGA_STD: 1479 case VGA_VIRTIO: 1480 return pci_vga_init(pci_bus) != NULL; 1481 default: 1482 error_setg(errp, 1483 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1484 return false; 1485 } 1486 } 1487 1488 static int spapr_post_load(void *opaque, int version_id) 1489 { 1490 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1491 int err = 0; 1492 1493 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1494 CPUState *cs; 1495 CPU_FOREACH(cs) { 1496 PowerPCCPU *cpu = POWERPC_CPU(cs); 1497 icp_resend(ICP(cpu->intc)); 1498 } 1499 } 1500 1501 /* In earlier versions, there was no separate qdev for the PAPR 1502 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1503 * So when migrating from those versions, poke the incoming offset 1504 * value into the RTC device */ 1505 if (version_id < 3) { 1506 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1507 } 1508 1509 if (spapr->patb_entry) { 1510 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1511 bool radix = !!(spapr->patb_entry & PATBE1_GR); 1512 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1513 1514 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1515 if (err) { 1516 error_report("Process table config unsupported by the host"); 1517 return -EINVAL; 1518 } 1519 } 1520 1521 return err; 1522 } 1523 1524 static bool version_before_3(void *opaque, int version_id) 1525 { 1526 return version_id < 3; 1527 } 1528 1529 static bool spapr_pending_events_needed(void *opaque) 1530 { 1531 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1532 return !QTAILQ_EMPTY(&spapr->pending_events); 1533 } 1534 1535 static const VMStateDescription vmstate_spapr_event_entry = { 1536 .name = "spapr_event_log_entry", 1537 .version_id = 1, 1538 .minimum_version_id = 1, 1539 .fields = (VMStateField[]) { 1540 VMSTATE_UINT32(summary, sPAPREventLogEntry), 1541 VMSTATE_UINT32(extended_length, sPAPREventLogEntry), 1542 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, 1543 NULL, extended_length), 1544 VMSTATE_END_OF_LIST() 1545 }, 1546 }; 1547 1548 static const VMStateDescription vmstate_spapr_pending_events = { 1549 .name = "spapr_pending_events", 1550 .version_id = 1, 1551 .minimum_version_id = 1, 1552 .needed = spapr_pending_events_needed, 1553 .fields = (VMStateField[]) { 1554 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, 1555 vmstate_spapr_event_entry, sPAPREventLogEntry, next), 1556 VMSTATE_END_OF_LIST() 1557 }, 1558 }; 1559 1560 static bool spapr_ov5_cas_needed(void *opaque) 1561 { 1562 sPAPRMachineState *spapr = opaque; 1563 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1564 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1565 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1566 bool cas_needed; 1567 1568 /* Prior to the introduction of sPAPROptionVector, we had two option 1569 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1570 * Both of these options encode machine topology into the device-tree 1571 * in such a way that the now-booted OS should still be able to interact 1572 * appropriately with QEMU regardless of what options were actually 1573 * negotiatied on the source side. 1574 * 1575 * As such, we can avoid migrating the CAS-negotiated options if these 1576 * are the only options available on the current machine/platform. 1577 * Since these are the only options available for pseries-2.7 and 1578 * earlier, this allows us to maintain old->new/new->old migration 1579 * compatibility. 1580 * 1581 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1582 * via default pseries-2.8 machines and explicit command-line parameters. 1583 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1584 * of the actual CAS-negotiated values to continue working properly. For 1585 * example, availability of memory unplug depends on knowing whether 1586 * OV5_HP_EVT was negotiated via CAS. 1587 * 1588 * Thus, for any cases where the set of available CAS-negotiatable 1589 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1590 * include the CAS-negotiated options in the migration stream. 1591 */ 1592 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1593 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1594 1595 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1596 * the mask itself since in the future it's possible "legacy" bits may be 1597 * removed via machine options, which could generate a false positive 1598 * that breaks migration. 1599 */ 1600 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1601 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1602 1603 spapr_ovec_cleanup(ov5_mask); 1604 spapr_ovec_cleanup(ov5_legacy); 1605 spapr_ovec_cleanup(ov5_removed); 1606 1607 return cas_needed; 1608 } 1609 1610 static const VMStateDescription vmstate_spapr_ov5_cas = { 1611 .name = "spapr_option_vector_ov5_cas", 1612 .version_id = 1, 1613 .minimum_version_id = 1, 1614 .needed = spapr_ov5_cas_needed, 1615 .fields = (VMStateField[]) { 1616 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1617 vmstate_spapr_ovec, sPAPROptionVector), 1618 VMSTATE_END_OF_LIST() 1619 }, 1620 }; 1621 1622 static bool spapr_patb_entry_needed(void *opaque) 1623 { 1624 sPAPRMachineState *spapr = opaque; 1625 1626 return !!spapr->patb_entry; 1627 } 1628 1629 static const VMStateDescription vmstate_spapr_patb_entry = { 1630 .name = "spapr_patb_entry", 1631 .version_id = 1, 1632 .minimum_version_id = 1, 1633 .needed = spapr_patb_entry_needed, 1634 .fields = (VMStateField[]) { 1635 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1636 VMSTATE_END_OF_LIST() 1637 }, 1638 }; 1639 1640 static const VMStateDescription vmstate_spapr = { 1641 .name = "spapr", 1642 .version_id = 3, 1643 .minimum_version_id = 1, 1644 .post_load = spapr_post_load, 1645 .fields = (VMStateField[]) { 1646 /* used to be @next_irq */ 1647 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1648 1649 /* RTC offset */ 1650 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1651 1652 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1653 VMSTATE_END_OF_LIST() 1654 }, 1655 .subsections = (const VMStateDescription*[]) { 1656 &vmstate_spapr_ov5_cas, 1657 &vmstate_spapr_patb_entry, 1658 &vmstate_spapr_pending_events, 1659 NULL 1660 } 1661 }; 1662 1663 static int htab_save_setup(QEMUFile *f, void *opaque) 1664 { 1665 sPAPRMachineState *spapr = opaque; 1666 1667 /* "Iteration" header */ 1668 if (!spapr->htab_shift) { 1669 qemu_put_be32(f, -1); 1670 } else { 1671 qemu_put_be32(f, spapr->htab_shift); 1672 } 1673 1674 if (spapr->htab) { 1675 spapr->htab_save_index = 0; 1676 spapr->htab_first_pass = true; 1677 } else { 1678 if (spapr->htab_shift) { 1679 assert(kvm_enabled()); 1680 } 1681 } 1682 1683 1684 return 0; 1685 } 1686 1687 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1688 int64_t max_ns) 1689 { 1690 bool has_timeout = max_ns != -1; 1691 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1692 int index = spapr->htab_save_index; 1693 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1694 1695 assert(spapr->htab_first_pass); 1696 1697 do { 1698 int chunkstart; 1699 1700 /* Consume invalid HPTEs */ 1701 while ((index < htabslots) 1702 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1703 CLEAN_HPTE(HPTE(spapr->htab, index)); 1704 index++; 1705 } 1706 1707 /* Consume valid HPTEs */ 1708 chunkstart = index; 1709 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1710 && HPTE_VALID(HPTE(spapr->htab, index))) { 1711 CLEAN_HPTE(HPTE(spapr->htab, index)); 1712 index++; 1713 } 1714 1715 if (index > chunkstart) { 1716 int n_valid = index - chunkstart; 1717 1718 qemu_put_be32(f, chunkstart); 1719 qemu_put_be16(f, n_valid); 1720 qemu_put_be16(f, 0); 1721 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1722 HASH_PTE_SIZE_64 * n_valid); 1723 1724 if (has_timeout && 1725 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1726 break; 1727 } 1728 } 1729 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1730 1731 if (index >= htabslots) { 1732 assert(index == htabslots); 1733 index = 0; 1734 spapr->htab_first_pass = false; 1735 } 1736 spapr->htab_save_index = index; 1737 } 1738 1739 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1740 int64_t max_ns) 1741 { 1742 bool final = max_ns < 0; 1743 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1744 int examined = 0, sent = 0; 1745 int index = spapr->htab_save_index; 1746 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1747 1748 assert(!spapr->htab_first_pass); 1749 1750 do { 1751 int chunkstart, invalidstart; 1752 1753 /* Consume non-dirty HPTEs */ 1754 while ((index < htabslots) 1755 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1756 index++; 1757 examined++; 1758 } 1759 1760 chunkstart = index; 1761 /* Consume valid dirty HPTEs */ 1762 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1763 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1764 && HPTE_VALID(HPTE(spapr->htab, index))) { 1765 CLEAN_HPTE(HPTE(spapr->htab, index)); 1766 index++; 1767 examined++; 1768 } 1769 1770 invalidstart = index; 1771 /* Consume invalid dirty HPTEs */ 1772 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1773 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1774 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1775 CLEAN_HPTE(HPTE(spapr->htab, index)); 1776 index++; 1777 examined++; 1778 } 1779 1780 if (index > chunkstart) { 1781 int n_valid = invalidstart - chunkstart; 1782 int n_invalid = index - invalidstart; 1783 1784 qemu_put_be32(f, chunkstart); 1785 qemu_put_be16(f, n_valid); 1786 qemu_put_be16(f, n_invalid); 1787 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1788 HASH_PTE_SIZE_64 * n_valid); 1789 sent += index - chunkstart; 1790 1791 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1792 break; 1793 } 1794 } 1795 1796 if (examined >= htabslots) { 1797 break; 1798 } 1799 1800 if (index >= htabslots) { 1801 assert(index == htabslots); 1802 index = 0; 1803 } 1804 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1805 1806 if (index >= htabslots) { 1807 assert(index == htabslots); 1808 index = 0; 1809 } 1810 1811 spapr->htab_save_index = index; 1812 1813 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1814 } 1815 1816 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1817 #define MAX_KVM_BUF_SIZE 2048 1818 1819 static int htab_save_iterate(QEMUFile *f, void *opaque) 1820 { 1821 sPAPRMachineState *spapr = opaque; 1822 int fd; 1823 int rc = 0; 1824 1825 /* Iteration header */ 1826 if (!spapr->htab_shift) { 1827 qemu_put_be32(f, -1); 1828 return 1; 1829 } else { 1830 qemu_put_be32(f, 0); 1831 } 1832 1833 if (!spapr->htab) { 1834 assert(kvm_enabled()); 1835 1836 fd = get_htab_fd(spapr); 1837 if (fd < 0) { 1838 return fd; 1839 } 1840 1841 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1842 if (rc < 0) { 1843 return rc; 1844 } 1845 } else if (spapr->htab_first_pass) { 1846 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1847 } else { 1848 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1849 } 1850 1851 /* End marker */ 1852 qemu_put_be32(f, 0); 1853 qemu_put_be16(f, 0); 1854 qemu_put_be16(f, 0); 1855 1856 return rc; 1857 } 1858 1859 static int htab_save_complete(QEMUFile *f, void *opaque) 1860 { 1861 sPAPRMachineState *spapr = opaque; 1862 int fd; 1863 1864 /* Iteration header */ 1865 if (!spapr->htab_shift) { 1866 qemu_put_be32(f, -1); 1867 return 0; 1868 } else { 1869 qemu_put_be32(f, 0); 1870 } 1871 1872 if (!spapr->htab) { 1873 int rc; 1874 1875 assert(kvm_enabled()); 1876 1877 fd = get_htab_fd(spapr); 1878 if (fd < 0) { 1879 return fd; 1880 } 1881 1882 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1883 if (rc < 0) { 1884 return rc; 1885 } 1886 } else { 1887 if (spapr->htab_first_pass) { 1888 htab_save_first_pass(f, spapr, -1); 1889 } 1890 htab_save_later_pass(f, spapr, -1); 1891 } 1892 1893 /* End marker */ 1894 qemu_put_be32(f, 0); 1895 qemu_put_be16(f, 0); 1896 qemu_put_be16(f, 0); 1897 1898 return 0; 1899 } 1900 1901 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1902 { 1903 sPAPRMachineState *spapr = opaque; 1904 uint32_t section_hdr; 1905 int fd = -1; 1906 1907 if (version_id < 1 || version_id > 1) { 1908 error_report("htab_load() bad version"); 1909 return -EINVAL; 1910 } 1911 1912 section_hdr = qemu_get_be32(f); 1913 1914 if (section_hdr == -1) { 1915 spapr_free_hpt(spapr); 1916 return 0; 1917 } 1918 1919 if (section_hdr) { 1920 Error *local_err = NULL; 1921 1922 /* First section gives the htab size */ 1923 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1924 if (local_err) { 1925 error_report_err(local_err); 1926 return -EINVAL; 1927 } 1928 return 0; 1929 } 1930 1931 if (!spapr->htab) { 1932 assert(kvm_enabled()); 1933 1934 fd = kvmppc_get_htab_fd(true); 1935 if (fd < 0) { 1936 error_report("Unable to open fd to restore KVM hash table: %s", 1937 strerror(errno)); 1938 } 1939 } 1940 1941 while (true) { 1942 uint32_t index; 1943 uint16_t n_valid, n_invalid; 1944 1945 index = qemu_get_be32(f); 1946 n_valid = qemu_get_be16(f); 1947 n_invalid = qemu_get_be16(f); 1948 1949 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1950 /* End of Stream */ 1951 break; 1952 } 1953 1954 if ((index + n_valid + n_invalid) > 1955 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1956 /* Bad index in stream */ 1957 error_report( 1958 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1959 index, n_valid, n_invalid, spapr->htab_shift); 1960 return -EINVAL; 1961 } 1962 1963 if (spapr->htab) { 1964 if (n_valid) { 1965 qemu_get_buffer(f, HPTE(spapr->htab, index), 1966 HASH_PTE_SIZE_64 * n_valid); 1967 } 1968 if (n_invalid) { 1969 memset(HPTE(spapr->htab, index + n_valid), 0, 1970 HASH_PTE_SIZE_64 * n_invalid); 1971 } 1972 } else { 1973 int rc; 1974 1975 assert(fd >= 0); 1976 1977 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1978 if (rc < 0) { 1979 return rc; 1980 } 1981 } 1982 } 1983 1984 if (!spapr->htab) { 1985 assert(fd >= 0); 1986 close(fd); 1987 } 1988 1989 return 0; 1990 } 1991 1992 static void htab_save_cleanup(void *opaque) 1993 { 1994 sPAPRMachineState *spapr = opaque; 1995 1996 close_htab_fd(spapr); 1997 } 1998 1999 static SaveVMHandlers savevm_htab_handlers = { 2000 .save_setup = htab_save_setup, 2001 .save_live_iterate = htab_save_iterate, 2002 .save_live_complete_precopy = htab_save_complete, 2003 .save_cleanup = htab_save_cleanup, 2004 .load_state = htab_load, 2005 }; 2006 2007 static void spapr_boot_set(void *opaque, const char *boot_device, 2008 Error **errp) 2009 { 2010 MachineState *machine = MACHINE(qdev_get_machine()); 2011 machine->boot_order = g_strdup(boot_device); 2012 } 2013 2014 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 2015 { 2016 MachineState *machine = MACHINE(spapr); 2017 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2018 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2019 int i; 2020 2021 for (i = 0; i < nr_lmbs; i++) { 2022 uint64_t addr; 2023 2024 addr = i * lmb_size + spapr->hotplug_memory.base; 2025 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2026 addr / lmb_size); 2027 } 2028 } 2029 2030 /* 2031 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2032 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2033 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2034 */ 2035 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2036 { 2037 int i; 2038 2039 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2040 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2041 " is not aligned to %llu MiB", 2042 machine->ram_size, 2043 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2044 return; 2045 } 2046 2047 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2048 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2049 " is not aligned to %llu MiB", 2050 machine->ram_size, 2051 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2052 return; 2053 } 2054 2055 for (i = 0; i < nb_numa_nodes; i++) { 2056 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2057 error_setg(errp, 2058 "Node %d memory size 0x%" PRIx64 2059 " is not aligned to %llu MiB", 2060 i, numa_info[i].node_mem, 2061 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2062 return; 2063 } 2064 } 2065 } 2066 2067 /* find cpu slot in machine->possible_cpus by core_id */ 2068 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2069 { 2070 int index = id / smp_threads; 2071 2072 if (index >= ms->possible_cpus->len) { 2073 return NULL; 2074 } 2075 if (idx) { 2076 *idx = index; 2077 } 2078 return &ms->possible_cpus->cpus[index]; 2079 } 2080 2081 static void spapr_init_cpus(sPAPRMachineState *spapr) 2082 { 2083 MachineState *machine = MACHINE(spapr); 2084 MachineClass *mc = MACHINE_GET_CLASS(machine); 2085 char *type = spapr_get_cpu_core_type(machine->cpu_model); 2086 int smt = kvmppc_smt_threads(); 2087 const CPUArchIdList *possible_cpus; 2088 int boot_cores_nr = smp_cpus / smp_threads; 2089 int i; 2090 2091 if (!type) { 2092 error_report("Unable to find sPAPR CPU Core definition"); 2093 exit(1); 2094 } 2095 2096 possible_cpus = mc->possible_cpu_arch_ids(machine); 2097 if (mc->has_hotpluggable_cpus) { 2098 if (smp_cpus % smp_threads) { 2099 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2100 smp_cpus, smp_threads); 2101 exit(1); 2102 } 2103 if (max_cpus % smp_threads) { 2104 error_report("max_cpus (%u) must be multiple of threads (%u)", 2105 max_cpus, smp_threads); 2106 exit(1); 2107 } 2108 } else { 2109 if (max_cpus != smp_cpus) { 2110 error_report("This machine version does not support CPU hotplug"); 2111 exit(1); 2112 } 2113 boot_cores_nr = possible_cpus->len; 2114 } 2115 2116 for (i = 0; i < possible_cpus->len; i++) { 2117 int core_id = i * smp_threads; 2118 2119 if (mc->has_hotpluggable_cpus) { 2120 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2121 (core_id / smp_threads) * smt); 2122 } 2123 2124 if (i < boot_cores_nr) { 2125 Object *core = object_new(type); 2126 int nr_threads = smp_threads; 2127 2128 /* Handle the partially filled core for older machine types */ 2129 if ((i + 1) * smp_threads >= smp_cpus) { 2130 nr_threads = smp_cpus - i * smp_threads; 2131 } 2132 2133 object_property_set_int(core, nr_threads, "nr-threads", 2134 &error_fatal); 2135 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2136 &error_fatal); 2137 object_property_set_bool(core, true, "realized", &error_fatal); 2138 } 2139 } 2140 g_free(type); 2141 } 2142 2143 /* pSeries LPAR / sPAPR hardware init */ 2144 static void ppc_spapr_init(MachineState *machine) 2145 { 2146 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2147 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2148 const char *kernel_filename = machine->kernel_filename; 2149 const char *initrd_filename = machine->initrd_filename; 2150 PCIHostState *phb; 2151 int i; 2152 MemoryRegion *sysmem = get_system_memory(); 2153 MemoryRegion *ram = g_new(MemoryRegion, 1); 2154 MemoryRegion *rma_region; 2155 void *rma = NULL; 2156 hwaddr rma_alloc_size; 2157 hwaddr node0_size = spapr_node0_size(); 2158 long load_limit, fw_size; 2159 char *filename; 2160 Error *resize_hpt_err = NULL; 2161 2162 msi_nonbroken = true; 2163 2164 QLIST_INIT(&spapr->phbs); 2165 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2166 2167 /* Check HPT resizing availability */ 2168 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2169 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2170 /* 2171 * If the user explicitly requested a mode we should either 2172 * supply it, or fail completely (which we do below). But if 2173 * it's not set explicitly, we reset our mode to something 2174 * that works 2175 */ 2176 if (resize_hpt_err) { 2177 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2178 error_free(resize_hpt_err); 2179 resize_hpt_err = NULL; 2180 } else { 2181 spapr->resize_hpt = smc->resize_hpt_default; 2182 } 2183 } 2184 2185 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2186 2187 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2188 /* 2189 * User requested HPT resize, but this host can't supply it. Bail out 2190 */ 2191 error_report_err(resize_hpt_err); 2192 exit(1); 2193 } 2194 2195 /* Allocate RMA if necessary */ 2196 rma_alloc_size = kvmppc_alloc_rma(&rma); 2197 2198 if (rma_alloc_size == -1) { 2199 error_report("Unable to create RMA"); 2200 exit(1); 2201 } 2202 2203 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 2204 spapr->rma_size = rma_alloc_size; 2205 } else { 2206 spapr->rma_size = node0_size; 2207 2208 /* With KVM, we don't actually know whether KVM supports an 2209 * unbounded RMA (PR KVM) or is limited by the hash table size 2210 * (HV KVM using VRMA), so we always assume the latter 2211 * 2212 * In that case, we also limit the initial allocations for RTAS 2213 * etc... to 256M since we have no way to know what the VRMA size 2214 * is going to be as it depends on the size of the hash table 2215 * isn't determined yet. 2216 */ 2217 if (kvm_enabled()) { 2218 spapr->vrma_adjust = 1; 2219 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2220 } 2221 2222 /* Actually we don't support unbounded RMA anymore since we 2223 * added proper emulation of HV mode. The max we can get is 2224 * 16G which also happens to be what we configure for PAPR 2225 * mode so make sure we don't do anything bigger than that 2226 */ 2227 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2228 } 2229 2230 if (spapr->rma_size > node0_size) { 2231 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2232 spapr->rma_size); 2233 exit(1); 2234 } 2235 2236 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2237 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2238 2239 /* Set up Interrupt Controller before we create the VCPUs */ 2240 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); 2241 2242 /* Set up containers for ibm,client-set-architecture negotiated options */ 2243 spapr->ov5 = spapr_ovec_new(); 2244 spapr->ov5_cas = spapr_ovec_new(); 2245 2246 if (smc->dr_lmb_enabled) { 2247 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2248 spapr_validate_node_memory(machine, &error_fatal); 2249 } 2250 2251 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2252 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) { 2253 /* KVM and TCG always allow GTSE with radix... */ 2254 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2255 } 2256 /* ... but not with hash (currently). */ 2257 2258 /* advertise support for dedicated HP event source to guests */ 2259 if (spapr->use_hotplug_event_source) { 2260 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2261 } 2262 2263 /* advertise support for HPT resizing */ 2264 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2265 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2266 } 2267 2268 /* init CPUs */ 2269 if (machine->cpu_model == NULL) { 2270 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; 2271 } 2272 2273 spapr_cpu_parse_features(spapr); 2274 2275 spapr_init_cpus(spapr); 2276 2277 if (kvm_enabled()) { 2278 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2279 kvmppc_enable_logical_ci_hcalls(); 2280 kvmppc_enable_set_mode_hcall(); 2281 2282 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2283 kvmppc_enable_clear_ref_mod_hcalls(); 2284 } 2285 2286 /* allocate RAM */ 2287 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2288 machine->ram_size); 2289 memory_region_add_subregion(sysmem, 0, ram); 2290 2291 if (rma_alloc_size && rma) { 2292 rma_region = g_new(MemoryRegion, 1); 2293 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 2294 rma_alloc_size, rma); 2295 vmstate_register_ram_global(rma_region); 2296 memory_region_add_subregion(sysmem, 0, rma_region); 2297 } 2298 2299 /* initialize hotplug memory address space */ 2300 if (machine->ram_size < machine->maxram_size) { 2301 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2302 /* 2303 * Limit the number of hotpluggable memory slots to half the number 2304 * slots that KVM supports, leaving the other half for PCI and other 2305 * devices. However ensure that number of slots doesn't drop below 32. 2306 */ 2307 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2308 SPAPR_MAX_RAM_SLOTS; 2309 2310 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2311 max_memslots = SPAPR_MAX_RAM_SLOTS; 2312 } 2313 if (machine->ram_slots > max_memslots) { 2314 error_report("Specified number of memory slots %" 2315 PRIu64" exceeds max supported %d", 2316 machine->ram_slots, max_memslots); 2317 exit(1); 2318 } 2319 2320 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2321 SPAPR_HOTPLUG_MEM_ALIGN); 2322 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2323 "hotplug-memory", hotplug_mem_size); 2324 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2325 &spapr->hotplug_memory.mr); 2326 } 2327 2328 if (smc->dr_lmb_enabled) { 2329 spapr_create_lmb_dr_connectors(spapr); 2330 } 2331 2332 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2333 if (!filename) { 2334 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2335 exit(1); 2336 } 2337 spapr->rtas_size = get_image_size(filename); 2338 if (spapr->rtas_size < 0) { 2339 error_report("Could not get size of LPAR rtas '%s'", filename); 2340 exit(1); 2341 } 2342 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2343 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2344 error_report("Could not load LPAR rtas '%s'", filename); 2345 exit(1); 2346 } 2347 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2348 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2349 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2350 exit(1); 2351 } 2352 g_free(filename); 2353 2354 /* Set up RTAS event infrastructure */ 2355 spapr_events_init(spapr); 2356 2357 /* Set up the RTC RTAS interfaces */ 2358 spapr_rtc_create(spapr); 2359 2360 /* Set up VIO bus */ 2361 spapr->vio_bus = spapr_vio_bus_init(); 2362 2363 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 2364 if (serial_hds[i]) { 2365 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 2366 } 2367 } 2368 2369 /* We always have at least the nvram device on VIO */ 2370 spapr_create_nvram(spapr); 2371 2372 /* Set up PCI */ 2373 spapr_pci_rtas_init(); 2374 2375 phb = spapr_create_phb(spapr, 0); 2376 2377 for (i = 0; i < nb_nics; i++) { 2378 NICInfo *nd = &nd_table[i]; 2379 2380 if (!nd->model) { 2381 nd->model = g_strdup("ibmveth"); 2382 } 2383 2384 if (strcmp(nd->model, "ibmveth") == 0) { 2385 spapr_vlan_create(spapr->vio_bus, nd); 2386 } else { 2387 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2388 } 2389 } 2390 2391 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2392 spapr_vscsi_create(spapr->vio_bus); 2393 } 2394 2395 /* Graphics */ 2396 if (spapr_vga_init(phb->bus, &error_fatal)) { 2397 spapr->has_graphics = true; 2398 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2399 } 2400 2401 if (machine->usb) { 2402 if (smc->use_ohci_by_default) { 2403 pci_create_simple(phb->bus, -1, "pci-ohci"); 2404 } else { 2405 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2406 } 2407 2408 if (spapr->has_graphics) { 2409 USBBus *usb_bus = usb_bus_find(-1); 2410 2411 usb_create_simple(usb_bus, "usb-kbd"); 2412 usb_create_simple(usb_bus, "usb-mouse"); 2413 } 2414 } 2415 2416 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2417 error_report( 2418 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2419 MIN_RMA_SLOF); 2420 exit(1); 2421 } 2422 2423 if (kernel_filename) { 2424 uint64_t lowaddr = 0; 2425 2426 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2427 NULL, NULL, &lowaddr, NULL, 1, 2428 PPC_ELF_MACHINE, 0, 0); 2429 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2430 spapr->kernel_size = load_elf(kernel_filename, 2431 translate_kernel_address, NULL, NULL, 2432 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2433 0, 0); 2434 spapr->kernel_le = spapr->kernel_size > 0; 2435 } 2436 if (spapr->kernel_size < 0) { 2437 error_report("error loading %s: %s", kernel_filename, 2438 load_elf_strerror(spapr->kernel_size)); 2439 exit(1); 2440 } 2441 2442 /* load initrd */ 2443 if (initrd_filename) { 2444 /* Try to locate the initrd in the gap between the kernel 2445 * and the firmware. Add a bit of space just in case 2446 */ 2447 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2448 + 0x1ffff) & ~0xffff; 2449 spapr->initrd_size = load_image_targphys(initrd_filename, 2450 spapr->initrd_base, 2451 load_limit 2452 - spapr->initrd_base); 2453 if (spapr->initrd_size < 0) { 2454 error_report("could not load initial ram disk '%s'", 2455 initrd_filename); 2456 exit(1); 2457 } 2458 } 2459 } 2460 2461 if (bios_name == NULL) { 2462 bios_name = FW_FILE_NAME; 2463 } 2464 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2465 if (!filename) { 2466 error_report("Could not find LPAR firmware '%s'", bios_name); 2467 exit(1); 2468 } 2469 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2470 if (fw_size <= 0) { 2471 error_report("Could not load LPAR firmware '%s'", filename); 2472 exit(1); 2473 } 2474 g_free(filename); 2475 2476 /* FIXME: Should register things through the MachineState's qdev 2477 * interface, this is a legacy from the sPAPREnvironment structure 2478 * which predated MachineState but had a similar function */ 2479 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2480 register_savevm_live(NULL, "spapr/htab", -1, 1, 2481 &savevm_htab_handlers, spapr); 2482 2483 qemu_register_boot_set(spapr_boot_set, spapr); 2484 2485 if (kvm_enabled()) { 2486 /* to stop and start vmclock */ 2487 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2488 &spapr->tb); 2489 2490 kvmppc_spapr_enable_inkernel_multitce(); 2491 } 2492 } 2493 2494 static int spapr_kvm_type(const char *vm_type) 2495 { 2496 if (!vm_type) { 2497 return 0; 2498 } 2499 2500 if (!strcmp(vm_type, "HV")) { 2501 return 1; 2502 } 2503 2504 if (!strcmp(vm_type, "PR")) { 2505 return 2; 2506 } 2507 2508 error_report("Unknown kvm-type specified '%s'", vm_type); 2509 exit(1); 2510 } 2511 2512 /* 2513 * Implementation of an interface to adjust firmware path 2514 * for the bootindex property handling. 2515 */ 2516 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2517 DeviceState *dev) 2518 { 2519 #define CAST(type, obj, name) \ 2520 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2521 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2522 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2523 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 2524 2525 if (d) { 2526 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2527 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2528 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2529 2530 if (spapr) { 2531 /* 2532 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2533 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2534 * in the top 16 bits of the 64-bit LUN 2535 */ 2536 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2537 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2538 (uint64_t)id << 48); 2539 } else if (virtio) { 2540 /* 2541 * We use SRP luns of the form 01000000 | (target << 8) | lun 2542 * in the top 32 bits of the 64-bit LUN 2543 * Note: the quote above is from SLOF and it is wrong, 2544 * the actual binding is: 2545 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2546 */ 2547 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2548 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2549 (uint64_t)id << 32); 2550 } else if (usb) { 2551 /* 2552 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2553 * in the top 32 bits of the 64-bit LUN 2554 */ 2555 unsigned usb_port = atoi(usb->port->path); 2556 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2557 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2558 (uint64_t)id << 32); 2559 } 2560 } 2561 2562 /* 2563 * SLOF probes the USB devices, and if it recognizes that the device is a 2564 * storage device, it changes its name to "storage" instead of "usb-host", 2565 * and additionally adds a child node for the SCSI LUN, so the correct 2566 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2567 */ 2568 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2569 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2570 if (usb_host_dev_is_scsi_storage(usbdev)) { 2571 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2572 } 2573 } 2574 2575 if (phb) { 2576 /* Replace "pci" with "pci@800000020000000" */ 2577 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2578 } 2579 2580 if (vsc) { 2581 /* Same logic as virtio above */ 2582 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 2583 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 2584 } 2585 2586 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 2587 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 2588 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 2589 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 2590 } 2591 2592 return NULL; 2593 } 2594 2595 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2596 { 2597 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2598 2599 return g_strdup(spapr->kvm_type); 2600 } 2601 2602 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2603 { 2604 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2605 2606 g_free(spapr->kvm_type); 2607 spapr->kvm_type = g_strdup(value); 2608 } 2609 2610 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2611 { 2612 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2613 2614 return spapr->use_hotplug_event_source; 2615 } 2616 2617 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2618 Error **errp) 2619 { 2620 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2621 2622 spapr->use_hotplug_event_source = value; 2623 } 2624 2625 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 2626 { 2627 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2628 2629 switch (spapr->resize_hpt) { 2630 case SPAPR_RESIZE_HPT_DEFAULT: 2631 return g_strdup("default"); 2632 case SPAPR_RESIZE_HPT_DISABLED: 2633 return g_strdup("disabled"); 2634 case SPAPR_RESIZE_HPT_ENABLED: 2635 return g_strdup("enabled"); 2636 case SPAPR_RESIZE_HPT_REQUIRED: 2637 return g_strdup("required"); 2638 } 2639 g_assert_not_reached(); 2640 } 2641 2642 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 2643 { 2644 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2645 2646 if (strcmp(value, "default") == 0) { 2647 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 2648 } else if (strcmp(value, "disabled") == 0) { 2649 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2650 } else if (strcmp(value, "enabled") == 0) { 2651 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 2652 } else if (strcmp(value, "required") == 0) { 2653 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 2654 } else { 2655 error_setg(errp, "Bad value for \"resize-hpt\" property"); 2656 } 2657 } 2658 2659 static void spapr_machine_initfn(Object *obj) 2660 { 2661 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2662 2663 spapr->htab_fd = -1; 2664 spapr->use_hotplug_event_source = true; 2665 object_property_add_str(obj, "kvm-type", 2666 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2667 object_property_set_description(obj, "kvm-type", 2668 "Specifies the KVM virtualization mode (HV, PR)", 2669 NULL); 2670 object_property_add_bool(obj, "modern-hotplug-events", 2671 spapr_get_modern_hotplug_events, 2672 spapr_set_modern_hotplug_events, 2673 NULL); 2674 object_property_set_description(obj, "modern-hotplug-events", 2675 "Use dedicated hotplug event mechanism in" 2676 " place of standard EPOW events when possible" 2677 " (required for memory hot-unplug support)", 2678 NULL); 2679 2680 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 2681 "Maximum permitted CPU compatibility mode", 2682 &error_fatal); 2683 2684 object_property_add_str(obj, "resize-hpt", 2685 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 2686 object_property_set_description(obj, "resize-hpt", 2687 "Resizing of the Hash Page Table (enabled, disabled, required)", 2688 NULL); 2689 } 2690 2691 static void spapr_machine_finalizefn(Object *obj) 2692 { 2693 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2694 2695 g_free(spapr->kvm_type); 2696 } 2697 2698 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 2699 { 2700 cpu_synchronize_state(cs); 2701 ppc_cpu_do_system_reset(cs); 2702 } 2703 2704 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2705 { 2706 CPUState *cs; 2707 2708 CPU_FOREACH(cs) { 2709 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 2710 } 2711 } 2712 2713 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2714 uint32_t node, bool dedicated_hp_event_source, 2715 Error **errp) 2716 { 2717 sPAPRDRConnector *drc; 2718 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2719 int i, fdt_offset, fdt_size; 2720 void *fdt; 2721 uint64_t addr = addr_start; 2722 bool hotplugged = spapr_drc_hotplugged(dev); 2723 Error *local_err = NULL; 2724 2725 for (i = 0; i < nr_lmbs; i++) { 2726 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2727 addr / SPAPR_MEMORY_BLOCK_SIZE); 2728 g_assert(drc); 2729 2730 fdt = create_device_tree(&fdt_size); 2731 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2732 SPAPR_MEMORY_BLOCK_SIZE); 2733 2734 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 2735 if (local_err) { 2736 while (addr > addr_start) { 2737 addr -= SPAPR_MEMORY_BLOCK_SIZE; 2738 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2739 addr / SPAPR_MEMORY_BLOCK_SIZE); 2740 spapr_drc_detach(drc); 2741 } 2742 g_free(fdt); 2743 error_propagate(errp, local_err); 2744 return; 2745 } 2746 if (!hotplugged) { 2747 spapr_drc_reset(drc); 2748 } 2749 addr += SPAPR_MEMORY_BLOCK_SIZE; 2750 } 2751 /* send hotplug notification to the 2752 * guest only in case of hotplugged memory 2753 */ 2754 if (hotplugged) { 2755 if (dedicated_hp_event_source) { 2756 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2757 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2758 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2759 nr_lmbs, 2760 spapr_drc_index(drc)); 2761 } else { 2762 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 2763 nr_lmbs); 2764 } 2765 } 2766 } 2767 2768 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2769 uint32_t node, Error **errp) 2770 { 2771 Error *local_err = NULL; 2772 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2773 PCDIMMDevice *dimm = PC_DIMM(dev); 2774 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2775 MemoryRegion *mr = ddc->get_memory_region(dimm); 2776 uint64_t align = memory_region_get_alignment(mr); 2777 uint64_t size = memory_region_size(mr); 2778 uint64_t addr; 2779 2780 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2781 if (local_err) { 2782 goto out; 2783 } 2784 2785 addr = object_property_get_uint(OBJECT(dimm), 2786 PC_DIMM_ADDR_PROP, &local_err); 2787 if (local_err) { 2788 goto out_unplug; 2789 } 2790 2791 spapr_add_lmbs(dev, addr, size, node, 2792 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 2793 &local_err); 2794 if (local_err) { 2795 goto out_unplug; 2796 } 2797 2798 return; 2799 2800 out_unplug: 2801 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2802 out: 2803 error_propagate(errp, local_err); 2804 } 2805 2806 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2807 Error **errp) 2808 { 2809 PCDIMMDevice *dimm = PC_DIMM(dev); 2810 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2811 MemoryRegion *mr = ddc->get_memory_region(dimm); 2812 uint64_t size = memory_region_size(mr); 2813 char *mem_dev; 2814 2815 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2816 error_setg(errp, "Hotplugged memory size must be a multiple of " 2817 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2818 return; 2819 } 2820 2821 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 2822 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 2823 error_setg(errp, "Memory backend has bad page size. " 2824 "Use 'memory-backend-file' with correct mem-path."); 2825 goto out; 2826 } 2827 2828 out: 2829 g_free(mem_dev); 2830 } 2831 2832 struct sPAPRDIMMState { 2833 PCDIMMDevice *dimm; 2834 uint32_t nr_lmbs; 2835 QTAILQ_ENTRY(sPAPRDIMMState) next; 2836 }; 2837 2838 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 2839 PCDIMMDevice *dimm) 2840 { 2841 sPAPRDIMMState *dimm_state = NULL; 2842 2843 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 2844 if (dimm_state->dimm == dimm) { 2845 break; 2846 } 2847 } 2848 return dimm_state; 2849 } 2850 2851 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 2852 uint32_t nr_lmbs, 2853 PCDIMMDevice *dimm) 2854 { 2855 sPAPRDIMMState *ds = NULL; 2856 2857 /* 2858 * If this request is for a DIMM whose removal had failed earlier 2859 * (due to guest's refusal to remove the LMBs), we would have this 2860 * dimm already in the pending_dimm_unplugs list. In that 2861 * case don't add again. 2862 */ 2863 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 2864 if (!ds) { 2865 ds = g_malloc0(sizeof(sPAPRDIMMState)); 2866 ds->nr_lmbs = nr_lmbs; 2867 ds->dimm = dimm; 2868 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 2869 } 2870 return ds; 2871 } 2872 2873 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 2874 sPAPRDIMMState *dimm_state) 2875 { 2876 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 2877 g_free(dimm_state); 2878 } 2879 2880 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 2881 PCDIMMDevice *dimm) 2882 { 2883 sPAPRDRConnector *drc; 2884 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2885 MemoryRegion *mr = ddc->get_memory_region(dimm); 2886 uint64_t size = memory_region_size(mr); 2887 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2888 uint32_t avail_lmbs = 0; 2889 uint64_t addr_start, addr; 2890 int i; 2891 2892 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 2893 &error_abort); 2894 2895 addr = addr_start; 2896 for (i = 0; i < nr_lmbs; i++) { 2897 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2898 addr / SPAPR_MEMORY_BLOCK_SIZE); 2899 g_assert(drc); 2900 if (drc->dev) { 2901 avail_lmbs++; 2902 } 2903 addr += SPAPR_MEMORY_BLOCK_SIZE; 2904 } 2905 2906 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 2907 } 2908 2909 /* Callback to be called during DRC release. */ 2910 void spapr_lmb_release(DeviceState *dev) 2911 { 2912 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_hotplug_handler(dev)); 2913 PCDIMMDevice *dimm = PC_DIMM(dev); 2914 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2915 MemoryRegion *mr = ddc->get_memory_region(dimm); 2916 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 2917 2918 /* This information will get lost if a migration occurs 2919 * during the unplug process. In this case recover it. */ 2920 if (ds == NULL) { 2921 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 2922 g_assert(ds); 2923 /* The DRC being examined by the caller at least must be counted */ 2924 g_assert(ds->nr_lmbs); 2925 } 2926 2927 if (--ds->nr_lmbs) { 2928 return; 2929 } 2930 2931 spapr_pending_dimm_unplugs_remove(spapr, ds); 2932 2933 /* 2934 * Now that all the LMBs have been removed by the guest, call the 2935 * pc-dimm unplug handler to cleanup up the pc-dimm device. 2936 */ 2937 pc_dimm_memory_unplug(dev, &spapr->hotplug_memory, mr); 2938 object_unparent(OBJECT(dev)); 2939 } 2940 2941 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 2942 DeviceState *dev, Error **errp) 2943 { 2944 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 2945 Error *local_err = NULL; 2946 PCDIMMDevice *dimm = PC_DIMM(dev); 2947 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2948 MemoryRegion *mr = ddc->get_memory_region(dimm); 2949 uint64_t size = memory_region_size(mr); 2950 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2951 uint64_t addr_start, addr; 2952 int i; 2953 sPAPRDRConnector *drc; 2954 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 2955 &local_err); 2956 if (local_err) { 2957 goto out; 2958 } 2959 2960 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 2961 2962 addr = addr_start; 2963 for (i = 0; i < nr_lmbs; i++) { 2964 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2965 addr / SPAPR_MEMORY_BLOCK_SIZE); 2966 g_assert(drc); 2967 2968 spapr_drc_detach(drc); 2969 addr += SPAPR_MEMORY_BLOCK_SIZE; 2970 } 2971 2972 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2973 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2974 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2975 nr_lmbs, spapr_drc_index(drc)); 2976 out: 2977 error_propagate(errp, local_err); 2978 } 2979 2980 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 2981 sPAPRMachineState *spapr) 2982 { 2983 PowerPCCPU *cpu = POWERPC_CPU(cs); 2984 DeviceClass *dc = DEVICE_GET_CLASS(cs); 2985 int id = ppc_get_vcpu_dt_id(cpu); 2986 void *fdt; 2987 int offset, fdt_size; 2988 char *nodename; 2989 2990 fdt = create_device_tree(&fdt_size); 2991 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 2992 offset = fdt_add_subnode(fdt, 0, nodename); 2993 2994 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 2995 g_free(nodename); 2996 2997 *fdt_offset = offset; 2998 return fdt; 2999 } 3000 3001 /* Callback to be called during DRC release. */ 3002 void spapr_core_release(DeviceState *dev) 3003 { 3004 MachineState *ms = MACHINE(qdev_get_hotplug_handler(dev)); 3005 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3006 CPUCore *cc = CPU_CORE(dev); 3007 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3008 3009 if (smc->pre_2_10_has_unused_icps) { 3010 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3011 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc)); 3012 const char *typename = object_class_get_name(scc->cpu_class); 3013 size_t size = object_type_get_instance_size(typename); 3014 int i; 3015 3016 for (i = 0; i < cc->nr_threads; i++) { 3017 CPUState *cs = CPU(sc->threads + i * size); 3018 3019 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3020 } 3021 } 3022 3023 assert(core_slot); 3024 core_slot->cpu = NULL; 3025 object_unparent(OBJECT(dev)); 3026 } 3027 3028 static 3029 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3030 Error **errp) 3031 { 3032 int index; 3033 sPAPRDRConnector *drc; 3034 CPUCore *cc = CPU_CORE(dev); 3035 int smt = kvmppc_smt_threads(); 3036 3037 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3038 error_setg(errp, "Unable to find CPU core with core-id: %d", 3039 cc->core_id); 3040 return; 3041 } 3042 if (index == 0) { 3043 error_setg(errp, "Boot CPU core may not be unplugged"); 3044 return; 3045 } 3046 3047 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); 3048 g_assert(drc); 3049 3050 spapr_drc_detach(drc); 3051 3052 spapr_hotplug_req_remove_by_index(drc); 3053 } 3054 3055 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3056 Error **errp) 3057 { 3058 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3059 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3060 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3061 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3062 CPUCore *cc = CPU_CORE(dev); 3063 CPUState *cs = CPU(core->threads); 3064 sPAPRDRConnector *drc; 3065 Error *local_err = NULL; 3066 int smt = kvmppc_smt_threads(); 3067 CPUArchId *core_slot; 3068 int index; 3069 bool hotplugged = spapr_drc_hotplugged(dev); 3070 3071 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3072 if (!core_slot) { 3073 error_setg(errp, "Unable to find CPU core with core-id: %d", 3074 cc->core_id); 3075 return; 3076 } 3077 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); 3078 3079 g_assert(drc || !mc->has_hotpluggable_cpus); 3080 3081 if (drc) { 3082 void *fdt; 3083 int fdt_offset; 3084 3085 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 3086 3087 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3088 if (local_err) { 3089 g_free(fdt); 3090 error_propagate(errp, local_err); 3091 return; 3092 } 3093 3094 if (hotplugged) { 3095 /* 3096 * Send hotplug notification interrupt to the guest only 3097 * in case of hotplugged CPUs. 3098 */ 3099 spapr_hotplug_req_add_by_index(drc); 3100 } else { 3101 spapr_drc_reset(drc); 3102 } 3103 } 3104 3105 core_slot->cpu = OBJECT(dev); 3106 3107 if (smc->pre_2_10_has_unused_icps) { 3108 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc)); 3109 const char *typename = object_class_get_name(scc->cpu_class); 3110 size_t size = object_type_get_instance_size(typename); 3111 int i; 3112 3113 for (i = 0; i < cc->nr_threads; i++) { 3114 sPAPRCPUCore *sc = SPAPR_CPU_CORE(dev); 3115 void *obj = sc->threads + i * size; 3116 3117 cs = CPU(obj); 3118 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3119 } 3120 } 3121 } 3122 3123 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3124 Error **errp) 3125 { 3126 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3127 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3128 Error *local_err = NULL; 3129 CPUCore *cc = CPU_CORE(dev); 3130 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model); 3131 const char *type = object_get_typename(OBJECT(dev)); 3132 CPUArchId *core_slot; 3133 int index; 3134 3135 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3136 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3137 goto out; 3138 } 3139 3140 if (strcmp(base_core_type, type)) { 3141 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3142 goto out; 3143 } 3144 3145 if (cc->core_id % smp_threads) { 3146 error_setg(&local_err, "invalid core id %d", cc->core_id); 3147 goto out; 3148 } 3149 3150 /* 3151 * In general we should have homogeneous threads-per-core, but old 3152 * (pre hotplug support) machine types allow the last core to have 3153 * reduced threads as a compatibility hack for when we allowed 3154 * total vcpus not a multiple of threads-per-core. 3155 */ 3156 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3157 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3158 cc->nr_threads, smp_threads); 3159 goto out; 3160 } 3161 3162 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3163 if (!core_slot) { 3164 error_setg(&local_err, "core id %d out of range", cc->core_id); 3165 goto out; 3166 } 3167 3168 if (core_slot->cpu) { 3169 error_setg(&local_err, "core %d already populated", cc->core_id); 3170 goto out; 3171 } 3172 3173 numa_cpu_pre_plug(core_slot, dev, &local_err); 3174 3175 out: 3176 g_free(base_core_type); 3177 error_propagate(errp, local_err); 3178 } 3179 3180 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3181 DeviceState *dev, Error **errp) 3182 { 3183 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 3184 3185 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3186 int node; 3187 3188 if (!smc->dr_lmb_enabled) { 3189 error_setg(errp, "Memory hotplug not supported for this machine"); 3190 return; 3191 } 3192 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 3193 if (*errp) { 3194 return; 3195 } 3196 if (node < 0 || node >= MAX_NODES) { 3197 error_setg(errp, "Invaild node %d", node); 3198 return; 3199 } 3200 3201 /* 3202 * Currently PowerPC kernel doesn't allow hot-adding memory to 3203 * memory-less node, but instead will silently add the memory 3204 * to the first node that has some memory. This causes two 3205 * unexpected behaviours for the user. 3206 * 3207 * - Memory gets hotplugged to a different node than what the user 3208 * specified. 3209 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 3210 * to memory-less node, a reboot will set things accordingly 3211 * and the previously hotplugged memory now ends in the right node. 3212 * This appears as if some memory moved from one node to another. 3213 * 3214 * So until kernel starts supporting memory hotplug to memory-less 3215 * nodes, just prevent such attempts upfront in QEMU. 3216 */ 3217 if (nb_numa_nodes && !numa_info[node].node_mem) { 3218 error_setg(errp, "Can't hotplug memory to memory-less node %d", 3219 node); 3220 return; 3221 } 3222 3223 spapr_memory_plug(hotplug_dev, dev, node, errp); 3224 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3225 spapr_core_plug(hotplug_dev, dev, errp); 3226 } 3227 } 3228 3229 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3230 DeviceState *dev, Error **errp) 3231 { 3232 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 3233 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 3234 3235 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3236 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3237 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3238 } else { 3239 /* NOTE: this means there is a window after guest reset, prior to 3240 * CAS negotiation, where unplug requests will fail due to the 3241 * capability not being detected yet. This is a bit different than 3242 * the case with PCI unplug, where the events will be queued and 3243 * eventually handled by the guest after boot 3244 */ 3245 error_setg(errp, "Memory hot unplug not supported for this guest"); 3246 } 3247 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3248 if (!mc->has_hotpluggable_cpus) { 3249 error_setg(errp, "CPU hot unplug not supported on this machine"); 3250 return; 3251 } 3252 spapr_core_unplug_request(hotplug_dev, dev, errp); 3253 } 3254 } 3255 3256 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3257 DeviceState *dev, Error **errp) 3258 { 3259 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3260 spapr_memory_pre_plug(hotplug_dev, dev, errp); 3261 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3262 spapr_core_pre_plug(hotplug_dev, dev, errp); 3263 } 3264 } 3265 3266 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3267 DeviceState *dev) 3268 { 3269 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3270 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3271 return HOTPLUG_HANDLER(machine); 3272 } 3273 return NULL; 3274 } 3275 3276 static CpuInstanceProperties 3277 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3278 { 3279 CPUArchId *core_slot; 3280 MachineClass *mc = MACHINE_GET_CLASS(machine); 3281 3282 /* make sure possible_cpu are intialized */ 3283 mc->possible_cpu_arch_ids(machine); 3284 /* get CPU core slot containing thread that matches cpu_index */ 3285 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3286 assert(core_slot); 3287 return core_slot->props; 3288 } 3289 3290 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3291 { 3292 int i; 3293 int spapr_max_cores = max_cpus / smp_threads; 3294 MachineClass *mc = MACHINE_GET_CLASS(machine); 3295 3296 if (!mc->has_hotpluggable_cpus) { 3297 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3298 } 3299 if (machine->possible_cpus) { 3300 assert(machine->possible_cpus->len == spapr_max_cores); 3301 return machine->possible_cpus; 3302 } 3303 3304 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3305 sizeof(CPUArchId) * spapr_max_cores); 3306 machine->possible_cpus->len = spapr_max_cores; 3307 for (i = 0; i < machine->possible_cpus->len; i++) { 3308 int core_id = i * smp_threads; 3309 3310 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3311 machine->possible_cpus->cpus[i].arch_id = core_id; 3312 machine->possible_cpus->cpus[i].props.has_core_id = true; 3313 machine->possible_cpus->cpus[i].props.core_id = core_id; 3314 3315 /* default distribution of CPUs over NUMA nodes */ 3316 if (nb_numa_nodes) { 3317 /* preset values but do not enable them i.e. 'has_node_id = false', 3318 * numa init code will enable them later if manual mapping wasn't 3319 * present on CLI */ 3320 machine->possible_cpus->cpus[i].props.node_id = 3321 core_id / smp_threads / smp_cores % nb_numa_nodes; 3322 } 3323 } 3324 return machine->possible_cpus; 3325 } 3326 3327 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3328 uint64_t *buid, hwaddr *pio, 3329 hwaddr *mmio32, hwaddr *mmio64, 3330 unsigned n_dma, uint32_t *liobns, Error **errp) 3331 { 3332 /* 3333 * New-style PHB window placement. 3334 * 3335 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3336 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3337 * windows. 3338 * 3339 * Some guest kernels can't work with MMIO windows above 1<<46 3340 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3341 * 3342 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3343 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3344 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3345 * 1TiB 64-bit MMIO windows for each PHB. 3346 */ 3347 const uint64_t base_buid = 0x800000020000000ULL; 3348 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3349 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3350 int i; 3351 3352 /* Sanity check natural alignments */ 3353 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3354 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3355 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3356 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3357 /* Sanity check bounds */ 3358 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3359 SPAPR_PCI_MEM32_WIN_SIZE); 3360 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3361 SPAPR_PCI_MEM64_WIN_SIZE); 3362 3363 if (index >= SPAPR_MAX_PHBS) { 3364 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3365 SPAPR_MAX_PHBS - 1); 3366 return; 3367 } 3368 3369 *buid = base_buid + index; 3370 for (i = 0; i < n_dma; ++i) { 3371 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3372 } 3373 3374 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3375 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3376 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3377 } 3378 3379 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3380 { 3381 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3382 3383 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3384 } 3385 3386 static void spapr_ics_resend(XICSFabric *dev) 3387 { 3388 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3389 3390 ics_resend(spapr->ics); 3391 } 3392 3393 static ICPState *spapr_icp_get(XICSFabric *xi, int cpu_dt_id) 3394 { 3395 PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id); 3396 3397 return cpu ? ICP(cpu->intc) : NULL; 3398 } 3399 3400 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3401 Monitor *mon) 3402 { 3403 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3404 CPUState *cs; 3405 3406 CPU_FOREACH(cs) { 3407 PowerPCCPU *cpu = POWERPC_CPU(cs); 3408 3409 icp_pic_print_info(ICP(cpu->intc), mon); 3410 } 3411 3412 ics_pic_print_info(spapr->ics, mon); 3413 } 3414 3415 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3416 { 3417 MachineClass *mc = MACHINE_CLASS(oc); 3418 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3419 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3420 NMIClass *nc = NMI_CLASS(oc); 3421 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3422 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3423 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3424 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3425 3426 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3427 3428 /* 3429 * We set up the default / latest behaviour here. The class_init 3430 * functions for the specific versioned machine types can override 3431 * these details for backwards compatibility 3432 */ 3433 mc->init = ppc_spapr_init; 3434 mc->reset = ppc_spapr_reset; 3435 mc->block_default_type = IF_SCSI; 3436 mc->max_cpus = 1024; 3437 mc->no_parallel = 1; 3438 mc->default_boot_order = ""; 3439 mc->default_ram_size = 512 * M_BYTE; 3440 mc->kvm_type = spapr_kvm_type; 3441 mc->has_dynamic_sysbus = true; 3442 mc->pci_allow_0_address = true; 3443 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3444 hc->pre_plug = spapr_machine_device_pre_plug; 3445 hc->plug = spapr_machine_device_plug; 3446 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 3447 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3448 hc->unplug_request = spapr_machine_device_unplug_request; 3449 3450 smc->dr_lmb_enabled = true; 3451 smc->tcg_default_cpu = "POWER8"; 3452 mc->has_hotpluggable_cpus = true; 3453 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 3454 fwc->get_dev_path = spapr_get_fw_dev_path; 3455 nc->nmi_monitor_handler = spapr_nmi; 3456 smc->phb_placement = spapr_phb_placement; 3457 vhc->hypercall = emulate_spapr_hypercall; 3458 vhc->hpt_mask = spapr_hpt_mask; 3459 vhc->map_hptes = spapr_map_hptes; 3460 vhc->unmap_hptes = spapr_unmap_hptes; 3461 vhc->store_hpte = spapr_store_hpte; 3462 vhc->get_patbe = spapr_get_patbe; 3463 xic->ics_get = spapr_ics_get; 3464 xic->ics_resend = spapr_ics_resend; 3465 xic->icp_get = spapr_icp_get; 3466 ispc->print_info = spapr_pic_print_info; 3467 /* Force NUMA node memory size to be a multiple of 3468 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 3469 * in which LMBs are represented and hot-added 3470 */ 3471 mc->numa_mem_align_shift = 28; 3472 } 3473 3474 static const TypeInfo spapr_machine_info = { 3475 .name = TYPE_SPAPR_MACHINE, 3476 .parent = TYPE_MACHINE, 3477 .abstract = true, 3478 .instance_size = sizeof(sPAPRMachineState), 3479 .instance_init = spapr_machine_initfn, 3480 .instance_finalize = spapr_machine_finalizefn, 3481 .class_size = sizeof(sPAPRMachineClass), 3482 .class_init = spapr_machine_class_init, 3483 .interfaces = (InterfaceInfo[]) { 3484 { TYPE_FW_PATH_PROVIDER }, 3485 { TYPE_NMI }, 3486 { TYPE_HOTPLUG_HANDLER }, 3487 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3488 { TYPE_XICS_FABRIC }, 3489 { TYPE_INTERRUPT_STATS_PROVIDER }, 3490 { } 3491 }, 3492 }; 3493 3494 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3495 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3496 void *data) \ 3497 { \ 3498 MachineClass *mc = MACHINE_CLASS(oc); \ 3499 spapr_machine_##suffix##_class_options(mc); \ 3500 if (latest) { \ 3501 mc->alias = "pseries"; \ 3502 mc->is_default = 1; \ 3503 } \ 3504 } \ 3505 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3506 { \ 3507 MachineState *machine = MACHINE(obj); \ 3508 spapr_machine_##suffix##_instance_options(machine); \ 3509 } \ 3510 static const TypeInfo spapr_machine_##suffix##_info = { \ 3511 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3512 .parent = TYPE_SPAPR_MACHINE, \ 3513 .class_init = spapr_machine_##suffix##_class_init, \ 3514 .instance_init = spapr_machine_##suffix##_instance_init, \ 3515 }; \ 3516 static void spapr_machine_register_##suffix(void) \ 3517 { \ 3518 type_register(&spapr_machine_##suffix##_info); \ 3519 } \ 3520 type_init(spapr_machine_register_##suffix) 3521 3522 /* 3523 * pseries-2.10 3524 */ 3525 static void spapr_machine_2_10_instance_options(MachineState *machine) 3526 { 3527 } 3528 3529 static void spapr_machine_2_10_class_options(MachineClass *mc) 3530 { 3531 /* Defaults for the latest behaviour inherited from the base class */ 3532 } 3533 3534 DEFINE_SPAPR_MACHINE(2_10, "2.10", true); 3535 3536 /* 3537 * pseries-2.9 3538 */ 3539 #define SPAPR_COMPAT_2_9 \ 3540 HW_COMPAT_2_9 \ 3541 { \ 3542 .driver = TYPE_POWERPC_CPU, \ 3543 .property = "pre-2.10-migration", \ 3544 .value = "on", \ 3545 }, \ 3546 3547 static void spapr_machine_2_9_instance_options(MachineState *machine) 3548 { 3549 spapr_machine_2_10_instance_options(machine); 3550 } 3551 3552 static void spapr_machine_2_9_class_options(MachineClass *mc) 3553 { 3554 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3555 3556 spapr_machine_2_10_class_options(mc); 3557 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); 3558 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 3559 smc->pre_2_10_has_unused_icps = true; 3560 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 3561 } 3562 3563 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 3564 3565 /* 3566 * pseries-2.8 3567 */ 3568 #define SPAPR_COMPAT_2_8 \ 3569 HW_COMPAT_2_8 \ 3570 { \ 3571 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3572 .property = "pcie-extended-configuration-space", \ 3573 .value = "off", \ 3574 }, 3575 3576 static void spapr_machine_2_8_instance_options(MachineState *machine) 3577 { 3578 spapr_machine_2_9_instance_options(machine); 3579 } 3580 3581 static void spapr_machine_2_8_class_options(MachineClass *mc) 3582 { 3583 spapr_machine_2_9_class_options(mc); 3584 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 3585 mc->numa_mem_align_shift = 23; 3586 } 3587 3588 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 3589 3590 /* 3591 * pseries-2.7 3592 */ 3593 #define SPAPR_COMPAT_2_7 \ 3594 HW_COMPAT_2_7 \ 3595 { \ 3596 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3597 .property = "mem_win_size", \ 3598 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 3599 }, \ 3600 { \ 3601 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3602 .property = "mem64_win_size", \ 3603 .value = "0", \ 3604 }, \ 3605 { \ 3606 .driver = TYPE_POWERPC_CPU, \ 3607 .property = "pre-2.8-migration", \ 3608 .value = "on", \ 3609 }, \ 3610 { \ 3611 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3612 .property = "pre-2.8-migration", \ 3613 .value = "on", \ 3614 }, 3615 3616 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 3617 uint64_t *buid, hwaddr *pio, 3618 hwaddr *mmio32, hwaddr *mmio64, 3619 unsigned n_dma, uint32_t *liobns, Error **errp) 3620 { 3621 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 3622 const uint64_t base_buid = 0x800000020000000ULL; 3623 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 3624 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 3625 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 3626 const uint32_t max_index = 255; 3627 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 3628 3629 uint64_t ram_top = MACHINE(spapr)->ram_size; 3630 hwaddr phb0_base, phb_base; 3631 int i; 3632 3633 /* Do we have hotpluggable memory? */ 3634 if (MACHINE(spapr)->maxram_size > ram_top) { 3635 /* Can't just use maxram_size, because there may be an 3636 * alignment gap between normal and hotpluggable memory 3637 * regions */ 3638 ram_top = spapr->hotplug_memory.base + 3639 memory_region_size(&spapr->hotplug_memory.mr); 3640 } 3641 3642 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 3643 3644 if (index > max_index) { 3645 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 3646 max_index); 3647 return; 3648 } 3649 3650 *buid = base_buid + index; 3651 for (i = 0; i < n_dma; ++i) { 3652 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3653 } 3654 3655 phb_base = phb0_base + index * phb_spacing; 3656 *pio = phb_base + pio_offset; 3657 *mmio32 = phb_base + mmio_offset; 3658 /* 3659 * We don't set the 64-bit MMIO window, relying on the PHB's 3660 * fallback behaviour of automatically splitting a large "32-bit" 3661 * window into contiguous 32-bit and 64-bit windows 3662 */ 3663 } 3664 3665 static void spapr_machine_2_7_instance_options(MachineState *machine) 3666 { 3667 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 3668 3669 spapr_machine_2_8_instance_options(machine); 3670 spapr->use_hotplug_event_source = false; 3671 } 3672 3673 static void spapr_machine_2_7_class_options(MachineClass *mc) 3674 { 3675 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3676 3677 spapr_machine_2_8_class_options(mc); 3678 smc->tcg_default_cpu = "POWER7"; 3679 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 3680 smc->phb_placement = phb_placement_2_7; 3681 } 3682 3683 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 3684 3685 /* 3686 * pseries-2.6 3687 */ 3688 #define SPAPR_COMPAT_2_6 \ 3689 HW_COMPAT_2_6 \ 3690 { \ 3691 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3692 .property = "ddw",\ 3693 .value = stringify(off),\ 3694 }, 3695 3696 static void spapr_machine_2_6_instance_options(MachineState *machine) 3697 { 3698 spapr_machine_2_7_instance_options(machine); 3699 } 3700 3701 static void spapr_machine_2_6_class_options(MachineClass *mc) 3702 { 3703 spapr_machine_2_7_class_options(mc); 3704 mc->has_hotpluggable_cpus = false; 3705 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 3706 } 3707 3708 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 3709 3710 /* 3711 * pseries-2.5 3712 */ 3713 #define SPAPR_COMPAT_2_5 \ 3714 HW_COMPAT_2_5 \ 3715 { \ 3716 .driver = "spapr-vlan", \ 3717 .property = "use-rx-buffer-pools", \ 3718 .value = "off", \ 3719 }, 3720 3721 static void spapr_machine_2_5_instance_options(MachineState *machine) 3722 { 3723 spapr_machine_2_6_instance_options(machine); 3724 } 3725 3726 static void spapr_machine_2_5_class_options(MachineClass *mc) 3727 { 3728 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3729 3730 spapr_machine_2_6_class_options(mc); 3731 smc->use_ohci_by_default = true; 3732 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 3733 } 3734 3735 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 3736 3737 /* 3738 * pseries-2.4 3739 */ 3740 #define SPAPR_COMPAT_2_4 \ 3741 HW_COMPAT_2_4 3742 3743 static void spapr_machine_2_4_instance_options(MachineState *machine) 3744 { 3745 spapr_machine_2_5_instance_options(machine); 3746 } 3747 3748 static void spapr_machine_2_4_class_options(MachineClass *mc) 3749 { 3750 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3751 3752 spapr_machine_2_5_class_options(mc); 3753 smc->dr_lmb_enabled = false; 3754 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 3755 } 3756 3757 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 3758 3759 /* 3760 * pseries-2.3 3761 */ 3762 #define SPAPR_COMPAT_2_3 \ 3763 HW_COMPAT_2_3 \ 3764 {\ 3765 .driver = "spapr-pci-host-bridge",\ 3766 .property = "dynamic-reconfiguration",\ 3767 .value = "off",\ 3768 }, 3769 3770 static void spapr_machine_2_3_instance_options(MachineState *machine) 3771 { 3772 spapr_machine_2_4_instance_options(machine); 3773 } 3774 3775 static void spapr_machine_2_3_class_options(MachineClass *mc) 3776 { 3777 spapr_machine_2_4_class_options(mc); 3778 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 3779 } 3780 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 3781 3782 /* 3783 * pseries-2.2 3784 */ 3785 3786 #define SPAPR_COMPAT_2_2 \ 3787 HW_COMPAT_2_2 \ 3788 {\ 3789 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3790 .property = "mem_win_size",\ 3791 .value = "0x20000000",\ 3792 }, 3793 3794 static void spapr_machine_2_2_instance_options(MachineState *machine) 3795 { 3796 spapr_machine_2_3_instance_options(machine); 3797 machine->suppress_vmdesc = true; 3798 } 3799 3800 static void spapr_machine_2_2_class_options(MachineClass *mc) 3801 { 3802 spapr_machine_2_3_class_options(mc); 3803 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 3804 } 3805 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 3806 3807 /* 3808 * pseries-2.1 3809 */ 3810 #define SPAPR_COMPAT_2_1 \ 3811 HW_COMPAT_2_1 3812 3813 static void spapr_machine_2_1_instance_options(MachineState *machine) 3814 { 3815 spapr_machine_2_2_instance_options(machine); 3816 } 3817 3818 static void spapr_machine_2_1_class_options(MachineClass *mc) 3819 { 3820 spapr_machine_2_2_class_options(mc); 3821 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 3822 } 3823 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 3824 3825 static void spapr_machine_register_types(void) 3826 { 3827 type_register_static(&spapr_machine_info); 3828 } 3829 3830 type_init(spapr_machine_register_types) 3831