1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "sysemu/sysemu.h" 28 #include "sysemu/numa.h" 29 #include "hw/hw.h" 30 #include "hw/fw-path-provider.h" 31 #include "elf.h" 32 #include "net/net.h" 33 #include "sysemu/device_tree.h" 34 #include "sysemu/block-backend.h" 35 #include "sysemu/cpus.h" 36 #include "sysemu/kvm.h" 37 #include "sysemu/device_tree.h" 38 #include "kvm_ppc.h" 39 #include "migration/migration.h" 40 #include "mmu-hash64.h" 41 #include "qom/cpu.h" 42 43 #include "hw/boards.h" 44 #include "hw/ppc/ppc.h" 45 #include "hw/loader.h" 46 47 #include "hw/ppc/spapr.h" 48 #include "hw/ppc/spapr_vio.h" 49 #include "hw/pci-host/spapr.h" 50 #include "hw/ppc/xics.h" 51 #include "hw/pci/msi.h" 52 53 #include "hw/pci/pci.h" 54 #include "hw/scsi/scsi.h" 55 #include "hw/virtio/virtio-scsi.h" 56 57 #include "exec/address-spaces.h" 58 #include "hw/usb.h" 59 #include "qemu/config-file.h" 60 #include "qemu/error-report.h" 61 #include "trace.h" 62 #include "hw/nmi.h" 63 64 #include "hw/compat.h" 65 #include "qemu-common.h" 66 67 #include <libfdt.h> 68 69 /* SLOF memory layout: 70 * 71 * SLOF raw image loaded at 0, copies its romfs right below the flat 72 * device-tree, then position SLOF itself 31M below that 73 * 74 * So we set FW_OVERHEAD to 40MB which should account for all of that 75 * and more 76 * 77 * We load our kernel at 4M, leaving space for SLOF initial image 78 */ 79 #define FDT_MAX_SIZE 0x100000 80 #define RTAS_MAX_SIZE 0x10000 81 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 82 #define FW_MAX_SIZE 0x400000 83 #define FW_FILE_NAME "slof.bin" 84 #define FW_OVERHEAD 0x2800000 85 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 86 87 #define MIN_RMA_SLOF 128UL 88 89 #define TIMEBASE_FREQ 512000000ULL 90 91 #define PHANDLE_XICP 0x00001111 92 93 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 94 95 static XICSState *try_create_xics(const char *type, int nr_servers, 96 int nr_irqs, Error **errp) 97 { 98 Error *err = NULL; 99 DeviceState *dev; 100 101 dev = qdev_create(NULL, type); 102 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 103 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 104 object_property_set_bool(OBJECT(dev), true, "realized", &err); 105 if (err) { 106 error_propagate(errp, err); 107 object_unparent(OBJECT(dev)); 108 return NULL; 109 } 110 return XICS_COMMON(dev); 111 } 112 113 static XICSState *xics_system_init(MachineState *machine, 114 int nr_servers, int nr_irqs) 115 { 116 XICSState *icp = NULL; 117 118 if (kvm_enabled()) { 119 Error *err = NULL; 120 121 if (machine_kernel_irqchip_allowed(machine)) { 122 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err); 123 } 124 if (machine_kernel_irqchip_required(machine) && !icp) { 125 error_report("kernel_irqchip requested but unavailable: %s", 126 error_get_pretty(err)); 127 } 128 error_free(err); 129 } 130 131 if (!icp) { 132 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, &error_abort); 133 } 134 135 return icp; 136 } 137 138 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 139 int smt_threads) 140 { 141 int i, ret = 0; 142 uint32_t servers_prop[smt_threads]; 143 uint32_t gservers_prop[smt_threads * 2]; 144 int index = ppc_get_vcpu_dt_id(cpu); 145 146 if (cpu->cpu_version) { 147 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); 148 if (ret < 0) { 149 return ret; 150 } 151 } 152 153 /* Build interrupt servers and gservers properties */ 154 for (i = 0; i < smt_threads; i++) { 155 servers_prop[i] = cpu_to_be32(index + i); 156 /* Hack, direct the group queues back to cpu 0 */ 157 gservers_prop[i*2] = cpu_to_be32(index + i); 158 gservers_prop[i*2 + 1] = 0; 159 } 160 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 161 servers_prop, sizeof(servers_prop)); 162 if (ret < 0) { 163 return ret; 164 } 165 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 166 gservers_prop, sizeof(gservers_prop)); 167 168 return ret; 169 } 170 171 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) 172 { 173 int ret = 0; 174 PowerPCCPU *cpu = POWERPC_CPU(cs); 175 int index = ppc_get_vcpu_dt_id(cpu); 176 uint32_t associativity[] = {cpu_to_be32(0x5), 177 cpu_to_be32(0x0), 178 cpu_to_be32(0x0), 179 cpu_to_be32(0x0), 180 cpu_to_be32(cs->numa_node), 181 cpu_to_be32(index)}; 182 183 /* Advertise NUMA via ibm,associativity */ 184 if (nb_numa_nodes > 1) { 185 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 186 sizeof(associativity)); 187 } 188 189 return ret; 190 } 191 192 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 193 { 194 int ret = 0, offset, cpus_offset; 195 CPUState *cs; 196 char cpu_model[32]; 197 int smt = kvmppc_smt_threads(); 198 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 199 200 CPU_FOREACH(cs) { 201 PowerPCCPU *cpu = POWERPC_CPU(cs); 202 DeviceClass *dc = DEVICE_GET_CLASS(cs); 203 int index = ppc_get_vcpu_dt_id(cpu); 204 205 if ((index % smt) != 0) { 206 continue; 207 } 208 209 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 210 211 cpus_offset = fdt_path_offset(fdt, "/cpus"); 212 if (cpus_offset < 0) { 213 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 214 "cpus"); 215 if (cpus_offset < 0) { 216 return cpus_offset; 217 } 218 } 219 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 220 if (offset < 0) { 221 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 222 if (offset < 0) { 223 return offset; 224 } 225 } 226 227 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 228 pft_size_prop, sizeof(pft_size_prop)); 229 if (ret < 0) { 230 return ret; 231 } 232 233 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); 234 if (ret < 0) { 235 return ret; 236 } 237 238 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 239 ppc_get_compat_smt_threads(cpu)); 240 if (ret < 0) { 241 return ret; 242 } 243 } 244 return ret; 245 } 246 247 248 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 249 size_t maxsize) 250 { 251 size_t maxcells = maxsize / sizeof(uint32_t); 252 int i, j, count; 253 uint32_t *p = prop; 254 255 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 256 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 257 258 if (!sps->page_shift) { 259 break; 260 } 261 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 262 if (sps->enc[count].page_shift == 0) { 263 break; 264 } 265 } 266 if ((p - prop) >= (maxcells - 3 - count * 2)) { 267 break; 268 } 269 *(p++) = cpu_to_be32(sps->page_shift); 270 *(p++) = cpu_to_be32(sps->slb_enc); 271 *(p++) = cpu_to_be32(count); 272 for (j = 0; j < count; j++) { 273 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 274 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 275 } 276 } 277 278 return (p - prop) * sizeof(uint32_t); 279 } 280 281 static hwaddr spapr_node0_size(void) 282 { 283 MachineState *machine = MACHINE(qdev_get_machine()); 284 285 if (nb_numa_nodes) { 286 int i; 287 for (i = 0; i < nb_numa_nodes; ++i) { 288 if (numa_info[i].node_mem) { 289 return MIN(pow2floor(numa_info[i].node_mem), 290 machine->ram_size); 291 } 292 } 293 } 294 return machine->ram_size; 295 } 296 297 #define _FDT(exp) \ 298 do { \ 299 int ret = (exp); \ 300 if (ret < 0) { \ 301 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 302 #exp, fdt_strerror(ret)); \ 303 exit(1); \ 304 } \ 305 } while (0) 306 307 static void add_str(GString *s, const gchar *s1) 308 { 309 g_string_append_len(s, s1, strlen(s1) + 1); 310 } 311 312 static void *spapr_create_fdt_skel(hwaddr initrd_base, 313 hwaddr initrd_size, 314 hwaddr kernel_size, 315 bool little_endian, 316 const char *kernel_cmdline, 317 uint32_t epow_irq) 318 { 319 void *fdt; 320 uint32_t start_prop = cpu_to_be32(initrd_base); 321 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 322 GString *hypertas = g_string_sized_new(256); 323 GString *qemu_hypertas = g_string_sized_new(256); 324 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 325 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)}; 326 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 327 char *buf; 328 329 add_str(hypertas, "hcall-pft"); 330 add_str(hypertas, "hcall-term"); 331 add_str(hypertas, "hcall-dabr"); 332 add_str(hypertas, "hcall-interrupt"); 333 add_str(hypertas, "hcall-tce"); 334 add_str(hypertas, "hcall-vio"); 335 add_str(hypertas, "hcall-splpar"); 336 add_str(hypertas, "hcall-bulk"); 337 add_str(hypertas, "hcall-set-mode"); 338 add_str(qemu_hypertas, "hcall-memop1"); 339 340 fdt = g_malloc0(FDT_MAX_SIZE); 341 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 342 343 if (kernel_size) { 344 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 345 } 346 if (initrd_size) { 347 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 348 } 349 _FDT((fdt_finish_reservemap(fdt))); 350 351 /* Root node */ 352 _FDT((fdt_begin_node(fdt, ""))); 353 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 354 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 355 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 356 357 /* 358 * Add info to guest to indentify which host is it being run on 359 * and what is the uuid of the guest 360 */ 361 if (kvmppc_get_host_model(&buf)) { 362 _FDT((fdt_property_string(fdt, "host-model", buf))); 363 g_free(buf); 364 } 365 if (kvmppc_get_host_serial(&buf)) { 366 _FDT((fdt_property_string(fdt, "host-serial", buf))); 367 g_free(buf); 368 } 369 370 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1], 371 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4], 372 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7], 373 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10], 374 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13], 375 qemu_uuid[14], qemu_uuid[15]); 376 377 _FDT((fdt_property_string(fdt, "vm,uuid", buf))); 378 if (qemu_uuid_set) { 379 _FDT((fdt_property_string(fdt, "system-id", buf))); 380 } 381 g_free(buf); 382 383 if (qemu_get_vm_name()) { 384 _FDT((fdt_property_string(fdt, "ibm,partition-name", 385 qemu_get_vm_name()))); 386 } 387 388 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 389 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 390 391 /* /chosen */ 392 _FDT((fdt_begin_node(fdt, "chosen"))); 393 394 /* Set Form1_affinity */ 395 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 396 397 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 398 _FDT((fdt_property(fdt, "linux,initrd-start", 399 &start_prop, sizeof(start_prop)))); 400 _FDT((fdt_property(fdt, "linux,initrd-end", 401 &end_prop, sizeof(end_prop)))); 402 if (kernel_size) { 403 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 404 cpu_to_be64(kernel_size) }; 405 406 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 407 if (little_endian) { 408 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 409 } 410 } 411 if (boot_menu) { 412 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); 413 } 414 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 415 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 416 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 417 418 _FDT((fdt_end_node(fdt))); 419 420 /* RTAS */ 421 _FDT((fdt_begin_node(fdt, "rtas"))); 422 423 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 424 add_str(hypertas, "hcall-multi-tce"); 425 } 426 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, 427 hypertas->len))); 428 g_string_free(hypertas, TRUE); 429 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, 430 qemu_hypertas->len))); 431 g_string_free(qemu_hypertas, TRUE); 432 433 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 434 refpoints, sizeof(refpoints)))); 435 436 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 437 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate", 438 RTAS_EVENT_SCAN_RATE))); 439 440 if (msi_supported) { 441 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0))); 442 } 443 444 /* 445 * According to PAPR, rtas ibm,os-term does not guarantee a return 446 * back to the guest cpu. 447 * 448 * While an additional ibm,extended-os-term property indicates that 449 * rtas call return will always occur. Set this property. 450 */ 451 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0))); 452 453 _FDT((fdt_end_node(fdt))); 454 455 /* interrupt controller */ 456 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 457 458 _FDT((fdt_property_string(fdt, "device_type", 459 "PowerPC-External-Interrupt-Presentation"))); 460 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 461 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 462 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 463 interrupt_server_ranges_prop, 464 sizeof(interrupt_server_ranges_prop)))); 465 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 466 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 467 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 468 469 _FDT((fdt_end_node(fdt))); 470 471 /* vdevice */ 472 _FDT((fdt_begin_node(fdt, "vdevice"))); 473 474 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 475 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 476 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 477 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 478 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 479 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 480 481 _FDT((fdt_end_node(fdt))); 482 483 /* event-sources */ 484 spapr_events_fdt_skel(fdt, epow_irq); 485 486 /* /hypervisor node */ 487 if (kvm_enabled()) { 488 uint8_t hypercall[16]; 489 490 /* indicate KVM hypercall interface */ 491 _FDT((fdt_begin_node(fdt, "hypervisor"))); 492 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); 493 if (kvmppc_has_cap_fixup_hcalls()) { 494 /* 495 * Older KVM versions with older guest kernels were broken with the 496 * magic page, don't allow the guest to map it. 497 */ 498 kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 499 sizeof(hypercall)); 500 _FDT((fdt_property(fdt, "hcall-instructions", hypercall, 501 sizeof(hypercall)))); 502 } 503 _FDT((fdt_end_node(fdt))); 504 } 505 506 _FDT((fdt_end_node(fdt))); /* close root node */ 507 _FDT((fdt_finish(fdt))); 508 509 return fdt; 510 } 511 512 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 513 hwaddr size) 514 { 515 uint32_t associativity[] = { 516 cpu_to_be32(0x4), /* length */ 517 cpu_to_be32(0x0), cpu_to_be32(0x0), 518 cpu_to_be32(0x0), cpu_to_be32(nodeid) 519 }; 520 char mem_name[32]; 521 uint64_t mem_reg_property[2]; 522 int off; 523 524 mem_reg_property[0] = cpu_to_be64(start); 525 mem_reg_property[1] = cpu_to_be64(size); 526 527 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 528 off = fdt_add_subnode(fdt, 0, mem_name); 529 _FDT(off); 530 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 531 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 532 sizeof(mem_reg_property)))); 533 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 534 sizeof(associativity)))); 535 return off; 536 } 537 538 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 539 { 540 MachineState *machine = MACHINE(spapr); 541 hwaddr mem_start, node_size; 542 int i, nb_nodes = nb_numa_nodes; 543 NodeInfo *nodes = numa_info; 544 NodeInfo ramnode; 545 546 /* No NUMA nodes, assume there is just one node with whole RAM */ 547 if (!nb_numa_nodes) { 548 nb_nodes = 1; 549 ramnode.node_mem = machine->ram_size; 550 nodes = &ramnode; 551 } 552 553 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 554 if (!nodes[i].node_mem) { 555 continue; 556 } 557 if (mem_start >= machine->ram_size) { 558 node_size = 0; 559 } else { 560 node_size = nodes[i].node_mem; 561 if (node_size > machine->ram_size - mem_start) { 562 node_size = machine->ram_size - mem_start; 563 } 564 } 565 if (!mem_start) { 566 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 567 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 568 mem_start += spapr->rma_size; 569 node_size -= spapr->rma_size; 570 } 571 for ( ; node_size; ) { 572 hwaddr sizetmp = pow2floor(node_size); 573 574 /* mem_start != 0 here */ 575 if (ctzl(mem_start) < ctzl(sizetmp)) { 576 sizetmp = 1ULL << ctzl(mem_start); 577 } 578 579 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 580 node_size -= sizetmp; 581 mem_start += sizetmp; 582 } 583 } 584 585 return 0; 586 } 587 588 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 589 sPAPRMachineState *spapr) 590 { 591 PowerPCCPU *cpu = POWERPC_CPU(cs); 592 CPUPPCState *env = &cpu->env; 593 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 594 int index = ppc_get_vcpu_dt_id(cpu); 595 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 596 0xffffffff, 0xffffffff}; 597 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 598 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 599 uint32_t page_sizes_prop[64]; 600 size_t page_sizes_prop_size; 601 uint32_t vcpus_per_socket = smp_threads * smp_cores; 602 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 603 604 /* Note: we keep CI large pages off for now because a 64K capable guest 605 * provisioned with large pages might otherwise try to map a qemu 606 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 607 * even if that qemu runs on a 4k host. 608 * 609 * We can later add this bit back when we are confident this is not 610 * an issue (!HV KVM or 64K host) 611 */ 612 uint8_t pa_features_206[] = { 6, 0, 613 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 614 uint8_t pa_features_207[] = { 24, 0, 615 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 616 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 617 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 618 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 619 uint8_t *pa_features; 620 size_t pa_size; 621 622 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 623 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 624 625 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 626 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 627 env->dcache_line_size))); 628 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 629 env->dcache_line_size))); 630 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 631 env->icache_line_size))); 632 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 633 env->icache_line_size))); 634 635 if (pcc->l1_dcache_size) { 636 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 637 pcc->l1_dcache_size))); 638 } else { 639 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 640 } 641 if (pcc->l1_icache_size) { 642 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 643 pcc->l1_icache_size))); 644 } else { 645 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 646 } 647 648 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 649 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 650 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 651 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 652 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 653 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 654 655 if (env->spr_cb[SPR_PURR].oea_read) { 656 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 657 } 658 659 if (env->mmu_model & POWERPC_MMU_1TSEG) { 660 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 661 segs, sizeof(segs)))); 662 } 663 664 /* Advertise VMX/VSX (vector extensions) if available 665 * 0 / no property == no vector extensions 666 * 1 == VMX / Altivec available 667 * 2 == VSX available */ 668 if (env->insns_flags & PPC_ALTIVEC) { 669 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 670 671 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 672 } 673 674 /* Advertise DFP (Decimal Floating Point) if available 675 * 0 / no property == no DFP 676 * 1 == DFP available */ 677 if (env->insns_flags2 & PPC2_DFP) { 678 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 679 } 680 681 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 682 sizeof(page_sizes_prop)); 683 if (page_sizes_prop_size) { 684 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 685 page_sizes_prop, page_sizes_prop_size))); 686 } 687 688 /* Do the ibm,pa-features property, adjust it for ci-large-pages */ 689 if (env->mmu_model == POWERPC_MMU_2_06) { 690 pa_features = pa_features_206; 691 pa_size = sizeof(pa_features_206); 692 } else /* env->mmu_model == POWERPC_MMU_2_07 */ { 693 pa_features = pa_features_207; 694 pa_size = sizeof(pa_features_207); 695 } 696 if (env->ci_large_pages) { 697 pa_features[3] |= 0x20; 698 } 699 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 700 701 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 702 cs->cpu_index / vcpus_per_socket))); 703 704 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 705 pft_size_prop, sizeof(pft_size_prop)))); 706 707 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); 708 709 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 710 ppc_get_compat_smt_threads(cpu))); 711 } 712 713 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 714 { 715 CPUState *cs; 716 int cpus_offset; 717 char *nodename; 718 int smt = kvmppc_smt_threads(); 719 720 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 721 _FDT(cpus_offset); 722 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 723 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 724 725 /* 726 * We walk the CPUs in reverse order to ensure that CPU DT nodes 727 * created by fdt_add_subnode() end up in the right order in FDT 728 * for the guest kernel the enumerate the CPUs correctly. 729 */ 730 CPU_FOREACH_REVERSE(cs) { 731 PowerPCCPU *cpu = POWERPC_CPU(cs); 732 int index = ppc_get_vcpu_dt_id(cpu); 733 DeviceClass *dc = DEVICE_GET_CLASS(cs); 734 int offset; 735 736 if ((index % smt) != 0) { 737 continue; 738 } 739 740 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 741 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 742 g_free(nodename); 743 _FDT(offset); 744 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 745 } 746 747 } 748 749 /* 750 * Adds ibm,dynamic-reconfiguration-memory node. 751 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 752 * of this device tree node. 753 */ 754 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 755 { 756 MachineState *machine = MACHINE(spapr); 757 int ret, i, offset; 758 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 759 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 760 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 761 uint32_t *int_buf, *cur_index, buf_len; 762 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 763 764 /* 765 * Allocate enough buffer size to fit in ibm,dynamic-memory 766 * or ibm,associativity-lookup-arrays 767 */ 768 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 769 * sizeof(uint32_t); 770 cur_index = int_buf = g_malloc0(buf_len); 771 772 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 773 774 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 775 sizeof(prop_lmb_size)); 776 if (ret < 0) { 777 goto out; 778 } 779 780 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 781 if (ret < 0) { 782 goto out; 783 } 784 785 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 786 if (ret < 0) { 787 goto out; 788 } 789 790 /* ibm,dynamic-memory */ 791 int_buf[0] = cpu_to_be32(nr_lmbs); 792 cur_index++; 793 for (i = 0; i < nr_lmbs; i++) { 794 sPAPRDRConnector *drc; 795 sPAPRDRConnectorClass *drck; 796 uint64_t addr = i * lmb_size + spapr->hotplug_memory.base;; 797 uint32_t *dynamic_memory = cur_index; 798 799 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 800 addr/lmb_size); 801 g_assert(drc); 802 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 803 804 dynamic_memory[0] = cpu_to_be32(addr >> 32); 805 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 806 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); 807 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 808 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 809 if (addr < machine->ram_size || 810 memory_region_present(get_system_memory(), addr)) { 811 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 812 } else { 813 dynamic_memory[5] = cpu_to_be32(0); 814 } 815 816 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 817 } 818 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 819 if (ret < 0) { 820 goto out; 821 } 822 823 /* ibm,associativity-lookup-arrays */ 824 cur_index = int_buf; 825 int_buf[0] = cpu_to_be32(nr_nodes); 826 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 827 cur_index += 2; 828 for (i = 0; i < nr_nodes; i++) { 829 uint32_t associativity[] = { 830 cpu_to_be32(0x0), 831 cpu_to_be32(0x0), 832 cpu_to_be32(0x0), 833 cpu_to_be32(i) 834 }; 835 memcpy(cur_index, associativity, sizeof(associativity)); 836 cur_index += 4; 837 } 838 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 839 (cur_index - int_buf) * sizeof(uint32_t)); 840 out: 841 g_free(int_buf); 842 return ret; 843 } 844 845 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 846 target_ulong addr, target_ulong size, 847 bool cpu_update, bool memory_update) 848 { 849 void *fdt, *fdt_skel; 850 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 851 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 852 853 size -= sizeof(hdr); 854 855 /* Create sceleton */ 856 fdt_skel = g_malloc0(size); 857 _FDT((fdt_create(fdt_skel, size))); 858 _FDT((fdt_begin_node(fdt_skel, ""))); 859 _FDT((fdt_end_node(fdt_skel))); 860 _FDT((fdt_finish(fdt_skel))); 861 fdt = g_malloc0(size); 862 _FDT((fdt_open_into(fdt_skel, fdt, size))); 863 g_free(fdt_skel); 864 865 /* Fixup cpu nodes */ 866 if (cpu_update) { 867 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 868 } 869 870 /* Generate memory nodes or ibm,dynamic-reconfiguration-memory node */ 871 if (memory_update && smc->dr_lmb_enabled) { 872 _FDT((spapr_populate_drconf_memory(spapr, fdt))); 873 } 874 875 /* Pack resulting tree */ 876 _FDT((fdt_pack(fdt))); 877 878 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 879 trace_spapr_cas_failed(size); 880 return -1; 881 } 882 883 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 884 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 885 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 886 g_free(fdt); 887 888 return 0; 889 } 890 891 static void spapr_finalize_fdt(sPAPRMachineState *spapr, 892 hwaddr fdt_addr, 893 hwaddr rtas_addr, 894 hwaddr rtas_size) 895 { 896 MachineState *machine = MACHINE(qdev_get_machine()); 897 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 898 const char *boot_device = machine->boot_order; 899 int ret, i; 900 size_t cb = 0; 901 char *bootlist; 902 void *fdt; 903 sPAPRPHBState *phb; 904 905 fdt = g_malloc(FDT_MAX_SIZE); 906 907 /* open out the base tree into a temp buffer for the final tweaks */ 908 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 909 910 ret = spapr_populate_memory(spapr, fdt); 911 if (ret < 0) { 912 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 913 exit(1); 914 } 915 916 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 917 if (ret < 0) { 918 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 919 exit(1); 920 } 921 922 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 923 ret = spapr_rng_populate_dt(fdt); 924 if (ret < 0) { 925 fprintf(stderr, "could not set up rng device in the fdt\n"); 926 exit(1); 927 } 928 } 929 930 QLIST_FOREACH(phb, &spapr->phbs, list) { 931 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 932 } 933 934 if (ret < 0) { 935 fprintf(stderr, "couldn't setup PCI devices in fdt\n"); 936 exit(1); 937 } 938 939 /* RTAS */ 940 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 941 if (ret < 0) { 942 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 943 } 944 945 /* cpus */ 946 spapr_populate_cpus_dt_node(fdt, spapr); 947 948 bootlist = get_boot_devices_list(&cb, true); 949 if (cb && bootlist) { 950 int offset = fdt_path_offset(fdt, "/chosen"); 951 if (offset < 0) { 952 exit(1); 953 } 954 for (i = 0; i < cb; i++) { 955 if (bootlist[i] == '\n') { 956 bootlist[i] = ' '; 957 } 958 959 } 960 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); 961 } 962 963 if (boot_device && strlen(boot_device)) { 964 int offset = fdt_path_offset(fdt, "/chosen"); 965 966 if (offset < 0) { 967 exit(1); 968 } 969 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device); 970 } 971 972 if (!spapr->has_graphics) { 973 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 974 } 975 976 if (smc->dr_lmb_enabled) { 977 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 978 } 979 980 _FDT((fdt_pack(fdt))); 981 982 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 983 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 984 fdt_totalsize(fdt), FDT_MAX_SIZE); 985 exit(1); 986 } 987 988 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 989 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 990 991 g_free(bootlist); 992 g_free(fdt); 993 } 994 995 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 996 { 997 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 998 } 999 1000 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 1001 { 1002 CPUPPCState *env = &cpu->env; 1003 1004 if (msr_pr) { 1005 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1006 env->gpr[3] = H_PRIVILEGE; 1007 } else { 1008 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1009 } 1010 } 1011 1012 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1013 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1014 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1015 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1016 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1017 1018 static void spapr_alloc_htab(sPAPRMachineState *spapr) 1019 { 1020 long shift; 1021 int index; 1022 1023 /* allocate hash page table. For now we always make this 16mb, 1024 * later we should probably make it scale to the size of guest 1025 * RAM */ 1026 1027 shift = kvmppc_reset_htab(spapr->htab_shift); 1028 if (shift < 0) { 1029 /* 1030 * For HV KVM, host kernel will return -ENOMEM when requested 1031 * HTAB size can't be allocated. 1032 */ 1033 error_setg(&error_abort, "Failed to allocate HTAB of requested size, try with smaller maxmem"); 1034 } else if (shift > 0) { 1035 /* 1036 * Kernel handles htab, we don't need to allocate one 1037 * 1038 * Older kernels can fall back to lower HTAB shift values, 1039 * but we don't allow booting of such guests. 1040 */ 1041 if (shift != spapr->htab_shift) { 1042 error_setg(&error_abort, "Failed to allocate HTAB of requested size, try with smaller maxmem"); 1043 } 1044 1045 spapr->htab_shift = shift; 1046 kvmppc_kern_htab = true; 1047 } else { 1048 /* Allocate htab */ 1049 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); 1050 1051 /* And clear it */ 1052 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 1053 1054 for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) { 1055 DIRTY_HPTE(HPTE(spapr->htab, index)); 1056 } 1057 } 1058 } 1059 1060 /* 1061 * Clear HTAB entries during reset. 1062 * 1063 * If host kernel has allocated HTAB, KVM_PPC_ALLOCATE_HTAB ioctl is 1064 * used to clear HTAB. Otherwise QEMU-allocated HTAB is cleared manually. 1065 */ 1066 static void spapr_reset_htab(sPAPRMachineState *spapr) 1067 { 1068 long shift; 1069 int index; 1070 1071 shift = kvmppc_reset_htab(spapr->htab_shift); 1072 if (shift < 0) { 1073 error_setg(&error_abort, "Failed to reset HTAB"); 1074 } else if (shift > 0) { 1075 if (shift != spapr->htab_shift) { 1076 error_setg(&error_abort, "Requested HTAB allocation failed during reset"); 1077 } 1078 1079 /* Tell readers to update their file descriptor */ 1080 if (spapr->htab_fd >= 0) { 1081 spapr->htab_fd_stale = true; 1082 } 1083 } else { 1084 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 1085 1086 for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) { 1087 DIRTY_HPTE(HPTE(spapr->htab, index)); 1088 } 1089 } 1090 1091 /* Update the RMA size if necessary */ 1092 if (spapr->vrma_adjust) { 1093 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1094 spapr->htab_shift); 1095 } 1096 } 1097 1098 static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1099 { 1100 bool matched = false; 1101 1102 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1103 matched = true; 1104 } 1105 1106 if (!matched) { 1107 error_report("Device %s is not supported by this machine yet.", 1108 qdev_fw_name(DEVICE(sbdev))); 1109 exit(1); 1110 } 1111 1112 return 0; 1113 } 1114 1115 /* 1116 * A guest reset will cause spapr->htab_fd to become stale if being used. 1117 * Reopen the file descriptor to make sure the whole HTAB is properly read. 1118 */ 1119 static int spapr_check_htab_fd(sPAPRMachineState *spapr) 1120 { 1121 int rc = 0; 1122 1123 if (spapr->htab_fd_stale) { 1124 close(spapr->htab_fd); 1125 spapr->htab_fd = kvmppc_get_htab_fd(false); 1126 if (spapr->htab_fd < 0) { 1127 error_report("Unable to open fd for reading hash table from KVM: " 1128 "%s", strerror(errno)); 1129 rc = -1; 1130 } 1131 spapr->htab_fd_stale = false; 1132 } 1133 1134 return rc; 1135 } 1136 1137 static void ppc_spapr_reset(void) 1138 { 1139 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1140 PowerPCCPU *first_ppc_cpu; 1141 uint32_t rtas_limit; 1142 1143 /* Check for unknown sysbus devices */ 1144 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1145 1146 /* Reset the hash table & recalc the RMA */ 1147 spapr_reset_htab(spapr); 1148 1149 qemu_devices_reset(); 1150 1151 /* 1152 * We place the device tree and RTAS just below either the top of the RMA, 1153 * or just below 2GB, whichever is lowere, so that it can be 1154 * processed with 32-bit real mode code if necessary 1155 */ 1156 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1157 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1158 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 1159 1160 /* Load the fdt */ 1161 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 1162 spapr->rtas_size); 1163 1164 /* Copy RTAS over */ 1165 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob, 1166 spapr->rtas_size); 1167 1168 /* Set up the entry state */ 1169 first_ppc_cpu = POWERPC_CPU(first_cpu); 1170 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 1171 first_ppc_cpu->env.gpr[5] = 0; 1172 first_cpu->halted = 0; 1173 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1174 1175 } 1176 1177 static void spapr_cpu_reset(void *opaque) 1178 { 1179 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1180 PowerPCCPU *cpu = opaque; 1181 CPUState *cs = CPU(cpu); 1182 CPUPPCState *env = &cpu->env; 1183 1184 cpu_reset(cs); 1185 1186 /* All CPUs start halted. CPU0 is unhalted from the machine level 1187 * reset code and the rest are explicitly started up by the guest 1188 * using an RTAS call */ 1189 cs->halted = 1; 1190 1191 env->spr[SPR_HIOR] = 0; 1192 1193 env->external_htab = (uint8_t *)spapr->htab; 1194 if (kvm_enabled() && !env->external_htab) { 1195 /* 1196 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte* 1197 * functions do the right thing. 1198 */ 1199 env->external_htab = (void *)1; 1200 } 1201 env->htab_base = -1; 1202 /* 1203 * htab_mask is the mask used to normalize hash value to PTEG index. 1204 * htab_shift is log2 of hash table size. 1205 * We have 8 hpte per group, and each hpte is 16 bytes. 1206 * ie have 128 bytes per hpte entry. 1207 */ 1208 env->htab_mask = (1ULL << (spapr->htab_shift - 7)) - 1; 1209 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | 1210 (spapr->htab_shift - 18); 1211 } 1212 1213 static void spapr_create_nvram(sPAPRMachineState *spapr) 1214 { 1215 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1216 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1217 1218 if (dinfo) { 1219 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1220 &error_fatal); 1221 } 1222 1223 qdev_init_nofail(dev); 1224 1225 spapr->nvram = (struct sPAPRNVRAM *)dev; 1226 } 1227 1228 static void spapr_rtc_create(sPAPRMachineState *spapr) 1229 { 1230 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); 1231 1232 qdev_init_nofail(dev); 1233 spapr->rtc = dev; 1234 1235 object_property_add_alias(qdev_get_machine(), "rtc-time", 1236 OBJECT(spapr->rtc), "date", NULL); 1237 } 1238 1239 /* Returns whether we want to use VGA or not */ 1240 static int spapr_vga_init(PCIBus *pci_bus) 1241 { 1242 switch (vga_interface_type) { 1243 case VGA_NONE: 1244 return false; 1245 case VGA_DEVICE: 1246 return true; 1247 case VGA_STD: 1248 case VGA_VIRTIO: 1249 return pci_vga_init(pci_bus) != NULL; 1250 default: 1251 fprintf(stderr, "This vga model is not supported," 1252 "currently it only supports -vga std\n"); 1253 exit(0); 1254 } 1255 } 1256 1257 static int spapr_post_load(void *opaque, int version_id) 1258 { 1259 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1260 int err = 0; 1261 1262 /* In earlier versions, there was no separate qdev for the PAPR 1263 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1264 * So when migrating from those versions, poke the incoming offset 1265 * value into the RTC device */ 1266 if (version_id < 3) { 1267 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); 1268 } 1269 1270 return err; 1271 } 1272 1273 static bool version_before_3(void *opaque, int version_id) 1274 { 1275 return version_id < 3; 1276 } 1277 1278 static const VMStateDescription vmstate_spapr = { 1279 .name = "spapr", 1280 .version_id = 3, 1281 .minimum_version_id = 1, 1282 .post_load = spapr_post_load, 1283 .fields = (VMStateField[]) { 1284 /* used to be @next_irq */ 1285 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1286 1287 /* RTC offset */ 1288 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1289 1290 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1291 VMSTATE_END_OF_LIST() 1292 }, 1293 }; 1294 1295 static int htab_save_setup(QEMUFile *f, void *opaque) 1296 { 1297 sPAPRMachineState *spapr = opaque; 1298 1299 /* "Iteration" header */ 1300 qemu_put_be32(f, spapr->htab_shift); 1301 1302 if (spapr->htab) { 1303 spapr->htab_save_index = 0; 1304 spapr->htab_first_pass = true; 1305 } else { 1306 assert(kvm_enabled()); 1307 1308 spapr->htab_fd = kvmppc_get_htab_fd(false); 1309 spapr->htab_fd_stale = false; 1310 if (spapr->htab_fd < 0) { 1311 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", 1312 strerror(errno)); 1313 return -1; 1314 } 1315 } 1316 1317 1318 return 0; 1319 } 1320 1321 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1322 int64_t max_ns) 1323 { 1324 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1325 int index = spapr->htab_save_index; 1326 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1327 1328 assert(spapr->htab_first_pass); 1329 1330 do { 1331 int chunkstart; 1332 1333 /* Consume invalid HPTEs */ 1334 while ((index < htabslots) 1335 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1336 index++; 1337 CLEAN_HPTE(HPTE(spapr->htab, index)); 1338 } 1339 1340 /* Consume valid HPTEs */ 1341 chunkstart = index; 1342 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1343 && HPTE_VALID(HPTE(spapr->htab, index))) { 1344 index++; 1345 CLEAN_HPTE(HPTE(spapr->htab, index)); 1346 } 1347 1348 if (index > chunkstart) { 1349 int n_valid = index - chunkstart; 1350 1351 qemu_put_be32(f, chunkstart); 1352 qemu_put_be16(f, n_valid); 1353 qemu_put_be16(f, 0); 1354 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1355 HASH_PTE_SIZE_64 * n_valid); 1356 1357 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1358 break; 1359 } 1360 } 1361 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1362 1363 if (index >= htabslots) { 1364 assert(index == htabslots); 1365 index = 0; 1366 spapr->htab_first_pass = false; 1367 } 1368 spapr->htab_save_index = index; 1369 } 1370 1371 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1372 int64_t max_ns) 1373 { 1374 bool final = max_ns < 0; 1375 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1376 int examined = 0, sent = 0; 1377 int index = spapr->htab_save_index; 1378 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1379 1380 assert(!spapr->htab_first_pass); 1381 1382 do { 1383 int chunkstart, invalidstart; 1384 1385 /* Consume non-dirty HPTEs */ 1386 while ((index < htabslots) 1387 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1388 index++; 1389 examined++; 1390 } 1391 1392 chunkstart = index; 1393 /* Consume valid dirty HPTEs */ 1394 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1395 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1396 && HPTE_VALID(HPTE(spapr->htab, index))) { 1397 CLEAN_HPTE(HPTE(spapr->htab, index)); 1398 index++; 1399 examined++; 1400 } 1401 1402 invalidstart = index; 1403 /* Consume invalid dirty HPTEs */ 1404 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1405 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1406 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1407 CLEAN_HPTE(HPTE(spapr->htab, index)); 1408 index++; 1409 examined++; 1410 } 1411 1412 if (index > chunkstart) { 1413 int n_valid = invalidstart - chunkstart; 1414 int n_invalid = index - invalidstart; 1415 1416 qemu_put_be32(f, chunkstart); 1417 qemu_put_be16(f, n_valid); 1418 qemu_put_be16(f, n_invalid); 1419 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1420 HASH_PTE_SIZE_64 * n_valid); 1421 sent += index - chunkstart; 1422 1423 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1424 break; 1425 } 1426 } 1427 1428 if (examined >= htabslots) { 1429 break; 1430 } 1431 1432 if (index >= htabslots) { 1433 assert(index == htabslots); 1434 index = 0; 1435 } 1436 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1437 1438 if (index >= htabslots) { 1439 assert(index == htabslots); 1440 index = 0; 1441 } 1442 1443 spapr->htab_save_index = index; 1444 1445 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1446 } 1447 1448 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1449 #define MAX_KVM_BUF_SIZE 2048 1450 1451 static int htab_save_iterate(QEMUFile *f, void *opaque) 1452 { 1453 sPAPRMachineState *spapr = opaque; 1454 int rc = 0; 1455 1456 /* Iteration header */ 1457 qemu_put_be32(f, 0); 1458 1459 if (!spapr->htab) { 1460 assert(kvm_enabled()); 1461 1462 rc = spapr_check_htab_fd(spapr); 1463 if (rc < 0) { 1464 return rc; 1465 } 1466 1467 rc = kvmppc_save_htab(f, spapr->htab_fd, 1468 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1469 if (rc < 0) { 1470 return rc; 1471 } 1472 } else if (spapr->htab_first_pass) { 1473 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1474 } else { 1475 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1476 } 1477 1478 /* End marker */ 1479 qemu_put_be32(f, 0); 1480 qemu_put_be16(f, 0); 1481 qemu_put_be16(f, 0); 1482 1483 return rc; 1484 } 1485 1486 static int htab_save_complete(QEMUFile *f, void *opaque) 1487 { 1488 sPAPRMachineState *spapr = opaque; 1489 1490 /* Iteration header */ 1491 qemu_put_be32(f, 0); 1492 1493 if (!spapr->htab) { 1494 int rc; 1495 1496 assert(kvm_enabled()); 1497 1498 rc = spapr_check_htab_fd(spapr); 1499 if (rc < 0) { 1500 return rc; 1501 } 1502 1503 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); 1504 if (rc < 0) { 1505 return rc; 1506 } 1507 close(spapr->htab_fd); 1508 spapr->htab_fd = -1; 1509 } else { 1510 htab_save_later_pass(f, spapr, -1); 1511 } 1512 1513 /* End marker */ 1514 qemu_put_be32(f, 0); 1515 qemu_put_be16(f, 0); 1516 qemu_put_be16(f, 0); 1517 1518 return 0; 1519 } 1520 1521 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1522 { 1523 sPAPRMachineState *spapr = opaque; 1524 uint32_t section_hdr; 1525 int fd = -1; 1526 1527 if (version_id < 1 || version_id > 1) { 1528 fprintf(stderr, "htab_load() bad version\n"); 1529 return -EINVAL; 1530 } 1531 1532 section_hdr = qemu_get_be32(f); 1533 1534 if (section_hdr) { 1535 /* First section, just the hash shift */ 1536 if (spapr->htab_shift != section_hdr) { 1537 error_report("htab_shift mismatch: source %d target %d", 1538 section_hdr, spapr->htab_shift); 1539 return -EINVAL; 1540 } 1541 return 0; 1542 } 1543 1544 if (!spapr->htab) { 1545 assert(kvm_enabled()); 1546 1547 fd = kvmppc_get_htab_fd(true); 1548 if (fd < 0) { 1549 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", 1550 strerror(errno)); 1551 } 1552 } 1553 1554 while (true) { 1555 uint32_t index; 1556 uint16_t n_valid, n_invalid; 1557 1558 index = qemu_get_be32(f); 1559 n_valid = qemu_get_be16(f); 1560 n_invalid = qemu_get_be16(f); 1561 1562 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1563 /* End of Stream */ 1564 break; 1565 } 1566 1567 if ((index + n_valid + n_invalid) > 1568 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1569 /* Bad index in stream */ 1570 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " 1571 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, 1572 spapr->htab_shift); 1573 return -EINVAL; 1574 } 1575 1576 if (spapr->htab) { 1577 if (n_valid) { 1578 qemu_get_buffer(f, HPTE(spapr->htab, index), 1579 HASH_PTE_SIZE_64 * n_valid); 1580 } 1581 if (n_invalid) { 1582 memset(HPTE(spapr->htab, index + n_valid), 0, 1583 HASH_PTE_SIZE_64 * n_invalid); 1584 } 1585 } else { 1586 int rc; 1587 1588 assert(fd >= 0); 1589 1590 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1591 if (rc < 0) { 1592 return rc; 1593 } 1594 } 1595 } 1596 1597 if (!spapr->htab) { 1598 assert(fd >= 0); 1599 close(fd); 1600 } 1601 1602 return 0; 1603 } 1604 1605 static SaveVMHandlers savevm_htab_handlers = { 1606 .save_live_setup = htab_save_setup, 1607 .save_live_iterate = htab_save_iterate, 1608 .save_live_complete_precopy = htab_save_complete, 1609 .load_state = htab_load, 1610 }; 1611 1612 static void spapr_boot_set(void *opaque, const char *boot_device, 1613 Error **errp) 1614 { 1615 MachineState *machine = MACHINE(qdev_get_machine()); 1616 machine->boot_order = g_strdup(boot_device); 1617 } 1618 1619 static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu) 1620 { 1621 CPUPPCState *env = &cpu->env; 1622 1623 /* Set time-base frequency to 512 MHz */ 1624 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 1625 1626 /* PAPR always has exception vectors in RAM not ROM. To ensure this, 1627 * MSR[IP] should never be set. 1628 */ 1629 env->msr_mask &= ~(1 << 6); 1630 1631 /* Tell KVM that we're in PAPR mode */ 1632 if (kvm_enabled()) { 1633 kvmppc_set_papr(cpu); 1634 } 1635 1636 if (cpu->max_compat) { 1637 if (ppc_set_compat(cpu, cpu->max_compat) < 0) { 1638 exit(1); 1639 } 1640 } 1641 1642 xics_cpu_setup(spapr->icp, cpu); 1643 1644 qemu_register_reset(spapr_cpu_reset, cpu); 1645 } 1646 1647 /* 1648 * Reset routine for LMB DR devices. 1649 * 1650 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1651 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1652 * when it walks all its children devices. LMB devices reset occurs 1653 * as part of spapr_ppc_reset(). 1654 */ 1655 static void spapr_drc_reset(void *opaque) 1656 { 1657 sPAPRDRConnector *drc = opaque; 1658 DeviceState *d = DEVICE(drc); 1659 1660 if (d) { 1661 device_reset(d); 1662 } 1663 } 1664 1665 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1666 { 1667 MachineState *machine = MACHINE(spapr); 1668 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1669 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1670 int i; 1671 1672 for (i = 0; i < nr_lmbs; i++) { 1673 sPAPRDRConnector *drc; 1674 uint64_t addr; 1675 1676 addr = i * lmb_size + spapr->hotplug_memory.base; 1677 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, 1678 addr/lmb_size); 1679 qemu_register_reset(spapr_drc_reset, drc); 1680 } 1681 } 1682 1683 /* 1684 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1685 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1686 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1687 */ 1688 static void spapr_validate_node_memory(MachineState *machine) 1689 { 1690 int i; 1691 1692 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE || 1693 machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1694 error_report("Can't support memory configuration where RAM size " 1695 "0x" RAM_ADDR_FMT " or maxmem size " 1696 "0x" RAM_ADDR_FMT " isn't aligned to %llu MB", 1697 machine->ram_size, machine->maxram_size, 1698 SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 1699 exit(EXIT_FAILURE); 1700 } 1701 1702 for (i = 0; i < nb_numa_nodes; i++) { 1703 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 1704 error_report("Can't support memory configuration where memory size" 1705 " %" PRIx64 " of node %d isn't aligned to %llu MB", 1706 numa_info[i].node_mem, i, 1707 SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 1708 exit(EXIT_FAILURE); 1709 } 1710 } 1711 } 1712 1713 /* pSeries LPAR / sPAPR hardware init */ 1714 static void ppc_spapr_init(MachineState *machine) 1715 { 1716 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1717 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1718 const char *kernel_filename = machine->kernel_filename; 1719 const char *kernel_cmdline = machine->kernel_cmdline; 1720 const char *initrd_filename = machine->initrd_filename; 1721 PowerPCCPU *cpu; 1722 PCIHostState *phb; 1723 int i; 1724 MemoryRegion *sysmem = get_system_memory(); 1725 MemoryRegion *ram = g_new(MemoryRegion, 1); 1726 MemoryRegion *rma_region; 1727 void *rma = NULL; 1728 hwaddr rma_alloc_size; 1729 hwaddr node0_size = spapr_node0_size(); 1730 uint32_t initrd_base = 0; 1731 long kernel_size = 0, initrd_size = 0; 1732 long load_limit, fw_size; 1733 bool kernel_le = false; 1734 char *filename; 1735 1736 msi_supported = true; 1737 1738 QLIST_INIT(&spapr->phbs); 1739 1740 cpu_ppc_hypercall = emulate_spapr_hypercall; 1741 1742 /* Allocate RMA if necessary */ 1743 rma_alloc_size = kvmppc_alloc_rma(&rma); 1744 1745 if (rma_alloc_size == -1) { 1746 error_report("Unable to create RMA"); 1747 exit(1); 1748 } 1749 1750 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1751 spapr->rma_size = rma_alloc_size; 1752 } else { 1753 spapr->rma_size = node0_size; 1754 1755 /* With KVM, we don't actually know whether KVM supports an 1756 * unbounded RMA (PR KVM) or is limited by the hash table size 1757 * (HV KVM using VRMA), so we always assume the latter 1758 * 1759 * In that case, we also limit the initial allocations for RTAS 1760 * etc... to 256M since we have no way to know what the VRMA size 1761 * is going to be as it depends on the size of the hash table 1762 * isn't determined yet. 1763 */ 1764 if (kvm_enabled()) { 1765 spapr->vrma_adjust = 1; 1766 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1767 } 1768 } 1769 1770 if (spapr->rma_size > node0_size) { 1771 fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n", 1772 spapr->rma_size); 1773 exit(1); 1774 } 1775 1776 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 1777 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 1778 1779 /* We aim for a hash table of size 1/128 the size of RAM. The 1780 * normal rule of thumb is 1/64 the size of RAM, but that's much 1781 * more than needed for the Linux guests we support. */ 1782 spapr->htab_shift = 18; /* Minimum architected size */ 1783 while (spapr->htab_shift <= 46) { 1784 if ((1ULL << (spapr->htab_shift + 7)) >= machine->maxram_size) { 1785 break; 1786 } 1787 spapr->htab_shift++; 1788 } 1789 spapr_alloc_htab(spapr); 1790 1791 /* Set up Interrupt Controller before we create the VCPUs */ 1792 spapr->icp = xics_system_init(machine, 1793 DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), 1794 smp_threads), 1795 XICS_IRQS); 1796 1797 if (smc->dr_lmb_enabled) { 1798 spapr_validate_node_memory(machine); 1799 } 1800 1801 /* init CPUs */ 1802 if (machine->cpu_model == NULL) { 1803 machine->cpu_model = kvm_enabled() ? "host" : "POWER7"; 1804 } 1805 for (i = 0; i < smp_cpus; i++) { 1806 cpu = cpu_ppc_init(machine->cpu_model); 1807 if (cpu == NULL) { 1808 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 1809 exit(1); 1810 } 1811 spapr_cpu_init(spapr, cpu); 1812 } 1813 1814 if (kvm_enabled()) { 1815 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 1816 kvmppc_enable_logical_ci_hcalls(); 1817 kvmppc_enable_set_mode_hcall(); 1818 } 1819 1820 /* allocate RAM */ 1821 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 1822 machine->ram_size); 1823 memory_region_add_subregion(sysmem, 0, ram); 1824 1825 if (rma_alloc_size && rma) { 1826 rma_region = g_new(MemoryRegion, 1); 1827 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 1828 rma_alloc_size, rma); 1829 vmstate_register_ram_global(rma_region); 1830 memory_region_add_subregion(sysmem, 0, rma_region); 1831 } 1832 1833 /* initialize hotplug memory address space */ 1834 if (machine->ram_size < machine->maxram_size) { 1835 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 1836 1837 if (machine->ram_slots > SPAPR_MAX_RAM_SLOTS) { 1838 error_report("Specified number of memory slots %"PRIu64" exceeds max supported %d\n", 1839 machine->ram_slots, SPAPR_MAX_RAM_SLOTS); 1840 exit(EXIT_FAILURE); 1841 } 1842 1843 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 1844 SPAPR_HOTPLUG_MEM_ALIGN); 1845 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 1846 "hotplug-memory", hotplug_mem_size); 1847 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 1848 &spapr->hotplug_memory.mr); 1849 } 1850 1851 if (smc->dr_lmb_enabled) { 1852 spapr_create_lmb_dr_connectors(spapr); 1853 } 1854 1855 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1856 if (!filename) { 1857 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 1858 exit(1); 1859 } 1860 spapr->rtas_size = get_image_size(filename); 1861 spapr->rtas_blob = g_malloc(spapr->rtas_size); 1862 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 1863 error_report("Could not load LPAR rtas '%s'", filename); 1864 exit(1); 1865 } 1866 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1867 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 1868 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 1869 exit(1); 1870 } 1871 g_free(filename); 1872 1873 /* Set up EPOW events infrastructure */ 1874 spapr_events_init(spapr); 1875 1876 /* Set up the RTC RTAS interfaces */ 1877 spapr_rtc_create(spapr); 1878 1879 /* Set up VIO bus */ 1880 spapr->vio_bus = spapr_vio_bus_init(); 1881 1882 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1883 if (serial_hds[i]) { 1884 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1885 } 1886 } 1887 1888 /* We always have at least the nvram device on VIO */ 1889 spapr_create_nvram(spapr); 1890 1891 /* Set up PCI */ 1892 spapr_pci_rtas_init(); 1893 1894 phb = spapr_create_phb(spapr, 0); 1895 1896 for (i = 0; i < nb_nics; i++) { 1897 NICInfo *nd = &nd_table[i]; 1898 1899 if (!nd->model) { 1900 nd->model = g_strdup("ibmveth"); 1901 } 1902 1903 if (strcmp(nd->model, "ibmveth") == 0) { 1904 spapr_vlan_create(spapr->vio_bus, nd); 1905 } else { 1906 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1907 } 1908 } 1909 1910 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1911 spapr_vscsi_create(spapr->vio_bus); 1912 } 1913 1914 /* Graphics */ 1915 if (spapr_vga_init(phb->bus)) { 1916 spapr->has_graphics = true; 1917 machine->usb |= defaults_enabled() && !machine->usb_disabled; 1918 } 1919 1920 if (machine->usb) { 1921 if (smc->use_ohci_by_default) { 1922 pci_create_simple(phb->bus, -1, "pci-ohci"); 1923 } else { 1924 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 1925 } 1926 1927 if (spapr->has_graphics) { 1928 USBBus *usb_bus = usb_bus_find(-1); 1929 1930 usb_create_simple(usb_bus, "usb-kbd"); 1931 usb_create_simple(usb_bus, "usb-mouse"); 1932 } 1933 } 1934 1935 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1936 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " 1937 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); 1938 exit(1); 1939 } 1940 1941 if (kernel_filename) { 1942 uint64_t lowaddr = 0; 1943 1944 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1945 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 0); 1946 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { 1947 kernel_size = load_elf(kernel_filename, 1948 translate_kernel_address, NULL, 1949 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE, 0); 1950 kernel_le = kernel_size > 0; 1951 } 1952 if (kernel_size < 0) { 1953 fprintf(stderr, "qemu: error loading %s: %s\n", 1954 kernel_filename, load_elf_strerror(kernel_size)); 1955 exit(1); 1956 } 1957 1958 /* load initrd */ 1959 if (initrd_filename) { 1960 /* Try to locate the initrd in the gap between the kernel 1961 * and the firmware. Add a bit of space just in case 1962 */ 1963 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1964 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1965 load_limit - initrd_base); 1966 if (initrd_size < 0) { 1967 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 1968 initrd_filename); 1969 exit(1); 1970 } 1971 } else { 1972 initrd_base = 0; 1973 initrd_size = 0; 1974 } 1975 } 1976 1977 if (bios_name == NULL) { 1978 bios_name = FW_FILE_NAME; 1979 } 1980 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1981 if (!filename) { 1982 error_report("Could not find LPAR firmware '%s'", bios_name); 1983 exit(1); 1984 } 1985 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 1986 if (fw_size <= 0) { 1987 error_report("Could not load LPAR firmware '%s'", filename); 1988 exit(1); 1989 } 1990 g_free(filename); 1991 1992 /* FIXME: Should register things through the MachineState's qdev 1993 * interface, this is a legacy from the sPAPREnvironment structure 1994 * which predated MachineState but had a similar function */ 1995 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 1996 register_savevm_live(NULL, "spapr/htab", -1, 1, 1997 &savevm_htab_handlers, spapr); 1998 1999 /* Prepare the device tree */ 2000 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 2001 kernel_size, kernel_le, 2002 kernel_cmdline, 2003 spapr->check_exception_irq); 2004 assert(spapr->fdt_skel != NULL); 2005 2006 /* used by RTAS */ 2007 QTAILQ_INIT(&spapr->ccs_list); 2008 qemu_register_reset(spapr_ccs_reset_hook, spapr); 2009 2010 qemu_register_boot_set(spapr_boot_set, spapr); 2011 } 2012 2013 static int spapr_kvm_type(const char *vm_type) 2014 { 2015 if (!vm_type) { 2016 return 0; 2017 } 2018 2019 if (!strcmp(vm_type, "HV")) { 2020 return 1; 2021 } 2022 2023 if (!strcmp(vm_type, "PR")) { 2024 return 2; 2025 } 2026 2027 error_report("Unknown kvm-type specified '%s'", vm_type); 2028 exit(1); 2029 } 2030 2031 /* 2032 * Implementation of an interface to adjust firmware path 2033 * for the bootindex property handling. 2034 */ 2035 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2036 DeviceState *dev) 2037 { 2038 #define CAST(type, obj, name) \ 2039 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2040 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2041 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2042 2043 if (d) { 2044 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2045 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2046 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2047 2048 if (spapr) { 2049 /* 2050 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2051 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2052 * in the top 16 bits of the 64-bit LUN 2053 */ 2054 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2055 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2056 (uint64_t)id << 48); 2057 } else if (virtio) { 2058 /* 2059 * We use SRP luns of the form 01000000 | (target << 8) | lun 2060 * in the top 32 bits of the 64-bit LUN 2061 * Note: the quote above is from SLOF and it is wrong, 2062 * the actual binding is: 2063 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2064 */ 2065 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2066 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2067 (uint64_t)id << 32); 2068 } else if (usb) { 2069 /* 2070 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2071 * in the top 32 bits of the 64-bit LUN 2072 */ 2073 unsigned usb_port = atoi(usb->port->path); 2074 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2075 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2076 (uint64_t)id << 32); 2077 } 2078 } 2079 2080 if (phb) { 2081 /* Replace "pci" with "pci@800000020000000" */ 2082 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2083 } 2084 2085 return NULL; 2086 } 2087 2088 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2089 { 2090 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2091 2092 return g_strdup(spapr->kvm_type); 2093 } 2094 2095 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2096 { 2097 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2098 2099 g_free(spapr->kvm_type); 2100 spapr->kvm_type = g_strdup(value); 2101 } 2102 2103 static void spapr_machine_initfn(Object *obj) 2104 { 2105 object_property_add_str(obj, "kvm-type", 2106 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2107 object_property_set_description(obj, "kvm-type", 2108 "Specifies the KVM virtualization mode (HV, PR)", 2109 NULL); 2110 } 2111 2112 static void spapr_machine_finalizefn(Object *obj) 2113 { 2114 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2115 2116 g_free(spapr->kvm_type); 2117 } 2118 2119 static void ppc_cpu_do_nmi_on_cpu(void *arg) 2120 { 2121 CPUState *cs = arg; 2122 2123 cpu_synchronize_state(cs); 2124 ppc_cpu_do_system_reset(cs); 2125 } 2126 2127 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2128 { 2129 CPUState *cs; 2130 2131 CPU_FOREACH(cs) { 2132 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs); 2133 } 2134 } 2135 2136 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size, 2137 uint32_t node, Error **errp) 2138 { 2139 sPAPRDRConnector *drc; 2140 sPAPRDRConnectorClass *drck; 2141 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2142 int i, fdt_offset, fdt_size; 2143 void *fdt; 2144 2145 /* 2146 * Check for DRC connectors and send hotplug notification to the 2147 * guest only in case of hotplugged memory. This allows cold plugged 2148 * memory to be specified at boot time. 2149 */ 2150 if (!dev->hotplugged) { 2151 return; 2152 } 2153 2154 for (i = 0; i < nr_lmbs; i++) { 2155 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2156 addr/SPAPR_MEMORY_BLOCK_SIZE); 2157 g_assert(drc); 2158 2159 fdt = create_device_tree(&fdt_size); 2160 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2161 SPAPR_MEMORY_BLOCK_SIZE); 2162 2163 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2164 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2165 addr += SPAPR_MEMORY_BLOCK_SIZE; 2166 } 2167 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs); 2168 } 2169 2170 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2171 uint32_t node, Error **errp) 2172 { 2173 Error *local_err = NULL; 2174 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2175 PCDIMMDevice *dimm = PC_DIMM(dev); 2176 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2177 MemoryRegion *mr = ddc->get_memory_region(dimm); 2178 uint64_t align = memory_region_get_alignment(mr); 2179 uint64_t size = memory_region_size(mr); 2180 uint64_t addr; 2181 2182 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2183 error_setg(&local_err, "Hotplugged memory size must be a multiple of " 2184 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 2185 goto out; 2186 } 2187 2188 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2189 if (local_err) { 2190 goto out; 2191 } 2192 2193 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2194 if (local_err) { 2195 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2196 goto out; 2197 } 2198 2199 spapr_add_lmbs(dev, addr, size, node, &error_abort); 2200 2201 out: 2202 error_propagate(errp, local_err); 2203 } 2204 2205 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 2206 DeviceState *dev, Error **errp) 2207 { 2208 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2209 2210 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2211 int node; 2212 2213 if (!smc->dr_lmb_enabled) { 2214 error_setg(errp, "Memory hotplug not supported for this machine"); 2215 return; 2216 } 2217 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 2218 if (*errp) { 2219 return; 2220 } 2221 2222 /* 2223 * Currently PowerPC kernel doesn't allow hot-adding memory to 2224 * memory-less node, but instead will silently add the memory 2225 * to the first node that has some memory. This causes two 2226 * unexpected behaviours for the user. 2227 * 2228 * - Memory gets hotplugged to a different node than what the user 2229 * specified. 2230 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 2231 * to memory-less node, a reboot will set things accordingly 2232 * and the previously hotplugged memory now ends in the right node. 2233 * This appears as if some memory moved from one node to another. 2234 * 2235 * So until kernel starts supporting memory hotplug to memory-less 2236 * nodes, just prevent such attempts upfront in QEMU. 2237 */ 2238 if (nb_numa_nodes && !numa_info[node].node_mem) { 2239 error_setg(errp, "Can't hotplug memory to memory-less node %d", 2240 node); 2241 return; 2242 } 2243 2244 spapr_memory_plug(hotplug_dev, dev, node, errp); 2245 } 2246 } 2247 2248 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 2249 DeviceState *dev, Error **errp) 2250 { 2251 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2252 error_setg(errp, "Memory hot unplug not supported by sPAPR"); 2253 } 2254 } 2255 2256 static HotplugHandler *spapr_get_hotpug_handler(MachineState *machine, 2257 DeviceState *dev) 2258 { 2259 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2260 return HOTPLUG_HANDLER(machine); 2261 } 2262 return NULL; 2263 } 2264 2265 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index) 2266 { 2267 /* Allocate to NUMA nodes on a "socket" basis (not that concept of 2268 * socket means much for the paravirtualized PAPR platform) */ 2269 return cpu_index / smp_threads / smp_cores; 2270 } 2271 2272 static void spapr_machine_class_init(ObjectClass *oc, void *data) 2273 { 2274 MachineClass *mc = MACHINE_CLASS(oc); 2275 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 2276 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 2277 NMIClass *nc = NMI_CLASS(oc); 2278 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2279 2280 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 2281 2282 /* 2283 * We set up the default / latest behaviour here. The class_init 2284 * functions for the specific versioned machine types can override 2285 * these details for backwards compatibility 2286 */ 2287 mc->init = ppc_spapr_init; 2288 mc->reset = ppc_spapr_reset; 2289 mc->block_default_type = IF_SCSI; 2290 mc->max_cpus = MAX_CPUMASK_BITS; 2291 mc->no_parallel = 1; 2292 mc->default_boot_order = ""; 2293 mc->default_ram_size = 512 * M_BYTE; 2294 mc->kvm_type = spapr_kvm_type; 2295 mc->has_dynamic_sysbus = true; 2296 mc->pci_allow_0_address = true; 2297 mc->get_hotplug_handler = spapr_get_hotpug_handler; 2298 hc->plug = spapr_machine_device_plug; 2299 hc->unplug = spapr_machine_device_unplug; 2300 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; 2301 2302 smc->dr_lmb_enabled = true; 2303 fwc->get_dev_path = spapr_get_fw_dev_path; 2304 nc->nmi_monitor_handler = spapr_nmi; 2305 } 2306 2307 static const TypeInfo spapr_machine_info = { 2308 .name = TYPE_SPAPR_MACHINE, 2309 .parent = TYPE_MACHINE, 2310 .abstract = true, 2311 .instance_size = sizeof(sPAPRMachineState), 2312 .instance_init = spapr_machine_initfn, 2313 .instance_finalize = spapr_machine_finalizefn, 2314 .class_size = sizeof(sPAPRMachineClass), 2315 .class_init = spapr_machine_class_init, 2316 .interfaces = (InterfaceInfo[]) { 2317 { TYPE_FW_PATH_PROVIDER }, 2318 { TYPE_NMI }, 2319 { TYPE_HOTPLUG_HANDLER }, 2320 { } 2321 }, 2322 }; 2323 2324 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 2325 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 2326 void *data) \ 2327 { \ 2328 MachineClass *mc = MACHINE_CLASS(oc); \ 2329 spapr_machine_##suffix##_class_options(mc); \ 2330 if (latest) { \ 2331 mc->alias = "pseries"; \ 2332 mc->is_default = 1; \ 2333 } \ 2334 } \ 2335 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 2336 { \ 2337 MachineState *machine = MACHINE(obj); \ 2338 spapr_machine_##suffix##_instance_options(machine); \ 2339 } \ 2340 static const TypeInfo spapr_machine_##suffix##_info = { \ 2341 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 2342 .parent = TYPE_SPAPR_MACHINE, \ 2343 .class_init = spapr_machine_##suffix##_class_init, \ 2344 .instance_init = spapr_machine_##suffix##_instance_init, \ 2345 }; \ 2346 static void spapr_machine_register_##suffix(void) \ 2347 { \ 2348 type_register(&spapr_machine_##suffix##_info); \ 2349 } \ 2350 machine_init(spapr_machine_register_##suffix) 2351 2352 /* 2353 * pseries-2.6 2354 */ 2355 static void spapr_machine_2_6_instance_options(MachineState *machine) 2356 { 2357 } 2358 2359 static void spapr_machine_2_6_class_options(MachineClass *mc) 2360 { 2361 /* Defaults for the latest behaviour inherited from the base class */ 2362 } 2363 2364 DEFINE_SPAPR_MACHINE(2_6, "2.6", true); 2365 2366 /* 2367 * pseries-2.5 2368 */ 2369 #define SPAPR_COMPAT_2_5 \ 2370 HW_COMPAT_2_5 2371 2372 static void spapr_machine_2_5_instance_options(MachineState *machine) 2373 { 2374 } 2375 2376 static void spapr_machine_2_5_class_options(MachineClass *mc) 2377 { 2378 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 2379 2380 spapr_machine_2_6_class_options(mc); 2381 smc->use_ohci_by_default = true; 2382 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 2383 } 2384 2385 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 2386 2387 /* 2388 * pseries-2.4 2389 */ 2390 #define SPAPR_COMPAT_2_4 \ 2391 HW_COMPAT_2_4 2392 2393 static void spapr_machine_2_4_instance_options(MachineState *machine) 2394 { 2395 spapr_machine_2_5_instance_options(machine); 2396 } 2397 2398 static void spapr_machine_2_4_class_options(MachineClass *mc) 2399 { 2400 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 2401 2402 spapr_machine_2_5_class_options(mc); 2403 smc->dr_lmb_enabled = false; 2404 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 2405 } 2406 2407 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 2408 2409 /* 2410 * pseries-2.3 2411 */ 2412 #define SPAPR_COMPAT_2_3 \ 2413 SPAPR_COMPAT_2_4 \ 2414 HW_COMPAT_2_3 \ 2415 {\ 2416 .driver = "spapr-pci-host-bridge",\ 2417 .property = "dynamic-reconfiguration",\ 2418 .value = "off",\ 2419 }, 2420 2421 static void spapr_machine_2_3_instance_options(MachineState *machine) 2422 { 2423 spapr_machine_2_4_instance_options(machine); 2424 savevm_skip_section_footers(); 2425 global_state_set_optional(); 2426 } 2427 2428 static void spapr_machine_2_3_class_options(MachineClass *mc) 2429 { 2430 spapr_machine_2_4_class_options(mc); 2431 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 2432 } 2433 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 2434 2435 /* 2436 * pseries-2.2 2437 */ 2438 2439 #define SPAPR_COMPAT_2_2 \ 2440 SPAPR_COMPAT_2_3 \ 2441 HW_COMPAT_2_2 \ 2442 {\ 2443 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 2444 .property = "mem_win_size",\ 2445 .value = "0x20000000",\ 2446 }, 2447 2448 static void spapr_machine_2_2_instance_options(MachineState *machine) 2449 { 2450 spapr_machine_2_3_instance_options(machine); 2451 } 2452 2453 static void spapr_machine_2_2_class_options(MachineClass *mc) 2454 { 2455 spapr_machine_2_3_class_options(mc); 2456 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 2457 } 2458 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 2459 2460 /* 2461 * pseries-2.1 2462 */ 2463 #define SPAPR_COMPAT_2_1 \ 2464 SPAPR_COMPAT_2_2 \ 2465 HW_COMPAT_2_1 2466 2467 static void spapr_machine_2_1_instance_options(MachineState *machine) 2468 { 2469 spapr_machine_2_2_instance_options(machine); 2470 } 2471 2472 static void spapr_machine_2_1_class_options(MachineClass *mc) 2473 { 2474 spapr_machine_2_2_class_options(mc); 2475 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 2476 } 2477 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 2478 2479 static void spapr_machine_register_types(void) 2480 { 2481 type_register_static(&spapr_machine_info); 2482 } 2483 2484 type_init(spapr_machine_register_types) 2485