1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "sysemu/sysemu.h" 28 #include "sysemu/numa.h" 29 #include "hw/hw.h" 30 #include "hw/fw-path-provider.h" 31 #include "elf.h" 32 #include "net/net.h" 33 #include "sysemu/block-backend.h" 34 #include "sysemu/cpus.h" 35 #include "sysemu/kvm.h" 36 #include "kvm_ppc.h" 37 #include "mmu-hash64.h" 38 #include "qom/cpu.h" 39 40 #include "hw/boards.h" 41 #include "hw/ppc/ppc.h" 42 #include "hw/loader.h" 43 44 #include "hw/ppc/spapr.h" 45 #include "hw/ppc/spapr_vio.h" 46 #include "hw/pci-host/spapr.h" 47 #include "hw/ppc/xics.h" 48 #include "hw/pci/msi.h" 49 50 #include "hw/pci/pci.h" 51 #include "hw/scsi/scsi.h" 52 #include "hw/virtio/virtio-scsi.h" 53 54 #include "exec/address-spaces.h" 55 #include "hw/usb.h" 56 #include "qemu/config-file.h" 57 #include "qemu/error-report.h" 58 #include "trace.h" 59 #include "hw/nmi.h" 60 61 #include "hw/compat.h" 62 63 #include <libfdt.h> 64 65 /* SLOF memory layout: 66 * 67 * SLOF raw image loaded at 0, copies its romfs right below the flat 68 * device-tree, then position SLOF itself 31M below that 69 * 70 * So we set FW_OVERHEAD to 40MB which should account for all of that 71 * and more 72 * 73 * We load our kernel at 4M, leaving space for SLOF initial image 74 */ 75 #define FDT_MAX_SIZE 0x40000 76 #define RTAS_MAX_SIZE 0x10000 77 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 78 #define FW_MAX_SIZE 0x400000 79 #define FW_FILE_NAME "slof.bin" 80 #define FW_OVERHEAD 0x2800000 81 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 82 83 #define MIN_RMA_SLOF 128UL 84 85 #define TIMEBASE_FREQ 512000000ULL 86 87 #define MAX_CPUS 255 88 89 #define PHANDLE_XICP 0x00001111 90 91 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 92 93 typedef struct sPAPRMachineState sPAPRMachineState; 94 95 #define TYPE_SPAPR_MACHINE "spapr-machine" 96 #define SPAPR_MACHINE(obj) \ 97 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 98 99 /** 100 * sPAPRMachineState: 101 */ 102 struct sPAPRMachineState { 103 /*< private >*/ 104 MachineState parent_obj; 105 106 /*< public >*/ 107 char *kvm_type; 108 }; 109 110 sPAPREnvironment *spapr; 111 112 static XICSState *try_create_xics(const char *type, int nr_servers, 113 int nr_irqs, Error **errp) 114 { 115 Error *err = NULL; 116 DeviceState *dev; 117 118 dev = qdev_create(NULL, type); 119 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 120 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 121 object_property_set_bool(OBJECT(dev), true, "realized", &err); 122 if (err) { 123 error_propagate(errp, err); 124 object_unparent(OBJECT(dev)); 125 return NULL; 126 } 127 return XICS_COMMON(dev); 128 } 129 130 static XICSState *xics_system_init(MachineState *machine, 131 int nr_servers, int nr_irqs) 132 { 133 XICSState *icp = NULL; 134 135 if (kvm_enabled()) { 136 Error *err = NULL; 137 138 if (machine_kernel_irqchip_allowed(machine)) { 139 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err); 140 } 141 if (machine_kernel_irqchip_required(machine) && !icp) { 142 error_report("kernel_irqchip requested but unavailable: %s", 143 error_get_pretty(err)); 144 } 145 } 146 147 if (!icp) { 148 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, &error_abort); 149 } 150 151 return icp; 152 } 153 154 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 155 int smt_threads) 156 { 157 int i, ret = 0; 158 uint32_t servers_prop[smt_threads]; 159 uint32_t gservers_prop[smt_threads * 2]; 160 int index = ppc_get_vcpu_dt_id(cpu); 161 162 if (cpu->cpu_version) { 163 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); 164 if (ret < 0) { 165 return ret; 166 } 167 } 168 169 /* Build interrupt servers and gservers properties */ 170 for (i = 0; i < smt_threads; i++) { 171 servers_prop[i] = cpu_to_be32(index + i); 172 /* Hack, direct the group queues back to cpu 0 */ 173 gservers_prop[i*2] = cpu_to_be32(index + i); 174 gservers_prop[i*2 + 1] = 0; 175 } 176 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 177 servers_prop, sizeof(servers_prop)); 178 if (ret < 0) { 179 return ret; 180 } 181 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 182 gservers_prop, sizeof(gservers_prop)); 183 184 return ret; 185 } 186 187 static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) 188 { 189 int ret = 0, offset, cpus_offset; 190 CPUState *cs; 191 char cpu_model[32]; 192 int smt = kvmppc_smt_threads(); 193 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 194 195 CPU_FOREACH(cs) { 196 PowerPCCPU *cpu = POWERPC_CPU(cs); 197 DeviceClass *dc = DEVICE_GET_CLASS(cs); 198 int index = ppc_get_vcpu_dt_id(cpu); 199 uint32_t associativity[] = {cpu_to_be32(0x5), 200 cpu_to_be32(0x0), 201 cpu_to_be32(0x0), 202 cpu_to_be32(0x0), 203 cpu_to_be32(cs->numa_node), 204 cpu_to_be32(index)}; 205 206 if ((index % smt) != 0) { 207 continue; 208 } 209 210 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 211 212 cpus_offset = fdt_path_offset(fdt, "/cpus"); 213 if (cpus_offset < 0) { 214 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 215 "cpus"); 216 if (cpus_offset < 0) { 217 return cpus_offset; 218 } 219 } 220 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 221 if (offset < 0) { 222 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 223 if (offset < 0) { 224 return offset; 225 } 226 } 227 228 if (nb_numa_nodes > 1) { 229 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 230 sizeof(associativity)); 231 if (ret < 0) { 232 return ret; 233 } 234 } 235 236 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 237 pft_size_prop, sizeof(pft_size_prop)); 238 if (ret < 0) { 239 return ret; 240 } 241 242 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 243 ppc_get_compat_smt_threads(cpu)); 244 if (ret < 0) { 245 return ret; 246 } 247 } 248 return ret; 249 } 250 251 252 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 253 size_t maxsize) 254 { 255 size_t maxcells = maxsize / sizeof(uint32_t); 256 int i, j, count; 257 uint32_t *p = prop; 258 259 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 260 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 261 262 if (!sps->page_shift) { 263 break; 264 } 265 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 266 if (sps->enc[count].page_shift == 0) { 267 break; 268 } 269 } 270 if ((p - prop) >= (maxcells - 3 - count * 2)) { 271 break; 272 } 273 *(p++) = cpu_to_be32(sps->page_shift); 274 *(p++) = cpu_to_be32(sps->slb_enc); 275 *(p++) = cpu_to_be32(count); 276 for (j = 0; j < count; j++) { 277 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 278 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 279 } 280 } 281 282 return (p - prop) * sizeof(uint32_t); 283 } 284 285 static hwaddr spapr_node0_size(void) 286 { 287 if (nb_numa_nodes) { 288 int i; 289 for (i = 0; i < nb_numa_nodes; ++i) { 290 if (numa_info[i].node_mem) { 291 return MIN(pow2floor(numa_info[i].node_mem), ram_size); 292 } 293 } 294 } 295 return ram_size; 296 } 297 298 #define _FDT(exp) \ 299 do { \ 300 int ret = (exp); \ 301 if (ret < 0) { \ 302 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 303 #exp, fdt_strerror(ret)); \ 304 exit(1); \ 305 } \ 306 } while (0) 307 308 static void add_str(GString *s, const gchar *s1) 309 { 310 g_string_append_len(s, s1, strlen(s1) + 1); 311 } 312 313 static void *spapr_create_fdt_skel(hwaddr initrd_base, 314 hwaddr initrd_size, 315 hwaddr kernel_size, 316 bool little_endian, 317 const char *kernel_cmdline, 318 uint32_t epow_irq) 319 { 320 void *fdt; 321 CPUState *cs; 322 uint32_t start_prop = cpu_to_be32(initrd_base); 323 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 324 GString *hypertas = g_string_sized_new(256); 325 GString *qemu_hypertas = g_string_sized_new(256); 326 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 327 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; 328 int smt = kvmppc_smt_threads(); 329 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 330 QemuOpts *opts = qemu_opts_find(qemu_find_opts("smp-opts"), NULL); 331 unsigned sockets = opts ? qemu_opt_get_number(opts, "sockets", 0) : 0; 332 uint32_t cpus_per_socket = sockets ? (smp_cpus / sockets) : 1; 333 char *buf; 334 335 add_str(hypertas, "hcall-pft"); 336 add_str(hypertas, "hcall-term"); 337 add_str(hypertas, "hcall-dabr"); 338 add_str(hypertas, "hcall-interrupt"); 339 add_str(hypertas, "hcall-tce"); 340 add_str(hypertas, "hcall-vio"); 341 add_str(hypertas, "hcall-splpar"); 342 add_str(hypertas, "hcall-bulk"); 343 add_str(hypertas, "hcall-set-mode"); 344 add_str(qemu_hypertas, "hcall-memop1"); 345 346 fdt = g_malloc0(FDT_MAX_SIZE); 347 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 348 349 if (kernel_size) { 350 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 351 } 352 if (initrd_size) { 353 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 354 } 355 _FDT((fdt_finish_reservemap(fdt))); 356 357 /* Root node */ 358 _FDT((fdt_begin_node(fdt, ""))); 359 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 360 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 361 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 362 363 /* 364 * Add info to guest to indentify which host is it being run on 365 * and what is the uuid of the guest 366 */ 367 if (kvmppc_get_host_model(&buf)) { 368 _FDT((fdt_property_string(fdt, "host-model", buf))); 369 g_free(buf); 370 } 371 if (kvmppc_get_host_serial(&buf)) { 372 _FDT((fdt_property_string(fdt, "host-serial", buf))); 373 g_free(buf); 374 } 375 376 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1], 377 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4], 378 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7], 379 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10], 380 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13], 381 qemu_uuid[14], qemu_uuid[15]); 382 383 _FDT((fdt_property_string(fdt, "vm,uuid", buf))); 384 g_free(buf); 385 386 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 387 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 388 389 /* /chosen */ 390 _FDT((fdt_begin_node(fdt, "chosen"))); 391 392 /* Set Form1_affinity */ 393 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 394 395 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 396 _FDT((fdt_property(fdt, "linux,initrd-start", 397 &start_prop, sizeof(start_prop)))); 398 _FDT((fdt_property(fdt, "linux,initrd-end", 399 &end_prop, sizeof(end_prop)))); 400 if (kernel_size) { 401 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 402 cpu_to_be64(kernel_size) }; 403 404 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 405 if (little_endian) { 406 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 407 } 408 } 409 if (boot_menu) { 410 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); 411 } 412 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 413 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 414 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 415 416 _FDT((fdt_end_node(fdt))); 417 418 /* cpus */ 419 _FDT((fdt_begin_node(fdt, "cpus"))); 420 421 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 422 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 423 424 CPU_FOREACH(cs) { 425 PowerPCCPU *cpu = POWERPC_CPU(cs); 426 CPUPPCState *env = &cpu->env; 427 DeviceClass *dc = DEVICE_GET_CLASS(cs); 428 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 429 int index = ppc_get_vcpu_dt_id(cpu); 430 char *nodename; 431 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 432 0xffffffff, 0xffffffff}; 433 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 434 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 435 uint32_t page_sizes_prop[64]; 436 size_t page_sizes_prop_size; 437 438 if ((index % smt) != 0) { 439 continue; 440 } 441 442 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 443 444 _FDT((fdt_begin_node(fdt, nodename))); 445 446 g_free(nodename); 447 448 _FDT((fdt_property_cell(fdt, "reg", index))); 449 _FDT((fdt_property_string(fdt, "device_type", "cpu"))); 450 451 _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); 452 _FDT((fdt_property_cell(fdt, "d-cache-block-size", 453 env->dcache_line_size))); 454 _FDT((fdt_property_cell(fdt, "d-cache-line-size", 455 env->dcache_line_size))); 456 _FDT((fdt_property_cell(fdt, "i-cache-block-size", 457 env->icache_line_size))); 458 _FDT((fdt_property_cell(fdt, "i-cache-line-size", 459 env->icache_line_size))); 460 461 if (pcc->l1_dcache_size) { 462 _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size))); 463 } else { 464 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 465 } 466 if (pcc->l1_icache_size) { 467 _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size))); 468 } else { 469 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 470 } 471 472 _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq))); 473 _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq))); 474 _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); 475 _FDT((fdt_property_string(fdt, "status", "okay"))); 476 _FDT((fdt_property(fdt, "64-bit", NULL, 0))); 477 478 if (env->spr_cb[SPR_PURR].oea_read) { 479 _FDT((fdt_property(fdt, "ibm,purr", NULL, 0))); 480 } 481 482 if (env->mmu_model & POWERPC_MMU_1TSEG) { 483 _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", 484 segs, sizeof(segs)))); 485 } 486 487 /* Advertise VMX/VSX (vector extensions) if available 488 * 0 / no property == no vector extensions 489 * 1 == VMX / Altivec available 490 * 2 == VSX available */ 491 if (env->insns_flags & PPC_ALTIVEC) { 492 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 493 494 _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx))); 495 } 496 497 /* Advertise DFP (Decimal Floating Point) if available 498 * 0 / no property == no DFP 499 * 1 == DFP available */ 500 if (env->insns_flags2 & PPC2_DFP) { 501 _FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); 502 } 503 504 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 505 sizeof(page_sizes_prop)); 506 if (page_sizes_prop_size) { 507 _FDT((fdt_property(fdt, "ibm,segment-page-sizes", 508 page_sizes_prop, page_sizes_prop_size))); 509 } 510 511 _FDT((fdt_property_cell(fdt, "ibm,chip-id", 512 cs->cpu_index / cpus_per_socket))); 513 514 _FDT((fdt_end_node(fdt))); 515 } 516 517 _FDT((fdt_end_node(fdt))); 518 519 /* RTAS */ 520 _FDT((fdt_begin_node(fdt, "rtas"))); 521 522 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 523 add_str(hypertas, "hcall-multi-tce"); 524 } 525 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, 526 hypertas->len))); 527 g_string_free(hypertas, TRUE); 528 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, 529 qemu_hypertas->len))); 530 g_string_free(qemu_hypertas, TRUE); 531 532 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 533 refpoints, sizeof(refpoints)))); 534 535 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 536 537 /* 538 * According to PAPR, rtas ibm,os-term does not guarantee a return 539 * back to the guest cpu. 540 * 541 * While an additional ibm,extended-os-term property indicates that 542 * rtas call return will always occur. Set this property. 543 */ 544 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0))); 545 546 _FDT((fdt_end_node(fdt))); 547 548 /* interrupt controller */ 549 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 550 551 _FDT((fdt_property_string(fdt, "device_type", 552 "PowerPC-External-Interrupt-Presentation"))); 553 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 554 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 555 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 556 interrupt_server_ranges_prop, 557 sizeof(interrupt_server_ranges_prop)))); 558 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 559 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 560 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 561 562 _FDT((fdt_end_node(fdt))); 563 564 /* vdevice */ 565 _FDT((fdt_begin_node(fdt, "vdevice"))); 566 567 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 568 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 569 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 570 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 571 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 572 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 573 574 _FDT((fdt_end_node(fdt))); 575 576 /* event-sources */ 577 spapr_events_fdt_skel(fdt, epow_irq); 578 579 /* /hypervisor node */ 580 if (kvm_enabled()) { 581 uint8_t hypercall[16]; 582 583 /* indicate KVM hypercall interface */ 584 _FDT((fdt_begin_node(fdt, "hypervisor"))); 585 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); 586 if (kvmppc_has_cap_fixup_hcalls()) { 587 /* 588 * Older KVM versions with older guest kernels were broken with the 589 * magic page, don't allow the guest to map it. 590 */ 591 kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 592 sizeof(hypercall)); 593 _FDT((fdt_property(fdt, "hcall-instructions", hypercall, 594 sizeof(hypercall)))); 595 } 596 _FDT((fdt_end_node(fdt))); 597 } 598 599 _FDT((fdt_end_node(fdt))); /* close root node */ 600 _FDT((fdt_finish(fdt))); 601 602 return fdt; 603 } 604 605 int spapr_h_cas_compose_response(target_ulong addr, target_ulong size) 606 { 607 void *fdt, *fdt_skel; 608 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 609 610 size -= sizeof(hdr); 611 612 /* Create sceleton */ 613 fdt_skel = g_malloc0(size); 614 _FDT((fdt_create(fdt_skel, size))); 615 _FDT((fdt_begin_node(fdt_skel, ""))); 616 _FDT((fdt_end_node(fdt_skel))); 617 _FDT((fdt_finish(fdt_skel))); 618 fdt = g_malloc0(size); 619 _FDT((fdt_open_into(fdt_skel, fdt, size))); 620 g_free(fdt_skel); 621 622 /* Fix skeleton up */ 623 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 624 625 /* Pack resulting tree */ 626 _FDT((fdt_pack(fdt))); 627 628 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 629 trace_spapr_cas_failed(size); 630 return -1; 631 } 632 633 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 634 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 635 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 636 g_free(fdt); 637 638 return 0; 639 } 640 641 static void spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 642 hwaddr size) 643 { 644 uint32_t associativity[] = { 645 cpu_to_be32(0x4), /* length */ 646 cpu_to_be32(0x0), cpu_to_be32(0x0), 647 cpu_to_be32(0x0), cpu_to_be32(nodeid) 648 }; 649 char mem_name[32]; 650 uint64_t mem_reg_property[2]; 651 int off; 652 653 mem_reg_property[0] = cpu_to_be64(start); 654 mem_reg_property[1] = cpu_to_be64(size); 655 656 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 657 off = fdt_add_subnode(fdt, 0, mem_name); 658 _FDT(off); 659 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 660 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 661 sizeof(mem_reg_property)))); 662 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 663 sizeof(associativity)))); 664 } 665 666 static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt) 667 { 668 hwaddr mem_start, node_size; 669 int i, nb_nodes = nb_numa_nodes; 670 NodeInfo *nodes = numa_info; 671 NodeInfo ramnode; 672 673 /* No NUMA nodes, assume there is just one node with whole RAM */ 674 if (!nb_numa_nodes) { 675 nb_nodes = 1; 676 ramnode.node_mem = ram_size; 677 nodes = &ramnode; 678 } 679 680 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 681 if (!nodes[i].node_mem) { 682 continue; 683 } 684 if (mem_start >= ram_size) { 685 node_size = 0; 686 } else { 687 node_size = nodes[i].node_mem; 688 if (node_size > ram_size - mem_start) { 689 node_size = ram_size - mem_start; 690 } 691 } 692 if (!mem_start) { 693 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 694 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 695 mem_start += spapr->rma_size; 696 node_size -= spapr->rma_size; 697 } 698 for ( ; node_size; ) { 699 hwaddr sizetmp = pow2floor(node_size); 700 701 /* mem_start != 0 here */ 702 if (ctzl(mem_start) < ctzl(sizetmp)) { 703 sizetmp = 1ULL << ctzl(mem_start); 704 } 705 706 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 707 node_size -= sizetmp; 708 mem_start += sizetmp; 709 } 710 } 711 712 return 0; 713 } 714 715 static void spapr_finalize_fdt(sPAPREnvironment *spapr, 716 hwaddr fdt_addr, 717 hwaddr rtas_addr, 718 hwaddr rtas_size) 719 { 720 MachineState *machine = MACHINE(qdev_get_machine()); 721 const char *boot_device = machine->boot_order; 722 int ret, i; 723 size_t cb = 0; 724 char *bootlist; 725 void *fdt; 726 sPAPRPHBState *phb; 727 728 fdt = g_malloc(FDT_MAX_SIZE); 729 730 /* open out the base tree into a temp buffer for the final tweaks */ 731 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 732 733 ret = spapr_populate_memory(spapr, fdt); 734 if (ret < 0) { 735 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 736 exit(1); 737 } 738 739 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 740 if (ret < 0) { 741 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 742 exit(1); 743 } 744 745 QLIST_FOREACH(phb, &spapr->phbs, list) { 746 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 747 } 748 749 if (ret < 0) { 750 fprintf(stderr, "couldn't setup PCI devices in fdt\n"); 751 exit(1); 752 } 753 754 /* RTAS */ 755 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 756 if (ret < 0) { 757 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 758 } 759 760 /* Advertise NUMA via ibm,associativity */ 761 ret = spapr_fixup_cpu_dt(fdt, spapr); 762 if (ret < 0) { 763 fprintf(stderr, "Couldn't finalize CPU device tree properties\n"); 764 } 765 766 bootlist = get_boot_devices_list(&cb, true); 767 if (cb && bootlist) { 768 int offset = fdt_path_offset(fdt, "/chosen"); 769 if (offset < 0) { 770 exit(1); 771 } 772 for (i = 0; i < cb; i++) { 773 if (bootlist[i] == '\n') { 774 bootlist[i] = ' '; 775 } 776 777 } 778 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); 779 } 780 781 if (boot_device && strlen(boot_device)) { 782 int offset = fdt_path_offset(fdt, "/chosen"); 783 784 if (offset < 0) { 785 exit(1); 786 } 787 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device); 788 } 789 790 if (!spapr->has_graphics) { 791 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 792 } 793 794 _FDT((fdt_pack(fdt))); 795 796 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 797 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n", 798 fdt_totalsize(fdt), FDT_MAX_SIZE); 799 exit(1); 800 } 801 802 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 803 804 g_free(bootlist); 805 g_free(fdt); 806 } 807 808 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 809 { 810 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 811 } 812 813 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 814 { 815 CPUPPCState *env = &cpu->env; 816 817 if (msr_pr) { 818 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 819 env->gpr[3] = H_PRIVILEGE; 820 } else { 821 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 822 } 823 } 824 825 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 826 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 827 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 828 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 829 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 830 831 static void spapr_reset_htab(sPAPREnvironment *spapr) 832 { 833 long shift; 834 int index; 835 836 /* allocate hash page table. For now we always make this 16mb, 837 * later we should probably make it scale to the size of guest 838 * RAM */ 839 840 shift = kvmppc_reset_htab(spapr->htab_shift); 841 842 if (shift > 0) { 843 /* Kernel handles htab, we don't need to allocate one */ 844 spapr->htab_shift = shift; 845 kvmppc_kern_htab = true; 846 847 /* Tell readers to update their file descriptor */ 848 if (spapr->htab_fd >= 0) { 849 spapr->htab_fd_stale = true; 850 } 851 } else { 852 if (!spapr->htab) { 853 /* Allocate an htab if we don't yet have one */ 854 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); 855 } 856 857 /* And clear it */ 858 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 859 860 for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) { 861 DIRTY_HPTE(HPTE(spapr->htab, index)); 862 } 863 } 864 865 /* Update the RMA size if necessary */ 866 if (spapr->vrma_adjust) { 867 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 868 spapr->htab_shift); 869 } 870 } 871 872 static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 873 { 874 bool matched = false; 875 876 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 877 matched = true; 878 } 879 880 if (!matched) { 881 error_report("Device %s is not supported by this machine yet.", 882 qdev_fw_name(DEVICE(sbdev))); 883 exit(1); 884 } 885 886 return 0; 887 } 888 889 /* 890 * A guest reset will cause spapr->htab_fd to become stale if being used. 891 * Reopen the file descriptor to make sure the whole HTAB is properly read. 892 */ 893 static int spapr_check_htab_fd(sPAPREnvironment *spapr) 894 { 895 int rc = 0; 896 897 if (spapr->htab_fd_stale) { 898 close(spapr->htab_fd); 899 spapr->htab_fd = kvmppc_get_htab_fd(false); 900 if (spapr->htab_fd < 0) { 901 error_report("Unable to open fd for reading hash table from KVM: " 902 "%s", strerror(errno)); 903 rc = -1; 904 } 905 spapr->htab_fd_stale = false; 906 } 907 908 return rc; 909 } 910 911 static void ppc_spapr_reset(void) 912 { 913 PowerPCCPU *first_ppc_cpu; 914 uint32_t rtas_limit; 915 916 /* Check for unknown sysbus devices */ 917 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 918 919 /* Reset the hash table & recalc the RMA */ 920 spapr_reset_htab(spapr); 921 922 qemu_devices_reset(); 923 924 /* 925 * We place the device tree and RTAS just below either the top of the RMA, 926 * or just below 2GB, whichever is lowere, so that it can be 927 * processed with 32-bit real mode code if necessary 928 */ 929 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 930 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 931 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 932 933 /* Load the fdt */ 934 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 935 spapr->rtas_size); 936 937 /* Copy RTAS over */ 938 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob, 939 spapr->rtas_size); 940 941 /* Set up the entry state */ 942 first_ppc_cpu = POWERPC_CPU(first_cpu); 943 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 944 first_ppc_cpu->env.gpr[5] = 0; 945 first_cpu->halted = 0; 946 first_ppc_cpu->env.nip = spapr->entry_point; 947 948 } 949 950 static void spapr_cpu_reset(void *opaque) 951 { 952 PowerPCCPU *cpu = opaque; 953 CPUState *cs = CPU(cpu); 954 CPUPPCState *env = &cpu->env; 955 956 cpu_reset(cs); 957 958 /* All CPUs start halted. CPU0 is unhalted from the machine level 959 * reset code and the rest are explicitly started up by the guest 960 * using an RTAS call */ 961 cs->halted = 1; 962 963 env->spr[SPR_HIOR] = 0; 964 965 env->external_htab = (uint8_t *)spapr->htab; 966 if (kvm_enabled() && !env->external_htab) { 967 /* 968 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte* 969 * functions do the right thing. 970 */ 971 env->external_htab = (void *)1; 972 } 973 env->htab_base = -1; 974 /* 975 * htab_mask is the mask used to normalize hash value to PTEG index. 976 * htab_shift is log2 of hash table size. 977 * We have 8 hpte per group, and each hpte is 16 bytes. 978 * ie have 128 bytes per hpte entry. 979 */ 980 env->htab_mask = (1ULL << ((spapr)->htab_shift - 7)) - 1; 981 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | 982 (spapr->htab_shift - 18); 983 } 984 985 static void spapr_create_nvram(sPAPREnvironment *spapr) 986 { 987 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 988 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 989 990 if (dinfo) { 991 qdev_prop_set_drive_nofail(dev, "drive", blk_by_legacy_dinfo(dinfo)); 992 } 993 994 qdev_init_nofail(dev); 995 996 spapr->nvram = (struct sPAPRNVRAM *)dev; 997 } 998 999 static void spapr_rtc_create(sPAPREnvironment *spapr) 1000 { 1001 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); 1002 1003 qdev_init_nofail(dev); 1004 spapr->rtc = dev; 1005 1006 object_property_add_alias(qdev_get_machine(), "rtc-time", 1007 OBJECT(spapr->rtc), "date", NULL); 1008 } 1009 1010 /* Returns whether we want to use VGA or not */ 1011 static int spapr_vga_init(PCIBus *pci_bus) 1012 { 1013 switch (vga_interface_type) { 1014 case VGA_NONE: 1015 return false; 1016 case VGA_DEVICE: 1017 return true; 1018 case VGA_STD: 1019 return pci_vga_init(pci_bus) != NULL; 1020 default: 1021 fprintf(stderr, "This vga model is not supported," 1022 "currently it only supports -vga std\n"); 1023 exit(0); 1024 } 1025 } 1026 1027 static int spapr_post_load(void *opaque, int version_id) 1028 { 1029 sPAPREnvironment *spapr = (sPAPREnvironment *)opaque; 1030 int err = 0; 1031 1032 /* In earlier versions, there was no seperate qdev for the PAPR 1033 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1034 * So when migrating from those versions, poke the incoming offset 1035 * value into the RTC device */ 1036 if (version_id < 3) { 1037 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); 1038 } 1039 1040 return err; 1041 } 1042 1043 static bool version_before_3(void *opaque, int version_id) 1044 { 1045 return version_id < 3; 1046 } 1047 1048 static const VMStateDescription vmstate_spapr = { 1049 .name = "spapr", 1050 .version_id = 3, 1051 .minimum_version_id = 1, 1052 .post_load = spapr_post_load, 1053 .fields = (VMStateField[]) { 1054 /* used to be @next_irq */ 1055 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1056 1057 /* RTC offset */ 1058 VMSTATE_UINT64_TEST(rtc_offset, sPAPREnvironment, version_before_3), 1059 1060 VMSTATE_PPC_TIMEBASE_V(tb, sPAPREnvironment, 2), 1061 VMSTATE_END_OF_LIST() 1062 }, 1063 }; 1064 1065 static int htab_save_setup(QEMUFile *f, void *opaque) 1066 { 1067 sPAPREnvironment *spapr = opaque; 1068 1069 /* "Iteration" header */ 1070 qemu_put_be32(f, spapr->htab_shift); 1071 1072 if (spapr->htab) { 1073 spapr->htab_save_index = 0; 1074 spapr->htab_first_pass = true; 1075 } else { 1076 assert(kvm_enabled()); 1077 1078 spapr->htab_fd = kvmppc_get_htab_fd(false); 1079 spapr->htab_fd_stale = false; 1080 if (spapr->htab_fd < 0) { 1081 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", 1082 strerror(errno)); 1083 return -1; 1084 } 1085 } 1086 1087 1088 return 0; 1089 } 1090 1091 static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr, 1092 int64_t max_ns) 1093 { 1094 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1095 int index = spapr->htab_save_index; 1096 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1097 1098 assert(spapr->htab_first_pass); 1099 1100 do { 1101 int chunkstart; 1102 1103 /* Consume invalid HPTEs */ 1104 while ((index < htabslots) 1105 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1106 index++; 1107 CLEAN_HPTE(HPTE(spapr->htab, index)); 1108 } 1109 1110 /* Consume valid HPTEs */ 1111 chunkstart = index; 1112 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1113 && HPTE_VALID(HPTE(spapr->htab, index))) { 1114 index++; 1115 CLEAN_HPTE(HPTE(spapr->htab, index)); 1116 } 1117 1118 if (index > chunkstart) { 1119 int n_valid = index - chunkstart; 1120 1121 qemu_put_be32(f, chunkstart); 1122 qemu_put_be16(f, n_valid); 1123 qemu_put_be16(f, 0); 1124 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1125 HASH_PTE_SIZE_64 * n_valid); 1126 1127 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1128 break; 1129 } 1130 } 1131 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1132 1133 if (index >= htabslots) { 1134 assert(index == htabslots); 1135 index = 0; 1136 spapr->htab_first_pass = false; 1137 } 1138 spapr->htab_save_index = index; 1139 } 1140 1141 static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, 1142 int64_t max_ns) 1143 { 1144 bool final = max_ns < 0; 1145 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1146 int examined = 0, sent = 0; 1147 int index = spapr->htab_save_index; 1148 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1149 1150 assert(!spapr->htab_first_pass); 1151 1152 do { 1153 int chunkstart, invalidstart; 1154 1155 /* Consume non-dirty HPTEs */ 1156 while ((index < htabslots) 1157 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1158 index++; 1159 examined++; 1160 } 1161 1162 chunkstart = index; 1163 /* Consume valid dirty HPTEs */ 1164 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1165 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1166 && HPTE_VALID(HPTE(spapr->htab, index))) { 1167 CLEAN_HPTE(HPTE(spapr->htab, index)); 1168 index++; 1169 examined++; 1170 } 1171 1172 invalidstart = index; 1173 /* Consume invalid dirty HPTEs */ 1174 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1175 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1176 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1177 CLEAN_HPTE(HPTE(spapr->htab, index)); 1178 index++; 1179 examined++; 1180 } 1181 1182 if (index > chunkstart) { 1183 int n_valid = invalidstart - chunkstart; 1184 int n_invalid = index - invalidstart; 1185 1186 qemu_put_be32(f, chunkstart); 1187 qemu_put_be16(f, n_valid); 1188 qemu_put_be16(f, n_invalid); 1189 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1190 HASH_PTE_SIZE_64 * n_valid); 1191 sent += index - chunkstart; 1192 1193 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1194 break; 1195 } 1196 } 1197 1198 if (examined >= htabslots) { 1199 break; 1200 } 1201 1202 if (index >= htabslots) { 1203 assert(index == htabslots); 1204 index = 0; 1205 } 1206 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1207 1208 if (index >= htabslots) { 1209 assert(index == htabslots); 1210 index = 0; 1211 } 1212 1213 spapr->htab_save_index = index; 1214 1215 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1216 } 1217 1218 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1219 #define MAX_KVM_BUF_SIZE 2048 1220 1221 static int htab_save_iterate(QEMUFile *f, void *opaque) 1222 { 1223 sPAPREnvironment *spapr = opaque; 1224 int rc = 0; 1225 1226 /* Iteration header */ 1227 qemu_put_be32(f, 0); 1228 1229 if (!spapr->htab) { 1230 assert(kvm_enabled()); 1231 1232 rc = spapr_check_htab_fd(spapr); 1233 if (rc < 0) { 1234 return rc; 1235 } 1236 1237 rc = kvmppc_save_htab(f, spapr->htab_fd, 1238 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1239 if (rc < 0) { 1240 return rc; 1241 } 1242 } else if (spapr->htab_first_pass) { 1243 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1244 } else { 1245 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1246 } 1247 1248 /* End marker */ 1249 qemu_put_be32(f, 0); 1250 qemu_put_be16(f, 0); 1251 qemu_put_be16(f, 0); 1252 1253 return rc; 1254 } 1255 1256 static int htab_save_complete(QEMUFile *f, void *opaque) 1257 { 1258 sPAPREnvironment *spapr = opaque; 1259 1260 /* Iteration header */ 1261 qemu_put_be32(f, 0); 1262 1263 if (!spapr->htab) { 1264 int rc; 1265 1266 assert(kvm_enabled()); 1267 1268 rc = spapr_check_htab_fd(spapr); 1269 if (rc < 0) { 1270 return rc; 1271 } 1272 1273 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); 1274 if (rc < 0) { 1275 return rc; 1276 } 1277 close(spapr->htab_fd); 1278 spapr->htab_fd = -1; 1279 } else { 1280 htab_save_later_pass(f, spapr, -1); 1281 } 1282 1283 /* End marker */ 1284 qemu_put_be32(f, 0); 1285 qemu_put_be16(f, 0); 1286 qemu_put_be16(f, 0); 1287 1288 return 0; 1289 } 1290 1291 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1292 { 1293 sPAPREnvironment *spapr = opaque; 1294 uint32_t section_hdr; 1295 int fd = -1; 1296 1297 if (version_id < 1 || version_id > 1) { 1298 fprintf(stderr, "htab_load() bad version\n"); 1299 return -EINVAL; 1300 } 1301 1302 section_hdr = qemu_get_be32(f); 1303 1304 if (section_hdr) { 1305 /* First section, just the hash shift */ 1306 if (spapr->htab_shift != section_hdr) { 1307 return -EINVAL; 1308 } 1309 return 0; 1310 } 1311 1312 if (!spapr->htab) { 1313 assert(kvm_enabled()); 1314 1315 fd = kvmppc_get_htab_fd(true); 1316 if (fd < 0) { 1317 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", 1318 strerror(errno)); 1319 } 1320 } 1321 1322 while (true) { 1323 uint32_t index; 1324 uint16_t n_valid, n_invalid; 1325 1326 index = qemu_get_be32(f); 1327 n_valid = qemu_get_be16(f); 1328 n_invalid = qemu_get_be16(f); 1329 1330 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1331 /* End of Stream */ 1332 break; 1333 } 1334 1335 if ((index + n_valid + n_invalid) > 1336 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1337 /* Bad index in stream */ 1338 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " 1339 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, 1340 spapr->htab_shift); 1341 return -EINVAL; 1342 } 1343 1344 if (spapr->htab) { 1345 if (n_valid) { 1346 qemu_get_buffer(f, HPTE(spapr->htab, index), 1347 HASH_PTE_SIZE_64 * n_valid); 1348 } 1349 if (n_invalid) { 1350 memset(HPTE(spapr->htab, index + n_valid), 0, 1351 HASH_PTE_SIZE_64 * n_invalid); 1352 } 1353 } else { 1354 int rc; 1355 1356 assert(fd >= 0); 1357 1358 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1359 if (rc < 0) { 1360 return rc; 1361 } 1362 } 1363 } 1364 1365 if (!spapr->htab) { 1366 assert(fd >= 0); 1367 close(fd); 1368 } 1369 1370 return 0; 1371 } 1372 1373 static SaveVMHandlers savevm_htab_handlers = { 1374 .save_live_setup = htab_save_setup, 1375 .save_live_iterate = htab_save_iterate, 1376 .save_live_complete = htab_save_complete, 1377 .load_state = htab_load, 1378 }; 1379 1380 static void spapr_boot_set(void *opaque, const char *boot_device, 1381 Error **errp) 1382 { 1383 MachineState *machine = MACHINE(qdev_get_machine()); 1384 machine->boot_order = g_strdup(boot_device); 1385 } 1386 1387 /* pSeries LPAR / sPAPR hardware init */ 1388 static void ppc_spapr_init(MachineState *machine) 1389 { 1390 ram_addr_t ram_size = machine->ram_size; 1391 const char *cpu_model = machine->cpu_model; 1392 const char *kernel_filename = machine->kernel_filename; 1393 const char *kernel_cmdline = machine->kernel_cmdline; 1394 const char *initrd_filename = machine->initrd_filename; 1395 PowerPCCPU *cpu; 1396 CPUPPCState *env; 1397 PCIHostState *phb; 1398 int i; 1399 MemoryRegion *sysmem = get_system_memory(); 1400 MemoryRegion *ram = g_new(MemoryRegion, 1); 1401 MemoryRegion *rma_region; 1402 void *rma = NULL; 1403 hwaddr rma_alloc_size; 1404 hwaddr node0_size = spapr_node0_size(); 1405 uint32_t initrd_base = 0; 1406 long kernel_size = 0, initrd_size = 0; 1407 long load_limit, fw_size; 1408 bool kernel_le = false; 1409 char *filename; 1410 1411 msi_supported = true; 1412 1413 spapr = g_malloc0(sizeof(*spapr)); 1414 QLIST_INIT(&spapr->phbs); 1415 1416 cpu_ppc_hypercall = emulate_spapr_hypercall; 1417 1418 /* Allocate RMA if necessary */ 1419 rma_alloc_size = kvmppc_alloc_rma(&rma); 1420 1421 if (rma_alloc_size == -1) { 1422 hw_error("qemu: Unable to create RMA\n"); 1423 exit(1); 1424 } 1425 1426 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1427 spapr->rma_size = rma_alloc_size; 1428 } else { 1429 spapr->rma_size = node0_size; 1430 1431 /* With KVM, we don't actually know whether KVM supports an 1432 * unbounded RMA (PR KVM) or is limited by the hash table size 1433 * (HV KVM using VRMA), so we always assume the latter 1434 * 1435 * In that case, we also limit the initial allocations for RTAS 1436 * etc... to 256M since we have no way to know what the VRMA size 1437 * is going to be as it depends on the size of the hash table 1438 * isn't determined yet. 1439 */ 1440 if (kvm_enabled()) { 1441 spapr->vrma_adjust = 1; 1442 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1443 } 1444 } 1445 1446 if (spapr->rma_size > node0_size) { 1447 fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n", 1448 spapr->rma_size); 1449 exit(1); 1450 } 1451 1452 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 1453 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 1454 1455 /* We aim for a hash table of size 1/128 the size of RAM. The 1456 * normal rule of thumb is 1/64 the size of RAM, but that's much 1457 * more than needed for the Linux guests we support. */ 1458 spapr->htab_shift = 18; /* Minimum architected size */ 1459 while (spapr->htab_shift <= 46) { 1460 if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) { 1461 break; 1462 } 1463 spapr->htab_shift++; 1464 } 1465 1466 /* Set up Interrupt Controller before we create the VCPUs */ 1467 spapr->icp = xics_system_init(machine, 1468 smp_cpus * kvmppc_smt_threads() / smp_threads, 1469 XICS_IRQS); 1470 1471 /* init CPUs */ 1472 if (cpu_model == NULL) { 1473 cpu_model = kvm_enabled() ? "host" : "POWER7"; 1474 } 1475 for (i = 0; i < smp_cpus; i++) { 1476 cpu = cpu_ppc_init(cpu_model); 1477 if (cpu == NULL) { 1478 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 1479 exit(1); 1480 } 1481 env = &cpu->env; 1482 1483 /* Set time-base frequency to 512 MHz */ 1484 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 1485 1486 /* PAPR always has exception vectors in RAM not ROM. To ensure this, 1487 * MSR[IP] should never be set. 1488 */ 1489 env->msr_mask &= ~(1 << 6); 1490 1491 /* Tell KVM that we're in PAPR mode */ 1492 if (kvm_enabled()) { 1493 kvmppc_set_papr(cpu); 1494 } 1495 1496 if (cpu->max_compat) { 1497 if (ppc_set_compat(cpu, cpu->max_compat) < 0) { 1498 exit(1); 1499 } 1500 } 1501 1502 xics_cpu_setup(spapr->icp, cpu); 1503 1504 qemu_register_reset(spapr_cpu_reset, cpu); 1505 } 1506 1507 /* allocate RAM */ 1508 spapr->ram_limit = ram_size; 1509 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 1510 spapr->ram_limit); 1511 memory_region_add_subregion(sysmem, 0, ram); 1512 1513 if (rma_alloc_size && rma) { 1514 rma_region = g_new(MemoryRegion, 1); 1515 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 1516 rma_alloc_size, rma); 1517 vmstate_register_ram_global(rma_region); 1518 memory_region_add_subregion(sysmem, 0, rma_region); 1519 } 1520 1521 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1522 if (!filename) { 1523 hw_error("Could not find LPAR rtas '%s'\n", "spapr-rtas.bin"); 1524 exit(1); 1525 } 1526 spapr->rtas_size = get_image_size(filename); 1527 spapr->rtas_blob = g_malloc(spapr->rtas_size); 1528 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 1529 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1530 exit(1); 1531 } 1532 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1533 hw_error("RTAS too big ! 0x%zx bytes (max is 0x%x)\n", 1534 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 1535 exit(1); 1536 } 1537 g_free(filename); 1538 1539 /* Set up EPOW events infrastructure */ 1540 spapr_events_init(spapr); 1541 1542 /* Set up the RTC RTAS interfaces */ 1543 spapr_rtc_create(spapr); 1544 1545 /* Set up VIO bus */ 1546 spapr->vio_bus = spapr_vio_bus_init(); 1547 1548 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1549 if (serial_hds[i]) { 1550 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1551 } 1552 } 1553 1554 /* We always have at least the nvram device on VIO */ 1555 spapr_create_nvram(spapr); 1556 1557 /* Set up PCI */ 1558 spapr_pci_rtas_init(); 1559 1560 phb = spapr_create_phb(spapr, 0); 1561 1562 for (i = 0; i < nb_nics; i++) { 1563 NICInfo *nd = &nd_table[i]; 1564 1565 if (!nd->model) { 1566 nd->model = g_strdup("ibmveth"); 1567 } 1568 1569 if (strcmp(nd->model, "ibmveth") == 0) { 1570 spapr_vlan_create(spapr->vio_bus, nd); 1571 } else { 1572 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1573 } 1574 } 1575 1576 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1577 spapr_vscsi_create(spapr->vio_bus); 1578 } 1579 1580 /* Graphics */ 1581 if (spapr_vga_init(phb->bus)) { 1582 spapr->has_graphics = true; 1583 machine->usb |= defaults_enabled() && !machine->usb_disabled; 1584 } 1585 1586 if (machine->usb) { 1587 pci_create_simple(phb->bus, -1, "pci-ohci"); 1588 1589 if (spapr->has_graphics) { 1590 USBBus *usb_bus = usb_bus_find(-1); 1591 1592 usb_create_simple(usb_bus, "usb-kbd"); 1593 usb_create_simple(usb_bus, "usb-mouse"); 1594 } 1595 } 1596 1597 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1598 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " 1599 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); 1600 exit(1); 1601 } 1602 1603 if (kernel_filename) { 1604 uint64_t lowaddr = 0; 1605 1606 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1607 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); 1608 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { 1609 kernel_size = load_elf(kernel_filename, 1610 translate_kernel_address, NULL, 1611 NULL, &lowaddr, NULL, 0, ELF_MACHINE, 0); 1612 kernel_le = kernel_size > 0; 1613 } 1614 if (kernel_size < 0) { 1615 fprintf(stderr, "qemu: error loading %s: %s\n", 1616 kernel_filename, load_elf_strerror(kernel_size)); 1617 exit(1); 1618 } 1619 1620 /* load initrd */ 1621 if (initrd_filename) { 1622 /* Try to locate the initrd in the gap between the kernel 1623 * and the firmware. Add a bit of space just in case 1624 */ 1625 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1626 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1627 load_limit - initrd_base); 1628 if (initrd_size < 0) { 1629 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 1630 initrd_filename); 1631 exit(1); 1632 } 1633 } else { 1634 initrd_base = 0; 1635 initrd_size = 0; 1636 } 1637 } 1638 1639 if (bios_name == NULL) { 1640 bios_name = FW_FILE_NAME; 1641 } 1642 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1643 if (!filename) { 1644 hw_error("Could not find LPAR rtas '%s'\n", bios_name); 1645 exit(1); 1646 } 1647 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 1648 if (fw_size < 0) { 1649 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1650 exit(1); 1651 } 1652 g_free(filename); 1653 1654 spapr->entry_point = 0x100; 1655 1656 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 1657 register_savevm_live(NULL, "spapr/htab", -1, 1, 1658 &savevm_htab_handlers, spapr); 1659 1660 /* Prepare the device tree */ 1661 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 1662 kernel_size, kernel_le, 1663 kernel_cmdline, spapr->epow_irq); 1664 assert(spapr->fdt_skel != NULL); 1665 1666 qemu_register_boot_set(spapr_boot_set, spapr); 1667 } 1668 1669 static int spapr_kvm_type(const char *vm_type) 1670 { 1671 if (!vm_type) { 1672 return 0; 1673 } 1674 1675 if (!strcmp(vm_type, "HV")) { 1676 return 1; 1677 } 1678 1679 if (!strcmp(vm_type, "PR")) { 1680 return 2; 1681 } 1682 1683 error_report("Unknown kvm-type specified '%s'", vm_type); 1684 exit(1); 1685 } 1686 1687 /* 1688 * Implementation of an interface to adjust firmware path 1689 * for the bootindex property handling. 1690 */ 1691 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 1692 DeviceState *dev) 1693 { 1694 #define CAST(type, obj, name) \ 1695 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 1696 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 1697 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 1698 1699 if (d) { 1700 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 1701 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 1702 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 1703 1704 if (spapr) { 1705 /* 1706 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 1707 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 1708 * in the top 16 bits of the 64-bit LUN 1709 */ 1710 unsigned id = 0x8000 | (d->id << 8) | d->lun; 1711 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1712 (uint64_t)id << 48); 1713 } else if (virtio) { 1714 /* 1715 * We use SRP luns of the form 01000000 | (target << 8) | lun 1716 * in the top 32 bits of the 64-bit LUN 1717 * Note: the quote above is from SLOF and it is wrong, 1718 * the actual binding is: 1719 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 1720 */ 1721 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 1722 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1723 (uint64_t)id << 32); 1724 } else if (usb) { 1725 /* 1726 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 1727 * in the top 32 bits of the 64-bit LUN 1728 */ 1729 unsigned usb_port = atoi(usb->port->path); 1730 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 1731 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1732 (uint64_t)id << 32); 1733 } 1734 } 1735 1736 if (phb) { 1737 /* Replace "pci" with "pci@800000020000000" */ 1738 return g_strdup_printf("pci@%"PRIX64, phb->buid); 1739 } 1740 1741 return NULL; 1742 } 1743 1744 static char *spapr_get_kvm_type(Object *obj, Error **errp) 1745 { 1746 sPAPRMachineState *sm = SPAPR_MACHINE(obj); 1747 1748 return g_strdup(sm->kvm_type); 1749 } 1750 1751 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 1752 { 1753 sPAPRMachineState *sm = SPAPR_MACHINE(obj); 1754 1755 g_free(sm->kvm_type); 1756 sm->kvm_type = g_strdup(value); 1757 } 1758 1759 static void spapr_machine_initfn(Object *obj) 1760 { 1761 object_property_add_str(obj, "kvm-type", 1762 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 1763 object_property_set_description(obj, "kvm-type", 1764 "Specifies the KVM virtualization mode (HV, PR)", 1765 NULL); 1766 } 1767 1768 static void ppc_cpu_do_nmi_on_cpu(void *arg) 1769 { 1770 CPUState *cs = arg; 1771 1772 cpu_synchronize_state(cs); 1773 ppc_cpu_do_system_reset(cs); 1774 } 1775 1776 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 1777 { 1778 CPUState *cs; 1779 1780 CPU_FOREACH(cs) { 1781 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs); 1782 } 1783 } 1784 1785 static void spapr_machine_class_init(ObjectClass *oc, void *data) 1786 { 1787 MachineClass *mc = MACHINE_CLASS(oc); 1788 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 1789 NMIClass *nc = NMI_CLASS(oc); 1790 1791 mc->init = ppc_spapr_init; 1792 mc->reset = ppc_spapr_reset; 1793 mc->block_default_type = IF_SCSI; 1794 mc->max_cpus = MAX_CPUS; 1795 mc->no_parallel = 1; 1796 mc->default_boot_order = ""; 1797 mc->kvm_type = spapr_kvm_type; 1798 mc->has_dynamic_sysbus = true; 1799 1800 fwc->get_dev_path = spapr_get_fw_dev_path; 1801 nc->nmi_monitor_handler = spapr_nmi; 1802 } 1803 1804 static const TypeInfo spapr_machine_info = { 1805 .name = TYPE_SPAPR_MACHINE, 1806 .parent = TYPE_MACHINE, 1807 .abstract = true, 1808 .instance_size = sizeof(sPAPRMachineState), 1809 .instance_init = spapr_machine_initfn, 1810 .class_init = spapr_machine_class_init, 1811 .interfaces = (InterfaceInfo[]) { 1812 { TYPE_FW_PATH_PROVIDER }, 1813 { TYPE_NMI }, 1814 { } 1815 }, 1816 }; 1817 1818 #define SPAPR_COMPAT_2_2 \ 1819 {\ 1820 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 1821 .property = "mem_win_size",\ 1822 .value = "0x20000000",\ 1823 } 1824 1825 #define SPAPR_COMPAT_2_1 \ 1826 SPAPR_COMPAT_2_2 1827 1828 static void spapr_machine_2_1_class_init(ObjectClass *oc, void *data) 1829 { 1830 MachineClass *mc = MACHINE_CLASS(oc); 1831 static GlobalProperty compat_props[] = { 1832 HW_COMPAT_2_1, 1833 SPAPR_COMPAT_2_1, 1834 { /* end of list */ } 1835 }; 1836 1837 mc->name = "pseries-2.1"; 1838 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.1"; 1839 mc->compat_props = compat_props; 1840 } 1841 1842 static const TypeInfo spapr_machine_2_1_info = { 1843 .name = TYPE_SPAPR_MACHINE "2.1", 1844 .parent = TYPE_SPAPR_MACHINE, 1845 .class_init = spapr_machine_2_1_class_init, 1846 }; 1847 1848 static void spapr_machine_2_2_class_init(ObjectClass *oc, void *data) 1849 { 1850 static GlobalProperty compat_props[] = { 1851 SPAPR_COMPAT_2_2, 1852 { /* end of list */ } 1853 }; 1854 MachineClass *mc = MACHINE_CLASS(oc); 1855 1856 mc->name = "pseries-2.2"; 1857 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.2"; 1858 mc->compat_props = compat_props; 1859 } 1860 1861 static const TypeInfo spapr_machine_2_2_info = { 1862 .name = TYPE_SPAPR_MACHINE "2.2", 1863 .parent = TYPE_SPAPR_MACHINE, 1864 .class_init = spapr_machine_2_2_class_init, 1865 }; 1866 1867 static void spapr_machine_2_3_class_init(ObjectClass *oc, void *data) 1868 { 1869 MachineClass *mc = MACHINE_CLASS(oc); 1870 1871 mc->name = "pseries-2.3"; 1872 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.3"; 1873 mc->alias = "pseries"; 1874 mc->is_default = 1; 1875 } 1876 1877 static const TypeInfo spapr_machine_2_3_info = { 1878 .name = TYPE_SPAPR_MACHINE "2.3", 1879 .parent = TYPE_SPAPR_MACHINE, 1880 .class_init = spapr_machine_2_3_class_init, 1881 }; 1882 1883 static void spapr_machine_register_types(void) 1884 { 1885 type_register_static(&spapr_machine_info); 1886 type_register_static(&spapr_machine_2_1_info); 1887 type_register_static(&spapr_machine_2_2_info); 1888 type_register_static(&spapr_machine_2_3_info); 1889 } 1890 1891 type_init(spapr_machine_register_types) 1892