xref: /openbmc/qemu/hw/ppc/spapr.c (revision 71f364b7)
1 /*
2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3  *
4  * Copyright (c) 2004-2007 Fabrice Bellard
5  * Copyright (c) 2007 Jocelyn Mayer
6  * Copyright (c) 2010 David Gibson, IBM Corporation.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a copy
9  * of this software and associated documentation files (the "Software"), to deal
10  * in the Software without restriction, including without limitation the rights
11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12  * copies of the Software, and to permit persons to whom the Software is
13  * furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be included in
16  * all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24  * THE SOFTWARE.
25  */
26 
27 #include "qemu/osdep.h"
28 #include "qemu-common.h"
29 #include "qapi/error.h"
30 #include "qapi/visitor.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/hostmem.h"
33 #include "sysemu/numa.h"
34 #include "sysemu/qtest.h"
35 #include "sysemu/reset.h"
36 #include "sysemu/runstate.h"
37 #include "qemu/log.h"
38 #include "hw/fw-path-provider.h"
39 #include "elf.h"
40 #include "net/net.h"
41 #include "sysemu/device_tree.h"
42 #include "sysemu/cpus.h"
43 #include "sysemu/hw_accel.h"
44 #include "kvm_ppc.h"
45 #include "migration/misc.h"
46 #include "migration/qemu-file-types.h"
47 #include "migration/global_state.h"
48 #include "migration/register.h"
49 #include "migration/blocker.h"
50 #include "mmu-hash64.h"
51 #include "mmu-book3s-v3.h"
52 #include "cpu-models.h"
53 #include "hw/core/cpu.h"
54 
55 #include "hw/boards.h"
56 #include "hw/ppc/ppc.h"
57 #include "hw/loader.h"
58 
59 #include "hw/ppc/fdt.h"
60 #include "hw/ppc/spapr.h"
61 #include "hw/ppc/spapr_vio.h"
62 #include "hw/qdev-properties.h"
63 #include "hw/pci-host/spapr.h"
64 #include "hw/pci/msi.h"
65 
66 #include "hw/pci/pci.h"
67 #include "hw/scsi/scsi.h"
68 #include "hw/virtio/virtio-scsi.h"
69 #include "hw/virtio/vhost-scsi-common.h"
70 
71 #include "exec/address-spaces.h"
72 #include "exec/ram_addr.h"
73 #include "hw/usb.h"
74 #include "qemu/config-file.h"
75 #include "qemu/error-report.h"
76 #include "trace.h"
77 #include "hw/nmi.h"
78 #include "hw/intc/intc.h"
79 
80 #include "hw/ppc/spapr_cpu_core.h"
81 #include "hw/mem/memory-device.h"
82 #include "hw/ppc/spapr_tpm_proxy.h"
83 #include "hw/ppc/spapr_nvdimm.h"
84 #include "hw/ppc/spapr_numa.h"
85 
86 #include "monitor/monitor.h"
87 
88 #include <libfdt.h>
89 
90 /* SLOF memory layout:
91  *
92  * SLOF raw image loaded at 0, copies its romfs right below the flat
93  * device-tree, then position SLOF itself 31M below that
94  *
95  * So we set FW_OVERHEAD to 40MB which should account for all of that
96  * and more
97  *
98  * We load our kernel at 4M, leaving space for SLOF initial image
99  */
100 #define RTAS_MAX_ADDR           0x80000000 /* RTAS must stay below that */
101 #define FW_MAX_SIZE             0x400000
102 #define FW_FILE_NAME            "slof.bin"
103 #define FW_OVERHEAD             0x2800000
104 #define KERNEL_LOAD_ADDR        FW_MAX_SIZE
105 
106 #define MIN_RMA_SLOF            (128 * MiB)
107 
108 #define PHANDLE_INTC            0x00001111
109 
110 /* These two functions implement the VCPU id numbering: one to compute them
111  * all and one to identify thread 0 of a VCORE. Any change to the first one
112  * is likely to have an impact on the second one, so let's keep them close.
113  */
114 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index)
115 {
116     MachineState *ms = MACHINE(spapr);
117     unsigned int smp_threads = ms->smp.threads;
118 
119     assert(spapr->vsmt);
120     return
121         (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads;
122 }
123 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr,
124                                       PowerPCCPU *cpu)
125 {
126     assert(spapr->vsmt);
127     return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0;
128 }
129 
130 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
131 {
132     /* Dummy entries correspond to unused ICPState objects in older QEMUs,
133      * and newer QEMUs don't even have them. In both cases, we don't want
134      * to send anything on the wire.
135      */
136     return false;
137 }
138 
139 static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
140     .name = "icp/server",
141     .version_id = 1,
142     .minimum_version_id = 1,
143     .needed = pre_2_10_vmstate_dummy_icp_needed,
144     .fields = (VMStateField[]) {
145         VMSTATE_UNUSED(4), /* uint32_t xirr */
146         VMSTATE_UNUSED(1), /* uint8_t pending_priority */
147         VMSTATE_UNUSED(1), /* uint8_t mfrr */
148         VMSTATE_END_OF_LIST()
149     },
150 };
151 
152 static void pre_2_10_vmstate_register_dummy_icp(int i)
153 {
154     vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
155                      (void *)(uintptr_t) i);
156 }
157 
158 static void pre_2_10_vmstate_unregister_dummy_icp(int i)
159 {
160     vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
161                        (void *)(uintptr_t) i);
162 }
163 
164 int spapr_max_server_number(SpaprMachineState *spapr)
165 {
166     MachineState *ms = MACHINE(spapr);
167 
168     assert(spapr->vsmt);
169     return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads);
170 }
171 
172 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
173                                   int smt_threads)
174 {
175     int i, ret = 0;
176     uint32_t servers_prop[smt_threads];
177     uint32_t gservers_prop[smt_threads * 2];
178     int index = spapr_get_vcpu_id(cpu);
179 
180     if (cpu->compat_pvr) {
181         ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
182         if (ret < 0) {
183             return ret;
184         }
185     }
186 
187     /* Build interrupt servers and gservers properties */
188     for (i = 0; i < smt_threads; i++) {
189         servers_prop[i] = cpu_to_be32(index + i);
190         /* Hack, direct the group queues back to cpu 0 */
191         gservers_prop[i*2] = cpu_to_be32(index + i);
192         gservers_prop[i*2 + 1] = 0;
193     }
194     ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
195                       servers_prop, sizeof(servers_prop));
196     if (ret < 0) {
197         return ret;
198     }
199     ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
200                       gservers_prop, sizeof(gservers_prop));
201 
202     return ret;
203 }
204 
205 static void spapr_dt_pa_features(SpaprMachineState *spapr,
206                                  PowerPCCPU *cpu,
207                                  void *fdt, int offset)
208 {
209     uint8_t pa_features_206[] = { 6, 0,
210         0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
211     uint8_t pa_features_207[] = { 24, 0,
212         0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
213         0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
214         0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
215         0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
216     uint8_t pa_features_300[] = { 66, 0,
217         /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
218         /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
219         0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
220         /* 6: DS207 */
221         0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
222         /* 16: Vector */
223         0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
224         /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
225         0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
226         /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
227         0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
228         /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
229         0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
230         /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
231         0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
232         /* 42: PM, 44: PC RA, 46: SC vec'd */
233         0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
234         /* 48: SIMD, 50: QP BFP, 52: String */
235         0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
236         /* 54: DecFP, 56: DecI, 58: SHA */
237         0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
238         /* 60: NM atomic, 62: RNG */
239         0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
240     };
241     uint8_t *pa_features = NULL;
242     size_t pa_size;
243 
244     if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) {
245         pa_features = pa_features_206;
246         pa_size = sizeof(pa_features_206);
247     }
248     if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) {
249         pa_features = pa_features_207;
250         pa_size = sizeof(pa_features_207);
251     }
252     if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) {
253         pa_features = pa_features_300;
254         pa_size = sizeof(pa_features_300);
255     }
256     if (!pa_features) {
257         return;
258     }
259 
260     if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
261         /*
262          * Note: we keep CI large pages off by default because a 64K capable
263          * guest provisioned with large pages might otherwise try to map a qemu
264          * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
265          * even if that qemu runs on a 4k host.
266          * We dd this bit back here if we are confident this is not an issue
267          */
268         pa_features[3] |= 0x20;
269     }
270     if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
271         pa_features[24] |= 0x80;    /* Transactional memory support */
272     }
273     if (spapr->cas_pre_isa3_guest && pa_size > 40) {
274         /* Workaround for broken kernels that attempt (guest) radix
275          * mode when they can't handle it, if they see the radix bit set
276          * in pa-features. So hide it from them. */
277         pa_features[40 + 2] &= ~0x80; /* Radix MMU */
278     }
279 
280     _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
281 }
282 
283 static hwaddr spapr_node0_size(MachineState *machine)
284 {
285     if (machine->numa_state->num_nodes) {
286         int i;
287         for (i = 0; i < machine->numa_state->num_nodes; ++i) {
288             if (machine->numa_state->nodes[i].node_mem) {
289                 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem),
290                            machine->ram_size);
291             }
292         }
293     }
294     return machine->ram_size;
295 }
296 
297 static void add_str(GString *s, const gchar *s1)
298 {
299     g_string_append_len(s, s1, strlen(s1) + 1);
300 }
301 
302 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid,
303                                 hwaddr start, hwaddr size)
304 {
305     char mem_name[32];
306     uint64_t mem_reg_property[2];
307     int off;
308 
309     mem_reg_property[0] = cpu_to_be64(start);
310     mem_reg_property[1] = cpu_to_be64(size);
311 
312     sprintf(mem_name, "memory@%" HWADDR_PRIx, start);
313     off = fdt_add_subnode(fdt, 0, mem_name);
314     _FDT(off);
315     _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
316     _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
317                       sizeof(mem_reg_property))));
318     spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid);
319     return off;
320 }
321 
322 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
323 {
324     MemoryDeviceInfoList *info;
325 
326     for (info = list; info; info = info->next) {
327         MemoryDeviceInfo *value = info->value;
328 
329         if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
330             PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
331 
332             if (addr >= pcdimm_info->addr &&
333                 addr < (pcdimm_info->addr + pcdimm_info->size)) {
334                 return pcdimm_info->node;
335             }
336         }
337     }
338 
339     return -1;
340 }
341 
342 struct sPAPRDrconfCellV2 {
343      uint32_t seq_lmbs;
344      uint64_t base_addr;
345      uint32_t drc_index;
346      uint32_t aa_index;
347      uint32_t flags;
348 } QEMU_PACKED;
349 
350 typedef struct DrconfCellQueue {
351     struct sPAPRDrconfCellV2 cell;
352     QSIMPLEQ_ENTRY(DrconfCellQueue) entry;
353 } DrconfCellQueue;
354 
355 static DrconfCellQueue *
356 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr,
357                       uint32_t drc_index, uint32_t aa_index,
358                       uint32_t flags)
359 {
360     DrconfCellQueue *elem;
361 
362     elem = g_malloc0(sizeof(*elem));
363     elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs);
364     elem->cell.base_addr = cpu_to_be64(base_addr);
365     elem->cell.drc_index = cpu_to_be32(drc_index);
366     elem->cell.aa_index = cpu_to_be32(aa_index);
367     elem->cell.flags = cpu_to_be32(flags);
368 
369     return elem;
370 }
371 
372 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt,
373                                       int offset, MemoryDeviceInfoList *dimms)
374 {
375     MachineState *machine = MACHINE(spapr);
376     uint8_t *int_buf, *cur_index;
377     int ret;
378     uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
379     uint64_t addr, cur_addr, size;
380     uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size);
381     uint64_t mem_end = machine->device_memory->base +
382                        memory_region_size(&machine->device_memory->mr);
383     uint32_t node, buf_len, nr_entries = 0;
384     SpaprDrc *drc;
385     DrconfCellQueue *elem, *next;
386     MemoryDeviceInfoList *info;
387     QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue
388         = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue);
389 
390     /* Entry to cover RAM and the gap area */
391     elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1,
392                                  SPAPR_LMB_FLAGS_RESERVED |
393                                  SPAPR_LMB_FLAGS_DRC_INVALID);
394     QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
395     nr_entries++;
396 
397     cur_addr = machine->device_memory->base;
398     for (info = dimms; info; info = info->next) {
399         PCDIMMDeviceInfo *di = info->value->u.dimm.data;
400 
401         addr = di->addr;
402         size = di->size;
403         node = di->node;
404 
405         /*
406          * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The
407          * area is marked hotpluggable in the next iteration for the bigger
408          * chunk including the NVDIMM occupied area.
409          */
410         if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM)
411             continue;
412 
413         /* Entry for hot-pluggable area */
414         if (cur_addr < addr) {
415             drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
416             g_assert(drc);
417             elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size,
418                                          cur_addr, spapr_drc_index(drc), -1, 0);
419             QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
420             nr_entries++;
421         }
422 
423         /* Entry for DIMM */
424         drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size);
425         g_assert(drc);
426         elem = spapr_get_drconf_cell(size / lmb_size, addr,
427                                      spapr_drc_index(drc), node,
428                                      (SPAPR_LMB_FLAGS_ASSIGNED |
429                                       SPAPR_LMB_FLAGS_HOTREMOVABLE));
430         QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
431         nr_entries++;
432         cur_addr = addr + size;
433     }
434 
435     /* Entry for remaining hotpluggable area */
436     if (cur_addr < mem_end) {
437         drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
438         g_assert(drc);
439         elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size,
440                                      cur_addr, spapr_drc_index(drc), -1, 0);
441         QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
442         nr_entries++;
443     }
444 
445     buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t);
446     int_buf = cur_index = g_malloc0(buf_len);
447     *(uint32_t *)int_buf = cpu_to_be32(nr_entries);
448     cur_index += sizeof(nr_entries);
449 
450     QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) {
451         memcpy(cur_index, &elem->cell, sizeof(elem->cell));
452         cur_index += sizeof(elem->cell);
453         QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry);
454         g_free(elem);
455     }
456 
457     ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len);
458     g_free(int_buf);
459     if (ret < 0) {
460         return -1;
461     }
462     return 0;
463 }
464 
465 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt,
466                                    int offset, MemoryDeviceInfoList *dimms)
467 {
468     MachineState *machine = MACHINE(spapr);
469     int i, ret;
470     uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
471     uint32_t device_lmb_start = machine->device_memory->base / lmb_size;
472     uint32_t nr_lmbs = (machine->device_memory->base +
473                        memory_region_size(&machine->device_memory->mr)) /
474                        lmb_size;
475     uint32_t *int_buf, *cur_index, buf_len;
476 
477     /*
478      * Allocate enough buffer size to fit in ibm,dynamic-memory
479      */
480     buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t);
481     cur_index = int_buf = g_malloc0(buf_len);
482     int_buf[0] = cpu_to_be32(nr_lmbs);
483     cur_index++;
484     for (i = 0; i < nr_lmbs; i++) {
485         uint64_t addr = i * lmb_size;
486         uint32_t *dynamic_memory = cur_index;
487 
488         if (i >= device_lmb_start) {
489             SpaprDrc *drc;
490 
491             drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
492             g_assert(drc);
493 
494             dynamic_memory[0] = cpu_to_be32(addr >> 32);
495             dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
496             dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
497             dynamic_memory[3] = cpu_to_be32(0); /* reserved */
498             dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr));
499             if (memory_region_present(get_system_memory(), addr)) {
500                 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
501             } else {
502                 dynamic_memory[5] = cpu_to_be32(0);
503             }
504         } else {
505             /*
506              * LMB information for RMA, boot time RAM and gap b/n RAM and
507              * device memory region -- all these are marked as reserved
508              * and as having no valid DRC.
509              */
510             dynamic_memory[0] = cpu_to_be32(addr >> 32);
511             dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
512             dynamic_memory[2] = cpu_to_be32(0);
513             dynamic_memory[3] = cpu_to_be32(0); /* reserved */
514             dynamic_memory[4] = cpu_to_be32(-1);
515             dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
516                                             SPAPR_LMB_FLAGS_DRC_INVALID);
517         }
518 
519         cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
520     }
521     ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
522     g_free(int_buf);
523     if (ret < 0) {
524         return -1;
525     }
526     return 0;
527 }
528 
529 /*
530  * Adds ibm,dynamic-reconfiguration-memory node.
531  * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
532  * of this device tree node.
533  */
534 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr,
535                                                    void *fdt)
536 {
537     MachineState *machine = MACHINE(spapr);
538     int ret, offset;
539     uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
540     uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32),
541                                 cpu_to_be32(lmb_size & 0xffffffff)};
542     MemoryDeviceInfoList *dimms = NULL;
543 
544     /*
545      * Don't create the node if there is no device memory
546      */
547     if (machine->ram_size == machine->maxram_size) {
548         return 0;
549     }
550 
551     offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
552 
553     ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
554                     sizeof(prop_lmb_size));
555     if (ret < 0) {
556         return ret;
557     }
558 
559     ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
560     if (ret < 0) {
561         return ret;
562     }
563 
564     ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
565     if (ret < 0) {
566         return ret;
567     }
568 
569     /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
570     dimms = qmp_memory_device_list();
571     if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) {
572         ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms);
573     } else {
574         ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms);
575     }
576     qapi_free_MemoryDeviceInfoList(dimms);
577 
578     if (ret < 0) {
579         return ret;
580     }
581 
582     ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset);
583 
584     return ret;
585 }
586 
587 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt)
588 {
589     MachineState *machine = MACHINE(spapr);
590     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
591     hwaddr mem_start, node_size;
592     int i, nb_nodes = machine->numa_state->num_nodes;
593     NodeInfo *nodes = machine->numa_state->nodes;
594 
595     for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
596         if (!nodes[i].node_mem) {
597             continue;
598         }
599         if (mem_start >= machine->ram_size) {
600             node_size = 0;
601         } else {
602             node_size = nodes[i].node_mem;
603             if (node_size > machine->ram_size - mem_start) {
604                 node_size = machine->ram_size - mem_start;
605             }
606         }
607         if (!mem_start) {
608             /* spapr_machine_init() checks for rma_size <= node0_size
609              * already */
610             spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size);
611             mem_start += spapr->rma_size;
612             node_size -= spapr->rma_size;
613         }
614         for ( ; node_size; ) {
615             hwaddr sizetmp = pow2floor(node_size);
616 
617             /* mem_start != 0 here */
618             if (ctzl(mem_start) < ctzl(sizetmp)) {
619                 sizetmp = 1ULL << ctzl(mem_start);
620             }
621 
622             spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp);
623             node_size -= sizetmp;
624             mem_start += sizetmp;
625         }
626     }
627 
628     /* Generate ibm,dynamic-reconfiguration-memory node if required */
629     if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) {
630         int ret;
631 
632         g_assert(smc->dr_lmb_enabled);
633         ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt);
634         if (ret) {
635             return ret;
636         }
637     }
638 
639     return 0;
640 }
641 
642 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset,
643                          SpaprMachineState *spapr)
644 {
645     MachineState *ms = MACHINE(spapr);
646     PowerPCCPU *cpu = POWERPC_CPU(cs);
647     CPUPPCState *env = &cpu->env;
648     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
649     int index = spapr_get_vcpu_id(cpu);
650     uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
651                        0xffffffff, 0xffffffff};
652     uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
653         : SPAPR_TIMEBASE_FREQ;
654     uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
655     uint32_t page_sizes_prop[64];
656     size_t page_sizes_prop_size;
657     unsigned int smp_threads = ms->smp.threads;
658     uint32_t vcpus_per_socket = smp_threads * ms->smp.cores;
659     uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
660     int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
661     SpaprDrc *drc;
662     int drc_index;
663     uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
664     int i;
665 
666     drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
667     if (drc) {
668         drc_index = spapr_drc_index(drc);
669         _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
670     }
671 
672     _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
673     _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
674 
675     _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
676     _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
677                            env->dcache_line_size)));
678     _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
679                            env->dcache_line_size)));
680     _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
681                            env->icache_line_size)));
682     _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
683                            env->icache_line_size)));
684 
685     if (pcc->l1_dcache_size) {
686         _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
687                                pcc->l1_dcache_size)));
688     } else {
689         warn_report("Unknown L1 dcache size for cpu");
690     }
691     if (pcc->l1_icache_size) {
692         _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
693                                pcc->l1_icache_size)));
694     } else {
695         warn_report("Unknown L1 icache size for cpu");
696     }
697 
698     _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
699     _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
700     _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size)));
701     _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
702     _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
703     _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
704 
705     if (env->spr_cb[SPR_PURR].oea_read) {
706         _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1)));
707     }
708     if (env->spr_cb[SPR_SPURR].oea_read) {
709         _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1)));
710     }
711 
712     if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
713         _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
714                           segs, sizeof(segs))));
715     }
716 
717     /* Advertise VSX (vector extensions) if available
718      *   1               == VMX / Altivec available
719      *   2               == VSX available
720      *
721      * Only CPUs for which we create core types in spapr_cpu_core.c
722      * are possible, and all of those have VMX */
723     if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) {
724         _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
725     } else {
726         _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
727     }
728 
729     /* Advertise DFP (Decimal Floating Point) if available
730      *   0 / no property == no DFP
731      *   1               == DFP available */
732     if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) {
733         _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
734     }
735 
736     page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
737                                                       sizeof(page_sizes_prop));
738     if (page_sizes_prop_size) {
739         _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
740                           page_sizes_prop, page_sizes_prop_size)));
741     }
742 
743     spapr_dt_pa_features(spapr, cpu, fdt, offset);
744 
745     _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
746                            cs->cpu_index / vcpus_per_socket)));
747 
748     _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
749                       pft_size_prop, sizeof(pft_size_prop))));
750 
751     if (ms->numa_state->num_nodes > 1) {
752         _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu));
753     }
754 
755     _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
756 
757     if (pcc->radix_page_info) {
758         for (i = 0; i < pcc->radix_page_info->count; i++) {
759             radix_AP_encodings[i] =
760                 cpu_to_be32(pcc->radix_page_info->entries[i]);
761         }
762         _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
763                           radix_AP_encodings,
764                           pcc->radix_page_info->count *
765                           sizeof(radix_AP_encodings[0]))));
766     }
767 
768     /*
769      * We set this property to let the guest know that it can use the large
770      * decrementer and its width in bits.
771      */
772     if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF)
773         _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits",
774                               pcc->lrg_decr_bits)));
775 }
776 
777 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr)
778 {
779     CPUState **rev;
780     CPUState *cs;
781     int n_cpus;
782     int cpus_offset;
783     char *nodename;
784     int i;
785 
786     cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
787     _FDT(cpus_offset);
788     _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
789     _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
790 
791     /*
792      * We walk the CPUs in reverse order to ensure that CPU DT nodes
793      * created by fdt_add_subnode() end up in the right order in FDT
794      * for the guest kernel the enumerate the CPUs correctly.
795      *
796      * The CPU list cannot be traversed in reverse order, so we need
797      * to do extra work.
798      */
799     n_cpus = 0;
800     rev = NULL;
801     CPU_FOREACH(cs) {
802         rev = g_renew(CPUState *, rev, n_cpus + 1);
803         rev[n_cpus++] = cs;
804     }
805 
806     for (i = n_cpus - 1; i >= 0; i--) {
807         CPUState *cs = rev[i];
808         PowerPCCPU *cpu = POWERPC_CPU(cs);
809         int index = spapr_get_vcpu_id(cpu);
810         DeviceClass *dc = DEVICE_GET_CLASS(cs);
811         int offset;
812 
813         if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
814             continue;
815         }
816 
817         nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
818         offset = fdt_add_subnode(fdt, cpus_offset, nodename);
819         g_free(nodename);
820         _FDT(offset);
821         spapr_dt_cpu(cs, fdt, offset, spapr);
822     }
823 
824     g_free(rev);
825 }
826 
827 static int spapr_dt_rng(void *fdt)
828 {
829     int node;
830     int ret;
831 
832     node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities");
833     if (node <= 0) {
834         return -1;
835     }
836     ret = fdt_setprop_string(fdt, node, "device_type",
837                              "ibm,platform-facilities");
838     ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1);
839     ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0);
840 
841     node = fdt_add_subnode(fdt, node, "ibm,random-v1");
842     if (node <= 0) {
843         return -1;
844     }
845     ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random");
846 
847     return ret ? -1 : 0;
848 }
849 
850 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
851 {
852     MachineState *ms = MACHINE(spapr);
853     int rtas;
854     GString *hypertas = g_string_sized_new(256);
855     GString *qemu_hypertas = g_string_sized_new(256);
856     uint64_t max_device_addr = MACHINE(spapr)->device_memory->base +
857         memory_region_size(&MACHINE(spapr)->device_memory->mr);
858     uint32_t lrdr_capacity[] = {
859         cpu_to_be32(max_device_addr >> 32),
860         cpu_to_be32(max_device_addr & 0xffffffff),
861         cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32),
862         cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff),
863         cpu_to_be32(ms->smp.max_cpus / ms->smp.threads),
864     };
865 
866     _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
867 
868     /* hypertas */
869     add_str(hypertas, "hcall-pft");
870     add_str(hypertas, "hcall-term");
871     add_str(hypertas, "hcall-dabr");
872     add_str(hypertas, "hcall-interrupt");
873     add_str(hypertas, "hcall-tce");
874     add_str(hypertas, "hcall-vio");
875     add_str(hypertas, "hcall-splpar");
876     add_str(hypertas, "hcall-join");
877     add_str(hypertas, "hcall-bulk");
878     add_str(hypertas, "hcall-set-mode");
879     add_str(hypertas, "hcall-sprg0");
880     add_str(hypertas, "hcall-copy");
881     add_str(hypertas, "hcall-debug");
882     add_str(hypertas, "hcall-vphn");
883     add_str(qemu_hypertas, "hcall-memop1");
884 
885     if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
886         add_str(hypertas, "hcall-multi-tce");
887     }
888 
889     if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
890         add_str(hypertas, "hcall-hpt-resize");
891     }
892 
893     _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
894                      hypertas->str, hypertas->len));
895     g_string_free(hypertas, TRUE);
896     _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
897                      qemu_hypertas->str, qemu_hypertas->len));
898     g_string_free(qemu_hypertas, TRUE);
899 
900     spapr_numa_write_rtas_dt(spapr, fdt, rtas);
901 
902     /*
903      * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log,
904      * and 16 bytes per CPU for system reset error log plus an extra 8 bytes.
905      *
906      * The system reset requirements are driven by existing Linux and PowerVM
907      * implementation which (contrary to PAPR) saves r3 in the error log
908      * structure like machine check, so Linux expects to find the saved r3
909      * value at the address in r3 upon FWNMI-enabled sreset interrupt (and
910      * does not look at the error value).
911      *
912      * System reset interrupts are not subject to interlock like machine
913      * check, so this memory area could be corrupted if the sreset is
914      * interrupted by a machine check (or vice versa) if it was shared. To
915      * prevent this, system reset uses per-CPU areas for the sreset save
916      * area. A system reset that interrupts a system reset handler could
917      * still overwrite this area, but Linux doesn't try to recover in that
918      * case anyway.
919      *
920      * The extra 8 bytes is required because Linux's FWNMI error log check
921      * is off-by-one.
922      */
923     _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX +
924 			  ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t)));
925     _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
926                           RTAS_ERROR_LOG_MAX));
927     _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
928                           RTAS_EVENT_SCAN_RATE));
929 
930     g_assert(msi_nonbroken);
931     _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
932 
933     /*
934      * According to PAPR, rtas ibm,os-term does not guarantee a return
935      * back to the guest cpu.
936      *
937      * While an additional ibm,extended-os-term property indicates
938      * that rtas call return will always occur. Set this property.
939      */
940     _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
941 
942     _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
943                      lrdr_capacity, sizeof(lrdr_capacity)));
944 
945     spapr_dt_rtas_tokens(fdt, rtas);
946 }
947 
948 /*
949  * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
950  * and the XIVE features that the guest may request and thus the valid
951  * values for bytes 23..26 of option vector 5:
952  */
953 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt,
954                                           int chosen)
955 {
956     PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
957 
958     char val[2 * 4] = {
959         23, 0x00, /* XICS / XIVE mode */
960         24, 0x00, /* Hash/Radix, filled in below. */
961         25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
962         26, 0x40, /* Radix options: GTSE == yes. */
963     };
964 
965     if (spapr->irq->xics && spapr->irq->xive) {
966         val[1] = SPAPR_OV5_XIVE_BOTH;
967     } else if (spapr->irq->xive) {
968         val[1] = SPAPR_OV5_XIVE_EXPLOIT;
969     } else {
970         assert(spapr->irq->xics);
971         val[1] = SPAPR_OV5_XIVE_LEGACY;
972     }
973 
974     if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
975                           first_ppc_cpu->compat_pvr)) {
976         /*
977          * If we're in a pre POWER9 compat mode then the guest should
978          * do hash and use the legacy interrupt mode
979          */
980         val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */
981         val[3] = 0x00; /* Hash */
982     } else if (kvm_enabled()) {
983         if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
984             val[3] = 0x80; /* OV5_MMU_BOTH */
985         } else if (kvmppc_has_cap_mmu_radix()) {
986             val[3] = 0x40; /* OV5_MMU_RADIX_300 */
987         } else {
988             val[3] = 0x00; /* Hash */
989         }
990     } else {
991         /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
992         val[3] = 0xC0;
993     }
994     _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
995                      val, sizeof(val)));
996 }
997 
998 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset)
999 {
1000     MachineState *machine = MACHINE(spapr);
1001     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1002     int chosen;
1003 
1004     _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
1005 
1006     if (reset) {
1007         const char *boot_device = machine->boot_order;
1008         char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
1009         size_t cb = 0;
1010         char *bootlist = get_boot_devices_list(&cb);
1011 
1012         if (machine->kernel_cmdline && machine->kernel_cmdline[0]) {
1013             _FDT(fdt_setprop_string(fdt, chosen, "bootargs",
1014                                     machine->kernel_cmdline));
1015         }
1016 
1017         if (spapr->initrd_size) {
1018             _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
1019                                   spapr->initrd_base));
1020             _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
1021                                   spapr->initrd_base + spapr->initrd_size));
1022         }
1023 
1024         if (spapr->kernel_size) {
1025             uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr),
1026                                   cpu_to_be64(spapr->kernel_size) };
1027 
1028             _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
1029                          &kprop, sizeof(kprop)));
1030             if (spapr->kernel_le) {
1031                 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
1032             }
1033         }
1034         if (boot_menu) {
1035             _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
1036         }
1037         _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
1038         _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
1039         _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1040 
1041         if (cb && bootlist) {
1042             int i;
1043 
1044             for (i = 0; i < cb; i++) {
1045                 if (bootlist[i] == '\n') {
1046                     bootlist[i] = ' ';
1047                 }
1048             }
1049             _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1050         }
1051 
1052         if (boot_device && strlen(boot_device)) {
1053             _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1054         }
1055 
1056         if (!spapr->has_graphics && stdout_path) {
1057             /*
1058              * "linux,stdout-path" and "stdout" properties are
1059              * deprecated by linux kernel. New platforms should only
1060              * use the "stdout-path" property. Set the new property
1061              * and continue using older property to remain compatible
1062              * with the existing firmware.
1063              */
1064             _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1065             _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
1066         }
1067 
1068         /*
1069          * We can deal with BAR reallocation just fine, advertise it
1070          * to the guest
1071          */
1072         if (smc->linux_pci_probe) {
1073             _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0));
1074         }
1075 
1076         spapr_dt_ov5_platform_support(spapr, fdt, chosen);
1077 
1078         g_free(stdout_path);
1079         g_free(bootlist);
1080     }
1081 
1082     _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5"));
1083 }
1084 
1085 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt)
1086 {
1087     /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1088      * KVM to work under pHyp with some guest co-operation */
1089     int hypervisor;
1090     uint8_t hypercall[16];
1091 
1092     _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1093     /* indicate KVM hypercall interface */
1094     _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1095     if (kvmppc_has_cap_fixup_hcalls()) {
1096         /*
1097          * Older KVM versions with older guest kernels were broken
1098          * with the magic page, don't allow the guest to map it.
1099          */
1100         if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1101                                   sizeof(hypercall))) {
1102             _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1103                              hypercall, sizeof(hypercall)));
1104         }
1105     }
1106 }
1107 
1108 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space)
1109 {
1110     MachineState *machine = MACHINE(spapr);
1111     MachineClass *mc = MACHINE_GET_CLASS(machine);
1112     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1113     int ret;
1114     void *fdt;
1115     SpaprPhbState *phb;
1116     char *buf;
1117 
1118     fdt = g_malloc0(space);
1119     _FDT((fdt_create_empty_tree(fdt, space)));
1120 
1121     /* Root node */
1122     _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1123     _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1124     _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1125 
1126     /* Guest UUID & Name*/
1127     buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1128     _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1129     if (qemu_uuid_set) {
1130         _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1131     }
1132     g_free(buf);
1133 
1134     if (qemu_get_vm_name()) {
1135         _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1136                                 qemu_get_vm_name()));
1137     }
1138 
1139     /* Host Model & Serial Number */
1140     if (spapr->host_model) {
1141         _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model));
1142     } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) {
1143         _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1144         g_free(buf);
1145     }
1146 
1147     if (spapr->host_serial) {
1148         _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial));
1149     } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) {
1150         _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1151         g_free(buf);
1152     }
1153 
1154     _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1155     _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1156 
1157     /* /interrupt controller */
1158     spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC);
1159 
1160     ret = spapr_dt_memory(spapr, fdt);
1161     if (ret < 0) {
1162         error_report("couldn't setup memory nodes in fdt");
1163         exit(1);
1164     }
1165 
1166     /* /vdevice */
1167     spapr_dt_vdevice(spapr->vio_bus, fdt);
1168 
1169     if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1170         ret = spapr_dt_rng(fdt);
1171         if (ret < 0) {
1172             error_report("could not set up rng device in the fdt");
1173             exit(1);
1174         }
1175     }
1176 
1177     QLIST_FOREACH(phb, &spapr->phbs, list) {
1178         ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL);
1179         if (ret < 0) {
1180             error_report("couldn't setup PCI devices in fdt");
1181             exit(1);
1182         }
1183     }
1184 
1185     spapr_dt_cpus(fdt, spapr);
1186 
1187     if (smc->dr_lmb_enabled) {
1188         _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1189     }
1190 
1191     if (mc->has_hotpluggable_cpus) {
1192         int offset = fdt_path_offset(fdt, "/cpus");
1193         ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU);
1194         if (ret < 0) {
1195             error_report("Couldn't set up CPU DR device tree properties");
1196             exit(1);
1197         }
1198     }
1199 
1200     /* /event-sources */
1201     spapr_dt_events(spapr, fdt);
1202 
1203     /* /rtas */
1204     spapr_dt_rtas(spapr, fdt);
1205 
1206     /* /chosen */
1207     spapr_dt_chosen(spapr, fdt, reset);
1208 
1209     /* /hypervisor */
1210     if (kvm_enabled()) {
1211         spapr_dt_hypervisor(spapr, fdt);
1212     }
1213 
1214     /* Build memory reserve map */
1215     if (reset) {
1216         if (spapr->kernel_size) {
1217             _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr,
1218                                   spapr->kernel_size)));
1219         }
1220         if (spapr->initrd_size) {
1221             _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base,
1222                                   spapr->initrd_size)));
1223         }
1224     }
1225 
1226     if (smc->dr_phb_enabled) {
1227         ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB);
1228         if (ret < 0) {
1229             error_report("Couldn't set up PHB DR device tree properties");
1230             exit(1);
1231         }
1232     }
1233 
1234     /* NVDIMM devices */
1235     if (mc->nvdimm_supported) {
1236         spapr_dt_persistent_memory(spapr, fdt);
1237     }
1238 
1239     return fdt;
1240 }
1241 
1242 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1243 {
1244     SpaprMachineState *spapr = opaque;
1245 
1246     return (addr & 0x0fffffff) + spapr->kernel_addr;
1247 }
1248 
1249 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1250                                     PowerPCCPU *cpu)
1251 {
1252     CPUPPCState *env = &cpu->env;
1253 
1254     /* The TCG path should also be holding the BQL at this point */
1255     g_assert(qemu_mutex_iothread_locked());
1256 
1257     if (msr_pr) {
1258         hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1259         env->gpr[3] = H_PRIVILEGE;
1260     } else {
1261         env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1262     }
1263 }
1264 
1265 struct LPCRSyncState {
1266     target_ulong value;
1267     target_ulong mask;
1268 };
1269 
1270 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg)
1271 {
1272     struct LPCRSyncState *s = arg.host_ptr;
1273     PowerPCCPU *cpu = POWERPC_CPU(cs);
1274     CPUPPCState *env = &cpu->env;
1275     target_ulong lpcr;
1276 
1277     cpu_synchronize_state(cs);
1278     lpcr = env->spr[SPR_LPCR];
1279     lpcr &= ~s->mask;
1280     lpcr |= s->value;
1281     ppc_store_lpcr(cpu, lpcr);
1282 }
1283 
1284 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask)
1285 {
1286     CPUState *cs;
1287     struct LPCRSyncState s = {
1288         .value = value,
1289         .mask = mask
1290     };
1291     CPU_FOREACH(cs) {
1292         run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s));
1293     }
1294 }
1295 
1296 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry)
1297 {
1298     SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1299 
1300     /* Copy PATE1:GR into PATE0:HR */
1301     entry->dw0 = spapr->patb_entry & PATE0_HR;
1302     entry->dw1 = spapr->patb_entry;
1303 }
1304 
1305 #define HPTE(_table, _i)   (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1306 #define HPTE_VALID(_hpte)  (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1307 #define HPTE_DIRTY(_hpte)  (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1308 #define CLEAN_HPTE(_hpte)  ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1309 #define DIRTY_HPTE(_hpte)  ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1310 
1311 /*
1312  * Get the fd to access the kernel htab, re-opening it if necessary
1313  */
1314 static int get_htab_fd(SpaprMachineState *spapr)
1315 {
1316     Error *local_err = NULL;
1317 
1318     if (spapr->htab_fd >= 0) {
1319         return spapr->htab_fd;
1320     }
1321 
1322     spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
1323     if (spapr->htab_fd < 0) {
1324         error_report_err(local_err);
1325     }
1326 
1327     return spapr->htab_fd;
1328 }
1329 
1330 void close_htab_fd(SpaprMachineState *spapr)
1331 {
1332     if (spapr->htab_fd >= 0) {
1333         close(spapr->htab_fd);
1334     }
1335     spapr->htab_fd = -1;
1336 }
1337 
1338 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1339 {
1340     SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1341 
1342     return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1343 }
1344 
1345 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
1346 {
1347     SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1348 
1349     assert(kvm_enabled());
1350 
1351     if (!spapr->htab) {
1352         return 0;
1353     }
1354 
1355     return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18);
1356 }
1357 
1358 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1359                                                 hwaddr ptex, int n)
1360 {
1361     SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1362     hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1363 
1364     if (!spapr->htab) {
1365         /*
1366          * HTAB is controlled by KVM. Fetch into temporary buffer
1367          */
1368         ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1369         kvmppc_read_hptes(hptes, ptex, n);
1370         return hptes;
1371     }
1372 
1373     /*
1374      * HTAB is controlled by QEMU. Just point to the internally
1375      * accessible PTEG.
1376      */
1377     return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1378 }
1379 
1380 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1381                               const ppc_hash_pte64_t *hptes,
1382                               hwaddr ptex, int n)
1383 {
1384     SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1385 
1386     if (!spapr->htab) {
1387         g_free((void *)hptes);
1388     }
1389 
1390     /* Nothing to do for qemu managed HPT */
1391 }
1392 
1393 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
1394                       uint64_t pte0, uint64_t pte1)
1395 {
1396     SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp);
1397     hwaddr offset = ptex * HASH_PTE_SIZE_64;
1398 
1399     if (!spapr->htab) {
1400         kvmppc_write_hpte(ptex, pte0, pte1);
1401     } else {
1402         if (pte0 & HPTE64_V_VALID) {
1403             stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1404             /*
1405              * When setting valid, we write PTE1 first. This ensures
1406              * proper synchronization with the reading code in
1407              * ppc_hash64_pteg_search()
1408              */
1409             smp_wmb();
1410             stq_p(spapr->htab + offset, pte0);
1411         } else {
1412             stq_p(spapr->htab + offset, pte0);
1413             /*
1414              * When clearing it we set PTE0 first. This ensures proper
1415              * synchronization with the reading code in
1416              * ppc_hash64_pteg_search()
1417              */
1418             smp_wmb();
1419             stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1420         }
1421     }
1422 }
1423 
1424 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1425                              uint64_t pte1)
1426 {
1427     hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15;
1428     SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1429 
1430     if (!spapr->htab) {
1431         /* There should always be a hash table when this is called */
1432         error_report("spapr_hpte_set_c called with no hash table !");
1433         return;
1434     }
1435 
1436     /* The HW performs a non-atomic byte update */
1437     stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80);
1438 }
1439 
1440 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1441                              uint64_t pte1)
1442 {
1443     hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14;
1444     SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1445 
1446     if (!spapr->htab) {
1447         /* There should always be a hash table when this is called */
1448         error_report("spapr_hpte_set_r called with no hash table !");
1449         return;
1450     }
1451 
1452     /* The HW performs a non-atomic byte update */
1453     stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01);
1454 }
1455 
1456 int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1457 {
1458     int shift;
1459 
1460     /* We aim for a hash table of size 1/128 the size of RAM (rounded
1461      * up).  The PAPR recommendation is actually 1/64 of RAM size, but
1462      * that's much more than is needed for Linux guests */
1463     shift = ctz64(pow2ceil(ramsize)) - 7;
1464     shift = MAX(shift, 18); /* Minimum architected size */
1465     shift = MIN(shift, 46); /* Maximum architected size */
1466     return shift;
1467 }
1468 
1469 void spapr_free_hpt(SpaprMachineState *spapr)
1470 {
1471     g_free(spapr->htab);
1472     spapr->htab = NULL;
1473     spapr->htab_shift = 0;
1474     close_htab_fd(spapr);
1475 }
1476 
1477 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift,
1478                           Error **errp)
1479 {
1480     long rc;
1481 
1482     /* Clean up any HPT info from a previous boot */
1483     spapr_free_hpt(spapr);
1484 
1485     rc = kvmppc_reset_htab(shift);
1486     if (rc < 0) {
1487         /* kernel-side HPT needed, but couldn't allocate one */
1488         error_setg_errno(errp, errno,
1489                          "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1490                          shift);
1491         /* This is almost certainly fatal, but if the caller really
1492          * wants to carry on with shift == 0, it's welcome to try */
1493     } else if (rc > 0) {
1494         /* kernel-side HPT allocated */
1495         if (rc != shift) {
1496             error_setg(errp,
1497                        "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1498                        shift, rc);
1499         }
1500 
1501         spapr->htab_shift = shift;
1502         spapr->htab = NULL;
1503     } else {
1504         /* kernel-side HPT not needed, allocate in userspace instead */
1505         size_t size = 1ULL << shift;
1506         int i;
1507 
1508         spapr->htab = qemu_memalign(size, size);
1509         if (!spapr->htab) {
1510             error_setg_errno(errp, errno,
1511                              "Could not allocate HPT of order %d", shift);
1512             return;
1513         }
1514 
1515         memset(spapr->htab, 0, size);
1516         spapr->htab_shift = shift;
1517 
1518         for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1519             DIRTY_HPTE(HPTE(spapr->htab, i));
1520         }
1521     }
1522     /* We're setting up a hash table, so that means we're not radix */
1523     spapr->patb_entry = 0;
1524     spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT);
1525 }
1526 
1527 void spapr_setup_hpt(SpaprMachineState *spapr)
1528 {
1529     int hpt_shift;
1530 
1531     if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) {
1532         hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1533     } else {
1534         uint64_t current_ram_size;
1535 
1536         current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
1537         hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size);
1538     }
1539     spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1540 
1541     if (kvm_enabled()) {
1542         hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift);
1543 
1544         /* Check our RMA fits in the possible VRMA */
1545         if (vrma_limit < spapr->rma_size) {
1546             error_report("Unable to create %" HWADDR_PRIu
1547                          "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB",
1548                          spapr->rma_size / MiB, vrma_limit / MiB);
1549             exit(EXIT_FAILURE);
1550         }
1551     }
1552 }
1553 
1554 static int spapr_reset_drcs(Object *child, void *opaque)
1555 {
1556     SpaprDrc *drc =
1557         (SpaprDrc *) object_dynamic_cast(child,
1558                                                  TYPE_SPAPR_DR_CONNECTOR);
1559 
1560     if (drc) {
1561         spapr_drc_reset(drc);
1562     }
1563 
1564     return 0;
1565 }
1566 
1567 static void spapr_machine_reset(MachineState *machine)
1568 {
1569     SpaprMachineState *spapr = SPAPR_MACHINE(machine);
1570     PowerPCCPU *first_ppc_cpu;
1571     hwaddr fdt_addr;
1572     void *fdt;
1573     int rc;
1574 
1575     kvmppc_svm_off(&error_fatal);
1576     spapr_caps_apply(spapr);
1577 
1578     first_ppc_cpu = POWERPC_CPU(first_cpu);
1579     if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1580         ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
1581                               spapr->max_compat_pvr)) {
1582         /*
1583          * If using KVM with radix mode available, VCPUs can be started
1584          * without a HPT because KVM will start them in radix mode.
1585          * Set the GR bit in PATE so that we know there is no HPT.
1586          */
1587         spapr->patb_entry = PATE1_GR;
1588         spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT);
1589     } else {
1590         spapr_setup_hpt(spapr);
1591     }
1592 
1593     qemu_devices_reset();
1594 
1595     spapr_ovec_cleanup(spapr->ov5_cas);
1596     spapr->ov5_cas = spapr_ovec_new();
1597 
1598     ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
1599 
1600     /*
1601      * This is fixing some of the default configuration of the XIVE
1602      * devices. To be called after the reset of the machine devices.
1603      */
1604     spapr_irq_reset(spapr, &error_fatal);
1605 
1606     /*
1607      * There is no CAS under qtest. Simulate one to please the code that
1608      * depends on spapr->ov5_cas. This is especially needed to test device
1609      * unplug, so we do that before resetting the DRCs.
1610      */
1611     if (qtest_enabled()) {
1612         spapr_ovec_cleanup(spapr->ov5_cas);
1613         spapr->ov5_cas = spapr_ovec_clone(spapr->ov5);
1614     }
1615 
1616     /* DRC reset may cause a device to be unplugged. This will cause troubles
1617      * if this device is used by another device (eg, a running vhost backend
1618      * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1619      * situations, we reset DRCs after all devices have been reset.
1620      */
1621     object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL);
1622 
1623     spapr_clear_pending_events(spapr);
1624 
1625     /*
1626      * We place the device tree and RTAS just below either the top of the RMA,
1627      * or just below 2GB, whichever is lower, so that it can be
1628      * processed with 32-bit real mode code if necessary
1629      */
1630     fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE;
1631 
1632     fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE);
1633 
1634     rc = fdt_pack(fdt);
1635 
1636     /* Should only fail if we've built a corrupted tree */
1637     assert(rc == 0);
1638 
1639     /* Load the fdt */
1640     qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1641     cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1642     g_free(spapr->fdt_blob);
1643     spapr->fdt_size = fdt_totalsize(fdt);
1644     spapr->fdt_initial_size = spapr->fdt_size;
1645     spapr->fdt_blob = fdt;
1646 
1647     /* Set up the entry state */
1648     spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0);
1649     first_ppc_cpu->env.gpr[5] = 0;
1650 
1651     spapr->fwnmi_system_reset_addr = -1;
1652     spapr->fwnmi_machine_check_addr = -1;
1653     spapr->fwnmi_machine_check_interlock = -1;
1654 
1655     /* Signal all vCPUs waiting on this condition */
1656     qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond);
1657 
1658     migrate_del_blocker(spapr->fwnmi_migration_blocker);
1659 }
1660 
1661 static void spapr_create_nvram(SpaprMachineState *spapr)
1662 {
1663     DeviceState *dev = qdev_new("spapr-nvram");
1664     DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1665 
1666     if (dinfo) {
1667         qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo),
1668                                 &error_fatal);
1669     }
1670 
1671     qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal);
1672 
1673     spapr->nvram = (struct SpaprNvram *)dev;
1674 }
1675 
1676 static void spapr_rtc_create(SpaprMachineState *spapr)
1677 {
1678     object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc,
1679                                        sizeof(spapr->rtc), TYPE_SPAPR_RTC,
1680                                        &error_fatal, NULL);
1681     qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal);
1682     object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1683                               "date");
1684 }
1685 
1686 /* Returns whether we want to use VGA or not */
1687 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1688 {
1689     switch (vga_interface_type) {
1690     case VGA_NONE:
1691         return false;
1692     case VGA_DEVICE:
1693         return true;
1694     case VGA_STD:
1695     case VGA_VIRTIO:
1696     case VGA_CIRRUS:
1697         return pci_vga_init(pci_bus) != NULL;
1698     default:
1699         error_setg(errp,
1700                    "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1701         return false;
1702     }
1703 }
1704 
1705 static int spapr_pre_load(void *opaque)
1706 {
1707     int rc;
1708 
1709     rc = spapr_caps_pre_load(opaque);
1710     if (rc) {
1711         return rc;
1712     }
1713 
1714     return 0;
1715 }
1716 
1717 static int spapr_post_load(void *opaque, int version_id)
1718 {
1719     SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1720     int err = 0;
1721 
1722     err = spapr_caps_post_migration(spapr);
1723     if (err) {
1724         return err;
1725     }
1726 
1727     /*
1728      * In earlier versions, there was no separate qdev for the PAPR
1729      * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1730      * So when migrating from those versions, poke the incoming offset
1731      * value into the RTC device
1732      */
1733     if (version_id < 3) {
1734         err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1735         if (err) {
1736             return err;
1737         }
1738     }
1739 
1740     if (kvm_enabled() && spapr->patb_entry) {
1741         PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1742         bool radix = !!(spapr->patb_entry & PATE1_GR);
1743         bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1744 
1745         /*
1746          * Update LPCR:HR and UPRT as they may not be set properly in
1747          * the stream
1748          */
1749         spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0,
1750                             LPCR_HR | LPCR_UPRT);
1751 
1752         err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1753         if (err) {
1754             error_report("Process table config unsupported by the host");
1755             return -EINVAL;
1756         }
1757     }
1758 
1759     err = spapr_irq_post_load(spapr, version_id);
1760     if (err) {
1761         return err;
1762     }
1763 
1764     return err;
1765 }
1766 
1767 static int spapr_pre_save(void *opaque)
1768 {
1769     int rc;
1770 
1771     rc = spapr_caps_pre_save(opaque);
1772     if (rc) {
1773         return rc;
1774     }
1775 
1776     return 0;
1777 }
1778 
1779 static bool version_before_3(void *opaque, int version_id)
1780 {
1781     return version_id < 3;
1782 }
1783 
1784 static bool spapr_pending_events_needed(void *opaque)
1785 {
1786     SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1787     return !QTAILQ_EMPTY(&spapr->pending_events);
1788 }
1789 
1790 static const VMStateDescription vmstate_spapr_event_entry = {
1791     .name = "spapr_event_log_entry",
1792     .version_id = 1,
1793     .minimum_version_id = 1,
1794     .fields = (VMStateField[]) {
1795         VMSTATE_UINT32(summary, SpaprEventLogEntry),
1796         VMSTATE_UINT32(extended_length, SpaprEventLogEntry),
1797         VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0,
1798                                      NULL, extended_length),
1799         VMSTATE_END_OF_LIST()
1800     },
1801 };
1802 
1803 static const VMStateDescription vmstate_spapr_pending_events = {
1804     .name = "spapr_pending_events",
1805     .version_id = 1,
1806     .minimum_version_id = 1,
1807     .needed = spapr_pending_events_needed,
1808     .fields = (VMStateField[]) {
1809         VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1,
1810                          vmstate_spapr_event_entry, SpaprEventLogEntry, next),
1811         VMSTATE_END_OF_LIST()
1812     },
1813 };
1814 
1815 static bool spapr_ov5_cas_needed(void *opaque)
1816 {
1817     SpaprMachineState *spapr = opaque;
1818     SpaprOptionVector *ov5_mask = spapr_ovec_new();
1819     bool cas_needed;
1820 
1821     /* Prior to the introduction of SpaprOptionVector, we had two option
1822      * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1823      * Both of these options encode machine topology into the device-tree
1824      * in such a way that the now-booted OS should still be able to interact
1825      * appropriately with QEMU regardless of what options were actually
1826      * negotiatied on the source side.
1827      *
1828      * As such, we can avoid migrating the CAS-negotiated options if these
1829      * are the only options available on the current machine/platform.
1830      * Since these are the only options available for pseries-2.7 and
1831      * earlier, this allows us to maintain old->new/new->old migration
1832      * compatibility.
1833      *
1834      * For QEMU 2.8+, there are additional CAS-negotiatable options available
1835      * via default pseries-2.8 machines and explicit command-line parameters.
1836      * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1837      * of the actual CAS-negotiated values to continue working properly. For
1838      * example, availability of memory unplug depends on knowing whether
1839      * OV5_HP_EVT was negotiated via CAS.
1840      *
1841      * Thus, for any cases where the set of available CAS-negotiatable
1842      * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1843      * include the CAS-negotiated options in the migration stream, unless
1844      * if they affect boot time behaviour only.
1845      */
1846     spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1847     spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1848     spapr_ovec_set(ov5_mask, OV5_DRMEM_V2);
1849 
1850     /* We need extra information if we have any bits outside the mask
1851      * defined above */
1852     cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask);
1853 
1854     spapr_ovec_cleanup(ov5_mask);
1855 
1856     return cas_needed;
1857 }
1858 
1859 static const VMStateDescription vmstate_spapr_ov5_cas = {
1860     .name = "spapr_option_vector_ov5_cas",
1861     .version_id = 1,
1862     .minimum_version_id = 1,
1863     .needed = spapr_ov5_cas_needed,
1864     .fields = (VMStateField[]) {
1865         VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1,
1866                                  vmstate_spapr_ovec, SpaprOptionVector),
1867         VMSTATE_END_OF_LIST()
1868     },
1869 };
1870 
1871 static bool spapr_patb_entry_needed(void *opaque)
1872 {
1873     SpaprMachineState *spapr = opaque;
1874 
1875     return !!spapr->patb_entry;
1876 }
1877 
1878 static const VMStateDescription vmstate_spapr_patb_entry = {
1879     .name = "spapr_patb_entry",
1880     .version_id = 1,
1881     .minimum_version_id = 1,
1882     .needed = spapr_patb_entry_needed,
1883     .fields = (VMStateField[]) {
1884         VMSTATE_UINT64(patb_entry, SpaprMachineState),
1885         VMSTATE_END_OF_LIST()
1886     },
1887 };
1888 
1889 static bool spapr_irq_map_needed(void *opaque)
1890 {
1891     SpaprMachineState *spapr = opaque;
1892 
1893     return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr);
1894 }
1895 
1896 static const VMStateDescription vmstate_spapr_irq_map = {
1897     .name = "spapr_irq_map",
1898     .version_id = 1,
1899     .minimum_version_id = 1,
1900     .needed = spapr_irq_map_needed,
1901     .fields = (VMStateField[]) {
1902         VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr),
1903         VMSTATE_END_OF_LIST()
1904     },
1905 };
1906 
1907 static bool spapr_dtb_needed(void *opaque)
1908 {
1909     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque);
1910 
1911     return smc->update_dt_enabled;
1912 }
1913 
1914 static int spapr_dtb_pre_load(void *opaque)
1915 {
1916     SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1917 
1918     g_free(spapr->fdt_blob);
1919     spapr->fdt_blob = NULL;
1920     spapr->fdt_size = 0;
1921 
1922     return 0;
1923 }
1924 
1925 static const VMStateDescription vmstate_spapr_dtb = {
1926     .name = "spapr_dtb",
1927     .version_id = 1,
1928     .minimum_version_id = 1,
1929     .needed = spapr_dtb_needed,
1930     .pre_load = spapr_dtb_pre_load,
1931     .fields = (VMStateField[]) {
1932         VMSTATE_UINT32(fdt_initial_size, SpaprMachineState),
1933         VMSTATE_UINT32(fdt_size, SpaprMachineState),
1934         VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL,
1935                                      fdt_size),
1936         VMSTATE_END_OF_LIST()
1937     },
1938 };
1939 
1940 static bool spapr_fwnmi_needed(void *opaque)
1941 {
1942     SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1943 
1944     return spapr->fwnmi_machine_check_addr != -1;
1945 }
1946 
1947 static int spapr_fwnmi_pre_save(void *opaque)
1948 {
1949     SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1950 
1951     /*
1952      * Check if machine check handling is in progress and print a
1953      * warning message.
1954      */
1955     if (spapr->fwnmi_machine_check_interlock != -1) {
1956         warn_report("A machine check is being handled during migration. The"
1957                 "handler may run and log hardware error on the destination");
1958     }
1959 
1960     return 0;
1961 }
1962 
1963 static const VMStateDescription vmstate_spapr_fwnmi = {
1964     .name = "spapr_fwnmi",
1965     .version_id = 1,
1966     .minimum_version_id = 1,
1967     .needed = spapr_fwnmi_needed,
1968     .pre_save = spapr_fwnmi_pre_save,
1969     .fields = (VMStateField[]) {
1970         VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState),
1971         VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState),
1972         VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState),
1973         VMSTATE_END_OF_LIST()
1974     },
1975 };
1976 
1977 static const VMStateDescription vmstate_spapr = {
1978     .name = "spapr",
1979     .version_id = 3,
1980     .minimum_version_id = 1,
1981     .pre_load = spapr_pre_load,
1982     .post_load = spapr_post_load,
1983     .pre_save = spapr_pre_save,
1984     .fields = (VMStateField[]) {
1985         /* used to be @next_irq */
1986         VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1987 
1988         /* RTC offset */
1989         VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3),
1990 
1991         VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2),
1992         VMSTATE_END_OF_LIST()
1993     },
1994     .subsections = (const VMStateDescription*[]) {
1995         &vmstate_spapr_ov5_cas,
1996         &vmstate_spapr_patb_entry,
1997         &vmstate_spapr_pending_events,
1998         &vmstate_spapr_cap_htm,
1999         &vmstate_spapr_cap_vsx,
2000         &vmstate_spapr_cap_dfp,
2001         &vmstate_spapr_cap_cfpc,
2002         &vmstate_spapr_cap_sbbc,
2003         &vmstate_spapr_cap_ibs,
2004         &vmstate_spapr_cap_hpt_maxpagesize,
2005         &vmstate_spapr_irq_map,
2006         &vmstate_spapr_cap_nested_kvm_hv,
2007         &vmstate_spapr_dtb,
2008         &vmstate_spapr_cap_large_decr,
2009         &vmstate_spapr_cap_ccf_assist,
2010         &vmstate_spapr_cap_fwnmi,
2011         &vmstate_spapr_fwnmi,
2012         NULL
2013     }
2014 };
2015 
2016 static int htab_save_setup(QEMUFile *f, void *opaque)
2017 {
2018     SpaprMachineState *spapr = opaque;
2019 
2020     /* "Iteration" header */
2021     if (!spapr->htab_shift) {
2022         qemu_put_be32(f, -1);
2023     } else {
2024         qemu_put_be32(f, spapr->htab_shift);
2025     }
2026 
2027     if (spapr->htab) {
2028         spapr->htab_save_index = 0;
2029         spapr->htab_first_pass = true;
2030     } else {
2031         if (spapr->htab_shift) {
2032             assert(kvm_enabled());
2033         }
2034     }
2035 
2036 
2037     return 0;
2038 }
2039 
2040 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr,
2041                             int chunkstart, int n_valid, int n_invalid)
2042 {
2043     qemu_put_be32(f, chunkstart);
2044     qemu_put_be16(f, n_valid);
2045     qemu_put_be16(f, n_invalid);
2046     qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
2047                     HASH_PTE_SIZE_64 * n_valid);
2048 }
2049 
2050 static void htab_save_end_marker(QEMUFile *f)
2051 {
2052     qemu_put_be32(f, 0);
2053     qemu_put_be16(f, 0);
2054     qemu_put_be16(f, 0);
2055 }
2056 
2057 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr,
2058                                  int64_t max_ns)
2059 {
2060     bool has_timeout = max_ns != -1;
2061     int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2062     int index = spapr->htab_save_index;
2063     int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2064 
2065     assert(spapr->htab_first_pass);
2066 
2067     do {
2068         int chunkstart;
2069 
2070         /* Consume invalid HPTEs */
2071         while ((index < htabslots)
2072                && !HPTE_VALID(HPTE(spapr->htab, index))) {
2073             CLEAN_HPTE(HPTE(spapr->htab, index));
2074             index++;
2075         }
2076 
2077         /* Consume valid HPTEs */
2078         chunkstart = index;
2079         while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2080                && HPTE_VALID(HPTE(spapr->htab, index))) {
2081             CLEAN_HPTE(HPTE(spapr->htab, index));
2082             index++;
2083         }
2084 
2085         if (index > chunkstart) {
2086             int n_valid = index - chunkstart;
2087 
2088             htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
2089 
2090             if (has_timeout &&
2091                 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2092                 break;
2093             }
2094         }
2095     } while ((index < htabslots) && !qemu_file_rate_limit(f));
2096 
2097     if (index >= htabslots) {
2098         assert(index == htabslots);
2099         index = 0;
2100         spapr->htab_first_pass = false;
2101     }
2102     spapr->htab_save_index = index;
2103 }
2104 
2105 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr,
2106                                 int64_t max_ns)
2107 {
2108     bool final = max_ns < 0;
2109     int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2110     int examined = 0, sent = 0;
2111     int index = spapr->htab_save_index;
2112     int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2113 
2114     assert(!spapr->htab_first_pass);
2115 
2116     do {
2117         int chunkstart, invalidstart;
2118 
2119         /* Consume non-dirty HPTEs */
2120         while ((index < htabslots)
2121                && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
2122             index++;
2123             examined++;
2124         }
2125 
2126         chunkstart = index;
2127         /* Consume valid dirty HPTEs */
2128         while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2129                && HPTE_DIRTY(HPTE(spapr->htab, index))
2130                && HPTE_VALID(HPTE(spapr->htab, index))) {
2131             CLEAN_HPTE(HPTE(spapr->htab, index));
2132             index++;
2133             examined++;
2134         }
2135 
2136         invalidstart = index;
2137         /* Consume invalid dirty HPTEs */
2138         while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
2139                && HPTE_DIRTY(HPTE(spapr->htab, index))
2140                && !HPTE_VALID(HPTE(spapr->htab, index))) {
2141             CLEAN_HPTE(HPTE(spapr->htab, index));
2142             index++;
2143             examined++;
2144         }
2145 
2146         if (index > chunkstart) {
2147             int n_valid = invalidstart - chunkstart;
2148             int n_invalid = index - invalidstart;
2149 
2150             htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
2151             sent += index - chunkstart;
2152 
2153             if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2154                 break;
2155             }
2156         }
2157 
2158         if (examined >= htabslots) {
2159             break;
2160         }
2161 
2162         if (index >= htabslots) {
2163             assert(index == htabslots);
2164             index = 0;
2165         }
2166     } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
2167 
2168     if (index >= htabslots) {
2169         assert(index == htabslots);
2170         index = 0;
2171     }
2172 
2173     spapr->htab_save_index = index;
2174 
2175     return (examined >= htabslots) && (sent == 0) ? 1 : 0;
2176 }
2177 
2178 #define MAX_ITERATION_NS    5000000 /* 5 ms */
2179 #define MAX_KVM_BUF_SIZE    2048
2180 
2181 static int htab_save_iterate(QEMUFile *f, void *opaque)
2182 {
2183     SpaprMachineState *spapr = opaque;
2184     int fd;
2185     int rc = 0;
2186 
2187     /* Iteration header */
2188     if (!spapr->htab_shift) {
2189         qemu_put_be32(f, -1);
2190         return 1;
2191     } else {
2192         qemu_put_be32(f, 0);
2193     }
2194 
2195     if (!spapr->htab) {
2196         assert(kvm_enabled());
2197 
2198         fd = get_htab_fd(spapr);
2199         if (fd < 0) {
2200             return fd;
2201         }
2202 
2203         rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
2204         if (rc < 0) {
2205             return rc;
2206         }
2207     } else  if (spapr->htab_first_pass) {
2208         htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
2209     } else {
2210         rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
2211     }
2212 
2213     htab_save_end_marker(f);
2214 
2215     return rc;
2216 }
2217 
2218 static int htab_save_complete(QEMUFile *f, void *opaque)
2219 {
2220     SpaprMachineState *spapr = opaque;
2221     int fd;
2222 
2223     /* Iteration header */
2224     if (!spapr->htab_shift) {
2225         qemu_put_be32(f, -1);
2226         return 0;
2227     } else {
2228         qemu_put_be32(f, 0);
2229     }
2230 
2231     if (!spapr->htab) {
2232         int rc;
2233 
2234         assert(kvm_enabled());
2235 
2236         fd = get_htab_fd(spapr);
2237         if (fd < 0) {
2238             return fd;
2239         }
2240 
2241         rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
2242         if (rc < 0) {
2243             return rc;
2244         }
2245     } else {
2246         if (spapr->htab_first_pass) {
2247             htab_save_first_pass(f, spapr, -1);
2248         }
2249         htab_save_later_pass(f, spapr, -1);
2250     }
2251 
2252     /* End marker */
2253     htab_save_end_marker(f);
2254 
2255     return 0;
2256 }
2257 
2258 static int htab_load(QEMUFile *f, void *opaque, int version_id)
2259 {
2260     SpaprMachineState *spapr = opaque;
2261     uint32_t section_hdr;
2262     int fd = -1;
2263     Error *local_err = NULL;
2264 
2265     if (version_id < 1 || version_id > 1) {
2266         error_report("htab_load() bad version");
2267         return -EINVAL;
2268     }
2269 
2270     section_hdr = qemu_get_be32(f);
2271 
2272     if (section_hdr == -1) {
2273         spapr_free_hpt(spapr);
2274         return 0;
2275     }
2276 
2277     if (section_hdr) {
2278         /* First section gives the htab size */
2279         spapr_reallocate_hpt(spapr, section_hdr, &local_err);
2280         if (local_err) {
2281             error_report_err(local_err);
2282             return -EINVAL;
2283         }
2284         return 0;
2285     }
2286 
2287     if (!spapr->htab) {
2288         assert(kvm_enabled());
2289 
2290         fd = kvmppc_get_htab_fd(true, 0, &local_err);
2291         if (fd < 0) {
2292             error_report_err(local_err);
2293             return fd;
2294         }
2295     }
2296 
2297     while (true) {
2298         uint32_t index;
2299         uint16_t n_valid, n_invalid;
2300 
2301         index = qemu_get_be32(f);
2302         n_valid = qemu_get_be16(f);
2303         n_invalid = qemu_get_be16(f);
2304 
2305         if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
2306             /* End of Stream */
2307             break;
2308         }
2309 
2310         if ((index + n_valid + n_invalid) >
2311             (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2312             /* Bad index in stream */
2313             error_report(
2314                 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2315                 index, n_valid, n_invalid, spapr->htab_shift);
2316             return -EINVAL;
2317         }
2318 
2319         if (spapr->htab) {
2320             if (n_valid) {
2321                 qemu_get_buffer(f, HPTE(spapr->htab, index),
2322                                 HASH_PTE_SIZE_64 * n_valid);
2323             }
2324             if (n_invalid) {
2325                 memset(HPTE(spapr->htab, index + n_valid), 0,
2326                        HASH_PTE_SIZE_64 * n_invalid);
2327             }
2328         } else {
2329             int rc;
2330 
2331             assert(fd >= 0);
2332 
2333             rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2334             if (rc < 0) {
2335                 return rc;
2336             }
2337         }
2338     }
2339 
2340     if (!spapr->htab) {
2341         assert(fd >= 0);
2342         close(fd);
2343     }
2344 
2345     return 0;
2346 }
2347 
2348 static void htab_save_cleanup(void *opaque)
2349 {
2350     SpaprMachineState *spapr = opaque;
2351 
2352     close_htab_fd(spapr);
2353 }
2354 
2355 static SaveVMHandlers savevm_htab_handlers = {
2356     .save_setup = htab_save_setup,
2357     .save_live_iterate = htab_save_iterate,
2358     .save_live_complete_precopy = htab_save_complete,
2359     .save_cleanup = htab_save_cleanup,
2360     .load_state = htab_load,
2361 };
2362 
2363 static void spapr_boot_set(void *opaque, const char *boot_device,
2364                            Error **errp)
2365 {
2366     MachineState *machine = MACHINE(opaque);
2367     machine->boot_order = g_strdup(boot_device);
2368 }
2369 
2370 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr)
2371 {
2372     MachineState *machine = MACHINE(spapr);
2373     uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2374     uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2375     int i;
2376 
2377     for (i = 0; i < nr_lmbs; i++) {
2378         uint64_t addr;
2379 
2380         addr = i * lmb_size + machine->device_memory->base;
2381         spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2382                                addr / lmb_size);
2383     }
2384 }
2385 
2386 /*
2387  * If RAM size, maxmem size and individual node mem sizes aren't aligned
2388  * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2389  * since we can't support such unaligned sizes with DRCONF_MEMORY.
2390  */
2391 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2392 {
2393     int i;
2394 
2395     if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2396         error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2397                    " is not aligned to %" PRIu64 " MiB",
2398                    machine->ram_size,
2399                    SPAPR_MEMORY_BLOCK_SIZE / MiB);
2400         return;
2401     }
2402 
2403     if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2404         error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2405                    " is not aligned to %" PRIu64 " MiB",
2406                    machine->ram_size,
2407                    SPAPR_MEMORY_BLOCK_SIZE / MiB);
2408         return;
2409     }
2410 
2411     for (i = 0; i < machine->numa_state->num_nodes; i++) {
2412         if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2413             error_setg(errp,
2414                        "Node %d memory size 0x%" PRIx64
2415                        " is not aligned to %" PRIu64 " MiB",
2416                        i, machine->numa_state->nodes[i].node_mem,
2417                        SPAPR_MEMORY_BLOCK_SIZE / MiB);
2418             return;
2419         }
2420     }
2421 }
2422 
2423 /* find cpu slot in machine->possible_cpus by core_id */
2424 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2425 {
2426     int index = id / ms->smp.threads;
2427 
2428     if (index >= ms->possible_cpus->len) {
2429         return NULL;
2430     }
2431     if (idx) {
2432         *idx = index;
2433     }
2434     return &ms->possible_cpus->cpus[index];
2435 }
2436 
2437 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp)
2438 {
2439     MachineState *ms = MACHINE(spapr);
2440     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
2441     Error *local_err = NULL;
2442     bool vsmt_user = !!spapr->vsmt;
2443     int kvm_smt = kvmppc_smt_threads();
2444     int ret;
2445     unsigned int smp_threads = ms->smp.threads;
2446 
2447     if (!kvm_enabled() && (smp_threads > 1)) {
2448         error_setg(errp, "TCG cannot support more than 1 thread/core "
2449                    "on a pseries machine");
2450         return;
2451     }
2452     if (!is_power_of_2(smp_threads)) {
2453         error_setg(errp, "Cannot support %d threads/core on a pseries "
2454                    "machine because it must be a power of 2", smp_threads);
2455         return;
2456     }
2457 
2458     /* Detemine the VSMT mode to use: */
2459     if (vsmt_user) {
2460         if (spapr->vsmt < smp_threads) {
2461             error_setg(errp, "Cannot support VSMT mode %d"
2462                        " because it must be >= threads/core (%d)",
2463                        spapr->vsmt, smp_threads);
2464             return;
2465         }
2466         /* In this case, spapr->vsmt has been set by the command line */
2467     } else if (!smc->smp_threads_vsmt) {
2468         /*
2469          * Default VSMT value is tricky, because we need it to be as
2470          * consistent as possible (for migration), but this requires
2471          * changing it for at least some existing cases.  We pick 8 as
2472          * the value that we'd get with KVM on POWER8, the
2473          * overwhelmingly common case in production systems.
2474          */
2475         spapr->vsmt = MAX(8, smp_threads);
2476     } else {
2477         spapr->vsmt = smp_threads;
2478     }
2479 
2480     /* KVM: If necessary, set the SMT mode: */
2481     if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2482         ret = kvmppc_set_smt_threads(spapr->vsmt);
2483         if (ret) {
2484             /* Looks like KVM isn't able to change VSMT mode */
2485             error_setg(&local_err,
2486                        "Failed to set KVM's VSMT mode to %d (errno %d)",
2487                        spapr->vsmt, ret);
2488             /* We can live with that if the default one is big enough
2489              * for the number of threads, and a submultiple of the one
2490              * we want.  In this case we'll waste some vcpu ids, but
2491              * behaviour will be correct */
2492             if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) {
2493                 warn_report_err(local_err);
2494             } else {
2495                 if (!vsmt_user) {
2496                     error_append_hint(&local_err,
2497                                       "On PPC, a VM with %d threads/core"
2498                                       " on a host with %d threads/core"
2499                                       " requires the use of VSMT mode %d.\n",
2500                                       smp_threads, kvm_smt, spapr->vsmt);
2501                 }
2502                 kvmppc_error_append_smt_possible_hint(&local_err);
2503                 error_propagate(errp, local_err);
2504             }
2505         }
2506     }
2507     /* else TCG: nothing to do currently */
2508 }
2509 
2510 static void spapr_init_cpus(SpaprMachineState *spapr)
2511 {
2512     MachineState *machine = MACHINE(spapr);
2513     MachineClass *mc = MACHINE_GET_CLASS(machine);
2514     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2515     const char *type = spapr_get_cpu_core_type(machine->cpu_type);
2516     const CPUArchIdList *possible_cpus;
2517     unsigned int smp_cpus = machine->smp.cpus;
2518     unsigned int smp_threads = machine->smp.threads;
2519     unsigned int max_cpus = machine->smp.max_cpus;
2520     int boot_cores_nr = smp_cpus / smp_threads;
2521     int i;
2522 
2523     possible_cpus = mc->possible_cpu_arch_ids(machine);
2524     if (mc->has_hotpluggable_cpus) {
2525         if (smp_cpus % smp_threads) {
2526             error_report("smp_cpus (%u) must be multiple of threads (%u)",
2527                          smp_cpus, smp_threads);
2528             exit(1);
2529         }
2530         if (max_cpus % smp_threads) {
2531             error_report("max_cpus (%u) must be multiple of threads (%u)",
2532                          max_cpus, smp_threads);
2533             exit(1);
2534         }
2535     } else {
2536         if (max_cpus != smp_cpus) {
2537             error_report("This machine version does not support CPU hotplug");
2538             exit(1);
2539         }
2540         boot_cores_nr = possible_cpus->len;
2541     }
2542 
2543     if (smc->pre_2_10_has_unused_icps) {
2544         int i;
2545 
2546         for (i = 0; i < spapr_max_server_number(spapr); i++) {
2547             /* Dummy entries get deregistered when real ICPState objects
2548              * are registered during CPU core hotplug.
2549              */
2550             pre_2_10_vmstate_register_dummy_icp(i);
2551         }
2552     }
2553 
2554     for (i = 0; i < possible_cpus->len; i++) {
2555         int core_id = i * smp_threads;
2556 
2557         if (mc->has_hotpluggable_cpus) {
2558             spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2559                                    spapr_vcpu_id(spapr, core_id));
2560         }
2561 
2562         if (i < boot_cores_nr) {
2563             Object *core  = object_new(type);
2564             int nr_threads = smp_threads;
2565 
2566             /* Handle the partially filled core for older machine types */
2567             if ((i + 1) * smp_threads >= smp_cpus) {
2568                 nr_threads = smp_cpus - i * smp_threads;
2569             }
2570 
2571             object_property_set_int(core, "nr-threads", nr_threads,
2572                                     &error_fatal);
2573             object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id,
2574                                     &error_fatal);
2575             qdev_realize(DEVICE(core), NULL, &error_fatal);
2576 
2577             object_unref(core);
2578         }
2579     }
2580 }
2581 
2582 static PCIHostState *spapr_create_default_phb(void)
2583 {
2584     DeviceState *dev;
2585 
2586     dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE);
2587     qdev_prop_set_uint32(dev, "index", 0);
2588     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
2589 
2590     return PCI_HOST_BRIDGE(dev);
2591 }
2592 
2593 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp)
2594 {
2595     MachineState *machine = MACHINE(spapr);
2596     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
2597     hwaddr rma_size = machine->ram_size;
2598     hwaddr node0_size = spapr_node0_size(machine);
2599 
2600     /* RMA has to fit in the first NUMA node */
2601     rma_size = MIN(rma_size, node0_size);
2602 
2603     /*
2604      * VRMA access is via a special 1TiB SLB mapping, so the RMA can
2605      * never exceed that
2606      */
2607     rma_size = MIN(rma_size, 1 * TiB);
2608 
2609     /*
2610      * Clamp the RMA size based on machine type.  This is for
2611      * migration compatibility with older qemu versions, which limited
2612      * the RMA size for complicated and mostly bad reasons.
2613      */
2614     if (smc->rma_limit) {
2615         rma_size = MIN(rma_size, smc->rma_limit);
2616     }
2617 
2618     if (rma_size < MIN_RMA_SLOF) {
2619         error_setg(errp,
2620                    "pSeries SLOF firmware requires >= %" HWADDR_PRIx
2621                    "ldMiB guest RMA (Real Mode Area memory)",
2622                    MIN_RMA_SLOF / MiB);
2623         return 0;
2624     }
2625 
2626     return rma_size;
2627 }
2628 
2629 /* pSeries LPAR / sPAPR hardware init */
2630 static void spapr_machine_init(MachineState *machine)
2631 {
2632     SpaprMachineState *spapr = SPAPR_MACHINE(machine);
2633     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2634     MachineClass *mc = MACHINE_GET_CLASS(machine);
2635     const char *kernel_filename = machine->kernel_filename;
2636     const char *initrd_filename = machine->initrd_filename;
2637     PCIHostState *phb;
2638     int i;
2639     MemoryRegion *sysmem = get_system_memory();
2640     long load_limit, fw_size;
2641     char *filename;
2642     Error *resize_hpt_err = NULL;
2643 
2644     msi_nonbroken = true;
2645 
2646     QLIST_INIT(&spapr->phbs);
2647     QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2648 
2649     /* Determine capabilities to run with */
2650     spapr_caps_init(spapr);
2651 
2652     kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2653     if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2654         /*
2655          * If the user explicitly requested a mode we should either
2656          * supply it, or fail completely (which we do below).  But if
2657          * it's not set explicitly, we reset our mode to something
2658          * that works
2659          */
2660         if (resize_hpt_err) {
2661             spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2662             error_free(resize_hpt_err);
2663             resize_hpt_err = NULL;
2664         } else {
2665             spapr->resize_hpt = smc->resize_hpt_default;
2666         }
2667     }
2668 
2669     assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2670 
2671     if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2672         /*
2673          * User requested HPT resize, but this host can't supply it.  Bail out
2674          */
2675         error_report_err(resize_hpt_err);
2676         exit(1);
2677     }
2678     error_free(resize_hpt_err);
2679 
2680     spapr->rma_size = spapr_rma_size(spapr, &error_fatal);
2681 
2682     /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2683     load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2684 
2685     /*
2686      * VSMT must be set in order to be able to compute VCPU ids, ie to
2687      * call spapr_max_server_number() or spapr_vcpu_id().
2688      */
2689     spapr_set_vsmt_mode(spapr, &error_fatal);
2690 
2691     /* Set up Interrupt Controller before we create the VCPUs */
2692     spapr_irq_init(spapr, &error_fatal);
2693 
2694     /* Set up containers for ibm,client-architecture-support negotiated options
2695      */
2696     spapr->ov5 = spapr_ovec_new();
2697     spapr->ov5_cas = spapr_ovec_new();
2698 
2699     if (smc->dr_lmb_enabled) {
2700         spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2701         spapr_validate_node_memory(machine, &error_fatal);
2702     }
2703 
2704     spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2705 
2706     /* advertise support for dedicated HP event source to guests */
2707     if (spapr->use_hotplug_event_source) {
2708         spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2709     }
2710 
2711     /* advertise support for HPT resizing */
2712     if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2713         spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2714     }
2715 
2716     /* advertise support for ibm,dyamic-memory-v2 */
2717     spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2);
2718 
2719     /* advertise XIVE on POWER9 machines */
2720     if (spapr->irq->xive) {
2721         spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT);
2722     }
2723 
2724     /* init CPUs */
2725     spapr_init_cpus(spapr);
2726 
2727     /*
2728      * check we don't have a memory-less/cpu-less NUMA node
2729      * Firmware relies on the existing memory/cpu topology to provide the
2730      * NUMA topology to the kernel.
2731      * And the linux kernel needs to know the NUMA topology at start
2732      * to be able to hotplug CPUs later.
2733      */
2734     if (machine->numa_state->num_nodes) {
2735         for (i = 0; i < machine->numa_state->num_nodes; ++i) {
2736             /* check for memory-less node */
2737             if (machine->numa_state->nodes[i].node_mem == 0) {
2738                 CPUState *cs;
2739                 int found = 0;
2740                 /* check for cpu-less node */
2741                 CPU_FOREACH(cs) {
2742                     PowerPCCPU *cpu = POWERPC_CPU(cs);
2743                     if (cpu->node_id == i) {
2744                         found = 1;
2745                         break;
2746                     }
2747                 }
2748                 /* memory-less and cpu-less node */
2749                 if (!found) {
2750                     error_report(
2751                        "Memory-less/cpu-less nodes are not supported (node %d)",
2752                                  i);
2753                     exit(1);
2754                 }
2755             }
2756         }
2757 
2758     }
2759 
2760     /*
2761      * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
2762      * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
2763      * called from vPHB reset handler so we initialize the counter here.
2764      * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM
2765      * must be equally distant from any other node.
2766      * The final value of spapr->gpu_numa_id is going to be written to
2767      * max-associativity-domains in spapr_build_fdt().
2768      */
2769     spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes);
2770 
2771     /* Init numa_assoc_array */
2772     spapr_numa_associativity_init(spapr, machine);
2773 
2774     if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2775         ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
2776                               spapr->max_compat_pvr)) {
2777         spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300);
2778         /* KVM and TCG always allow GTSE with radix... */
2779         spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2780     }
2781     /* ... but not with hash (currently). */
2782 
2783     if (kvm_enabled()) {
2784         /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2785         kvmppc_enable_logical_ci_hcalls();
2786         kvmppc_enable_set_mode_hcall();
2787 
2788         /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2789         kvmppc_enable_clear_ref_mod_hcalls();
2790 
2791         /* Enable H_PAGE_INIT */
2792         kvmppc_enable_h_page_init();
2793     }
2794 
2795     /* map RAM */
2796     memory_region_add_subregion(sysmem, 0, machine->ram);
2797 
2798     /* always allocate the device memory information */
2799     machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
2800 
2801     /* initialize hotplug memory address space */
2802     if (machine->ram_size < machine->maxram_size) {
2803         ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
2804         /*
2805          * Limit the number of hotpluggable memory slots to half the number
2806          * slots that KVM supports, leaving the other half for PCI and other
2807          * devices. However ensure that number of slots doesn't drop below 32.
2808          */
2809         int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2810                            SPAPR_MAX_RAM_SLOTS;
2811 
2812         if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2813             max_memslots = SPAPR_MAX_RAM_SLOTS;
2814         }
2815         if (machine->ram_slots > max_memslots) {
2816             error_report("Specified number of memory slots %"
2817                          PRIu64" exceeds max supported %d",
2818                          machine->ram_slots, max_memslots);
2819             exit(1);
2820         }
2821 
2822         machine->device_memory->base = ROUND_UP(machine->ram_size,
2823                                                 SPAPR_DEVICE_MEM_ALIGN);
2824         memory_region_init(&machine->device_memory->mr, OBJECT(spapr),
2825                            "device-memory", device_mem_size);
2826         memory_region_add_subregion(sysmem, machine->device_memory->base,
2827                                     &machine->device_memory->mr);
2828     }
2829 
2830     if (smc->dr_lmb_enabled) {
2831         spapr_create_lmb_dr_connectors(spapr);
2832     }
2833 
2834     if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) {
2835         /* Create the error string for live migration blocker */
2836         error_setg(&spapr->fwnmi_migration_blocker,
2837             "A machine check is being handled during migration. The handler"
2838             "may run and log hardware error on the destination");
2839     }
2840 
2841     if (mc->nvdimm_supported) {
2842         spapr_create_nvdimm_dr_connectors(spapr);
2843     }
2844 
2845     /* Set up RTAS event infrastructure */
2846     spapr_events_init(spapr);
2847 
2848     /* Set up the RTC RTAS interfaces */
2849     spapr_rtc_create(spapr);
2850 
2851     /* Set up VIO bus */
2852     spapr->vio_bus = spapr_vio_bus_init();
2853 
2854     for (i = 0; i < serial_max_hds(); i++) {
2855         if (serial_hd(i)) {
2856             spapr_vty_create(spapr->vio_bus, serial_hd(i));
2857         }
2858     }
2859 
2860     /* We always have at least the nvram device on VIO */
2861     spapr_create_nvram(spapr);
2862 
2863     /*
2864      * Setup hotplug / dynamic-reconfiguration connectors. top-level
2865      * connectors (described in root DT node's "ibm,drc-types" property)
2866      * are pre-initialized here. additional child connectors (such as
2867      * connectors for a PHBs PCI slots) are added as needed during their
2868      * parent's realization.
2869      */
2870     if (smc->dr_phb_enabled) {
2871         for (i = 0; i < SPAPR_MAX_PHBS; i++) {
2872             spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i);
2873         }
2874     }
2875 
2876     /* Set up PCI */
2877     spapr_pci_rtas_init();
2878 
2879     phb = spapr_create_default_phb();
2880 
2881     for (i = 0; i < nb_nics; i++) {
2882         NICInfo *nd = &nd_table[i];
2883 
2884         if (!nd->model) {
2885             nd->model = g_strdup("spapr-vlan");
2886         }
2887 
2888         if (g_str_equal(nd->model, "spapr-vlan") ||
2889             g_str_equal(nd->model, "ibmveth")) {
2890             spapr_vlan_create(spapr->vio_bus, nd);
2891         } else {
2892             pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2893         }
2894     }
2895 
2896     for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2897         spapr_vscsi_create(spapr->vio_bus);
2898     }
2899 
2900     /* Graphics */
2901     if (spapr_vga_init(phb->bus, &error_fatal)) {
2902         spapr->has_graphics = true;
2903         machine->usb |= defaults_enabled() && !machine->usb_disabled;
2904     }
2905 
2906     if (machine->usb) {
2907         if (smc->use_ohci_by_default) {
2908             pci_create_simple(phb->bus, -1, "pci-ohci");
2909         } else {
2910             pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2911         }
2912 
2913         if (spapr->has_graphics) {
2914             USBBus *usb_bus = usb_bus_find(-1);
2915 
2916             usb_create_simple(usb_bus, "usb-kbd");
2917             usb_create_simple(usb_bus, "usb-mouse");
2918         }
2919     }
2920 
2921     if (kernel_filename) {
2922         spapr->kernel_size = load_elf(kernel_filename, NULL,
2923                                       translate_kernel_address, spapr,
2924                                       NULL, NULL, NULL, NULL, 1,
2925                                       PPC_ELF_MACHINE, 0, 0);
2926         if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2927             spapr->kernel_size = load_elf(kernel_filename, NULL,
2928                                           translate_kernel_address, spapr,
2929                                           NULL, NULL, NULL, NULL, 0,
2930                                           PPC_ELF_MACHINE, 0, 0);
2931             spapr->kernel_le = spapr->kernel_size > 0;
2932         }
2933         if (spapr->kernel_size < 0) {
2934             error_report("error loading %s: %s", kernel_filename,
2935                          load_elf_strerror(spapr->kernel_size));
2936             exit(1);
2937         }
2938 
2939         /* load initrd */
2940         if (initrd_filename) {
2941             /* Try to locate the initrd in the gap between the kernel
2942              * and the firmware. Add a bit of space just in case
2943              */
2944             spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size
2945                                   + 0x1ffff) & ~0xffff;
2946             spapr->initrd_size = load_image_targphys(initrd_filename,
2947                                                      spapr->initrd_base,
2948                                                      load_limit
2949                                                      - spapr->initrd_base);
2950             if (spapr->initrd_size < 0) {
2951                 error_report("could not load initial ram disk '%s'",
2952                              initrd_filename);
2953                 exit(1);
2954             }
2955         }
2956     }
2957 
2958     if (bios_name == NULL) {
2959         bios_name = FW_FILE_NAME;
2960     }
2961     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2962     if (!filename) {
2963         error_report("Could not find LPAR firmware '%s'", bios_name);
2964         exit(1);
2965     }
2966     fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2967     if (fw_size <= 0) {
2968         error_report("Could not load LPAR firmware '%s'", filename);
2969         exit(1);
2970     }
2971     g_free(filename);
2972 
2973     /* FIXME: Should register things through the MachineState's qdev
2974      * interface, this is a legacy from the sPAPREnvironment structure
2975      * which predated MachineState but had a similar function */
2976     vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2977     register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1,
2978                          &savevm_htab_handlers, spapr);
2979 
2980     qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine));
2981 
2982     qemu_register_boot_set(spapr_boot_set, spapr);
2983 
2984     /*
2985      * Nothing needs to be done to resume a suspended guest because
2986      * suspending does not change the machine state, so no need for
2987      * a ->wakeup method.
2988      */
2989     qemu_register_wakeup_support();
2990 
2991     if (kvm_enabled()) {
2992         /* to stop and start vmclock */
2993         qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
2994                                          &spapr->tb);
2995 
2996         kvmppc_spapr_enable_inkernel_multitce();
2997     }
2998 
2999     qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond);
3000 }
3001 
3002 static int spapr_kvm_type(MachineState *machine, const char *vm_type)
3003 {
3004     if (!vm_type) {
3005         return 0;
3006     }
3007 
3008     if (!strcmp(vm_type, "HV")) {
3009         return 1;
3010     }
3011 
3012     if (!strcmp(vm_type, "PR")) {
3013         return 2;
3014     }
3015 
3016     error_report("Unknown kvm-type specified '%s'", vm_type);
3017     exit(1);
3018 }
3019 
3020 /*
3021  * Implementation of an interface to adjust firmware path
3022  * for the bootindex property handling.
3023  */
3024 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
3025                                    DeviceState *dev)
3026 {
3027 #define CAST(type, obj, name) \
3028     ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3029     SCSIDevice *d = CAST(SCSIDevice,  dev, TYPE_SCSI_DEVICE);
3030     SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
3031     VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
3032 
3033     if (d) {
3034         void *spapr = CAST(void, bus->parent, "spapr-vscsi");
3035         VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
3036         USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
3037 
3038         if (spapr) {
3039             /*
3040              * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
3041              * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
3042              * 0x8000 | (target << 8) | (bus << 5) | lun
3043              * (see the "Logical unit addressing format" table in SAM5)
3044              */
3045             unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun;
3046             return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3047                                    (uint64_t)id << 48);
3048         } else if (virtio) {
3049             /*
3050              * We use SRP luns of the form 01000000 | (target << 8) | lun
3051              * in the top 32 bits of the 64-bit LUN
3052              * Note: the quote above is from SLOF and it is wrong,
3053              * the actual binding is:
3054              * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
3055              */
3056             unsigned id = 0x1000000 | (d->id << 16) | d->lun;
3057             if (d->lun >= 256) {
3058                 /* Use the LUN "flat space addressing method" */
3059                 id |= 0x4000;
3060             }
3061             return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3062                                    (uint64_t)id << 32);
3063         } else if (usb) {
3064             /*
3065              * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3066              * in the top 32 bits of the 64-bit LUN
3067              */
3068             unsigned usb_port = atoi(usb->port->path);
3069             unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
3070             return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3071                                    (uint64_t)id << 32);
3072         }
3073     }
3074 
3075     /*
3076      * SLOF probes the USB devices, and if it recognizes that the device is a
3077      * storage device, it changes its name to "storage" instead of "usb-host",
3078      * and additionally adds a child node for the SCSI LUN, so the correct
3079      * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3080      */
3081     if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
3082         USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
3083         if (usb_host_dev_is_scsi_storage(usbdev)) {
3084             return g_strdup_printf("storage@%s/disk", usbdev->port->path);
3085         }
3086     }
3087 
3088     if (phb) {
3089         /* Replace "pci" with "pci@800000020000000" */
3090         return g_strdup_printf("pci@%"PRIX64, phb->buid);
3091     }
3092 
3093     if (vsc) {
3094         /* Same logic as virtio above */
3095         unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
3096         return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
3097     }
3098 
3099     if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
3100         /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3101         PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
3102         return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
3103     }
3104 
3105     return NULL;
3106 }
3107 
3108 static char *spapr_get_kvm_type(Object *obj, Error **errp)
3109 {
3110     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3111 
3112     return g_strdup(spapr->kvm_type);
3113 }
3114 
3115 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
3116 {
3117     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3118 
3119     g_free(spapr->kvm_type);
3120     spapr->kvm_type = g_strdup(value);
3121 }
3122 
3123 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
3124 {
3125     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3126 
3127     return spapr->use_hotplug_event_source;
3128 }
3129 
3130 static void spapr_set_modern_hotplug_events(Object *obj, bool value,
3131                                             Error **errp)
3132 {
3133     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3134 
3135     spapr->use_hotplug_event_source = value;
3136 }
3137 
3138 static bool spapr_get_msix_emulation(Object *obj, Error **errp)
3139 {
3140     return true;
3141 }
3142 
3143 static char *spapr_get_resize_hpt(Object *obj, Error **errp)
3144 {
3145     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3146 
3147     switch (spapr->resize_hpt) {
3148     case SPAPR_RESIZE_HPT_DEFAULT:
3149         return g_strdup("default");
3150     case SPAPR_RESIZE_HPT_DISABLED:
3151         return g_strdup("disabled");
3152     case SPAPR_RESIZE_HPT_ENABLED:
3153         return g_strdup("enabled");
3154     case SPAPR_RESIZE_HPT_REQUIRED:
3155         return g_strdup("required");
3156     }
3157     g_assert_not_reached();
3158 }
3159 
3160 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
3161 {
3162     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3163 
3164     if (strcmp(value, "default") == 0) {
3165         spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
3166     } else if (strcmp(value, "disabled") == 0) {
3167         spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
3168     } else if (strcmp(value, "enabled") == 0) {
3169         spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
3170     } else if (strcmp(value, "required") == 0) {
3171         spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
3172     } else {
3173         error_setg(errp, "Bad value for \"resize-hpt\" property");
3174     }
3175 }
3176 
3177 static char *spapr_get_ic_mode(Object *obj, Error **errp)
3178 {
3179     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3180 
3181     if (spapr->irq == &spapr_irq_xics_legacy) {
3182         return g_strdup("legacy");
3183     } else if (spapr->irq == &spapr_irq_xics) {
3184         return g_strdup("xics");
3185     } else if (spapr->irq == &spapr_irq_xive) {
3186         return g_strdup("xive");
3187     } else if (spapr->irq == &spapr_irq_dual) {
3188         return g_strdup("dual");
3189     }
3190     g_assert_not_reached();
3191 }
3192 
3193 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp)
3194 {
3195     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3196 
3197     if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
3198         error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3199         return;
3200     }
3201 
3202     /* The legacy IRQ backend can not be set */
3203     if (strcmp(value, "xics") == 0) {
3204         spapr->irq = &spapr_irq_xics;
3205     } else if (strcmp(value, "xive") == 0) {
3206         spapr->irq = &spapr_irq_xive;
3207     } else if (strcmp(value, "dual") == 0) {
3208         spapr->irq = &spapr_irq_dual;
3209     } else {
3210         error_setg(errp, "Bad value for \"ic-mode\" property");
3211     }
3212 }
3213 
3214 static char *spapr_get_host_model(Object *obj, Error **errp)
3215 {
3216     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3217 
3218     return g_strdup(spapr->host_model);
3219 }
3220 
3221 static void spapr_set_host_model(Object *obj, const char *value, Error **errp)
3222 {
3223     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3224 
3225     g_free(spapr->host_model);
3226     spapr->host_model = g_strdup(value);
3227 }
3228 
3229 static char *spapr_get_host_serial(Object *obj, Error **errp)
3230 {
3231     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3232 
3233     return g_strdup(spapr->host_serial);
3234 }
3235 
3236 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp)
3237 {
3238     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3239 
3240     g_free(spapr->host_serial);
3241     spapr->host_serial = g_strdup(value);
3242 }
3243 
3244 static void spapr_instance_init(Object *obj)
3245 {
3246     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3247     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3248 
3249     spapr->htab_fd = -1;
3250     spapr->use_hotplug_event_source = true;
3251     object_property_add_str(obj, "kvm-type",
3252                             spapr_get_kvm_type, spapr_set_kvm_type);
3253     object_property_set_description(obj, "kvm-type",
3254                                     "Specifies the KVM virtualization mode (HV, PR)");
3255     object_property_add_bool(obj, "modern-hotplug-events",
3256                             spapr_get_modern_hotplug_events,
3257                             spapr_set_modern_hotplug_events);
3258     object_property_set_description(obj, "modern-hotplug-events",
3259                                     "Use dedicated hotplug event mechanism in"
3260                                     " place of standard EPOW events when possible"
3261                                     " (required for memory hot-unplug support)");
3262     ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
3263                             "Maximum permitted CPU compatibility mode");
3264 
3265     object_property_add_str(obj, "resize-hpt",
3266                             spapr_get_resize_hpt, spapr_set_resize_hpt);
3267     object_property_set_description(obj, "resize-hpt",
3268                                     "Resizing of the Hash Page Table (enabled, disabled, required)");
3269     object_property_add_uint32_ptr(obj, "vsmt",
3270                                    &spapr->vsmt, OBJ_PROP_FLAG_READWRITE);
3271     object_property_set_description(obj, "vsmt",
3272                                     "Virtual SMT: KVM behaves as if this were"
3273                                     " the host's SMT mode");
3274 
3275     object_property_add_bool(obj, "vfio-no-msix-emulation",
3276                              spapr_get_msix_emulation, NULL);
3277 
3278     object_property_add_uint64_ptr(obj, "kernel-addr",
3279                                    &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE);
3280     object_property_set_description(obj, "kernel-addr",
3281                                     stringify(KERNEL_LOAD_ADDR)
3282                                     " for -kernel is the default");
3283     spapr->kernel_addr = KERNEL_LOAD_ADDR;
3284     /* The machine class defines the default interrupt controller mode */
3285     spapr->irq = smc->irq;
3286     object_property_add_str(obj, "ic-mode", spapr_get_ic_mode,
3287                             spapr_set_ic_mode);
3288     object_property_set_description(obj, "ic-mode",
3289                  "Specifies the interrupt controller mode (xics, xive, dual)");
3290 
3291     object_property_add_str(obj, "host-model",
3292         spapr_get_host_model, spapr_set_host_model);
3293     object_property_set_description(obj, "host-model",
3294         "Host model to advertise in guest device tree");
3295     object_property_add_str(obj, "host-serial",
3296         spapr_get_host_serial, spapr_set_host_serial);
3297     object_property_set_description(obj, "host-serial",
3298         "Host serial number to advertise in guest device tree");
3299 }
3300 
3301 static void spapr_machine_finalizefn(Object *obj)
3302 {
3303     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3304 
3305     g_free(spapr->kvm_type);
3306 }
3307 
3308 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
3309 {
3310     SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
3311     PowerPCCPU *cpu = POWERPC_CPU(cs);
3312     CPUPPCState *env = &cpu->env;
3313 
3314     cpu_synchronize_state(cs);
3315     /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */
3316     if (spapr->fwnmi_system_reset_addr != -1) {
3317         uint64_t rtas_addr, addr;
3318 
3319         /* get rtas addr from fdt */
3320         rtas_addr = spapr_get_rtas_addr();
3321         if (!rtas_addr) {
3322             qemu_system_guest_panicked(NULL);
3323             return;
3324         }
3325 
3326         addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2;
3327         stq_be_phys(&address_space_memory, addr, env->gpr[3]);
3328         stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0);
3329         env->gpr[3] = addr;
3330     }
3331     ppc_cpu_do_system_reset(cs);
3332     if (spapr->fwnmi_system_reset_addr != -1) {
3333         env->nip = spapr->fwnmi_system_reset_addr;
3334     }
3335 }
3336 
3337 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
3338 {
3339     CPUState *cs;
3340 
3341     CPU_FOREACH(cs) {
3342         async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
3343     }
3344 }
3345 
3346 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3347                           void *fdt, int *fdt_start_offset, Error **errp)
3348 {
3349     uint64_t addr;
3350     uint32_t node;
3351 
3352     addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE;
3353     node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP,
3354                                     &error_abort);
3355     *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr,
3356                                              SPAPR_MEMORY_BLOCK_SIZE);
3357     return 0;
3358 }
3359 
3360 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
3361                            bool dedicated_hp_event_source, Error **errp)
3362 {
3363     SpaprDrc *drc;
3364     uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
3365     int i;
3366     uint64_t addr = addr_start;
3367     bool hotplugged = spapr_drc_hotplugged(dev);
3368     Error *local_err = NULL;
3369 
3370     for (i = 0; i < nr_lmbs; i++) {
3371         drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3372                               addr / SPAPR_MEMORY_BLOCK_SIZE);
3373         g_assert(drc);
3374 
3375         spapr_drc_attach(drc, dev, &local_err);
3376         if (local_err) {
3377             while (addr > addr_start) {
3378                 addr -= SPAPR_MEMORY_BLOCK_SIZE;
3379                 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3380                                       addr / SPAPR_MEMORY_BLOCK_SIZE);
3381                 spapr_drc_detach(drc);
3382             }
3383             error_propagate(errp, local_err);
3384             return;
3385         }
3386         if (!hotplugged) {
3387             spapr_drc_reset(drc);
3388         }
3389         addr += SPAPR_MEMORY_BLOCK_SIZE;
3390     }
3391     /* send hotplug notification to the
3392      * guest only in case of hotplugged memory
3393      */
3394     if (hotplugged) {
3395         if (dedicated_hp_event_source) {
3396             drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3397                                   addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3398             spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3399                                                    nr_lmbs,
3400                                                    spapr_drc_index(drc));
3401         } else {
3402             spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
3403                                            nr_lmbs);
3404         }
3405     }
3406 }
3407 
3408 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3409                               Error **errp)
3410 {
3411     Error *local_err = NULL;
3412     SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev);
3413     PCDIMMDevice *dimm = PC_DIMM(dev);
3414     uint64_t size, addr, slot;
3415     bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
3416 
3417     size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort);
3418 
3419     pc_dimm_plug(dimm, MACHINE(ms), &local_err);
3420     if (local_err) {
3421         goto out;
3422     }
3423 
3424     if (!is_nvdimm) {
3425         addr = object_property_get_uint(OBJECT(dimm),
3426                                         PC_DIMM_ADDR_PROP, &local_err);
3427         if (local_err) {
3428             goto out_unplug;
3429         }
3430         spapr_add_lmbs(dev, addr, size,
3431                        spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
3432                        &local_err);
3433     } else {
3434         slot = object_property_get_uint(OBJECT(dimm),
3435                                         PC_DIMM_SLOT_PROP, &local_err);
3436         if (local_err) {
3437             goto out_unplug;
3438         }
3439         spapr_add_nvdimm(dev, slot, &local_err);
3440     }
3441 
3442     if (local_err) {
3443         goto out_unplug;
3444     }
3445 
3446     return;
3447 
3448 out_unplug:
3449     pc_dimm_unplug(dimm, MACHINE(ms));
3450 out:
3451     error_propagate(errp, local_err);
3452 }
3453 
3454 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3455                                   Error **errp)
3456 {
3457     const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev);
3458     SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3459     bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
3460     PCDIMMDevice *dimm = PC_DIMM(dev);
3461     Error *local_err = NULL;
3462     uint64_t size;
3463     Object *memdev;
3464     hwaddr pagesize;
3465 
3466     if (!smc->dr_lmb_enabled) {
3467         error_setg(errp, "Memory hotplug not supported for this machine");
3468         return;
3469     }
3470 
3471     size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err);
3472     if (local_err) {
3473         error_propagate(errp, local_err);
3474         return;
3475     }
3476 
3477     if (is_nvdimm) {
3478         spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, &local_err);
3479         if (local_err) {
3480             error_propagate(errp, local_err);
3481             return;
3482         }
3483     } else if (size % SPAPR_MEMORY_BLOCK_SIZE) {
3484         error_setg(errp, "Hotplugged memory size must be a multiple of "
3485                    "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB);
3486         return;
3487     }
3488 
3489     memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP,
3490                                       &error_abort);
3491     pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev));
3492     spapr_check_pagesize(spapr, pagesize, &local_err);
3493     if (local_err) {
3494         error_propagate(errp, local_err);
3495         return;
3496     }
3497 
3498     pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp);
3499 }
3500 
3501 struct SpaprDimmState {
3502     PCDIMMDevice *dimm;
3503     uint32_t nr_lmbs;
3504     QTAILQ_ENTRY(SpaprDimmState) next;
3505 };
3506 
3507 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s,
3508                                                        PCDIMMDevice *dimm)
3509 {
3510     SpaprDimmState *dimm_state = NULL;
3511 
3512     QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) {
3513         if (dimm_state->dimm == dimm) {
3514             break;
3515         }
3516     }
3517     return dimm_state;
3518 }
3519 
3520 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr,
3521                                                       uint32_t nr_lmbs,
3522                                                       PCDIMMDevice *dimm)
3523 {
3524     SpaprDimmState *ds = NULL;
3525 
3526     /*
3527      * If this request is for a DIMM whose removal had failed earlier
3528      * (due to guest's refusal to remove the LMBs), we would have this
3529      * dimm already in the pending_dimm_unplugs list. In that
3530      * case don't add again.
3531      */
3532     ds = spapr_pending_dimm_unplugs_find(spapr, dimm);
3533     if (!ds) {
3534         ds = g_malloc0(sizeof(SpaprDimmState));
3535         ds->nr_lmbs = nr_lmbs;
3536         ds->dimm = dimm;
3537         QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next);
3538     }
3539     return ds;
3540 }
3541 
3542 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr,
3543                                               SpaprDimmState *dimm_state)
3544 {
3545     QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next);
3546     g_free(dimm_state);
3547 }
3548 
3549 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms,
3550                                                         PCDIMMDevice *dimm)
3551 {
3552     SpaprDrc *drc;
3553     uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm),
3554                                                   &error_abort);
3555     uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3556     uint32_t avail_lmbs = 0;
3557     uint64_t addr_start, addr;
3558     int i;
3559 
3560     addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3561                                          &error_abort);
3562 
3563     addr = addr_start;
3564     for (i = 0; i < nr_lmbs; i++) {
3565         drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3566                               addr / SPAPR_MEMORY_BLOCK_SIZE);
3567         g_assert(drc);
3568         if (drc->dev) {
3569             avail_lmbs++;
3570         }
3571         addr += SPAPR_MEMORY_BLOCK_SIZE;
3572     }
3573 
3574     return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm);
3575 }
3576 
3577 /* Callback to be called during DRC release. */
3578 void spapr_lmb_release(DeviceState *dev)
3579 {
3580     HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3581     SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl);
3582     SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3583 
3584     /* This information will get lost if a migration occurs
3585      * during the unplug process. In this case recover it. */
3586     if (ds == NULL) {
3587         ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev));
3588         g_assert(ds);
3589         /* The DRC being examined by the caller at least must be counted */
3590         g_assert(ds->nr_lmbs);
3591     }
3592 
3593     if (--ds->nr_lmbs) {
3594         return;
3595     }
3596 
3597     /*
3598      * Now that all the LMBs have been removed by the guest, call the
3599      * unplug handler chain. This can never fail.
3600      */
3601     hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3602     object_unparent(OBJECT(dev));
3603 }
3604 
3605 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3606 {
3607     SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3608     SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3609 
3610     pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev));
3611     qdev_unrealize(dev);
3612     spapr_pending_dimm_unplugs_remove(spapr, ds);
3613 }
3614 
3615 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
3616                                         DeviceState *dev, Error **errp)
3617 {
3618     SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3619     Error *local_err = NULL;
3620     PCDIMMDevice *dimm = PC_DIMM(dev);
3621     uint32_t nr_lmbs;
3622     uint64_t size, addr_start, addr;
3623     int i;
3624     SpaprDrc *drc;
3625 
3626     if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
3627         error_setg(errp, "nvdimm device hot unplug is not supported yet.");
3628         return;
3629     }
3630 
3631     size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort);
3632     nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3633 
3634     addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3635                                          &local_err);
3636     if (local_err) {
3637         error_propagate(errp, local_err);
3638         return;
3639     }
3640 
3641     /*
3642      * An existing pending dimm state for this DIMM means that there is an
3643      * unplug operation in progress, waiting for the spapr_lmb_release
3644      * callback to complete the job (BQL can't cover that far). In this case,
3645      * bail out to avoid detaching DRCs that were already released.
3646      */
3647     if (spapr_pending_dimm_unplugs_find(spapr, dimm)) {
3648         error_setg(errp, "Memory unplug already in progress for device %s",
3649                    dev->id);
3650         return;
3651     }
3652 
3653     spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm);
3654 
3655     addr = addr_start;
3656     for (i = 0; i < nr_lmbs; i++) {
3657         drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3658                               addr / SPAPR_MEMORY_BLOCK_SIZE);
3659         g_assert(drc);
3660 
3661         spapr_drc_detach(drc);
3662         addr += SPAPR_MEMORY_BLOCK_SIZE;
3663     }
3664 
3665     drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3666                           addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3667     spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3668                                               nr_lmbs, spapr_drc_index(drc));
3669 }
3670 
3671 /* Callback to be called during DRC release. */
3672 void spapr_core_release(DeviceState *dev)
3673 {
3674     HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3675 
3676     /* Call the unplug handler chain. This can never fail. */
3677     hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3678     object_unparent(OBJECT(dev));
3679 }
3680 
3681 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3682 {
3683     MachineState *ms = MACHINE(hotplug_dev);
3684     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3685     CPUCore *cc = CPU_CORE(dev);
3686     CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
3687 
3688     if (smc->pre_2_10_has_unused_icps) {
3689         SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
3690         int i;
3691 
3692         for (i = 0; i < cc->nr_threads; i++) {
3693             CPUState *cs = CPU(sc->threads[i]);
3694 
3695             pre_2_10_vmstate_register_dummy_icp(cs->cpu_index);
3696         }
3697     }
3698 
3699     assert(core_slot);
3700     core_slot->cpu = NULL;
3701     qdev_unrealize(dev);
3702 }
3703 
3704 static
3705 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
3706                                Error **errp)
3707 {
3708     SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3709     int index;
3710     SpaprDrc *drc;
3711     CPUCore *cc = CPU_CORE(dev);
3712 
3713     if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
3714         error_setg(errp, "Unable to find CPU core with core-id: %d",
3715                    cc->core_id);
3716         return;
3717     }
3718     if (index == 0) {
3719         error_setg(errp, "Boot CPU core may not be unplugged");
3720         return;
3721     }
3722 
3723     drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3724                           spapr_vcpu_id(spapr, cc->core_id));
3725     g_assert(drc);
3726 
3727     if (!spapr_drc_unplug_requested(drc)) {
3728         spapr_drc_detach(drc);
3729         spapr_hotplug_req_remove_by_index(drc);
3730     }
3731 }
3732 
3733 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3734                            void *fdt, int *fdt_start_offset, Error **errp)
3735 {
3736     SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev);
3737     CPUState *cs = CPU(core->threads[0]);
3738     PowerPCCPU *cpu = POWERPC_CPU(cs);
3739     DeviceClass *dc = DEVICE_GET_CLASS(cs);
3740     int id = spapr_get_vcpu_id(cpu);
3741     char *nodename;
3742     int offset;
3743 
3744     nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
3745     offset = fdt_add_subnode(fdt, 0, nodename);
3746     g_free(nodename);
3747 
3748     spapr_dt_cpu(cs, fdt, offset, spapr);
3749 
3750     *fdt_start_offset = offset;
3751     return 0;
3752 }
3753 
3754 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3755                             Error **errp)
3756 {
3757     SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3758     MachineClass *mc = MACHINE_GET_CLASS(spapr);
3759     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3760     SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev));
3761     CPUCore *cc = CPU_CORE(dev);
3762     CPUState *cs;
3763     SpaprDrc *drc;
3764     Error *local_err = NULL;
3765     CPUArchId *core_slot;
3766     int index;
3767     bool hotplugged = spapr_drc_hotplugged(dev);
3768     int i;
3769 
3770     core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3771     if (!core_slot) {
3772         error_setg(errp, "Unable to find CPU core with core-id: %d",
3773                    cc->core_id);
3774         return;
3775     }
3776     drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3777                           spapr_vcpu_id(spapr, cc->core_id));
3778 
3779     g_assert(drc || !mc->has_hotpluggable_cpus);
3780 
3781     if (drc) {
3782         spapr_drc_attach(drc, dev, &local_err);
3783         if (local_err) {
3784             error_propagate(errp, local_err);
3785             return;
3786         }
3787 
3788         if (hotplugged) {
3789             /*
3790              * Send hotplug notification interrupt to the guest only
3791              * in case of hotplugged CPUs.
3792              */
3793             spapr_hotplug_req_add_by_index(drc);
3794         } else {
3795             spapr_drc_reset(drc);
3796         }
3797     }
3798 
3799     core_slot->cpu = OBJECT(dev);
3800 
3801     if (smc->pre_2_10_has_unused_icps) {
3802         for (i = 0; i < cc->nr_threads; i++) {
3803             cs = CPU(core->threads[i]);
3804             pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
3805         }
3806     }
3807 
3808     /*
3809      * Set compatibility mode to match the boot CPU, which was either set
3810      * by the machine reset code or by CAS.
3811      */
3812     if (hotplugged) {
3813         for (i = 0; i < cc->nr_threads; i++) {
3814             ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr,
3815                            &local_err);
3816             if (local_err) {
3817                 error_propagate(errp, local_err);
3818                 return;
3819             }
3820         }
3821     }
3822 }
3823 
3824 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3825                                 Error **errp)
3826 {
3827     MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3828     MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
3829     CPUCore *cc = CPU_CORE(dev);
3830     const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type);
3831     const char *type = object_get_typename(OBJECT(dev));
3832     CPUArchId *core_slot;
3833     int index;
3834     unsigned int smp_threads = machine->smp.threads;
3835 
3836     if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
3837         error_setg(errp, "CPU hotplug not supported for this machine");
3838         return;
3839     }
3840 
3841     if (strcmp(base_core_type, type)) {
3842         error_setg(errp, "CPU core type should be %s", base_core_type);
3843         return;
3844     }
3845 
3846     if (cc->core_id % smp_threads) {
3847         error_setg(errp, "invalid core id %d", cc->core_id);
3848         return;
3849     }
3850 
3851     /*
3852      * In general we should have homogeneous threads-per-core, but old
3853      * (pre hotplug support) machine types allow the last core to have
3854      * reduced threads as a compatibility hack for when we allowed
3855      * total vcpus not a multiple of threads-per-core.
3856      */
3857     if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) {
3858         error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads,
3859                    smp_threads);
3860         return;
3861     }
3862 
3863     core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3864     if (!core_slot) {
3865         error_setg(errp, "core id %d out of range", cc->core_id);
3866         return;
3867     }
3868 
3869     if (core_slot->cpu) {
3870         error_setg(errp, "core %d already populated", cc->core_id);
3871         return;
3872     }
3873 
3874     numa_cpu_pre_plug(core_slot, dev, errp);
3875 }
3876 
3877 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3878                           void *fdt, int *fdt_start_offset, Error **errp)
3879 {
3880     SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev);
3881     int intc_phandle;
3882 
3883     intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp);
3884     if (intc_phandle <= 0) {
3885         return -1;
3886     }
3887 
3888     if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) {
3889         error_setg(errp, "unable to create FDT node for PHB %d", sphb->index);
3890         return -1;
3891     }
3892 
3893     /* generally SLOF creates these, for hotplug it's up to QEMU */
3894     _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci"));
3895 
3896     return 0;
3897 }
3898 
3899 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3900                                Error **errp)
3901 {
3902     SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3903     SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
3904     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3905     const unsigned windows_supported = spapr_phb_windows_supported(sphb);
3906 
3907     if (dev->hotplugged && !smc->dr_phb_enabled) {
3908         error_setg(errp, "PHB hotplug not supported for this machine");
3909         return;
3910     }
3911 
3912     if (sphb->index == (uint32_t)-1) {
3913         error_setg(errp, "\"index\" for PAPR PHB is mandatory");
3914         return;
3915     }
3916 
3917     /*
3918      * This will check that sphb->index doesn't exceed the maximum number of
3919      * PHBs for the current machine type.
3920      */
3921     smc->phb_placement(spapr, sphb->index,
3922                        &sphb->buid, &sphb->io_win_addr,
3923                        &sphb->mem_win_addr, &sphb->mem64_win_addr,
3924                        windows_supported, sphb->dma_liobn,
3925                        &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr,
3926                        errp);
3927 }
3928 
3929 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3930                            Error **errp)
3931 {
3932     SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3933     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3934     SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
3935     SpaprDrc *drc;
3936     bool hotplugged = spapr_drc_hotplugged(dev);
3937     Error *local_err = NULL;
3938 
3939     if (!smc->dr_phb_enabled) {
3940         return;
3941     }
3942 
3943     drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index);
3944     /* hotplug hooks should check it's enabled before getting this far */
3945     assert(drc);
3946 
3947     spapr_drc_attach(drc, dev, &local_err);
3948     if (local_err) {
3949         error_propagate(errp, local_err);
3950         return;
3951     }
3952 
3953     if (hotplugged) {
3954         spapr_hotplug_req_add_by_index(drc);
3955     } else {
3956         spapr_drc_reset(drc);
3957     }
3958 }
3959 
3960 void spapr_phb_release(DeviceState *dev)
3961 {
3962     HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3963 
3964     hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3965     object_unparent(OBJECT(dev));
3966 }
3967 
3968 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3969 {
3970     qdev_unrealize(dev);
3971 }
3972 
3973 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev,
3974                                      DeviceState *dev, Error **errp)
3975 {
3976     SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
3977     SpaprDrc *drc;
3978 
3979     drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index);
3980     assert(drc);
3981 
3982     if (!spapr_drc_unplug_requested(drc)) {
3983         spapr_drc_detach(drc);
3984         spapr_hotplug_req_remove_by_index(drc);
3985     }
3986 }
3987 
3988 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3989                                  Error **errp)
3990 {
3991     SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3992     SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev);
3993 
3994     if (spapr->tpm_proxy != NULL) {
3995         error_setg(errp, "Only one TPM proxy can be specified for this machine");
3996         return;
3997     }
3998 
3999     spapr->tpm_proxy = tpm_proxy;
4000 }
4001 
4002 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
4003 {
4004     SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
4005 
4006     qdev_unrealize(dev);
4007     object_unparent(OBJECT(dev));
4008     spapr->tpm_proxy = NULL;
4009 }
4010 
4011 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
4012                                       DeviceState *dev, Error **errp)
4013 {
4014     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4015         spapr_memory_plug(hotplug_dev, dev, errp);
4016     } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4017         spapr_core_plug(hotplug_dev, dev, errp);
4018     } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4019         spapr_phb_plug(hotplug_dev, dev, errp);
4020     } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) {
4021         spapr_tpm_proxy_plug(hotplug_dev, dev, errp);
4022     }
4023 }
4024 
4025 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
4026                                         DeviceState *dev, Error **errp)
4027 {
4028     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4029         spapr_memory_unplug(hotplug_dev, dev);
4030     } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4031         spapr_core_unplug(hotplug_dev, dev);
4032     } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4033         spapr_phb_unplug(hotplug_dev, dev);
4034     } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) {
4035         spapr_tpm_proxy_unplug(hotplug_dev, dev);
4036     }
4037 }
4038 
4039 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
4040                                                 DeviceState *dev, Error **errp)
4041 {
4042     SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev));
4043     MachineClass *mc = MACHINE_GET_CLASS(sms);
4044     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4045 
4046     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4047         if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
4048             spapr_memory_unplug_request(hotplug_dev, dev, errp);
4049         } else {
4050             /* NOTE: this means there is a window after guest reset, prior to
4051              * CAS negotiation, where unplug requests will fail due to the
4052              * capability not being detected yet. This is a bit different than
4053              * the case with PCI unplug, where the events will be queued and
4054              * eventually handled by the guest after boot
4055              */
4056             error_setg(errp, "Memory hot unplug not supported for this guest");
4057         }
4058     } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4059         if (!mc->has_hotpluggable_cpus) {
4060             error_setg(errp, "CPU hot unplug not supported on this machine");
4061             return;
4062         }
4063         spapr_core_unplug_request(hotplug_dev, dev, errp);
4064     } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4065         if (!smc->dr_phb_enabled) {
4066             error_setg(errp, "PHB hot unplug not supported on this machine");
4067             return;
4068         }
4069         spapr_phb_unplug_request(hotplug_dev, dev, errp);
4070     } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) {
4071         spapr_tpm_proxy_unplug(hotplug_dev, dev);
4072     }
4073 }
4074 
4075 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
4076                                           DeviceState *dev, Error **errp)
4077 {
4078     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4079         spapr_memory_pre_plug(hotplug_dev, dev, errp);
4080     } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4081         spapr_core_pre_plug(hotplug_dev, dev, errp);
4082     } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4083         spapr_phb_pre_plug(hotplug_dev, dev, errp);
4084     }
4085 }
4086 
4087 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
4088                                                  DeviceState *dev)
4089 {
4090     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
4091         object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) ||
4092         object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) ||
4093         object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) {
4094         return HOTPLUG_HANDLER(machine);
4095     }
4096     if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
4097         PCIDevice *pcidev = PCI_DEVICE(dev);
4098         PCIBus *root = pci_device_root_bus(pcidev);
4099         SpaprPhbState *phb =
4100             (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent),
4101                                                  TYPE_SPAPR_PCI_HOST_BRIDGE);
4102 
4103         if (phb) {
4104             return HOTPLUG_HANDLER(phb);
4105         }
4106     }
4107     return NULL;
4108 }
4109 
4110 static CpuInstanceProperties
4111 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
4112 {
4113     CPUArchId *core_slot;
4114     MachineClass *mc = MACHINE_GET_CLASS(machine);
4115 
4116     /* make sure possible_cpu are intialized */
4117     mc->possible_cpu_arch_ids(machine);
4118     /* get CPU core slot containing thread that matches cpu_index */
4119     core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
4120     assert(core_slot);
4121     return core_slot->props;
4122 }
4123 
4124 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx)
4125 {
4126     return idx / ms->smp.cores % ms->numa_state->num_nodes;
4127 }
4128 
4129 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
4130 {
4131     int i;
4132     unsigned int smp_threads = machine->smp.threads;
4133     unsigned int smp_cpus = machine->smp.cpus;
4134     const char *core_type;
4135     int spapr_max_cores = machine->smp.max_cpus / smp_threads;
4136     MachineClass *mc = MACHINE_GET_CLASS(machine);
4137 
4138     if (!mc->has_hotpluggable_cpus) {
4139         spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
4140     }
4141     if (machine->possible_cpus) {
4142         assert(machine->possible_cpus->len == spapr_max_cores);
4143         return machine->possible_cpus;
4144     }
4145 
4146     core_type = spapr_get_cpu_core_type(machine->cpu_type);
4147     if (!core_type) {
4148         error_report("Unable to find sPAPR CPU Core definition");
4149         exit(1);
4150     }
4151 
4152     machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
4153                              sizeof(CPUArchId) * spapr_max_cores);
4154     machine->possible_cpus->len = spapr_max_cores;
4155     for (i = 0; i < machine->possible_cpus->len; i++) {
4156         int core_id = i * smp_threads;
4157 
4158         machine->possible_cpus->cpus[i].type = core_type;
4159         machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
4160         machine->possible_cpus->cpus[i].arch_id = core_id;
4161         machine->possible_cpus->cpus[i].props.has_core_id = true;
4162         machine->possible_cpus->cpus[i].props.core_id = core_id;
4163     }
4164     return machine->possible_cpus;
4165 }
4166 
4167 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index,
4168                                 uint64_t *buid, hwaddr *pio,
4169                                 hwaddr *mmio32, hwaddr *mmio64,
4170                                 unsigned n_dma, uint32_t *liobns,
4171                                 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp)
4172 {
4173     /*
4174      * New-style PHB window placement.
4175      *
4176      * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
4177      * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
4178      * windows.
4179      *
4180      * Some guest kernels can't work with MMIO windows above 1<<46
4181      * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
4182      *
4183      * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
4184      * PHB stacked together.  (32TiB+2GiB)..(32TiB+64GiB) contains the
4185      * 2GiB 32-bit MMIO windows for each PHB.  Then 33..64TiB has the
4186      * 1TiB 64-bit MMIO windows for each PHB.
4187      */
4188     const uint64_t base_buid = 0x800000020000000ULL;
4189     int i;
4190 
4191     /* Sanity check natural alignments */
4192     QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
4193     QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
4194     QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
4195     QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
4196     /* Sanity check bounds */
4197     QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
4198                       SPAPR_PCI_MEM32_WIN_SIZE);
4199     QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
4200                       SPAPR_PCI_MEM64_WIN_SIZE);
4201 
4202     if (index >= SPAPR_MAX_PHBS) {
4203         error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
4204                    SPAPR_MAX_PHBS - 1);
4205         return;
4206     }
4207 
4208     *buid = base_buid + index;
4209     for (i = 0; i < n_dma; ++i) {
4210         liobns[i] = SPAPR_PCI_LIOBN(index, i);
4211     }
4212 
4213     *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
4214     *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
4215     *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
4216 
4217     *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE;
4218     *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE;
4219 }
4220 
4221 static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
4222 {
4223     SpaprMachineState *spapr = SPAPR_MACHINE(dev);
4224 
4225     return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
4226 }
4227 
4228 static void spapr_ics_resend(XICSFabric *dev)
4229 {
4230     SpaprMachineState *spapr = SPAPR_MACHINE(dev);
4231 
4232     ics_resend(spapr->ics);
4233 }
4234 
4235 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
4236 {
4237     PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
4238 
4239     return cpu ? spapr_cpu_state(cpu)->icp : NULL;
4240 }
4241 
4242 static void spapr_pic_print_info(InterruptStatsProvider *obj,
4243                                  Monitor *mon)
4244 {
4245     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
4246 
4247     spapr_irq_print_info(spapr, mon);
4248     monitor_printf(mon, "irqchip: %s\n",
4249                    kvm_irqchip_in_kernel() ? "in-kernel" : "emulated");
4250 }
4251 
4252 /*
4253  * This is a XIVE only operation
4254  */
4255 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format,
4256                            uint8_t nvt_blk, uint32_t nvt_idx,
4257                            bool cam_ignore, uint8_t priority,
4258                            uint32_t logic_serv, XiveTCTXMatch *match)
4259 {
4260     SpaprMachineState *spapr = SPAPR_MACHINE(xfb);
4261     XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc);
4262     XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
4263     int count;
4264 
4265     count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
4266                            priority, logic_serv, match);
4267     if (count < 0) {
4268         return count;
4269     }
4270 
4271     /*
4272      * When we implement the save and restore of the thread interrupt
4273      * contexts in the enter/exit CPU handlers of the machine and the
4274      * escalations in QEMU, we should be able to handle non dispatched
4275      * vCPUs.
4276      *
4277      * Until this is done, the sPAPR machine should find at least one
4278      * matching context always.
4279      */
4280     if (count == 0) {
4281         qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n",
4282                       nvt_blk, nvt_idx);
4283     }
4284 
4285     return count;
4286 }
4287 
4288 int spapr_get_vcpu_id(PowerPCCPU *cpu)
4289 {
4290     return cpu->vcpu_id;
4291 }
4292 
4293 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp)
4294 {
4295     SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
4296     MachineState *ms = MACHINE(spapr);
4297     int vcpu_id;
4298 
4299     vcpu_id = spapr_vcpu_id(spapr, cpu_index);
4300 
4301     if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) {
4302         error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id);
4303         error_append_hint(errp, "Adjust the number of cpus to %d "
4304                           "or try to raise the number of threads per core\n",
4305                           vcpu_id * ms->smp.threads / spapr->vsmt);
4306         return;
4307     }
4308 
4309     cpu->vcpu_id = vcpu_id;
4310 }
4311 
4312 PowerPCCPU *spapr_find_cpu(int vcpu_id)
4313 {
4314     CPUState *cs;
4315 
4316     CPU_FOREACH(cs) {
4317         PowerPCCPU *cpu = POWERPC_CPU(cs);
4318 
4319         if (spapr_get_vcpu_id(cpu) == vcpu_id) {
4320             return cpu;
4321         }
4322     }
4323 
4324     return NULL;
4325 }
4326 
4327 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
4328 {
4329     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
4330 
4331     /* These are only called by TCG, KVM maintains dispatch state */
4332 
4333     spapr_cpu->prod = false;
4334     if (spapr_cpu->vpa_addr) {
4335         CPUState *cs = CPU(cpu);
4336         uint32_t dispatch;
4337 
4338         dispatch = ldl_be_phys(cs->as,
4339                                spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER);
4340         dispatch++;
4341         if ((dispatch & 1) != 0) {
4342             qemu_log_mask(LOG_GUEST_ERROR,
4343                           "VPA: incorrect dispatch counter value for "
4344                           "dispatched partition %u, correcting.\n", dispatch);
4345             dispatch++;
4346         }
4347         stl_be_phys(cs->as,
4348                     spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch);
4349     }
4350 }
4351 
4352 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
4353 {
4354     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
4355 
4356     if (spapr_cpu->vpa_addr) {
4357         CPUState *cs = CPU(cpu);
4358         uint32_t dispatch;
4359 
4360         dispatch = ldl_be_phys(cs->as,
4361                                spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER);
4362         dispatch++;
4363         if ((dispatch & 1) != 1) {
4364             qemu_log_mask(LOG_GUEST_ERROR,
4365                           "VPA: incorrect dispatch counter value for "
4366                           "preempted partition %u, correcting.\n", dispatch);
4367             dispatch++;
4368         }
4369         stl_be_phys(cs->as,
4370                     spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch);
4371     }
4372 }
4373 
4374 static void spapr_machine_class_init(ObjectClass *oc, void *data)
4375 {
4376     MachineClass *mc = MACHINE_CLASS(oc);
4377     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
4378     FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
4379     NMIClass *nc = NMI_CLASS(oc);
4380     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
4381     PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
4382     XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
4383     InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
4384     XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
4385 
4386     mc->desc = "pSeries Logical Partition (PAPR compliant)";
4387     mc->ignore_boot_device_suffixes = true;
4388 
4389     /*
4390      * We set up the default / latest behaviour here.  The class_init
4391      * functions for the specific versioned machine types can override
4392      * these details for backwards compatibility
4393      */
4394     mc->init = spapr_machine_init;
4395     mc->reset = spapr_machine_reset;
4396     mc->block_default_type = IF_SCSI;
4397     mc->max_cpus = 1024;
4398     mc->no_parallel = 1;
4399     mc->default_boot_order = "";
4400     mc->default_ram_size = 512 * MiB;
4401     mc->default_ram_id = "ppc_spapr.ram";
4402     mc->default_display = "std";
4403     mc->kvm_type = spapr_kvm_type;
4404     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE);
4405     mc->pci_allow_0_address = true;
4406     assert(!mc->get_hotplug_handler);
4407     mc->get_hotplug_handler = spapr_get_hotplug_handler;
4408     hc->pre_plug = spapr_machine_device_pre_plug;
4409     hc->plug = spapr_machine_device_plug;
4410     mc->cpu_index_to_instance_props = spapr_cpu_index_to_props;
4411     mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id;
4412     mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
4413     hc->unplug_request = spapr_machine_device_unplug_request;
4414     hc->unplug = spapr_machine_device_unplug;
4415 
4416     smc->dr_lmb_enabled = true;
4417     smc->update_dt_enabled = true;
4418     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
4419     mc->has_hotpluggable_cpus = true;
4420     mc->nvdimm_supported = true;
4421     smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
4422     fwc->get_dev_path = spapr_get_fw_dev_path;
4423     nc->nmi_monitor_handler = spapr_nmi;
4424     smc->phb_placement = spapr_phb_placement;
4425     vhc->hypercall = emulate_spapr_hypercall;
4426     vhc->hpt_mask = spapr_hpt_mask;
4427     vhc->map_hptes = spapr_map_hptes;
4428     vhc->unmap_hptes = spapr_unmap_hptes;
4429     vhc->hpte_set_c = spapr_hpte_set_c;
4430     vhc->hpte_set_r = spapr_hpte_set_r;
4431     vhc->get_pate = spapr_get_pate;
4432     vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr;
4433     vhc->cpu_exec_enter = spapr_cpu_exec_enter;
4434     vhc->cpu_exec_exit = spapr_cpu_exec_exit;
4435     xic->ics_get = spapr_ics_get;
4436     xic->ics_resend = spapr_ics_resend;
4437     xic->icp_get = spapr_icp_get;
4438     ispc->print_info = spapr_pic_print_info;
4439     /* Force NUMA node memory size to be a multiple of
4440      * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
4441      * in which LMBs are represented and hot-added
4442      */
4443     mc->numa_mem_align_shift = 28;
4444     mc->auto_enable_numa = true;
4445 
4446     smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF;
4447     smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON;
4448     smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON;
4449     smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
4450     smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
4451     smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND;
4452     smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */
4453     smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF;
4454     smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON;
4455     smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON;
4456     smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON;
4457     spapr_caps_add_properties(smc);
4458     smc->irq = &spapr_irq_dual;
4459     smc->dr_phb_enabled = true;
4460     smc->linux_pci_probe = true;
4461     smc->smp_threads_vsmt = true;
4462     smc->nr_xirqs = SPAPR_NR_XIRQS;
4463     xfc->match_nvt = spapr_match_nvt;
4464 }
4465 
4466 static const TypeInfo spapr_machine_info = {
4467     .name          = TYPE_SPAPR_MACHINE,
4468     .parent        = TYPE_MACHINE,
4469     .abstract      = true,
4470     .instance_size = sizeof(SpaprMachineState),
4471     .instance_init = spapr_instance_init,
4472     .instance_finalize = spapr_machine_finalizefn,
4473     .class_size    = sizeof(SpaprMachineClass),
4474     .class_init    = spapr_machine_class_init,
4475     .interfaces = (InterfaceInfo[]) {
4476         { TYPE_FW_PATH_PROVIDER },
4477         { TYPE_NMI },
4478         { TYPE_HOTPLUG_HANDLER },
4479         { TYPE_PPC_VIRTUAL_HYPERVISOR },
4480         { TYPE_XICS_FABRIC },
4481         { TYPE_INTERRUPT_STATS_PROVIDER },
4482         { TYPE_XIVE_FABRIC },
4483         { }
4484     },
4485 };
4486 
4487 static void spapr_machine_latest_class_options(MachineClass *mc)
4488 {
4489     mc->alias = "pseries";
4490     mc->is_default = true;
4491 }
4492 
4493 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest)                 \
4494     static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4495                                                     void *data)      \
4496     {                                                                \
4497         MachineClass *mc = MACHINE_CLASS(oc);                        \
4498         spapr_machine_##suffix##_class_options(mc);                  \
4499         if (latest) {                                                \
4500             spapr_machine_latest_class_options(mc);                  \
4501         }                                                            \
4502     }                                                                \
4503     static const TypeInfo spapr_machine_##suffix##_info = {          \
4504         .name = MACHINE_TYPE_NAME("pseries-" verstr),                \
4505         .parent = TYPE_SPAPR_MACHINE,                                \
4506         .class_init = spapr_machine_##suffix##_class_init,           \
4507     };                                                               \
4508     static void spapr_machine_register_##suffix(void)                \
4509     {                                                                \
4510         type_register(&spapr_machine_##suffix##_info);               \
4511     }                                                                \
4512     type_init(spapr_machine_register_##suffix)
4513 
4514 /*
4515  * pseries-5.2
4516  */
4517 static void spapr_machine_5_2_class_options(MachineClass *mc)
4518 {
4519     /* Defaults for the latest behaviour inherited from the base class */
4520 }
4521 
4522 DEFINE_SPAPR_MACHINE(5_2, "5.2", true);
4523 
4524 /*
4525  * pseries-5.1
4526  */
4527 static void spapr_machine_5_1_class_options(MachineClass *mc)
4528 {
4529     spapr_machine_5_2_class_options(mc);
4530     compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
4531 }
4532 
4533 DEFINE_SPAPR_MACHINE(5_1, "5.1", false);
4534 
4535 /*
4536  * pseries-5.0
4537  */
4538 static void spapr_machine_5_0_class_options(MachineClass *mc)
4539 {
4540     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4541     static GlobalProperty compat[] = {
4542         { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" },
4543     };
4544 
4545     spapr_machine_5_1_class_options(mc);
4546     compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
4547     compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4548     mc->numa_mem_supported = true;
4549     smc->pre_5_1_assoc_refpoints = true;
4550 }
4551 
4552 DEFINE_SPAPR_MACHINE(5_0, "5.0", false);
4553 
4554 /*
4555  * pseries-4.2
4556  */
4557 static void spapr_machine_4_2_class_options(MachineClass *mc)
4558 {
4559     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4560 
4561     spapr_machine_5_0_class_options(mc);
4562     compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
4563     smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF;
4564     smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF;
4565     smc->rma_limit = 16 * GiB;
4566     mc->nvdimm_supported = false;
4567 }
4568 
4569 DEFINE_SPAPR_MACHINE(4_2, "4.2", false);
4570 
4571 /*
4572  * pseries-4.1
4573  */
4574 static void spapr_machine_4_1_class_options(MachineClass *mc)
4575 {
4576     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4577     static GlobalProperty compat[] = {
4578         /* Only allow 4kiB and 64kiB IOMMU pagesizes */
4579         { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" },
4580     };
4581 
4582     spapr_machine_4_2_class_options(mc);
4583     smc->linux_pci_probe = false;
4584     smc->smp_threads_vsmt = false;
4585     compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
4586     compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4587 }
4588 
4589 DEFINE_SPAPR_MACHINE(4_1, "4.1", false);
4590 
4591 /*
4592  * pseries-4.0
4593  */
4594 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index,
4595                               uint64_t *buid, hwaddr *pio,
4596                               hwaddr *mmio32, hwaddr *mmio64,
4597                               unsigned n_dma, uint32_t *liobns,
4598                               hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp)
4599 {
4600     spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns,
4601                         nv2gpa, nv2atsd, errp);
4602     *nv2gpa = 0;
4603     *nv2atsd = 0;
4604 }
4605 
4606 static void spapr_machine_4_0_class_options(MachineClass *mc)
4607 {
4608     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4609 
4610     spapr_machine_4_1_class_options(mc);
4611     compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
4612     smc->phb_placement = phb_placement_4_0;
4613     smc->irq = &spapr_irq_xics;
4614     smc->pre_4_1_migration = true;
4615 }
4616 
4617 DEFINE_SPAPR_MACHINE(4_0, "4.0", false);
4618 
4619 /*
4620  * pseries-3.1
4621  */
4622 static void spapr_machine_3_1_class_options(MachineClass *mc)
4623 {
4624     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4625 
4626     spapr_machine_4_0_class_options(mc);
4627     compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
4628 
4629     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
4630     smc->update_dt_enabled = false;
4631     smc->dr_phb_enabled = false;
4632     smc->broken_host_serial_model = true;
4633     smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN;
4634     smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN;
4635     smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN;
4636     smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF;
4637 }
4638 
4639 DEFINE_SPAPR_MACHINE(3_1, "3.1", false);
4640 
4641 /*
4642  * pseries-3.0
4643  */
4644 
4645 static void spapr_machine_3_0_class_options(MachineClass *mc)
4646 {
4647     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4648 
4649     spapr_machine_3_1_class_options(mc);
4650     compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
4651 
4652     smc->legacy_irq_allocation = true;
4653     smc->nr_xirqs = 0x400;
4654     smc->irq = &spapr_irq_xics_legacy;
4655 }
4656 
4657 DEFINE_SPAPR_MACHINE(3_0, "3.0", false);
4658 
4659 /*
4660  * pseries-2.12
4661  */
4662 static void spapr_machine_2_12_class_options(MachineClass *mc)
4663 {
4664     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4665     static GlobalProperty compat[] = {
4666         { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" },
4667         { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" },
4668     };
4669 
4670     spapr_machine_3_0_class_options(mc);
4671     compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
4672     compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4673 
4674     /* We depend on kvm_enabled() to choose a default value for the
4675      * hpt-max-page-size capability. Of course we can't do it here
4676      * because this is too early and the HW accelerator isn't initialzed
4677      * yet. Postpone this to machine init (see default_caps_with_cpu()).
4678      */
4679     smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0;
4680 }
4681 
4682 DEFINE_SPAPR_MACHINE(2_12, "2.12", false);
4683 
4684 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc)
4685 {
4686     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4687 
4688     spapr_machine_2_12_class_options(mc);
4689     smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
4690     smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
4691     smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD;
4692 }
4693 
4694 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false);
4695 
4696 /*
4697  * pseries-2.11
4698  */
4699 
4700 static void spapr_machine_2_11_class_options(MachineClass *mc)
4701 {
4702     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4703 
4704     spapr_machine_2_12_class_options(mc);
4705     smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON;
4706     compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
4707 }
4708 
4709 DEFINE_SPAPR_MACHINE(2_11, "2.11", false);
4710 
4711 /*
4712  * pseries-2.10
4713  */
4714 
4715 static void spapr_machine_2_10_class_options(MachineClass *mc)
4716 {
4717     spapr_machine_2_11_class_options(mc);
4718     compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
4719 }
4720 
4721 DEFINE_SPAPR_MACHINE(2_10, "2.10", false);
4722 
4723 /*
4724  * pseries-2.9
4725  */
4726 
4727 static void spapr_machine_2_9_class_options(MachineClass *mc)
4728 {
4729     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4730     static GlobalProperty compat[] = {
4731         { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" },
4732     };
4733 
4734     spapr_machine_2_10_class_options(mc);
4735     compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
4736     compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4737     smc->pre_2_10_has_unused_icps = true;
4738     smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
4739 }
4740 
4741 DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
4742 
4743 /*
4744  * pseries-2.8
4745  */
4746 
4747 static void spapr_machine_2_8_class_options(MachineClass *mc)
4748 {
4749     static GlobalProperty compat[] = {
4750         { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" },
4751     };
4752 
4753     spapr_machine_2_9_class_options(mc);
4754     compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
4755     compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4756     mc->numa_mem_align_shift = 23;
4757 }
4758 
4759 DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
4760 
4761 /*
4762  * pseries-2.7
4763  */
4764 
4765 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index,
4766                               uint64_t *buid, hwaddr *pio,
4767                               hwaddr *mmio32, hwaddr *mmio64,
4768                               unsigned n_dma, uint32_t *liobns,
4769                               hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp)
4770 {
4771     /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4772     const uint64_t base_buid = 0x800000020000000ULL;
4773     const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
4774     const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
4775     const hwaddr pio_offset = 0x80000000; /* 2 GiB */
4776     const uint32_t max_index = 255;
4777     const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */
4778 
4779     uint64_t ram_top = MACHINE(spapr)->ram_size;
4780     hwaddr phb0_base, phb_base;
4781     int i;
4782 
4783     /* Do we have device memory? */
4784     if (MACHINE(spapr)->maxram_size > ram_top) {
4785         /* Can't just use maxram_size, because there may be an
4786          * alignment gap between normal and device memory regions
4787          */
4788         ram_top = MACHINE(spapr)->device_memory->base +
4789             memory_region_size(&MACHINE(spapr)->device_memory->mr);
4790     }
4791 
4792     phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
4793 
4794     if (index > max_index) {
4795         error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
4796                    max_index);
4797         return;
4798     }
4799 
4800     *buid = base_buid + index;
4801     for (i = 0; i < n_dma; ++i) {
4802         liobns[i] = SPAPR_PCI_LIOBN(index, i);
4803     }
4804 
4805     phb_base = phb0_base + index * phb_spacing;
4806     *pio = phb_base + pio_offset;
4807     *mmio32 = phb_base + mmio_offset;
4808     /*
4809      * We don't set the 64-bit MMIO window, relying on the PHB's
4810      * fallback behaviour of automatically splitting a large "32-bit"
4811      * window into contiguous 32-bit and 64-bit windows
4812      */
4813 
4814     *nv2gpa = 0;
4815     *nv2atsd = 0;
4816 }
4817 
4818 static void spapr_machine_2_7_class_options(MachineClass *mc)
4819 {
4820     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4821     static GlobalProperty compat[] = {
4822         { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", },
4823         { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", },
4824         { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", },
4825         { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", },
4826     };
4827 
4828     spapr_machine_2_8_class_options(mc);
4829     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3");
4830     mc->default_machine_opts = "modern-hotplug-events=off";
4831     compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
4832     compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4833     smc->phb_placement = phb_placement_2_7;
4834 }
4835 
4836 DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
4837 
4838 /*
4839  * pseries-2.6
4840  */
4841 
4842 static void spapr_machine_2_6_class_options(MachineClass *mc)
4843 {
4844     static GlobalProperty compat[] = {
4845         { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" },
4846     };
4847 
4848     spapr_machine_2_7_class_options(mc);
4849     mc->has_hotpluggable_cpus = false;
4850     compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
4851     compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4852 }
4853 
4854 DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
4855 
4856 /*
4857  * pseries-2.5
4858  */
4859 
4860 static void spapr_machine_2_5_class_options(MachineClass *mc)
4861 {
4862     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4863     static GlobalProperty compat[] = {
4864         { "spapr-vlan", "use-rx-buffer-pools", "off" },
4865     };
4866 
4867     spapr_machine_2_6_class_options(mc);
4868     smc->use_ohci_by_default = true;
4869     compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len);
4870     compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4871 }
4872 
4873 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
4874 
4875 /*
4876  * pseries-2.4
4877  */
4878 
4879 static void spapr_machine_2_4_class_options(MachineClass *mc)
4880 {
4881     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4882 
4883     spapr_machine_2_5_class_options(mc);
4884     smc->dr_lmb_enabled = false;
4885     compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len);
4886 }
4887 
4888 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
4889 
4890 /*
4891  * pseries-2.3
4892  */
4893 
4894 static void spapr_machine_2_3_class_options(MachineClass *mc)
4895 {
4896     static GlobalProperty compat[] = {
4897         { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" },
4898     };
4899     spapr_machine_2_4_class_options(mc);
4900     compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len);
4901     compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4902 }
4903 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
4904 
4905 /*
4906  * pseries-2.2
4907  */
4908 
4909 static void spapr_machine_2_2_class_options(MachineClass *mc)
4910 {
4911     static GlobalProperty compat[] = {
4912         { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" },
4913     };
4914 
4915     spapr_machine_2_3_class_options(mc);
4916     compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len);
4917     compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4918     mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on";
4919 }
4920 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
4921 
4922 /*
4923  * pseries-2.1
4924  */
4925 
4926 static void spapr_machine_2_1_class_options(MachineClass *mc)
4927 {
4928     spapr_machine_2_2_class_options(mc);
4929     compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len);
4930 }
4931 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
4932 
4933 static void spapr_machine_register_types(void)
4934 {
4935     type_register_static(&spapr_machine_info);
4936 }
4937 
4938 type_init(spapr_machine_register_types)
4939