1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/numa.h" 31 #include "hw/hw.h" 32 #include "qemu/log.h" 33 #include "hw/fw-path-provider.h" 34 #include "elf.h" 35 #include "net/net.h" 36 #include "sysemu/device_tree.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/kvm.h" 40 #include "sysemu/device_tree.h" 41 #include "kvm_ppc.h" 42 #include "migration/migration.h" 43 #include "mmu-hash64.h" 44 #include "qom/cpu.h" 45 46 #include "hw/boards.h" 47 #include "hw/ppc/ppc.h" 48 #include "hw/loader.h" 49 50 #include "hw/ppc/fdt.h" 51 #include "hw/ppc/spapr.h" 52 #include "hw/ppc/spapr_vio.h" 53 #include "hw/pci-host/spapr.h" 54 #include "hw/ppc/xics.h" 55 #include "hw/pci/msi.h" 56 57 #include "hw/pci/pci.h" 58 #include "hw/scsi/scsi.h" 59 #include "hw/virtio/virtio-scsi.h" 60 61 #include "exec/address-spaces.h" 62 #include "hw/usb.h" 63 #include "qemu/config-file.h" 64 #include "qemu/error-report.h" 65 #include "trace.h" 66 #include "hw/nmi.h" 67 68 #include "hw/compat.h" 69 #include "qemu/cutils.h" 70 #include "hw/ppc/spapr_cpu_core.h" 71 #include "qmp-commands.h" 72 73 #include <libfdt.h> 74 75 /* SLOF memory layout: 76 * 77 * SLOF raw image loaded at 0, copies its romfs right below the flat 78 * device-tree, then position SLOF itself 31M below that 79 * 80 * So we set FW_OVERHEAD to 40MB which should account for all of that 81 * and more 82 * 83 * We load our kernel at 4M, leaving space for SLOF initial image 84 */ 85 #define FDT_MAX_SIZE 0x100000 86 #define RTAS_MAX_SIZE 0x10000 87 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 88 #define FW_MAX_SIZE 0x400000 89 #define FW_FILE_NAME "slof.bin" 90 #define FW_OVERHEAD 0x2800000 91 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 92 93 #define MIN_RMA_SLOF 128UL 94 95 #define PHANDLE_XICP 0x00001111 96 97 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 98 99 static XICSState *try_create_xics(const char *type, int nr_servers, 100 int nr_irqs, Error **errp) 101 { 102 Error *err = NULL; 103 DeviceState *dev; 104 105 dev = qdev_create(NULL, type); 106 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 107 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 108 object_property_set_bool(OBJECT(dev), true, "realized", &err); 109 if (err) { 110 error_propagate(errp, err); 111 object_unparent(OBJECT(dev)); 112 return NULL; 113 } 114 return XICS_COMMON(dev); 115 } 116 117 static XICSState *xics_system_init(MachineState *machine, 118 int nr_servers, int nr_irqs, Error **errp) 119 { 120 XICSState *xics = NULL; 121 122 if (kvm_enabled()) { 123 Error *err = NULL; 124 125 if (machine_kernel_irqchip_allowed(machine)) { 126 xics = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs, 127 &err); 128 } 129 if (machine_kernel_irqchip_required(machine) && !xics) { 130 error_reportf_err(err, 131 "kernel_irqchip requested but unavailable: "); 132 } else { 133 error_free(err); 134 } 135 } 136 137 if (!xics) { 138 xics = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp); 139 } 140 141 return xics; 142 } 143 144 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 145 int smt_threads) 146 { 147 int i, ret = 0; 148 uint32_t servers_prop[smt_threads]; 149 uint32_t gservers_prop[smt_threads * 2]; 150 int index = ppc_get_vcpu_dt_id(cpu); 151 152 if (cpu->cpu_version) { 153 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); 154 if (ret < 0) { 155 return ret; 156 } 157 } 158 159 /* Build interrupt servers and gservers properties */ 160 for (i = 0; i < smt_threads; i++) { 161 servers_prop[i] = cpu_to_be32(index + i); 162 /* Hack, direct the group queues back to cpu 0 */ 163 gservers_prop[i*2] = cpu_to_be32(index + i); 164 gservers_prop[i*2 + 1] = 0; 165 } 166 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 167 servers_prop, sizeof(servers_prop)); 168 if (ret < 0) { 169 return ret; 170 } 171 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 172 gservers_prop, sizeof(gservers_prop)); 173 174 return ret; 175 } 176 177 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) 178 { 179 int ret = 0; 180 PowerPCCPU *cpu = POWERPC_CPU(cs); 181 int index = ppc_get_vcpu_dt_id(cpu); 182 uint32_t associativity[] = {cpu_to_be32(0x5), 183 cpu_to_be32(0x0), 184 cpu_to_be32(0x0), 185 cpu_to_be32(0x0), 186 cpu_to_be32(cs->numa_node), 187 cpu_to_be32(index)}; 188 189 /* Advertise NUMA via ibm,associativity */ 190 if (nb_numa_nodes > 1) { 191 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 192 sizeof(associativity)); 193 } 194 195 return ret; 196 } 197 198 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 199 { 200 int ret = 0, offset, cpus_offset; 201 CPUState *cs; 202 char cpu_model[32]; 203 int smt = kvmppc_smt_threads(); 204 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 205 206 CPU_FOREACH(cs) { 207 PowerPCCPU *cpu = POWERPC_CPU(cs); 208 DeviceClass *dc = DEVICE_GET_CLASS(cs); 209 int index = ppc_get_vcpu_dt_id(cpu); 210 211 if ((index % smt) != 0) { 212 continue; 213 } 214 215 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 216 217 cpus_offset = fdt_path_offset(fdt, "/cpus"); 218 if (cpus_offset < 0) { 219 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 220 "cpus"); 221 if (cpus_offset < 0) { 222 return cpus_offset; 223 } 224 } 225 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 226 if (offset < 0) { 227 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 228 if (offset < 0) { 229 return offset; 230 } 231 } 232 233 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 234 pft_size_prop, sizeof(pft_size_prop)); 235 if (ret < 0) { 236 return ret; 237 } 238 239 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); 240 if (ret < 0) { 241 return ret; 242 } 243 244 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 245 ppc_get_compat_smt_threads(cpu)); 246 if (ret < 0) { 247 return ret; 248 } 249 } 250 return ret; 251 } 252 253 static hwaddr spapr_node0_size(void) 254 { 255 MachineState *machine = MACHINE(qdev_get_machine()); 256 257 if (nb_numa_nodes) { 258 int i; 259 for (i = 0; i < nb_numa_nodes; ++i) { 260 if (numa_info[i].node_mem) { 261 return MIN(pow2floor(numa_info[i].node_mem), 262 machine->ram_size); 263 } 264 } 265 } 266 return machine->ram_size; 267 } 268 269 static void add_str(GString *s, const gchar *s1) 270 { 271 g_string_append_len(s, s1, strlen(s1) + 1); 272 } 273 274 static void *spapr_create_fdt_skel(hwaddr initrd_base, 275 hwaddr initrd_size, 276 hwaddr kernel_size, 277 bool little_endian, 278 const char *kernel_cmdline, 279 uint32_t epow_irq) 280 { 281 void *fdt; 282 uint32_t start_prop = cpu_to_be32(initrd_base); 283 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 284 GString *hypertas = g_string_sized_new(256); 285 GString *qemu_hypertas = g_string_sized_new(256); 286 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 287 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)}; 288 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 289 char *buf; 290 291 add_str(hypertas, "hcall-pft"); 292 add_str(hypertas, "hcall-term"); 293 add_str(hypertas, "hcall-dabr"); 294 add_str(hypertas, "hcall-interrupt"); 295 add_str(hypertas, "hcall-tce"); 296 add_str(hypertas, "hcall-vio"); 297 add_str(hypertas, "hcall-splpar"); 298 add_str(hypertas, "hcall-bulk"); 299 add_str(hypertas, "hcall-set-mode"); 300 add_str(hypertas, "hcall-sprg0"); 301 add_str(hypertas, "hcall-copy"); 302 add_str(hypertas, "hcall-debug"); 303 add_str(qemu_hypertas, "hcall-memop1"); 304 305 fdt = g_malloc0(FDT_MAX_SIZE); 306 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 307 308 if (kernel_size) { 309 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 310 } 311 if (initrd_size) { 312 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 313 } 314 _FDT((fdt_finish_reservemap(fdt))); 315 316 /* Root node */ 317 _FDT((fdt_begin_node(fdt, ""))); 318 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 319 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 320 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 321 322 /* 323 * Add info to guest to indentify which host is it being run on 324 * and what is the uuid of the guest 325 */ 326 if (kvmppc_get_host_model(&buf)) { 327 _FDT((fdt_property_string(fdt, "host-model", buf))); 328 g_free(buf); 329 } 330 if (kvmppc_get_host_serial(&buf)) { 331 _FDT((fdt_property_string(fdt, "host-serial", buf))); 332 g_free(buf); 333 } 334 335 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 336 337 _FDT((fdt_property_string(fdt, "vm,uuid", buf))); 338 if (qemu_uuid_set) { 339 _FDT((fdt_property_string(fdt, "system-id", buf))); 340 } 341 g_free(buf); 342 343 if (qemu_get_vm_name()) { 344 _FDT((fdt_property_string(fdt, "ibm,partition-name", 345 qemu_get_vm_name()))); 346 } 347 348 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 349 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 350 351 /* /chosen */ 352 _FDT((fdt_begin_node(fdt, "chosen"))); 353 354 /* Set Form1_affinity */ 355 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 356 357 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 358 _FDT((fdt_property(fdt, "linux,initrd-start", 359 &start_prop, sizeof(start_prop)))); 360 _FDT((fdt_property(fdt, "linux,initrd-end", 361 &end_prop, sizeof(end_prop)))); 362 if (kernel_size) { 363 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 364 cpu_to_be64(kernel_size) }; 365 366 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 367 if (little_endian) { 368 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 369 } 370 } 371 if (boot_menu) { 372 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); 373 } 374 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 375 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 376 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 377 378 _FDT((fdt_end_node(fdt))); 379 380 /* RTAS */ 381 _FDT((fdt_begin_node(fdt, "rtas"))); 382 383 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 384 add_str(hypertas, "hcall-multi-tce"); 385 } 386 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, 387 hypertas->len))); 388 g_string_free(hypertas, TRUE); 389 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, 390 qemu_hypertas->len))); 391 g_string_free(qemu_hypertas, TRUE); 392 393 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 394 refpoints, sizeof(refpoints)))); 395 396 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 397 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate", 398 RTAS_EVENT_SCAN_RATE))); 399 400 if (msi_nonbroken) { 401 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0))); 402 } 403 404 /* 405 * According to PAPR, rtas ibm,os-term does not guarantee a return 406 * back to the guest cpu. 407 * 408 * While an additional ibm,extended-os-term property indicates that 409 * rtas call return will always occur. Set this property. 410 */ 411 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0))); 412 413 _FDT((fdt_end_node(fdt))); 414 415 /* interrupt controller */ 416 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 417 418 _FDT((fdt_property_string(fdt, "device_type", 419 "PowerPC-External-Interrupt-Presentation"))); 420 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 421 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 422 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 423 interrupt_server_ranges_prop, 424 sizeof(interrupt_server_ranges_prop)))); 425 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 426 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 427 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 428 429 _FDT((fdt_end_node(fdt))); 430 431 /* vdevice */ 432 _FDT((fdt_begin_node(fdt, "vdevice"))); 433 434 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 435 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 436 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 437 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 438 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 439 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 440 441 _FDT((fdt_end_node(fdt))); 442 443 /* event-sources */ 444 spapr_events_fdt_skel(fdt, epow_irq); 445 446 /* /hypervisor node */ 447 if (kvm_enabled()) { 448 uint8_t hypercall[16]; 449 450 /* indicate KVM hypercall interface */ 451 _FDT((fdt_begin_node(fdt, "hypervisor"))); 452 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); 453 if (kvmppc_has_cap_fixup_hcalls()) { 454 /* 455 * Older KVM versions with older guest kernels were broken with the 456 * magic page, don't allow the guest to map it. 457 */ 458 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 459 sizeof(hypercall))) { 460 _FDT((fdt_property(fdt, "hcall-instructions", hypercall, 461 sizeof(hypercall)))); 462 } 463 } 464 _FDT((fdt_end_node(fdt))); 465 } 466 467 _FDT((fdt_end_node(fdt))); /* close root node */ 468 _FDT((fdt_finish(fdt))); 469 470 return fdt; 471 } 472 473 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 474 hwaddr size) 475 { 476 uint32_t associativity[] = { 477 cpu_to_be32(0x4), /* length */ 478 cpu_to_be32(0x0), cpu_to_be32(0x0), 479 cpu_to_be32(0x0), cpu_to_be32(nodeid) 480 }; 481 char mem_name[32]; 482 uint64_t mem_reg_property[2]; 483 int off; 484 485 mem_reg_property[0] = cpu_to_be64(start); 486 mem_reg_property[1] = cpu_to_be64(size); 487 488 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 489 off = fdt_add_subnode(fdt, 0, mem_name); 490 _FDT(off); 491 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 492 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 493 sizeof(mem_reg_property)))); 494 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 495 sizeof(associativity)))); 496 return off; 497 } 498 499 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 500 { 501 MachineState *machine = MACHINE(spapr); 502 hwaddr mem_start, node_size; 503 int i, nb_nodes = nb_numa_nodes; 504 NodeInfo *nodes = numa_info; 505 NodeInfo ramnode; 506 507 /* No NUMA nodes, assume there is just one node with whole RAM */ 508 if (!nb_numa_nodes) { 509 nb_nodes = 1; 510 ramnode.node_mem = machine->ram_size; 511 nodes = &ramnode; 512 } 513 514 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 515 if (!nodes[i].node_mem) { 516 continue; 517 } 518 if (mem_start >= machine->ram_size) { 519 node_size = 0; 520 } else { 521 node_size = nodes[i].node_mem; 522 if (node_size > machine->ram_size - mem_start) { 523 node_size = machine->ram_size - mem_start; 524 } 525 } 526 if (!mem_start) { 527 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 528 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 529 mem_start += spapr->rma_size; 530 node_size -= spapr->rma_size; 531 } 532 for ( ; node_size; ) { 533 hwaddr sizetmp = pow2floor(node_size); 534 535 /* mem_start != 0 here */ 536 if (ctzl(mem_start) < ctzl(sizetmp)) { 537 sizetmp = 1ULL << ctzl(mem_start); 538 } 539 540 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 541 node_size -= sizetmp; 542 mem_start += sizetmp; 543 } 544 } 545 546 return 0; 547 } 548 549 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 550 sPAPRMachineState *spapr) 551 { 552 PowerPCCPU *cpu = POWERPC_CPU(cs); 553 CPUPPCState *env = &cpu->env; 554 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 555 int index = ppc_get_vcpu_dt_id(cpu); 556 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 557 0xffffffff, 0xffffffff}; 558 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 559 : SPAPR_TIMEBASE_FREQ; 560 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 561 uint32_t page_sizes_prop[64]; 562 size_t page_sizes_prop_size; 563 uint32_t vcpus_per_socket = smp_threads * smp_cores; 564 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 565 sPAPRDRConnector *drc; 566 sPAPRDRConnectorClass *drck; 567 int drc_index; 568 569 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index); 570 if (drc) { 571 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 572 drc_index = drck->get_index(drc); 573 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 574 } 575 576 /* Note: we keep CI large pages off for now because a 64K capable guest 577 * provisioned with large pages might otherwise try to map a qemu 578 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 579 * even if that qemu runs on a 4k host. 580 * 581 * We can later add this bit back when we are confident this is not 582 * an issue (!HV KVM or 64K host) 583 */ 584 uint8_t pa_features_206[] = { 6, 0, 585 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 586 uint8_t pa_features_207[] = { 24, 0, 587 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 588 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 589 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 590 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 591 uint8_t *pa_features; 592 size_t pa_size; 593 594 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 595 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 596 597 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 598 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 599 env->dcache_line_size))); 600 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 601 env->dcache_line_size))); 602 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 603 env->icache_line_size))); 604 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 605 env->icache_line_size))); 606 607 if (pcc->l1_dcache_size) { 608 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 609 pcc->l1_dcache_size))); 610 } else { 611 error_report("Warning: Unknown L1 dcache size for cpu"); 612 } 613 if (pcc->l1_icache_size) { 614 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 615 pcc->l1_icache_size))); 616 } else { 617 error_report("Warning: Unknown L1 icache size for cpu"); 618 } 619 620 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 621 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 622 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 623 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 624 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 625 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 626 627 if (env->spr_cb[SPR_PURR].oea_read) { 628 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 629 } 630 631 if (env->mmu_model & POWERPC_MMU_1TSEG) { 632 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 633 segs, sizeof(segs)))); 634 } 635 636 /* Advertise VMX/VSX (vector extensions) if available 637 * 0 / no property == no vector extensions 638 * 1 == VMX / Altivec available 639 * 2 == VSX available */ 640 if (env->insns_flags & PPC_ALTIVEC) { 641 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 642 643 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 644 } 645 646 /* Advertise DFP (Decimal Floating Point) if available 647 * 0 / no property == no DFP 648 * 1 == DFP available */ 649 if (env->insns_flags2 & PPC2_DFP) { 650 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 651 } 652 653 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 654 sizeof(page_sizes_prop)); 655 if (page_sizes_prop_size) { 656 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 657 page_sizes_prop, page_sizes_prop_size))); 658 } 659 660 /* Do the ibm,pa-features property, adjust it for ci-large-pages */ 661 if (env->mmu_model == POWERPC_MMU_2_06) { 662 pa_features = pa_features_206; 663 pa_size = sizeof(pa_features_206); 664 } else /* env->mmu_model == POWERPC_MMU_2_07 */ { 665 pa_features = pa_features_207; 666 pa_size = sizeof(pa_features_207); 667 } 668 if (env->ci_large_pages) { 669 pa_features[3] |= 0x20; 670 } 671 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 672 673 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 674 cs->cpu_index / vcpus_per_socket))); 675 676 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 677 pft_size_prop, sizeof(pft_size_prop)))); 678 679 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); 680 681 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 682 ppc_get_compat_smt_threads(cpu))); 683 } 684 685 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 686 { 687 CPUState *cs; 688 int cpus_offset; 689 char *nodename; 690 int smt = kvmppc_smt_threads(); 691 692 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 693 _FDT(cpus_offset); 694 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 695 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 696 697 /* 698 * We walk the CPUs in reverse order to ensure that CPU DT nodes 699 * created by fdt_add_subnode() end up in the right order in FDT 700 * for the guest kernel the enumerate the CPUs correctly. 701 */ 702 CPU_FOREACH_REVERSE(cs) { 703 PowerPCCPU *cpu = POWERPC_CPU(cs); 704 int index = ppc_get_vcpu_dt_id(cpu); 705 DeviceClass *dc = DEVICE_GET_CLASS(cs); 706 int offset; 707 708 if ((index % smt) != 0) { 709 continue; 710 } 711 712 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 713 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 714 g_free(nodename); 715 _FDT(offset); 716 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 717 } 718 719 } 720 721 /* 722 * Adds ibm,dynamic-reconfiguration-memory node. 723 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 724 * of this device tree node. 725 */ 726 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 727 { 728 MachineState *machine = MACHINE(spapr); 729 int ret, i, offset; 730 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 731 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 732 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 733 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 734 memory_region_size(&spapr->hotplug_memory.mr)) / 735 lmb_size; 736 uint32_t *int_buf, *cur_index, buf_len; 737 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 738 739 /* 740 * Don't create the node if there is no hotpluggable memory 741 */ 742 if (machine->ram_size == machine->maxram_size) { 743 return 0; 744 } 745 746 /* 747 * Allocate enough buffer size to fit in ibm,dynamic-memory 748 * or ibm,associativity-lookup-arrays 749 */ 750 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 751 * sizeof(uint32_t); 752 cur_index = int_buf = g_malloc0(buf_len); 753 754 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 755 756 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 757 sizeof(prop_lmb_size)); 758 if (ret < 0) { 759 goto out; 760 } 761 762 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 763 if (ret < 0) { 764 goto out; 765 } 766 767 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 768 if (ret < 0) { 769 goto out; 770 } 771 772 /* ibm,dynamic-memory */ 773 int_buf[0] = cpu_to_be32(nr_lmbs); 774 cur_index++; 775 for (i = 0; i < nr_lmbs; i++) { 776 uint64_t addr = i * lmb_size; 777 uint32_t *dynamic_memory = cur_index; 778 779 if (i >= hotplug_lmb_start) { 780 sPAPRDRConnector *drc; 781 sPAPRDRConnectorClass *drck; 782 783 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i); 784 g_assert(drc); 785 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 786 787 dynamic_memory[0] = cpu_to_be32(addr >> 32); 788 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 789 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); 790 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 791 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 792 if (memory_region_present(get_system_memory(), addr)) { 793 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 794 } else { 795 dynamic_memory[5] = cpu_to_be32(0); 796 } 797 } else { 798 /* 799 * LMB information for RMA, boot time RAM and gap b/n RAM and 800 * hotplug memory region -- all these are marked as reserved 801 * and as having no valid DRC. 802 */ 803 dynamic_memory[0] = cpu_to_be32(addr >> 32); 804 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 805 dynamic_memory[2] = cpu_to_be32(0); 806 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 807 dynamic_memory[4] = cpu_to_be32(-1); 808 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 809 SPAPR_LMB_FLAGS_DRC_INVALID); 810 } 811 812 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 813 } 814 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 815 if (ret < 0) { 816 goto out; 817 } 818 819 /* ibm,associativity-lookup-arrays */ 820 cur_index = int_buf; 821 int_buf[0] = cpu_to_be32(nr_nodes); 822 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 823 cur_index += 2; 824 for (i = 0; i < nr_nodes; i++) { 825 uint32_t associativity[] = { 826 cpu_to_be32(0x0), 827 cpu_to_be32(0x0), 828 cpu_to_be32(0x0), 829 cpu_to_be32(i) 830 }; 831 memcpy(cur_index, associativity, sizeof(associativity)); 832 cur_index += 4; 833 } 834 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 835 (cur_index - int_buf) * sizeof(uint32_t)); 836 out: 837 g_free(int_buf); 838 return ret; 839 } 840 841 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 842 target_ulong addr, target_ulong size, 843 bool cpu_update, bool memory_update) 844 { 845 void *fdt, *fdt_skel; 846 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 847 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 848 849 size -= sizeof(hdr); 850 851 /* Create sceleton */ 852 fdt_skel = g_malloc0(size); 853 _FDT((fdt_create(fdt_skel, size))); 854 _FDT((fdt_begin_node(fdt_skel, ""))); 855 _FDT((fdt_end_node(fdt_skel))); 856 _FDT((fdt_finish(fdt_skel))); 857 fdt = g_malloc0(size); 858 _FDT((fdt_open_into(fdt_skel, fdt, size))); 859 g_free(fdt_skel); 860 861 /* Fixup cpu nodes */ 862 if (cpu_update) { 863 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 864 } 865 866 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 867 if (memory_update && smc->dr_lmb_enabled) { 868 _FDT((spapr_populate_drconf_memory(spapr, fdt))); 869 } 870 871 /* Pack resulting tree */ 872 _FDT((fdt_pack(fdt))); 873 874 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 875 trace_spapr_cas_failed(size); 876 return -1; 877 } 878 879 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 880 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 881 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 882 g_free(fdt); 883 884 return 0; 885 } 886 887 static void spapr_finalize_fdt(sPAPRMachineState *spapr, 888 hwaddr fdt_addr, 889 hwaddr rtas_addr, 890 hwaddr rtas_size) 891 { 892 MachineState *machine = MACHINE(qdev_get_machine()); 893 MachineClass *mc = MACHINE_GET_CLASS(machine); 894 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 895 const char *boot_device = machine->boot_order; 896 int ret, i; 897 size_t cb = 0; 898 char *bootlist; 899 void *fdt; 900 sPAPRPHBState *phb; 901 902 fdt = g_malloc(FDT_MAX_SIZE); 903 904 /* open out the base tree into a temp buffer for the final tweaks */ 905 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 906 907 ret = spapr_populate_memory(spapr, fdt); 908 if (ret < 0) { 909 error_report("couldn't setup memory nodes in fdt"); 910 exit(1); 911 } 912 913 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 914 if (ret < 0) { 915 error_report("couldn't setup vio devices in fdt"); 916 exit(1); 917 } 918 919 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 920 ret = spapr_rng_populate_dt(fdt); 921 if (ret < 0) { 922 error_report("could not set up rng device in the fdt"); 923 exit(1); 924 } 925 } 926 927 QLIST_FOREACH(phb, &spapr->phbs, list) { 928 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 929 if (ret < 0) { 930 error_report("couldn't setup PCI devices in fdt"); 931 exit(1); 932 } 933 } 934 935 /* RTAS */ 936 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 937 if (ret < 0) { 938 error_report("Couldn't set up RTAS device tree properties"); 939 } 940 941 /* cpus */ 942 spapr_populate_cpus_dt_node(fdt, spapr); 943 944 bootlist = get_boot_devices_list(&cb, true); 945 if (cb && bootlist) { 946 int offset = fdt_path_offset(fdt, "/chosen"); 947 if (offset < 0) { 948 exit(1); 949 } 950 for (i = 0; i < cb; i++) { 951 if (bootlist[i] == '\n') { 952 bootlist[i] = ' '; 953 } 954 955 } 956 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); 957 } 958 959 if (boot_device && strlen(boot_device)) { 960 int offset = fdt_path_offset(fdt, "/chosen"); 961 962 if (offset < 0) { 963 exit(1); 964 } 965 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device); 966 } 967 968 if (!spapr->has_graphics) { 969 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 970 } 971 972 if (smc->dr_lmb_enabled) { 973 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 974 } 975 976 if (mc->query_hotpluggable_cpus) { 977 int offset = fdt_path_offset(fdt, "/cpus"); 978 ret = spapr_drc_populate_dt(fdt, offset, NULL, 979 SPAPR_DR_CONNECTOR_TYPE_CPU); 980 if (ret < 0) { 981 error_report("Couldn't set up CPU DR device tree properties"); 982 exit(1); 983 } 984 } 985 986 _FDT((fdt_pack(fdt))); 987 988 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 989 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 990 fdt_totalsize(fdt), FDT_MAX_SIZE); 991 exit(1); 992 } 993 994 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 995 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 996 997 g_free(bootlist); 998 g_free(fdt); 999 } 1000 1001 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1002 { 1003 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1004 } 1005 1006 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 1007 { 1008 CPUPPCState *env = &cpu->env; 1009 1010 if (msr_pr) { 1011 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1012 env->gpr[3] = H_PRIVILEGE; 1013 } else { 1014 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1015 } 1016 } 1017 1018 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1019 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1020 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1021 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1022 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1023 1024 /* 1025 * Get the fd to access the kernel htab, re-opening it if necessary 1026 */ 1027 static int get_htab_fd(sPAPRMachineState *spapr) 1028 { 1029 if (spapr->htab_fd >= 0) { 1030 return spapr->htab_fd; 1031 } 1032 1033 spapr->htab_fd = kvmppc_get_htab_fd(false); 1034 if (spapr->htab_fd < 0) { 1035 error_report("Unable to open fd for reading hash table from KVM: %s", 1036 strerror(errno)); 1037 } 1038 1039 return spapr->htab_fd; 1040 } 1041 1042 static void close_htab_fd(sPAPRMachineState *spapr) 1043 { 1044 if (spapr->htab_fd >= 0) { 1045 close(spapr->htab_fd); 1046 } 1047 spapr->htab_fd = -1; 1048 } 1049 1050 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1051 { 1052 int shift; 1053 1054 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1055 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1056 * that's much more than is needed for Linux guests */ 1057 shift = ctz64(pow2ceil(ramsize)) - 7; 1058 shift = MAX(shift, 18); /* Minimum architected size */ 1059 shift = MIN(shift, 46); /* Maximum architected size */ 1060 return shift; 1061 } 1062 1063 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1064 Error **errp) 1065 { 1066 long rc; 1067 1068 /* Clean up any HPT info from a previous boot */ 1069 g_free(spapr->htab); 1070 spapr->htab = NULL; 1071 spapr->htab_shift = 0; 1072 close_htab_fd(spapr); 1073 1074 rc = kvmppc_reset_htab(shift); 1075 if (rc < 0) { 1076 /* kernel-side HPT needed, but couldn't allocate one */ 1077 error_setg_errno(errp, errno, 1078 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1079 shift); 1080 /* This is almost certainly fatal, but if the caller really 1081 * wants to carry on with shift == 0, it's welcome to try */ 1082 } else if (rc > 0) { 1083 /* kernel-side HPT allocated */ 1084 if (rc != shift) { 1085 error_setg(errp, 1086 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1087 shift, rc); 1088 } 1089 1090 spapr->htab_shift = shift; 1091 spapr->htab = NULL; 1092 } else { 1093 /* kernel-side HPT not needed, allocate in userspace instead */ 1094 size_t size = 1ULL << shift; 1095 int i; 1096 1097 spapr->htab = qemu_memalign(size, size); 1098 if (!spapr->htab) { 1099 error_setg_errno(errp, errno, 1100 "Could not allocate HPT of order %d", shift); 1101 return; 1102 } 1103 1104 memset(spapr->htab, 0, size); 1105 spapr->htab_shift = shift; 1106 1107 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1108 DIRTY_HPTE(HPTE(spapr->htab, i)); 1109 } 1110 } 1111 } 1112 1113 static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1114 { 1115 bool matched = false; 1116 1117 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1118 matched = true; 1119 } 1120 1121 if (!matched) { 1122 error_report("Device %s is not supported by this machine yet.", 1123 qdev_fw_name(DEVICE(sbdev))); 1124 exit(1); 1125 } 1126 1127 return 0; 1128 } 1129 1130 static void ppc_spapr_reset(void) 1131 { 1132 MachineState *machine = MACHINE(qdev_get_machine()); 1133 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1134 PowerPCCPU *first_ppc_cpu; 1135 uint32_t rtas_limit; 1136 1137 /* Check for unknown sysbus devices */ 1138 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1139 1140 /* Allocate and/or reset the hash page table */ 1141 spapr_reallocate_hpt(spapr, 1142 spapr_hpt_shift_for_ramsize(machine->maxram_size), 1143 &error_fatal); 1144 1145 /* Update the RMA size if necessary */ 1146 if (spapr->vrma_adjust) { 1147 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1148 spapr->htab_shift); 1149 } 1150 1151 qemu_devices_reset(); 1152 1153 /* 1154 * We place the device tree and RTAS just below either the top of the RMA, 1155 * or just below 2GB, whichever is lowere, so that it can be 1156 * processed with 32-bit real mode code if necessary 1157 */ 1158 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1159 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1160 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 1161 1162 /* Load the fdt */ 1163 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 1164 spapr->rtas_size); 1165 1166 /* Copy RTAS over */ 1167 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob, 1168 spapr->rtas_size); 1169 1170 /* Set up the entry state */ 1171 first_ppc_cpu = POWERPC_CPU(first_cpu); 1172 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 1173 first_ppc_cpu->env.gpr[5] = 0; 1174 first_cpu->halted = 0; 1175 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1176 1177 } 1178 1179 static void spapr_create_nvram(sPAPRMachineState *spapr) 1180 { 1181 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1182 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1183 1184 if (dinfo) { 1185 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1186 &error_fatal); 1187 } 1188 1189 qdev_init_nofail(dev); 1190 1191 spapr->nvram = (struct sPAPRNVRAM *)dev; 1192 } 1193 1194 static void spapr_rtc_create(sPAPRMachineState *spapr) 1195 { 1196 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); 1197 1198 qdev_init_nofail(dev); 1199 spapr->rtc = dev; 1200 1201 object_property_add_alias(qdev_get_machine(), "rtc-time", 1202 OBJECT(spapr->rtc), "date", NULL); 1203 } 1204 1205 /* Returns whether we want to use VGA or not */ 1206 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1207 { 1208 switch (vga_interface_type) { 1209 case VGA_NONE: 1210 return false; 1211 case VGA_DEVICE: 1212 return true; 1213 case VGA_STD: 1214 case VGA_VIRTIO: 1215 return pci_vga_init(pci_bus) != NULL; 1216 default: 1217 error_setg(errp, 1218 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1219 return false; 1220 } 1221 } 1222 1223 static int spapr_post_load(void *opaque, int version_id) 1224 { 1225 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1226 int err = 0; 1227 1228 /* In earlier versions, there was no separate qdev for the PAPR 1229 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1230 * So when migrating from those versions, poke the incoming offset 1231 * value into the RTC device */ 1232 if (version_id < 3) { 1233 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); 1234 } 1235 1236 return err; 1237 } 1238 1239 static bool version_before_3(void *opaque, int version_id) 1240 { 1241 return version_id < 3; 1242 } 1243 1244 static const VMStateDescription vmstate_spapr = { 1245 .name = "spapr", 1246 .version_id = 3, 1247 .minimum_version_id = 1, 1248 .post_load = spapr_post_load, 1249 .fields = (VMStateField[]) { 1250 /* used to be @next_irq */ 1251 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1252 1253 /* RTC offset */ 1254 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1255 1256 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1257 VMSTATE_END_OF_LIST() 1258 }, 1259 }; 1260 1261 static int htab_save_setup(QEMUFile *f, void *opaque) 1262 { 1263 sPAPRMachineState *spapr = opaque; 1264 1265 /* "Iteration" header */ 1266 qemu_put_be32(f, spapr->htab_shift); 1267 1268 if (spapr->htab) { 1269 spapr->htab_save_index = 0; 1270 spapr->htab_first_pass = true; 1271 } else { 1272 assert(kvm_enabled()); 1273 } 1274 1275 1276 return 0; 1277 } 1278 1279 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1280 int64_t max_ns) 1281 { 1282 bool has_timeout = max_ns != -1; 1283 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1284 int index = spapr->htab_save_index; 1285 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1286 1287 assert(spapr->htab_first_pass); 1288 1289 do { 1290 int chunkstart; 1291 1292 /* Consume invalid HPTEs */ 1293 while ((index < htabslots) 1294 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1295 index++; 1296 CLEAN_HPTE(HPTE(spapr->htab, index)); 1297 } 1298 1299 /* Consume valid HPTEs */ 1300 chunkstart = index; 1301 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1302 && HPTE_VALID(HPTE(spapr->htab, index))) { 1303 index++; 1304 CLEAN_HPTE(HPTE(spapr->htab, index)); 1305 } 1306 1307 if (index > chunkstart) { 1308 int n_valid = index - chunkstart; 1309 1310 qemu_put_be32(f, chunkstart); 1311 qemu_put_be16(f, n_valid); 1312 qemu_put_be16(f, 0); 1313 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1314 HASH_PTE_SIZE_64 * n_valid); 1315 1316 if (has_timeout && 1317 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1318 break; 1319 } 1320 } 1321 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1322 1323 if (index >= htabslots) { 1324 assert(index == htabslots); 1325 index = 0; 1326 spapr->htab_first_pass = false; 1327 } 1328 spapr->htab_save_index = index; 1329 } 1330 1331 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1332 int64_t max_ns) 1333 { 1334 bool final = max_ns < 0; 1335 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1336 int examined = 0, sent = 0; 1337 int index = spapr->htab_save_index; 1338 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1339 1340 assert(!spapr->htab_first_pass); 1341 1342 do { 1343 int chunkstart, invalidstart; 1344 1345 /* Consume non-dirty HPTEs */ 1346 while ((index < htabslots) 1347 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1348 index++; 1349 examined++; 1350 } 1351 1352 chunkstart = index; 1353 /* Consume valid dirty HPTEs */ 1354 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1355 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1356 && HPTE_VALID(HPTE(spapr->htab, index))) { 1357 CLEAN_HPTE(HPTE(spapr->htab, index)); 1358 index++; 1359 examined++; 1360 } 1361 1362 invalidstart = index; 1363 /* Consume invalid dirty HPTEs */ 1364 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1365 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1366 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1367 CLEAN_HPTE(HPTE(spapr->htab, index)); 1368 index++; 1369 examined++; 1370 } 1371 1372 if (index > chunkstart) { 1373 int n_valid = invalidstart - chunkstart; 1374 int n_invalid = index - invalidstart; 1375 1376 qemu_put_be32(f, chunkstart); 1377 qemu_put_be16(f, n_valid); 1378 qemu_put_be16(f, n_invalid); 1379 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1380 HASH_PTE_SIZE_64 * n_valid); 1381 sent += index - chunkstart; 1382 1383 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1384 break; 1385 } 1386 } 1387 1388 if (examined >= htabslots) { 1389 break; 1390 } 1391 1392 if (index >= htabslots) { 1393 assert(index == htabslots); 1394 index = 0; 1395 } 1396 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1397 1398 if (index >= htabslots) { 1399 assert(index == htabslots); 1400 index = 0; 1401 } 1402 1403 spapr->htab_save_index = index; 1404 1405 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1406 } 1407 1408 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1409 #define MAX_KVM_BUF_SIZE 2048 1410 1411 static int htab_save_iterate(QEMUFile *f, void *opaque) 1412 { 1413 sPAPRMachineState *spapr = opaque; 1414 int fd; 1415 int rc = 0; 1416 1417 /* Iteration header */ 1418 qemu_put_be32(f, 0); 1419 1420 if (!spapr->htab) { 1421 assert(kvm_enabled()); 1422 1423 fd = get_htab_fd(spapr); 1424 if (fd < 0) { 1425 return fd; 1426 } 1427 1428 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1429 if (rc < 0) { 1430 return rc; 1431 } 1432 } else if (spapr->htab_first_pass) { 1433 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1434 } else { 1435 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1436 } 1437 1438 /* End marker */ 1439 qemu_put_be32(f, 0); 1440 qemu_put_be16(f, 0); 1441 qemu_put_be16(f, 0); 1442 1443 return rc; 1444 } 1445 1446 static int htab_save_complete(QEMUFile *f, void *opaque) 1447 { 1448 sPAPRMachineState *spapr = opaque; 1449 int fd; 1450 1451 /* Iteration header */ 1452 qemu_put_be32(f, 0); 1453 1454 if (!spapr->htab) { 1455 int rc; 1456 1457 assert(kvm_enabled()); 1458 1459 fd = get_htab_fd(spapr); 1460 if (fd < 0) { 1461 return fd; 1462 } 1463 1464 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1465 if (rc < 0) { 1466 return rc; 1467 } 1468 } else { 1469 if (spapr->htab_first_pass) { 1470 htab_save_first_pass(f, spapr, -1); 1471 } 1472 htab_save_later_pass(f, spapr, -1); 1473 } 1474 1475 /* End marker */ 1476 qemu_put_be32(f, 0); 1477 qemu_put_be16(f, 0); 1478 qemu_put_be16(f, 0); 1479 1480 return 0; 1481 } 1482 1483 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1484 { 1485 sPAPRMachineState *spapr = opaque; 1486 uint32_t section_hdr; 1487 int fd = -1; 1488 1489 if (version_id < 1 || version_id > 1) { 1490 error_report("htab_load() bad version"); 1491 return -EINVAL; 1492 } 1493 1494 section_hdr = qemu_get_be32(f); 1495 1496 if (section_hdr) { 1497 Error *local_err = NULL; 1498 1499 /* First section gives the htab size */ 1500 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1501 if (local_err) { 1502 error_report_err(local_err); 1503 return -EINVAL; 1504 } 1505 return 0; 1506 } 1507 1508 if (!spapr->htab) { 1509 assert(kvm_enabled()); 1510 1511 fd = kvmppc_get_htab_fd(true); 1512 if (fd < 0) { 1513 error_report("Unable to open fd to restore KVM hash table: %s", 1514 strerror(errno)); 1515 } 1516 } 1517 1518 while (true) { 1519 uint32_t index; 1520 uint16_t n_valid, n_invalid; 1521 1522 index = qemu_get_be32(f); 1523 n_valid = qemu_get_be16(f); 1524 n_invalid = qemu_get_be16(f); 1525 1526 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1527 /* End of Stream */ 1528 break; 1529 } 1530 1531 if ((index + n_valid + n_invalid) > 1532 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1533 /* Bad index in stream */ 1534 error_report( 1535 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1536 index, n_valid, n_invalid, spapr->htab_shift); 1537 return -EINVAL; 1538 } 1539 1540 if (spapr->htab) { 1541 if (n_valid) { 1542 qemu_get_buffer(f, HPTE(spapr->htab, index), 1543 HASH_PTE_SIZE_64 * n_valid); 1544 } 1545 if (n_invalid) { 1546 memset(HPTE(spapr->htab, index + n_valid), 0, 1547 HASH_PTE_SIZE_64 * n_invalid); 1548 } 1549 } else { 1550 int rc; 1551 1552 assert(fd >= 0); 1553 1554 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1555 if (rc < 0) { 1556 return rc; 1557 } 1558 } 1559 } 1560 1561 if (!spapr->htab) { 1562 assert(fd >= 0); 1563 close(fd); 1564 } 1565 1566 return 0; 1567 } 1568 1569 static void htab_cleanup(void *opaque) 1570 { 1571 sPAPRMachineState *spapr = opaque; 1572 1573 close_htab_fd(spapr); 1574 } 1575 1576 static SaveVMHandlers savevm_htab_handlers = { 1577 .save_live_setup = htab_save_setup, 1578 .save_live_iterate = htab_save_iterate, 1579 .save_live_complete_precopy = htab_save_complete, 1580 .cleanup = htab_cleanup, 1581 .load_state = htab_load, 1582 }; 1583 1584 static void spapr_boot_set(void *opaque, const char *boot_device, 1585 Error **errp) 1586 { 1587 MachineState *machine = MACHINE(qdev_get_machine()); 1588 machine->boot_order = g_strdup(boot_device); 1589 } 1590 1591 /* 1592 * Reset routine for LMB DR devices. 1593 * 1594 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1595 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1596 * when it walks all its children devices. LMB devices reset occurs 1597 * as part of spapr_ppc_reset(). 1598 */ 1599 static void spapr_drc_reset(void *opaque) 1600 { 1601 sPAPRDRConnector *drc = opaque; 1602 DeviceState *d = DEVICE(drc); 1603 1604 if (d) { 1605 device_reset(d); 1606 } 1607 } 1608 1609 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1610 { 1611 MachineState *machine = MACHINE(spapr); 1612 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1613 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1614 int i; 1615 1616 for (i = 0; i < nr_lmbs; i++) { 1617 sPAPRDRConnector *drc; 1618 uint64_t addr; 1619 1620 addr = i * lmb_size + spapr->hotplug_memory.base; 1621 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, 1622 addr/lmb_size); 1623 qemu_register_reset(spapr_drc_reset, drc); 1624 } 1625 } 1626 1627 /* 1628 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1629 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1630 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1631 */ 1632 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 1633 { 1634 int i; 1635 1636 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1637 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 1638 " is not aligned to %llu MiB", 1639 machine->ram_size, 1640 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1641 return; 1642 } 1643 1644 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1645 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 1646 " is not aligned to %llu MiB", 1647 machine->ram_size, 1648 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1649 return; 1650 } 1651 1652 for (i = 0; i < nb_numa_nodes; i++) { 1653 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 1654 error_setg(errp, 1655 "Node %d memory size 0x%" PRIx64 1656 " is not aligned to %llu MiB", 1657 i, numa_info[i].node_mem, 1658 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1659 return; 1660 } 1661 } 1662 } 1663 1664 /* pSeries LPAR / sPAPR hardware init */ 1665 static void ppc_spapr_init(MachineState *machine) 1666 { 1667 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1668 MachineClass *mc = MACHINE_GET_CLASS(machine); 1669 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1670 const char *kernel_filename = machine->kernel_filename; 1671 const char *kernel_cmdline = machine->kernel_cmdline; 1672 const char *initrd_filename = machine->initrd_filename; 1673 PCIHostState *phb; 1674 int i; 1675 MemoryRegion *sysmem = get_system_memory(); 1676 MemoryRegion *ram = g_new(MemoryRegion, 1); 1677 MemoryRegion *rma_region; 1678 void *rma = NULL; 1679 hwaddr rma_alloc_size; 1680 hwaddr node0_size = spapr_node0_size(); 1681 uint32_t initrd_base = 0; 1682 long kernel_size = 0, initrd_size = 0; 1683 long load_limit, fw_size; 1684 bool kernel_le = false; 1685 char *filename; 1686 int smt = kvmppc_smt_threads(); 1687 int spapr_cores = smp_cpus / smp_threads; 1688 int spapr_max_cores = max_cpus / smp_threads; 1689 1690 if (mc->query_hotpluggable_cpus) { 1691 if (smp_cpus % smp_threads) { 1692 error_report("smp_cpus (%u) must be multiple of threads (%u)", 1693 smp_cpus, smp_threads); 1694 exit(1); 1695 } 1696 if (max_cpus % smp_threads) { 1697 error_report("max_cpus (%u) must be multiple of threads (%u)", 1698 max_cpus, smp_threads); 1699 exit(1); 1700 } 1701 } 1702 1703 msi_nonbroken = true; 1704 1705 QLIST_INIT(&spapr->phbs); 1706 1707 cpu_ppc_hypercall = emulate_spapr_hypercall; 1708 1709 /* Allocate RMA if necessary */ 1710 rma_alloc_size = kvmppc_alloc_rma(&rma); 1711 1712 if (rma_alloc_size == -1) { 1713 error_report("Unable to create RMA"); 1714 exit(1); 1715 } 1716 1717 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1718 spapr->rma_size = rma_alloc_size; 1719 } else { 1720 spapr->rma_size = node0_size; 1721 1722 /* With KVM, we don't actually know whether KVM supports an 1723 * unbounded RMA (PR KVM) or is limited by the hash table size 1724 * (HV KVM using VRMA), so we always assume the latter 1725 * 1726 * In that case, we also limit the initial allocations for RTAS 1727 * etc... to 256M since we have no way to know what the VRMA size 1728 * is going to be as it depends on the size of the hash table 1729 * isn't determined yet. 1730 */ 1731 if (kvm_enabled()) { 1732 spapr->vrma_adjust = 1; 1733 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1734 } 1735 1736 /* Actually we don't support unbounded RMA anymore since we 1737 * added proper emulation of HV mode. The max we can get is 1738 * 16G which also happens to be what we configure for PAPR 1739 * mode so make sure we don't do anything bigger than that 1740 */ 1741 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 1742 } 1743 1744 if (spapr->rma_size > node0_size) { 1745 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 1746 spapr->rma_size); 1747 exit(1); 1748 } 1749 1750 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 1751 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 1752 1753 /* Set up Interrupt Controller before we create the VCPUs */ 1754 spapr->xics = xics_system_init(machine, 1755 DIV_ROUND_UP(max_cpus * smt, smp_threads), 1756 XICS_IRQS_SPAPR, &error_fatal); 1757 1758 if (smc->dr_lmb_enabled) { 1759 spapr_validate_node_memory(machine, &error_fatal); 1760 } 1761 1762 /* init CPUs */ 1763 if (machine->cpu_model == NULL) { 1764 machine->cpu_model = kvm_enabled() ? "host" : "POWER7"; 1765 } 1766 1767 ppc_cpu_parse_features(machine->cpu_model); 1768 1769 if (mc->query_hotpluggable_cpus) { 1770 char *type = spapr_get_cpu_core_type(machine->cpu_model); 1771 1772 if (type == NULL) { 1773 error_report("Unable to find sPAPR CPU Core definition"); 1774 exit(1); 1775 } 1776 1777 spapr->cores = g_new0(Object *, spapr_max_cores); 1778 for (i = 0; i < spapr_max_cores; i++) { 1779 int core_id = i * smp_threads; 1780 sPAPRDRConnector *drc = 1781 spapr_dr_connector_new(OBJECT(spapr), 1782 SPAPR_DR_CONNECTOR_TYPE_CPU, 1783 (core_id / smp_threads) * smt); 1784 1785 qemu_register_reset(spapr_drc_reset, drc); 1786 1787 if (i < spapr_cores) { 1788 Object *core = object_new(type); 1789 object_property_set_int(core, smp_threads, "nr-threads", 1790 &error_fatal); 1791 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 1792 &error_fatal); 1793 object_property_set_bool(core, true, "realized", &error_fatal); 1794 } 1795 } 1796 g_free(type); 1797 } else { 1798 for (i = 0; i < smp_cpus; i++) { 1799 PowerPCCPU *cpu = cpu_ppc_init(machine->cpu_model); 1800 if (cpu == NULL) { 1801 error_report("Unable to find PowerPC CPU definition"); 1802 exit(1); 1803 } 1804 spapr_cpu_init(spapr, cpu, &error_fatal); 1805 } 1806 } 1807 1808 if (kvm_enabled()) { 1809 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 1810 kvmppc_enable_logical_ci_hcalls(); 1811 kvmppc_enable_set_mode_hcall(); 1812 1813 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 1814 kvmppc_enable_clear_ref_mod_hcalls(); 1815 } 1816 1817 /* allocate RAM */ 1818 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 1819 machine->ram_size); 1820 memory_region_add_subregion(sysmem, 0, ram); 1821 1822 if (rma_alloc_size && rma) { 1823 rma_region = g_new(MemoryRegion, 1); 1824 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 1825 rma_alloc_size, rma); 1826 vmstate_register_ram_global(rma_region); 1827 memory_region_add_subregion(sysmem, 0, rma_region); 1828 } 1829 1830 /* initialize hotplug memory address space */ 1831 if (machine->ram_size < machine->maxram_size) { 1832 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 1833 /* 1834 * Limit the number of hotpluggable memory slots to half the number 1835 * slots that KVM supports, leaving the other half for PCI and other 1836 * devices. However ensure that number of slots doesn't drop below 32. 1837 */ 1838 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 1839 SPAPR_MAX_RAM_SLOTS; 1840 1841 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 1842 max_memslots = SPAPR_MAX_RAM_SLOTS; 1843 } 1844 if (machine->ram_slots > max_memslots) { 1845 error_report("Specified number of memory slots %" 1846 PRIu64" exceeds max supported %d", 1847 machine->ram_slots, max_memslots); 1848 exit(1); 1849 } 1850 1851 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 1852 SPAPR_HOTPLUG_MEM_ALIGN); 1853 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 1854 "hotplug-memory", hotplug_mem_size); 1855 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 1856 &spapr->hotplug_memory.mr); 1857 } 1858 1859 if (smc->dr_lmb_enabled) { 1860 spapr_create_lmb_dr_connectors(spapr); 1861 } 1862 1863 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1864 if (!filename) { 1865 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 1866 exit(1); 1867 } 1868 spapr->rtas_size = get_image_size(filename); 1869 if (spapr->rtas_size < 0) { 1870 error_report("Could not get size of LPAR rtas '%s'", filename); 1871 exit(1); 1872 } 1873 spapr->rtas_blob = g_malloc(spapr->rtas_size); 1874 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 1875 error_report("Could not load LPAR rtas '%s'", filename); 1876 exit(1); 1877 } 1878 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1879 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 1880 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 1881 exit(1); 1882 } 1883 g_free(filename); 1884 1885 /* Set up EPOW events infrastructure */ 1886 spapr_events_init(spapr); 1887 1888 /* Set up the RTC RTAS interfaces */ 1889 spapr_rtc_create(spapr); 1890 1891 /* Set up VIO bus */ 1892 spapr->vio_bus = spapr_vio_bus_init(); 1893 1894 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1895 if (serial_hds[i]) { 1896 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1897 } 1898 } 1899 1900 /* We always have at least the nvram device on VIO */ 1901 spapr_create_nvram(spapr); 1902 1903 /* Set up PCI */ 1904 spapr_pci_rtas_init(); 1905 1906 phb = spapr_create_phb(spapr, 0); 1907 1908 for (i = 0; i < nb_nics; i++) { 1909 NICInfo *nd = &nd_table[i]; 1910 1911 if (!nd->model) { 1912 nd->model = g_strdup("ibmveth"); 1913 } 1914 1915 if (strcmp(nd->model, "ibmveth") == 0) { 1916 spapr_vlan_create(spapr->vio_bus, nd); 1917 } else { 1918 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1919 } 1920 } 1921 1922 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1923 spapr_vscsi_create(spapr->vio_bus); 1924 } 1925 1926 /* Graphics */ 1927 if (spapr_vga_init(phb->bus, &error_fatal)) { 1928 spapr->has_graphics = true; 1929 machine->usb |= defaults_enabled() && !machine->usb_disabled; 1930 } 1931 1932 if (machine->usb) { 1933 if (smc->use_ohci_by_default) { 1934 pci_create_simple(phb->bus, -1, "pci-ohci"); 1935 } else { 1936 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 1937 } 1938 1939 if (spapr->has_graphics) { 1940 USBBus *usb_bus = usb_bus_find(-1); 1941 1942 usb_create_simple(usb_bus, "usb-kbd"); 1943 usb_create_simple(usb_bus, "usb-mouse"); 1944 } 1945 } 1946 1947 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1948 error_report( 1949 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 1950 MIN_RMA_SLOF); 1951 exit(1); 1952 } 1953 1954 if (kernel_filename) { 1955 uint64_t lowaddr = 0; 1956 1957 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1958 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 1959 0, 0); 1960 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { 1961 kernel_size = load_elf(kernel_filename, 1962 translate_kernel_address, NULL, 1963 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE, 1964 0, 0); 1965 kernel_le = kernel_size > 0; 1966 } 1967 if (kernel_size < 0) { 1968 error_report("error loading %s: %s", 1969 kernel_filename, load_elf_strerror(kernel_size)); 1970 exit(1); 1971 } 1972 1973 /* load initrd */ 1974 if (initrd_filename) { 1975 /* Try to locate the initrd in the gap between the kernel 1976 * and the firmware. Add a bit of space just in case 1977 */ 1978 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1979 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1980 load_limit - initrd_base); 1981 if (initrd_size < 0) { 1982 error_report("could not load initial ram disk '%s'", 1983 initrd_filename); 1984 exit(1); 1985 } 1986 } else { 1987 initrd_base = 0; 1988 initrd_size = 0; 1989 } 1990 } 1991 1992 if (bios_name == NULL) { 1993 bios_name = FW_FILE_NAME; 1994 } 1995 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1996 if (!filename) { 1997 error_report("Could not find LPAR firmware '%s'", bios_name); 1998 exit(1); 1999 } 2000 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2001 if (fw_size <= 0) { 2002 error_report("Could not load LPAR firmware '%s'", filename); 2003 exit(1); 2004 } 2005 g_free(filename); 2006 2007 /* FIXME: Should register things through the MachineState's qdev 2008 * interface, this is a legacy from the sPAPREnvironment structure 2009 * which predated MachineState but had a similar function */ 2010 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2011 register_savevm_live(NULL, "spapr/htab", -1, 1, 2012 &savevm_htab_handlers, spapr); 2013 2014 /* Prepare the device tree */ 2015 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 2016 kernel_size, kernel_le, 2017 kernel_cmdline, 2018 spapr->check_exception_irq); 2019 assert(spapr->fdt_skel != NULL); 2020 2021 /* used by RTAS */ 2022 QTAILQ_INIT(&spapr->ccs_list); 2023 qemu_register_reset(spapr_ccs_reset_hook, spapr); 2024 2025 qemu_register_boot_set(spapr_boot_set, spapr); 2026 } 2027 2028 static int spapr_kvm_type(const char *vm_type) 2029 { 2030 if (!vm_type) { 2031 return 0; 2032 } 2033 2034 if (!strcmp(vm_type, "HV")) { 2035 return 1; 2036 } 2037 2038 if (!strcmp(vm_type, "PR")) { 2039 return 2; 2040 } 2041 2042 error_report("Unknown kvm-type specified '%s'", vm_type); 2043 exit(1); 2044 } 2045 2046 /* 2047 * Implementation of an interface to adjust firmware path 2048 * for the bootindex property handling. 2049 */ 2050 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2051 DeviceState *dev) 2052 { 2053 #define CAST(type, obj, name) \ 2054 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2055 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2056 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2057 2058 if (d) { 2059 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2060 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2061 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2062 2063 if (spapr) { 2064 /* 2065 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2066 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2067 * in the top 16 bits of the 64-bit LUN 2068 */ 2069 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2070 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2071 (uint64_t)id << 48); 2072 } else if (virtio) { 2073 /* 2074 * We use SRP luns of the form 01000000 | (target << 8) | lun 2075 * in the top 32 bits of the 64-bit LUN 2076 * Note: the quote above is from SLOF and it is wrong, 2077 * the actual binding is: 2078 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2079 */ 2080 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2081 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2082 (uint64_t)id << 32); 2083 } else if (usb) { 2084 /* 2085 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2086 * in the top 32 bits of the 64-bit LUN 2087 */ 2088 unsigned usb_port = atoi(usb->port->path); 2089 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2090 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2091 (uint64_t)id << 32); 2092 } 2093 } 2094 2095 if (phb) { 2096 /* Replace "pci" with "pci@800000020000000" */ 2097 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2098 } 2099 2100 return NULL; 2101 } 2102 2103 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2104 { 2105 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2106 2107 return g_strdup(spapr->kvm_type); 2108 } 2109 2110 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2111 { 2112 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2113 2114 g_free(spapr->kvm_type); 2115 spapr->kvm_type = g_strdup(value); 2116 } 2117 2118 static void spapr_machine_initfn(Object *obj) 2119 { 2120 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2121 2122 spapr->htab_fd = -1; 2123 object_property_add_str(obj, "kvm-type", 2124 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2125 object_property_set_description(obj, "kvm-type", 2126 "Specifies the KVM virtualization mode (HV, PR)", 2127 NULL); 2128 } 2129 2130 static void spapr_machine_finalizefn(Object *obj) 2131 { 2132 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2133 2134 g_free(spapr->kvm_type); 2135 } 2136 2137 static void ppc_cpu_do_nmi_on_cpu(CPUState *cs, void *arg) 2138 { 2139 cpu_synchronize_state(cs); 2140 ppc_cpu_do_system_reset(cs); 2141 } 2142 2143 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2144 { 2145 CPUState *cs; 2146 2147 CPU_FOREACH(cs) { 2148 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, NULL); 2149 } 2150 } 2151 2152 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size, 2153 uint32_t node, Error **errp) 2154 { 2155 sPAPRDRConnector *drc; 2156 sPAPRDRConnectorClass *drck; 2157 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2158 int i, fdt_offset, fdt_size; 2159 void *fdt; 2160 2161 for (i = 0; i < nr_lmbs; i++) { 2162 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2163 addr/SPAPR_MEMORY_BLOCK_SIZE); 2164 g_assert(drc); 2165 2166 fdt = create_device_tree(&fdt_size); 2167 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2168 SPAPR_MEMORY_BLOCK_SIZE); 2169 2170 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2171 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2172 addr += SPAPR_MEMORY_BLOCK_SIZE; 2173 } 2174 /* send hotplug notification to the 2175 * guest only in case of hotplugged memory 2176 */ 2177 if (dev->hotplugged) { 2178 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs); 2179 } 2180 } 2181 2182 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2183 uint32_t node, Error **errp) 2184 { 2185 Error *local_err = NULL; 2186 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2187 PCDIMMDevice *dimm = PC_DIMM(dev); 2188 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2189 MemoryRegion *mr = ddc->get_memory_region(dimm); 2190 uint64_t align = memory_region_get_alignment(mr); 2191 uint64_t size = memory_region_size(mr); 2192 uint64_t addr; 2193 2194 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2195 error_setg(&local_err, "Hotplugged memory size must be a multiple of " 2196 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 2197 goto out; 2198 } 2199 2200 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2201 if (local_err) { 2202 goto out; 2203 } 2204 2205 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2206 if (local_err) { 2207 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2208 goto out; 2209 } 2210 2211 spapr_add_lmbs(dev, addr, size, node, &error_abort); 2212 2213 out: 2214 error_propagate(errp, local_err); 2215 } 2216 2217 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 2218 sPAPRMachineState *spapr) 2219 { 2220 PowerPCCPU *cpu = POWERPC_CPU(cs); 2221 DeviceClass *dc = DEVICE_GET_CLASS(cs); 2222 int id = ppc_get_vcpu_dt_id(cpu); 2223 void *fdt; 2224 int offset, fdt_size; 2225 char *nodename; 2226 2227 fdt = create_device_tree(&fdt_size); 2228 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 2229 offset = fdt_add_subnode(fdt, 0, nodename); 2230 2231 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 2232 g_free(nodename); 2233 2234 *fdt_offset = offset; 2235 return fdt; 2236 } 2237 2238 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 2239 DeviceState *dev, Error **errp) 2240 { 2241 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2242 2243 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2244 int node; 2245 2246 if (!smc->dr_lmb_enabled) { 2247 error_setg(errp, "Memory hotplug not supported for this machine"); 2248 return; 2249 } 2250 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 2251 if (*errp) { 2252 return; 2253 } 2254 if (node < 0 || node >= MAX_NODES) { 2255 error_setg(errp, "Invaild node %d", node); 2256 return; 2257 } 2258 2259 /* 2260 * Currently PowerPC kernel doesn't allow hot-adding memory to 2261 * memory-less node, but instead will silently add the memory 2262 * to the first node that has some memory. This causes two 2263 * unexpected behaviours for the user. 2264 * 2265 * - Memory gets hotplugged to a different node than what the user 2266 * specified. 2267 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 2268 * to memory-less node, a reboot will set things accordingly 2269 * and the previously hotplugged memory now ends in the right node. 2270 * This appears as if some memory moved from one node to another. 2271 * 2272 * So until kernel starts supporting memory hotplug to memory-less 2273 * nodes, just prevent such attempts upfront in QEMU. 2274 */ 2275 if (nb_numa_nodes && !numa_info[node].node_mem) { 2276 error_setg(errp, "Can't hotplug memory to memory-less node %d", 2277 node); 2278 return; 2279 } 2280 2281 spapr_memory_plug(hotplug_dev, dev, node, errp); 2282 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2283 spapr_core_plug(hotplug_dev, dev, errp); 2284 } 2285 } 2286 2287 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 2288 DeviceState *dev, Error **errp) 2289 { 2290 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2291 2292 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2293 error_setg(errp, "Memory hot unplug not supported by sPAPR"); 2294 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2295 if (!mc->query_hotpluggable_cpus) { 2296 error_setg(errp, "CPU hot unplug not supported on this machine"); 2297 return; 2298 } 2299 spapr_core_unplug(hotplug_dev, dev, errp); 2300 } 2301 } 2302 2303 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 2304 DeviceState *dev, Error **errp) 2305 { 2306 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2307 spapr_core_pre_plug(hotplug_dev, dev, errp); 2308 } 2309 } 2310 2311 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 2312 DeviceState *dev) 2313 { 2314 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2315 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2316 return HOTPLUG_HANDLER(machine); 2317 } 2318 return NULL; 2319 } 2320 2321 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index) 2322 { 2323 /* Allocate to NUMA nodes on a "socket" basis (not that concept of 2324 * socket means much for the paravirtualized PAPR platform) */ 2325 return cpu_index / smp_threads / smp_cores; 2326 } 2327 2328 static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine) 2329 { 2330 int i; 2331 HotpluggableCPUList *head = NULL; 2332 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2333 int spapr_max_cores = max_cpus / smp_threads; 2334 2335 for (i = 0; i < spapr_max_cores; i++) { 2336 HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1); 2337 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); 2338 CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1); 2339 2340 cpu_item->type = spapr_get_cpu_core_type(machine->cpu_model); 2341 cpu_item->vcpus_count = smp_threads; 2342 cpu_props->has_core_id = true; 2343 cpu_props->core_id = i * smp_threads; 2344 /* TODO: add 'has_node/node' here to describe 2345 to which node core belongs */ 2346 2347 cpu_item->props = cpu_props; 2348 if (spapr->cores[i]) { 2349 cpu_item->has_qom_path = true; 2350 cpu_item->qom_path = object_get_canonical_path(spapr->cores[i]); 2351 } 2352 list_item->value = cpu_item; 2353 list_item->next = head; 2354 head = list_item; 2355 } 2356 return head; 2357 } 2358 2359 static void spapr_machine_class_init(ObjectClass *oc, void *data) 2360 { 2361 MachineClass *mc = MACHINE_CLASS(oc); 2362 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 2363 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 2364 NMIClass *nc = NMI_CLASS(oc); 2365 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2366 2367 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 2368 2369 /* 2370 * We set up the default / latest behaviour here. The class_init 2371 * functions for the specific versioned machine types can override 2372 * these details for backwards compatibility 2373 */ 2374 mc->init = ppc_spapr_init; 2375 mc->reset = ppc_spapr_reset; 2376 mc->block_default_type = IF_SCSI; 2377 mc->max_cpus = MAX_CPUMASK_BITS; 2378 mc->no_parallel = 1; 2379 mc->default_boot_order = ""; 2380 mc->default_ram_size = 512 * M_BYTE; 2381 mc->kvm_type = spapr_kvm_type; 2382 mc->has_dynamic_sysbus = true; 2383 mc->pci_allow_0_address = true; 2384 mc->get_hotplug_handler = spapr_get_hotplug_handler; 2385 hc->pre_plug = spapr_machine_device_pre_plug; 2386 hc->plug = spapr_machine_device_plug; 2387 hc->unplug = spapr_machine_device_unplug; 2388 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; 2389 2390 smc->dr_lmb_enabled = true; 2391 mc->query_hotpluggable_cpus = spapr_query_hotpluggable_cpus; 2392 fwc->get_dev_path = spapr_get_fw_dev_path; 2393 nc->nmi_monitor_handler = spapr_nmi; 2394 } 2395 2396 static const TypeInfo spapr_machine_info = { 2397 .name = TYPE_SPAPR_MACHINE, 2398 .parent = TYPE_MACHINE, 2399 .abstract = true, 2400 .instance_size = sizeof(sPAPRMachineState), 2401 .instance_init = spapr_machine_initfn, 2402 .instance_finalize = spapr_machine_finalizefn, 2403 .class_size = sizeof(sPAPRMachineClass), 2404 .class_init = spapr_machine_class_init, 2405 .interfaces = (InterfaceInfo[]) { 2406 { TYPE_FW_PATH_PROVIDER }, 2407 { TYPE_NMI }, 2408 { TYPE_HOTPLUG_HANDLER }, 2409 { } 2410 }, 2411 }; 2412 2413 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 2414 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 2415 void *data) \ 2416 { \ 2417 MachineClass *mc = MACHINE_CLASS(oc); \ 2418 spapr_machine_##suffix##_class_options(mc); \ 2419 if (latest) { \ 2420 mc->alias = "pseries"; \ 2421 mc->is_default = 1; \ 2422 } \ 2423 } \ 2424 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 2425 { \ 2426 MachineState *machine = MACHINE(obj); \ 2427 spapr_machine_##suffix##_instance_options(machine); \ 2428 } \ 2429 static const TypeInfo spapr_machine_##suffix##_info = { \ 2430 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 2431 .parent = TYPE_SPAPR_MACHINE, \ 2432 .class_init = spapr_machine_##suffix##_class_init, \ 2433 .instance_init = spapr_machine_##suffix##_instance_init, \ 2434 }; \ 2435 static void spapr_machine_register_##suffix(void) \ 2436 { \ 2437 type_register(&spapr_machine_##suffix##_info); \ 2438 } \ 2439 type_init(spapr_machine_register_##suffix) 2440 2441 /* 2442 * pseries-2.7 2443 */ 2444 static void spapr_machine_2_7_instance_options(MachineState *machine) 2445 { 2446 } 2447 2448 static void spapr_machine_2_7_class_options(MachineClass *mc) 2449 { 2450 /* Defaults for the latest behaviour inherited from the base class */ 2451 } 2452 2453 DEFINE_SPAPR_MACHINE(2_7, "2.7", true); 2454 2455 /* 2456 * pseries-2.6 2457 */ 2458 #define SPAPR_COMPAT_2_6 \ 2459 HW_COMPAT_2_6 \ 2460 { \ 2461 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 2462 .property = "ddw",\ 2463 .value = stringify(off),\ 2464 }, 2465 2466 static void spapr_machine_2_6_instance_options(MachineState *machine) 2467 { 2468 } 2469 2470 static void spapr_machine_2_6_class_options(MachineClass *mc) 2471 { 2472 spapr_machine_2_7_class_options(mc); 2473 mc->query_hotpluggable_cpus = NULL; 2474 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 2475 } 2476 2477 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 2478 2479 /* 2480 * pseries-2.5 2481 */ 2482 #define SPAPR_COMPAT_2_5 \ 2483 HW_COMPAT_2_5 \ 2484 { \ 2485 .driver = "spapr-vlan", \ 2486 .property = "use-rx-buffer-pools", \ 2487 .value = "off", \ 2488 }, 2489 2490 static void spapr_machine_2_5_instance_options(MachineState *machine) 2491 { 2492 } 2493 2494 static void spapr_machine_2_5_class_options(MachineClass *mc) 2495 { 2496 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 2497 2498 spapr_machine_2_6_class_options(mc); 2499 smc->use_ohci_by_default = true; 2500 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 2501 } 2502 2503 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 2504 2505 /* 2506 * pseries-2.4 2507 */ 2508 #define SPAPR_COMPAT_2_4 \ 2509 HW_COMPAT_2_4 2510 2511 static void spapr_machine_2_4_instance_options(MachineState *machine) 2512 { 2513 spapr_machine_2_5_instance_options(machine); 2514 } 2515 2516 static void spapr_machine_2_4_class_options(MachineClass *mc) 2517 { 2518 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 2519 2520 spapr_machine_2_5_class_options(mc); 2521 smc->dr_lmb_enabled = false; 2522 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 2523 } 2524 2525 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 2526 2527 /* 2528 * pseries-2.3 2529 */ 2530 #define SPAPR_COMPAT_2_3 \ 2531 HW_COMPAT_2_3 \ 2532 {\ 2533 .driver = "spapr-pci-host-bridge",\ 2534 .property = "dynamic-reconfiguration",\ 2535 .value = "off",\ 2536 }, 2537 2538 static void spapr_machine_2_3_instance_options(MachineState *machine) 2539 { 2540 spapr_machine_2_4_instance_options(machine); 2541 savevm_skip_section_footers(); 2542 global_state_set_optional(); 2543 savevm_skip_configuration(); 2544 } 2545 2546 static void spapr_machine_2_3_class_options(MachineClass *mc) 2547 { 2548 spapr_machine_2_4_class_options(mc); 2549 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 2550 } 2551 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 2552 2553 /* 2554 * pseries-2.2 2555 */ 2556 2557 #define SPAPR_COMPAT_2_2 \ 2558 HW_COMPAT_2_2 \ 2559 {\ 2560 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 2561 .property = "mem_win_size",\ 2562 .value = "0x20000000",\ 2563 }, 2564 2565 static void spapr_machine_2_2_instance_options(MachineState *machine) 2566 { 2567 spapr_machine_2_3_instance_options(machine); 2568 machine->suppress_vmdesc = true; 2569 } 2570 2571 static void spapr_machine_2_2_class_options(MachineClass *mc) 2572 { 2573 spapr_machine_2_3_class_options(mc); 2574 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 2575 } 2576 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 2577 2578 /* 2579 * pseries-2.1 2580 */ 2581 #define SPAPR_COMPAT_2_1 \ 2582 HW_COMPAT_2_1 2583 2584 static void spapr_machine_2_1_instance_options(MachineState *machine) 2585 { 2586 spapr_machine_2_2_instance_options(machine); 2587 } 2588 2589 static void spapr_machine_2_1_class_options(MachineClass *mc) 2590 { 2591 spapr_machine_2_2_class_options(mc); 2592 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 2593 } 2594 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 2595 2596 static void spapr_machine_register_types(void) 2597 { 2598 type_register_static(&spapr_machine_info); 2599 } 2600 2601 type_init(spapr_machine_register_types) 2602