1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qapi/error.h" 30 #include "qapi/visitor.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/hostmem.h" 33 #include "sysemu/numa.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/runstate.h" 37 #include "qemu/log.h" 38 #include "hw/fw-path-provider.h" 39 #include "elf.h" 40 #include "net/net.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/cpus.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_ppc.h" 45 #include "migration/misc.h" 46 #include "migration/qemu-file-types.h" 47 #include "migration/global_state.h" 48 #include "migration/register.h" 49 #include "mmu-hash64.h" 50 #include "mmu-book3s-v3.h" 51 #include "cpu-models.h" 52 #include "hw/core/cpu.h" 53 54 #include "hw/boards.h" 55 #include "hw/ppc/ppc.h" 56 #include "hw/loader.h" 57 58 #include "hw/ppc/fdt.h" 59 #include "hw/ppc/spapr.h" 60 #include "hw/ppc/spapr_vio.h" 61 #include "hw/qdev-properties.h" 62 #include "hw/pci-host/spapr.h" 63 #include "hw/pci/msi.h" 64 65 #include "hw/pci/pci.h" 66 #include "hw/scsi/scsi.h" 67 #include "hw/virtio/virtio-scsi.h" 68 #include "hw/virtio/vhost-scsi-common.h" 69 70 #include "exec/address-spaces.h" 71 #include "exec/ram_addr.h" 72 #include "hw/usb.h" 73 #include "qemu/config-file.h" 74 #include "qemu/error-report.h" 75 #include "trace.h" 76 #include "hw/nmi.h" 77 #include "hw/intc/intc.h" 78 79 #include "hw/ppc/spapr_cpu_core.h" 80 #include "hw/mem/memory-device.h" 81 #include "hw/ppc/spapr_tpm_proxy.h" 82 83 #include "monitor/monitor.h" 84 85 #include <libfdt.h> 86 87 /* SLOF memory layout: 88 * 89 * SLOF raw image loaded at 0, copies its romfs right below the flat 90 * device-tree, then position SLOF itself 31M below that 91 * 92 * So we set FW_OVERHEAD to 40MB which should account for all of that 93 * and more 94 * 95 * We load our kernel at 4M, leaving space for SLOF initial image 96 */ 97 #define FDT_MAX_SIZE 0x100000 98 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 99 #define FW_MAX_SIZE 0x400000 100 #define FW_FILE_NAME "slof.bin" 101 #define FW_OVERHEAD 0x2800000 102 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 103 104 #define MIN_RMA_SLOF 128UL 105 106 #define PHANDLE_INTC 0x00001111 107 108 /* These two functions implement the VCPU id numbering: one to compute them 109 * all and one to identify thread 0 of a VCORE. Any change to the first one 110 * is likely to have an impact on the second one, so let's keep them close. 111 */ 112 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 113 { 114 MachineState *ms = MACHINE(spapr); 115 unsigned int smp_threads = ms->smp.threads; 116 117 assert(spapr->vsmt); 118 return 119 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 120 } 121 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 122 PowerPCCPU *cpu) 123 { 124 assert(spapr->vsmt); 125 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 126 } 127 128 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 129 { 130 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 131 * and newer QEMUs don't even have them. In both cases, we don't want 132 * to send anything on the wire. 133 */ 134 return false; 135 } 136 137 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 138 .name = "icp/server", 139 .version_id = 1, 140 .minimum_version_id = 1, 141 .needed = pre_2_10_vmstate_dummy_icp_needed, 142 .fields = (VMStateField[]) { 143 VMSTATE_UNUSED(4), /* uint32_t xirr */ 144 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 145 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 146 VMSTATE_END_OF_LIST() 147 }, 148 }; 149 150 static void pre_2_10_vmstate_register_dummy_icp(int i) 151 { 152 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 153 (void *)(uintptr_t) i); 154 } 155 156 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 157 { 158 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 159 (void *)(uintptr_t) i); 160 } 161 162 int spapr_max_server_number(SpaprMachineState *spapr) 163 { 164 MachineState *ms = MACHINE(spapr); 165 166 assert(spapr->vsmt); 167 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 168 } 169 170 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 171 int smt_threads) 172 { 173 int i, ret = 0; 174 uint32_t servers_prop[smt_threads]; 175 uint32_t gservers_prop[smt_threads * 2]; 176 int index = spapr_get_vcpu_id(cpu); 177 178 if (cpu->compat_pvr) { 179 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 180 if (ret < 0) { 181 return ret; 182 } 183 } 184 185 /* Build interrupt servers and gservers properties */ 186 for (i = 0; i < smt_threads; i++) { 187 servers_prop[i] = cpu_to_be32(index + i); 188 /* Hack, direct the group queues back to cpu 0 */ 189 gservers_prop[i*2] = cpu_to_be32(index + i); 190 gservers_prop[i*2 + 1] = 0; 191 } 192 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 193 servers_prop, sizeof(servers_prop)); 194 if (ret < 0) { 195 return ret; 196 } 197 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 198 gservers_prop, sizeof(gservers_prop)); 199 200 return ret; 201 } 202 203 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 204 { 205 int index = spapr_get_vcpu_id(cpu); 206 uint32_t associativity[] = {cpu_to_be32(0x5), 207 cpu_to_be32(0x0), 208 cpu_to_be32(0x0), 209 cpu_to_be32(0x0), 210 cpu_to_be32(cpu->node_id), 211 cpu_to_be32(index)}; 212 213 /* Advertise NUMA via ibm,associativity */ 214 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 215 sizeof(associativity)); 216 } 217 218 /* Populate the "ibm,pa-features" property */ 219 static void spapr_populate_pa_features(SpaprMachineState *spapr, 220 PowerPCCPU *cpu, 221 void *fdt, int offset) 222 { 223 uint8_t pa_features_206[] = { 6, 0, 224 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 225 uint8_t pa_features_207[] = { 24, 0, 226 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 227 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 228 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 229 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 230 uint8_t pa_features_300[] = { 66, 0, 231 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 232 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 233 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 234 /* 6: DS207 */ 235 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 236 /* 16: Vector */ 237 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 238 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 239 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 240 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 241 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 242 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 243 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 244 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 245 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 246 /* 42: PM, 44: PC RA, 46: SC vec'd */ 247 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 248 /* 48: SIMD, 50: QP BFP, 52: String */ 249 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 250 /* 54: DecFP, 56: DecI, 58: SHA */ 251 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 252 /* 60: NM atomic, 62: RNG */ 253 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 254 }; 255 uint8_t *pa_features = NULL; 256 size_t pa_size; 257 258 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 259 pa_features = pa_features_206; 260 pa_size = sizeof(pa_features_206); 261 } 262 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 263 pa_features = pa_features_207; 264 pa_size = sizeof(pa_features_207); 265 } 266 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 267 pa_features = pa_features_300; 268 pa_size = sizeof(pa_features_300); 269 } 270 if (!pa_features) { 271 return; 272 } 273 274 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 275 /* 276 * Note: we keep CI large pages off by default because a 64K capable 277 * guest provisioned with large pages might otherwise try to map a qemu 278 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 279 * even if that qemu runs on a 4k host. 280 * We dd this bit back here if we are confident this is not an issue 281 */ 282 pa_features[3] |= 0x20; 283 } 284 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 285 pa_features[24] |= 0x80; /* Transactional memory support */ 286 } 287 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 288 /* Workaround for broken kernels that attempt (guest) radix 289 * mode when they can't handle it, if they see the radix bit set 290 * in pa-features. So hide it from them. */ 291 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 292 } 293 294 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 295 } 296 297 static hwaddr spapr_node0_size(MachineState *machine) 298 { 299 if (machine->numa_state->num_nodes) { 300 int i; 301 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 302 if (machine->numa_state->nodes[i].node_mem) { 303 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 304 machine->ram_size); 305 } 306 } 307 } 308 return machine->ram_size; 309 } 310 311 static void add_str(GString *s, const gchar *s1) 312 { 313 g_string_append_len(s, s1, strlen(s1) + 1); 314 } 315 316 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 317 hwaddr size) 318 { 319 uint32_t associativity[] = { 320 cpu_to_be32(0x4), /* length */ 321 cpu_to_be32(0x0), cpu_to_be32(0x0), 322 cpu_to_be32(0x0), cpu_to_be32(nodeid) 323 }; 324 char mem_name[32]; 325 uint64_t mem_reg_property[2]; 326 int off; 327 328 mem_reg_property[0] = cpu_to_be64(start); 329 mem_reg_property[1] = cpu_to_be64(size); 330 331 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 332 off = fdt_add_subnode(fdt, 0, mem_name); 333 _FDT(off); 334 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 335 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 336 sizeof(mem_reg_property)))); 337 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 338 sizeof(associativity)))); 339 return off; 340 } 341 342 static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt) 343 { 344 MachineState *machine = MACHINE(spapr); 345 hwaddr mem_start, node_size; 346 int i, nb_nodes = machine->numa_state->num_nodes; 347 NodeInfo *nodes = machine->numa_state->nodes; 348 349 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 350 if (!nodes[i].node_mem) { 351 continue; 352 } 353 if (mem_start >= machine->ram_size) { 354 node_size = 0; 355 } else { 356 node_size = nodes[i].node_mem; 357 if (node_size > machine->ram_size - mem_start) { 358 node_size = machine->ram_size - mem_start; 359 } 360 } 361 if (!mem_start) { 362 /* spapr_machine_init() checks for rma_size <= node0_size 363 * already */ 364 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 365 mem_start += spapr->rma_size; 366 node_size -= spapr->rma_size; 367 } 368 for ( ; node_size; ) { 369 hwaddr sizetmp = pow2floor(node_size); 370 371 /* mem_start != 0 here */ 372 if (ctzl(mem_start) < ctzl(sizetmp)) { 373 sizetmp = 1ULL << ctzl(mem_start); 374 } 375 376 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 377 node_size -= sizetmp; 378 mem_start += sizetmp; 379 } 380 } 381 382 return 0; 383 } 384 385 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 386 SpaprMachineState *spapr) 387 { 388 MachineState *ms = MACHINE(spapr); 389 PowerPCCPU *cpu = POWERPC_CPU(cs); 390 CPUPPCState *env = &cpu->env; 391 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 392 int index = spapr_get_vcpu_id(cpu); 393 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 394 0xffffffff, 0xffffffff}; 395 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 396 : SPAPR_TIMEBASE_FREQ; 397 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 398 uint32_t page_sizes_prop[64]; 399 size_t page_sizes_prop_size; 400 unsigned int smp_threads = ms->smp.threads; 401 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 402 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 403 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 404 SpaprDrc *drc; 405 int drc_index; 406 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 407 int i; 408 409 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 410 if (drc) { 411 drc_index = spapr_drc_index(drc); 412 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 413 } 414 415 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 416 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 417 418 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 419 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 420 env->dcache_line_size))); 421 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 422 env->dcache_line_size))); 423 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 424 env->icache_line_size))); 425 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 426 env->icache_line_size))); 427 428 if (pcc->l1_dcache_size) { 429 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 430 pcc->l1_dcache_size))); 431 } else { 432 warn_report("Unknown L1 dcache size for cpu"); 433 } 434 if (pcc->l1_icache_size) { 435 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 436 pcc->l1_icache_size))); 437 } else { 438 warn_report("Unknown L1 icache size for cpu"); 439 } 440 441 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 442 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 443 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 444 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 445 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 446 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 447 448 if (env->spr_cb[SPR_PURR].oea_read) { 449 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 450 } 451 if (env->spr_cb[SPR_SPURR].oea_read) { 452 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 453 } 454 455 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 456 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 457 segs, sizeof(segs)))); 458 } 459 460 /* Advertise VSX (vector extensions) if available 461 * 1 == VMX / Altivec available 462 * 2 == VSX available 463 * 464 * Only CPUs for which we create core types in spapr_cpu_core.c 465 * are possible, and all of those have VMX */ 466 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 467 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 468 } else { 469 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 470 } 471 472 /* Advertise DFP (Decimal Floating Point) if available 473 * 0 / no property == no DFP 474 * 1 == DFP available */ 475 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 476 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 477 } 478 479 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 480 sizeof(page_sizes_prop)); 481 if (page_sizes_prop_size) { 482 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 483 page_sizes_prop, page_sizes_prop_size))); 484 } 485 486 spapr_populate_pa_features(spapr, cpu, fdt, offset); 487 488 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 489 cs->cpu_index / vcpus_per_socket))); 490 491 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 492 pft_size_prop, sizeof(pft_size_prop)))); 493 494 if (ms->numa_state->num_nodes > 1) { 495 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 496 } 497 498 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 499 500 if (pcc->radix_page_info) { 501 for (i = 0; i < pcc->radix_page_info->count; i++) { 502 radix_AP_encodings[i] = 503 cpu_to_be32(pcc->radix_page_info->entries[i]); 504 } 505 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 506 radix_AP_encodings, 507 pcc->radix_page_info->count * 508 sizeof(radix_AP_encodings[0])))); 509 } 510 511 /* 512 * We set this property to let the guest know that it can use the large 513 * decrementer and its width in bits. 514 */ 515 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 516 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 517 pcc->lrg_decr_bits))); 518 } 519 520 static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spapr) 521 { 522 CPUState **rev; 523 CPUState *cs; 524 int n_cpus; 525 int cpus_offset; 526 char *nodename; 527 int i; 528 529 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 530 _FDT(cpus_offset); 531 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 532 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 533 534 /* 535 * We walk the CPUs in reverse order to ensure that CPU DT nodes 536 * created by fdt_add_subnode() end up in the right order in FDT 537 * for the guest kernel the enumerate the CPUs correctly. 538 * 539 * The CPU list cannot be traversed in reverse order, so we need 540 * to do extra work. 541 */ 542 n_cpus = 0; 543 rev = NULL; 544 CPU_FOREACH(cs) { 545 rev = g_renew(CPUState *, rev, n_cpus + 1); 546 rev[n_cpus++] = cs; 547 } 548 549 for (i = n_cpus - 1; i >= 0; i--) { 550 CPUState *cs = rev[i]; 551 PowerPCCPU *cpu = POWERPC_CPU(cs); 552 int index = spapr_get_vcpu_id(cpu); 553 DeviceClass *dc = DEVICE_GET_CLASS(cs); 554 int offset; 555 556 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 557 continue; 558 } 559 560 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 561 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 562 g_free(nodename); 563 _FDT(offset); 564 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 565 } 566 567 g_free(rev); 568 } 569 570 static int spapr_rng_populate_dt(void *fdt) 571 { 572 int node; 573 int ret; 574 575 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 576 if (node <= 0) { 577 return -1; 578 } 579 ret = fdt_setprop_string(fdt, node, "device_type", 580 "ibm,platform-facilities"); 581 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 582 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 583 584 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 585 if (node <= 0) { 586 return -1; 587 } 588 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 589 590 return ret ? -1 : 0; 591 } 592 593 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 594 { 595 MemoryDeviceInfoList *info; 596 597 for (info = list; info; info = info->next) { 598 MemoryDeviceInfo *value = info->value; 599 600 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 601 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 602 603 if (addr >= pcdimm_info->addr && 604 addr < (pcdimm_info->addr + pcdimm_info->size)) { 605 return pcdimm_info->node; 606 } 607 } 608 } 609 610 return -1; 611 } 612 613 struct sPAPRDrconfCellV2 { 614 uint32_t seq_lmbs; 615 uint64_t base_addr; 616 uint32_t drc_index; 617 uint32_t aa_index; 618 uint32_t flags; 619 } QEMU_PACKED; 620 621 typedef struct DrconfCellQueue { 622 struct sPAPRDrconfCellV2 cell; 623 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 624 } DrconfCellQueue; 625 626 static DrconfCellQueue * 627 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 628 uint32_t drc_index, uint32_t aa_index, 629 uint32_t flags) 630 { 631 DrconfCellQueue *elem; 632 633 elem = g_malloc0(sizeof(*elem)); 634 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 635 elem->cell.base_addr = cpu_to_be64(base_addr); 636 elem->cell.drc_index = cpu_to_be32(drc_index); 637 elem->cell.aa_index = cpu_to_be32(aa_index); 638 elem->cell.flags = cpu_to_be32(flags); 639 640 return elem; 641 } 642 643 /* ibm,dynamic-memory-v2 */ 644 static int spapr_populate_drmem_v2(SpaprMachineState *spapr, void *fdt, 645 int offset, MemoryDeviceInfoList *dimms) 646 { 647 MachineState *machine = MACHINE(spapr); 648 uint8_t *int_buf, *cur_index; 649 int ret; 650 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 651 uint64_t addr, cur_addr, size; 652 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 653 uint64_t mem_end = machine->device_memory->base + 654 memory_region_size(&machine->device_memory->mr); 655 uint32_t node, buf_len, nr_entries = 0; 656 SpaprDrc *drc; 657 DrconfCellQueue *elem, *next; 658 MemoryDeviceInfoList *info; 659 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 660 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 661 662 /* Entry to cover RAM and the gap area */ 663 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 664 SPAPR_LMB_FLAGS_RESERVED | 665 SPAPR_LMB_FLAGS_DRC_INVALID); 666 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 667 nr_entries++; 668 669 cur_addr = machine->device_memory->base; 670 for (info = dimms; info; info = info->next) { 671 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 672 673 addr = di->addr; 674 size = di->size; 675 node = di->node; 676 677 /* Entry for hot-pluggable area */ 678 if (cur_addr < addr) { 679 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 680 g_assert(drc); 681 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 682 cur_addr, spapr_drc_index(drc), -1, 0); 683 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 684 nr_entries++; 685 } 686 687 /* Entry for DIMM */ 688 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 689 g_assert(drc); 690 elem = spapr_get_drconf_cell(size / lmb_size, addr, 691 spapr_drc_index(drc), node, 692 SPAPR_LMB_FLAGS_ASSIGNED); 693 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 694 nr_entries++; 695 cur_addr = addr + size; 696 } 697 698 /* Entry for remaining hotpluggable area */ 699 if (cur_addr < mem_end) { 700 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 701 g_assert(drc); 702 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 703 cur_addr, spapr_drc_index(drc), -1, 0); 704 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 705 nr_entries++; 706 } 707 708 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 709 int_buf = cur_index = g_malloc0(buf_len); 710 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 711 cur_index += sizeof(nr_entries); 712 713 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 714 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 715 cur_index += sizeof(elem->cell); 716 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 717 g_free(elem); 718 } 719 720 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 721 g_free(int_buf); 722 if (ret < 0) { 723 return -1; 724 } 725 return 0; 726 } 727 728 /* ibm,dynamic-memory */ 729 static int spapr_populate_drmem_v1(SpaprMachineState *spapr, void *fdt, 730 int offset, MemoryDeviceInfoList *dimms) 731 { 732 MachineState *machine = MACHINE(spapr); 733 int i, ret; 734 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 735 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 736 uint32_t nr_lmbs = (machine->device_memory->base + 737 memory_region_size(&machine->device_memory->mr)) / 738 lmb_size; 739 uint32_t *int_buf, *cur_index, buf_len; 740 741 /* 742 * Allocate enough buffer size to fit in ibm,dynamic-memory 743 */ 744 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 745 cur_index = int_buf = g_malloc0(buf_len); 746 int_buf[0] = cpu_to_be32(nr_lmbs); 747 cur_index++; 748 for (i = 0; i < nr_lmbs; i++) { 749 uint64_t addr = i * lmb_size; 750 uint32_t *dynamic_memory = cur_index; 751 752 if (i >= device_lmb_start) { 753 SpaprDrc *drc; 754 755 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 756 g_assert(drc); 757 758 dynamic_memory[0] = cpu_to_be32(addr >> 32); 759 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 760 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 761 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 762 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 763 if (memory_region_present(get_system_memory(), addr)) { 764 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 765 } else { 766 dynamic_memory[5] = cpu_to_be32(0); 767 } 768 } else { 769 /* 770 * LMB information for RMA, boot time RAM and gap b/n RAM and 771 * device memory region -- all these are marked as reserved 772 * and as having no valid DRC. 773 */ 774 dynamic_memory[0] = cpu_to_be32(addr >> 32); 775 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 776 dynamic_memory[2] = cpu_to_be32(0); 777 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 778 dynamic_memory[4] = cpu_to_be32(-1); 779 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 780 SPAPR_LMB_FLAGS_DRC_INVALID); 781 } 782 783 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 784 } 785 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 786 g_free(int_buf); 787 if (ret < 0) { 788 return -1; 789 } 790 return 0; 791 } 792 793 /* 794 * Adds ibm,dynamic-reconfiguration-memory node. 795 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 796 * of this device tree node. 797 */ 798 static int spapr_populate_drconf_memory(SpaprMachineState *spapr, void *fdt) 799 { 800 MachineState *machine = MACHINE(spapr); 801 int nb_numa_nodes = machine->numa_state->num_nodes; 802 int ret, i, offset; 803 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 804 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 805 uint32_t *int_buf, *cur_index, buf_len; 806 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 807 MemoryDeviceInfoList *dimms = NULL; 808 809 /* 810 * Don't create the node if there is no device memory 811 */ 812 if (machine->ram_size == machine->maxram_size) { 813 return 0; 814 } 815 816 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 817 818 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 819 sizeof(prop_lmb_size)); 820 if (ret < 0) { 821 return ret; 822 } 823 824 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 825 if (ret < 0) { 826 return ret; 827 } 828 829 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 830 if (ret < 0) { 831 return ret; 832 } 833 834 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 835 dimms = qmp_memory_device_list(); 836 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 837 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 838 } else { 839 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 840 } 841 qapi_free_MemoryDeviceInfoList(dimms); 842 843 if (ret < 0) { 844 return ret; 845 } 846 847 /* ibm,associativity-lookup-arrays */ 848 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 849 cur_index = int_buf = g_malloc0(buf_len); 850 int_buf[0] = cpu_to_be32(nr_nodes); 851 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 852 cur_index += 2; 853 for (i = 0; i < nr_nodes; i++) { 854 uint32_t associativity[] = { 855 cpu_to_be32(0x0), 856 cpu_to_be32(0x0), 857 cpu_to_be32(0x0), 858 cpu_to_be32(i) 859 }; 860 memcpy(cur_index, associativity, sizeof(associativity)); 861 cur_index += 4; 862 } 863 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 864 (cur_index - int_buf) * sizeof(uint32_t)); 865 g_free(int_buf); 866 867 return ret; 868 } 869 870 static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt, 871 SpaprOptionVector *ov5_updates) 872 { 873 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 874 int ret = 0, offset; 875 876 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 877 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 878 g_assert(smc->dr_lmb_enabled); 879 ret = spapr_populate_drconf_memory(spapr, fdt); 880 if (ret) { 881 goto out; 882 } 883 } 884 885 offset = fdt_path_offset(fdt, "/chosen"); 886 if (offset < 0) { 887 offset = fdt_add_subnode(fdt, 0, "chosen"); 888 if (offset < 0) { 889 return offset; 890 } 891 } 892 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 893 "ibm,architecture-vec-5"); 894 895 out: 896 return ret; 897 } 898 899 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 900 { 901 MachineState *ms = MACHINE(spapr); 902 int rtas; 903 GString *hypertas = g_string_sized_new(256); 904 GString *qemu_hypertas = g_string_sized_new(256); 905 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 906 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 907 memory_region_size(&MACHINE(spapr)->device_memory->mr); 908 uint32_t lrdr_capacity[] = { 909 cpu_to_be32(max_device_addr >> 32), 910 cpu_to_be32(max_device_addr & 0xffffffff), 911 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 912 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 913 }; 914 uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0); 915 uint32_t maxdomains[] = { 916 cpu_to_be32(4), 917 maxdomain, 918 maxdomain, 919 maxdomain, 920 cpu_to_be32(spapr->gpu_numa_id), 921 }; 922 923 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 924 925 /* hypertas */ 926 add_str(hypertas, "hcall-pft"); 927 add_str(hypertas, "hcall-term"); 928 add_str(hypertas, "hcall-dabr"); 929 add_str(hypertas, "hcall-interrupt"); 930 add_str(hypertas, "hcall-tce"); 931 add_str(hypertas, "hcall-vio"); 932 add_str(hypertas, "hcall-splpar"); 933 add_str(hypertas, "hcall-join"); 934 add_str(hypertas, "hcall-bulk"); 935 add_str(hypertas, "hcall-set-mode"); 936 add_str(hypertas, "hcall-sprg0"); 937 add_str(hypertas, "hcall-copy"); 938 add_str(hypertas, "hcall-debug"); 939 add_str(hypertas, "hcall-vphn"); 940 add_str(qemu_hypertas, "hcall-memop1"); 941 942 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 943 add_str(hypertas, "hcall-multi-tce"); 944 } 945 946 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 947 add_str(hypertas, "hcall-hpt-resize"); 948 } 949 950 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 951 hypertas->str, hypertas->len)); 952 g_string_free(hypertas, TRUE); 953 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 954 qemu_hypertas->str, qemu_hypertas->len)); 955 g_string_free(qemu_hypertas, TRUE); 956 957 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 958 refpoints, sizeof(refpoints))); 959 960 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 961 maxdomains, sizeof(maxdomains))); 962 963 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 964 RTAS_ERROR_LOG_MAX)); 965 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 966 RTAS_EVENT_SCAN_RATE)); 967 968 g_assert(msi_nonbroken); 969 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 970 971 /* 972 * According to PAPR, rtas ibm,os-term does not guarantee a return 973 * back to the guest cpu. 974 * 975 * While an additional ibm,extended-os-term property indicates 976 * that rtas call return will always occur. Set this property. 977 */ 978 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 979 980 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 981 lrdr_capacity, sizeof(lrdr_capacity))); 982 983 spapr_dt_rtas_tokens(fdt, rtas); 984 } 985 986 /* 987 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 988 * and the XIVE features that the guest may request and thus the valid 989 * values for bytes 23..26 of option vector 5: 990 */ 991 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 992 int chosen) 993 { 994 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 995 996 char val[2 * 4] = { 997 23, 0x00, /* XICS / XIVE mode */ 998 24, 0x00, /* Hash/Radix, filled in below. */ 999 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1000 26, 0x40, /* Radix options: GTSE == yes. */ 1001 }; 1002 1003 if (spapr->irq->xics && spapr->irq->xive) { 1004 val[1] = SPAPR_OV5_XIVE_BOTH; 1005 } else if (spapr->irq->xive) { 1006 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1007 } else { 1008 assert(spapr->irq->xics); 1009 val[1] = SPAPR_OV5_XIVE_LEGACY; 1010 } 1011 1012 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1013 first_ppc_cpu->compat_pvr)) { 1014 /* 1015 * If we're in a pre POWER9 compat mode then the guest should 1016 * do hash and use the legacy interrupt mode 1017 */ 1018 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1019 val[3] = 0x00; /* Hash */ 1020 } else if (kvm_enabled()) { 1021 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1022 val[3] = 0x80; /* OV5_MMU_BOTH */ 1023 } else if (kvmppc_has_cap_mmu_radix()) { 1024 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1025 } else { 1026 val[3] = 0x00; /* Hash */ 1027 } 1028 } else { 1029 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1030 val[3] = 0xC0; 1031 } 1032 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1033 val, sizeof(val))); 1034 } 1035 1036 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt) 1037 { 1038 MachineState *machine = MACHINE(spapr); 1039 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1040 int chosen; 1041 const char *boot_device = machine->boot_order; 1042 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1043 size_t cb = 0; 1044 char *bootlist = get_boot_devices_list(&cb); 1045 1046 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1047 1048 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1049 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1050 machine->kernel_cmdline)); 1051 } 1052 if (spapr->initrd_size) { 1053 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1054 spapr->initrd_base)); 1055 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1056 spapr->initrd_base + spapr->initrd_size)); 1057 } 1058 1059 if (spapr->kernel_size) { 1060 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1061 cpu_to_be64(spapr->kernel_size) }; 1062 1063 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1064 &kprop, sizeof(kprop))); 1065 if (spapr->kernel_le) { 1066 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1067 } 1068 } 1069 if (boot_menu) { 1070 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1071 } 1072 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1073 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1074 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1075 1076 if (cb && bootlist) { 1077 int i; 1078 1079 for (i = 0; i < cb; i++) { 1080 if (bootlist[i] == '\n') { 1081 bootlist[i] = ' '; 1082 } 1083 } 1084 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1085 } 1086 1087 if (boot_device && strlen(boot_device)) { 1088 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1089 } 1090 1091 if (!spapr->has_graphics && stdout_path) { 1092 /* 1093 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1094 * kernel. New platforms should only use the "stdout-path" property. Set 1095 * the new property and continue using older property to remain 1096 * compatible with the existing firmware. 1097 */ 1098 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1099 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1100 } 1101 1102 /* We can deal with BAR reallocation just fine, advertise it to the guest */ 1103 if (smc->linux_pci_probe) { 1104 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1105 } 1106 1107 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1108 1109 g_free(stdout_path); 1110 g_free(bootlist); 1111 } 1112 1113 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1114 { 1115 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1116 * KVM to work under pHyp with some guest co-operation */ 1117 int hypervisor; 1118 uint8_t hypercall[16]; 1119 1120 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1121 /* indicate KVM hypercall interface */ 1122 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1123 if (kvmppc_has_cap_fixup_hcalls()) { 1124 /* 1125 * Older KVM versions with older guest kernels were broken 1126 * with the magic page, don't allow the guest to map it. 1127 */ 1128 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1129 sizeof(hypercall))) { 1130 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1131 hypercall, sizeof(hypercall))); 1132 } 1133 } 1134 } 1135 1136 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1137 { 1138 MachineState *machine = MACHINE(spapr); 1139 MachineClass *mc = MACHINE_GET_CLASS(machine); 1140 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1141 int ret; 1142 void *fdt; 1143 SpaprPhbState *phb; 1144 char *buf; 1145 1146 fdt = g_malloc0(space); 1147 _FDT((fdt_create_empty_tree(fdt, space))); 1148 1149 /* Root node */ 1150 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1151 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1152 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1153 1154 /* Guest UUID & Name*/ 1155 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1156 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1157 if (qemu_uuid_set) { 1158 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1159 } 1160 g_free(buf); 1161 1162 if (qemu_get_vm_name()) { 1163 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1164 qemu_get_vm_name())); 1165 } 1166 1167 /* Host Model & Serial Number */ 1168 if (spapr->host_model) { 1169 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1170 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1171 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1172 g_free(buf); 1173 } 1174 1175 if (spapr->host_serial) { 1176 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1177 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1178 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1179 g_free(buf); 1180 } 1181 1182 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1183 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1184 1185 /* /interrupt controller */ 1186 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1187 1188 ret = spapr_populate_memory(spapr, fdt); 1189 if (ret < 0) { 1190 error_report("couldn't setup memory nodes in fdt"); 1191 exit(1); 1192 } 1193 1194 /* /vdevice */ 1195 spapr_dt_vdevice(spapr->vio_bus, fdt); 1196 1197 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1198 ret = spapr_rng_populate_dt(fdt); 1199 if (ret < 0) { 1200 error_report("could not set up rng device in the fdt"); 1201 exit(1); 1202 } 1203 } 1204 1205 QLIST_FOREACH(phb, &spapr->phbs, list) { 1206 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1207 if (ret < 0) { 1208 error_report("couldn't setup PCI devices in fdt"); 1209 exit(1); 1210 } 1211 } 1212 1213 /* cpus */ 1214 spapr_populate_cpus_dt_node(fdt, spapr); 1215 1216 if (smc->dr_lmb_enabled) { 1217 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1218 } 1219 1220 if (mc->has_hotpluggable_cpus) { 1221 int offset = fdt_path_offset(fdt, "/cpus"); 1222 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1223 if (ret < 0) { 1224 error_report("Couldn't set up CPU DR device tree properties"); 1225 exit(1); 1226 } 1227 } 1228 1229 /* /event-sources */ 1230 spapr_dt_events(spapr, fdt); 1231 1232 /* /rtas */ 1233 spapr_dt_rtas(spapr, fdt); 1234 1235 /* /chosen */ 1236 if (reset) { 1237 spapr_dt_chosen(spapr, fdt); 1238 } 1239 1240 /* /hypervisor */ 1241 if (kvm_enabled()) { 1242 spapr_dt_hypervisor(spapr, fdt); 1243 } 1244 1245 /* Build memory reserve map */ 1246 if (reset) { 1247 if (spapr->kernel_size) { 1248 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1249 } 1250 if (spapr->initrd_size) { 1251 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1252 spapr->initrd_size))); 1253 } 1254 } 1255 1256 /* ibm,client-architecture-support updates */ 1257 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1258 if (ret < 0) { 1259 error_report("couldn't setup CAS properties fdt"); 1260 exit(1); 1261 } 1262 1263 if (smc->dr_phb_enabled) { 1264 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); 1265 if (ret < 0) { 1266 error_report("Couldn't set up PHB DR device tree properties"); 1267 exit(1); 1268 } 1269 } 1270 1271 return fdt; 1272 } 1273 1274 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1275 { 1276 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1277 } 1278 1279 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1280 PowerPCCPU *cpu) 1281 { 1282 CPUPPCState *env = &cpu->env; 1283 1284 /* The TCG path should also be holding the BQL at this point */ 1285 g_assert(qemu_mutex_iothread_locked()); 1286 1287 if (msr_pr) { 1288 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1289 env->gpr[3] = H_PRIVILEGE; 1290 } else { 1291 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1292 } 1293 } 1294 1295 struct LPCRSyncState { 1296 target_ulong value; 1297 target_ulong mask; 1298 }; 1299 1300 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1301 { 1302 struct LPCRSyncState *s = arg.host_ptr; 1303 PowerPCCPU *cpu = POWERPC_CPU(cs); 1304 CPUPPCState *env = &cpu->env; 1305 target_ulong lpcr; 1306 1307 cpu_synchronize_state(cs); 1308 lpcr = env->spr[SPR_LPCR]; 1309 lpcr &= ~s->mask; 1310 lpcr |= s->value; 1311 ppc_store_lpcr(cpu, lpcr); 1312 } 1313 1314 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1315 { 1316 CPUState *cs; 1317 struct LPCRSyncState s = { 1318 .value = value, 1319 .mask = mask 1320 }; 1321 CPU_FOREACH(cs) { 1322 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1323 } 1324 } 1325 1326 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1327 { 1328 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1329 1330 /* Copy PATE1:GR into PATE0:HR */ 1331 entry->dw0 = spapr->patb_entry & PATE0_HR; 1332 entry->dw1 = spapr->patb_entry; 1333 } 1334 1335 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1336 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1337 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1338 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1339 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1340 1341 /* 1342 * Get the fd to access the kernel htab, re-opening it if necessary 1343 */ 1344 static int get_htab_fd(SpaprMachineState *spapr) 1345 { 1346 Error *local_err = NULL; 1347 1348 if (spapr->htab_fd >= 0) { 1349 return spapr->htab_fd; 1350 } 1351 1352 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1353 if (spapr->htab_fd < 0) { 1354 error_report_err(local_err); 1355 } 1356 1357 return spapr->htab_fd; 1358 } 1359 1360 void close_htab_fd(SpaprMachineState *spapr) 1361 { 1362 if (spapr->htab_fd >= 0) { 1363 close(spapr->htab_fd); 1364 } 1365 spapr->htab_fd = -1; 1366 } 1367 1368 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1369 { 1370 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1371 1372 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1373 } 1374 1375 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1376 { 1377 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1378 1379 assert(kvm_enabled()); 1380 1381 if (!spapr->htab) { 1382 return 0; 1383 } 1384 1385 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1386 } 1387 1388 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1389 hwaddr ptex, int n) 1390 { 1391 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1392 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1393 1394 if (!spapr->htab) { 1395 /* 1396 * HTAB is controlled by KVM. Fetch into temporary buffer 1397 */ 1398 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1399 kvmppc_read_hptes(hptes, ptex, n); 1400 return hptes; 1401 } 1402 1403 /* 1404 * HTAB is controlled by QEMU. Just point to the internally 1405 * accessible PTEG. 1406 */ 1407 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1408 } 1409 1410 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1411 const ppc_hash_pte64_t *hptes, 1412 hwaddr ptex, int n) 1413 { 1414 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1415 1416 if (!spapr->htab) { 1417 g_free((void *)hptes); 1418 } 1419 1420 /* Nothing to do for qemu managed HPT */ 1421 } 1422 1423 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1424 uint64_t pte0, uint64_t pte1) 1425 { 1426 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1427 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1428 1429 if (!spapr->htab) { 1430 kvmppc_write_hpte(ptex, pte0, pte1); 1431 } else { 1432 if (pte0 & HPTE64_V_VALID) { 1433 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1434 /* 1435 * When setting valid, we write PTE1 first. This ensures 1436 * proper synchronization with the reading code in 1437 * ppc_hash64_pteg_search() 1438 */ 1439 smp_wmb(); 1440 stq_p(spapr->htab + offset, pte0); 1441 } else { 1442 stq_p(spapr->htab + offset, pte0); 1443 /* 1444 * When clearing it we set PTE0 first. This ensures proper 1445 * synchronization with the reading code in 1446 * ppc_hash64_pteg_search() 1447 */ 1448 smp_wmb(); 1449 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1450 } 1451 } 1452 } 1453 1454 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1455 uint64_t pte1) 1456 { 1457 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1458 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1459 1460 if (!spapr->htab) { 1461 /* There should always be a hash table when this is called */ 1462 error_report("spapr_hpte_set_c called with no hash table !"); 1463 return; 1464 } 1465 1466 /* The HW performs a non-atomic byte update */ 1467 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1468 } 1469 1470 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1471 uint64_t pte1) 1472 { 1473 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1474 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1475 1476 if (!spapr->htab) { 1477 /* There should always be a hash table when this is called */ 1478 error_report("spapr_hpte_set_r called with no hash table !"); 1479 return; 1480 } 1481 1482 /* The HW performs a non-atomic byte update */ 1483 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1484 } 1485 1486 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1487 { 1488 int shift; 1489 1490 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1491 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1492 * that's much more than is needed for Linux guests */ 1493 shift = ctz64(pow2ceil(ramsize)) - 7; 1494 shift = MAX(shift, 18); /* Minimum architected size */ 1495 shift = MIN(shift, 46); /* Maximum architected size */ 1496 return shift; 1497 } 1498 1499 void spapr_free_hpt(SpaprMachineState *spapr) 1500 { 1501 g_free(spapr->htab); 1502 spapr->htab = NULL; 1503 spapr->htab_shift = 0; 1504 close_htab_fd(spapr); 1505 } 1506 1507 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 1508 Error **errp) 1509 { 1510 long rc; 1511 1512 /* Clean up any HPT info from a previous boot */ 1513 spapr_free_hpt(spapr); 1514 1515 rc = kvmppc_reset_htab(shift); 1516 if (rc < 0) { 1517 /* kernel-side HPT needed, but couldn't allocate one */ 1518 error_setg_errno(errp, errno, 1519 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1520 shift); 1521 /* This is almost certainly fatal, but if the caller really 1522 * wants to carry on with shift == 0, it's welcome to try */ 1523 } else if (rc > 0) { 1524 /* kernel-side HPT allocated */ 1525 if (rc != shift) { 1526 error_setg(errp, 1527 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1528 shift, rc); 1529 } 1530 1531 spapr->htab_shift = shift; 1532 spapr->htab = NULL; 1533 } else { 1534 /* kernel-side HPT not needed, allocate in userspace instead */ 1535 size_t size = 1ULL << shift; 1536 int i; 1537 1538 spapr->htab = qemu_memalign(size, size); 1539 if (!spapr->htab) { 1540 error_setg_errno(errp, errno, 1541 "Could not allocate HPT of order %d", shift); 1542 return; 1543 } 1544 1545 memset(spapr->htab, 0, size); 1546 spapr->htab_shift = shift; 1547 1548 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1549 DIRTY_HPTE(HPTE(spapr->htab, i)); 1550 } 1551 } 1552 /* We're setting up a hash table, so that means we're not radix */ 1553 spapr->patb_entry = 0; 1554 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1555 } 1556 1557 void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr) 1558 { 1559 int hpt_shift; 1560 1561 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1562 || (spapr->cas_reboot 1563 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1564 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1565 } else { 1566 uint64_t current_ram_size; 1567 1568 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1569 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1570 } 1571 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1572 1573 if (spapr->vrma_adjust) { 1574 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1575 spapr->htab_shift); 1576 } 1577 } 1578 1579 static int spapr_reset_drcs(Object *child, void *opaque) 1580 { 1581 SpaprDrc *drc = 1582 (SpaprDrc *) object_dynamic_cast(child, 1583 TYPE_SPAPR_DR_CONNECTOR); 1584 1585 if (drc) { 1586 spapr_drc_reset(drc); 1587 } 1588 1589 return 0; 1590 } 1591 1592 static void spapr_machine_reset(MachineState *machine) 1593 { 1594 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1595 PowerPCCPU *first_ppc_cpu; 1596 hwaddr fdt_addr; 1597 void *fdt; 1598 int rc; 1599 1600 kvmppc_svm_off(&error_fatal); 1601 spapr_caps_apply(spapr); 1602 1603 first_ppc_cpu = POWERPC_CPU(first_cpu); 1604 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1605 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1606 spapr->max_compat_pvr)) { 1607 /* 1608 * If using KVM with radix mode available, VCPUs can be started 1609 * without a HPT because KVM will start them in radix mode. 1610 * Set the GR bit in PATE so that we know there is no HPT. 1611 */ 1612 spapr->patb_entry = PATE1_GR; 1613 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1614 } else { 1615 spapr_setup_hpt_and_vrma(spapr); 1616 } 1617 1618 qemu_devices_reset(); 1619 1620 /* 1621 * If this reset wasn't generated by CAS, we should reset our 1622 * negotiated options and start from scratch 1623 */ 1624 if (!spapr->cas_reboot) { 1625 spapr_ovec_cleanup(spapr->ov5_cas); 1626 spapr->ov5_cas = spapr_ovec_new(); 1627 1628 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1629 } 1630 1631 /* 1632 * This is fixing some of the default configuration of the XIVE 1633 * devices. To be called after the reset of the machine devices. 1634 */ 1635 spapr_irq_reset(spapr, &error_fatal); 1636 1637 /* 1638 * There is no CAS under qtest. Simulate one to please the code that 1639 * depends on spapr->ov5_cas. This is especially needed to test device 1640 * unplug, so we do that before resetting the DRCs. 1641 */ 1642 if (qtest_enabled()) { 1643 spapr_ovec_cleanup(spapr->ov5_cas); 1644 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1645 } 1646 1647 /* DRC reset may cause a device to be unplugged. This will cause troubles 1648 * if this device is used by another device (eg, a running vhost backend 1649 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1650 * situations, we reset DRCs after all devices have been reset. 1651 */ 1652 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1653 1654 spapr_clear_pending_events(spapr); 1655 1656 /* 1657 * We place the device tree and RTAS just below either the top of the RMA, 1658 * or just below 2GB, whichever is lower, so that it can be 1659 * processed with 32-bit real mode code if necessary 1660 */ 1661 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1662 1663 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1664 1665 rc = fdt_pack(fdt); 1666 1667 /* Should only fail if we've built a corrupted tree */ 1668 assert(rc == 0); 1669 1670 /* Load the fdt */ 1671 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1672 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1673 g_free(spapr->fdt_blob); 1674 spapr->fdt_size = fdt_totalsize(fdt); 1675 spapr->fdt_initial_size = spapr->fdt_size; 1676 spapr->fdt_blob = fdt; 1677 1678 /* Set up the entry state */ 1679 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); 1680 first_ppc_cpu->env.gpr[5] = 0; 1681 1682 spapr->cas_reboot = false; 1683 } 1684 1685 static void spapr_create_nvram(SpaprMachineState *spapr) 1686 { 1687 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1688 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1689 1690 if (dinfo) { 1691 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1692 &error_fatal); 1693 } 1694 1695 qdev_init_nofail(dev); 1696 1697 spapr->nvram = (struct SpaprNvram *)dev; 1698 } 1699 1700 static void spapr_rtc_create(SpaprMachineState *spapr) 1701 { 1702 object_initialize_child(OBJECT(spapr), "rtc", 1703 &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1704 &error_fatal, NULL); 1705 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1706 &error_fatal); 1707 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1708 "date", &error_fatal); 1709 } 1710 1711 /* Returns whether we want to use VGA or not */ 1712 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1713 { 1714 switch (vga_interface_type) { 1715 case VGA_NONE: 1716 return false; 1717 case VGA_DEVICE: 1718 return true; 1719 case VGA_STD: 1720 case VGA_VIRTIO: 1721 case VGA_CIRRUS: 1722 return pci_vga_init(pci_bus) != NULL; 1723 default: 1724 error_setg(errp, 1725 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1726 return false; 1727 } 1728 } 1729 1730 static int spapr_pre_load(void *opaque) 1731 { 1732 int rc; 1733 1734 rc = spapr_caps_pre_load(opaque); 1735 if (rc) { 1736 return rc; 1737 } 1738 1739 return 0; 1740 } 1741 1742 static int spapr_post_load(void *opaque, int version_id) 1743 { 1744 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1745 int err = 0; 1746 1747 err = spapr_caps_post_migration(spapr); 1748 if (err) { 1749 return err; 1750 } 1751 1752 /* 1753 * In earlier versions, there was no separate qdev for the PAPR 1754 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1755 * So when migrating from those versions, poke the incoming offset 1756 * value into the RTC device 1757 */ 1758 if (version_id < 3) { 1759 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1760 if (err) { 1761 return err; 1762 } 1763 } 1764 1765 if (kvm_enabled() && spapr->patb_entry) { 1766 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1767 bool radix = !!(spapr->patb_entry & PATE1_GR); 1768 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1769 1770 /* 1771 * Update LPCR:HR and UPRT as they may not be set properly in 1772 * the stream 1773 */ 1774 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1775 LPCR_HR | LPCR_UPRT); 1776 1777 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1778 if (err) { 1779 error_report("Process table config unsupported by the host"); 1780 return -EINVAL; 1781 } 1782 } 1783 1784 err = spapr_irq_post_load(spapr, version_id); 1785 if (err) { 1786 return err; 1787 } 1788 1789 return err; 1790 } 1791 1792 static int spapr_pre_save(void *opaque) 1793 { 1794 int rc; 1795 1796 rc = spapr_caps_pre_save(opaque); 1797 if (rc) { 1798 return rc; 1799 } 1800 1801 return 0; 1802 } 1803 1804 static bool version_before_3(void *opaque, int version_id) 1805 { 1806 return version_id < 3; 1807 } 1808 1809 static bool spapr_pending_events_needed(void *opaque) 1810 { 1811 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1812 return !QTAILQ_EMPTY(&spapr->pending_events); 1813 } 1814 1815 static const VMStateDescription vmstate_spapr_event_entry = { 1816 .name = "spapr_event_log_entry", 1817 .version_id = 1, 1818 .minimum_version_id = 1, 1819 .fields = (VMStateField[]) { 1820 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1821 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1822 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1823 NULL, extended_length), 1824 VMSTATE_END_OF_LIST() 1825 }, 1826 }; 1827 1828 static const VMStateDescription vmstate_spapr_pending_events = { 1829 .name = "spapr_pending_events", 1830 .version_id = 1, 1831 .minimum_version_id = 1, 1832 .needed = spapr_pending_events_needed, 1833 .fields = (VMStateField[]) { 1834 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1835 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1836 VMSTATE_END_OF_LIST() 1837 }, 1838 }; 1839 1840 static bool spapr_ov5_cas_needed(void *opaque) 1841 { 1842 SpaprMachineState *spapr = opaque; 1843 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1844 bool cas_needed; 1845 1846 /* Prior to the introduction of SpaprOptionVector, we had two option 1847 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1848 * Both of these options encode machine topology into the device-tree 1849 * in such a way that the now-booted OS should still be able to interact 1850 * appropriately with QEMU regardless of what options were actually 1851 * negotiatied on the source side. 1852 * 1853 * As such, we can avoid migrating the CAS-negotiated options if these 1854 * are the only options available on the current machine/platform. 1855 * Since these are the only options available for pseries-2.7 and 1856 * earlier, this allows us to maintain old->new/new->old migration 1857 * compatibility. 1858 * 1859 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1860 * via default pseries-2.8 machines and explicit command-line parameters. 1861 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1862 * of the actual CAS-negotiated values to continue working properly. For 1863 * example, availability of memory unplug depends on knowing whether 1864 * OV5_HP_EVT was negotiated via CAS. 1865 * 1866 * Thus, for any cases where the set of available CAS-negotiatable 1867 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1868 * include the CAS-negotiated options in the migration stream, unless 1869 * if they affect boot time behaviour only. 1870 */ 1871 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1872 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1873 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1874 1875 /* We need extra information if we have any bits outside the mask 1876 * defined above */ 1877 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1878 1879 spapr_ovec_cleanup(ov5_mask); 1880 1881 return cas_needed; 1882 } 1883 1884 static const VMStateDescription vmstate_spapr_ov5_cas = { 1885 .name = "spapr_option_vector_ov5_cas", 1886 .version_id = 1, 1887 .minimum_version_id = 1, 1888 .needed = spapr_ov5_cas_needed, 1889 .fields = (VMStateField[]) { 1890 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1891 vmstate_spapr_ovec, SpaprOptionVector), 1892 VMSTATE_END_OF_LIST() 1893 }, 1894 }; 1895 1896 static bool spapr_patb_entry_needed(void *opaque) 1897 { 1898 SpaprMachineState *spapr = opaque; 1899 1900 return !!spapr->patb_entry; 1901 } 1902 1903 static const VMStateDescription vmstate_spapr_patb_entry = { 1904 .name = "spapr_patb_entry", 1905 .version_id = 1, 1906 .minimum_version_id = 1, 1907 .needed = spapr_patb_entry_needed, 1908 .fields = (VMStateField[]) { 1909 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1910 VMSTATE_END_OF_LIST() 1911 }, 1912 }; 1913 1914 static bool spapr_irq_map_needed(void *opaque) 1915 { 1916 SpaprMachineState *spapr = opaque; 1917 1918 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1919 } 1920 1921 static const VMStateDescription vmstate_spapr_irq_map = { 1922 .name = "spapr_irq_map", 1923 .version_id = 1, 1924 .minimum_version_id = 1, 1925 .needed = spapr_irq_map_needed, 1926 .fields = (VMStateField[]) { 1927 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1928 VMSTATE_END_OF_LIST() 1929 }, 1930 }; 1931 1932 static bool spapr_dtb_needed(void *opaque) 1933 { 1934 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1935 1936 return smc->update_dt_enabled; 1937 } 1938 1939 static int spapr_dtb_pre_load(void *opaque) 1940 { 1941 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1942 1943 g_free(spapr->fdt_blob); 1944 spapr->fdt_blob = NULL; 1945 spapr->fdt_size = 0; 1946 1947 return 0; 1948 } 1949 1950 static const VMStateDescription vmstate_spapr_dtb = { 1951 .name = "spapr_dtb", 1952 .version_id = 1, 1953 .minimum_version_id = 1, 1954 .needed = spapr_dtb_needed, 1955 .pre_load = spapr_dtb_pre_load, 1956 .fields = (VMStateField[]) { 1957 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1958 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1959 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1960 fdt_size), 1961 VMSTATE_END_OF_LIST() 1962 }, 1963 }; 1964 1965 static const VMStateDescription vmstate_spapr = { 1966 .name = "spapr", 1967 .version_id = 3, 1968 .minimum_version_id = 1, 1969 .pre_load = spapr_pre_load, 1970 .post_load = spapr_post_load, 1971 .pre_save = spapr_pre_save, 1972 .fields = (VMStateField[]) { 1973 /* used to be @next_irq */ 1974 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1975 1976 /* RTC offset */ 1977 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 1978 1979 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 1980 VMSTATE_END_OF_LIST() 1981 }, 1982 .subsections = (const VMStateDescription*[]) { 1983 &vmstate_spapr_ov5_cas, 1984 &vmstate_spapr_patb_entry, 1985 &vmstate_spapr_pending_events, 1986 &vmstate_spapr_cap_htm, 1987 &vmstate_spapr_cap_vsx, 1988 &vmstate_spapr_cap_dfp, 1989 &vmstate_spapr_cap_cfpc, 1990 &vmstate_spapr_cap_sbbc, 1991 &vmstate_spapr_cap_ibs, 1992 &vmstate_spapr_cap_hpt_maxpagesize, 1993 &vmstate_spapr_irq_map, 1994 &vmstate_spapr_cap_nested_kvm_hv, 1995 &vmstate_spapr_dtb, 1996 &vmstate_spapr_cap_large_decr, 1997 &vmstate_spapr_cap_ccf_assist, 1998 NULL 1999 } 2000 }; 2001 2002 static int htab_save_setup(QEMUFile *f, void *opaque) 2003 { 2004 SpaprMachineState *spapr = opaque; 2005 2006 /* "Iteration" header */ 2007 if (!spapr->htab_shift) { 2008 qemu_put_be32(f, -1); 2009 } else { 2010 qemu_put_be32(f, spapr->htab_shift); 2011 } 2012 2013 if (spapr->htab) { 2014 spapr->htab_save_index = 0; 2015 spapr->htab_first_pass = true; 2016 } else { 2017 if (spapr->htab_shift) { 2018 assert(kvm_enabled()); 2019 } 2020 } 2021 2022 2023 return 0; 2024 } 2025 2026 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2027 int chunkstart, int n_valid, int n_invalid) 2028 { 2029 qemu_put_be32(f, chunkstart); 2030 qemu_put_be16(f, n_valid); 2031 qemu_put_be16(f, n_invalid); 2032 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2033 HASH_PTE_SIZE_64 * n_valid); 2034 } 2035 2036 static void htab_save_end_marker(QEMUFile *f) 2037 { 2038 qemu_put_be32(f, 0); 2039 qemu_put_be16(f, 0); 2040 qemu_put_be16(f, 0); 2041 } 2042 2043 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2044 int64_t max_ns) 2045 { 2046 bool has_timeout = max_ns != -1; 2047 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2048 int index = spapr->htab_save_index; 2049 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2050 2051 assert(spapr->htab_first_pass); 2052 2053 do { 2054 int chunkstart; 2055 2056 /* Consume invalid HPTEs */ 2057 while ((index < htabslots) 2058 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2059 CLEAN_HPTE(HPTE(spapr->htab, index)); 2060 index++; 2061 } 2062 2063 /* Consume valid HPTEs */ 2064 chunkstart = index; 2065 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2066 && HPTE_VALID(HPTE(spapr->htab, index))) { 2067 CLEAN_HPTE(HPTE(spapr->htab, index)); 2068 index++; 2069 } 2070 2071 if (index > chunkstart) { 2072 int n_valid = index - chunkstart; 2073 2074 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2075 2076 if (has_timeout && 2077 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2078 break; 2079 } 2080 } 2081 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2082 2083 if (index >= htabslots) { 2084 assert(index == htabslots); 2085 index = 0; 2086 spapr->htab_first_pass = false; 2087 } 2088 spapr->htab_save_index = index; 2089 } 2090 2091 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2092 int64_t max_ns) 2093 { 2094 bool final = max_ns < 0; 2095 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2096 int examined = 0, sent = 0; 2097 int index = spapr->htab_save_index; 2098 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2099 2100 assert(!spapr->htab_first_pass); 2101 2102 do { 2103 int chunkstart, invalidstart; 2104 2105 /* Consume non-dirty HPTEs */ 2106 while ((index < htabslots) 2107 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2108 index++; 2109 examined++; 2110 } 2111 2112 chunkstart = index; 2113 /* Consume valid dirty HPTEs */ 2114 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2115 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2116 && HPTE_VALID(HPTE(spapr->htab, index))) { 2117 CLEAN_HPTE(HPTE(spapr->htab, index)); 2118 index++; 2119 examined++; 2120 } 2121 2122 invalidstart = index; 2123 /* Consume invalid dirty HPTEs */ 2124 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2125 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2126 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2127 CLEAN_HPTE(HPTE(spapr->htab, index)); 2128 index++; 2129 examined++; 2130 } 2131 2132 if (index > chunkstart) { 2133 int n_valid = invalidstart - chunkstart; 2134 int n_invalid = index - invalidstart; 2135 2136 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2137 sent += index - chunkstart; 2138 2139 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2140 break; 2141 } 2142 } 2143 2144 if (examined >= htabslots) { 2145 break; 2146 } 2147 2148 if (index >= htabslots) { 2149 assert(index == htabslots); 2150 index = 0; 2151 } 2152 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2153 2154 if (index >= htabslots) { 2155 assert(index == htabslots); 2156 index = 0; 2157 } 2158 2159 spapr->htab_save_index = index; 2160 2161 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2162 } 2163 2164 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2165 #define MAX_KVM_BUF_SIZE 2048 2166 2167 static int htab_save_iterate(QEMUFile *f, void *opaque) 2168 { 2169 SpaprMachineState *spapr = opaque; 2170 int fd; 2171 int rc = 0; 2172 2173 /* Iteration header */ 2174 if (!spapr->htab_shift) { 2175 qemu_put_be32(f, -1); 2176 return 1; 2177 } else { 2178 qemu_put_be32(f, 0); 2179 } 2180 2181 if (!spapr->htab) { 2182 assert(kvm_enabled()); 2183 2184 fd = get_htab_fd(spapr); 2185 if (fd < 0) { 2186 return fd; 2187 } 2188 2189 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2190 if (rc < 0) { 2191 return rc; 2192 } 2193 } else if (spapr->htab_first_pass) { 2194 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2195 } else { 2196 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2197 } 2198 2199 htab_save_end_marker(f); 2200 2201 return rc; 2202 } 2203 2204 static int htab_save_complete(QEMUFile *f, void *opaque) 2205 { 2206 SpaprMachineState *spapr = opaque; 2207 int fd; 2208 2209 /* Iteration header */ 2210 if (!spapr->htab_shift) { 2211 qemu_put_be32(f, -1); 2212 return 0; 2213 } else { 2214 qemu_put_be32(f, 0); 2215 } 2216 2217 if (!spapr->htab) { 2218 int rc; 2219 2220 assert(kvm_enabled()); 2221 2222 fd = get_htab_fd(spapr); 2223 if (fd < 0) { 2224 return fd; 2225 } 2226 2227 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2228 if (rc < 0) { 2229 return rc; 2230 } 2231 } else { 2232 if (spapr->htab_first_pass) { 2233 htab_save_first_pass(f, spapr, -1); 2234 } 2235 htab_save_later_pass(f, spapr, -1); 2236 } 2237 2238 /* End marker */ 2239 htab_save_end_marker(f); 2240 2241 return 0; 2242 } 2243 2244 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2245 { 2246 SpaprMachineState *spapr = opaque; 2247 uint32_t section_hdr; 2248 int fd = -1; 2249 Error *local_err = NULL; 2250 2251 if (version_id < 1 || version_id > 1) { 2252 error_report("htab_load() bad version"); 2253 return -EINVAL; 2254 } 2255 2256 section_hdr = qemu_get_be32(f); 2257 2258 if (section_hdr == -1) { 2259 spapr_free_hpt(spapr); 2260 return 0; 2261 } 2262 2263 if (section_hdr) { 2264 /* First section gives the htab size */ 2265 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2266 if (local_err) { 2267 error_report_err(local_err); 2268 return -EINVAL; 2269 } 2270 return 0; 2271 } 2272 2273 if (!spapr->htab) { 2274 assert(kvm_enabled()); 2275 2276 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2277 if (fd < 0) { 2278 error_report_err(local_err); 2279 return fd; 2280 } 2281 } 2282 2283 while (true) { 2284 uint32_t index; 2285 uint16_t n_valid, n_invalid; 2286 2287 index = qemu_get_be32(f); 2288 n_valid = qemu_get_be16(f); 2289 n_invalid = qemu_get_be16(f); 2290 2291 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2292 /* End of Stream */ 2293 break; 2294 } 2295 2296 if ((index + n_valid + n_invalid) > 2297 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2298 /* Bad index in stream */ 2299 error_report( 2300 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2301 index, n_valid, n_invalid, spapr->htab_shift); 2302 return -EINVAL; 2303 } 2304 2305 if (spapr->htab) { 2306 if (n_valid) { 2307 qemu_get_buffer(f, HPTE(spapr->htab, index), 2308 HASH_PTE_SIZE_64 * n_valid); 2309 } 2310 if (n_invalid) { 2311 memset(HPTE(spapr->htab, index + n_valid), 0, 2312 HASH_PTE_SIZE_64 * n_invalid); 2313 } 2314 } else { 2315 int rc; 2316 2317 assert(fd >= 0); 2318 2319 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2320 if (rc < 0) { 2321 return rc; 2322 } 2323 } 2324 } 2325 2326 if (!spapr->htab) { 2327 assert(fd >= 0); 2328 close(fd); 2329 } 2330 2331 return 0; 2332 } 2333 2334 static void htab_save_cleanup(void *opaque) 2335 { 2336 SpaprMachineState *spapr = opaque; 2337 2338 close_htab_fd(spapr); 2339 } 2340 2341 static SaveVMHandlers savevm_htab_handlers = { 2342 .save_setup = htab_save_setup, 2343 .save_live_iterate = htab_save_iterate, 2344 .save_live_complete_precopy = htab_save_complete, 2345 .save_cleanup = htab_save_cleanup, 2346 .load_state = htab_load, 2347 }; 2348 2349 static void spapr_boot_set(void *opaque, const char *boot_device, 2350 Error **errp) 2351 { 2352 MachineState *machine = MACHINE(opaque); 2353 machine->boot_order = g_strdup(boot_device); 2354 } 2355 2356 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2357 { 2358 MachineState *machine = MACHINE(spapr); 2359 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2360 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2361 int i; 2362 2363 for (i = 0; i < nr_lmbs; i++) { 2364 uint64_t addr; 2365 2366 addr = i * lmb_size + machine->device_memory->base; 2367 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2368 addr / lmb_size); 2369 } 2370 } 2371 2372 /* 2373 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2374 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2375 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2376 */ 2377 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2378 { 2379 int i; 2380 2381 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2382 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2383 " is not aligned to %" PRIu64 " MiB", 2384 machine->ram_size, 2385 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2386 return; 2387 } 2388 2389 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2390 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2391 " is not aligned to %" PRIu64 " MiB", 2392 machine->ram_size, 2393 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2394 return; 2395 } 2396 2397 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2398 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2399 error_setg(errp, 2400 "Node %d memory size 0x%" PRIx64 2401 " is not aligned to %" PRIu64 " MiB", 2402 i, machine->numa_state->nodes[i].node_mem, 2403 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2404 return; 2405 } 2406 } 2407 } 2408 2409 /* find cpu slot in machine->possible_cpus by core_id */ 2410 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2411 { 2412 int index = id / ms->smp.threads; 2413 2414 if (index >= ms->possible_cpus->len) { 2415 return NULL; 2416 } 2417 if (idx) { 2418 *idx = index; 2419 } 2420 return &ms->possible_cpus->cpus[index]; 2421 } 2422 2423 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2424 { 2425 MachineState *ms = MACHINE(spapr); 2426 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2427 Error *local_err = NULL; 2428 bool vsmt_user = !!spapr->vsmt; 2429 int kvm_smt = kvmppc_smt_threads(); 2430 int ret; 2431 unsigned int smp_threads = ms->smp.threads; 2432 2433 if (!kvm_enabled() && (smp_threads > 1)) { 2434 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2435 "on a pseries machine"); 2436 goto out; 2437 } 2438 if (!is_power_of_2(smp_threads)) { 2439 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2440 "machine because it must be a power of 2", smp_threads); 2441 goto out; 2442 } 2443 2444 /* Detemine the VSMT mode to use: */ 2445 if (vsmt_user) { 2446 if (spapr->vsmt < smp_threads) { 2447 error_setg(&local_err, "Cannot support VSMT mode %d" 2448 " because it must be >= threads/core (%d)", 2449 spapr->vsmt, smp_threads); 2450 goto out; 2451 } 2452 /* In this case, spapr->vsmt has been set by the command line */ 2453 } else if (!smc->smp_threads_vsmt) { 2454 /* 2455 * Default VSMT value is tricky, because we need it to be as 2456 * consistent as possible (for migration), but this requires 2457 * changing it for at least some existing cases. We pick 8 as 2458 * the value that we'd get with KVM on POWER8, the 2459 * overwhelmingly common case in production systems. 2460 */ 2461 spapr->vsmt = MAX(8, smp_threads); 2462 } else { 2463 spapr->vsmt = smp_threads; 2464 } 2465 2466 /* KVM: If necessary, set the SMT mode: */ 2467 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2468 ret = kvmppc_set_smt_threads(spapr->vsmt); 2469 if (ret) { 2470 /* Looks like KVM isn't able to change VSMT mode */ 2471 error_setg(&local_err, 2472 "Failed to set KVM's VSMT mode to %d (errno %d)", 2473 spapr->vsmt, ret); 2474 /* We can live with that if the default one is big enough 2475 * for the number of threads, and a submultiple of the one 2476 * we want. In this case we'll waste some vcpu ids, but 2477 * behaviour will be correct */ 2478 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2479 warn_report_err(local_err); 2480 local_err = NULL; 2481 goto out; 2482 } else { 2483 if (!vsmt_user) { 2484 error_append_hint(&local_err, 2485 "On PPC, a VM with %d threads/core" 2486 " on a host with %d threads/core" 2487 " requires the use of VSMT mode %d.\n", 2488 smp_threads, kvm_smt, spapr->vsmt); 2489 } 2490 kvmppc_error_append_smt_possible_hint(&local_err); 2491 goto out; 2492 } 2493 } 2494 } 2495 /* else TCG: nothing to do currently */ 2496 out: 2497 error_propagate(errp, local_err); 2498 } 2499 2500 static void spapr_init_cpus(SpaprMachineState *spapr) 2501 { 2502 MachineState *machine = MACHINE(spapr); 2503 MachineClass *mc = MACHINE_GET_CLASS(machine); 2504 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2505 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2506 const CPUArchIdList *possible_cpus; 2507 unsigned int smp_cpus = machine->smp.cpus; 2508 unsigned int smp_threads = machine->smp.threads; 2509 unsigned int max_cpus = machine->smp.max_cpus; 2510 int boot_cores_nr = smp_cpus / smp_threads; 2511 int i; 2512 2513 possible_cpus = mc->possible_cpu_arch_ids(machine); 2514 if (mc->has_hotpluggable_cpus) { 2515 if (smp_cpus % smp_threads) { 2516 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2517 smp_cpus, smp_threads); 2518 exit(1); 2519 } 2520 if (max_cpus % smp_threads) { 2521 error_report("max_cpus (%u) must be multiple of threads (%u)", 2522 max_cpus, smp_threads); 2523 exit(1); 2524 } 2525 } else { 2526 if (max_cpus != smp_cpus) { 2527 error_report("This machine version does not support CPU hotplug"); 2528 exit(1); 2529 } 2530 boot_cores_nr = possible_cpus->len; 2531 } 2532 2533 if (smc->pre_2_10_has_unused_icps) { 2534 int i; 2535 2536 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2537 /* Dummy entries get deregistered when real ICPState objects 2538 * are registered during CPU core hotplug. 2539 */ 2540 pre_2_10_vmstate_register_dummy_icp(i); 2541 } 2542 } 2543 2544 for (i = 0; i < possible_cpus->len; i++) { 2545 int core_id = i * smp_threads; 2546 2547 if (mc->has_hotpluggable_cpus) { 2548 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2549 spapr_vcpu_id(spapr, core_id)); 2550 } 2551 2552 if (i < boot_cores_nr) { 2553 Object *core = object_new(type); 2554 int nr_threads = smp_threads; 2555 2556 /* Handle the partially filled core for older machine types */ 2557 if ((i + 1) * smp_threads >= smp_cpus) { 2558 nr_threads = smp_cpus - i * smp_threads; 2559 } 2560 2561 object_property_set_int(core, nr_threads, "nr-threads", 2562 &error_fatal); 2563 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2564 &error_fatal); 2565 object_property_set_bool(core, true, "realized", &error_fatal); 2566 2567 object_unref(core); 2568 } 2569 } 2570 } 2571 2572 static PCIHostState *spapr_create_default_phb(void) 2573 { 2574 DeviceState *dev; 2575 2576 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 2577 qdev_prop_set_uint32(dev, "index", 0); 2578 qdev_init_nofail(dev); 2579 2580 return PCI_HOST_BRIDGE(dev); 2581 } 2582 2583 /* pSeries LPAR / sPAPR hardware init */ 2584 static void spapr_machine_init(MachineState *machine) 2585 { 2586 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2587 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2588 const char *kernel_filename = machine->kernel_filename; 2589 const char *initrd_filename = machine->initrd_filename; 2590 PCIHostState *phb; 2591 int i; 2592 MemoryRegion *sysmem = get_system_memory(); 2593 MemoryRegion *ram = g_new(MemoryRegion, 1); 2594 hwaddr node0_size = spapr_node0_size(machine); 2595 long load_limit, fw_size; 2596 char *filename; 2597 Error *resize_hpt_err = NULL; 2598 2599 msi_nonbroken = true; 2600 2601 QLIST_INIT(&spapr->phbs); 2602 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2603 2604 /* Determine capabilities to run with */ 2605 spapr_caps_init(spapr); 2606 2607 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2608 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2609 /* 2610 * If the user explicitly requested a mode we should either 2611 * supply it, or fail completely (which we do below). But if 2612 * it's not set explicitly, we reset our mode to something 2613 * that works 2614 */ 2615 if (resize_hpt_err) { 2616 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2617 error_free(resize_hpt_err); 2618 resize_hpt_err = NULL; 2619 } else { 2620 spapr->resize_hpt = smc->resize_hpt_default; 2621 } 2622 } 2623 2624 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2625 2626 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2627 /* 2628 * User requested HPT resize, but this host can't supply it. Bail out 2629 */ 2630 error_report_err(resize_hpt_err); 2631 exit(1); 2632 } 2633 2634 spapr->rma_size = node0_size; 2635 2636 /* With KVM, we don't actually know whether KVM supports an 2637 * unbounded RMA (PR KVM) or is limited by the hash table size 2638 * (HV KVM using VRMA), so we always assume the latter 2639 * 2640 * In that case, we also limit the initial allocations for RTAS 2641 * etc... to 256M since we have no way to know what the VRMA size 2642 * is going to be as it depends on the size of the hash table 2643 * which isn't determined yet. 2644 */ 2645 if (kvm_enabled()) { 2646 spapr->vrma_adjust = 1; 2647 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2648 } 2649 2650 /* Actually we don't support unbounded RMA anymore since we added 2651 * proper emulation of HV mode. The max we can get is 16G which 2652 * also happens to be what we configure for PAPR mode so make sure 2653 * we don't do anything bigger than that 2654 */ 2655 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2656 2657 if (spapr->rma_size > node0_size) { 2658 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2659 spapr->rma_size); 2660 exit(1); 2661 } 2662 2663 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2664 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2665 2666 /* 2667 * VSMT must be set in order to be able to compute VCPU ids, ie to 2668 * call spapr_max_server_number() or spapr_vcpu_id(). 2669 */ 2670 spapr_set_vsmt_mode(spapr, &error_fatal); 2671 2672 /* Set up Interrupt Controller before we create the VCPUs */ 2673 spapr_irq_init(spapr, &error_fatal); 2674 2675 /* Set up containers for ibm,client-architecture-support negotiated options 2676 */ 2677 spapr->ov5 = spapr_ovec_new(); 2678 spapr->ov5_cas = spapr_ovec_new(); 2679 2680 if (smc->dr_lmb_enabled) { 2681 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2682 spapr_validate_node_memory(machine, &error_fatal); 2683 } 2684 2685 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2686 2687 /* advertise support for dedicated HP event source to guests */ 2688 if (spapr->use_hotplug_event_source) { 2689 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2690 } 2691 2692 /* advertise support for HPT resizing */ 2693 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2694 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2695 } 2696 2697 /* advertise support for ibm,dyamic-memory-v2 */ 2698 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2699 2700 /* advertise XIVE on POWER9 machines */ 2701 if (spapr->irq->xive) { 2702 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2703 } 2704 2705 /* init CPUs */ 2706 spapr_init_cpus(spapr); 2707 2708 /* 2709 * check we don't have a memory-less/cpu-less NUMA node 2710 * Firmware relies on the existing memory/cpu topology to provide the 2711 * NUMA topology to the kernel. 2712 * And the linux kernel needs to know the NUMA topology at start 2713 * to be able to hotplug CPUs later. 2714 */ 2715 if (machine->numa_state->num_nodes) { 2716 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2717 /* check for memory-less node */ 2718 if (machine->numa_state->nodes[i].node_mem == 0) { 2719 CPUState *cs; 2720 int found = 0; 2721 /* check for cpu-less node */ 2722 CPU_FOREACH(cs) { 2723 PowerPCCPU *cpu = POWERPC_CPU(cs); 2724 if (cpu->node_id == i) { 2725 found = 1; 2726 break; 2727 } 2728 } 2729 /* memory-less and cpu-less node */ 2730 if (!found) { 2731 error_report( 2732 "Memory-less/cpu-less nodes are not supported (node %d)", 2733 i); 2734 exit(1); 2735 } 2736 } 2737 } 2738 2739 } 2740 2741 /* 2742 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2743 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2744 * called from vPHB reset handler so we initialize the counter here. 2745 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2746 * must be equally distant from any other node. 2747 * The final value of spapr->gpu_numa_id is going to be written to 2748 * max-associativity-domains in spapr_build_fdt(). 2749 */ 2750 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2751 2752 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2753 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2754 spapr->max_compat_pvr)) { 2755 /* KVM and TCG always allow GTSE with radix... */ 2756 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2757 } 2758 /* ... but not with hash (currently). */ 2759 2760 if (kvm_enabled()) { 2761 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2762 kvmppc_enable_logical_ci_hcalls(); 2763 kvmppc_enable_set_mode_hcall(); 2764 2765 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2766 kvmppc_enable_clear_ref_mod_hcalls(); 2767 2768 /* Enable H_PAGE_INIT */ 2769 kvmppc_enable_h_page_init(); 2770 } 2771 2772 /* allocate RAM */ 2773 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2774 machine->ram_size); 2775 memory_region_add_subregion(sysmem, 0, ram); 2776 2777 /* always allocate the device memory information */ 2778 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2779 2780 /* initialize hotplug memory address space */ 2781 if (machine->ram_size < machine->maxram_size) { 2782 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2783 /* 2784 * Limit the number of hotpluggable memory slots to half the number 2785 * slots that KVM supports, leaving the other half for PCI and other 2786 * devices. However ensure that number of slots doesn't drop below 32. 2787 */ 2788 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2789 SPAPR_MAX_RAM_SLOTS; 2790 2791 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2792 max_memslots = SPAPR_MAX_RAM_SLOTS; 2793 } 2794 if (machine->ram_slots > max_memslots) { 2795 error_report("Specified number of memory slots %" 2796 PRIu64" exceeds max supported %d", 2797 machine->ram_slots, max_memslots); 2798 exit(1); 2799 } 2800 2801 machine->device_memory->base = ROUND_UP(machine->ram_size, 2802 SPAPR_DEVICE_MEM_ALIGN); 2803 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2804 "device-memory", device_mem_size); 2805 memory_region_add_subregion(sysmem, machine->device_memory->base, 2806 &machine->device_memory->mr); 2807 } 2808 2809 if (smc->dr_lmb_enabled) { 2810 spapr_create_lmb_dr_connectors(spapr); 2811 } 2812 2813 /* Set up RTAS event infrastructure */ 2814 spapr_events_init(spapr); 2815 2816 /* Set up the RTC RTAS interfaces */ 2817 spapr_rtc_create(spapr); 2818 2819 /* Set up VIO bus */ 2820 spapr->vio_bus = spapr_vio_bus_init(); 2821 2822 for (i = 0; i < serial_max_hds(); i++) { 2823 if (serial_hd(i)) { 2824 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2825 } 2826 } 2827 2828 /* We always have at least the nvram device on VIO */ 2829 spapr_create_nvram(spapr); 2830 2831 /* 2832 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2833 * connectors (described in root DT node's "ibm,drc-types" property) 2834 * are pre-initialized here. additional child connectors (such as 2835 * connectors for a PHBs PCI slots) are added as needed during their 2836 * parent's realization. 2837 */ 2838 if (smc->dr_phb_enabled) { 2839 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2840 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2841 } 2842 } 2843 2844 /* Set up PCI */ 2845 spapr_pci_rtas_init(); 2846 2847 phb = spapr_create_default_phb(); 2848 2849 for (i = 0; i < nb_nics; i++) { 2850 NICInfo *nd = &nd_table[i]; 2851 2852 if (!nd->model) { 2853 nd->model = g_strdup("spapr-vlan"); 2854 } 2855 2856 if (g_str_equal(nd->model, "spapr-vlan") || 2857 g_str_equal(nd->model, "ibmveth")) { 2858 spapr_vlan_create(spapr->vio_bus, nd); 2859 } else { 2860 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2861 } 2862 } 2863 2864 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2865 spapr_vscsi_create(spapr->vio_bus); 2866 } 2867 2868 /* Graphics */ 2869 if (spapr_vga_init(phb->bus, &error_fatal)) { 2870 spapr->has_graphics = true; 2871 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2872 } 2873 2874 if (machine->usb) { 2875 if (smc->use_ohci_by_default) { 2876 pci_create_simple(phb->bus, -1, "pci-ohci"); 2877 } else { 2878 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2879 } 2880 2881 if (spapr->has_graphics) { 2882 USBBus *usb_bus = usb_bus_find(-1); 2883 2884 usb_create_simple(usb_bus, "usb-kbd"); 2885 usb_create_simple(usb_bus, "usb-mouse"); 2886 } 2887 } 2888 2889 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) { 2890 error_report( 2891 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2892 MIN_RMA_SLOF); 2893 exit(1); 2894 } 2895 2896 if (kernel_filename) { 2897 uint64_t lowaddr = 0; 2898 2899 spapr->kernel_size = load_elf(kernel_filename, NULL, 2900 translate_kernel_address, NULL, 2901 NULL, &lowaddr, NULL, 1, 2902 PPC_ELF_MACHINE, 0, 0); 2903 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2904 spapr->kernel_size = load_elf(kernel_filename, NULL, 2905 translate_kernel_address, NULL, NULL, 2906 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2907 0, 0); 2908 spapr->kernel_le = spapr->kernel_size > 0; 2909 } 2910 if (spapr->kernel_size < 0) { 2911 error_report("error loading %s: %s", kernel_filename, 2912 load_elf_strerror(spapr->kernel_size)); 2913 exit(1); 2914 } 2915 2916 /* load initrd */ 2917 if (initrd_filename) { 2918 /* Try to locate the initrd in the gap between the kernel 2919 * and the firmware. Add a bit of space just in case 2920 */ 2921 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2922 + 0x1ffff) & ~0xffff; 2923 spapr->initrd_size = load_image_targphys(initrd_filename, 2924 spapr->initrd_base, 2925 load_limit 2926 - spapr->initrd_base); 2927 if (spapr->initrd_size < 0) { 2928 error_report("could not load initial ram disk '%s'", 2929 initrd_filename); 2930 exit(1); 2931 } 2932 } 2933 } 2934 2935 if (bios_name == NULL) { 2936 bios_name = FW_FILE_NAME; 2937 } 2938 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2939 if (!filename) { 2940 error_report("Could not find LPAR firmware '%s'", bios_name); 2941 exit(1); 2942 } 2943 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2944 if (fw_size <= 0) { 2945 error_report("Could not load LPAR firmware '%s'", filename); 2946 exit(1); 2947 } 2948 g_free(filename); 2949 2950 /* FIXME: Should register things through the MachineState's qdev 2951 * interface, this is a legacy from the sPAPREnvironment structure 2952 * which predated MachineState but had a similar function */ 2953 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2954 register_savevm_live("spapr/htab", -1, 1, 2955 &savevm_htab_handlers, spapr); 2956 2957 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine), 2958 &error_fatal); 2959 2960 qemu_register_boot_set(spapr_boot_set, spapr); 2961 2962 /* 2963 * Nothing needs to be done to resume a suspended guest because 2964 * suspending does not change the machine state, so no need for 2965 * a ->wakeup method. 2966 */ 2967 qemu_register_wakeup_support(); 2968 2969 if (kvm_enabled()) { 2970 /* to stop and start vmclock */ 2971 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2972 &spapr->tb); 2973 2974 kvmppc_spapr_enable_inkernel_multitce(); 2975 } 2976 } 2977 2978 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 2979 { 2980 if (!vm_type) { 2981 return 0; 2982 } 2983 2984 if (!strcmp(vm_type, "HV")) { 2985 return 1; 2986 } 2987 2988 if (!strcmp(vm_type, "PR")) { 2989 return 2; 2990 } 2991 2992 error_report("Unknown kvm-type specified '%s'", vm_type); 2993 exit(1); 2994 } 2995 2996 /* 2997 * Implementation of an interface to adjust firmware path 2998 * for the bootindex property handling. 2999 */ 3000 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3001 DeviceState *dev) 3002 { 3003 #define CAST(type, obj, name) \ 3004 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3005 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3006 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3007 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3008 3009 if (d) { 3010 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3011 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3012 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3013 3014 if (spapr) { 3015 /* 3016 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3017 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3018 * 0x8000 | (target << 8) | (bus << 5) | lun 3019 * (see the "Logical unit addressing format" table in SAM5) 3020 */ 3021 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3022 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3023 (uint64_t)id << 48); 3024 } else if (virtio) { 3025 /* 3026 * We use SRP luns of the form 01000000 | (target << 8) | lun 3027 * in the top 32 bits of the 64-bit LUN 3028 * Note: the quote above is from SLOF and it is wrong, 3029 * the actual binding is: 3030 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3031 */ 3032 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3033 if (d->lun >= 256) { 3034 /* Use the LUN "flat space addressing method" */ 3035 id |= 0x4000; 3036 } 3037 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3038 (uint64_t)id << 32); 3039 } else if (usb) { 3040 /* 3041 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3042 * in the top 32 bits of the 64-bit LUN 3043 */ 3044 unsigned usb_port = atoi(usb->port->path); 3045 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3046 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3047 (uint64_t)id << 32); 3048 } 3049 } 3050 3051 /* 3052 * SLOF probes the USB devices, and if it recognizes that the device is a 3053 * storage device, it changes its name to "storage" instead of "usb-host", 3054 * and additionally adds a child node for the SCSI LUN, so the correct 3055 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3056 */ 3057 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3058 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3059 if (usb_host_dev_is_scsi_storage(usbdev)) { 3060 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3061 } 3062 } 3063 3064 if (phb) { 3065 /* Replace "pci" with "pci@800000020000000" */ 3066 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3067 } 3068 3069 if (vsc) { 3070 /* Same logic as virtio above */ 3071 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3072 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3073 } 3074 3075 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3076 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3077 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3078 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3079 } 3080 3081 return NULL; 3082 } 3083 3084 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3085 { 3086 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3087 3088 return g_strdup(spapr->kvm_type); 3089 } 3090 3091 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3092 { 3093 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3094 3095 g_free(spapr->kvm_type); 3096 spapr->kvm_type = g_strdup(value); 3097 } 3098 3099 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3100 { 3101 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3102 3103 return spapr->use_hotplug_event_source; 3104 } 3105 3106 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3107 Error **errp) 3108 { 3109 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3110 3111 spapr->use_hotplug_event_source = value; 3112 } 3113 3114 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3115 { 3116 return true; 3117 } 3118 3119 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3120 { 3121 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3122 3123 switch (spapr->resize_hpt) { 3124 case SPAPR_RESIZE_HPT_DEFAULT: 3125 return g_strdup("default"); 3126 case SPAPR_RESIZE_HPT_DISABLED: 3127 return g_strdup("disabled"); 3128 case SPAPR_RESIZE_HPT_ENABLED: 3129 return g_strdup("enabled"); 3130 case SPAPR_RESIZE_HPT_REQUIRED: 3131 return g_strdup("required"); 3132 } 3133 g_assert_not_reached(); 3134 } 3135 3136 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3137 { 3138 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3139 3140 if (strcmp(value, "default") == 0) { 3141 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3142 } else if (strcmp(value, "disabled") == 0) { 3143 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3144 } else if (strcmp(value, "enabled") == 0) { 3145 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3146 } else if (strcmp(value, "required") == 0) { 3147 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3148 } else { 3149 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3150 } 3151 } 3152 3153 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3154 void *opaque, Error **errp) 3155 { 3156 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3157 } 3158 3159 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3160 void *opaque, Error **errp) 3161 { 3162 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3163 } 3164 3165 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3166 { 3167 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3168 3169 if (spapr->irq == &spapr_irq_xics_legacy) { 3170 return g_strdup("legacy"); 3171 } else if (spapr->irq == &spapr_irq_xics) { 3172 return g_strdup("xics"); 3173 } else if (spapr->irq == &spapr_irq_xive) { 3174 return g_strdup("xive"); 3175 } else if (spapr->irq == &spapr_irq_dual) { 3176 return g_strdup("dual"); 3177 } 3178 g_assert_not_reached(); 3179 } 3180 3181 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3182 { 3183 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3184 3185 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3186 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3187 return; 3188 } 3189 3190 /* The legacy IRQ backend can not be set */ 3191 if (strcmp(value, "xics") == 0) { 3192 spapr->irq = &spapr_irq_xics; 3193 } else if (strcmp(value, "xive") == 0) { 3194 spapr->irq = &spapr_irq_xive; 3195 } else if (strcmp(value, "dual") == 0) { 3196 spapr->irq = &spapr_irq_dual; 3197 } else { 3198 error_setg(errp, "Bad value for \"ic-mode\" property"); 3199 } 3200 } 3201 3202 static char *spapr_get_host_model(Object *obj, Error **errp) 3203 { 3204 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3205 3206 return g_strdup(spapr->host_model); 3207 } 3208 3209 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3210 { 3211 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3212 3213 g_free(spapr->host_model); 3214 spapr->host_model = g_strdup(value); 3215 } 3216 3217 static char *spapr_get_host_serial(Object *obj, Error **errp) 3218 { 3219 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3220 3221 return g_strdup(spapr->host_serial); 3222 } 3223 3224 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3225 { 3226 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3227 3228 g_free(spapr->host_serial); 3229 spapr->host_serial = g_strdup(value); 3230 } 3231 3232 static void spapr_instance_init(Object *obj) 3233 { 3234 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3235 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3236 3237 spapr->htab_fd = -1; 3238 spapr->use_hotplug_event_source = true; 3239 object_property_add_str(obj, "kvm-type", 3240 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3241 object_property_set_description(obj, "kvm-type", 3242 "Specifies the KVM virtualization mode (HV, PR)", 3243 NULL); 3244 object_property_add_bool(obj, "modern-hotplug-events", 3245 spapr_get_modern_hotplug_events, 3246 spapr_set_modern_hotplug_events, 3247 NULL); 3248 object_property_set_description(obj, "modern-hotplug-events", 3249 "Use dedicated hotplug event mechanism in" 3250 " place of standard EPOW events when possible" 3251 " (required for memory hot-unplug support)", 3252 NULL); 3253 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3254 "Maximum permitted CPU compatibility mode", 3255 &error_fatal); 3256 3257 object_property_add_str(obj, "resize-hpt", 3258 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3259 object_property_set_description(obj, "resize-hpt", 3260 "Resizing of the Hash Page Table (enabled, disabled, required)", 3261 NULL); 3262 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3263 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3264 object_property_set_description(obj, "vsmt", 3265 "Virtual SMT: KVM behaves as if this were" 3266 " the host's SMT mode", &error_abort); 3267 object_property_add_bool(obj, "vfio-no-msix-emulation", 3268 spapr_get_msix_emulation, NULL, NULL); 3269 3270 /* The machine class defines the default interrupt controller mode */ 3271 spapr->irq = smc->irq; 3272 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3273 spapr_set_ic_mode, NULL); 3274 object_property_set_description(obj, "ic-mode", 3275 "Specifies the interrupt controller mode (xics, xive, dual)", 3276 NULL); 3277 3278 object_property_add_str(obj, "host-model", 3279 spapr_get_host_model, spapr_set_host_model, 3280 &error_abort); 3281 object_property_set_description(obj, "host-model", 3282 "Host model to advertise in guest device tree", &error_abort); 3283 object_property_add_str(obj, "host-serial", 3284 spapr_get_host_serial, spapr_set_host_serial, 3285 &error_abort); 3286 object_property_set_description(obj, "host-serial", 3287 "Host serial number to advertise in guest device tree", &error_abort); 3288 } 3289 3290 static void spapr_machine_finalizefn(Object *obj) 3291 { 3292 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3293 3294 g_free(spapr->kvm_type); 3295 } 3296 3297 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3298 { 3299 cpu_synchronize_state(cs); 3300 ppc_cpu_do_system_reset(cs); 3301 } 3302 3303 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3304 { 3305 CPUState *cs; 3306 3307 CPU_FOREACH(cs) { 3308 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3309 } 3310 } 3311 3312 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3313 void *fdt, int *fdt_start_offset, Error **errp) 3314 { 3315 uint64_t addr; 3316 uint32_t node; 3317 3318 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3319 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3320 &error_abort); 3321 *fdt_start_offset = spapr_populate_memory_node(fdt, node, addr, 3322 SPAPR_MEMORY_BLOCK_SIZE); 3323 return 0; 3324 } 3325 3326 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3327 bool dedicated_hp_event_source, Error **errp) 3328 { 3329 SpaprDrc *drc; 3330 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3331 int i; 3332 uint64_t addr = addr_start; 3333 bool hotplugged = spapr_drc_hotplugged(dev); 3334 Error *local_err = NULL; 3335 3336 for (i = 0; i < nr_lmbs; i++) { 3337 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3338 addr / SPAPR_MEMORY_BLOCK_SIZE); 3339 g_assert(drc); 3340 3341 spapr_drc_attach(drc, dev, &local_err); 3342 if (local_err) { 3343 while (addr > addr_start) { 3344 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3345 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3346 addr / SPAPR_MEMORY_BLOCK_SIZE); 3347 spapr_drc_detach(drc); 3348 } 3349 error_propagate(errp, local_err); 3350 return; 3351 } 3352 if (!hotplugged) { 3353 spapr_drc_reset(drc); 3354 } 3355 addr += SPAPR_MEMORY_BLOCK_SIZE; 3356 } 3357 /* send hotplug notification to the 3358 * guest only in case of hotplugged memory 3359 */ 3360 if (hotplugged) { 3361 if (dedicated_hp_event_source) { 3362 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3363 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3364 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3365 nr_lmbs, 3366 spapr_drc_index(drc)); 3367 } else { 3368 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3369 nr_lmbs); 3370 } 3371 } 3372 } 3373 3374 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3375 Error **errp) 3376 { 3377 Error *local_err = NULL; 3378 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3379 PCDIMMDevice *dimm = PC_DIMM(dev); 3380 uint64_t size, addr; 3381 3382 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3383 3384 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3385 if (local_err) { 3386 goto out; 3387 } 3388 3389 addr = object_property_get_uint(OBJECT(dimm), 3390 PC_DIMM_ADDR_PROP, &local_err); 3391 if (local_err) { 3392 goto out_unplug; 3393 } 3394 3395 spapr_add_lmbs(dev, addr, size, spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3396 &local_err); 3397 if (local_err) { 3398 goto out_unplug; 3399 } 3400 3401 return; 3402 3403 out_unplug: 3404 pc_dimm_unplug(dimm, MACHINE(ms)); 3405 out: 3406 error_propagate(errp, local_err); 3407 } 3408 3409 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3410 Error **errp) 3411 { 3412 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3413 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3414 PCDIMMDevice *dimm = PC_DIMM(dev); 3415 Error *local_err = NULL; 3416 uint64_t size; 3417 Object *memdev; 3418 hwaddr pagesize; 3419 3420 if (!smc->dr_lmb_enabled) { 3421 error_setg(errp, "Memory hotplug not supported for this machine"); 3422 return; 3423 } 3424 3425 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3426 if (local_err) { 3427 error_propagate(errp, local_err); 3428 return; 3429 } 3430 3431 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3432 error_setg(errp, "Hotplugged memory size must be a multiple of " 3433 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3434 return; 3435 } 3436 3437 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3438 &error_abort); 3439 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3440 spapr_check_pagesize(spapr, pagesize, &local_err); 3441 if (local_err) { 3442 error_propagate(errp, local_err); 3443 return; 3444 } 3445 3446 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3447 } 3448 3449 struct SpaprDimmState { 3450 PCDIMMDevice *dimm; 3451 uint32_t nr_lmbs; 3452 QTAILQ_ENTRY(SpaprDimmState) next; 3453 }; 3454 3455 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3456 PCDIMMDevice *dimm) 3457 { 3458 SpaprDimmState *dimm_state = NULL; 3459 3460 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3461 if (dimm_state->dimm == dimm) { 3462 break; 3463 } 3464 } 3465 return dimm_state; 3466 } 3467 3468 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3469 uint32_t nr_lmbs, 3470 PCDIMMDevice *dimm) 3471 { 3472 SpaprDimmState *ds = NULL; 3473 3474 /* 3475 * If this request is for a DIMM whose removal had failed earlier 3476 * (due to guest's refusal to remove the LMBs), we would have this 3477 * dimm already in the pending_dimm_unplugs list. In that 3478 * case don't add again. 3479 */ 3480 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3481 if (!ds) { 3482 ds = g_malloc0(sizeof(SpaprDimmState)); 3483 ds->nr_lmbs = nr_lmbs; 3484 ds->dimm = dimm; 3485 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3486 } 3487 return ds; 3488 } 3489 3490 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3491 SpaprDimmState *dimm_state) 3492 { 3493 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3494 g_free(dimm_state); 3495 } 3496 3497 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3498 PCDIMMDevice *dimm) 3499 { 3500 SpaprDrc *drc; 3501 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3502 &error_abort); 3503 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3504 uint32_t avail_lmbs = 0; 3505 uint64_t addr_start, addr; 3506 int i; 3507 3508 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3509 &error_abort); 3510 3511 addr = addr_start; 3512 for (i = 0; i < nr_lmbs; i++) { 3513 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3514 addr / SPAPR_MEMORY_BLOCK_SIZE); 3515 g_assert(drc); 3516 if (drc->dev) { 3517 avail_lmbs++; 3518 } 3519 addr += SPAPR_MEMORY_BLOCK_SIZE; 3520 } 3521 3522 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3523 } 3524 3525 /* Callback to be called during DRC release. */ 3526 void spapr_lmb_release(DeviceState *dev) 3527 { 3528 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3529 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3530 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3531 3532 /* This information will get lost if a migration occurs 3533 * during the unplug process. In this case recover it. */ 3534 if (ds == NULL) { 3535 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3536 g_assert(ds); 3537 /* The DRC being examined by the caller at least must be counted */ 3538 g_assert(ds->nr_lmbs); 3539 } 3540 3541 if (--ds->nr_lmbs) { 3542 return; 3543 } 3544 3545 /* 3546 * Now that all the LMBs have been removed by the guest, call the 3547 * unplug handler chain. This can never fail. 3548 */ 3549 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3550 object_unparent(OBJECT(dev)); 3551 } 3552 3553 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3554 { 3555 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3556 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3557 3558 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3559 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3560 spapr_pending_dimm_unplugs_remove(spapr, ds); 3561 } 3562 3563 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3564 DeviceState *dev, Error **errp) 3565 { 3566 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3567 Error *local_err = NULL; 3568 PCDIMMDevice *dimm = PC_DIMM(dev); 3569 uint32_t nr_lmbs; 3570 uint64_t size, addr_start, addr; 3571 int i; 3572 SpaprDrc *drc; 3573 3574 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3575 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3576 3577 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3578 &local_err); 3579 if (local_err) { 3580 goto out; 3581 } 3582 3583 /* 3584 * An existing pending dimm state for this DIMM means that there is an 3585 * unplug operation in progress, waiting for the spapr_lmb_release 3586 * callback to complete the job (BQL can't cover that far). In this case, 3587 * bail out to avoid detaching DRCs that were already released. 3588 */ 3589 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3590 error_setg(&local_err, 3591 "Memory unplug already in progress for device %s", 3592 dev->id); 3593 goto out; 3594 } 3595 3596 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3597 3598 addr = addr_start; 3599 for (i = 0; i < nr_lmbs; i++) { 3600 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3601 addr / SPAPR_MEMORY_BLOCK_SIZE); 3602 g_assert(drc); 3603 3604 spapr_drc_detach(drc); 3605 addr += SPAPR_MEMORY_BLOCK_SIZE; 3606 } 3607 3608 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3609 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3610 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3611 nr_lmbs, spapr_drc_index(drc)); 3612 out: 3613 error_propagate(errp, local_err); 3614 } 3615 3616 /* Callback to be called during DRC release. */ 3617 void spapr_core_release(DeviceState *dev) 3618 { 3619 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3620 3621 /* Call the unplug handler chain. This can never fail. */ 3622 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3623 object_unparent(OBJECT(dev)); 3624 } 3625 3626 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3627 { 3628 MachineState *ms = MACHINE(hotplug_dev); 3629 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3630 CPUCore *cc = CPU_CORE(dev); 3631 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3632 3633 if (smc->pre_2_10_has_unused_icps) { 3634 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3635 int i; 3636 3637 for (i = 0; i < cc->nr_threads; i++) { 3638 CPUState *cs = CPU(sc->threads[i]); 3639 3640 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3641 } 3642 } 3643 3644 assert(core_slot); 3645 core_slot->cpu = NULL; 3646 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3647 } 3648 3649 static 3650 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3651 Error **errp) 3652 { 3653 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3654 int index; 3655 SpaprDrc *drc; 3656 CPUCore *cc = CPU_CORE(dev); 3657 3658 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3659 error_setg(errp, "Unable to find CPU core with core-id: %d", 3660 cc->core_id); 3661 return; 3662 } 3663 if (index == 0) { 3664 error_setg(errp, "Boot CPU core may not be unplugged"); 3665 return; 3666 } 3667 3668 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3669 spapr_vcpu_id(spapr, cc->core_id)); 3670 g_assert(drc); 3671 3672 if (!spapr_drc_unplug_requested(drc)) { 3673 spapr_drc_detach(drc); 3674 spapr_hotplug_req_remove_by_index(drc); 3675 } 3676 } 3677 3678 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3679 void *fdt, int *fdt_start_offset, Error **errp) 3680 { 3681 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3682 CPUState *cs = CPU(core->threads[0]); 3683 PowerPCCPU *cpu = POWERPC_CPU(cs); 3684 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3685 int id = spapr_get_vcpu_id(cpu); 3686 char *nodename; 3687 int offset; 3688 3689 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3690 offset = fdt_add_subnode(fdt, 0, nodename); 3691 g_free(nodename); 3692 3693 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3694 3695 *fdt_start_offset = offset; 3696 return 0; 3697 } 3698 3699 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3700 Error **errp) 3701 { 3702 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3703 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3704 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3705 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3706 CPUCore *cc = CPU_CORE(dev); 3707 CPUState *cs; 3708 SpaprDrc *drc; 3709 Error *local_err = NULL; 3710 CPUArchId *core_slot; 3711 int index; 3712 bool hotplugged = spapr_drc_hotplugged(dev); 3713 int i; 3714 3715 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3716 if (!core_slot) { 3717 error_setg(errp, "Unable to find CPU core with core-id: %d", 3718 cc->core_id); 3719 return; 3720 } 3721 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3722 spapr_vcpu_id(spapr, cc->core_id)); 3723 3724 g_assert(drc || !mc->has_hotpluggable_cpus); 3725 3726 if (drc) { 3727 spapr_drc_attach(drc, dev, &local_err); 3728 if (local_err) { 3729 error_propagate(errp, local_err); 3730 return; 3731 } 3732 3733 if (hotplugged) { 3734 /* 3735 * Send hotplug notification interrupt to the guest only 3736 * in case of hotplugged CPUs. 3737 */ 3738 spapr_hotplug_req_add_by_index(drc); 3739 } else { 3740 spapr_drc_reset(drc); 3741 } 3742 } 3743 3744 core_slot->cpu = OBJECT(dev); 3745 3746 if (smc->pre_2_10_has_unused_icps) { 3747 for (i = 0; i < cc->nr_threads; i++) { 3748 cs = CPU(core->threads[i]); 3749 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3750 } 3751 } 3752 3753 /* 3754 * Set compatibility mode to match the boot CPU, which was either set 3755 * by the machine reset code or by CAS. 3756 */ 3757 if (hotplugged) { 3758 for (i = 0; i < cc->nr_threads; i++) { 3759 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3760 &local_err); 3761 if (local_err) { 3762 error_propagate(errp, local_err); 3763 return; 3764 } 3765 } 3766 } 3767 } 3768 3769 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3770 Error **errp) 3771 { 3772 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3773 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3774 Error *local_err = NULL; 3775 CPUCore *cc = CPU_CORE(dev); 3776 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3777 const char *type = object_get_typename(OBJECT(dev)); 3778 CPUArchId *core_slot; 3779 int index; 3780 unsigned int smp_threads = machine->smp.threads; 3781 3782 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3783 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3784 goto out; 3785 } 3786 3787 if (strcmp(base_core_type, type)) { 3788 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3789 goto out; 3790 } 3791 3792 if (cc->core_id % smp_threads) { 3793 error_setg(&local_err, "invalid core id %d", cc->core_id); 3794 goto out; 3795 } 3796 3797 /* 3798 * In general we should have homogeneous threads-per-core, but old 3799 * (pre hotplug support) machine types allow the last core to have 3800 * reduced threads as a compatibility hack for when we allowed 3801 * total vcpus not a multiple of threads-per-core. 3802 */ 3803 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3804 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3805 cc->nr_threads, smp_threads); 3806 goto out; 3807 } 3808 3809 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3810 if (!core_slot) { 3811 error_setg(&local_err, "core id %d out of range", cc->core_id); 3812 goto out; 3813 } 3814 3815 if (core_slot->cpu) { 3816 error_setg(&local_err, "core %d already populated", cc->core_id); 3817 goto out; 3818 } 3819 3820 numa_cpu_pre_plug(core_slot, dev, &local_err); 3821 3822 out: 3823 error_propagate(errp, local_err); 3824 } 3825 3826 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3827 void *fdt, int *fdt_start_offset, Error **errp) 3828 { 3829 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3830 int intc_phandle; 3831 3832 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3833 if (intc_phandle <= 0) { 3834 return -1; 3835 } 3836 3837 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3838 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3839 return -1; 3840 } 3841 3842 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3843 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3844 3845 return 0; 3846 } 3847 3848 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3849 Error **errp) 3850 { 3851 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3852 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3853 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3854 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3855 3856 if (dev->hotplugged && !smc->dr_phb_enabled) { 3857 error_setg(errp, "PHB hotplug not supported for this machine"); 3858 return; 3859 } 3860 3861 if (sphb->index == (uint32_t)-1) { 3862 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3863 return; 3864 } 3865 3866 /* 3867 * This will check that sphb->index doesn't exceed the maximum number of 3868 * PHBs for the current machine type. 3869 */ 3870 smc->phb_placement(spapr, sphb->index, 3871 &sphb->buid, &sphb->io_win_addr, 3872 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3873 windows_supported, sphb->dma_liobn, 3874 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3875 errp); 3876 } 3877 3878 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3879 Error **errp) 3880 { 3881 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3882 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3883 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3884 SpaprDrc *drc; 3885 bool hotplugged = spapr_drc_hotplugged(dev); 3886 Error *local_err = NULL; 3887 3888 if (!smc->dr_phb_enabled) { 3889 return; 3890 } 3891 3892 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3893 /* hotplug hooks should check it's enabled before getting this far */ 3894 assert(drc); 3895 3896 spapr_drc_attach(drc, DEVICE(dev), &local_err); 3897 if (local_err) { 3898 error_propagate(errp, local_err); 3899 return; 3900 } 3901 3902 if (hotplugged) { 3903 spapr_hotplug_req_add_by_index(drc); 3904 } else { 3905 spapr_drc_reset(drc); 3906 } 3907 } 3908 3909 void spapr_phb_release(DeviceState *dev) 3910 { 3911 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3912 3913 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3914 object_unparent(OBJECT(dev)); 3915 } 3916 3917 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3918 { 3919 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3920 } 3921 3922 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 3923 DeviceState *dev, Error **errp) 3924 { 3925 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3926 SpaprDrc *drc; 3927 3928 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3929 assert(drc); 3930 3931 if (!spapr_drc_unplug_requested(drc)) { 3932 spapr_drc_detach(drc); 3933 spapr_hotplug_req_remove_by_index(drc); 3934 } 3935 } 3936 3937 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3938 Error **errp) 3939 { 3940 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3941 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 3942 3943 if (spapr->tpm_proxy != NULL) { 3944 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 3945 return; 3946 } 3947 3948 spapr->tpm_proxy = tpm_proxy; 3949 } 3950 3951 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3952 { 3953 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3954 3955 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3956 object_unparent(OBJECT(dev)); 3957 spapr->tpm_proxy = NULL; 3958 } 3959 3960 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3961 DeviceState *dev, Error **errp) 3962 { 3963 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3964 spapr_memory_plug(hotplug_dev, dev, errp); 3965 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3966 spapr_core_plug(hotplug_dev, dev, errp); 3967 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 3968 spapr_phb_plug(hotplug_dev, dev, errp); 3969 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 3970 spapr_tpm_proxy_plug(hotplug_dev, dev, errp); 3971 } 3972 } 3973 3974 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 3975 DeviceState *dev, Error **errp) 3976 { 3977 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3978 spapr_memory_unplug(hotplug_dev, dev); 3979 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3980 spapr_core_unplug(hotplug_dev, dev); 3981 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 3982 spapr_phb_unplug(hotplug_dev, dev); 3983 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 3984 spapr_tpm_proxy_unplug(hotplug_dev, dev); 3985 } 3986 } 3987 3988 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3989 DeviceState *dev, Error **errp) 3990 { 3991 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3992 MachineClass *mc = MACHINE_GET_CLASS(sms); 3993 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3994 3995 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3996 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3997 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3998 } else { 3999 /* NOTE: this means there is a window after guest reset, prior to 4000 * CAS negotiation, where unplug requests will fail due to the 4001 * capability not being detected yet. This is a bit different than 4002 * the case with PCI unplug, where the events will be queued and 4003 * eventually handled by the guest after boot 4004 */ 4005 error_setg(errp, "Memory hot unplug not supported for this guest"); 4006 } 4007 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4008 if (!mc->has_hotpluggable_cpus) { 4009 error_setg(errp, "CPU hot unplug not supported on this machine"); 4010 return; 4011 } 4012 spapr_core_unplug_request(hotplug_dev, dev, errp); 4013 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4014 if (!smc->dr_phb_enabled) { 4015 error_setg(errp, "PHB hot unplug not supported on this machine"); 4016 return; 4017 } 4018 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4019 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4020 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4021 } 4022 } 4023 4024 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4025 DeviceState *dev, Error **errp) 4026 { 4027 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4028 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4029 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4030 spapr_core_pre_plug(hotplug_dev, dev, errp); 4031 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4032 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4033 } 4034 } 4035 4036 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4037 DeviceState *dev) 4038 { 4039 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4040 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4041 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4042 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4043 return HOTPLUG_HANDLER(machine); 4044 } 4045 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4046 PCIDevice *pcidev = PCI_DEVICE(dev); 4047 PCIBus *root = pci_device_root_bus(pcidev); 4048 SpaprPhbState *phb = 4049 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4050 TYPE_SPAPR_PCI_HOST_BRIDGE); 4051 4052 if (phb) { 4053 return HOTPLUG_HANDLER(phb); 4054 } 4055 } 4056 return NULL; 4057 } 4058 4059 static CpuInstanceProperties 4060 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4061 { 4062 CPUArchId *core_slot; 4063 MachineClass *mc = MACHINE_GET_CLASS(machine); 4064 4065 /* make sure possible_cpu are intialized */ 4066 mc->possible_cpu_arch_ids(machine); 4067 /* get CPU core slot containing thread that matches cpu_index */ 4068 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4069 assert(core_slot); 4070 return core_slot->props; 4071 } 4072 4073 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4074 { 4075 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4076 } 4077 4078 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4079 { 4080 int i; 4081 unsigned int smp_threads = machine->smp.threads; 4082 unsigned int smp_cpus = machine->smp.cpus; 4083 const char *core_type; 4084 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4085 MachineClass *mc = MACHINE_GET_CLASS(machine); 4086 4087 if (!mc->has_hotpluggable_cpus) { 4088 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4089 } 4090 if (machine->possible_cpus) { 4091 assert(machine->possible_cpus->len == spapr_max_cores); 4092 return machine->possible_cpus; 4093 } 4094 4095 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4096 if (!core_type) { 4097 error_report("Unable to find sPAPR CPU Core definition"); 4098 exit(1); 4099 } 4100 4101 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4102 sizeof(CPUArchId) * spapr_max_cores); 4103 machine->possible_cpus->len = spapr_max_cores; 4104 for (i = 0; i < machine->possible_cpus->len; i++) { 4105 int core_id = i * smp_threads; 4106 4107 machine->possible_cpus->cpus[i].type = core_type; 4108 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4109 machine->possible_cpus->cpus[i].arch_id = core_id; 4110 machine->possible_cpus->cpus[i].props.has_core_id = true; 4111 machine->possible_cpus->cpus[i].props.core_id = core_id; 4112 } 4113 return machine->possible_cpus; 4114 } 4115 4116 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4117 uint64_t *buid, hwaddr *pio, 4118 hwaddr *mmio32, hwaddr *mmio64, 4119 unsigned n_dma, uint32_t *liobns, 4120 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4121 { 4122 /* 4123 * New-style PHB window placement. 4124 * 4125 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4126 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4127 * windows. 4128 * 4129 * Some guest kernels can't work with MMIO windows above 1<<46 4130 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4131 * 4132 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4133 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4134 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4135 * 1TiB 64-bit MMIO windows for each PHB. 4136 */ 4137 const uint64_t base_buid = 0x800000020000000ULL; 4138 int i; 4139 4140 /* Sanity check natural alignments */ 4141 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4142 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4143 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4144 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4145 /* Sanity check bounds */ 4146 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4147 SPAPR_PCI_MEM32_WIN_SIZE); 4148 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4149 SPAPR_PCI_MEM64_WIN_SIZE); 4150 4151 if (index >= SPAPR_MAX_PHBS) { 4152 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4153 SPAPR_MAX_PHBS - 1); 4154 return; 4155 } 4156 4157 *buid = base_buid + index; 4158 for (i = 0; i < n_dma; ++i) { 4159 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4160 } 4161 4162 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4163 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4164 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4165 4166 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4167 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4168 } 4169 4170 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4171 { 4172 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4173 4174 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4175 } 4176 4177 static void spapr_ics_resend(XICSFabric *dev) 4178 { 4179 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4180 4181 ics_resend(spapr->ics); 4182 } 4183 4184 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4185 { 4186 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4187 4188 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4189 } 4190 4191 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4192 Monitor *mon) 4193 { 4194 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4195 4196 spapr_irq_print_info(spapr, mon); 4197 monitor_printf(mon, "irqchip: %s\n", 4198 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4199 } 4200 4201 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4202 uint8_t nvt_blk, uint32_t nvt_idx, 4203 bool cam_ignore, uint8_t priority, 4204 uint32_t logic_serv, XiveTCTXMatch *match) 4205 { 4206 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4207 XivePresenter *xptr = XIVE_PRESENTER(spapr->xive); 4208 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4209 int count; 4210 4211 /* This is a XIVE only operation */ 4212 assert(spapr->active_intc == SPAPR_INTC(spapr->xive)); 4213 4214 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4215 priority, logic_serv, match); 4216 if (count < 0) { 4217 return count; 4218 } 4219 4220 /* 4221 * When we implement the save and restore of the thread interrupt 4222 * contexts in the enter/exit CPU handlers of the machine and the 4223 * escalations in QEMU, we should be able to handle non dispatched 4224 * vCPUs. 4225 * 4226 * Until this is done, the sPAPR machine should find at least one 4227 * matching context always. 4228 */ 4229 if (count == 0) { 4230 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4231 nvt_blk, nvt_idx); 4232 } 4233 4234 return count; 4235 } 4236 4237 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4238 { 4239 return cpu->vcpu_id; 4240 } 4241 4242 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4243 { 4244 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4245 MachineState *ms = MACHINE(spapr); 4246 int vcpu_id; 4247 4248 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4249 4250 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4251 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4252 error_append_hint(errp, "Adjust the number of cpus to %d " 4253 "or try to raise the number of threads per core\n", 4254 vcpu_id * ms->smp.threads / spapr->vsmt); 4255 return; 4256 } 4257 4258 cpu->vcpu_id = vcpu_id; 4259 } 4260 4261 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4262 { 4263 CPUState *cs; 4264 4265 CPU_FOREACH(cs) { 4266 PowerPCCPU *cpu = POWERPC_CPU(cs); 4267 4268 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4269 return cpu; 4270 } 4271 } 4272 4273 return NULL; 4274 } 4275 4276 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4277 { 4278 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4279 4280 /* These are only called by TCG, KVM maintains dispatch state */ 4281 4282 spapr_cpu->prod = false; 4283 if (spapr_cpu->vpa_addr) { 4284 CPUState *cs = CPU(cpu); 4285 uint32_t dispatch; 4286 4287 dispatch = ldl_be_phys(cs->as, 4288 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4289 dispatch++; 4290 if ((dispatch & 1) != 0) { 4291 qemu_log_mask(LOG_GUEST_ERROR, 4292 "VPA: incorrect dispatch counter value for " 4293 "dispatched partition %u, correcting.\n", dispatch); 4294 dispatch++; 4295 } 4296 stl_be_phys(cs->as, 4297 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4298 } 4299 } 4300 4301 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4302 { 4303 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4304 4305 if (spapr_cpu->vpa_addr) { 4306 CPUState *cs = CPU(cpu); 4307 uint32_t dispatch; 4308 4309 dispatch = ldl_be_phys(cs->as, 4310 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4311 dispatch++; 4312 if ((dispatch & 1) != 1) { 4313 qemu_log_mask(LOG_GUEST_ERROR, 4314 "VPA: incorrect dispatch counter value for " 4315 "preempted partition %u, correcting.\n", dispatch); 4316 dispatch++; 4317 } 4318 stl_be_phys(cs->as, 4319 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4320 } 4321 } 4322 4323 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4324 { 4325 MachineClass *mc = MACHINE_CLASS(oc); 4326 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4327 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4328 NMIClass *nc = NMI_CLASS(oc); 4329 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4330 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4331 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4332 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4333 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4334 4335 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4336 mc->ignore_boot_device_suffixes = true; 4337 4338 /* 4339 * We set up the default / latest behaviour here. The class_init 4340 * functions for the specific versioned machine types can override 4341 * these details for backwards compatibility 4342 */ 4343 mc->init = spapr_machine_init; 4344 mc->reset = spapr_machine_reset; 4345 mc->block_default_type = IF_SCSI; 4346 mc->max_cpus = 1024; 4347 mc->no_parallel = 1; 4348 mc->default_boot_order = ""; 4349 mc->default_ram_size = 512 * MiB; 4350 mc->default_display = "std"; 4351 mc->kvm_type = spapr_kvm_type; 4352 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4353 mc->pci_allow_0_address = true; 4354 assert(!mc->get_hotplug_handler); 4355 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4356 hc->pre_plug = spapr_machine_device_pre_plug; 4357 hc->plug = spapr_machine_device_plug; 4358 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4359 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4360 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4361 hc->unplug_request = spapr_machine_device_unplug_request; 4362 hc->unplug = spapr_machine_device_unplug; 4363 4364 smc->dr_lmb_enabled = true; 4365 smc->update_dt_enabled = true; 4366 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4367 mc->has_hotpluggable_cpus = true; 4368 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4369 fwc->get_dev_path = spapr_get_fw_dev_path; 4370 nc->nmi_monitor_handler = spapr_nmi; 4371 smc->phb_placement = spapr_phb_placement; 4372 vhc->hypercall = emulate_spapr_hypercall; 4373 vhc->hpt_mask = spapr_hpt_mask; 4374 vhc->map_hptes = spapr_map_hptes; 4375 vhc->unmap_hptes = spapr_unmap_hptes; 4376 vhc->hpte_set_c = spapr_hpte_set_c; 4377 vhc->hpte_set_r = spapr_hpte_set_r; 4378 vhc->get_pate = spapr_get_pate; 4379 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4380 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4381 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4382 xic->ics_get = spapr_ics_get; 4383 xic->ics_resend = spapr_ics_resend; 4384 xic->icp_get = spapr_icp_get; 4385 ispc->print_info = spapr_pic_print_info; 4386 /* Force NUMA node memory size to be a multiple of 4387 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4388 * in which LMBs are represented and hot-added 4389 */ 4390 mc->numa_mem_align_shift = 28; 4391 mc->numa_mem_supported = true; 4392 mc->auto_enable_numa = true; 4393 4394 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4395 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4396 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4397 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4398 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4399 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4400 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4401 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4402 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4403 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4404 spapr_caps_add_properties(smc, &error_abort); 4405 smc->irq = &spapr_irq_dual; 4406 smc->dr_phb_enabled = true; 4407 smc->linux_pci_probe = true; 4408 smc->smp_threads_vsmt = true; 4409 smc->nr_xirqs = SPAPR_NR_XIRQS; 4410 xfc->match_nvt = spapr_match_nvt; 4411 } 4412 4413 static const TypeInfo spapr_machine_info = { 4414 .name = TYPE_SPAPR_MACHINE, 4415 .parent = TYPE_MACHINE, 4416 .abstract = true, 4417 .instance_size = sizeof(SpaprMachineState), 4418 .instance_init = spapr_instance_init, 4419 .instance_finalize = spapr_machine_finalizefn, 4420 .class_size = sizeof(SpaprMachineClass), 4421 .class_init = spapr_machine_class_init, 4422 .interfaces = (InterfaceInfo[]) { 4423 { TYPE_FW_PATH_PROVIDER }, 4424 { TYPE_NMI }, 4425 { TYPE_HOTPLUG_HANDLER }, 4426 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4427 { TYPE_XICS_FABRIC }, 4428 { TYPE_INTERRUPT_STATS_PROVIDER }, 4429 { TYPE_XIVE_FABRIC }, 4430 { } 4431 }, 4432 }; 4433 4434 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4435 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4436 void *data) \ 4437 { \ 4438 MachineClass *mc = MACHINE_CLASS(oc); \ 4439 spapr_machine_##suffix##_class_options(mc); \ 4440 if (latest) { \ 4441 mc->alias = "pseries"; \ 4442 mc->is_default = 1; \ 4443 } \ 4444 } \ 4445 static const TypeInfo spapr_machine_##suffix##_info = { \ 4446 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4447 .parent = TYPE_SPAPR_MACHINE, \ 4448 .class_init = spapr_machine_##suffix##_class_init, \ 4449 }; \ 4450 static void spapr_machine_register_##suffix(void) \ 4451 { \ 4452 type_register(&spapr_machine_##suffix##_info); \ 4453 } \ 4454 type_init(spapr_machine_register_##suffix) 4455 4456 /* 4457 * pseries-5.0 4458 */ 4459 static void spapr_machine_5_0_class_options(MachineClass *mc) 4460 { 4461 /* Defaults for the latest behaviour inherited from the base class */ 4462 } 4463 4464 DEFINE_SPAPR_MACHINE(5_0, "5.0", true); 4465 4466 /* 4467 * pseries-4.2 4468 */ 4469 static void spapr_machine_4_2_class_options(MachineClass *mc) 4470 { 4471 spapr_machine_5_0_class_options(mc); 4472 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4473 } 4474 4475 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4476 4477 /* 4478 * pseries-4.1 4479 */ 4480 static void spapr_machine_4_1_class_options(MachineClass *mc) 4481 { 4482 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4483 static GlobalProperty compat[] = { 4484 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4485 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4486 }; 4487 4488 spapr_machine_4_2_class_options(mc); 4489 smc->linux_pci_probe = false; 4490 smc->smp_threads_vsmt = false; 4491 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4492 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4493 } 4494 4495 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4496 4497 /* 4498 * pseries-4.0 4499 */ 4500 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4501 uint64_t *buid, hwaddr *pio, 4502 hwaddr *mmio32, hwaddr *mmio64, 4503 unsigned n_dma, uint32_t *liobns, 4504 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4505 { 4506 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, 4507 nv2gpa, nv2atsd, errp); 4508 *nv2gpa = 0; 4509 *nv2atsd = 0; 4510 } 4511 4512 static void spapr_machine_4_0_class_options(MachineClass *mc) 4513 { 4514 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4515 4516 spapr_machine_4_1_class_options(mc); 4517 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4518 smc->phb_placement = phb_placement_4_0; 4519 smc->irq = &spapr_irq_xics; 4520 smc->pre_4_1_migration = true; 4521 } 4522 4523 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4524 4525 /* 4526 * pseries-3.1 4527 */ 4528 static void spapr_machine_3_1_class_options(MachineClass *mc) 4529 { 4530 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4531 4532 spapr_machine_4_0_class_options(mc); 4533 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4534 4535 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4536 smc->update_dt_enabled = false; 4537 smc->dr_phb_enabled = false; 4538 smc->broken_host_serial_model = true; 4539 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4540 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4541 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4542 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4543 } 4544 4545 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4546 4547 /* 4548 * pseries-3.0 4549 */ 4550 4551 static void spapr_machine_3_0_class_options(MachineClass *mc) 4552 { 4553 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4554 4555 spapr_machine_3_1_class_options(mc); 4556 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4557 4558 smc->legacy_irq_allocation = true; 4559 smc->nr_xirqs = 0x400; 4560 smc->irq = &spapr_irq_xics_legacy; 4561 } 4562 4563 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4564 4565 /* 4566 * pseries-2.12 4567 */ 4568 static void spapr_machine_2_12_class_options(MachineClass *mc) 4569 { 4570 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4571 static GlobalProperty compat[] = { 4572 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4573 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4574 }; 4575 4576 spapr_machine_3_0_class_options(mc); 4577 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4578 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4579 4580 /* We depend on kvm_enabled() to choose a default value for the 4581 * hpt-max-page-size capability. Of course we can't do it here 4582 * because this is too early and the HW accelerator isn't initialzed 4583 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4584 */ 4585 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4586 } 4587 4588 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4589 4590 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4591 { 4592 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4593 4594 spapr_machine_2_12_class_options(mc); 4595 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4596 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4597 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4598 } 4599 4600 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4601 4602 /* 4603 * pseries-2.11 4604 */ 4605 4606 static void spapr_machine_2_11_class_options(MachineClass *mc) 4607 { 4608 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4609 4610 spapr_machine_2_12_class_options(mc); 4611 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4612 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4613 } 4614 4615 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4616 4617 /* 4618 * pseries-2.10 4619 */ 4620 4621 static void spapr_machine_2_10_class_options(MachineClass *mc) 4622 { 4623 spapr_machine_2_11_class_options(mc); 4624 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4625 } 4626 4627 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4628 4629 /* 4630 * pseries-2.9 4631 */ 4632 4633 static void spapr_machine_2_9_class_options(MachineClass *mc) 4634 { 4635 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4636 static GlobalProperty compat[] = { 4637 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4638 }; 4639 4640 spapr_machine_2_10_class_options(mc); 4641 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4642 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4643 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4644 smc->pre_2_10_has_unused_icps = true; 4645 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4646 } 4647 4648 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4649 4650 /* 4651 * pseries-2.8 4652 */ 4653 4654 static void spapr_machine_2_8_class_options(MachineClass *mc) 4655 { 4656 static GlobalProperty compat[] = { 4657 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4658 }; 4659 4660 spapr_machine_2_9_class_options(mc); 4661 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4662 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4663 mc->numa_mem_align_shift = 23; 4664 } 4665 4666 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4667 4668 /* 4669 * pseries-2.7 4670 */ 4671 4672 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4673 uint64_t *buid, hwaddr *pio, 4674 hwaddr *mmio32, hwaddr *mmio64, 4675 unsigned n_dma, uint32_t *liobns, 4676 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4677 { 4678 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4679 const uint64_t base_buid = 0x800000020000000ULL; 4680 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4681 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4682 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4683 const uint32_t max_index = 255; 4684 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4685 4686 uint64_t ram_top = MACHINE(spapr)->ram_size; 4687 hwaddr phb0_base, phb_base; 4688 int i; 4689 4690 /* Do we have device memory? */ 4691 if (MACHINE(spapr)->maxram_size > ram_top) { 4692 /* Can't just use maxram_size, because there may be an 4693 * alignment gap between normal and device memory regions 4694 */ 4695 ram_top = MACHINE(spapr)->device_memory->base + 4696 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4697 } 4698 4699 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4700 4701 if (index > max_index) { 4702 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4703 max_index); 4704 return; 4705 } 4706 4707 *buid = base_buid + index; 4708 for (i = 0; i < n_dma; ++i) { 4709 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4710 } 4711 4712 phb_base = phb0_base + index * phb_spacing; 4713 *pio = phb_base + pio_offset; 4714 *mmio32 = phb_base + mmio_offset; 4715 /* 4716 * We don't set the 64-bit MMIO window, relying on the PHB's 4717 * fallback behaviour of automatically splitting a large "32-bit" 4718 * window into contiguous 32-bit and 64-bit windows 4719 */ 4720 4721 *nv2gpa = 0; 4722 *nv2atsd = 0; 4723 } 4724 4725 static void spapr_machine_2_7_class_options(MachineClass *mc) 4726 { 4727 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4728 static GlobalProperty compat[] = { 4729 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4730 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4731 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4732 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4733 }; 4734 4735 spapr_machine_2_8_class_options(mc); 4736 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4737 mc->default_machine_opts = "modern-hotplug-events=off"; 4738 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4739 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4740 smc->phb_placement = phb_placement_2_7; 4741 } 4742 4743 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4744 4745 /* 4746 * pseries-2.6 4747 */ 4748 4749 static void spapr_machine_2_6_class_options(MachineClass *mc) 4750 { 4751 static GlobalProperty compat[] = { 4752 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4753 }; 4754 4755 spapr_machine_2_7_class_options(mc); 4756 mc->has_hotpluggable_cpus = false; 4757 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4758 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4759 } 4760 4761 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4762 4763 /* 4764 * pseries-2.5 4765 */ 4766 4767 static void spapr_machine_2_5_class_options(MachineClass *mc) 4768 { 4769 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4770 static GlobalProperty compat[] = { 4771 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4772 }; 4773 4774 spapr_machine_2_6_class_options(mc); 4775 smc->use_ohci_by_default = true; 4776 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4777 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4778 } 4779 4780 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4781 4782 /* 4783 * pseries-2.4 4784 */ 4785 4786 static void spapr_machine_2_4_class_options(MachineClass *mc) 4787 { 4788 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4789 4790 spapr_machine_2_5_class_options(mc); 4791 smc->dr_lmb_enabled = false; 4792 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4793 } 4794 4795 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4796 4797 /* 4798 * pseries-2.3 4799 */ 4800 4801 static void spapr_machine_2_3_class_options(MachineClass *mc) 4802 { 4803 static GlobalProperty compat[] = { 4804 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4805 }; 4806 spapr_machine_2_4_class_options(mc); 4807 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4808 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4809 } 4810 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4811 4812 /* 4813 * pseries-2.2 4814 */ 4815 4816 static void spapr_machine_2_2_class_options(MachineClass *mc) 4817 { 4818 static GlobalProperty compat[] = { 4819 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4820 }; 4821 4822 spapr_machine_2_3_class_options(mc); 4823 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4824 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4825 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4826 } 4827 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4828 4829 /* 4830 * pseries-2.1 4831 */ 4832 4833 static void spapr_machine_2_1_class_options(MachineClass *mc) 4834 { 4835 spapr_machine_2_2_class_options(mc); 4836 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4837 } 4838 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4839 4840 static void spapr_machine_register_types(void) 4841 { 4842 type_register_static(&spapr_machine_info); 4843 } 4844 4845 type_init(spapr_machine_register_types) 4846