xref: /openbmc/qemu/hw/ppc/spapr.c (revision 650d103d3ea959212f826acb9d3fe80cf30e347b)
1 /*
2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3  *
4  * Copyright (c) 2004-2007 Fabrice Bellard
5  * Copyright (c) 2007 Jocelyn Mayer
6  * Copyright (c) 2010 David Gibson, IBM Corporation.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a copy
9  * of this software and associated documentation files (the "Software"), to deal
10  * in the Software without restriction, including without limitation the rights
11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12  * copies of the Software, and to permit persons to whom the Software is
13  * furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be included in
16  * all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24  * THE SOFTWARE.
25  */
26 
27 #include "qemu/osdep.h"
28 #include "qemu-common.h"
29 #include "qapi/error.h"
30 #include "qapi/visitor.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/numa.h"
33 #include "sysemu/qtest.h"
34 #include "sysemu/reset.h"
35 #include "qemu/log.h"
36 #include "hw/fw-path-provider.h"
37 #include "elf.h"
38 #include "net/net.h"
39 #include "sysemu/device_tree.h"
40 #include "sysemu/cpus.h"
41 #include "sysemu/hw_accel.h"
42 #include "kvm_ppc.h"
43 #include "migration/misc.h"
44 #include "migration/qemu-file-types.h"
45 #include "migration/global_state.h"
46 #include "migration/register.h"
47 #include "mmu-hash64.h"
48 #include "mmu-book3s-v3.h"
49 #include "cpu-models.h"
50 #include "qom/cpu.h"
51 
52 #include "hw/boards.h"
53 #include "hw/ppc/ppc.h"
54 #include "hw/loader.h"
55 
56 #include "hw/ppc/fdt.h"
57 #include "hw/ppc/spapr.h"
58 #include "hw/ppc/spapr_vio.h"
59 #include "hw/pci-host/spapr.h"
60 #include "hw/pci/msi.h"
61 
62 #include "hw/pci/pci.h"
63 #include "hw/scsi/scsi.h"
64 #include "hw/virtio/virtio-scsi.h"
65 #include "hw/virtio/vhost-scsi-common.h"
66 
67 #include "exec/address-spaces.h"
68 #include "exec/ram_addr.h"
69 #include "hw/usb.h"
70 #include "qemu/config-file.h"
71 #include "qemu/error-report.h"
72 #include "trace.h"
73 #include "hw/nmi.h"
74 #include "hw/intc/intc.h"
75 
76 #include "qemu/cutils.h"
77 #include "hw/ppc/spapr_cpu_core.h"
78 #include "hw/mem/memory-device.h"
79 
80 #include <libfdt.h>
81 
82 /* SLOF memory layout:
83  *
84  * SLOF raw image loaded at 0, copies its romfs right below the flat
85  * device-tree, then position SLOF itself 31M below that
86  *
87  * So we set FW_OVERHEAD to 40MB which should account for all of that
88  * and more
89  *
90  * We load our kernel at 4M, leaving space for SLOF initial image
91  */
92 #define FDT_MAX_SIZE            0x100000
93 #define RTAS_MAX_SIZE           0x10000
94 #define RTAS_MAX_ADDR           0x80000000 /* RTAS must stay below that */
95 #define FW_MAX_SIZE             0x400000
96 #define FW_FILE_NAME            "slof.bin"
97 #define FW_OVERHEAD             0x2800000
98 #define KERNEL_LOAD_ADDR        FW_MAX_SIZE
99 
100 #define MIN_RMA_SLOF            128UL
101 
102 #define PHANDLE_INTC            0x00001111
103 
104 /* These two functions implement the VCPU id numbering: one to compute them
105  * all and one to identify thread 0 of a VCORE. Any change to the first one
106  * is likely to have an impact on the second one, so let's keep them close.
107  */
108 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index)
109 {
110     MachineState *ms = MACHINE(spapr);
111     unsigned int smp_threads = ms->smp.threads;
112 
113     assert(spapr->vsmt);
114     return
115         (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads;
116 }
117 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr,
118                                       PowerPCCPU *cpu)
119 {
120     assert(spapr->vsmt);
121     return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0;
122 }
123 
124 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
125 {
126     /* Dummy entries correspond to unused ICPState objects in older QEMUs,
127      * and newer QEMUs don't even have them. In both cases, we don't want
128      * to send anything on the wire.
129      */
130     return false;
131 }
132 
133 static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
134     .name = "icp/server",
135     .version_id = 1,
136     .minimum_version_id = 1,
137     .needed = pre_2_10_vmstate_dummy_icp_needed,
138     .fields = (VMStateField[]) {
139         VMSTATE_UNUSED(4), /* uint32_t xirr */
140         VMSTATE_UNUSED(1), /* uint8_t pending_priority */
141         VMSTATE_UNUSED(1), /* uint8_t mfrr */
142         VMSTATE_END_OF_LIST()
143     },
144 };
145 
146 static void pre_2_10_vmstate_register_dummy_icp(int i)
147 {
148     vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
149                      (void *)(uintptr_t) i);
150 }
151 
152 static void pre_2_10_vmstate_unregister_dummy_icp(int i)
153 {
154     vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
155                        (void *)(uintptr_t) i);
156 }
157 
158 int spapr_max_server_number(SpaprMachineState *spapr)
159 {
160     MachineState *ms = MACHINE(spapr);
161 
162     assert(spapr->vsmt);
163     return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads);
164 }
165 
166 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
167                                   int smt_threads)
168 {
169     int i, ret = 0;
170     uint32_t servers_prop[smt_threads];
171     uint32_t gservers_prop[smt_threads * 2];
172     int index = spapr_get_vcpu_id(cpu);
173 
174     if (cpu->compat_pvr) {
175         ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
176         if (ret < 0) {
177             return ret;
178         }
179     }
180 
181     /* Build interrupt servers and gservers properties */
182     for (i = 0; i < smt_threads; i++) {
183         servers_prop[i] = cpu_to_be32(index + i);
184         /* Hack, direct the group queues back to cpu 0 */
185         gservers_prop[i*2] = cpu_to_be32(index + i);
186         gservers_prop[i*2 + 1] = 0;
187     }
188     ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
189                       servers_prop, sizeof(servers_prop));
190     if (ret < 0) {
191         return ret;
192     }
193     ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
194                       gservers_prop, sizeof(gservers_prop));
195 
196     return ret;
197 }
198 
199 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
200 {
201     int index = spapr_get_vcpu_id(cpu);
202     uint32_t associativity[] = {cpu_to_be32(0x5),
203                                 cpu_to_be32(0x0),
204                                 cpu_to_be32(0x0),
205                                 cpu_to_be32(0x0),
206                                 cpu_to_be32(cpu->node_id),
207                                 cpu_to_be32(index)};
208 
209     /* Advertise NUMA via ibm,associativity */
210     return fdt_setprop(fdt, offset, "ibm,associativity", associativity,
211                           sizeof(associativity));
212 }
213 
214 /* Populate the "ibm,pa-features" property */
215 static void spapr_populate_pa_features(SpaprMachineState *spapr,
216                                        PowerPCCPU *cpu,
217                                        void *fdt, int offset,
218                                        bool legacy_guest)
219 {
220     uint8_t pa_features_206[] = { 6, 0,
221         0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
222     uint8_t pa_features_207[] = { 24, 0,
223         0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
224         0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
225         0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
226         0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
227     uint8_t pa_features_300[] = { 66, 0,
228         /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
229         /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
230         0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
231         /* 6: DS207 */
232         0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
233         /* 16: Vector */
234         0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
235         /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
236         0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
237         /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
238         0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
239         /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
240         0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
241         /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
242         0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
243         /* 42: PM, 44: PC RA, 46: SC vec'd */
244         0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
245         /* 48: SIMD, 50: QP BFP, 52: String */
246         0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
247         /* 54: DecFP, 56: DecI, 58: SHA */
248         0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
249         /* 60: NM atomic, 62: RNG */
250         0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
251     };
252     uint8_t *pa_features = NULL;
253     size_t pa_size;
254 
255     if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) {
256         pa_features = pa_features_206;
257         pa_size = sizeof(pa_features_206);
258     }
259     if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) {
260         pa_features = pa_features_207;
261         pa_size = sizeof(pa_features_207);
262     }
263     if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) {
264         pa_features = pa_features_300;
265         pa_size = sizeof(pa_features_300);
266     }
267     if (!pa_features) {
268         return;
269     }
270 
271     if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
272         /*
273          * Note: we keep CI large pages off by default because a 64K capable
274          * guest provisioned with large pages might otherwise try to map a qemu
275          * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
276          * even if that qemu runs on a 4k host.
277          * We dd this bit back here if we are confident this is not an issue
278          */
279         pa_features[3] |= 0x20;
280     }
281     if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
282         pa_features[24] |= 0x80;    /* Transactional memory support */
283     }
284     if (legacy_guest && pa_size > 40) {
285         /* Workaround for broken kernels that attempt (guest) radix
286          * mode when they can't handle it, if they see the radix bit set
287          * in pa-features. So hide it from them. */
288         pa_features[40 + 2] &= ~0x80; /* Radix MMU */
289     }
290 
291     _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
292 }
293 
294 static int spapr_fixup_cpu_dt(void *fdt, SpaprMachineState *spapr)
295 {
296     MachineState *ms = MACHINE(spapr);
297     int ret = 0, offset, cpus_offset;
298     CPUState *cs;
299     char cpu_model[32];
300     uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
301 
302     CPU_FOREACH(cs) {
303         PowerPCCPU *cpu = POWERPC_CPU(cs);
304         DeviceClass *dc = DEVICE_GET_CLASS(cs);
305         int index = spapr_get_vcpu_id(cpu);
306         int compat_smt = MIN(ms->smp.threads, ppc_compat_max_vthreads(cpu));
307 
308         if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
309             continue;
310         }
311 
312         snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
313 
314         cpus_offset = fdt_path_offset(fdt, "/cpus");
315         if (cpus_offset < 0) {
316             cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
317             if (cpus_offset < 0) {
318                 return cpus_offset;
319             }
320         }
321         offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
322         if (offset < 0) {
323             offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
324             if (offset < 0) {
325                 return offset;
326             }
327         }
328 
329         ret = fdt_setprop(fdt, offset, "ibm,pft-size",
330                           pft_size_prop, sizeof(pft_size_prop));
331         if (ret < 0) {
332             return ret;
333         }
334 
335         if (nb_numa_nodes > 1) {
336             ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu);
337             if (ret < 0) {
338                 return ret;
339             }
340         }
341 
342         ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
343         if (ret < 0) {
344             return ret;
345         }
346 
347         spapr_populate_pa_features(spapr, cpu, fdt, offset,
348                                    spapr->cas_legacy_guest_workaround);
349     }
350     return ret;
351 }
352 
353 static hwaddr spapr_node0_size(MachineState *machine)
354 {
355     if (nb_numa_nodes) {
356         int i;
357         for (i = 0; i < nb_numa_nodes; ++i) {
358             if (numa_info[i].node_mem) {
359                 return MIN(pow2floor(numa_info[i].node_mem),
360                            machine->ram_size);
361             }
362         }
363     }
364     return machine->ram_size;
365 }
366 
367 static void add_str(GString *s, const gchar *s1)
368 {
369     g_string_append_len(s, s1, strlen(s1) + 1);
370 }
371 
372 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
373                                        hwaddr size)
374 {
375     uint32_t associativity[] = {
376         cpu_to_be32(0x4), /* length */
377         cpu_to_be32(0x0), cpu_to_be32(0x0),
378         cpu_to_be32(0x0), cpu_to_be32(nodeid)
379     };
380     char mem_name[32];
381     uint64_t mem_reg_property[2];
382     int off;
383 
384     mem_reg_property[0] = cpu_to_be64(start);
385     mem_reg_property[1] = cpu_to_be64(size);
386 
387     sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
388     off = fdt_add_subnode(fdt, 0, mem_name);
389     _FDT(off);
390     _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
391     _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
392                       sizeof(mem_reg_property))));
393     _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
394                       sizeof(associativity))));
395     return off;
396 }
397 
398 static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt)
399 {
400     MachineState *machine = MACHINE(spapr);
401     hwaddr mem_start, node_size;
402     int i, nb_nodes = nb_numa_nodes;
403     NodeInfo *nodes = numa_info;
404     NodeInfo ramnode;
405 
406     /* No NUMA nodes, assume there is just one node with whole RAM */
407     if (!nb_numa_nodes) {
408         nb_nodes = 1;
409         ramnode.node_mem = machine->ram_size;
410         nodes = &ramnode;
411     }
412 
413     for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
414         if (!nodes[i].node_mem) {
415             continue;
416         }
417         if (mem_start >= machine->ram_size) {
418             node_size = 0;
419         } else {
420             node_size = nodes[i].node_mem;
421             if (node_size > machine->ram_size - mem_start) {
422                 node_size = machine->ram_size - mem_start;
423             }
424         }
425         if (!mem_start) {
426             /* spapr_machine_init() checks for rma_size <= node0_size
427              * already */
428             spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
429             mem_start += spapr->rma_size;
430             node_size -= spapr->rma_size;
431         }
432         for ( ; node_size; ) {
433             hwaddr sizetmp = pow2floor(node_size);
434 
435             /* mem_start != 0 here */
436             if (ctzl(mem_start) < ctzl(sizetmp)) {
437                 sizetmp = 1ULL << ctzl(mem_start);
438             }
439 
440             spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
441             node_size -= sizetmp;
442             mem_start += sizetmp;
443         }
444     }
445 
446     return 0;
447 }
448 
449 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
450                                   SpaprMachineState *spapr)
451 {
452     MachineState *ms = MACHINE(spapr);
453     PowerPCCPU *cpu = POWERPC_CPU(cs);
454     CPUPPCState *env = &cpu->env;
455     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
456     int index = spapr_get_vcpu_id(cpu);
457     uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
458                        0xffffffff, 0xffffffff};
459     uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
460         : SPAPR_TIMEBASE_FREQ;
461     uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
462     uint32_t page_sizes_prop[64];
463     size_t page_sizes_prop_size;
464     unsigned int smp_threads = ms->smp.threads;
465     uint32_t vcpus_per_socket = smp_threads * ms->smp.cores;
466     uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
467     int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
468     SpaprDrc *drc;
469     int drc_index;
470     uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
471     int i;
472 
473     drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
474     if (drc) {
475         drc_index = spapr_drc_index(drc);
476         _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
477     }
478 
479     _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
480     _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
481 
482     _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
483     _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
484                            env->dcache_line_size)));
485     _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
486                            env->dcache_line_size)));
487     _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
488                            env->icache_line_size)));
489     _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
490                            env->icache_line_size)));
491 
492     if (pcc->l1_dcache_size) {
493         _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
494                                pcc->l1_dcache_size)));
495     } else {
496         warn_report("Unknown L1 dcache size for cpu");
497     }
498     if (pcc->l1_icache_size) {
499         _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
500                                pcc->l1_icache_size)));
501     } else {
502         warn_report("Unknown L1 icache size for cpu");
503     }
504 
505     _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
506     _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
507     _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size)));
508     _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
509     _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
510     _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
511 
512     if (env->spr_cb[SPR_PURR].oea_read) {
513         _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1)));
514     }
515     if (env->spr_cb[SPR_SPURR].oea_read) {
516         _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1)));
517     }
518 
519     if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
520         _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
521                           segs, sizeof(segs))));
522     }
523 
524     /* Advertise VSX (vector extensions) if available
525      *   1               == VMX / Altivec available
526      *   2               == VSX available
527      *
528      * Only CPUs for which we create core types in spapr_cpu_core.c
529      * are possible, and all of those have VMX */
530     if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) {
531         _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
532     } else {
533         _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
534     }
535 
536     /* Advertise DFP (Decimal Floating Point) if available
537      *   0 / no property == no DFP
538      *   1               == DFP available */
539     if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) {
540         _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
541     }
542 
543     page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
544                                                       sizeof(page_sizes_prop));
545     if (page_sizes_prop_size) {
546         _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
547                           page_sizes_prop, page_sizes_prop_size)));
548     }
549 
550     spapr_populate_pa_features(spapr, cpu, fdt, offset, false);
551 
552     _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
553                            cs->cpu_index / vcpus_per_socket)));
554 
555     _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
556                       pft_size_prop, sizeof(pft_size_prop))));
557 
558     if (nb_numa_nodes > 1) {
559         _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
560     }
561 
562     _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
563 
564     if (pcc->radix_page_info) {
565         for (i = 0; i < pcc->radix_page_info->count; i++) {
566             radix_AP_encodings[i] =
567                 cpu_to_be32(pcc->radix_page_info->entries[i]);
568         }
569         _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
570                           radix_AP_encodings,
571                           pcc->radix_page_info->count *
572                           sizeof(radix_AP_encodings[0]))));
573     }
574 
575     /*
576      * We set this property to let the guest know that it can use the large
577      * decrementer and its width in bits.
578      */
579     if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF)
580         _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits",
581                               pcc->lrg_decr_bits)));
582 }
583 
584 static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spapr)
585 {
586     CPUState **rev;
587     CPUState *cs;
588     int n_cpus;
589     int cpus_offset;
590     char *nodename;
591     int i;
592 
593     cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
594     _FDT(cpus_offset);
595     _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
596     _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
597 
598     /*
599      * We walk the CPUs in reverse order to ensure that CPU DT nodes
600      * created by fdt_add_subnode() end up in the right order in FDT
601      * for the guest kernel the enumerate the CPUs correctly.
602      *
603      * The CPU list cannot be traversed in reverse order, so we need
604      * to do extra work.
605      */
606     n_cpus = 0;
607     rev = NULL;
608     CPU_FOREACH(cs) {
609         rev = g_renew(CPUState *, rev, n_cpus + 1);
610         rev[n_cpus++] = cs;
611     }
612 
613     for (i = n_cpus - 1; i >= 0; i--) {
614         CPUState *cs = rev[i];
615         PowerPCCPU *cpu = POWERPC_CPU(cs);
616         int index = spapr_get_vcpu_id(cpu);
617         DeviceClass *dc = DEVICE_GET_CLASS(cs);
618         int offset;
619 
620         if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
621             continue;
622         }
623 
624         nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
625         offset = fdt_add_subnode(fdt, cpus_offset, nodename);
626         g_free(nodename);
627         _FDT(offset);
628         spapr_populate_cpu_dt(cs, fdt, offset, spapr);
629     }
630 
631     g_free(rev);
632 }
633 
634 static int spapr_rng_populate_dt(void *fdt)
635 {
636     int node;
637     int ret;
638 
639     node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities");
640     if (node <= 0) {
641         return -1;
642     }
643     ret = fdt_setprop_string(fdt, node, "device_type",
644                              "ibm,platform-facilities");
645     ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1);
646     ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0);
647 
648     node = fdt_add_subnode(fdt, node, "ibm,random-v1");
649     if (node <= 0) {
650         return -1;
651     }
652     ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random");
653 
654     return ret ? -1 : 0;
655 }
656 
657 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
658 {
659     MemoryDeviceInfoList *info;
660 
661     for (info = list; info; info = info->next) {
662         MemoryDeviceInfo *value = info->value;
663 
664         if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
665             PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
666 
667             if (addr >= pcdimm_info->addr &&
668                 addr < (pcdimm_info->addr + pcdimm_info->size)) {
669                 return pcdimm_info->node;
670             }
671         }
672     }
673 
674     return -1;
675 }
676 
677 struct sPAPRDrconfCellV2 {
678      uint32_t seq_lmbs;
679      uint64_t base_addr;
680      uint32_t drc_index;
681      uint32_t aa_index;
682      uint32_t flags;
683 } QEMU_PACKED;
684 
685 typedef struct DrconfCellQueue {
686     struct sPAPRDrconfCellV2 cell;
687     QSIMPLEQ_ENTRY(DrconfCellQueue) entry;
688 } DrconfCellQueue;
689 
690 static DrconfCellQueue *
691 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr,
692                       uint32_t drc_index, uint32_t aa_index,
693                       uint32_t flags)
694 {
695     DrconfCellQueue *elem;
696 
697     elem = g_malloc0(sizeof(*elem));
698     elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs);
699     elem->cell.base_addr = cpu_to_be64(base_addr);
700     elem->cell.drc_index = cpu_to_be32(drc_index);
701     elem->cell.aa_index = cpu_to_be32(aa_index);
702     elem->cell.flags = cpu_to_be32(flags);
703 
704     return elem;
705 }
706 
707 /* ibm,dynamic-memory-v2 */
708 static int spapr_populate_drmem_v2(SpaprMachineState *spapr, void *fdt,
709                                    int offset, MemoryDeviceInfoList *dimms)
710 {
711     MachineState *machine = MACHINE(spapr);
712     uint8_t *int_buf, *cur_index;
713     int ret;
714     uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
715     uint64_t addr, cur_addr, size;
716     uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size);
717     uint64_t mem_end = machine->device_memory->base +
718                        memory_region_size(&machine->device_memory->mr);
719     uint32_t node, buf_len, nr_entries = 0;
720     SpaprDrc *drc;
721     DrconfCellQueue *elem, *next;
722     MemoryDeviceInfoList *info;
723     QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue
724         = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue);
725 
726     /* Entry to cover RAM and the gap area */
727     elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1,
728                                  SPAPR_LMB_FLAGS_RESERVED |
729                                  SPAPR_LMB_FLAGS_DRC_INVALID);
730     QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
731     nr_entries++;
732 
733     cur_addr = machine->device_memory->base;
734     for (info = dimms; info; info = info->next) {
735         PCDIMMDeviceInfo *di = info->value->u.dimm.data;
736 
737         addr = di->addr;
738         size = di->size;
739         node = di->node;
740 
741         /* Entry for hot-pluggable area */
742         if (cur_addr < addr) {
743             drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
744             g_assert(drc);
745             elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size,
746                                          cur_addr, spapr_drc_index(drc), -1, 0);
747             QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
748             nr_entries++;
749         }
750 
751         /* Entry for DIMM */
752         drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size);
753         g_assert(drc);
754         elem = spapr_get_drconf_cell(size / lmb_size, addr,
755                                      spapr_drc_index(drc), node,
756                                      SPAPR_LMB_FLAGS_ASSIGNED);
757         QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
758         nr_entries++;
759         cur_addr = addr + size;
760     }
761 
762     /* Entry for remaining hotpluggable area */
763     if (cur_addr < mem_end) {
764         drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
765         g_assert(drc);
766         elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size,
767                                      cur_addr, spapr_drc_index(drc), -1, 0);
768         QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
769         nr_entries++;
770     }
771 
772     buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t);
773     int_buf = cur_index = g_malloc0(buf_len);
774     *(uint32_t *)int_buf = cpu_to_be32(nr_entries);
775     cur_index += sizeof(nr_entries);
776 
777     QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) {
778         memcpy(cur_index, &elem->cell, sizeof(elem->cell));
779         cur_index += sizeof(elem->cell);
780         QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry);
781         g_free(elem);
782     }
783 
784     ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len);
785     g_free(int_buf);
786     if (ret < 0) {
787         return -1;
788     }
789     return 0;
790 }
791 
792 /* ibm,dynamic-memory */
793 static int spapr_populate_drmem_v1(SpaprMachineState *spapr, void *fdt,
794                                    int offset, MemoryDeviceInfoList *dimms)
795 {
796     MachineState *machine = MACHINE(spapr);
797     int i, ret;
798     uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
799     uint32_t device_lmb_start = machine->device_memory->base / lmb_size;
800     uint32_t nr_lmbs = (machine->device_memory->base +
801                        memory_region_size(&machine->device_memory->mr)) /
802                        lmb_size;
803     uint32_t *int_buf, *cur_index, buf_len;
804 
805     /*
806      * Allocate enough buffer size to fit in ibm,dynamic-memory
807      */
808     buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t);
809     cur_index = int_buf = g_malloc0(buf_len);
810     int_buf[0] = cpu_to_be32(nr_lmbs);
811     cur_index++;
812     for (i = 0; i < nr_lmbs; i++) {
813         uint64_t addr = i * lmb_size;
814         uint32_t *dynamic_memory = cur_index;
815 
816         if (i >= device_lmb_start) {
817             SpaprDrc *drc;
818 
819             drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
820             g_assert(drc);
821 
822             dynamic_memory[0] = cpu_to_be32(addr >> 32);
823             dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
824             dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
825             dynamic_memory[3] = cpu_to_be32(0); /* reserved */
826             dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr));
827             if (memory_region_present(get_system_memory(), addr)) {
828                 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
829             } else {
830                 dynamic_memory[5] = cpu_to_be32(0);
831             }
832         } else {
833             /*
834              * LMB information for RMA, boot time RAM and gap b/n RAM and
835              * device memory region -- all these are marked as reserved
836              * and as having no valid DRC.
837              */
838             dynamic_memory[0] = cpu_to_be32(addr >> 32);
839             dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
840             dynamic_memory[2] = cpu_to_be32(0);
841             dynamic_memory[3] = cpu_to_be32(0); /* reserved */
842             dynamic_memory[4] = cpu_to_be32(-1);
843             dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
844                                             SPAPR_LMB_FLAGS_DRC_INVALID);
845         }
846 
847         cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
848     }
849     ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
850     g_free(int_buf);
851     if (ret < 0) {
852         return -1;
853     }
854     return 0;
855 }
856 
857 /*
858  * Adds ibm,dynamic-reconfiguration-memory node.
859  * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
860  * of this device tree node.
861  */
862 static int spapr_populate_drconf_memory(SpaprMachineState *spapr, void *fdt)
863 {
864     MachineState *machine = MACHINE(spapr);
865     int ret, i, offset;
866     uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
867     uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
868     uint32_t *int_buf, *cur_index, buf_len;
869     int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
870     MemoryDeviceInfoList *dimms = NULL;
871 
872     /*
873      * Don't create the node if there is no device memory
874      */
875     if (machine->ram_size == machine->maxram_size) {
876         return 0;
877     }
878 
879     offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
880 
881     ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
882                     sizeof(prop_lmb_size));
883     if (ret < 0) {
884         return ret;
885     }
886 
887     ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
888     if (ret < 0) {
889         return ret;
890     }
891 
892     ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
893     if (ret < 0) {
894         return ret;
895     }
896 
897     /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
898     dimms = qmp_memory_device_list();
899     if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) {
900         ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms);
901     } else {
902         ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms);
903     }
904     qapi_free_MemoryDeviceInfoList(dimms);
905 
906     if (ret < 0) {
907         return ret;
908     }
909 
910     /* ibm,associativity-lookup-arrays */
911     buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t);
912     cur_index = int_buf = g_malloc0(buf_len);
913     int_buf[0] = cpu_to_be32(nr_nodes);
914     int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
915     cur_index += 2;
916     for (i = 0; i < nr_nodes; i++) {
917         uint32_t associativity[] = {
918             cpu_to_be32(0x0),
919             cpu_to_be32(0x0),
920             cpu_to_be32(0x0),
921             cpu_to_be32(i)
922         };
923         memcpy(cur_index, associativity, sizeof(associativity));
924         cur_index += 4;
925     }
926     ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
927             (cur_index - int_buf) * sizeof(uint32_t));
928     g_free(int_buf);
929 
930     return ret;
931 }
932 
933 static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt,
934                                 SpaprOptionVector *ov5_updates)
935 {
936     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
937     int ret = 0, offset;
938 
939     /* Generate ibm,dynamic-reconfiguration-memory node if required */
940     if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
941         g_assert(smc->dr_lmb_enabled);
942         ret = spapr_populate_drconf_memory(spapr, fdt);
943         if (ret) {
944             goto out;
945         }
946     }
947 
948     offset = fdt_path_offset(fdt, "/chosen");
949     if (offset < 0) {
950         offset = fdt_add_subnode(fdt, 0, "chosen");
951         if (offset < 0) {
952             return offset;
953         }
954     }
955     ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
956                                  "ibm,architecture-vec-5");
957 
958 out:
959     return ret;
960 }
961 
962 static bool spapr_hotplugged_dev_before_cas(void)
963 {
964     Object *drc_container, *obj;
965     ObjectProperty *prop;
966     ObjectPropertyIterator iter;
967 
968     drc_container = container_get(object_get_root(), "/dr-connector");
969     object_property_iter_init(&iter, drc_container);
970     while ((prop = object_property_iter_next(&iter))) {
971         if (!strstart(prop->type, "link<", NULL)) {
972             continue;
973         }
974         obj = object_property_get_link(drc_container, prop->name, NULL);
975         if (spapr_drc_needed(obj)) {
976             return true;
977         }
978     }
979     return false;
980 }
981 
982 int spapr_h_cas_compose_response(SpaprMachineState *spapr,
983                                  target_ulong addr, target_ulong size,
984                                  SpaprOptionVector *ov5_updates)
985 {
986     void *fdt, *fdt_skel;
987     SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 };
988 
989     if (spapr_hotplugged_dev_before_cas()) {
990         return 1;
991     }
992 
993     if (size < sizeof(hdr) || size > FW_MAX_SIZE) {
994         error_report("SLOF provided an unexpected CAS buffer size "
995                      TARGET_FMT_lu " (min: %zu, max: %u)",
996                      size, sizeof(hdr), FW_MAX_SIZE);
997         exit(EXIT_FAILURE);
998     }
999 
1000     size -= sizeof(hdr);
1001 
1002     /* Create skeleton */
1003     fdt_skel = g_malloc0(size);
1004     _FDT((fdt_create(fdt_skel, size)));
1005     _FDT((fdt_finish_reservemap(fdt_skel)));
1006     _FDT((fdt_begin_node(fdt_skel, "")));
1007     _FDT((fdt_end_node(fdt_skel)));
1008     _FDT((fdt_finish(fdt_skel)));
1009     fdt = g_malloc0(size);
1010     _FDT((fdt_open_into(fdt_skel, fdt, size)));
1011     g_free(fdt_skel);
1012 
1013     /* Fixup cpu nodes */
1014     _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
1015 
1016     if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
1017         return -1;
1018     }
1019 
1020     /* Pack resulting tree */
1021     _FDT((fdt_pack(fdt)));
1022 
1023     if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
1024         trace_spapr_cas_failed(size);
1025         return -1;
1026     }
1027 
1028     cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
1029     cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
1030     trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
1031     g_free(fdt);
1032 
1033     return 0;
1034 }
1035 
1036 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
1037 {
1038     MachineState *ms = MACHINE(spapr);
1039     int rtas;
1040     GString *hypertas = g_string_sized_new(256);
1041     GString *qemu_hypertas = g_string_sized_new(256);
1042     uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
1043     uint64_t max_device_addr = MACHINE(spapr)->device_memory->base +
1044         memory_region_size(&MACHINE(spapr)->device_memory->mr);
1045     uint32_t lrdr_capacity[] = {
1046         cpu_to_be32(max_device_addr >> 32),
1047         cpu_to_be32(max_device_addr & 0xffffffff),
1048         0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
1049         cpu_to_be32(ms->smp.max_cpus / ms->smp.threads),
1050     };
1051     uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0);
1052     uint32_t maxdomains[] = {
1053         cpu_to_be32(4),
1054         maxdomain,
1055         maxdomain,
1056         maxdomain,
1057         cpu_to_be32(spapr->gpu_numa_id),
1058     };
1059 
1060     _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
1061 
1062     /* hypertas */
1063     add_str(hypertas, "hcall-pft");
1064     add_str(hypertas, "hcall-term");
1065     add_str(hypertas, "hcall-dabr");
1066     add_str(hypertas, "hcall-interrupt");
1067     add_str(hypertas, "hcall-tce");
1068     add_str(hypertas, "hcall-vio");
1069     add_str(hypertas, "hcall-splpar");
1070     add_str(hypertas, "hcall-bulk");
1071     add_str(hypertas, "hcall-set-mode");
1072     add_str(hypertas, "hcall-sprg0");
1073     add_str(hypertas, "hcall-copy");
1074     add_str(hypertas, "hcall-debug");
1075     add_str(hypertas, "hcall-vphn");
1076     add_str(qemu_hypertas, "hcall-memop1");
1077 
1078     if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
1079         add_str(hypertas, "hcall-multi-tce");
1080     }
1081 
1082     if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
1083         add_str(hypertas, "hcall-hpt-resize");
1084     }
1085 
1086     _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
1087                      hypertas->str, hypertas->len));
1088     g_string_free(hypertas, TRUE);
1089     _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
1090                      qemu_hypertas->str, qemu_hypertas->len));
1091     g_string_free(qemu_hypertas, TRUE);
1092 
1093     _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
1094                      refpoints, sizeof(refpoints)));
1095 
1096     _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains",
1097                      maxdomains, sizeof(maxdomains)));
1098 
1099     _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
1100                           RTAS_ERROR_LOG_MAX));
1101     _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
1102                           RTAS_EVENT_SCAN_RATE));
1103 
1104     g_assert(msi_nonbroken);
1105     _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
1106 
1107     /*
1108      * According to PAPR, rtas ibm,os-term does not guarantee a return
1109      * back to the guest cpu.
1110      *
1111      * While an additional ibm,extended-os-term property indicates
1112      * that rtas call return will always occur. Set this property.
1113      */
1114     _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
1115 
1116     _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
1117                      lrdr_capacity, sizeof(lrdr_capacity)));
1118 
1119     spapr_dt_rtas_tokens(fdt, rtas);
1120 }
1121 
1122 /*
1123  * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
1124  * and the XIVE features that the guest may request and thus the valid
1125  * values for bytes 23..26 of option vector 5:
1126  */
1127 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt,
1128                                           int chosen)
1129 {
1130     PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
1131 
1132     char val[2 * 4] = {
1133         23, spapr->irq->ov5, /* Xive mode. */
1134         24, 0x00, /* Hash/Radix, filled in below. */
1135         25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
1136         26, 0x40, /* Radix options: GTSE == yes. */
1137     };
1138 
1139     if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
1140                           first_ppc_cpu->compat_pvr)) {
1141         /*
1142          * If we're in a pre POWER9 compat mode then the guest should
1143          * do hash and use the legacy interrupt mode
1144          */
1145         val[1] = 0x00; /* XICS */
1146         val[3] = 0x00; /* Hash */
1147     } else if (kvm_enabled()) {
1148         if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1149             val[3] = 0x80; /* OV5_MMU_BOTH */
1150         } else if (kvmppc_has_cap_mmu_radix()) {
1151             val[3] = 0x40; /* OV5_MMU_RADIX_300 */
1152         } else {
1153             val[3] = 0x00; /* Hash */
1154         }
1155     } else {
1156         /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1157         val[3] = 0xC0;
1158     }
1159     _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
1160                      val, sizeof(val)));
1161 }
1162 
1163 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt)
1164 {
1165     MachineState *machine = MACHINE(spapr);
1166     int chosen;
1167     const char *boot_device = machine->boot_order;
1168     char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
1169     size_t cb = 0;
1170     char *bootlist = get_boot_devices_list(&cb);
1171 
1172     _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
1173 
1174     _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
1175     _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
1176                           spapr->initrd_base));
1177     _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
1178                           spapr->initrd_base + spapr->initrd_size));
1179 
1180     if (spapr->kernel_size) {
1181         uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
1182                               cpu_to_be64(spapr->kernel_size) };
1183 
1184         _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
1185                          &kprop, sizeof(kprop)));
1186         if (spapr->kernel_le) {
1187             _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
1188         }
1189     }
1190     if (boot_menu) {
1191         _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
1192     }
1193     _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
1194     _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
1195     _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1196 
1197     if (cb && bootlist) {
1198         int i;
1199 
1200         for (i = 0; i < cb; i++) {
1201             if (bootlist[i] == '\n') {
1202                 bootlist[i] = ' ';
1203             }
1204         }
1205         _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1206     }
1207 
1208     if (boot_device && strlen(boot_device)) {
1209         _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1210     }
1211 
1212     if (!spapr->has_graphics && stdout_path) {
1213         /*
1214          * "linux,stdout-path" and "stdout" properties are deprecated by linux
1215          * kernel. New platforms should only use the "stdout-path" property. Set
1216          * the new property and continue using older property to remain
1217          * compatible with the existing firmware.
1218          */
1219         _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1220         _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
1221     }
1222 
1223     spapr_dt_ov5_platform_support(spapr, fdt, chosen);
1224 
1225     g_free(stdout_path);
1226     g_free(bootlist);
1227 }
1228 
1229 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt)
1230 {
1231     /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1232      * KVM to work under pHyp with some guest co-operation */
1233     int hypervisor;
1234     uint8_t hypercall[16];
1235 
1236     _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1237     /* indicate KVM hypercall interface */
1238     _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1239     if (kvmppc_has_cap_fixup_hcalls()) {
1240         /*
1241          * Older KVM versions with older guest kernels were broken
1242          * with the magic page, don't allow the guest to map it.
1243          */
1244         if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1245                                   sizeof(hypercall))) {
1246             _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1247                              hypercall, sizeof(hypercall)));
1248         }
1249     }
1250 }
1251 
1252 static void *spapr_build_fdt(SpaprMachineState *spapr)
1253 {
1254     MachineState *machine = MACHINE(spapr);
1255     MachineClass *mc = MACHINE_GET_CLASS(machine);
1256     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1257     int ret;
1258     void *fdt;
1259     SpaprPhbState *phb;
1260     char *buf;
1261 
1262     fdt = g_malloc0(FDT_MAX_SIZE);
1263     _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
1264 
1265     /* Root node */
1266     _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1267     _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1268     _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1269 
1270     /* Guest UUID & Name*/
1271     buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1272     _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1273     if (qemu_uuid_set) {
1274         _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1275     }
1276     g_free(buf);
1277 
1278     if (qemu_get_vm_name()) {
1279         _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1280                                 qemu_get_vm_name()));
1281     }
1282 
1283     /* Host Model & Serial Number */
1284     if (spapr->host_model) {
1285         _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model));
1286     } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) {
1287         _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1288         g_free(buf);
1289     }
1290 
1291     if (spapr->host_serial) {
1292         _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial));
1293     } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) {
1294         _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1295         g_free(buf);
1296     }
1297 
1298     _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1299     _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1300 
1301     /* /interrupt controller */
1302     spapr->irq->dt_populate(spapr, spapr_max_server_number(spapr), fdt,
1303                           PHANDLE_INTC);
1304 
1305     ret = spapr_populate_memory(spapr, fdt);
1306     if (ret < 0) {
1307         error_report("couldn't setup memory nodes in fdt");
1308         exit(1);
1309     }
1310 
1311     /* /vdevice */
1312     spapr_dt_vdevice(spapr->vio_bus, fdt);
1313 
1314     if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1315         ret = spapr_rng_populate_dt(fdt);
1316         if (ret < 0) {
1317             error_report("could not set up rng device in the fdt");
1318             exit(1);
1319         }
1320     }
1321 
1322     QLIST_FOREACH(phb, &spapr->phbs, list) {
1323         ret = spapr_dt_phb(phb, PHANDLE_INTC, fdt, spapr->irq->nr_msis, NULL);
1324         if (ret < 0) {
1325             error_report("couldn't setup PCI devices in fdt");
1326             exit(1);
1327         }
1328     }
1329 
1330     /* cpus */
1331     spapr_populate_cpus_dt_node(fdt, spapr);
1332 
1333     if (smc->dr_lmb_enabled) {
1334         _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1335     }
1336 
1337     if (mc->has_hotpluggable_cpus) {
1338         int offset = fdt_path_offset(fdt, "/cpus");
1339         ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU);
1340         if (ret < 0) {
1341             error_report("Couldn't set up CPU DR device tree properties");
1342             exit(1);
1343         }
1344     }
1345 
1346     /* /event-sources */
1347     spapr_dt_events(spapr, fdt);
1348 
1349     /* /rtas */
1350     spapr_dt_rtas(spapr, fdt);
1351 
1352     /* /chosen */
1353     spapr_dt_chosen(spapr, fdt);
1354 
1355     /* /hypervisor */
1356     if (kvm_enabled()) {
1357         spapr_dt_hypervisor(spapr, fdt);
1358     }
1359 
1360     /* Build memory reserve map */
1361     if (spapr->kernel_size) {
1362         _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1363     }
1364     if (spapr->initrd_size) {
1365         _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
1366     }
1367 
1368     /* ibm,client-architecture-support updates */
1369     ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1370     if (ret < 0) {
1371         error_report("couldn't setup CAS properties fdt");
1372         exit(1);
1373     }
1374 
1375     if (smc->dr_phb_enabled) {
1376         ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB);
1377         if (ret < 0) {
1378             error_report("Couldn't set up PHB DR device tree properties");
1379             exit(1);
1380         }
1381     }
1382 
1383     return fdt;
1384 }
1385 
1386 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1387 {
1388     return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1389 }
1390 
1391 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1392                                     PowerPCCPU *cpu)
1393 {
1394     CPUPPCState *env = &cpu->env;
1395 
1396     /* The TCG path should also be holding the BQL at this point */
1397     g_assert(qemu_mutex_iothread_locked());
1398 
1399     if (msr_pr) {
1400         hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1401         env->gpr[3] = H_PRIVILEGE;
1402     } else {
1403         env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1404     }
1405 }
1406 
1407 struct LPCRSyncState {
1408     target_ulong value;
1409     target_ulong mask;
1410 };
1411 
1412 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg)
1413 {
1414     struct LPCRSyncState *s = arg.host_ptr;
1415     PowerPCCPU *cpu = POWERPC_CPU(cs);
1416     CPUPPCState *env = &cpu->env;
1417     target_ulong lpcr;
1418 
1419     cpu_synchronize_state(cs);
1420     lpcr = env->spr[SPR_LPCR];
1421     lpcr &= ~s->mask;
1422     lpcr |= s->value;
1423     ppc_store_lpcr(cpu, lpcr);
1424 }
1425 
1426 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask)
1427 {
1428     CPUState *cs;
1429     struct LPCRSyncState s = {
1430         .value = value,
1431         .mask = mask
1432     };
1433     CPU_FOREACH(cs) {
1434         run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s));
1435     }
1436 }
1437 
1438 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry)
1439 {
1440     SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1441 
1442     /* Copy PATE1:GR into PATE0:HR */
1443     entry->dw0 = spapr->patb_entry & PATE0_HR;
1444     entry->dw1 = spapr->patb_entry;
1445 }
1446 
1447 #define HPTE(_table, _i)   (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1448 #define HPTE_VALID(_hpte)  (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1449 #define HPTE_DIRTY(_hpte)  (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1450 #define CLEAN_HPTE(_hpte)  ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1451 #define DIRTY_HPTE(_hpte)  ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1452 
1453 /*
1454  * Get the fd to access the kernel htab, re-opening it if necessary
1455  */
1456 static int get_htab_fd(SpaprMachineState *spapr)
1457 {
1458     Error *local_err = NULL;
1459 
1460     if (spapr->htab_fd >= 0) {
1461         return spapr->htab_fd;
1462     }
1463 
1464     spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
1465     if (spapr->htab_fd < 0) {
1466         error_report_err(local_err);
1467     }
1468 
1469     return spapr->htab_fd;
1470 }
1471 
1472 void close_htab_fd(SpaprMachineState *spapr)
1473 {
1474     if (spapr->htab_fd >= 0) {
1475         close(spapr->htab_fd);
1476     }
1477     spapr->htab_fd = -1;
1478 }
1479 
1480 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1481 {
1482     SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1483 
1484     return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1485 }
1486 
1487 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
1488 {
1489     SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1490 
1491     assert(kvm_enabled());
1492 
1493     if (!spapr->htab) {
1494         return 0;
1495     }
1496 
1497     return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18);
1498 }
1499 
1500 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1501                                                 hwaddr ptex, int n)
1502 {
1503     SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1504     hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1505 
1506     if (!spapr->htab) {
1507         /*
1508          * HTAB is controlled by KVM. Fetch into temporary buffer
1509          */
1510         ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1511         kvmppc_read_hptes(hptes, ptex, n);
1512         return hptes;
1513     }
1514 
1515     /*
1516      * HTAB is controlled by QEMU. Just point to the internally
1517      * accessible PTEG.
1518      */
1519     return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1520 }
1521 
1522 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1523                               const ppc_hash_pte64_t *hptes,
1524                               hwaddr ptex, int n)
1525 {
1526     SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1527 
1528     if (!spapr->htab) {
1529         g_free((void *)hptes);
1530     }
1531 
1532     /* Nothing to do for qemu managed HPT */
1533 }
1534 
1535 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
1536                       uint64_t pte0, uint64_t pte1)
1537 {
1538     SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp);
1539     hwaddr offset = ptex * HASH_PTE_SIZE_64;
1540 
1541     if (!spapr->htab) {
1542         kvmppc_write_hpte(ptex, pte0, pte1);
1543     } else {
1544         if (pte0 & HPTE64_V_VALID) {
1545             stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1546             /*
1547              * When setting valid, we write PTE1 first. This ensures
1548              * proper synchronization with the reading code in
1549              * ppc_hash64_pteg_search()
1550              */
1551             smp_wmb();
1552             stq_p(spapr->htab + offset, pte0);
1553         } else {
1554             stq_p(spapr->htab + offset, pte0);
1555             /*
1556              * When clearing it we set PTE0 first. This ensures proper
1557              * synchronization with the reading code in
1558              * ppc_hash64_pteg_search()
1559              */
1560             smp_wmb();
1561             stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1562         }
1563     }
1564 }
1565 
1566 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1567                              uint64_t pte1)
1568 {
1569     hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15;
1570     SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1571 
1572     if (!spapr->htab) {
1573         /* There should always be a hash table when this is called */
1574         error_report("spapr_hpte_set_c called with no hash table !");
1575         return;
1576     }
1577 
1578     /* The HW performs a non-atomic byte update */
1579     stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80);
1580 }
1581 
1582 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1583                              uint64_t pte1)
1584 {
1585     hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14;
1586     SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1587 
1588     if (!spapr->htab) {
1589         /* There should always be a hash table when this is called */
1590         error_report("spapr_hpte_set_r called with no hash table !");
1591         return;
1592     }
1593 
1594     /* The HW performs a non-atomic byte update */
1595     stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01);
1596 }
1597 
1598 int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1599 {
1600     int shift;
1601 
1602     /* We aim for a hash table of size 1/128 the size of RAM (rounded
1603      * up).  The PAPR recommendation is actually 1/64 of RAM size, but
1604      * that's much more than is needed for Linux guests */
1605     shift = ctz64(pow2ceil(ramsize)) - 7;
1606     shift = MAX(shift, 18); /* Minimum architected size */
1607     shift = MIN(shift, 46); /* Maximum architected size */
1608     return shift;
1609 }
1610 
1611 void spapr_free_hpt(SpaprMachineState *spapr)
1612 {
1613     g_free(spapr->htab);
1614     spapr->htab = NULL;
1615     spapr->htab_shift = 0;
1616     close_htab_fd(spapr);
1617 }
1618 
1619 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift,
1620                           Error **errp)
1621 {
1622     long rc;
1623 
1624     /* Clean up any HPT info from a previous boot */
1625     spapr_free_hpt(spapr);
1626 
1627     rc = kvmppc_reset_htab(shift);
1628     if (rc < 0) {
1629         /* kernel-side HPT needed, but couldn't allocate one */
1630         error_setg_errno(errp, errno,
1631                          "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1632                          shift);
1633         /* This is almost certainly fatal, but if the caller really
1634          * wants to carry on with shift == 0, it's welcome to try */
1635     } else if (rc > 0) {
1636         /* kernel-side HPT allocated */
1637         if (rc != shift) {
1638             error_setg(errp,
1639                        "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1640                        shift, rc);
1641         }
1642 
1643         spapr->htab_shift = shift;
1644         spapr->htab = NULL;
1645     } else {
1646         /* kernel-side HPT not needed, allocate in userspace instead */
1647         size_t size = 1ULL << shift;
1648         int i;
1649 
1650         spapr->htab = qemu_memalign(size, size);
1651         if (!spapr->htab) {
1652             error_setg_errno(errp, errno,
1653                              "Could not allocate HPT of order %d", shift);
1654             return;
1655         }
1656 
1657         memset(spapr->htab, 0, size);
1658         spapr->htab_shift = shift;
1659 
1660         for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1661             DIRTY_HPTE(HPTE(spapr->htab, i));
1662         }
1663     }
1664     /* We're setting up a hash table, so that means we're not radix */
1665     spapr->patb_entry = 0;
1666     spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT);
1667 }
1668 
1669 void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr)
1670 {
1671     int hpt_shift;
1672 
1673     if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)
1674         || (spapr->cas_reboot
1675             && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {
1676         hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1677     } else {
1678         uint64_t current_ram_size;
1679 
1680         current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
1681         hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size);
1682     }
1683     spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1684 
1685     if (spapr->vrma_adjust) {
1686         spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)),
1687                                           spapr->htab_shift);
1688     }
1689 }
1690 
1691 static int spapr_reset_drcs(Object *child, void *opaque)
1692 {
1693     SpaprDrc *drc =
1694         (SpaprDrc *) object_dynamic_cast(child,
1695                                                  TYPE_SPAPR_DR_CONNECTOR);
1696 
1697     if (drc) {
1698         spapr_drc_reset(drc);
1699     }
1700 
1701     return 0;
1702 }
1703 
1704 static void spapr_machine_reset(MachineState *machine)
1705 {
1706     SpaprMachineState *spapr = SPAPR_MACHINE(machine);
1707     PowerPCCPU *first_ppc_cpu;
1708     uint32_t rtas_limit;
1709     hwaddr rtas_addr, fdt_addr;
1710     void *fdt;
1711     int rc;
1712 
1713     spapr_caps_apply(spapr);
1714 
1715     first_ppc_cpu = POWERPC_CPU(first_cpu);
1716     if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1717         ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
1718                               spapr->max_compat_pvr)) {
1719         /*
1720          * If using KVM with radix mode available, VCPUs can be started
1721          * without a HPT because KVM will start them in radix mode.
1722          * Set the GR bit in PATE so that we know there is no HPT.
1723          */
1724         spapr->patb_entry = PATE1_GR;
1725         spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT);
1726     } else {
1727         spapr_setup_hpt_and_vrma(spapr);
1728     }
1729 
1730     /*
1731      * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
1732      * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
1733      * called from vPHB reset handler so we initialize the counter here.
1734      * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM
1735      * must be equally distant from any other node.
1736      * The final value of spapr->gpu_numa_id is going to be written to
1737      * max-associativity-domains in spapr_build_fdt().
1738      */
1739     spapr->gpu_numa_id = MAX(1, nb_numa_nodes);
1740     qemu_devices_reset();
1741 
1742     /*
1743      * If this reset wasn't generated by CAS, we should reset our
1744      * negotiated options and start from scratch
1745      */
1746     if (!spapr->cas_reboot) {
1747         spapr_ovec_cleanup(spapr->ov5_cas);
1748         spapr->ov5_cas = spapr_ovec_new();
1749 
1750         ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal);
1751     }
1752 
1753     if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
1754         spapr_irq_msi_reset(spapr);
1755     }
1756 
1757     /*
1758      * This is fixing some of the default configuration of the XIVE
1759      * devices. To be called after the reset of the machine devices.
1760      */
1761     spapr_irq_reset(spapr, &error_fatal);
1762 
1763     /*
1764      * There is no CAS under qtest. Simulate one to please the code that
1765      * depends on spapr->ov5_cas. This is especially needed to test device
1766      * unplug, so we do that before resetting the DRCs.
1767      */
1768     if (qtest_enabled()) {
1769         spapr_ovec_cleanup(spapr->ov5_cas);
1770         spapr->ov5_cas = spapr_ovec_clone(spapr->ov5);
1771     }
1772 
1773     /* DRC reset may cause a device to be unplugged. This will cause troubles
1774      * if this device is used by another device (eg, a running vhost backend
1775      * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1776      * situations, we reset DRCs after all devices have been reset.
1777      */
1778     object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL);
1779 
1780     spapr_clear_pending_events(spapr);
1781 
1782     /*
1783      * We place the device tree and RTAS just below either the top of the RMA,
1784      * or just below 2GB, whichever is lower, so that it can be
1785      * processed with 32-bit real mode code if necessary
1786      */
1787     rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1788     rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1789     fdt_addr = rtas_addr - FDT_MAX_SIZE;
1790 
1791     fdt = spapr_build_fdt(spapr);
1792 
1793     spapr_load_rtas(spapr, fdt, rtas_addr);
1794 
1795     rc = fdt_pack(fdt);
1796 
1797     /* Should only fail if we've built a corrupted tree */
1798     assert(rc == 0);
1799 
1800     if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1801         error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1802                      fdt_totalsize(fdt), FDT_MAX_SIZE);
1803         exit(1);
1804     }
1805 
1806     /* Load the fdt */
1807     qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1808     cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1809     g_free(spapr->fdt_blob);
1810     spapr->fdt_size = fdt_totalsize(fdt);
1811     spapr->fdt_initial_size = spapr->fdt_size;
1812     spapr->fdt_blob = fdt;
1813 
1814     /* Set up the entry state */
1815     spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr);
1816     first_ppc_cpu->env.gpr[5] = 0;
1817 
1818     spapr->cas_reboot = false;
1819 }
1820 
1821 static void spapr_create_nvram(SpaprMachineState *spapr)
1822 {
1823     DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1824     DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1825 
1826     if (dinfo) {
1827         qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1828                             &error_fatal);
1829     }
1830 
1831     qdev_init_nofail(dev);
1832 
1833     spapr->nvram = (struct SpaprNvram *)dev;
1834 }
1835 
1836 static void spapr_rtc_create(SpaprMachineState *spapr)
1837 {
1838     object_initialize_child(OBJECT(spapr), "rtc",
1839                             &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC,
1840                             &error_fatal, NULL);
1841     object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1842                               &error_fatal);
1843     object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1844                               "date", &error_fatal);
1845 }
1846 
1847 /* Returns whether we want to use VGA or not */
1848 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1849 {
1850     switch (vga_interface_type) {
1851     case VGA_NONE:
1852         return false;
1853     case VGA_DEVICE:
1854         return true;
1855     case VGA_STD:
1856     case VGA_VIRTIO:
1857     case VGA_CIRRUS:
1858         return pci_vga_init(pci_bus) != NULL;
1859     default:
1860         error_setg(errp,
1861                    "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1862         return false;
1863     }
1864 }
1865 
1866 static int spapr_pre_load(void *opaque)
1867 {
1868     int rc;
1869 
1870     rc = spapr_caps_pre_load(opaque);
1871     if (rc) {
1872         return rc;
1873     }
1874 
1875     return 0;
1876 }
1877 
1878 static int spapr_post_load(void *opaque, int version_id)
1879 {
1880     SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1881     int err = 0;
1882 
1883     err = spapr_caps_post_migration(spapr);
1884     if (err) {
1885         return err;
1886     }
1887 
1888     /*
1889      * In earlier versions, there was no separate qdev for the PAPR
1890      * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1891      * So when migrating from those versions, poke the incoming offset
1892      * value into the RTC device
1893      */
1894     if (version_id < 3) {
1895         err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1896         if (err) {
1897             return err;
1898         }
1899     }
1900 
1901     if (kvm_enabled() && spapr->patb_entry) {
1902         PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1903         bool radix = !!(spapr->patb_entry & PATE1_GR);
1904         bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1905 
1906         /*
1907          * Update LPCR:HR and UPRT as they may not be set properly in
1908          * the stream
1909          */
1910         spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0,
1911                             LPCR_HR | LPCR_UPRT);
1912 
1913         err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1914         if (err) {
1915             error_report("Process table config unsupported by the host");
1916             return -EINVAL;
1917         }
1918     }
1919 
1920     err = spapr_irq_post_load(spapr, version_id);
1921     if (err) {
1922         return err;
1923     }
1924 
1925     return err;
1926 }
1927 
1928 static int spapr_pre_save(void *opaque)
1929 {
1930     int rc;
1931 
1932     rc = spapr_caps_pre_save(opaque);
1933     if (rc) {
1934         return rc;
1935     }
1936 
1937     return 0;
1938 }
1939 
1940 static bool version_before_3(void *opaque, int version_id)
1941 {
1942     return version_id < 3;
1943 }
1944 
1945 static bool spapr_pending_events_needed(void *opaque)
1946 {
1947     SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1948     return !QTAILQ_EMPTY(&spapr->pending_events);
1949 }
1950 
1951 static const VMStateDescription vmstate_spapr_event_entry = {
1952     .name = "spapr_event_log_entry",
1953     .version_id = 1,
1954     .minimum_version_id = 1,
1955     .fields = (VMStateField[]) {
1956         VMSTATE_UINT32(summary, SpaprEventLogEntry),
1957         VMSTATE_UINT32(extended_length, SpaprEventLogEntry),
1958         VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0,
1959                                      NULL, extended_length),
1960         VMSTATE_END_OF_LIST()
1961     },
1962 };
1963 
1964 static const VMStateDescription vmstate_spapr_pending_events = {
1965     .name = "spapr_pending_events",
1966     .version_id = 1,
1967     .minimum_version_id = 1,
1968     .needed = spapr_pending_events_needed,
1969     .fields = (VMStateField[]) {
1970         VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1,
1971                          vmstate_spapr_event_entry, SpaprEventLogEntry, next),
1972         VMSTATE_END_OF_LIST()
1973     },
1974 };
1975 
1976 static bool spapr_ov5_cas_needed(void *opaque)
1977 {
1978     SpaprMachineState *spapr = opaque;
1979     SpaprOptionVector *ov5_mask = spapr_ovec_new();
1980     SpaprOptionVector *ov5_legacy = spapr_ovec_new();
1981     SpaprOptionVector *ov5_removed = spapr_ovec_new();
1982     bool cas_needed;
1983 
1984     /* Prior to the introduction of SpaprOptionVector, we had two option
1985      * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1986      * Both of these options encode machine topology into the device-tree
1987      * in such a way that the now-booted OS should still be able to interact
1988      * appropriately with QEMU regardless of what options were actually
1989      * negotiatied on the source side.
1990      *
1991      * As such, we can avoid migrating the CAS-negotiated options if these
1992      * are the only options available on the current machine/platform.
1993      * Since these are the only options available for pseries-2.7 and
1994      * earlier, this allows us to maintain old->new/new->old migration
1995      * compatibility.
1996      *
1997      * For QEMU 2.8+, there are additional CAS-negotiatable options available
1998      * via default pseries-2.8 machines and explicit command-line parameters.
1999      * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
2000      * of the actual CAS-negotiated values to continue working properly. For
2001      * example, availability of memory unplug depends on knowing whether
2002      * OV5_HP_EVT was negotiated via CAS.
2003      *
2004      * Thus, for any cases where the set of available CAS-negotiatable
2005      * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
2006      * include the CAS-negotiated options in the migration stream, unless
2007      * if they affect boot time behaviour only.
2008      */
2009     spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
2010     spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
2011     spapr_ovec_set(ov5_mask, OV5_DRMEM_V2);
2012 
2013     /* spapr_ovec_diff returns true if bits were removed. we avoid using
2014      * the mask itself since in the future it's possible "legacy" bits may be
2015      * removed via machine options, which could generate a false positive
2016      * that breaks migration.
2017      */
2018     spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
2019     cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
2020 
2021     spapr_ovec_cleanup(ov5_mask);
2022     spapr_ovec_cleanup(ov5_legacy);
2023     spapr_ovec_cleanup(ov5_removed);
2024 
2025     return cas_needed;
2026 }
2027 
2028 static const VMStateDescription vmstate_spapr_ov5_cas = {
2029     .name = "spapr_option_vector_ov5_cas",
2030     .version_id = 1,
2031     .minimum_version_id = 1,
2032     .needed = spapr_ov5_cas_needed,
2033     .fields = (VMStateField[]) {
2034         VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1,
2035                                  vmstate_spapr_ovec, SpaprOptionVector),
2036         VMSTATE_END_OF_LIST()
2037     },
2038 };
2039 
2040 static bool spapr_patb_entry_needed(void *opaque)
2041 {
2042     SpaprMachineState *spapr = opaque;
2043 
2044     return !!spapr->patb_entry;
2045 }
2046 
2047 static const VMStateDescription vmstate_spapr_patb_entry = {
2048     .name = "spapr_patb_entry",
2049     .version_id = 1,
2050     .minimum_version_id = 1,
2051     .needed = spapr_patb_entry_needed,
2052     .fields = (VMStateField[]) {
2053         VMSTATE_UINT64(patb_entry, SpaprMachineState),
2054         VMSTATE_END_OF_LIST()
2055     },
2056 };
2057 
2058 static bool spapr_irq_map_needed(void *opaque)
2059 {
2060     SpaprMachineState *spapr = opaque;
2061 
2062     return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr);
2063 }
2064 
2065 static const VMStateDescription vmstate_spapr_irq_map = {
2066     .name = "spapr_irq_map",
2067     .version_id = 1,
2068     .minimum_version_id = 1,
2069     .needed = spapr_irq_map_needed,
2070     .fields = (VMStateField[]) {
2071         VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr),
2072         VMSTATE_END_OF_LIST()
2073     },
2074 };
2075 
2076 static bool spapr_dtb_needed(void *opaque)
2077 {
2078     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque);
2079 
2080     return smc->update_dt_enabled;
2081 }
2082 
2083 static int spapr_dtb_pre_load(void *opaque)
2084 {
2085     SpaprMachineState *spapr = (SpaprMachineState *)opaque;
2086 
2087     g_free(spapr->fdt_blob);
2088     spapr->fdt_blob = NULL;
2089     spapr->fdt_size = 0;
2090 
2091     return 0;
2092 }
2093 
2094 static const VMStateDescription vmstate_spapr_dtb = {
2095     .name = "spapr_dtb",
2096     .version_id = 1,
2097     .minimum_version_id = 1,
2098     .needed = spapr_dtb_needed,
2099     .pre_load = spapr_dtb_pre_load,
2100     .fields = (VMStateField[]) {
2101         VMSTATE_UINT32(fdt_initial_size, SpaprMachineState),
2102         VMSTATE_UINT32(fdt_size, SpaprMachineState),
2103         VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL,
2104                                      fdt_size),
2105         VMSTATE_END_OF_LIST()
2106     },
2107 };
2108 
2109 static const VMStateDescription vmstate_spapr = {
2110     .name = "spapr",
2111     .version_id = 3,
2112     .minimum_version_id = 1,
2113     .pre_load = spapr_pre_load,
2114     .post_load = spapr_post_load,
2115     .pre_save = spapr_pre_save,
2116     .fields = (VMStateField[]) {
2117         /* used to be @next_irq */
2118         VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
2119 
2120         /* RTC offset */
2121         VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3),
2122 
2123         VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2),
2124         VMSTATE_END_OF_LIST()
2125     },
2126     .subsections = (const VMStateDescription*[]) {
2127         &vmstate_spapr_ov5_cas,
2128         &vmstate_spapr_patb_entry,
2129         &vmstate_spapr_pending_events,
2130         &vmstate_spapr_cap_htm,
2131         &vmstate_spapr_cap_vsx,
2132         &vmstate_spapr_cap_dfp,
2133         &vmstate_spapr_cap_cfpc,
2134         &vmstate_spapr_cap_sbbc,
2135         &vmstate_spapr_cap_ibs,
2136         &vmstate_spapr_cap_hpt_maxpagesize,
2137         &vmstate_spapr_irq_map,
2138         &vmstate_spapr_cap_nested_kvm_hv,
2139         &vmstate_spapr_dtb,
2140         &vmstate_spapr_cap_large_decr,
2141         &vmstate_spapr_cap_ccf_assist,
2142         NULL
2143     }
2144 };
2145 
2146 static int htab_save_setup(QEMUFile *f, void *opaque)
2147 {
2148     SpaprMachineState *spapr = opaque;
2149 
2150     /* "Iteration" header */
2151     if (!spapr->htab_shift) {
2152         qemu_put_be32(f, -1);
2153     } else {
2154         qemu_put_be32(f, spapr->htab_shift);
2155     }
2156 
2157     if (spapr->htab) {
2158         spapr->htab_save_index = 0;
2159         spapr->htab_first_pass = true;
2160     } else {
2161         if (spapr->htab_shift) {
2162             assert(kvm_enabled());
2163         }
2164     }
2165 
2166 
2167     return 0;
2168 }
2169 
2170 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr,
2171                             int chunkstart, int n_valid, int n_invalid)
2172 {
2173     qemu_put_be32(f, chunkstart);
2174     qemu_put_be16(f, n_valid);
2175     qemu_put_be16(f, n_invalid);
2176     qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
2177                     HASH_PTE_SIZE_64 * n_valid);
2178 }
2179 
2180 static void htab_save_end_marker(QEMUFile *f)
2181 {
2182     qemu_put_be32(f, 0);
2183     qemu_put_be16(f, 0);
2184     qemu_put_be16(f, 0);
2185 }
2186 
2187 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr,
2188                                  int64_t max_ns)
2189 {
2190     bool has_timeout = max_ns != -1;
2191     int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2192     int index = spapr->htab_save_index;
2193     int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2194 
2195     assert(spapr->htab_first_pass);
2196 
2197     do {
2198         int chunkstart;
2199 
2200         /* Consume invalid HPTEs */
2201         while ((index < htabslots)
2202                && !HPTE_VALID(HPTE(spapr->htab, index))) {
2203             CLEAN_HPTE(HPTE(spapr->htab, index));
2204             index++;
2205         }
2206 
2207         /* Consume valid HPTEs */
2208         chunkstart = index;
2209         while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2210                && HPTE_VALID(HPTE(spapr->htab, index))) {
2211             CLEAN_HPTE(HPTE(spapr->htab, index));
2212             index++;
2213         }
2214 
2215         if (index > chunkstart) {
2216             int n_valid = index - chunkstart;
2217 
2218             htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
2219 
2220             if (has_timeout &&
2221                 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2222                 break;
2223             }
2224         }
2225     } while ((index < htabslots) && !qemu_file_rate_limit(f));
2226 
2227     if (index >= htabslots) {
2228         assert(index == htabslots);
2229         index = 0;
2230         spapr->htab_first_pass = false;
2231     }
2232     spapr->htab_save_index = index;
2233 }
2234 
2235 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr,
2236                                 int64_t max_ns)
2237 {
2238     bool final = max_ns < 0;
2239     int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2240     int examined = 0, sent = 0;
2241     int index = spapr->htab_save_index;
2242     int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2243 
2244     assert(!spapr->htab_first_pass);
2245 
2246     do {
2247         int chunkstart, invalidstart;
2248 
2249         /* Consume non-dirty HPTEs */
2250         while ((index < htabslots)
2251                && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
2252             index++;
2253             examined++;
2254         }
2255 
2256         chunkstart = index;
2257         /* Consume valid dirty HPTEs */
2258         while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2259                && HPTE_DIRTY(HPTE(spapr->htab, index))
2260                && HPTE_VALID(HPTE(spapr->htab, index))) {
2261             CLEAN_HPTE(HPTE(spapr->htab, index));
2262             index++;
2263             examined++;
2264         }
2265 
2266         invalidstart = index;
2267         /* Consume invalid dirty HPTEs */
2268         while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
2269                && HPTE_DIRTY(HPTE(spapr->htab, index))
2270                && !HPTE_VALID(HPTE(spapr->htab, index))) {
2271             CLEAN_HPTE(HPTE(spapr->htab, index));
2272             index++;
2273             examined++;
2274         }
2275 
2276         if (index > chunkstart) {
2277             int n_valid = invalidstart - chunkstart;
2278             int n_invalid = index - invalidstart;
2279 
2280             htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
2281             sent += index - chunkstart;
2282 
2283             if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2284                 break;
2285             }
2286         }
2287 
2288         if (examined >= htabslots) {
2289             break;
2290         }
2291 
2292         if (index >= htabslots) {
2293             assert(index == htabslots);
2294             index = 0;
2295         }
2296     } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
2297 
2298     if (index >= htabslots) {
2299         assert(index == htabslots);
2300         index = 0;
2301     }
2302 
2303     spapr->htab_save_index = index;
2304 
2305     return (examined >= htabslots) && (sent == 0) ? 1 : 0;
2306 }
2307 
2308 #define MAX_ITERATION_NS    5000000 /* 5 ms */
2309 #define MAX_KVM_BUF_SIZE    2048
2310 
2311 static int htab_save_iterate(QEMUFile *f, void *opaque)
2312 {
2313     SpaprMachineState *spapr = opaque;
2314     int fd;
2315     int rc = 0;
2316 
2317     /* Iteration header */
2318     if (!spapr->htab_shift) {
2319         qemu_put_be32(f, -1);
2320         return 1;
2321     } else {
2322         qemu_put_be32(f, 0);
2323     }
2324 
2325     if (!spapr->htab) {
2326         assert(kvm_enabled());
2327 
2328         fd = get_htab_fd(spapr);
2329         if (fd < 0) {
2330             return fd;
2331         }
2332 
2333         rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
2334         if (rc < 0) {
2335             return rc;
2336         }
2337     } else  if (spapr->htab_first_pass) {
2338         htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
2339     } else {
2340         rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
2341     }
2342 
2343     htab_save_end_marker(f);
2344 
2345     return rc;
2346 }
2347 
2348 static int htab_save_complete(QEMUFile *f, void *opaque)
2349 {
2350     SpaprMachineState *spapr = opaque;
2351     int fd;
2352 
2353     /* Iteration header */
2354     if (!spapr->htab_shift) {
2355         qemu_put_be32(f, -1);
2356         return 0;
2357     } else {
2358         qemu_put_be32(f, 0);
2359     }
2360 
2361     if (!spapr->htab) {
2362         int rc;
2363 
2364         assert(kvm_enabled());
2365 
2366         fd = get_htab_fd(spapr);
2367         if (fd < 0) {
2368             return fd;
2369         }
2370 
2371         rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
2372         if (rc < 0) {
2373             return rc;
2374         }
2375     } else {
2376         if (spapr->htab_first_pass) {
2377             htab_save_first_pass(f, spapr, -1);
2378         }
2379         htab_save_later_pass(f, spapr, -1);
2380     }
2381 
2382     /* End marker */
2383     htab_save_end_marker(f);
2384 
2385     return 0;
2386 }
2387 
2388 static int htab_load(QEMUFile *f, void *opaque, int version_id)
2389 {
2390     SpaprMachineState *spapr = opaque;
2391     uint32_t section_hdr;
2392     int fd = -1;
2393     Error *local_err = NULL;
2394 
2395     if (version_id < 1 || version_id > 1) {
2396         error_report("htab_load() bad version");
2397         return -EINVAL;
2398     }
2399 
2400     section_hdr = qemu_get_be32(f);
2401 
2402     if (section_hdr == -1) {
2403         spapr_free_hpt(spapr);
2404         return 0;
2405     }
2406 
2407     if (section_hdr) {
2408         /* First section gives the htab size */
2409         spapr_reallocate_hpt(spapr, section_hdr, &local_err);
2410         if (local_err) {
2411             error_report_err(local_err);
2412             return -EINVAL;
2413         }
2414         return 0;
2415     }
2416 
2417     if (!spapr->htab) {
2418         assert(kvm_enabled());
2419 
2420         fd = kvmppc_get_htab_fd(true, 0, &local_err);
2421         if (fd < 0) {
2422             error_report_err(local_err);
2423             return fd;
2424         }
2425     }
2426 
2427     while (true) {
2428         uint32_t index;
2429         uint16_t n_valid, n_invalid;
2430 
2431         index = qemu_get_be32(f);
2432         n_valid = qemu_get_be16(f);
2433         n_invalid = qemu_get_be16(f);
2434 
2435         if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
2436             /* End of Stream */
2437             break;
2438         }
2439 
2440         if ((index + n_valid + n_invalid) >
2441             (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2442             /* Bad index in stream */
2443             error_report(
2444                 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2445                 index, n_valid, n_invalid, spapr->htab_shift);
2446             return -EINVAL;
2447         }
2448 
2449         if (spapr->htab) {
2450             if (n_valid) {
2451                 qemu_get_buffer(f, HPTE(spapr->htab, index),
2452                                 HASH_PTE_SIZE_64 * n_valid);
2453             }
2454             if (n_invalid) {
2455                 memset(HPTE(spapr->htab, index + n_valid), 0,
2456                        HASH_PTE_SIZE_64 * n_invalid);
2457             }
2458         } else {
2459             int rc;
2460 
2461             assert(fd >= 0);
2462 
2463             rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2464             if (rc < 0) {
2465                 return rc;
2466             }
2467         }
2468     }
2469 
2470     if (!spapr->htab) {
2471         assert(fd >= 0);
2472         close(fd);
2473     }
2474 
2475     return 0;
2476 }
2477 
2478 static void htab_save_cleanup(void *opaque)
2479 {
2480     SpaprMachineState *spapr = opaque;
2481 
2482     close_htab_fd(spapr);
2483 }
2484 
2485 static SaveVMHandlers savevm_htab_handlers = {
2486     .save_setup = htab_save_setup,
2487     .save_live_iterate = htab_save_iterate,
2488     .save_live_complete_precopy = htab_save_complete,
2489     .save_cleanup = htab_save_cleanup,
2490     .load_state = htab_load,
2491 };
2492 
2493 static void spapr_boot_set(void *opaque, const char *boot_device,
2494                            Error **errp)
2495 {
2496     MachineState *machine = MACHINE(opaque);
2497     machine->boot_order = g_strdup(boot_device);
2498 }
2499 
2500 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr)
2501 {
2502     MachineState *machine = MACHINE(spapr);
2503     uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2504     uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2505     int i;
2506 
2507     for (i = 0; i < nr_lmbs; i++) {
2508         uint64_t addr;
2509 
2510         addr = i * lmb_size + machine->device_memory->base;
2511         spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2512                                addr / lmb_size);
2513     }
2514 }
2515 
2516 /*
2517  * If RAM size, maxmem size and individual node mem sizes aren't aligned
2518  * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2519  * since we can't support such unaligned sizes with DRCONF_MEMORY.
2520  */
2521 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2522 {
2523     int i;
2524 
2525     if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2526         error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2527                    " is not aligned to %" PRIu64 " MiB",
2528                    machine->ram_size,
2529                    SPAPR_MEMORY_BLOCK_SIZE / MiB);
2530         return;
2531     }
2532 
2533     if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2534         error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2535                    " is not aligned to %" PRIu64 " MiB",
2536                    machine->ram_size,
2537                    SPAPR_MEMORY_BLOCK_SIZE / MiB);
2538         return;
2539     }
2540 
2541     for (i = 0; i < nb_numa_nodes; i++) {
2542         if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2543             error_setg(errp,
2544                        "Node %d memory size 0x%" PRIx64
2545                        " is not aligned to %" PRIu64 " MiB",
2546                        i, numa_info[i].node_mem,
2547                        SPAPR_MEMORY_BLOCK_SIZE / MiB);
2548             return;
2549         }
2550     }
2551 }
2552 
2553 /* find cpu slot in machine->possible_cpus by core_id */
2554 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2555 {
2556     int index = id / ms->smp.threads;
2557 
2558     if (index >= ms->possible_cpus->len) {
2559         return NULL;
2560     }
2561     if (idx) {
2562         *idx = index;
2563     }
2564     return &ms->possible_cpus->cpus[index];
2565 }
2566 
2567 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp)
2568 {
2569     MachineState *ms = MACHINE(spapr);
2570     Error *local_err = NULL;
2571     bool vsmt_user = !!spapr->vsmt;
2572     int kvm_smt = kvmppc_smt_threads();
2573     int ret;
2574     unsigned int smp_threads = ms->smp.threads;
2575 
2576     if (!kvm_enabled() && (smp_threads > 1)) {
2577         error_setg(&local_err, "TCG cannot support more than 1 thread/core "
2578                      "on a pseries machine");
2579         goto out;
2580     }
2581     if (!is_power_of_2(smp_threads)) {
2582         error_setg(&local_err, "Cannot support %d threads/core on a pseries "
2583                      "machine because it must be a power of 2", smp_threads);
2584         goto out;
2585     }
2586 
2587     /* Detemine the VSMT mode to use: */
2588     if (vsmt_user) {
2589         if (spapr->vsmt < smp_threads) {
2590             error_setg(&local_err, "Cannot support VSMT mode %d"
2591                          " because it must be >= threads/core (%d)",
2592                          spapr->vsmt, smp_threads);
2593             goto out;
2594         }
2595         /* In this case, spapr->vsmt has been set by the command line */
2596     } else {
2597         /*
2598          * Default VSMT value is tricky, because we need it to be as
2599          * consistent as possible (for migration), but this requires
2600          * changing it for at least some existing cases.  We pick 8 as
2601          * the value that we'd get with KVM on POWER8, the
2602          * overwhelmingly common case in production systems.
2603          */
2604         spapr->vsmt = MAX(8, smp_threads);
2605     }
2606 
2607     /* KVM: If necessary, set the SMT mode: */
2608     if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2609         ret = kvmppc_set_smt_threads(spapr->vsmt);
2610         if (ret) {
2611             /* Looks like KVM isn't able to change VSMT mode */
2612             error_setg(&local_err,
2613                        "Failed to set KVM's VSMT mode to %d (errno %d)",
2614                        spapr->vsmt, ret);
2615             /* We can live with that if the default one is big enough
2616              * for the number of threads, and a submultiple of the one
2617              * we want.  In this case we'll waste some vcpu ids, but
2618              * behaviour will be correct */
2619             if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) {
2620                 warn_report_err(local_err);
2621                 local_err = NULL;
2622                 goto out;
2623             } else {
2624                 if (!vsmt_user) {
2625                     error_append_hint(&local_err,
2626                                       "On PPC, a VM with %d threads/core"
2627                                       " on a host with %d threads/core"
2628                                       " requires the use of VSMT mode %d.\n",
2629                                       smp_threads, kvm_smt, spapr->vsmt);
2630                 }
2631                 kvmppc_hint_smt_possible(&local_err);
2632                 goto out;
2633             }
2634         }
2635     }
2636     /* else TCG: nothing to do currently */
2637 out:
2638     error_propagate(errp, local_err);
2639 }
2640 
2641 static void spapr_init_cpus(SpaprMachineState *spapr)
2642 {
2643     MachineState *machine = MACHINE(spapr);
2644     MachineClass *mc = MACHINE_GET_CLASS(machine);
2645     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2646     const char *type = spapr_get_cpu_core_type(machine->cpu_type);
2647     const CPUArchIdList *possible_cpus;
2648     unsigned int smp_cpus = machine->smp.cpus;
2649     unsigned int smp_threads = machine->smp.threads;
2650     unsigned int max_cpus = machine->smp.max_cpus;
2651     int boot_cores_nr = smp_cpus / smp_threads;
2652     int i;
2653 
2654     possible_cpus = mc->possible_cpu_arch_ids(machine);
2655     if (mc->has_hotpluggable_cpus) {
2656         if (smp_cpus % smp_threads) {
2657             error_report("smp_cpus (%u) must be multiple of threads (%u)",
2658                          smp_cpus, smp_threads);
2659             exit(1);
2660         }
2661         if (max_cpus % smp_threads) {
2662             error_report("max_cpus (%u) must be multiple of threads (%u)",
2663                          max_cpus, smp_threads);
2664             exit(1);
2665         }
2666     } else {
2667         if (max_cpus != smp_cpus) {
2668             error_report("This machine version does not support CPU hotplug");
2669             exit(1);
2670         }
2671         boot_cores_nr = possible_cpus->len;
2672     }
2673 
2674     if (smc->pre_2_10_has_unused_icps) {
2675         int i;
2676 
2677         for (i = 0; i < spapr_max_server_number(spapr); i++) {
2678             /* Dummy entries get deregistered when real ICPState objects
2679              * are registered during CPU core hotplug.
2680              */
2681             pre_2_10_vmstate_register_dummy_icp(i);
2682         }
2683     }
2684 
2685     for (i = 0; i < possible_cpus->len; i++) {
2686         int core_id = i * smp_threads;
2687 
2688         if (mc->has_hotpluggable_cpus) {
2689             spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2690                                    spapr_vcpu_id(spapr, core_id));
2691         }
2692 
2693         if (i < boot_cores_nr) {
2694             Object *core  = object_new(type);
2695             int nr_threads = smp_threads;
2696 
2697             /* Handle the partially filled core for older machine types */
2698             if ((i + 1) * smp_threads >= smp_cpus) {
2699                 nr_threads = smp_cpus - i * smp_threads;
2700             }
2701 
2702             object_property_set_int(core, nr_threads, "nr-threads",
2703                                     &error_fatal);
2704             object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2705                                     &error_fatal);
2706             object_property_set_bool(core, true, "realized", &error_fatal);
2707 
2708             object_unref(core);
2709         }
2710     }
2711 }
2712 
2713 static PCIHostState *spapr_create_default_phb(void)
2714 {
2715     DeviceState *dev;
2716 
2717     dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
2718     qdev_prop_set_uint32(dev, "index", 0);
2719     qdev_init_nofail(dev);
2720 
2721     return PCI_HOST_BRIDGE(dev);
2722 }
2723 
2724 /* pSeries LPAR / sPAPR hardware init */
2725 static void spapr_machine_init(MachineState *machine)
2726 {
2727     SpaprMachineState *spapr = SPAPR_MACHINE(machine);
2728     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2729     const char *kernel_filename = machine->kernel_filename;
2730     const char *initrd_filename = machine->initrd_filename;
2731     PCIHostState *phb;
2732     int i;
2733     MemoryRegion *sysmem = get_system_memory();
2734     MemoryRegion *ram = g_new(MemoryRegion, 1);
2735     hwaddr node0_size = spapr_node0_size(machine);
2736     long load_limit, fw_size;
2737     char *filename;
2738     Error *resize_hpt_err = NULL;
2739 
2740     msi_nonbroken = true;
2741 
2742     QLIST_INIT(&spapr->phbs);
2743     QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2744 
2745     /* Determine capabilities to run with */
2746     spapr_caps_init(spapr);
2747 
2748     kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2749     if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2750         /*
2751          * If the user explicitly requested a mode we should either
2752          * supply it, or fail completely (which we do below).  But if
2753          * it's not set explicitly, we reset our mode to something
2754          * that works
2755          */
2756         if (resize_hpt_err) {
2757             spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2758             error_free(resize_hpt_err);
2759             resize_hpt_err = NULL;
2760         } else {
2761             spapr->resize_hpt = smc->resize_hpt_default;
2762         }
2763     }
2764 
2765     assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2766 
2767     if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2768         /*
2769          * User requested HPT resize, but this host can't supply it.  Bail out
2770          */
2771         error_report_err(resize_hpt_err);
2772         exit(1);
2773     }
2774 
2775     spapr->rma_size = node0_size;
2776 
2777     /* With KVM, we don't actually know whether KVM supports an
2778      * unbounded RMA (PR KVM) or is limited by the hash table size
2779      * (HV KVM using VRMA), so we always assume the latter
2780      *
2781      * In that case, we also limit the initial allocations for RTAS
2782      * etc... to 256M since we have no way to know what the VRMA size
2783      * is going to be as it depends on the size of the hash table
2784      * which isn't determined yet.
2785      */
2786     if (kvm_enabled()) {
2787         spapr->vrma_adjust = 1;
2788         spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2789     }
2790 
2791     /* Actually we don't support unbounded RMA anymore since we added
2792      * proper emulation of HV mode. The max we can get is 16G which
2793      * also happens to be what we configure for PAPR mode so make sure
2794      * we don't do anything bigger than that
2795      */
2796     spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2797 
2798     if (spapr->rma_size > node0_size) {
2799         error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2800                      spapr->rma_size);
2801         exit(1);
2802     }
2803 
2804     /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2805     load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2806 
2807     /*
2808      * VSMT must be set in order to be able to compute VCPU ids, ie to
2809      * call spapr_max_server_number() or spapr_vcpu_id().
2810      */
2811     spapr_set_vsmt_mode(spapr, &error_fatal);
2812 
2813     /* Set up Interrupt Controller before we create the VCPUs */
2814     spapr_irq_init(spapr, &error_fatal);
2815 
2816     /* Set up containers for ibm,client-architecture-support negotiated options
2817      */
2818     spapr->ov5 = spapr_ovec_new();
2819     spapr->ov5_cas = spapr_ovec_new();
2820 
2821     if (smc->dr_lmb_enabled) {
2822         spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2823         spapr_validate_node_memory(machine, &error_fatal);
2824     }
2825 
2826     spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2827 
2828     /* advertise support for dedicated HP event source to guests */
2829     if (spapr->use_hotplug_event_source) {
2830         spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2831     }
2832 
2833     /* advertise support for HPT resizing */
2834     if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2835         spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2836     }
2837 
2838     /* advertise support for ibm,dyamic-memory-v2 */
2839     spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2);
2840 
2841     /* advertise XIVE on POWER9 machines */
2842     if (spapr->irq->ov5 & (SPAPR_OV5_XIVE_EXPLOIT | SPAPR_OV5_XIVE_BOTH)) {
2843         spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT);
2844     }
2845 
2846     /* init CPUs */
2847     spapr_init_cpus(spapr);
2848 
2849     if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2850         ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
2851                               spapr->max_compat_pvr)) {
2852         /* KVM and TCG always allow GTSE with radix... */
2853         spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2854     }
2855     /* ... but not with hash (currently). */
2856 
2857     if (kvm_enabled()) {
2858         /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2859         kvmppc_enable_logical_ci_hcalls();
2860         kvmppc_enable_set_mode_hcall();
2861 
2862         /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2863         kvmppc_enable_clear_ref_mod_hcalls();
2864 
2865         /* Enable H_PAGE_INIT */
2866         kvmppc_enable_h_page_init();
2867     }
2868 
2869     /* allocate RAM */
2870     memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2871                                          machine->ram_size);
2872     memory_region_add_subregion(sysmem, 0, ram);
2873 
2874     /* always allocate the device memory information */
2875     machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
2876 
2877     /* initialize hotplug memory address space */
2878     if (machine->ram_size < machine->maxram_size) {
2879         ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
2880         /*
2881          * Limit the number of hotpluggable memory slots to half the number
2882          * slots that KVM supports, leaving the other half for PCI and other
2883          * devices. However ensure that number of slots doesn't drop below 32.
2884          */
2885         int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2886                            SPAPR_MAX_RAM_SLOTS;
2887 
2888         if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2889             max_memslots = SPAPR_MAX_RAM_SLOTS;
2890         }
2891         if (machine->ram_slots > max_memslots) {
2892             error_report("Specified number of memory slots %"
2893                          PRIu64" exceeds max supported %d",
2894                          machine->ram_slots, max_memslots);
2895             exit(1);
2896         }
2897 
2898         machine->device_memory->base = ROUND_UP(machine->ram_size,
2899                                                 SPAPR_DEVICE_MEM_ALIGN);
2900         memory_region_init(&machine->device_memory->mr, OBJECT(spapr),
2901                            "device-memory", device_mem_size);
2902         memory_region_add_subregion(sysmem, machine->device_memory->base,
2903                                     &machine->device_memory->mr);
2904     }
2905 
2906     if (smc->dr_lmb_enabled) {
2907         spapr_create_lmb_dr_connectors(spapr);
2908     }
2909 
2910     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
2911     if (!filename) {
2912         error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2913         exit(1);
2914     }
2915     spapr->rtas_size = get_image_size(filename);
2916     if (spapr->rtas_size < 0) {
2917         error_report("Could not get size of LPAR rtas '%s'", filename);
2918         exit(1);
2919     }
2920     spapr->rtas_blob = g_malloc(spapr->rtas_size);
2921     if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2922         error_report("Could not load LPAR rtas '%s'", filename);
2923         exit(1);
2924     }
2925     if (spapr->rtas_size > RTAS_MAX_SIZE) {
2926         error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2927                      (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2928         exit(1);
2929     }
2930     g_free(filename);
2931 
2932     /* Set up RTAS event infrastructure */
2933     spapr_events_init(spapr);
2934 
2935     /* Set up the RTC RTAS interfaces */
2936     spapr_rtc_create(spapr);
2937 
2938     /* Set up VIO bus */
2939     spapr->vio_bus = spapr_vio_bus_init();
2940 
2941     for (i = 0; i < serial_max_hds(); i++) {
2942         if (serial_hd(i)) {
2943             spapr_vty_create(spapr->vio_bus, serial_hd(i));
2944         }
2945     }
2946 
2947     /* We always have at least the nvram device on VIO */
2948     spapr_create_nvram(spapr);
2949 
2950     /*
2951      * Setup hotplug / dynamic-reconfiguration connectors. top-level
2952      * connectors (described in root DT node's "ibm,drc-types" property)
2953      * are pre-initialized here. additional child connectors (such as
2954      * connectors for a PHBs PCI slots) are added as needed during their
2955      * parent's realization.
2956      */
2957     if (smc->dr_phb_enabled) {
2958         for (i = 0; i < SPAPR_MAX_PHBS; i++) {
2959             spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i);
2960         }
2961     }
2962 
2963     /* Set up PCI */
2964     spapr_pci_rtas_init();
2965 
2966     phb = spapr_create_default_phb();
2967 
2968     for (i = 0; i < nb_nics; i++) {
2969         NICInfo *nd = &nd_table[i];
2970 
2971         if (!nd->model) {
2972             nd->model = g_strdup("spapr-vlan");
2973         }
2974 
2975         if (g_str_equal(nd->model, "spapr-vlan") ||
2976             g_str_equal(nd->model, "ibmveth")) {
2977             spapr_vlan_create(spapr->vio_bus, nd);
2978         } else {
2979             pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2980         }
2981     }
2982 
2983     for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2984         spapr_vscsi_create(spapr->vio_bus);
2985     }
2986 
2987     /* Graphics */
2988     if (spapr_vga_init(phb->bus, &error_fatal)) {
2989         spapr->has_graphics = true;
2990         machine->usb |= defaults_enabled() && !machine->usb_disabled;
2991     }
2992 
2993     if (machine->usb) {
2994         if (smc->use_ohci_by_default) {
2995             pci_create_simple(phb->bus, -1, "pci-ohci");
2996         } else {
2997             pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2998         }
2999 
3000         if (spapr->has_graphics) {
3001             USBBus *usb_bus = usb_bus_find(-1);
3002 
3003             usb_create_simple(usb_bus, "usb-kbd");
3004             usb_create_simple(usb_bus, "usb-mouse");
3005         }
3006     }
3007 
3008     if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) {
3009         error_report(
3010             "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
3011             MIN_RMA_SLOF);
3012         exit(1);
3013     }
3014 
3015     if (kernel_filename) {
3016         uint64_t lowaddr = 0;
3017 
3018         spapr->kernel_size = load_elf(kernel_filename, NULL,
3019                                       translate_kernel_address, NULL,
3020                                       NULL, &lowaddr, NULL, 1,
3021                                       PPC_ELF_MACHINE, 0, 0);
3022         if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
3023             spapr->kernel_size = load_elf(kernel_filename, NULL,
3024                                           translate_kernel_address, NULL, NULL,
3025                                           &lowaddr, NULL, 0, PPC_ELF_MACHINE,
3026                                           0, 0);
3027             spapr->kernel_le = spapr->kernel_size > 0;
3028         }
3029         if (spapr->kernel_size < 0) {
3030             error_report("error loading %s: %s", kernel_filename,
3031                          load_elf_strerror(spapr->kernel_size));
3032             exit(1);
3033         }
3034 
3035         /* load initrd */
3036         if (initrd_filename) {
3037             /* Try to locate the initrd in the gap between the kernel
3038              * and the firmware. Add a bit of space just in case
3039              */
3040             spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
3041                                   + 0x1ffff) & ~0xffff;
3042             spapr->initrd_size = load_image_targphys(initrd_filename,
3043                                                      spapr->initrd_base,
3044                                                      load_limit
3045                                                      - spapr->initrd_base);
3046             if (spapr->initrd_size < 0) {
3047                 error_report("could not load initial ram disk '%s'",
3048                              initrd_filename);
3049                 exit(1);
3050             }
3051         }
3052     }
3053 
3054     if (bios_name == NULL) {
3055         bios_name = FW_FILE_NAME;
3056     }
3057     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
3058     if (!filename) {
3059         error_report("Could not find LPAR firmware '%s'", bios_name);
3060         exit(1);
3061     }
3062     fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
3063     if (fw_size <= 0) {
3064         error_report("Could not load LPAR firmware '%s'", filename);
3065         exit(1);
3066     }
3067     g_free(filename);
3068 
3069     /* FIXME: Should register things through the MachineState's qdev
3070      * interface, this is a legacy from the sPAPREnvironment structure
3071      * which predated MachineState but had a similar function */
3072     vmstate_register(NULL, 0, &vmstate_spapr, spapr);
3073     register_savevm_live(NULL, "spapr/htab", -1, 1,
3074                          &savevm_htab_handlers, spapr);
3075 
3076     qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine),
3077                              &error_fatal);
3078 
3079     qemu_register_boot_set(spapr_boot_set, spapr);
3080 
3081     if (kvm_enabled()) {
3082         /* to stop and start vmclock */
3083         qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
3084                                          &spapr->tb);
3085 
3086         kvmppc_spapr_enable_inkernel_multitce();
3087     }
3088 }
3089 
3090 static int spapr_kvm_type(MachineState *machine, const char *vm_type)
3091 {
3092     if (!vm_type) {
3093         return 0;
3094     }
3095 
3096     if (!strcmp(vm_type, "HV")) {
3097         return 1;
3098     }
3099 
3100     if (!strcmp(vm_type, "PR")) {
3101         return 2;
3102     }
3103 
3104     error_report("Unknown kvm-type specified '%s'", vm_type);
3105     exit(1);
3106 }
3107 
3108 /*
3109  * Implementation of an interface to adjust firmware path
3110  * for the bootindex property handling.
3111  */
3112 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
3113                                    DeviceState *dev)
3114 {
3115 #define CAST(type, obj, name) \
3116     ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3117     SCSIDevice *d = CAST(SCSIDevice,  dev, TYPE_SCSI_DEVICE);
3118     SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
3119     VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
3120 
3121     if (d) {
3122         void *spapr = CAST(void, bus->parent, "spapr-vscsi");
3123         VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
3124         USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
3125 
3126         if (spapr) {
3127             /*
3128              * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
3129              * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
3130              * 0x8000 | (target << 8) | (bus << 5) | lun
3131              * (see the "Logical unit addressing format" table in SAM5)
3132              */
3133             unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun;
3134             return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3135                                    (uint64_t)id << 48);
3136         } else if (virtio) {
3137             /*
3138              * We use SRP luns of the form 01000000 | (target << 8) | lun
3139              * in the top 32 bits of the 64-bit LUN
3140              * Note: the quote above is from SLOF and it is wrong,
3141              * the actual binding is:
3142              * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
3143              */
3144             unsigned id = 0x1000000 | (d->id << 16) | d->lun;
3145             if (d->lun >= 256) {
3146                 /* Use the LUN "flat space addressing method" */
3147                 id |= 0x4000;
3148             }
3149             return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3150                                    (uint64_t)id << 32);
3151         } else if (usb) {
3152             /*
3153              * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3154              * in the top 32 bits of the 64-bit LUN
3155              */
3156             unsigned usb_port = atoi(usb->port->path);
3157             unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
3158             return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3159                                    (uint64_t)id << 32);
3160         }
3161     }
3162 
3163     /*
3164      * SLOF probes the USB devices, and if it recognizes that the device is a
3165      * storage device, it changes its name to "storage" instead of "usb-host",
3166      * and additionally adds a child node for the SCSI LUN, so the correct
3167      * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3168      */
3169     if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
3170         USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
3171         if (usb_host_dev_is_scsi_storage(usbdev)) {
3172             return g_strdup_printf("storage@%s/disk", usbdev->port->path);
3173         }
3174     }
3175 
3176     if (phb) {
3177         /* Replace "pci" with "pci@800000020000000" */
3178         return g_strdup_printf("pci@%"PRIX64, phb->buid);
3179     }
3180 
3181     if (vsc) {
3182         /* Same logic as virtio above */
3183         unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
3184         return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
3185     }
3186 
3187     if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
3188         /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3189         PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
3190         return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
3191     }
3192 
3193     return NULL;
3194 }
3195 
3196 static char *spapr_get_kvm_type(Object *obj, Error **errp)
3197 {
3198     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3199 
3200     return g_strdup(spapr->kvm_type);
3201 }
3202 
3203 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
3204 {
3205     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3206 
3207     g_free(spapr->kvm_type);
3208     spapr->kvm_type = g_strdup(value);
3209 }
3210 
3211 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
3212 {
3213     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3214 
3215     return spapr->use_hotplug_event_source;
3216 }
3217 
3218 static void spapr_set_modern_hotplug_events(Object *obj, bool value,
3219                                             Error **errp)
3220 {
3221     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3222 
3223     spapr->use_hotplug_event_source = value;
3224 }
3225 
3226 static bool spapr_get_msix_emulation(Object *obj, Error **errp)
3227 {
3228     return true;
3229 }
3230 
3231 static char *spapr_get_resize_hpt(Object *obj, Error **errp)
3232 {
3233     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3234 
3235     switch (spapr->resize_hpt) {
3236     case SPAPR_RESIZE_HPT_DEFAULT:
3237         return g_strdup("default");
3238     case SPAPR_RESIZE_HPT_DISABLED:
3239         return g_strdup("disabled");
3240     case SPAPR_RESIZE_HPT_ENABLED:
3241         return g_strdup("enabled");
3242     case SPAPR_RESIZE_HPT_REQUIRED:
3243         return g_strdup("required");
3244     }
3245     g_assert_not_reached();
3246 }
3247 
3248 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
3249 {
3250     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3251 
3252     if (strcmp(value, "default") == 0) {
3253         spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
3254     } else if (strcmp(value, "disabled") == 0) {
3255         spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
3256     } else if (strcmp(value, "enabled") == 0) {
3257         spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
3258     } else if (strcmp(value, "required") == 0) {
3259         spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
3260     } else {
3261         error_setg(errp, "Bad value for \"resize-hpt\" property");
3262     }
3263 }
3264 
3265 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name,
3266                                    void *opaque, Error **errp)
3267 {
3268     visit_type_uint32(v, name, (uint32_t *)opaque, errp);
3269 }
3270 
3271 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name,
3272                                    void *opaque, Error **errp)
3273 {
3274     visit_type_uint32(v, name, (uint32_t *)opaque, errp);
3275 }
3276 
3277 static char *spapr_get_ic_mode(Object *obj, Error **errp)
3278 {
3279     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3280 
3281     if (spapr->irq == &spapr_irq_xics_legacy) {
3282         return g_strdup("legacy");
3283     } else if (spapr->irq == &spapr_irq_xics) {
3284         return g_strdup("xics");
3285     } else if (spapr->irq == &spapr_irq_xive) {
3286         return g_strdup("xive");
3287     } else if (spapr->irq == &spapr_irq_dual) {
3288         return g_strdup("dual");
3289     }
3290     g_assert_not_reached();
3291 }
3292 
3293 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp)
3294 {
3295     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3296 
3297     if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
3298         error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3299         return;
3300     }
3301 
3302     /* The legacy IRQ backend can not be set */
3303     if (strcmp(value, "xics") == 0) {
3304         spapr->irq = &spapr_irq_xics;
3305     } else if (strcmp(value, "xive") == 0) {
3306         spapr->irq = &spapr_irq_xive;
3307     } else if (strcmp(value, "dual") == 0) {
3308         spapr->irq = &spapr_irq_dual;
3309     } else {
3310         error_setg(errp, "Bad value for \"ic-mode\" property");
3311     }
3312 }
3313 
3314 static char *spapr_get_host_model(Object *obj, Error **errp)
3315 {
3316     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3317 
3318     return g_strdup(spapr->host_model);
3319 }
3320 
3321 static void spapr_set_host_model(Object *obj, const char *value, Error **errp)
3322 {
3323     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3324 
3325     g_free(spapr->host_model);
3326     spapr->host_model = g_strdup(value);
3327 }
3328 
3329 static char *spapr_get_host_serial(Object *obj, Error **errp)
3330 {
3331     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3332 
3333     return g_strdup(spapr->host_serial);
3334 }
3335 
3336 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp)
3337 {
3338     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3339 
3340     g_free(spapr->host_serial);
3341     spapr->host_serial = g_strdup(value);
3342 }
3343 
3344 static void spapr_instance_init(Object *obj)
3345 {
3346     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3347     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3348 
3349     spapr->htab_fd = -1;
3350     spapr->use_hotplug_event_source = true;
3351     object_property_add_str(obj, "kvm-type",
3352                             spapr_get_kvm_type, spapr_set_kvm_type, NULL);
3353     object_property_set_description(obj, "kvm-type",
3354                                     "Specifies the KVM virtualization mode (HV, PR)",
3355                                     NULL);
3356     object_property_add_bool(obj, "modern-hotplug-events",
3357                             spapr_get_modern_hotplug_events,
3358                             spapr_set_modern_hotplug_events,
3359                             NULL);
3360     object_property_set_description(obj, "modern-hotplug-events",
3361                                     "Use dedicated hotplug event mechanism in"
3362                                     " place of standard EPOW events when possible"
3363                                     " (required for memory hot-unplug support)",
3364                                     NULL);
3365     ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
3366                             "Maximum permitted CPU compatibility mode",
3367                             &error_fatal);
3368 
3369     object_property_add_str(obj, "resize-hpt",
3370                             spapr_get_resize_hpt, spapr_set_resize_hpt, NULL);
3371     object_property_set_description(obj, "resize-hpt",
3372                                     "Resizing of the Hash Page Table (enabled, disabled, required)",
3373                                     NULL);
3374     object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt,
3375                         spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort);
3376     object_property_set_description(obj, "vsmt",
3377                                     "Virtual SMT: KVM behaves as if this were"
3378                                     " the host's SMT mode", &error_abort);
3379     object_property_add_bool(obj, "vfio-no-msix-emulation",
3380                              spapr_get_msix_emulation, NULL, NULL);
3381 
3382     /* The machine class defines the default interrupt controller mode */
3383     spapr->irq = smc->irq;
3384     object_property_add_str(obj, "ic-mode", spapr_get_ic_mode,
3385                             spapr_set_ic_mode, NULL);
3386     object_property_set_description(obj, "ic-mode",
3387                  "Specifies the interrupt controller mode (xics, xive, dual)",
3388                  NULL);
3389 
3390     object_property_add_str(obj, "host-model",
3391         spapr_get_host_model, spapr_set_host_model,
3392         &error_abort);
3393     object_property_set_description(obj, "host-model",
3394         "Host model to advertise in guest device tree", &error_abort);
3395     object_property_add_str(obj, "host-serial",
3396         spapr_get_host_serial, spapr_set_host_serial,
3397         &error_abort);
3398     object_property_set_description(obj, "host-serial",
3399         "Host serial number to advertise in guest device tree", &error_abort);
3400 }
3401 
3402 static void spapr_machine_finalizefn(Object *obj)
3403 {
3404     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3405 
3406     g_free(spapr->kvm_type);
3407 }
3408 
3409 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
3410 {
3411     cpu_synchronize_state(cs);
3412     ppc_cpu_do_system_reset(cs);
3413 }
3414 
3415 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
3416 {
3417     CPUState *cs;
3418 
3419     CPU_FOREACH(cs) {
3420         async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
3421     }
3422 }
3423 
3424 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3425                           void *fdt, int *fdt_start_offset, Error **errp)
3426 {
3427     uint64_t addr;
3428     uint32_t node;
3429 
3430     addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE;
3431     node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP,
3432                                     &error_abort);
3433     *fdt_start_offset = spapr_populate_memory_node(fdt, node, addr,
3434                                                    SPAPR_MEMORY_BLOCK_SIZE);
3435     return 0;
3436 }
3437 
3438 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
3439                            bool dedicated_hp_event_source, Error **errp)
3440 {
3441     SpaprDrc *drc;
3442     uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
3443     int i;
3444     uint64_t addr = addr_start;
3445     bool hotplugged = spapr_drc_hotplugged(dev);
3446     Error *local_err = NULL;
3447 
3448     for (i = 0; i < nr_lmbs; i++) {
3449         drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3450                               addr / SPAPR_MEMORY_BLOCK_SIZE);
3451         g_assert(drc);
3452 
3453         spapr_drc_attach(drc, dev, &local_err);
3454         if (local_err) {
3455             while (addr > addr_start) {
3456                 addr -= SPAPR_MEMORY_BLOCK_SIZE;
3457                 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3458                                       addr / SPAPR_MEMORY_BLOCK_SIZE);
3459                 spapr_drc_detach(drc);
3460             }
3461             error_propagate(errp, local_err);
3462             return;
3463         }
3464         if (!hotplugged) {
3465             spapr_drc_reset(drc);
3466         }
3467         addr += SPAPR_MEMORY_BLOCK_SIZE;
3468     }
3469     /* send hotplug notification to the
3470      * guest only in case of hotplugged memory
3471      */
3472     if (hotplugged) {
3473         if (dedicated_hp_event_source) {
3474             drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3475                                   addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3476             spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3477                                                    nr_lmbs,
3478                                                    spapr_drc_index(drc));
3479         } else {
3480             spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
3481                                            nr_lmbs);
3482         }
3483     }
3484 }
3485 
3486 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3487                               Error **errp)
3488 {
3489     Error *local_err = NULL;
3490     SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev);
3491     PCDIMMDevice *dimm = PC_DIMM(dev);
3492     uint64_t size, addr;
3493 
3494     size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort);
3495 
3496     pc_dimm_plug(dimm, MACHINE(ms), &local_err);
3497     if (local_err) {
3498         goto out;
3499     }
3500 
3501     addr = object_property_get_uint(OBJECT(dimm),
3502                                     PC_DIMM_ADDR_PROP, &local_err);
3503     if (local_err) {
3504         goto out_unplug;
3505     }
3506 
3507     spapr_add_lmbs(dev, addr, size, spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
3508                    &local_err);
3509     if (local_err) {
3510         goto out_unplug;
3511     }
3512 
3513     return;
3514 
3515 out_unplug:
3516     pc_dimm_unplug(dimm, MACHINE(ms));
3517 out:
3518     error_propagate(errp, local_err);
3519 }
3520 
3521 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3522                                   Error **errp)
3523 {
3524     const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev);
3525     SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3526     PCDIMMDevice *dimm = PC_DIMM(dev);
3527     Error *local_err = NULL;
3528     uint64_t size;
3529     Object *memdev;
3530     hwaddr pagesize;
3531 
3532     if (!smc->dr_lmb_enabled) {
3533         error_setg(errp, "Memory hotplug not supported for this machine");
3534         return;
3535     }
3536 
3537     size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err);
3538     if (local_err) {
3539         error_propagate(errp, local_err);
3540         return;
3541     }
3542 
3543     if (size % SPAPR_MEMORY_BLOCK_SIZE) {
3544         error_setg(errp, "Hotplugged memory size must be a multiple of "
3545                       "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB);
3546         return;
3547     }
3548 
3549     memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP,
3550                                       &error_abort);
3551     pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev));
3552     spapr_check_pagesize(spapr, pagesize, &local_err);
3553     if (local_err) {
3554         error_propagate(errp, local_err);
3555         return;
3556     }
3557 
3558     pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp);
3559 }
3560 
3561 struct SpaprDimmState {
3562     PCDIMMDevice *dimm;
3563     uint32_t nr_lmbs;
3564     QTAILQ_ENTRY(SpaprDimmState) next;
3565 };
3566 
3567 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s,
3568                                                        PCDIMMDevice *dimm)
3569 {
3570     SpaprDimmState *dimm_state = NULL;
3571 
3572     QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) {
3573         if (dimm_state->dimm == dimm) {
3574             break;
3575         }
3576     }
3577     return dimm_state;
3578 }
3579 
3580 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr,
3581                                                       uint32_t nr_lmbs,
3582                                                       PCDIMMDevice *dimm)
3583 {
3584     SpaprDimmState *ds = NULL;
3585 
3586     /*
3587      * If this request is for a DIMM whose removal had failed earlier
3588      * (due to guest's refusal to remove the LMBs), we would have this
3589      * dimm already in the pending_dimm_unplugs list. In that
3590      * case don't add again.
3591      */
3592     ds = spapr_pending_dimm_unplugs_find(spapr, dimm);
3593     if (!ds) {
3594         ds = g_malloc0(sizeof(SpaprDimmState));
3595         ds->nr_lmbs = nr_lmbs;
3596         ds->dimm = dimm;
3597         QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next);
3598     }
3599     return ds;
3600 }
3601 
3602 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr,
3603                                               SpaprDimmState *dimm_state)
3604 {
3605     QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next);
3606     g_free(dimm_state);
3607 }
3608 
3609 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms,
3610                                                         PCDIMMDevice *dimm)
3611 {
3612     SpaprDrc *drc;
3613     uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm),
3614                                                   &error_abort);
3615     uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3616     uint32_t avail_lmbs = 0;
3617     uint64_t addr_start, addr;
3618     int i;
3619 
3620     addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3621                                          &error_abort);
3622 
3623     addr = addr_start;
3624     for (i = 0; i < nr_lmbs; i++) {
3625         drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3626                               addr / SPAPR_MEMORY_BLOCK_SIZE);
3627         g_assert(drc);
3628         if (drc->dev) {
3629             avail_lmbs++;
3630         }
3631         addr += SPAPR_MEMORY_BLOCK_SIZE;
3632     }
3633 
3634     return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm);
3635 }
3636 
3637 /* Callback to be called during DRC release. */
3638 void spapr_lmb_release(DeviceState *dev)
3639 {
3640     HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3641     SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl);
3642     SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3643 
3644     /* This information will get lost if a migration occurs
3645      * during the unplug process. In this case recover it. */
3646     if (ds == NULL) {
3647         ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev));
3648         g_assert(ds);
3649         /* The DRC being examined by the caller at least must be counted */
3650         g_assert(ds->nr_lmbs);
3651     }
3652 
3653     if (--ds->nr_lmbs) {
3654         return;
3655     }
3656 
3657     /*
3658      * Now that all the LMBs have been removed by the guest, call the
3659      * unplug handler chain. This can never fail.
3660      */
3661     hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3662     object_unparent(OBJECT(dev));
3663 }
3664 
3665 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3666 {
3667     SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3668     SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3669 
3670     pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev));
3671     object_property_set_bool(OBJECT(dev), false, "realized", NULL);
3672     spapr_pending_dimm_unplugs_remove(spapr, ds);
3673 }
3674 
3675 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
3676                                         DeviceState *dev, Error **errp)
3677 {
3678     SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3679     Error *local_err = NULL;
3680     PCDIMMDevice *dimm = PC_DIMM(dev);
3681     uint32_t nr_lmbs;
3682     uint64_t size, addr_start, addr;
3683     int i;
3684     SpaprDrc *drc;
3685 
3686     size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort);
3687     nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3688 
3689     addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3690                                          &local_err);
3691     if (local_err) {
3692         goto out;
3693     }
3694 
3695     /*
3696      * An existing pending dimm state for this DIMM means that there is an
3697      * unplug operation in progress, waiting for the spapr_lmb_release
3698      * callback to complete the job (BQL can't cover that far). In this case,
3699      * bail out to avoid detaching DRCs that were already released.
3700      */
3701     if (spapr_pending_dimm_unplugs_find(spapr, dimm)) {
3702         error_setg(&local_err,
3703                    "Memory unplug already in progress for device %s",
3704                    dev->id);
3705         goto out;
3706     }
3707 
3708     spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm);
3709 
3710     addr = addr_start;
3711     for (i = 0; i < nr_lmbs; i++) {
3712         drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3713                               addr / SPAPR_MEMORY_BLOCK_SIZE);
3714         g_assert(drc);
3715 
3716         spapr_drc_detach(drc);
3717         addr += SPAPR_MEMORY_BLOCK_SIZE;
3718     }
3719 
3720     drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3721                           addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3722     spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3723                                               nr_lmbs, spapr_drc_index(drc));
3724 out:
3725     error_propagate(errp, local_err);
3726 }
3727 
3728 /* Callback to be called during DRC release. */
3729 void spapr_core_release(DeviceState *dev)
3730 {
3731     HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3732 
3733     /* Call the unplug handler chain. This can never fail. */
3734     hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3735     object_unparent(OBJECT(dev));
3736 }
3737 
3738 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3739 {
3740     MachineState *ms = MACHINE(hotplug_dev);
3741     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3742     CPUCore *cc = CPU_CORE(dev);
3743     CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
3744 
3745     if (smc->pre_2_10_has_unused_icps) {
3746         SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
3747         int i;
3748 
3749         for (i = 0; i < cc->nr_threads; i++) {
3750             CPUState *cs = CPU(sc->threads[i]);
3751 
3752             pre_2_10_vmstate_register_dummy_icp(cs->cpu_index);
3753         }
3754     }
3755 
3756     assert(core_slot);
3757     core_slot->cpu = NULL;
3758     object_property_set_bool(OBJECT(dev), false, "realized", NULL);
3759 }
3760 
3761 static
3762 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
3763                                Error **errp)
3764 {
3765     SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3766     int index;
3767     SpaprDrc *drc;
3768     CPUCore *cc = CPU_CORE(dev);
3769 
3770     if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
3771         error_setg(errp, "Unable to find CPU core with core-id: %d",
3772                    cc->core_id);
3773         return;
3774     }
3775     if (index == 0) {
3776         error_setg(errp, "Boot CPU core may not be unplugged");
3777         return;
3778     }
3779 
3780     drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3781                           spapr_vcpu_id(spapr, cc->core_id));
3782     g_assert(drc);
3783 
3784     spapr_drc_detach(drc);
3785 
3786     spapr_hotplug_req_remove_by_index(drc);
3787 }
3788 
3789 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3790                            void *fdt, int *fdt_start_offset, Error **errp)
3791 {
3792     SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev);
3793     CPUState *cs = CPU(core->threads[0]);
3794     PowerPCCPU *cpu = POWERPC_CPU(cs);
3795     DeviceClass *dc = DEVICE_GET_CLASS(cs);
3796     int id = spapr_get_vcpu_id(cpu);
3797     char *nodename;
3798     int offset;
3799 
3800     nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
3801     offset = fdt_add_subnode(fdt, 0, nodename);
3802     g_free(nodename);
3803 
3804     spapr_populate_cpu_dt(cs, fdt, offset, spapr);
3805 
3806     *fdt_start_offset = offset;
3807     return 0;
3808 }
3809 
3810 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3811                             Error **errp)
3812 {
3813     SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3814     MachineClass *mc = MACHINE_GET_CLASS(spapr);
3815     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3816     SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev));
3817     CPUCore *cc = CPU_CORE(dev);
3818     CPUState *cs;
3819     SpaprDrc *drc;
3820     Error *local_err = NULL;
3821     CPUArchId *core_slot;
3822     int index;
3823     bool hotplugged = spapr_drc_hotplugged(dev);
3824 
3825     core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3826     if (!core_slot) {
3827         error_setg(errp, "Unable to find CPU core with core-id: %d",
3828                    cc->core_id);
3829         return;
3830     }
3831     drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3832                           spapr_vcpu_id(spapr, cc->core_id));
3833 
3834     g_assert(drc || !mc->has_hotpluggable_cpus);
3835 
3836     if (drc) {
3837         spapr_drc_attach(drc, dev, &local_err);
3838         if (local_err) {
3839             error_propagate(errp, local_err);
3840             return;
3841         }
3842 
3843         if (hotplugged) {
3844             /*
3845              * Send hotplug notification interrupt to the guest only
3846              * in case of hotplugged CPUs.
3847              */
3848             spapr_hotplug_req_add_by_index(drc);
3849         } else {
3850             spapr_drc_reset(drc);
3851         }
3852     }
3853 
3854     core_slot->cpu = OBJECT(dev);
3855 
3856     if (smc->pre_2_10_has_unused_icps) {
3857         int i;
3858 
3859         for (i = 0; i < cc->nr_threads; i++) {
3860             cs = CPU(core->threads[i]);
3861             pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
3862         }
3863     }
3864 }
3865 
3866 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3867                                 Error **errp)
3868 {
3869     MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3870     MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
3871     Error *local_err = NULL;
3872     CPUCore *cc = CPU_CORE(dev);
3873     const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type);
3874     const char *type = object_get_typename(OBJECT(dev));
3875     CPUArchId *core_slot;
3876     int index;
3877     unsigned int smp_threads = machine->smp.threads;
3878 
3879     if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
3880         error_setg(&local_err, "CPU hotplug not supported for this machine");
3881         goto out;
3882     }
3883 
3884     if (strcmp(base_core_type, type)) {
3885         error_setg(&local_err, "CPU core type should be %s", base_core_type);
3886         goto out;
3887     }
3888 
3889     if (cc->core_id % smp_threads) {
3890         error_setg(&local_err, "invalid core id %d", cc->core_id);
3891         goto out;
3892     }
3893 
3894     /*
3895      * In general we should have homogeneous threads-per-core, but old
3896      * (pre hotplug support) machine types allow the last core to have
3897      * reduced threads as a compatibility hack for when we allowed
3898      * total vcpus not a multiple of threads-per-core.
3899      */
3900     if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) {
3901         error_setg(&local_err, "invalid nr-threads %d, must be %d",
3902                    cc->nr_threads, smp_threads);
3903         goto out;
3904     }
3905 
3906     core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3907     if (!core_slot) {
3908         error_setg(&local_err, "core id %d out of range", cc->core_id);
3909         goto out;
3910     }
3911 
3912     if (core_slot->cpu) {
3913         error_setg(&local_err, "core %d already populated", cc->core_id);
3914         goto out;
3915     }
3916 
3917     numa_cpu_pre_plug(core_slot, dev, &local_err);
3918 
3919 out:
3920     error_propagate(errp, local_err);
3921 }
3922 
3923 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3924                           void *fdt, int *fdt_start_offset, Error **errp)
3925 {
3926     SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev);
3927     int intc_phandle;
3928 
3929     intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp);
3930     if (intc_phandle <= 0) {
3931         return -1;
3932     }
3933 
3934     if (spapr_dt_phb(sphb, intc_phandle, fdt, spapr->irq->nr_msis,
3935                      fdt_start_offset)) {
3936         error_setg(errp, "unable to create FDT node for PHB %d", sphb->index);
3937         return -1;
3938     }
3939 
3940     /* generally SLOF creates these, for hotplug it's up to QEMU */
3941     _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci"));
3942 
3943     return 0;
3944 }
3945 
3946 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3947                                Error **errp)
3948 {
3949     SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3950     SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
3951     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3952     const unsigned windows_supported = spapr_phb_windows_supported(sphb);
3953 
3954     if (dev->hotplugged && !smc->dr_phb_enabled) {
3955         error_setg(errp, "PHB hotplug not supported for this machine");
3956         return;
3957     }
3958 
3959     if (sphb->index == (uint32_t)-1) {
3960         error_setg(errp, "\"index\" for PAPR PHB is mandatory");
3961         return;
3962     }
3963 
3964     /*
3965      * This will check that sphb->index doesn't exceed the maximum number of
3966      * PHBs for the current machine type.
3967      */
3968     smc->phb_placement(spapr, sphb->index,
3969                        &sphb->buid, &sphb->io_win_addr,
3970                        &sphb->mem_win_addr, &sphb->mem64_win_addr,
3971                        windows_supported, sphb->dma_liobn,
3972                        &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr,
3973                        errp);
3974 }
3975 
3976 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3977                            Error **errp)
3978 {
3979     SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3980     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3981     SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
3982     SpaprDrc *drc;
3983     bool hotplugged = spapr_drc_hotplugged(dev);
3984     Error *local_err = NULL;
3985 
3986     if (!smc->dr_phb_enabled) {
3987         return;
3988     }
3989 
3990     drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index);
3991     /* hotplug hooks should check it's enabled before getting this far */
3992     assert(drc);
3993 
3994     spapr_drc_attach(drc, DEVICE(dev), &local_err);
3995     if (local_err) {
3996         error_propagate(errp, local_err);
3997         return;
3998     }
3999 
4000     if (hotplugged) {
4001         spapr_hotplug_req_add_by_index(drc);
4002     } else {
4003         spapr_drc_reset(drc);
4004     }
4005 }
4006 
4007 void spapr_phb_release(DeviceState *dev)
4008 {
4009     HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
4010 
4011     hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
4012     object_unparent(OBJECT(dev));
4013 }
4014 
4015 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
4016 {
4017     object_property_set_bool(OBJECT(dev), false, "realized", NULL);
4018 }
4019 
4020 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev,
4021                                      DeviceState *dev, Error **errp)
4022 {
4023     SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
4024     SpaprDrc *drc;
4025 
4026     drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index);
4027     assert(drc);
4028 
4029     if (!spapr_drc_unplug_requested(drc)) {
4030         spapr_drc_detach(drc);
4031         spapr_hotplug_req_remove_by_index(drc);
4032     }
4033 }
4034 
4035 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
4036                                       DeviceState *dev, Error **errp)
4037 {
4038     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4039         spapr_memory_plug(hotplug_dev, dev, errp);
4040     } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4041         spapr_core_plug(hotplug_dev, dev, errp);
4042     } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4043         spapr_phb_plug(hotplug_dev, dev, errp);
4044     }
4045 }
4046 
4047 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
4048                                         DeviceState *dev, Error **errp)
4049 {
4050     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4051         spapr_memory_unplug(hotplug_dev, dev);
4052     } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4053         spapr_core_unplug(hotplug_dev, dev);
4054     } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4055         spapr_phb_unplug(hotplug_dev, dev);
4056     }
4057 }
4058 
4059 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
4060                                                 DeviceState *dev, Error **errp)
4061 {
4062     SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev));
4063     MachineClass *mc = MACHINE_GET_CLASS(sms);
4064     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4065 
4066     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4067         if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
4068             spapr_memory_unplug_request(hotplug_dev, dev, errp);
4069         } else {
4070             /* NOTE: this means there is a window after guest reset, prior to
4071              * CAS negotiation, where unplug requests will fail due to the
4072              * capability not being detected yet. This is a bit different than
4073              * the case with PCI unplug, where the events will be queued and
4074              * eventually handled by the guest after boot
4075              */
4076             error_setg(errp, "Memory hot unplug not supported for this guest");
4077         }
4078     } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4079         if (!mc->has_hotpluggable_cpus) {
4080             error_setg(errp, "CPU hot unplug not supported on this machine");
4081             return;
4082         }
4083         spapr_core_unplug_request(hotplug_dev, dev, errp);
4084     } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4085         if (!smc->dr_phb_enabled) {
4086             error_setg(errp, "PHB hot unplug not supported on this machine");
4087             return;
4088         }
4089         spapr_phb_unplug_request(hotplug_dev, dev, errp);
4090     }
4091 }
4092 
4093 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
4094                                           DeviceState *dev, Error **errp)
4095 {
4096     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4097         spapr_memory_pre_plug(hotplug_dev, dev, errp);
4098     } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4099         spapr_core_pre_plug(hotplug_dev, dev, errp);
4100     } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4101         spapr_phb_pre_plug(hotplug_dev, dev, errp);
4102     }
4103 }
4104 
4105 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
4106                                                  DeviceState *dev)
4107 {
4108     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
4109         object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) ||
4110         object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4111         return HOTPLUG_HANDLER(machine);
4112     }
4113     if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
4114         PCIDevice *pcidev = PCI_DEVICE(dev);
4115         PCIBus *root = pci_device_root_bus(pcidev);
4116         SpaprPhbState *phb =
4117             (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent),
4118                                                  TYPE_SPAPR_PCI_HOST_BRIDGE);
4119 
4120         if (phb) {
4121             return HOTPLUG_HANDLER(phb);
4122         }
4123     }
4124     return NULL;
4125 }
4126 
4127 static CpuInstanceProperties
4128 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
4129 {
4130     CPUArchId *core_slot;
4131     MachineClass *mc = MACHINE_GET_CLASS(machine);
4132 
4133     /* make sure possible_cpu are intialized */
4134     mc->possible_cpu_arch_ids(machine);
4135     /* get CPU core slot containing thread that matches cpu_index */
4136     core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
4137     assert(core_slot);
4138     return core_slot->props;
4139 }
4140 
4141 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx)
4142 {
4143     return idx / ms->smp.cores % nb_numa_nodes;
4144 }
4145 
4146 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
4147 {
4148     int i;
4149     unsigned int smp_threads = machine->smp.threads;
4150     unsigned int smp_cpus = machine->smp.cpus;
4151     const char *core_type;
4152     int spapr_max_cores = machine->smp.max_cpus / smp_threads;
4153     MachineClass *mc = MACHINE_GET_CLASS(machine);
4154 
4155     if (!mc->has_hotpluggable_cpus) {
4156         spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
4157     }
4158     if (machine->possible_cpus) {
4159         assert(machine->possible_cpus->len == spapr_max_cores);
4160         return machine->possible_cpus;
4161     }
4162 
4163     core_type = spapr_get_cpu_core_type(machine->cpu_type);
4164     if (!core_type) {
4165         error_report("Unable to find sPAPR CPU Core definition");
4166         exit(1);
4167     }
4168 
4169     machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
4170                              sizeof(CPUArchId) * spapr_max_cores);
4171     machine->possible_cpus->len = spapr_max_cores;
4172     for (i = 0; i < machine->possible_cpus->len; i++) {
4173         int core_id = i * smp_threads;
4174 
4175         machine->possible_cpus->cpus[i].type = core_type;
4176         machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
4177         machine->possible_cpus->cpus[i].arch_id = core_id;
4178         machine->possible_cpus->cpus[i].props.has_core_id = true;
4179         machine->possible_cpus->cpus[i].props.core_id = core_id;
4180     }
4181     return machine->possible_cpus;
4182 }
4183 
4184 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index,
4185                                 uint64_t *buid, hwaddr *pio,
4186                                 hwaddr *mmio32, hwaddr *mmio64,
4187                                 unsigned n_dma, uint32_t *liobns,
4188                                 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp)
4189 {
4190     /*
4191      * New-style PHB window placement.
4192      *
4193      * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
4194      * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
4195      * windows.
4196      *
4197      * Some guest kernels can't work with MMIO windows above 1<<46
4198      * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
4199      *
4200      * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
4201      * PHB stacked together.  (32TiB+2GiB)..(32TiB+64GiB) contains the
4202      * 2GiB 32-bit MMIO windows for each PHB.  Then 33..64TiB has the
4203      * 1TiB 64-bit MMIO windows for each PHB.
4204      */
4205     const uint64_t base_buid = 0x800000020000000ULL;
4206     int i;
4207 
4208     /* Sanity check natural alignments */
4209     QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
4210     QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
4211     QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
4212     QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
4213     /* Sanity check bounds */
4214     QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
4215                       SPAPR_PCI_MEM32_WIN_SIZE);
4216     QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
4217                       SPAPR_PCI_MEM64_WIN_SIZE);
4218 
4219     if (index >= SPAPR_MAX_PHBS) {
4220         error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
4221                    SPAPR_MAX_PHBS - 1);
4222         return;
4223     }
4224 
4225     *buid = base_buid + index;
4226     for (i = 0; i < n_dma; ++i) {
4227         liobns[i] = SPAPR_PCI_LIOBN(index, i);
4228     }
4229 
4230     *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
4231     *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
4232     *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
4233 
4234     *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE;
4235     *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE;
4236 }
4237 
4238 static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
4239 {
4240     SpaprMachineState *spapr = SPAPR_MACHINE(dev);
4241 
4242     return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
4243 }
4244 
4245 static void spapr_ics_resend(XICSFabric *dev)
4246 {
4247     SpaprMachineState *spapr = SPAPR_MACHINE(dev);
4248 
4249     ics_resend(spapr->ics);
4250 }
4251 
4252 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
4253 {
4254     PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
4255 
4256     return cpu ? spapr_cpu_state(cpu)->icp : NULL;
4257 }
4258 
4259 static void spapr_pic_print_info(InterruptStatsProvider *obj,
4260                                  Monitor *mon)
4261 {
4262     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
4263 
4264     spapr->irq->print_info(spapr, mon);
4265 }
4266 
4267 int spapr_get_vcpu_id(PowerPCCPU *cpu)
4268 {
4269     return cpu->vcpu_id;
4270 }
4271 
4272 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp)
4273 {
4274     SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
4275     MachineState *ms = MACHINE(spapr);
4276     int vcpu_id;
4277 
4278     vcpu_id = spapr_vcpu_id(spapr, cpu_index);
4279 
4280     if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) {
4281         error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id);
4282         error_append_hint(errp, "Adjust the number of cpus to %d "
4283                           "or try to raise the number of threads per core\n",
4284                           vcpu_id * ms->smp.threads / spapr->vsmt);
4285         return;
4286     }
4287 
4288     cpu->vcpu_id = vcpu_id;
4289 }
4290 
4291 PowerPCCPU *spapr_find_cpu(int vcpu_id)
4292 {
4293     CPUState *cs;
4294 
4295     CPU_FOREACH(cs) {
4296         PowerPCCPU *cpu = POWERPC_CPU(cs);
4297 
4298         if (spapr_get_vcpu_id(cpu) == vcpu_id) {
4299             return cpu;
4300         }
4301     }
4302 
4303     return NULL;
4304 }
4305 
4306 static void spapr_machine_class_init(ObjectClass *oc, void *data)
4307 {
4308     MachineClass *mc = MACHINE_CLASS(oc);
4309     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
4310     FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
4311     NMIClass *nc = NMI_CLASS(oc);
4312     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
4313     PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
4314     XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
4315     InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
4316 
4317     mc->desc = "pSeries Logical Partition (PAPR compliant)";
4318     mc->ignore_boot_device_suffixes = true;
4319 
4320     /*
4321      * We set up the default / latest behaviour here.  The class_init
4322      * functions for the specific versioned machine types can override
4323      * these details for backwards compatibility
4324      */
4325     mc->init = spapr_machine_init;
4326     mc->reset = spapr_machine_reset;
4327     mc->block_default_type = IF_SCSI;
4328     mc->max_cpus = 1024;
4329     mc->no_parallel = 1;
4330     mc->default_boot_order = "";
4331     mc->default_ram_size = 512 * MiB;
4332     mc->default_display = "std";
4333     mc->kvm_type = spapr_kvm_type;
4334     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE);
4335     mc->pci_allow_0_address = true;
4336     assert(!mc->get_hotplug_handler);
4337     mc->get_hotplug_handler = spapr_get_hotplug_handler;
4338     hc->pre_plug = spapr_machine_device_pre_plug;
4339     hc->plug = spapr_machine_device_plug;
4340     mc->cpu_index_to_instance_props = spapr_cpu_index_to_props;
4341     mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id;
4342     mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
4343     hc->unplug_request = spapr_machine_device_unplug_request;
4344     hc->unplug = spapr_machine_device_unplug;
4345 
4346     smc->dr_lmb_enabled = true;
4347     smc->update_dt_enabled = true;
4348     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
4349     mc->has_hotpluggable_cpus = true;
4350     smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
4351     fwc->get_dev_path = spapr_get_fw_dev_path;
4352     nc->nmi_monitor_handler = spapr_nmi;
4353     smc->phb_placement = spapr_phb_placement;
4354     vhc->hypercall = emulate_spapr_hypercall;
4355     vhc->hpt_mask = spapr_hpt_mask;
4356     vhc->map_hptes = spapr_map_hptes;
4357     vhc->unmap_hptes = spapr_unmap_hptes;
4358     vhc->hpte_set_c = spapr_hpte_set_c;
4359     vhc->hpte_set_r = spapr_hpte_set_r;
4360     vhc->get_pate = spapr_get_pate;
4361     vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr;
4362     xic->ics_get = spapr_ics_get;
4363     xic->ics_resend = spapr_ics_resend;
4364     xic->icp_get = spapr_icp_get;
4365     ispc->print_info = spapr_pic_print_info;
4366     /* Force NUMA node memory size to be a multiple of
4367      * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
4368      * in which LMBs are represented and hot-added
4369      */
4370     mc->numa_mem_align_shift = 28;
4371     mc->numa_mem_supported = true;
4372 
4373     smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF;
4374     smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON;
4375     smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON;
4376     smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
4377     smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
4378     smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND;
4379     smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */
4380     smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF;
4381     smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON;
4382     smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF;
4383     spapr_caps_add_properties(smc, &error_abort);
4384     smc->irq = &spapr_irq_dual;
4385     smc->dr_phb_enabled = true;
4386 }
4387 
4388 static const TypeInfo spapr_machine_info = {
4389     .name          = TYPE_SPAPR_MACHINE,
4390     .parent        = TYPE_MACHINE,
4391     .abstract      = true,
4392     .instance_size = sizeof(SpaprMachineState),
4393     .instance_init = spapr_instance_init,
4394     .instance_finalize = spapr_machine_finalizefn,
4395     .class_size    = sizeof(SpaprMachineClass),
4396     .class_init    = spapr_machine_class_init,
4397     .interfaces = (InterfaceInfo[]) {
4398         { TYPE_FW_PATH_PROVIDER },
4399         { TYPE_NMI },
4400         { TYPE_HOTPLUG_HANDLER },
4401         { TYPE_PPC_VIRTUAL_HYPERVISOR },
4402         { TYPE_XICS_FABRIC },
4403         { TYPE_INTERRUPT_STATS_PROVIDER },
4404         { }
4405     },
4406 };
4407 
4408 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest)                 \
4409     static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4410                                                     void *data)      \
4411     {                                                                \
4412         MachineClass *mc = MACHINE_CLASS(oc);                        \
4413         spapr_machine_##suffix##_class_options(mc);                  \
4414         if (latest) {                                                \
4415             mc->alias = "pseries";                                   \
4416             mc->is_default = 1;                                      \
4417         }                                                            \
4418     }                                                                \
4419     static const TypeInfo spapr_machine_##suffix##_info = {          \
4420         .name = MACHINE_TYPE_NAME("pseries-" verstr),                \
4421         .parent = TYPE_SPAPR_MACHINE,                                \
4422         .class_init = spapr_machine_##suffix##_class_init,           \
4423     };                                                               \
4424     static void spapr_machine_register_##suffix(void)                \
4425     {                                                                \
4426         type_register(&spapr_machine_##suffix##_info);               \
4427     }                                                                \
4428     type_init(spapr_machine_register_##suffix)
4429 
4430 /*
4431  * pseries-4.1
4432  */
4433 static void spapr_machine_4_1_class_options(MachineClass *mc)
4434 {
4435     /* Defaults for the latest behaviour inherited from the base class */
4436 }
4437 
4438 DEFINE_SPAPR_MACHINE(4_1, "4.1", true);
4439 
4440 /*
4441  * pseries-4.0
4442  */
4443 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index,
4444                               uint64_t *buid, hwaddr *pio,
4445                               hwaddr *mmio32, hwaddr *mmio64,
4446                               unsigned n_dma, uint32_t *liobns,
4447                               hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp)
4448 {
4449     spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns,
4450                         nv2gpa, nv2atsd, errp);
4451     *nv2gpa = 0;
4452     *nv2atsd = 0;
4453 }
4454 
4455 static void spapr_machine_4_0_class_options(MachineClass *mc)
4456 {
4457     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4458 
4459     spapr_machine_4_1_class_options(mc);
4460     compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
4461     smc->phb_placement = phb_placement_4_0;
4462     smc->irq = &spapr_irq_xics;
4463     smc->pre_4_1_migration = true;
4464 }
4465 
4466 DEFINE_SPAPR_MACHINE(4_0, "4.0", false);
4467 
4468 /*
4469  * pseries-3.1
4470  */
4471 static void spapr_machine_3_1_class_options(MachineClass *mc)
4472 {
4473     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4474 
4475     spapr_machine_4_0_class_options(mc);
4476     compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
4477 
4478     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
4479     smc->update_dt_enabled = false;
4480     smc->dr_phb_enabled = false;
4481     smc->broken_host_serial_model = true;
4482     smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN;
4483     smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN;
4484     smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN;
4485     smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF;
4486 }
4487 
4488 DEFINE_SPAPR_MACHINE(3_1, "3.1", false);
4489 
4490 /*
4491  * pseries-3.0
4492  */
4493 
4494 static void spapr_machine_3_0_class_options(MachineClass *mc)
4495 {
4496     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4497 
4498     spapr_machine_3_1_class_options(mc);
4499     compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
4500 
4501     smc->legacy_irq_allocation = true;
4502     smc->irq = &spapr_irq_xics_legacy;
4503 }
4504 
4505 DEFINE_SPAPR_MACHINE(3_0, "3.0", false);
4506 
4507 /*
4508  * pseries-2.12
4509  */
4510 static void spapr_machine_2_12_class_options(MachineClass *mc)
4511 {
4512     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4513     static GlobalProperty compat[] = {
4514         { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" },
4515         { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" },
4516     };
4517 
4518     spapr_machine_3_0_class_options(mc);
4519     compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
4520     compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4521 
4522     /* We depend on kvm_enabled() to choose a default value for the
4523      * hpt-max-page-size capability. Of course we can't do it here
4524      * because this is too early and the HW accelerator isn't initialzed
4525      * yet. Postpone this to machine init (see default_caps_with_cpu()).
4526      */
4527     smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0;
4528 }
4529 
4530 DEFINE_SPAPR_MACHINE(2_12, "2.12", false);
4531 
4532 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc)
4533 {
4534     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4535 
4536     spapr_machine_2_12_class_options(mc);
4537     smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
4538     smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
4539     smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD;
4540 }
4541 
4542 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false);
4543 
4544 /*
4545  * pseries-2.11
4546  */
4547 
4548 static void spapr_machine_2_11_class_options(MachineClass *mc)
4549 {
4550     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4551 
4552     spapr_machine_2_12_class_options(mc);
4553     smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON;
4554     compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
4555 }
4556 
4557 DEFINE_SPAPR_MACHINE(2_11, "2.11", false);
4558 
4559 /*
4560  * pseries-2.10
4561  */
4562 
4563 static void spapr_machine_2_10_class_options(MachineClass *mc)
4564 {
4565     spapr_machine_2_11_class_options(mc);
4566     compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
4567 }
4568 
4569 DEFINE_SPAPR_MACHINE(2_10, "2.10", false);
4570 
4571 /*
4572  * pseries-2.9
4573  */
4574 
4575 static void spapr_machine_2_9_class_options(MachineClass *mc)
4576 {
4577     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4578     static GlobalProperty compat[] = {
4579         { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" },
4580     };
4581 
4582     spapr_machine_2_10_class_options(mc);
4583     compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
4584     compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4585     mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
4586     smc->pre_2_10_has_unused_icps = true;
4587     smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
4588 }
4589 
4590 DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
4591 
4592 /*
4593  * pseries-2.8
4594  */
4595 
4596 static void spapr_machine_2_8_class_options(MachineClass *mc)
4597 {
4598     static GlobalProperty compat[] = {
4599         { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" },
4600     };
4601 
4602     spapr_machine_2_9_class_options(mc);
4603     compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
4604     compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4605     mc->numa_mem_align_shift = 23;
4606 }
4607 
4608 DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
4609 
4610 /*
4611  * pseries-2.7
4612  */
4613 
4614 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index,
4615                               uint64_t *buid, hwaddr *pio,
4616                               hwaddr *mmio32, hwaddr *mmio64,
4617                               unsigned n_dma, uint32_t *liobns,
4618                               hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp)
4619 {
4620     /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4621     const uint64_t base_buid = 0x800000020000000ULL;
4622     const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
4623     const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
4624     const hwaddr pio_offset = 0x80000000; /* 2 GiB */
4625     const uint32_t max_index = 255;
4626     const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */
4627 
4628     uint64_t ram_top = MACHINE(spapr)->ram_size;
4629     hwaddr phb0_base, phb_base;
4630     int i;
4631 
4632     /* Do we have device memory? */
4633     if (MACHINE(spapr)->maxram_size > ram_top) {
4634         /* Can't just use maxram_size, because there may be an
4635          * alignment gap between normal and device memory regions
4636          */
4637         ram_top = MACHINE(spapr)->device_memory->base +
4638             memory_region_size(&MACHINE(spapr)->device_memory->mr);
4639     }
4640 
4641     phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
4642 
4643     if (index > max_index) {
4644         error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
4645                    max_index);
4646         return;
4647     }
4648 
4649     *buid = base_buid + index;
4650     for (i = 0; i < n_dma; ++i) {
4651         liobns[i] = SPAPR_PCI_LIOBN(index, i);
4652     }
4653 
4654     phb_base = phb0_base + index * phb_spacing;
4655     *pio = phb_base + pio_offset;
4656     *mmio32 = phb_base + mmio_offset;
4657     /*
4658      * We don't set the 64-bit MMIO window, relying on the PHB's
4659      * fallback behaviour of automatically splitting a large "32-bit"
4660      * window into contiguous 32-bit and 64-bit windows
4661      */
4662 
4663     *nv2gpa = 0;
4664     *nv2atsd = 0;
4665 }
4666 
4667 static void spapr_machine_2_7_class_options(MachineClass *mc)
4668 {
4669     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4670     static GlobalProperty compat[] = {
4671         { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", },
4672         { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", },
4673         { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", },
4674         { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", },
4675     };
4676 
4677     spapr_machine_2_8_class_options(mc);
4678     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3");
4679     mc->default_machine_opts = "modern-hotplug-events=off";
4680     compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
4681     compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4682     smc->phb_placement = phb_placement_2_7;
4683 }
4684 
4685 DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
4686 
4687 /*
4688  * pseries-2.6
4689  */
4690 
4691 static void spapr_machine_2_6_class_options(MachineClass *mc)
4692 {
4693     static GlobalProperty compat[] = {
4694         { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" },
4695     };
4696 
4697     spapr_machine_2_7_class_options(mc);
4698     mc->has_hotpluggable_cpus = false;
4699     compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
4700     compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4701 }
4702 
4703 DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
4704 
4705 /*
4706  * pseries-2.5
4707  */
4708 
4709 static void spapr_machine_2_5_class_options(MachineClass *mc)
4710 {
4711     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4712     static GlobalProperty compat[] = {
4713         { "spapr-vlan", "use-rx-buffer-pools", "off" },
4714     };
4715 
4716     spapr_machine_2_6_class_options(mc);
4717     smc->use_ohci_by_default = true;
4718     compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len);
4719     compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4720 }
4721 
4722 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
4723 
4724 /*
4725  * pseries-2.4
4726  */
4727 
4728 static void spapr_machine_2_4_class_options(MachineClass *mc)
4729 {
4730     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4731 
4732     spapr_machine_2_5_class_options(mc);
4733     smc->dr_lmb_enabled = false;
4734     compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len);
4735 }
4736 
4737 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
4738 
4739 /*
4740  * pseries-2.3
4741  */
4742 
4743 static void spapr_machine_2_3_class_options(MachineClass *mc)
4744 {
4745     static GlobalProperty compat[] = {
4746         { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" },
4747     };
4748     spapr_machine_2_4_class_options(mc);
4749     compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len);
4750     compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4751 }
4752 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
4753 
4754 /*
4755  * pseries-2.2
4756  */
4757 
4758 static void spapr_machine_2_2_class_options(MachineClass *mc)
4759 {
4760     static GlobalProperty compat[] = {
4761         { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" },
4762     };
4763 
4764     spapr_machine_2_3_class_options(mc);
4765     compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len);
4766     compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4767     mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on";
4768 }
4769 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
4770 
4771 /*
4772  * pseries-2.1
4773  */
4774 
4775 static void spapr_machine_2_1_class_options(MachineClass *mc)
4776 {
4777     spapr_machine_2_2_class_options(mc);
4778     compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len);
4779 }
4780 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
4781 
4782 static void spapr_machine_register_types(void)
4783 {
4784     type_register_static(&spapr_machine_info);
4785 }
4786 
4787 type_init(spapr_machine_register_types)
4788