1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/datadir.h" 30 #include "qapi/error.h" 31 #include "qapi/visitor.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/hostmem.h" 34 #include "sysemu/numa.h" 35 #include "sysemu/qtest.h" 36 #include "sysemu/reset.h" 37 #include "sysemu/runstate.h" 38 #include "qemu/log.h" 39 #include "hw/fw-path-provider.h" 40 #include "elf.h" 41 #include "net/net.h" 42 #include "sysemu/device_tree.h" 43 #include "sysemu/cpus.h" 44 #include "sysemu/hw_accel.h" 45 #include "kvm_ppc.h" 46 #include "migration/misc.h" 47 #include "migration/qemu-file-types.h" 48 #include "migration/global_state.h" 49 #include "migration/register.h" 50 #include "migration/blocker.h" 51 #include "mmu-hash64.h" 52 #include "mmu-book3s-v3.h" 53 #include "cpu-models.h" 54 #include "hw/core/cpu.h" 55 56 #include "hw/boards.h" 57 #include "hw/ppc/ppc.h" 58 #include "hw/loader.h" 59 60 #include "hw/ppc/fdt.h" 61 #include "hw/ppc/spapr.h" 62 #include "hw/ppc/spapr_vio.h" 63 #include "hw/qdev-properties.h" 64 #include "hw/pci-host/spapr.h" 65 #include "hw/pci/msi.h" 66 67 #include "hw/pci/pci.h" 68 #include "hw/scsi/scsi.h" 69 #include "hw/virtio/virtio-scsi.h" 70 #include "hw/virtio/vhost-scsi-common.h" 71 72 #include "exec/address-spaces.h" 73 #include "exec/ram_addr.h" 74 #include "hw/usb.h" 75 #include "qemu/config-file.h" 76 #include "qemu/error-report.h" 77 #include "trace.h" 78 #include "hw/nmi.h" 79 #include "hw/intc/intc.h" 80 81 #include "hw/ppc/spapr_cpu_core.h" 82 #include "hw/mem/memory-device.h" 83 #include "hw/ppc/spapr_tpm_proxy.h" 84 #include "hw/ppc/spapr_nvdimm.h" 85 #include "hw/ppc/spapr_numa.h" 86 87 #include "monitor/monitor.h" 88 89 #include <libfdt.h> 90 91 /* SLOF memory layout: 92 * 93 * SLOF raw image loaded at 0, copies its romfs right below the flat 94 * device-tree, then position SLOF itself 31M below that 95 * 96 * So we set FW_OVERHEAD to 40MB which should account for all of that 97 * and more 98 * 99 * We load our kernel at 4M, leaving space for SLOF initial image 100 */ 101 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 102 #define FW_MAX_SIZE 0x400000 103 #define FW_FILE_NAME "slof.bin" 104 #define FW_OVERHEAD 0x2800000 105 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 106 107 #define MIN_RMA_SLOF (128 * MiB) 108 109 #define PHANDLE_INTC 0x00001111 110 111 /* These two functions implement the VCPU id numbering: one to compute them 112 * all and one to identify thread 0 of a VCORE. Any change to the first one 113 * is likely to have an impact on the second one, so let's keep them close. 114 */ 115 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 116 { 117 MachineState *ms = MACHINE(spapr); 118 unsigned int smp_threads = ms->smp.threads; 119 120 assert(spapr->vsmt); 121 return 122 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 123 } 124 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 125 PowerPCCPU *cpu) 126 { 127 assert(spapr->vsmt); 128 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 129 } 130 131 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 132 { 133 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 134 * and newer QEMUs don't even have them. In both cases, we don't want 135 * to send anything on the wire. 136 */ 137 return false; 138 } 139 140 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 141 .name = "icp/server", 142 .version_id = 1, 143 .minimum_version_id = 1, 144 .needed = pre_2_10_vmstate_dummy_icp_needed, 145 .fields = (VMStateField[]) { 146 VMSTATE_UNUSED(4), /* uint32_t xirr */ 147 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 148 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 149 VMSTATE_END_OF_LIST() 150 }, 151 }; 152 153 static void pre_2_10_vmstate_register_dummy_icp(int i) 154 { 155 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 156 (void *)(uintptr_t) i); 157 } 158 159 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 160 { 161 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 162 (void *)(uintptr_t) i); 163 } 164 165 int spapr_max_server_number(SpaprMachineState *spapr) 166 { 167 MachineState *ms = MACHINE(spapr); 168 169 assert(spapr->vsmt); 170 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 171 } 172 173 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 174 int smt_threads) 175 { 176 int i, ret = 0; 177 uint32_t servers_prop[smt_threads]; 178 uint32_t gservers_prop[smt_threads * 2]; 179 int index = spapr_get_vcpu_id(cpu); 180 181 if (cpu->compat_pvr) { 182 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 183 if (ret < 0) { 184 return ret; 185 } 186 } 187 188 /* Build interrupt servers and gservers properties */ 189 for (i = 0; i < smt_threads; i++) { 190 servers_prop[i] = cpu_to_be32(index + i); 191 /* Hack, direct the group queues back to cpu 0 */ 192 gservers_prop[i*2] = cpu_to_be32(index + i); 193 gservers_prop[i*2 + 1] = 0; 194 } 195 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 196 servers_prop, sizeof(servers_prop)); 197 if (ret < 0) { 198 return ret; 199 } 200 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 201 gservers_prop, sizeof(gservers_prop)); 202 203 return ret; 204 } 205 206 static void spapr_dt_pa_features(SpaprMachineState *spapr, 207 PowerPCCPU *cpu, 208 void *fdt, int offset) 209 { 210 uint8_t pa_features_206[] = { 6, 0, 211 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 212 uint8_t pa_features_207[] = { 24, 0, 213 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 214 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 215 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 216 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 217 uint8_t pa_features_300[] = { 66, 0, 218 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 219 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 220 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 221 /* 6: DS207 */ 222 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 223 /* 16: Vector */ 224 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 225 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 226 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 227 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 228 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 229 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 230 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 231 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 232 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 233 /* 42: PM, 44: PC RA, 46: SC vec'd */ 234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 235 /* 48: SIMD, 50: QP BFP, 52: String */ 236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 237 /* 54: DecFP, 56: DecI, 58: SHA */ 238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 239 /* 60: NM atomic, 62: RNG */ 240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 241 }; 242 uint8_t *pa_features = NULL; 243 size_t pa_size; 244 245 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 246 pa_features = pa_features_206; 247 pa_size = sizeof(pa_features_206); 248 } 249 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 250 pa_features = pa_features_207; 251 pa_size = sizeof(pa_features_207); 252 } 253 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 254 pa_features = pa_features_300; 255 pa_size = sizeof(pa_features_300); 256 } 257 if (!pa_features) { 258 return; 259 } 260 261 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 262 /* 263 * Note: we keep CI large pages off by default because a 64K capable 264 * guest provisioned with large pages might otherwise try to map a qemu 265 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 266 * even if that qemu runs on a 4k host. 267 * We dd this bit back here if we are confident this is not an issue 268 */ 269 pa_features[3] |= 0x20; 270 } 271 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 272 pa_features[24] |= 0x80; /* Transactional memory support */ 273 } 274 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 275 /* Workaround for broken kernels that attempt (guest) radix 276 * mode when they can't handle it, if they see the radix bit set 277 * in pa-features. So hide it from them. */ 278 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 279 } 280 281 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 282 } 283 284 static hwaddr spapr_node0_size(MachineState *machine) 285 { 286 if (machine->numa_state->num_nodes) { 287 int i; 288 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 289 if (machine->numa_state->nodes[i].node_mem) { 290 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 291 machine->ram_size); 292 } 293 } 294 } 295 return machine->ram_size; 296 } 297 298 bool spapr_machine_using_legacy_numa(SpaprMachineState *spapr) 299 { 300 MachineState *machine = MACHINE(spapr); 301 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 302 303 return smc->pre_5_2_numa_associativity || 304 machine->numa_state->num_nodes <= 1; 305 } 306 307 static void add_str(GString *s, const gchar *s1) 308 { 309 g_string_append_len(s, s1, strlen(s1) + 1); 310 } 311 312 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 313 hwaddr start, hwaddr size) 314 { 315 char mem_name[32]; 316 uint64_t mem_reg_property[2]; 317 int off; 318 319 mem_reg_property[0] = cpu_to_be64(start); 320 mem_reg_property[1] = cpu_to_be64(size); 321 322 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 323 off = fdt_add_subnode(fdt, 0, mem_name); 324 _FDT(off); 325 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 326 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 327 sizeof(mem_reg_property)))); 328 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 329 return off; 330 } 331 332 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 333 { 334 MemoryDeviceInfoList *info; 335 336 for (info = list; info; info = info->next) { 337 MemoryDeviceInfo *value = info->value; 338 339 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 340 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 341 342 if (addr >= pcdimm_info->addr && 343 addr < (pcdimm_info->addr + pcdimm_info->size)) { 344 return pcdimm_info->node; 345 } 346 } 347 } 348 349 return -1; 350 } 351 352 struct sPAPRDrconfCellV2 { 353 uint32_t seq_lmbs; 354 uint64_t base_addr; 355 uint32_t drc_index; 356 uint32_t aa_index; 357 uint32_t flags; 358 } QEMU_PACKED; 359 360 typedef struct DrconfCellQueue { 361 struct sPAPRDrconfCellV2 cell; 362 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 363 } DrconfCellQueue; 364 365 static DrconfCellQueue * 366 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 367 uint32_t drc_index, uint32_t aa_index, 368 uint32_t flags) 369 { 370 DrconfCellQueue *elem; 371 372 elem = g_malloc0(sizeof(*elem)); 373 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 374 elem->cell.base_addr = cpu_to_be64(base_addr); 375 elem->cell.drc_index = cpu_to_be32(drc_index); 376 elem->cell.aa_index = cpu_to_be32(aa_index); 377 elem->cell.flags = cpu_to_be32(flags); 378 379 return elem; 380 } 381 382 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 383 int offset, MemoryDeviceInfoList *dimms) 384 { 385 MachineState *machine = MACHINE(spapr); 386 uint8_t *int_buf, *cur_index; 387 int ret; 388 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 389 uint64_t addr, cur_addr, size; 390 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 391 uint64_t mem_end = machine->device_memory->base + 392 memory_region_size(&machine->device_memory->mr); 393 uint32_t node, buf_len, nr_entries = 0; 394 SpaprDrc *drc; 395 DrconfCellQueue *elem, *next; 396 MemoryDeviceInfoList *info; 397 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 398 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 399 400 /* Entry to cover RAM and the gap area */ 401 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 402 SPAPR_LMB_FLAGS_RESERVED | 403 SPAPR_LMB_FLAGS_DRC_INVALID); 404 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 405 nr_entries++; 406 407 cur_addr = machine->device_memory->base; 408 for (info = dimms; info; info = info->next) { 409 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 410 411 addr = di->addr; 412 size = di->size; 413 node = di->node; 414 415 /* 416 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 417 * area is marked hotpluggable in the next iteration for the bigger 418 * chunk including the NVDIMM occupied area. 419 */ 420 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 421 continue; 422 423 /* Entry for hot-pluggable area */ 424 if (cur_addr < addr) { 425 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 426 g_assert(drc); 427 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 428 cur_addr, spapr_drc_index(drc), -1, 0); 429 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 430 nr_entries++; 431 } 432 433 /* Entry for DIMM */ 434 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 435 g_assert(drc); 436 elem = spapr_get_drconf_cell(size / lmb_size, addr, 437 spapr_drc_index(drc), node, 438 (SPAPR_LMB_FLAGS_ASSIGNED | 439 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 440 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 441 nr_entries++; 442 cur_addr = addr + size; 443 } 444 445 /* Entry for remaining hotpluggable area */ 446 if (cur_addr < mem_end) { 447 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 448 g_assert(drc); 449 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 450 cur_addr, spapr_drc_index(drc), -1, 0); 451 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 452 nr_entries++; 453 } 454 455 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 456 int_buf = cur_index = g_malloc0(buf_len); 457 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 458 cur_index += sizeof(nr_entries); 459 460 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 461 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 462 cur_index += sizeof(elem->cell); 463 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 464 g_free(elem); 465 } 466 467 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 468 g_free(int_buf); 469 if (ret < 0) { 470 return -1; 471 } 472 return 0; 473 } 474 475 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 476 int offset, MemoryDeviceInfoList *dimms) 477 { 478 MachineState *machine = MACHINE(spapr); 479 int i, ret; 480 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 481 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 482 uint32_t nr_lmbs = (machine->device_memory->base + 483 memory_region_size(&machine->device_memory->mr)) / 484 lmb_size; 485 uint32_t *int_buf, *cur_index, buf_len; 486 487 /* 488 * Allocate enough buffer size to fit in ibm,dynamic-memory 489 */ 490 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 491 cur_index = int_buf = g_malloc0(buf_len); 492 int_buf[0] = cpu_to_be32(nr_lmbs); 493 cur_index++; 494 for (i = 0; i < nr_lmbs; i++) { 495 uint64_t addr = i * lmb_size; 496 uint32_t *dynamic_memory = cur_index; 497 498 if (i >= device_lmb_start) { 499 SpaprDrc *drc; 500 501 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 502 g_assert(drc); 503 504 dynamic_memory[0] = cpu_to_be32(addr >> 32); 505 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 506 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 507 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 508 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 509 if (memory_region_present(get_system_memory(), addr)) { 510 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 511 } else { 512 dynamic_memory[5] = cpu_to_be32(0); 513 } 514 } else { 515 /* 516 * LMB information for RMA, boot time RAM and gap b/n RAM and 517 * device memory region -- all these are marked as reserved 518 * and as having no valid DRC. 519 */ 520 dynamic_memory[0] = cpu_to_be32(addr >> 32); 521 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 522 dynamic_memory[2] = cpu_to_be32(0); 523 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 524 dynamic_memory[4] = cpu_to_be32(-1); 525 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 526 SPAPR_LMB_FLAGS_DRC_INVALID); 527 } 528 529 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 530 } 531 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 532 g_free(int_buf); 533 if (ret < 0) { 534 return -1; 535 } 536 return 0; 537 } 538 539 /* 540 * Adds ibm,dynamic-reconfiguration-memory node. 541 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 542 * of this device tree node. 543 */ 544 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 545 void *fdt) 546 { 547 MachineState *machine = MACHINE(spapr); 548 int ret, offset; 549 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 550 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 551 cpu_to_be32(lmb_size & 0xffffffff)}; 552 MemoryDeviceInfoList *dimms = NULL; 553 554 /* 555 * Don't create the node if there is no device memory 556 */ 557 if (machine->ram_size == machine->maxram_size) { 558 return 0; 559 } 560 561 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 562 563 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 564 sizeof(prop_lmb_size)); 565 if (ret < 0) { 566 return ret; 567 } 568 569 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 570 if (ret < 0) { 571 return ret; 572 } 573 574 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 575 if (ret < 0) { 576 return ret; 577 } 578 579 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 580 dimms = qmp_memory_device_list(); 581 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 582 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 583 } else { 584 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 585 } 586 qapi_free_MemoryDeviceInfoList(dimms); 587 588 if (ret < 0) { 589 return ret; 590 } 591 592 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 593 594 return ret; 595 } 596 597 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 598 { 599 MachineState *machine = MACHINE(spapr); 600 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 601 hwaddr mem_start, node_size; 602 int i, nb_nodes = machine->numa_state->num_nodes; 603 NodeInfo *nodes = machine->numa_state->nodes; 604 605 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 606 if (!nodes[i].node_mem) { 607 continue; 608 } 609 if (mem_start >= machine->ram_size) { 610 node_size = 0; 611 } else { 612 node_size = nodes[i].node_mem; 613 if (node_size > machine->ram_size - mem_start) { 614 node_size = machine->ram_size - mem_start; 615 } 616 } 617 if (!mem_start) { 618 /* spapr_machine_init() checks for rma_size <= node0_size 619 * already */ 620 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 621 mem_start += spapr->rma_size; 622 node_size -= spapr->rma_size; 623 } 624 for ( ; node_size; ) { 625 hwaddr sizetmp = pow2floor(node_size); 626 627 /* mem_start != 0 here */ 628 if (ctzl(mem_start) < ctzl(sizetmp)) { 629 sizetmp = 1ULL << ctzl(mem_start); 630 } 631 632 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 633 node_size -= sizetmp; 634 mem_start += sizetmp; 635 } 636 } 637 638 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 639 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 640 int ret; 641 642 g_assert(smc->dr_lmb_enabled); 643 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 644 if (ret) { 645 return ret; 646 } 647 } 648 649 return 0; 650 } 651 652 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 653 SpaprMachineState *spapr) 654 { 655 MachineState *ms = MACHINE(spapr); 656 PowerPCCPU *cpu = POWERPC_CPU(cs); 657 CPUPPCState *env = &cpu->env; 658 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 659 int index = spapr_get_vcpu_id(cpu); 660 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 661 0xffffffff, 0xffffffff}; 662 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 663 : SPAPR_TIMEBASE_FREQ; 664 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 665 uint32_t page_sizes_prop[64]; 666 size_t page_sizes_prop_size; 667 unsigned int smp_threads = ms->smp.threads; 668 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 669 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 670 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 671 SpaprDrc *drc; 672 int drc_index; 673 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 674 int i; 675 676 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 677 if (drc) { 678 drc_index = spapr_drc_index(drc); 679 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 680 } 681 682 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 683 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 684 685 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 686 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 687 env->dcache_line_size))); 688 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 689 env->dcache_line_size))); 690 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 691 env->icache_line_size))); 692 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 693 env->icache_line_size))); 694 695 if (pcc->l1_dcache_size) { 696 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 697 pcc->l1_dcache_size))); 698 } else { 699 warn_report("Unknown L1 dcache size for cpu"); 700 } 701 if (pcc->l1_icache_size) { 702 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 703 pcc->l1_icache_size))); 704 } else { 705 warn_report("Unknown L1 icache size for cpu"); 706 } 707 708 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 709 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 710 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 711 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 712 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 713 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 714 715 if (env->spr_cb[SPR_PURR].oea_read) { 716 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 717 } 718 if (env->spr_cb[SPR_SPURR].oea_read) { 719 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 720 } 721 722 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 723 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 724 segs, sizeof(segs)))); 725 } 726 727 /* Advertise VSX (vector extensions) if available 728 * 1 == VMX / Altivec available 729 * 2 == VSX available 730 * 731 * Only CPUs for which we create core types in spapr_cpu_core.c 732 * are possible, and all of those have VMX */ 733 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 734 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 735 } else { 736 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 737 } 738 739 /* Advertise DFP (Decimal Floating Point) if available 740 * 0 / no property == no DFP 741 * 1 == DFP available */ 742 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 743 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 744 } 745 746 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 747 sizeof(page_sizes_prop)); 748 if (page_sizes_prop_size) { 749 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 750 page_sizes_prop, page_sizes_prop_size))); 751 } 752 753 spapr_dt_pa_features(spapr, cpu, fdt, offset); 754 755 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 756 cs->cpu_index / vcpus_per_socket))); 757 758 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 759 pft_size_prop, sizeof(pft_size_prop)))); 760 761 if (ms->numa_state->num_nodes > 1) { 762 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 763 } 764 765 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 766 767 if (pcc->radix_page_info) { 768 for (i = 0; i < pcc->radix_page_info->count; i++) { 769 radix_AP_encodings[i] = 770 cpu_to_be32(pcc->radix_page_info->entries[i]); 771 } 772 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 773 radix_AP_encodings, 774 pcc->radix_page_info->count * 775 sizeof(radix_AP_encodings[0])))); 776 } 777 778 /* 779 * We set this property to let the guest know that it can use the large 780 * decrementer and its width in bits. 781 */ 782 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 783 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 784 pcc->lrg_decr_bits))); 785 } 786 787 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 788 { 789 CPUState **rev; 790 CPUState *cs; 791 int n_cpus; 792 int cpus_offset; 793 char *nodename; 794 int i; 795 796 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 797 _FDT(cpus_offset); 798 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 799 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 800 801 /* 802 * We walk the CPUs in reverse order to ensure that CPU DT nodes 803 * created by fdt_add_subnode() end up in the right order in FDT 804 * for the guest kernel the enumerate the CPUs correctly. 805 * 806 * The CPU list cannot be traversed in reverse order, so we need 807 * to do extra work. 808 */ 809 n_cpus = 0; 810 rev = NULL; 811 CPU_FOREACH(cs) { 812 rev = g_renew(CPUState *, rev, n_cpus + 1); 813 rev[n_cpus++] = cs; 814 } 815 816 for (i = n_cpus - 1; i >= 0; i--) { 817 CPUState *cs = rev[i]; 818 PowerPCCPU *cpu = POWERPC_CPU(cs); 819 int index = spapr_get_vcpu_id(cpu); 820 DeviceClass *dc = DEVICE_GET_CLASS(cs); 821 int offset; 822 823 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 824 continue; 825 } 826 827 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 828 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 829 g_free(nodename); 830 _FDT(offset); 831 spapr_dt_cpu(cs, fdt, offset, spapr); 832 } 833 834 g_free(rev); 835 } 836 837 static int spapr_dt_rng(void *fdt) 838 { 839 int node; 840 int ret; 841 842 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 843 if (node <= 0) { 844 return -1; 845 } 846 ret = fdt_setprop_string(fdt, node, "device_type", 847 "ibm,platform-facilities"); 848 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 849 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 850 851 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 852 if (node <= 0) { 853 return -1; 854 } 855 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 856 857 return ret ? -1 : 0; 858 } 859 860 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 861 { 862 MachineState *ms = MACHINE(spapr); 863 int rtas; 864 GString *hypertas = g_string_sized_new(256); 865 GString *qemu_hypertas = g_string_sized_new(256); 866 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 867 memory_region_size(&MACHINE(spapr)->device_memory->mr); 868 uint32_t lrdr_capacity[] = { 869 cpu_to_be32(max_device_addr >> 32), 870 cpu_to_be32(max_device_addr & 0xffffffff), 871 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 872 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 873 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 874 }; 875 876 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 877 878 /* hypertas */ 879 add_str(hypertas, "hcall-pft"); 880 add_str(hypertas, "hcall-term"); 881 add_str(hypertas, "hcall-dabr"); 882 add_str(hypertas, "hcall-interrupt"); 883 add_str(hypertas, "hcall-tce"); 884 add_str(hypertas, "hcall-vio"); 885 add_str(hypertas, "hcall-splpar"); 886 add_str(hypertas, "hcall-join"); 887 add_str(hypertas, "hcall-bulk"); 888 add_str(hypertas, "hcall-set-mode"); 889 add_str(hypertas, "hcall-sprg0"); 890 add_str(hypertas, "hcall-copy"); 891 add_str(hypertas, "hcall-debug"); 892 add_str(hypertas, "hcall-vphn"); 893 add_str(qemu_hypertas, "hcall-memop1"); 894 895 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 896 add_str(hypertas, "hcall-multi-tce"); 897 } 898 899 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 900 add_str(hypertas, "hcall-hpt-resize"); 901 } 902 903 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 904 hypertas->str, hypertas->len)); 905 g_string_free(hypertas, TRUE); 906 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 907 qemu_hypertas->str, qemu_hypertas->len)); 908 g_string_free(qemu_hypertas, TRUE); 909 910 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 911 912 /* 913 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 914 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 915 * 916 * The system reset requirements are driven by existing Linux and PowerVM 917 * implementation which (contrary to PAPR) saves r3 in the error log 918 * structure like machine check, so Linux expects to find the saved r3 919 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 920 * does not look at the error value). 921 * 922 * System reset interrupts are not subject to interlock like machine 923 * check, so this memory area could be corrupted if the sreset is 924 * interrupted by a machine check (or vice versa) if it was shared. To 925 * prevent this, system reset uses per-CPU areas for the sreset save 926 * area. A system reset that interrupts a system reset handler could 927 * still overwrite this area, but Linux doesn't try to recover in that 928 * case anyway. 929 * 930 * The extra 8 bytes is required because Linux's FWNMI error log check 931 * is off-by-one. 932 */ 933 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX + 934 ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t))); 935 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 936 RTAS_ERROR_LOG_MAX)); 937 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 938 RTAS_EVENT_SCAN_RATE)); 939 940 g_assert(msi_nonbroken); 941 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 942 943 /* 944 * According to PAPR, rtas ibm,os-term does not guarantee a return 945 * back to the guest cpu. 946 * 947 * While an additional ibm,extended-os-term property indicates 948 * that rtas call return will always occur. Set this property. 949 */ 950 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 951 952 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 953 lrdr_capacity, sizeof(lrdr_capacity))); 954 955 spapr_dt_rtas_tokens(fdt, rtas); 956 } 957 958 /* 959 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 960 * and the XIVE features that the guest may request and thus the valid 961 * values for bytes 23..26 of option vector 5: 962 */ 963 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 964 int chosen) 965 { 966 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 967 968 char val[2 * 4] = { 969 23, 0x00, /* XICS / XIVE mode */ 970 24, 0x00, /* Hash/Radix, filled in below. */ 971 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 972 26, 0x40, /* Radix options: GTSE == yes. */ 973 }; 974 975 if (spapr->irq->xics && spapr->irq->xive) { 976 val[1] = SPAPR_OV5_XIVE_BOTH; 977 } else if (spapr->irq->xive) { 978 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 979 } else { 980 assert(spapr->irq->xics); 981 val[1] = SPAPR_OV5_XIVE_LEGACY; 982 } 983 984 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 985 first_ppc_cpu->compat_pvr)) { 986 /* 987 * If we're in a pre POWER9 compat mode then the guest should 988 * do hash and use the legacy interrupt mode 989 */ 990 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 991 val[3] = 0x00; /* Hash */ 992 } else if (kvm_enabled()) { 993 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 994 val[3] = 0x80; /* OV5_MMU_BOTH */ 995 } else if (kvmppc_has_cap_mmu_radix()) { 996 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 997 } else { 998 val[3] = 0x00; /* Hash */ 999 } 1000 } else { 1001 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1002 val[3] = 0xC0; 1003 } 1004 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1005 val, sizeof(val))); 1006 } 1007 1008 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1009 { 1010 MachineState *machine = MACHINE(spapr); 1011 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1012 int chosen; 1013 1014 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1015 1016 if (reset) { 1017 const char *boot_device = machine->boot_order; 1018 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1019 size_t cb = 0; 1020 char *bootlist = get_boot_devices_list(&cb); 1021 1022 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1023 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1024 machine->kernel_cmdline)); 1025 } 1026 1027 if (spapr->initrd_size) { 1028 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1029 spapr->initrd_base)); 1030 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1031 spapr->initrd_base + spapr->initrd_size)); 1032 } 1033 1034 if (spapr->kernel_size) { 1035 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1036 cpu_to_be64(spapr->kernel_size) }; 1037 1038 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1039 &kprop, sizeof(kprop))); 1040 if (spapr->kernel_le) { 1041 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1042 } 1043 } 1044 if (boot_menu) { 1045 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1046 } 1047 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1048 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1049 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1050 1051 if (cb && bootlist) { 1052 int i; 1053 1054 for (i = 0; i < cb; i++) { 1055 if (bootlist[i] == '\n') { 1056 bootlist[i] = ' '; 1057 } 1058 } 1059 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1060 } 1061 1062 if (boot_device && strlen(boot_device)) { 1063 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1064 } 1065 1066 if (!spapr->has_graphics && stdout_path) { 1067 /* 1068 * "linux,stdout-path" and "stdout" properties are 1069 * deprecated by linux kernel. New platforms should only 1070 * use the "stdout-path" property. Set the new property 1071 * and continue using older property to remain compatible 1072 * with the existing firmware. 1073 */ 1074 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1075 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1076 } 1077 1078 /* 1079 * We can deal with BAR reallocation just fine, advertise it 1080 * to the guest 1081 */ 1082 if (smc->linux_pci_probe) { 1083 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1084 } 1085 1086 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1087 1088 g_free(stdout_path); 1089 g_free(bootlist); 1090 } 1091 1092 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1093 } 1094 1095 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1096 { 1097 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1098 * KVM to work under pHyp with some guest co-operation */ 1099 int hypervisor; 1100 uint8_t hypercall[16]; 1101 1102 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1103 /* indicate KVM hypercall interface */ 1104 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1105 if (kvmppc_has_cap_fixup_hcalls()) { 1106 /* 1107 * Older KVM versions with older guest kernels were broken 1108 * with the magic page, don't allow the guest to map it. 1109 */ 1110 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1111 sizeof(hypercall))) { 1112 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1113 hypercall, sizeof(hypercall))); 1114 } 1115 } 1116 } 1117 1118 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1119 { 1120 MachineState *machine = MACHINE(spapr); 1121 MachineClass *mc = MACHINE_GET_CLASS(machine); 1122 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1123 uint32_t root_drc_type_mask = 0; 1124 int ret; 1125 void *fdt; 1126 SpaprPhbState *phb; 1127 char *buf; 1128 1129 fdt = g_malloc0(space); 1130 _FDT((fdt_create_empty_tree(fdt, space))); 1131 1132 /* Root node */ 1133 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1134 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1135 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1136 1137 /* Guest UUID & Name*/ 1138 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1139 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1140 if (qemu_uuid_set) { 1141 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1142 } 1143 g_free(buf); 1144 1145 if (qemu_get_vm_name()) { 1146 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1147 qemu_get_vm_name())); 1148 } 1149 1150 /* Host Model & Serial Number */ 1151 if (spapr->host_model) { 1152 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1153 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1154 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1155 g_free(buf); 1156 } 1157 1158 if (spapr->host_serial) { 1159 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1160 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1161 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1162 g_free(buf); 1163 } 1164 1165 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1166 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1167 1168 /* /interrupt controller */ 1169 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1170 1171 ret = spapr_dt_memory(spapr, fdt); 1172 if (ret < 0) { 1173 error_report("couldn't setup memory nodes in fdt"); 1174 exit(1); 1175 } 1176 1177 /* /vdevice */ 1178 spapr_dt_vdevice(spapr->vio_bus, fdt); 1179 1180 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1181 ret = spapr_dt_rng(fdt); 1182 if (ret < 0) { 1183 error_report("could not set up rng device in the fdt"); 1184 exit(1); 1185 } 1186 } 1187 1188 QLIST_FOREACH(phb, &spapr->phbs, list) { 1189 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1190 if (ret < 0) { 1191 error_report("couldn't setup PCI devices in fdt"); 1192 exit(1); 1193 } 1194 } 1195 1196 spapr_dt_cpus(fdt, spapr); 1197 1198 /* ibm,drc-indexes and friends */ 1199 if (smc->dr_lmb_enabled) { 1200 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1201 } 1202 if (smc->dr_phb_enabled) { 1203 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1204 } 1205 if (mc->nvdimm_supported) { 1206 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1207 } 1208 if (root_drc_type_mask) { 1209 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1210 } 1211 1212 if (mc->has_hotpluggable_cpus) { 1213 int offset = fdt_path_offset(fdt, "/cpus"); 1214 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1215 if (ret < 0) { 1216 error_report("Couldn't set up CPU DR device tree properties"); 1217 exit(1); 1218 } 1219 } 1220 1221 /* /event-sources */ 1222 spapr_dt_events(spapr, fdt); 1223 1224 /* /rtas */ 1225 spapr_dt_rtas(spapr, fdt); 1226 1227 /* /chosen */ 1228 spapr_dt_chosen(spapr, fdt, reset); 1229 1230 /* /hypervisor */ 1231 if (kvm_enabled()) { 1232 spapr_dt_hypervisor(spapr, fdt); 1233 } 1234 1235 /* Build memory reserve map */ 1236 if (reset) { 1237 if (spapr->kernel_size) { 1238 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1239 spapr->kernel_size))); 1240 } 1241 if (spapr->initrd_size) { 1242 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1243 spapr->initrd_size))); 1244 } 1245 } 1246 1247 /* NVDIMM devices */ 1248 if (mc->nvdimm_supported) { 1249 spapr_dt_persistent_memory(spapr, fdt); 1250 } 1251 1252 return fdt; 1253 } 1254 1255 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1256 { 1257 SpaprMachineState *spapr = opaque; 1258 1259 return (addr & 0x0fffffff) + spapr->kernel_addr; 1260 } 1261 1262 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1263 PowerPCCPU *cpu) 1264 { 1265 CPUPPCState *env = &cpu->env; 1266 1267 /* The TCG path should also be holding the BQL at this point */ 1268 g_assert(qemu_mutex_iothread_locked()); 1269 1270 if (msr_pr) { 1271 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1272 env->gpr[3] = H_PRIVILEGE; 1273 } else { 1274 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1275 } 1276 } 1277 1278 struct LPCRSyncState { 1279 target_ulong value; 1280 target_ulong mask; 1281 }; 1282 1283 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1284 { 1285 struct LPCRSyncState *s = arg.host_ptr; 1286 PowerPCCPU *cpu = POWERPC_CPU(cs); 1287 CPUPPCState *env = &cpu->env; 1288 target_ulong lpcr; 1289 1290 cpu_synchronize_state(cs); 1291 lpcr = env->spr[SPR_LPCR]; 1292 lpcr &= ~s->mask; 1293 lpcr |= s->value; 1294 ppc_store_lpcr(cpu, lpcr); 1295 } 1296 1297 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1298 { 1299 CPUState *cs; 1300 struct LPCRSyncState s = { 1301 .value = value, 1302 .mask = mask 1303 }; 1304 CPU_FOREACH(cs) { 1305 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1306 } 1307 } 1308 1309 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1310 { 1311 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1312 1313 /* Copy PATE1:GR into PATE0:HR */ 1314 entry->dw0 = spapr->patb_entry & PATE0_HR; 1315 entry->dw1 = spapr->patb_entry; 1316 } 1317 1318 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1319 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1320 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1321 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1322 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1323 1324 /* 1325 * Get the fd to access the kernel htab, re-opening it if necessary 1326 */ 1327 static int get_htab_fd(SpaprMachineState *spapr) 1328 { 1329 Error *local_err = NULL; 1330 1331 if (spapr->htab_fd >= 0) { 1332 return spapr->htab_fd; 1333 } 1334 1335 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1336 if (spapr->htab_fd < 0) { 1337 error_report_err(local_err); 1338 } 1339 1340 return spapr->htab_fd; 1341 } 1342 1343 void close_htab_fd(SpaprMachineState *spapr) 1344 { 1345 if (spapr->htab_fd >= 0) { 1346 close(spapr->htab_fd); 1347 } 1348 spapr->htab_fd = -1; 1349 } 1350 1351 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1352 { 1353 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1354 1355 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1356 } 1357 1358 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1359 { 1360 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1361 1362 assert(kvm_enabled()); 1363 1364 if (!spapr->htab) { 1365 return 0; 1366 } 1367 1368 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1369 } 1370 1371 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1372 hwaddr ptex, int n) 1373 { 1374 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1375 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1376 1377 if (!spapr->htab) { 1378 /* 1379 * HTAB is controlled by KVM. Fetch into temporary buffer 1380 */ 1381 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1382 kvmppc_read_hptes(hptes, ptex, n); 1383 return hptes; 1384 } 1385 1386 /* 1387 * HTAB is controlled by QEMU. Just point to the internally 1388 * accessible PTEG. 1389 */ 1390 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1391 } 1392 1393 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1394 const ppc_hash_pte64_t *hptes, 1395 hwaddr ptex, int n) 1396 { 1397 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1398 1399 if (!spapr->htab) { 1400 g_free((void *)hptes); 1401 } 1402 1403 /* Nothing to do for qemu managed HPT */ 1404 } 1405 1406 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1407 uint64_t pte0, uint64_t pte1) 1408 { 1409 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1410 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1411 1412 if (!spapr->htab) { 1413 kvmppc_write_hpte(ptex, pte0, pte1); 1414 } else { 1415 if (pte0 & HPTE64_V_VALID) { 1416 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1417 /* 1418 * When setting valid, we write PTE1 first. This ensures 1419 * proper synchronization with the reading code in 1420 * ppc_hash64_pteg_search() 1421 */ 1422 smp_wmb(); 1423 stq_p(spapr->htab + offset, pte0); 1424 } else { 1425 stq_p(spapr->htab + offset, pte0); 1426 /* 1427 * When clearing it we set PTE0 first. This ensures proper 1428 * synchronization with the reading code in 1429 * ppc_hash64_pteg_search() 1430 */ 1431 smp_wmb(); 1432 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1433 } 1434 } 1435 } 1436 1437 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1438 uint64_t pte1) 1439 { 1440 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1441 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1442 1443 if (!spapr->htab) { 1444 /* There should always be a hash table when this is called */ 1445 error_report("spapr_hpte_set_c called with no hash table !"); 1446 return; 1447 } 1448 1449 /* The HW performs a non-atomic byte update */ 1450 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1451 } 1452 1453 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1454 uint64_t pte1) 1455 { 1456 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1457 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1458 1459 if (!spapr->htab) { 1460 /* There should always be a hash table when this is called */ 1461 error_report("spapr_hpte_set_r called with no hash table !"); 1462 return; 1463 } 1464 1465 /* The HW performs a non-atomic byte update */ 1466 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1467 } 1468 1469 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1470 { 1471 int shift; 1472 1473 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1474 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1475 * that's much more than is needed for Linux guests */ 1476 shift = ctz64(pow2ceil(ramsize)) - 7; 1477 shift = MAX(shift, 18); /* Minimum architected size */ 1478 shift = MIN(shift, 46); /* Maximum architected size */ 1479 return shift; 1480 } 1481 1482 void spapr_free_hpt(SpaprMachineState *spapr) 1483 { 1484 g_free(spapr->htab); 1485 spapr->htab = NULL; 1486 spapr->htab_shift = 0; 1487 close_htab_fd(spapr); 1488 } 1489 1490 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1491 { 1492 ERRP_GUARD(); 1493 long rc; 1494 1495 /* Clean up any HPT info from a previous boot */ 1496 spapr_free_hpt(spapr); 1497 1498 rc = kvmppc_reset_htab(shift); 1499 1500 if (rc == -EOPNOTSUPP) { 1501 error_setg(errp, "HPT not supported in nested guests"); 1502 return -EOPNOTSUPP; 1503 } 1504 1505 if (rc < 0) { 1506 /* kernel-side HPT needed, but couldn't allocate one */ 1507 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1508 shift); 1509 error_append_hint(errp, "Try smaller maxmem?\n"); 1510 return -errno; 1511 } else if (rc > 0) { 1512 /* kernel-side HPT allocated */ 1513 if (rc != shift) { 1514 error_setg(errp, 1515 "Requested order %d HPT, but kernel allocated order %ld", 1516 shift, rc); 1517 error_append_hint(errp, "Try smaller maxmem?\n"); 1518 return -ENOSPC; 1519 } 1520 1521 spapr->htab_shift = shift; 1522 spapr->htab = NULL; 1523 } else { 1524 /* kernel-side HPT not needed, allocate in userspace instead */ 1525 size_t size = 1ULL << shift; 1526 int i; 1527 1528 spapr->htab = qemu_memalign(size, size); 1529 memset(spapr->htab, 0, size); 1530 spapr->htab_shift = shift; 1531 1532 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1533 DIRTY_HPTE(HPTE(spapr->htab, i)); 1534 } 1535 } 1536 /* We're setting up a hash table, so that means we're not radix */ 1537 spapr->patb_entry = 0; 1538 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1539 return 0; 1540 } 1541 1542 void spapr_setup_hpt(SpaprMachineState *spapr) 1543 { 1544 int hpt_shift; 1545 1546 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1547 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1548 } else { 1549 uint64_t current_ram_size; 1550 1551 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1552 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1553 } 1554 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1555 1556 if (kvm_enabled()) { 1557 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1558 1559 /* Check our RMA fits in the possible VRMA */ 1560 if (vrma_limit < spapr->rma_size) { 1561 error_report("Unable to create %" HWADDR_PRIu 1562 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1563 spapr->rma_size / MiB, vrma_limit / MiB); 1564 exit(EXIT_FAILURE); 1565 } 1566 } 1567 } 1568 1569 static void spapr_machine_reset(MachineState *machine) 1570 { 1571 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1572 PowerPCCPU *first_ppc_cpu; 1573 hwaddr fdt_addr; 1574 void *fdt; 1575 int rc; 1576 1577 kvmppc_svm_off(&error_fatal); 1578 spapr_caps_apply(spapr); 1579 1580 first_ppc_cpu = POWERPC_CPU(first_cpu); 1581 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1582 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1583 spapr->max_compat_pvr)) { 1584 /* 1585 * If using KVM with radix mode available, VCPUs can be started 1586 * without a HPT because KVM will start them in radix mode. 1587 * Set the GR bit in PATE so that we know there is no HPT. 1588 */ 1589 spapr->patb_entry = PATE1_GR; 1590 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1591 } else { 1592 spapr_setup_hpt(spapr); 1593 } 1594 1595 qemu_devices_reset(); 1596 1597 spapr_ovec_cleanup(spapr->ov5_cas); 1598 spapr->ov5_cas = spapr_ovec_new(); 1599 1600 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1601 1602 /* 1603 * This is fixing some of the default configuration of the XIVE 1604 * devices. To be called after the reset of the machine devices. 1605 */ 1606 spapr_irq_reset(spapr, &error_fatal); 1607 1608 /* 1609 * There is no CAS under qtest. Simulate one to please the code that 1610 * depends on spapr->ov5_cas. This is especially needed to test device 1611 * unplug, so we do that before resetting the DRCs. 1612 */ 1613 if (qtest_enabled()) { 1614 spapr_ovec_cleanup(spapr->ov5_cas); 1615 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1616 } 1617 1618 /* DRC reset may cause a device to be unplugged. This will cause troubles 1619 * if this device is used by another device (eg, a running vhost backend 1620 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1621 * situations, we reset DRCs after all devices have been reset. 1622 */ 1623 spapr_drc_reset_all(spapr); 1624 1625 spapr_clear_pending_events(spapr); 1626 1627 /* 1628 * We place the device tree and RTAS just below either the top of the RMA, 1629 * or just below 2GB, whichever is lower, so that it can be 1630 * processed with 32-bit real mode code if necessary 1631 */ 1632 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1633 1634 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1635 1636 rc = fdt_pack(fdt); 1637 1638 /* Should only fail if we've built a corrupted tree */ 1639 assert(rc == 0); 1640 1641 /* Load the fdt */ 1642 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1643 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1644 g_free(spapr->fdt_blob); 1645 spapr->fdt_size = fdt_totalsize(fdt); 1646 spapr->fdt_initial_size = spapr->fdt_size; 1647 spapr->fdt_blob = fdt; 1648 1649 /* Set up the entry state */ 1650 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); 1651 first_ppc_cpu->env.gpr[5] = 0; 1652 1653 spapr->fwnmi_system_reset_addr = -1; 1654 spapr->fwnmi_machine_check_addr = -1; 1655 spapr->fwnmi_machine_check_interlock = -1; 1656 1657 /* Signal all vCPUs waiting on this condition */ 1658 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1659 1660 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1661 } 1662 1663 static void spapr_create_nvram(SpaprMachineState *spapr) 1664 { 1665 DeviceState *dev = qdev_new("spapr-nvram"); 1666 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1667 1668 if (dinfo) { 1669 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1670 &error_fatal); 1671 } 1672 1673 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1674 1675 spapr->nvram = (struct SpaprNvram *)dev; 1676 } 1677 1678 static void spapr_rtc_create(SpaprMachineState *spapr) 1679 { 1680 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1681 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1682 &error_fatal, NULL); 1683 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1684 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1685 "date"); 1686 } 1687 1688 /* Returns whether we want to use VGA or not */ 1689 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1690 { 1691 switch (vga_interface_type) { 1692 case VGA_NONE: 1693 return false; 1694 case VGA_DEVICE: 1695 return true; 1696 case VGA_STD: 1697 case VGA_VIRTIO: 1698 case VGA_CIRRUS: 1699 return pci_vga_init(pci_bus) != NULL; 1700 default: 1701 error_setg(errp, 1702 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1703 return false; 1704 } 1705 } 1706 1707 static int spapr_pre_load(void *opaque) 1708 { 1709 int rc; 1710 1711 rc = spapr_caps_pre_load(opaque); 1712 if (rc) { 1713 return rc; 1714 } 1715 1716 return 0; 1717 } 1718 1719 static int spapr_post_load(void *opaque, int version_id) 1720 { 1721 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1722 int err = 0; 1723 1724 err = spapr_caps_post_migration(spapr); 1725 if (err) { 1726 return err; 1727 } 1728 1729 /* 1730 * In earlier versions, there was no separate qdev for the PAPR 1731 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1732 * So when migrating from those versions, poke the incoming offset 1733 * value into the RTC device 1734 */ 1735 if (version_id < 3) { 1736 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1737 if (err) { 1738 return err; 1739 } 1740 } 1741 1742 if (kvm_enabled() && spapr->patb_entry) { 1743 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1744 bool radix = !!(spapr->patb_entry & PATE1_GR); 1745 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1746 1747 /* 1748 * Update LPCR:HR and UPRT as they may not be set properly in 1749 * the stream 1750 */ 1751 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1752 LPCR_HR | LPCR_UPRT); 1753 1754 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1755 if (err) { 1756 error_report("Process table config unsupported by the host"); 1757 return -EINVAL; 1758 } 1759 } 1760 1761 err = spapr_irq_post_load(spapr, version_id); 1762 if (err) { 1763 return err; 1764 } 1765 1766 return err; 1767 } 1768 1769 static int spapr_pre_save(void *opaque) 1770 { 1771 int rc; 1772 1773 rc = spapr_caps_pre_save(opaque); 1774 if (rc) { 1775 return rc; 1776 } 1777 1778 return 0; 1779 } 1780 1781 static bool version_before_3(void *opaque, int version_id) 1782 { 1783 return version_id < 3; 1784 } 1785 1786 static bool spapr_pending_events_needed(void *opaque) 1787 { 1788 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1789 return !QTAILQ_EMPTY(&spapr->pending_events); 1790 } 1791 1792 static const VMStateDescription vmstate_spapr_event_entry = { 1793 .name = "spapr_event_log_entry", 1794 .version_id = 1, 1795 .minimum_version_id = 1, 1796 .fields = (VMStateField[]) { 1797 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1798 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1799 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1800 NULL, extended_length), 1801 VMSTATE_END_OF_LIST() 1802 }, 1803 }; 1804 1805 static const VMStateDescription vmstate_spapr_pending_events = { 1806 .name = "spapr_pending_events", 1807 .version_id = 1, 1808 .minimum_version_id = 1, 1809 .needed = spapr_pending_events_needed, 1810 .fields = (VMStateField[]) { 1811 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1812 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1813 VMSTATE_END_OF_LIST() 1814 }, 1815 }; 1816 1817 static bool spapr_ov5_cas_needed(void *opaque) 1818 { 1819 SpaprMachineState *spapr = opaque; 1820 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1821 bool cas_needed; 1822 1823 /* Prior to the introduction of SpaprOptionVector, we had two option 1824 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1825 * Both of these options encode machine topology into the device-tree 1826 * in such a way that the now-booted OS should still be able to interact 1827 * appropriately with QEMU regardless of what options were actually 1828 * negotiatied on the source side. 1829 * 1830 * As such, we can avoid migrating the CAS-negotiated options if these 1831 * are the only options available on the current machine/platform. 1832 * Since these are the only options available for pseries-2.7 and 1833 * earlier, this allows us to maintain old->new/new->old migration 1834 * compatibility. 1835 * 1836 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1837 * via default pseries-2.8 machines and explicit command-line parameters. 1838 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1839 * of the actual CAS-negotiated values to continue working properly. For 1840 * example, availability of memory unplug depends on knowing whether 1841 * OV5_HP_EVT was negotiated via CAS. 1842 * 1843 * Thus, for any cases where the set of available CAS-negotiatable 1844 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1845 * include the CAS-negotiated options in the migration stream, unless 1846 * if they affect boot time behaviour only. 1847 */ 1848 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1849 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1850 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1851 1852 /* We need extra information if we have any bits outside the mask 1853 * defined above */ 1854 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1855 1856 spapr_ovec_cleanup(ov5_mask); 1857 1858 return cas_needed; 1859 } 1860 1861 static const VMStateDescription vmstate_spapr_ov5_cas = { 1862 .name = "spapr_option_vector_ov5_cas", 1863 .version_id = 1, 1864 .minimum_version_id = 1, 1865 .needed = spapr_ov5_cas_needed, 1866 .fields = (VMStateField[]) { 1867 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1868 vmstate_spapr_ovec, SpaprOptionVector), 1869 VMSTATE_END_OF_LIST() 1870 }, 1871 }; 1872 1873 static bool spapr_patb_entry_needed(void *opaque) 1874 { 1875 SpaprMachineState *spapr = opaque; 1876 1877 return !!spapr->patb_entry; 1878 } 1879 1880 static const VMStateDescription vmstate_spapr_patb_entry = { 1881 .name = "spapr_patb_entry", 1882 .version_id = 1, 1883 .minimum_version_id = 1, 1884 .needed = spapr_patb_entry_needed, 1885 .fields = (VMStateField[]) { 1886 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1887 VMSTATE_END_OF_LIST() 1888 }, 1889 }; 1890 1891 static bool spapr_irq_map_needed(void *opaque) 1892 { 1893 SpaprMachineState *spapr = opaque; 1894 1895 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1896 } 1897 1898 static const VMStateDescription vmstate_spapr_irq_map = { 1899 .name = "spapr_irq_map", 1900 .version_id = 1, 1901 .minimum_version_id = 1, 1902 .needed = spapr_irq_map_needed, 1903 .fields = (VMStateField[]) { 1904 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1905 VMSTATE_END_OF_LIST() 1906 }, 1907 }; 1908 1909 static bool spapr_dtb_needed(void *opaque) 1910 { 1911 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1912 1913 return smc->update_dt_enabled; 1914 } 1915 1916 static int spapr_dtb_pre_load(void *opaque) 1917 { 1918 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1919 1920 g_free(spapr->fdt_blob); 1921 spapr->fdt_blob = NULL; 1922 spapr->fdt_size = 0; 1923 1924 return 0; 1925 } 1926 1927 static const VMStateDescription vmstate_spapr_dtb = { 1928 .name = "spapr_dtb", 1929 .version_id = 1, 1930 .minimum_version_id = 1, 1931 .needed = spapr_dtb_needed, 1932 .pre_load = spapr_dtb_pre_load, 1933 .fields = (VMStateField[]) { 1934 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1935 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1936 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1937 fdt_size), 1938 VMSTATE_END_OF_LIST() 1939 }, 1940 }; 1941 1942 static bool spapr_fwnmi_needed(void *opaque) 1943 { 1944 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1945 1946 return spapr->fwnmi_machine_check_addr != -1; 1947 } 1948 1949 static int spapr_fwnmi_pre_save(void *opaque) 1950 { 1951 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1952 1953 /* 1954 * Check if machine check handling is in progress and print a 1955 * warning message. 1956 */ 1957 if (spapr->fwnmi_machine_check_interlock != -1) { 1958 warn_report("A machine check is being handled during migration. The" 1959 "handler may run and log hardware error on the destination"); 1960 } 1961 1962 return 0; 1963 } 1964 1965 static const VMStateDescription vmstate_spapr_fwnmi = { 1966 .name = "spapr_fwnmi", 1967 .version_id = 1, 1968 .minimum_version_id = 1, 1969 .needed = spapr_fwnmi_needed, 1970 .pre_save = spapr_fwnmi_pre_save, 1971 .fields = (VMStateField[]) { 1972 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 1973 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 1974 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 1975 VMSTATE_END_OF_LIST() 1976 }, 1977 }; 1978 1979 static const VMStateDescription vmstate_spapr = { 1980 .name = "spapr", 1981 .version_id = 3, 1982 .minimum_version_id = 1, 1983 .pre_load = spapr_pre_load, 1984 .post_load = spapr_post_load, 1985 .pre_save = spapr_pre_save, 1986 .fields = (VMStateField[]) { 1987 /* used to be @next_irq */ 1988 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1989 1990 /* RTC offset */ 1991 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 1992 1993 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 1994 VMSTATE_END_OF_LIST() 1995 }, 1996 .subsections = (const VMStateDescription*[]) { 1997 &vmstate_spapr_ov5_cas, 1998 &vmstate_spapr_patb_entry, 1999 &vmstate_spapr_pending_events, 2000 &vmstate_spapr_cap_htm, 2001 &vmstate_spapr_cap_vsx, 2002 &vmstate_spapr_cap_dfp, 2003 &vmstate_spapr_cap_cfpc, 2004 &vmstate_spapr_cap_sbbc, 2005 &vmstate_spapr_cap_ibs, 2006 &vmstate_spapr_cap_hpt_maxpagesize, 2007 &vmstate_spapr_irq_map, 2008 &vmstate_spapr_cap_nested_kvm_hv, 2009 &vmstate_spapr_dtb, 2010 &vmstate_spapr_cap_large_decr, 2011 &vmstate_spapr_cap_ccf_assist, 2012 &vmstate_spapr_cap_fwnmi, 2013 &vmstate_spapr_fwnmi, 2014 NULL 2015 } 2016 }; 2017 2018 static int htab_save_setup(QEMUFile *f, void *opaque) 2019 { 2020 SpaprMachineState *spapr = opaque; 2021 2022 /* "Iteration" header */ 2023 if (!spapr->htab_shift) { 2024 qemu_put_be32(f, -1); 2025 } else { 2026 qemu_put_be32(f, spapr->htab_shift); 2027 } 2028 2029 if (spapr->htab) { 2030 spapr->htab_save_index = 0; 2031 spapr->htab_first_pass = true; 2032 } else { 2033 if (spapr->htab_shift) { 2034 assert(kvm_enabled()); 2035 } 2036 } 2037 2038 2039 return 0; 2040 } 2041 2042 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2043 int chunkstart, int n_valid, int n_invalid) 2044 { 2045 qemu_put_be32(f, chunkstart); 2046 qemu_put_be16(f, n_valid); 2047 qemu_put_be16(f, n_invalid); 2048 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2049 HASH_PTE_SIZE_64 * n_valid); 2050 } 2051 2052 static void htab_save_end_marker(QEMUFile *f) 2053 { 2054 qemu_put_be32(f, 0); 2055 qemu_put_be16(f, 0); 2056 qemu_put_be16(f, 0); 2057 } 2058 2059 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2060 int64_t max_ns) 2061 { 2062 bool has_timeout = max_ns != -1; 2063 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2064 int index = spapr->htab_save_index; 2065 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2066 2067 assert(spapr->htab_first_pass); 2068 2069 do { 2070 int chunkstart; 2071 2072 /* Consume invalid HPTEs */ 2073 while ((index < htabslots) 2074 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2075 CLEAN_HPTE(HPTE(spapr->htab, index)); 2076 index++; 2077 } 2078 2079 /* Consume valid HPTEs */ 2080 chunkstart = index; 2081 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2082 && HPTE_VALID(HPTE(spapr->htab, index))) { 2083 CLEAN_HPTE(HPTE(spapr->htab, index)); 2084 index++; 2085 } 2086 2087 if (index > chunkstart) { 2088 int n_valid = index - chunkstart; 2089 2090 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2091 2092 if (has_timeout && 2093 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2094 break; 2095 } 2096 } 2097 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2098 2099 if (index >= htabslots) { 2100 assert(index == htabslots); 2101 index = 0; 2102 spapr->htab_first_pass = false; 2103 } 2104 spapr->htab_save_index = index; 2105 } 2106 2107 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2108 int64_t max_ns) 2109 { 2110 bool final = max_ns < 0; 2111 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2112 int examined = 0, sent = 0; 2113 int index = spapr->htab_save_index; 2114 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2115 2116 assert(!spapr->htab_first_pass); 2117 2118 do { 2119 int chunkstart, invalidstart; 2120 2121 /* Consume non-dirty HPTEs */ 2122 while ((index < htabslots) 2123 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2124 index++; 2125 examined++; 2126 } 2127 2128 chunkstart = index; 2129 /* Consume valid dirty HPTEs */ 2130 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2131 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2132 && HPTE_VALID(HPTE(spapr->htab, index))) { 2133 CLEAN_HPTE(HPTE(spapr->htab, index)); 2134 index++; 2135 examined++; 2136 } 2137 2138 invalidstart = index; 2139 /* Consume invalid dirty HPTEs */ 2140 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2141 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2142 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2143 CLEAN_HPTE(HPTE(spapr->htab, index)); 2144 index++; 2145 examined++; 2146 } 2147 2148 if (index > chunkstart) { 2149 int n_valid = invalidstart - chunkstart; 2150 int n_invalid = index - invalidstart; 2151 2152 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2153 sent += index - chunkstart; 2154 2155 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2156 break; 2157 } 2158 } 2159 2160 if (examined >= htabslots) { 2161 break; 2162 } 2163 2164 if (index >= htabslots) { 2165 assert(index == htabslots); 2166 index = 0; 2167 } 2168 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2169 2170 if (index >= htabslots) { 2171 assert(index == htabslots); 2172 index = 0; 2173 } 2174 2175 spapr->htab_save_index = index; 2176 2177 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2178 } 2179 2180 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2181 #define MAX_KVM_BUF_SIZE 2048 2182 2183 static int htab_save_iterate(QEMUFile *f, void *opaque) 2184 { 2185 SpaprMachineState *spapr = opaque; 2186 int fd; 2187 int rc = 0; 2188 2189 /* Iteration header */ 2190 if (!spapr->htab_shift) { 2191 qemu_put_be32(f, -1); 2192 return 1; 2193 } else { 2194 qemu_put_be32(f, 0); 2195 } 2196 2197 if (!spapr->htab) { 2198 assert(kvm_enabled()); 2199 2200 fd = get_htab_fd(spapr); 2201 if (fd < 0) { 2202 return fd; 2203 } 2204 2205 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2206 if (rc < 0) { 2207 return rc; 2208 } 2209 } else if (spapr->htab_first_pass) { 2210 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2211 } else { 2212 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2213 } 2214 2215 htab_save_end_marker(f); 2216 2217 return rc; 2218 } 2219 2220 static int htab_save_complete(QEMUFile *f, void *opaque) 2221 { 2222 SpaprMachineState *spapr = opaque; 2223 int fd; 2224 2225 /* Iteration header */ 2226 if (!spapr->htab_shift) { 2227 qemu_put_be32(f, -1); 2228 return 0; 2229 } else { 2230 qemu_put_be32(f, 0); 2231 } 2232 2233 if (!spapr->htab) { 2234 int rc; 2235 2236 assert(kvm_enabled()); 2237 2238 fd = get_htab_fd(spapr); 2239 if (fd < 0) { 2240 return fd; 2241 } 2242 2243 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2244 if (rc < 0) { 2245 return rc; 2246 } 2247 } else { 2248 if (spapr->htab_first_pass) { 2249 htab_save_first_pass(f, spapr, -1); 2250 } 2251 htab_save_later_pass(f, spapr, -1); 2252 } 2253 2254 /* End marker */ 2255 htab_save_end_marker(f); 2256 2257 return 0; 2258 } 2259 2260 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2261 { 2262 SpaprMachineState *spapr = opaque; 2263 uint32_t section_hdr; 2264 int fd = -1; 2265 Error *local_err = NULL; 2266 2267 if (version_id < 1 || version_id > 1) { 2268 error_report("htab_load() bad version"); 2269 return -EINVAL; 2270 } 2271 2272 section_hdr = qemu_get_be32(f); 2273 2274 if (section_hdr == -1) { 2275 spapr_free_hpt(spapr); 2276 return 0; 2277 } 2278 2279 if (section_hdr) { 2280 int ret; 2281 2282 /* First section gives the htab size */ 2283 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2284 if (ret < 0) { 2285 error_report_err(local_err); 2286 return ret; 2287 } 2288 return 0; 2289 } 2290 2291 if (!spapr->htab) { 2292 assert(kvm_enabled()); 2293 2294 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2295 if (fd < 0) { 2296 error_report_err(local_err); 2297 return fd; 2298 } 2299 } 2300 2301 while (true) { 2302 uint32_t index; 2303 uint16_t n_valid, n_invalid; 2304 2305 index = qemu_get_be32(f); 2306 n_valid = qemu_get_be16(f); 2307 n_invalid = qemu_get_be16(f); 2308 2309 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2310 /* End of Stream */ 2311 break; 2312 } 2313 2314 if ((index + n_valid + n_invalid) > 2315 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2316 /* Bad index in stream */ 2317 error_report( 2318 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2319 index, n_valid, n_invalid, spapr->htab_shift); 2320 return -EINVAL; 2321 } 2322 2323 if (spapr->htab) { 2324 if (n_valid) { 2325 qemu_get_buffer(f, HPTE(spapr->htab, index), 2326 HASH_PTE_SIZE_64 * n_valid); 2327 } 2328 if (n_invalid) { 2329 memset(HPTE(spapr->htab, index + n_valid), 0, 2330 HASH_PTE_SIZE_64 * n_invalid); 2331 } 2332 } else { 2333 int rc; 2334 2335 assert(fd >= 0); 2336 2337 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2338 &local_err); 2339 if (rc < 0) { 2340 error_report_err(local_err); 2341 return rc; 2342 } 2343 } 2344 } 2345 2346 if (!spapr->htab) { 2347 assert(fd >= 0); 2348 close(fd); 2349 } 2350 2351 return 0; 2352 } 2353 2354 static void htab_save_cleanup(void *opaque) 2355 { 2356 SpaprMachineState *spapr = opaque; 2357 2358 close_htab_fd(spapr); 2359 } 2360 2361 static SaveVMHandlers savevm_htab_handlers = { 2362 .save_setup = htab_save_setup, 2363 .save_live_iterate = htab_save_iterate, 2364 .save_live_complete_precopy = htab_save_complete, 2365 .save_cleanup = htab_save_cleanup, 2366 .load_state = htab_load, 2367 }; 2368 2369 static void spapr_boot_set(void *opaque, const char *boot_device, 2370 Error **errp) 2371 { 2372 MachineState *machine = MACHINE(opaque); 2373 machine->boot_order = g_strdup(boot_device); 2374 } 2375 2376 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2377 { 2378 MachineState *machine = MACHINE(spapr); 2379 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2380 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2381 int i; 2382 2383 for (i = 0; i < nr_lmbs; i++) { 2384 uint64_t addr; 2385 2386 addr = i * lmb_size + machine->device_memory->base; 2387 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2388 addr / lmb_size); 2389 } 2390 } 2391 2392 /* 2393 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2394 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2395 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2396 */ 2397 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2398 { 2399 int i; 2400 2401 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2402 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2403 " is not aligned to %" PRIu64 " MiB", 2404 machine->ram_size, 2405 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2406 return; 2407 } 2408 2409 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2410 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2411 " is not aligned to %" PRIu64 " MiB", 2412 machine->ram_size, 2413 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2414 return; 2415 } 2416 2417 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2418 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2419 error_setg(errp, 2420 "Node %d memory size 0x%" PRIx64 2421 " is not aligned to %" PRIu64 " MiB", 2422 i, machine->numa_state->nodes[i].node_mem, 2423 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2424 return; 2425 } 2426 } 2427 } 2428 2429 /* find cpu slot in machine->possible_cpus by core_id */ 2430 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2431 { 2432 int index = id / ms->smp.threads; 2433 2434 if (index >= ms->possible_cpus->len) { 2435 return NULL; 2436 } 2437 if (idx) { 2438 *idx = index; 2439 } 2440 return &ms->possible_cpus->cpus[index]; 2441 } 2442 2443 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2444 { 2445 MachineState *ms = MACHINE(spapr); 2446 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2447 Error *local_err = NULL; 2448 bool vsmt_user = !!spapr->vsmt; 2449 int kvm_smt = kvmppc_smt_threads(); 2450 int ret; 2451 unsigned int smp_threads = ms->smp.threads; 2452 2453 if (!kvm_enabled() && (smp_threads > 1)) { 2454 error_setg(errp, "TCG cannot support more than 1 thread/core " 2455 "on a pseries machine"); 2456 return; 2457 } 2458 if (!is_power_of_2(smp_threads)) { 2459 error_setg(errp, "Cannot support %d threads/core on a pseries " 2460 "machine because it must be a power of 2", smp_threads); 2461 return; 2462 } 2463 2464 /* Detemine the VSMT mode to use: */ 2465 if (vsmt_user) { 2466 if (spapr->vsmt < smp_threads) { 2467 error_setg(errp, "Cannot support VSMT mode %d" 2468 " because it must be >= threads/core (%d)", 2469 spapr->vsmt, smp_threads); 2470 return; 2471 } 2472 /* In this case, spapr->vsmt has been set by the command line */ 2473 } else if (!smc->smp_threads_vsmt) { 2474 /* 2475 * Default VSMT value is tricky, because we need it to be as 2476 * consistent as possible (for migration), but this requires 2477 * changing it for at least some existing cases. We pick 8 as 2478 * the value that we'd get with KVM on POWER8, the 2479 * overwhelmingly common case in production systems. 2480 */ 2481 spapr->vsmt = MAX(8, smp_threads); 2482 } else { 2483 spapr->vsmt = smp_threads; 2484 } 2485 2486 /* KVM: If necessary, set the SMT mode: */ 2487 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2488 ret = kvmppc_set_smt_threads(spapr->vsmt); 2489 if (ret) { 2490 /* Looks like KVM isn't able to change VSMT mode */ 2491 error_setg(&local_err, 2492 "Failed to set KVM's VSMT mode to %d (errno %d)", 2493 spapr->vsmt, ret); 2494 /* We can live with that if the default one is big enough 2495 * for the number of threads, and a submultiple of the one 2496 * we want. In this case we'll waste some vcpu ids, but 2497 * behaviour will be correct */ 2498 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2499 warn_report_err(local_err); 2500 } else { 2501 if (!vsmt_user) { 2502 error_append_hint(&local_err, 2503 "On PPC, a VM with %d threads/core" 2504 " on a host with %d threads/core" 2505 " requires the use of VSMT mode %d.\n", 2506 smp_threads, kvm_smt, spapr->vsmt); 2507 } 2508 kvmppc_error_append_smt_possible_hint(&local_err); 2509 error_propagate(errp, local_err); 2510 } 2511 } 2512 } 2513 /* else TCG: nothing to do currently */ 2514 } 2515 2516 static void spapr_init_cpus(SpaprMachineState *spapr) 2517 { 2518 MachineState *machine = MACHINE(spapr); 2519 MachineClass *mc = MACHINE_GET_CLASS(machine); 2520 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2521 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2522 const CPUArchIdList *possible_cpus; 2523 unsigned int smp_cpus = machine->smp.cpus; 2524 unsigned int smp_threads = machine->smp.threads; 2525 unsigned int max_cpus = machine->smp.max_cpus; 2526 int boot_cores_nr = smp_cpus / smp_threads; 2527 int i; 2528 2529 possible_cpus = mc->possible_cpu_arch_ids(machine); 2530 if (mc->has_hotpluggable_cpus) { 2531 if (smp_cpus % smp_threads) { 2532 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2533 smp_cpus, smp_threads); 2534 exit(1); 2535 } 2536 if (max_cpus % smp_threads) { 2537 error_report("max_cpus (%u) must be multiple of threads (%u)", 2538 max_cpus, smp_threads); 2539 exit(1); 2540 } 2541 } else { 2542 if (max_cpus != smp_cpus) { 2543 error_report("This machine version does not support CPU hotplug"); 2544 exit(1); 2545 } 2546 boot_cores_nr = possible_cpus->len; 2547 } 2548 2549 if (smc->pre_2_10_has_unused_icps) { 2550 int i; 2551 2552 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2553 /* Dummy entries get deregistered when real ICPState objects 2554 * are registered during CPU core hotplug. 2555 */ 2556 pre_2_10_vmstate_register_dummy_icp(i); 2557 } 2558 } 2559 2560 for (i = 0; i < possible_cpus->len; i++) { 2561 int core_id = i * smp_threads; 2562 2563 if (mc->has_hotpluggable_cpus) { 2564 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2565 spapr_vcpu_id(spapr, core_id)); 2566 } 2567 2568 if (i < boot_cores_nr) { 2569 Object *core = object_new(type); 2570 int nr_threads = smp_threads; 2571 2572 /* Handle the partially filled core for older machine types */ 2573 if ((i + 1) * smp_threads >= smp_cpus) { 2574 nr_threads = smp_cpus - i * smp_threads; 2575 } 2576 2577 object_property_set_int(core, "nr-threads", nr_threads, 2578 &error_fatal); 2579 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2580 &error_fatal); 2581 qdev_realize(DEVICE(core), NULL, &error_fatal); 2582 2583 object_unref(core); 2584 } 2585 } 2586 } 2587 2588 static PCIHostState *spapr_create_default_phb(void) 2589 { 2590 DeviceState *dev; 2591 2592 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2593 qdev_prop_set_uint32(dev, "index", 0); 2594 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2595 2596 return PCI_HOST_BRIDGE(dev); 2597 } 2598 2599 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2600 { 2601 MachineState *machine = MACHINE(spapr); 2602 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2603 hwaddr rma_size = machine->ram_size; 2604 hwaddr node0_size = spapr_node0_size(machine); 2605 2606 /* RMA has to fit in the first NUMA node */ 2607 rma_size = MIN(rma_size, node0_size); 2608 2609 /* 2610 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2611 * never exceed that 2612 */ 2613 rma_size = MIN(rma_size, 1 * TiB); 2614 2615 /* 2616 * Clamp the RMA size based on machine type. This is for 2617 * migration compatibility with older qemu versions, which limited 2618 * the RMA size for complicated and mostly bad reasons. 2619 */ 2620 if (smc->rma_limit) { 2621 rma_size = MIN(rma_size, smc->rma_limit); 2622 } 2623 2624 if (rma_size < MIN_RMA_SLOF) { 2625 error_setg(errp, 2626 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2627 "ldMiB guest RMA (Real Mode Area memory)", 2628 MIN_RMA_SLOF / MiB); 2629 return 0; 2630 } 2631 2632 return rma_size; 2633 } 2634 2635 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2636 { 2637 MachineState *machine = MACHINE(spapr); 2638 int i; 2639 2640 for (i = 0; i < machine->ram_slots; i++) { 2641 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2642 } 2643 } 2644 2645 /* pSeries LPAR / sPAPR hardware init */ 2646 static void spapr_machine_init(MachineState *machine) 2647 { 2648 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2649 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2650 MachineClass *mc = MACHINE_GET_CLASS(machine); 2651 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 2652 const char *kernel_filename = machine->kernel_filename; 2653 const char *initrd_filename = machine->initrd_filename; 2654 PCIHostState *phb; 2655 int i; 2656 MemoryRegion *sysmem = get_system_memory(); 2657 long load_limit, fw_size; 2658 char *filename; 2659 Error *resize_hpt_err = NULL; 2660 2661 msi_nonbroken = true; 2662 2663 QLIST_INIT(&spapr->phbs); 2664 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2665 2666 /* Determine capabilities to run with */ 2667 spapr_caps_init(spapr); 2668 2669 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2670 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2671 /* 2672 * If the user explicitly requested a mode we should either 2673 * supply it, or fail completely (which we do below). But if 2674 * it's not set explicitly, we reset our mode to something 2675 * that works 2676 */ 2677 if (resize_hpt_err) { 2678 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2679 error_free(resize_hpt_err); 2680 resize_hpt_err = NULL; 2681 } else { 2682 spapr->resize_hpt = smc->resize_hpt_default; 2683 } 2684 } 2685 2686 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2687 2688 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2689 /* 2690 * User requested HPT resize, but this host can't supply it. Bail out 2691 */ 2692 error_report_err(resize_hpt_err); 2693 exit(1); 2694 } 2695 error_free(resize_hpt_err); 2696 2697 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2698 2699 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2700 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2701 2702 /* 2703 * VSMT must be set in order to be able to compute VCPU ids, ie to 2704 * call spapr_max_server_number() or spapr_vcpu_id(). 2705 */ 2706 spapr_set_vsmt_mode(spapr, &error_fatal); 2707 2708 /* Set up Interrupt Controller before we create the VCPUs */ 2709 spapr_irq_init(spapr, &error_fatal); 2710 2711 /* Set up containers for ibm,client-architecture-support negotiated options 2712 */ 2713 spapr->ov5 = spapr_ovec_new(); 2714 spapr->ov5_cas = spapr_ovec_new(); 2715 2716 if (smc->dr_lmb_enabled) { 2717 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2718 spapr_validate_node_memory(machine, &error_fatal); 2719 } 2720 2721 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2722 2723 /* advertise support for dedicated HP event source to guests */ 2724 if (spapr->use_hotplug_event_source) { 2725 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2726 } 2727 2728 /* advertise support for HPT resizing */ 2729 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2730 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2731 } 2732 2733 /* advertise support for ibm,dyamic-memory-v2 */ 2734 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2735 2736 /* advertise XIVE on POWER9 machines */ 2737 if (spapr->irq->xive) { 2738 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2739 } 2740 2741 /* init CPUs */ 2742 spapr_init_cpus(spapr); 2743 2744 /* 2745 * check we don't have a memory-less/cpu-less NUMA node 2746 * Firmware relies on the existing memory/cpu topology to provide the 2747 * NUMA topology to the kernel. 2748 * And the linux kernel needs to know the NUMA topology at start 2749 * to be able to hotplug CPUs later. 2750 */ 2751 if (machine->numa_state->num_nodes) { 2752 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2753 /* check for memory-less node */ 2754 if (machine->numa_state->nodes[i].node_mem == 0) { 2755 CPUState *cs; 2756 int found = 0; 2757 /* check for cpu-less node */ 2758 CPU_FOREACH(cs) { 2759 PowerPCCPU *cpu = POWERPC_CPU(cs); 2760 if (cpu->node_id == i) { 2761 found = 1; 2762 break; 2763 } 2764 } 2765 /* memory-less and cpu-less node */ 2766 if (!found) { 2767 error_report( 2768 "Memory-less/cpu-less nodes are not supported (node %d)", 2769 i); 2770 exit(1); 2771 } 2772 } 2773 } 2774 2775 } 2776 2777 /* 2778 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2779 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2780 * called from vPHB reset handler so we initialize the counter here. 2781 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2782 * must be equally distant from any other node. 2783 * The final value of spapr->gpu_numa_id is going to be written to 2784 * max-associativity-domains in spapr_build_fdt(). 2785 */ 2786 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2787 2788 /* Init numa_assoc_array */ 2789 spapr_numa_associativity_init(spapr, machine); 2790 2791 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2792 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2793 spapr->max_compat_pvr)) { 2794 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2795 /* KVM and TCG always allow GTSE with radix... */ 2796 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2797 } 2798 /* ... but not with hash (currently). */ 2799 2800 if (kvm_enabled()) { 2801 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2802 kvmppc_enable_logical_ci_hcalls(); 2803 kvmppc_enable_set_mode_hcall(); 2804 2805 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2806 kvmppc_enable_clear_ref_mod_hcalls(); 2807 2808 /* Enable H_PAGE_INIT */ 2809 kvmppc_enable_h_page_init(); 2810 } 2811 2812 /* map RAM */ 2813 memory_region_add_subregion(sysmem, 0, machine->ram); 2814 2815 /* always allocate the device memory information */ 2816 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2817 2818 /* initialize hotplug memory address space */ 2819 if (machine->ram_size < machine->maxram_size) { 2820 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2821 /* 2822 * Limit the number of hotpluggable memory slots to half the number 2823 * slots that KVM supports, leaving the other half for PCI and other 2824 * devices. However ensure that number of slots doesn't drop below 32. 2825 */ 2826 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2827 SPAPR_MAX_RAM_SLOTS; 2828 2829 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2830 max_memslots = SPAPR_MAX_RAM_SLOTS; 2831 } 2832 if (machine->ram_slots > max_memslots) { 2833 error_report("Specified number of memory slots %" 2834 PRIu64" exceeds max supported %d", 2835 machine->ram_slots, max_memslots); 2836 exit(1); 2837 } 2838 2839 machine->device_memory->base = ROUND_UP(machine->ram_size, 2840 SPAPR_DEVICE_MEM_ALIGN); 2841 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2842 "device-memory", device_mem_size); 2843 memory_region_add_subregion(sysmem, machine->device_memory->base, 2844 &machine->device_memory->mr); 2845 } 2846 2847 if (smc->dr_lmb_enabled) { 2848 spapr_create_lmb_dr_connectors(spapr); 2849 } 2850 2851 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2852 /* Create the error string for live migration blocker */ 2853 error_setg(&spapr->fwnmi_migration_blocker, 2854 "A machine check is being handled during migration. The handler" 2855 "may run and log hardware error on the destination"); 2856 } 2857 2858 if (mc->nvdimm_supported) { 2859 spapr_create_nvdimm_dr_connectors(spapr); 2860 } 2861 2862 /* Set up RTAS event infrastructure */ 2863 spapr_events_init(spapr); 2864 2865 /* Set up the RTC RTAS interfaces */ 2866 spapr_rtc_create(spapr); 2867 2868 /* Set up VIO bus */ 2869 spapr->vio_bus = spapr_vio_bus_init(); 2870 2871 for (i = 0; serial_hd(i); i++) { 2872 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2873 } 2874 2875 /* We always have at least the nvram device on VIO */ 2876 spapr_create_nvram(spapr); 2877 2878 /* 2879 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2880 * connectors (described in root DT node's "ibm,drc-types" property) 2881 * are pre-initialized here. additional child connectors (such as 2882 * connectors for a PHBs PCI slots) are added as needed during their 2883 * parent's realization. 2884 */ 2885 if (smc->dr_phb_enabled) { 2886 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2887 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2888 } 2889 } 2890 2891 /* Set up PCI */ 2892 spapr_pci_rtas_init(); 2893 2894 phb = spapr_create_default_phb(); 2895 2896 for (i = 0; i < nb_nics; i++) { 2897 NICInfo *nd = &nd_table[i]; 2898 2899 if (!nd->model) { 2900 nd->model = g_strdup("spapr-vlan"); 2901 } 2902 2903 if (g_str_equal(nd->model, "spapr-vlan") || 2904 g_str_equal(nd->model, "ibmveth")) { 2905 spapr_vlan_create(spapr->vio_bus, nd); 2906 } else { 2907 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2908 } 2909 } 2910 2911 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2912 spapr_vscsi_create(spapr->vio_bus); 2913 } 2914 2915 /* Graphics */ 2916 if (spapr_vga_init(phb->bus, &error_fatal)) { 2917 spapr->has_graphics = true; 2918 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2919 } 2920 2921 if (machine->usb) { 2922 if (smc->use_ohci_by_default) { 2923 pci_create_simple(phb->bus, -1, "pci-ohci"); 2924 } else { 2925 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2926 } 2927 2928 if (spapr->has_graphics) { 2929 USBBus *usb_bus = usb_bus_find(-1); 2930 2931 usb_create_simple(usb_bus, "usb-kbd"); 2932 usb_create_simple(usb_bus, "usb-mouse"); 2933 } 2934 } 2935 2936 if (kernel_filename) { 2937 spapr->kernel_size = load_elf(kernel_filename, NULL, 2938 translate_kernel_address, spapr, 2939 NULL, NULL, NULL, NULL, 1, 2940 PPC_ELF_MACHINE, 0, 0); 2941 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2942 spapr->kernel_size = load_elf(kernel_filename, NULL, 2943 translate_kernel_address, spapr, 2944 NULL, NULL, NULL, NULL, 0, 2945 PPC_ELF_MACHINE, 0, 0); 2946 spapr->kernel_le = spapr->kernel_size > 0; 2947 } 2948 if (spapr->kernel_size < 0) { 2949 error_report("error loading %s: %s", kernel_filename, 2950 load_elf_strerror(spapr->kernel_size)); 2951 exit(1); 2952 } 2953 2954 /* load initrd */ 2955 if (initrd_filename) { 2956 /* Try to locate the initrd in the gap between the kernel 2957 * and the firmware. Add a bit of space just in case 2958 */ 2959 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2960 + 0x1ffff) & ~0xffff; 2961 spapr->initrd_size = load_image_targphys(initrd_filename, 2962 spapr->initrd_base, 2963 load_limit 2964 - spapr->initrd_base); 2965 if (spapr->initrd_size < 0) { 2966 error_report("could not load initial ram disk '%s'", 2967 initrd_filename); 2968 exit(1); 2969 } 2970 } 2971 } 2972 2973 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2974 if (!filename) { 2975 error_report("Could not find LPAR firmware '%s'", bios_name); 2976 exit(1); 2977 } 2978 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2979 if (fw_size <= 0) { 2980 error_report("Could not load LPAR firmware '%s'", filename); 2981 exit(1); 2982 } 2983 g_free(filename); 2984 2985 /* FIXME: Should register things through the MachineState's qdev 2986 * interface, this is a legacy from the sPAPREnvironment structure 2987 * which predated MachineState but had a similar function */ 2988 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2989 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 2990 &savevm_htab_handlers, spapr); 2991 2992 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 2993 2994 qemu_register_boot_set(spapr_boot_set, spapr); 2995 2996 /* 2997 * Nothing needs to be done to resume a suspended guest because 2998 * suspending does not change the machine state, so no need for 2999 * a ->wakeup method. 3000 */ 3001 qemu_register_wakeup_support(); 3002 3003 if (kvm_enabled()) { 3004 /* to stop and start vmclock */ 3005 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3006 &spapr->tb); 3007 3008 kvmppc_spapr_enable_inkernel_multitce(); 3009 } 3010 3011 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3012 } 3013 3014 #define DEFAULT_KVM_TYPE "auto" 3015 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3016 { 3017 /* 3018 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3019 * accomodate the 'HV' and 'PV' formats that exists in the 3020 * wild. The 'auto' mode is being introduced already as 3021 * lower-case, thus we don't need to bother checking for 3022 * "AUTO". 3023 */ 3024 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3025 return 0; 3026 } 3027 3028 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3029 return 1; 3030 } 3031 3032 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3033 return 2; 3034 } 3035 3036 error_report("Unknown kvm-type specified '%s'", vm_type); 3037 exit(1); 3038 } 3039 3040 /* 3041 * Implementation of an interface to adjust firmware path 3042 * for the bootindex property handling. 3043 */ 3044 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3045 DeviceState *dev) 3046 { 3047 #define CAST(type, obj, name) \ 3048 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3049 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3050 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3051 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3052 3053 if (d) { 3054 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3055 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3056 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3057 3058 if (spapr) { 3059 /* 3060 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3061 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3062 * 0x8000 | (target << 8) | (bus << 5) | lun 3063 * (see the "Logical unit addressing format" table in SAM5) 3064 */ 3065 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3066 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3067 (uint64_t)id << 48); 3068 } else if (virtio) { 3069 /* 3070 * We use SRP luns of the form 01000000 | (target << 8) | lun 3071 * in the top 32 bits of the 64-bit LUN 3072 * Note: the quote above is from SLOF and it is wrong, 3073 * the actual binding is: 3074 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3075 */ 3076 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3077 if (d->lun >= 256) { 3078 /* Use the LUN "flat space addressing method" */ 3079 id |= 0x4000; 3080 } 3081 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3082 (uint64_t)id << 32); 3083 } else if (usb) { 3084 /* 3085 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3086 * in the top 32 bits of the 64-bit LUN 3087 */ 3088 unsigned usb_port = atoi(usb->port->path); 3089 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3090 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3091 (uint64_t)id << 32); 3092 } 3093 } 3094 3095 /* 3096 * SLOF probes the USB devices, and if it recognizes that the device is a 3097 * storage device, it changes its name to "storage" instead of "usb-host", 3098 * and additionally adds a child node for the SCSI LUN, so the correct 3099 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3100 */ 3101 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3102 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3103 if (usb_host_dev_is_scsi_storage(usbdev)) { 3104 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3105 } 3106 } 3107 3108 if (phb) { 3109 /* Replace "pci" with "pci@800000020000000" */ 3110 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3111 } 3112 3113 if (vsc) { 3114 /* Same logic as virtio above */ 3115 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3116 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3117 } 3118 3119 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3120 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3121 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3122 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3123 } 3124 3125 return NULL; 3126 } 3127 3128 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3129 { 3130 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3131 3132 return g_strdup(spapr->kvm_type); 3133 } 3134 3135 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3136 { 3137 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3138 3139 g_free(spapr->kvm_type); 3140 spapr->kvm_type = g_strdup(value); 3141 } 3142 3143 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3144 { 3145 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3146 3147 return spapr->use_hotplug_event_source; 3148 } 3149 3150 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3151 Error **errp) 3152 { 3153 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3154 3155 spapr->use_hotplug_event_source = value; 3156 } 3157 3158 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3159 { 3160 return true; 3161 } 3162 3163 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3164 { 3165 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3166 3167 switch (spapr->resize_hpt) { 3168 case SPAPR_RESIZE_HPT_DEFAULT: 3169 return g_strdup("default"); 3170 case SPAPR_RESIZE_HPT_DISABLED: 3171 return g_strdup("disabled"); 3172 case SPAPR_RESIZE_HPT_ENABLED: 3173 return g_strdup("enabled"); 3174 case SPAPR_RESIZE_HPT_REQUIRED: 3175 return g_strdup("required"); 3176 } 3177 g_assert_not_reached(); 3178 } 3179 3180 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3181 { 3182 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3183 3184 if (strcmp(value, "default") == 0) { 3185 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3186 } else if (strcmp(value, "disabled") == 0) { 3187 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3188 } else if (strcmp(value, "enabled") == 0) { 3189 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3190 } else if (strcmp(value, "required") == 0) { 3191 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3192 } else { 3193 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3194 } 3195 } 3196 3197 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3198 { 3199 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3200 3201 if (spapr->irq == &spapr_irq_xics_legacy) { 3202 return g_strdup("legacy"); 3203 } else if (spapr->irq == &spapr_irq_xics) { 3204 return g_strdup("xics"); 3205 } else if (spapr->irq == &spapr_irq_xive) { 3206 return g_strdup("xive"); 3207 } else if (spapr->irq == &spapr_irq_dual) { 3208 return g_strdup("dual"); 3209 } 3210 g_assert_not_reached(); 3211 } 3212 3213 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3214 { 3215 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3216 3217 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3218 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3219 return; 3220 } 3221 3222 /* The legacy IRQ backend can not be set */ 3223 if (strcmp(value, "xics") == 0) { 3224 spapr->irq = &spapr_irq_xics; 3225 } else if (strcmp(value, "xive") == 0) { 3226 spapr->irq = &spapr_irq_xive; 3227 } else if (strcmp(value, "dual") == 0) { 3228 spapr->irq = &spapr_irq_dual; 3229 } else { 3230 error_setg(errp, "Bad value for \"ic-mode\" property"); 3231 } 3232 } 3233 3234 static char *spapr_get_host_model(Object *obj, Error **errp) 3235 { 3236 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3237 3238 return g_strdup(spapr->host_model); 3239 } 3240 3241 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3242 { 3243 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3244 3245 g_free(spapr->host_model); 3246 spapr->host_model = g_strdup(value); 3247 } 3248 3249 static char *spapr_get_host_serial(Object *obj, Error **errp) 3250 { 3251 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3252 3253 return g_strdup(spapr->host_serial); 3254 } 3255 3256 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3257 { 3258 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3259 3260 g_free(spapr->host_serial); 3261 spapr->host_serial = g_strdup(value); 3262 } 3263 3264 static void spapr_instance_init(Object *obj) 3265 { 3266 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3267 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3268 MachineState *ms = MACHINE(spapr); 3269 MachineClass *mc = MACHINE_GET_CLASS(ms); 3270 3271 /* 3272 * NVDIMM support went live in 5.1 without considering that, in 3273 * other archs, the user needs to enable NVDIMM support with the 3274 * 'nvdimm' machine option and the default behavior is NVDIMM 3275 * support disabled. It is too late to roll back to the standard 3276 * behavior without breaking 5.1 guests. 3277 */ 3278 if (mc->nvdimm_supported) { 3279 ms->nvdimms_state->is_enabled = true; 3280 } 3281 3282 spapr->htab_fd = -1; 3283 spapr->use_hotplug_event_source = true; 3284 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3285 object_property_add_str(obj, "kvm-type", 3286 spapr_get_kvm_type, spapr_set_kvm_type); 3287 object_property_set_description(obj, "kvm-type", 3288 "Specifies the KVM virtualization mode (auto," 3289 " hv, pr). Defaults to 'auto'. This mode will use" 3290 " any available KVM module loaded in the host," 3291 " where kvm_hv takes precedence if both kvm_hv and" 3292 " kvm_pr are loaded."); 3293 object_property_add_bool(obj, "modern-hotplug-events", 3294 spapr_get_modern_hotplug_events, 3295 spapr_set_modern_hotplug_events); 3296 object_property_set_description(obj, "modern-hotplug-events", 3297 "Use dedicated hotplug event mechanism in" 3298 " place of standard EPOW events when possible" 3299 " (required for memory hot-unplug support)"); 3300 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3301 "Maximum permitted CPU compatibility mode"); 3302 3303 object_property_add_str(obj, "resize-hpt", 3304 spapr_get_resize_hpt, spapr_set_resize_hpt); 3305 object_property_set_description(obj, "resize-hpt", 3306 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3307 object_property_add_uint32_ptr(obj, "vsmt", 3308 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3309 object_property_set_description(obj, "vsmt", 3310 "Virtual SMT: KVM behaves as if this were" 3311 " the host's SMT mode"); 3312 3313 object_property_add_bool(obj, "vfio-no-msix-emulation", 3314 spapr_get_msix_emulation, NULL); 3315 3316 object_property_add_uint64_ptr(obj, "kernel-addr", 3317 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3318 object_property_set_description(obj, "kernel-addr", 3319 stringify(KERNEL_LOAD_ADDR) 3320 " for -kernel is the default"); 3321 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3322 /* The machine class defines the default interrupt controller mode */ 3323 spapr->irq = smc->irq; 3324 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3325 spapr_set_ic_mode); 3326 object_property_set_description(obj, "ic-mode", 3327 "Specifies the interrupt controller mode (xics, xive, dual)"); 3328 3329 object_property_add_str(obj, "host-model", 3330 spapr_get_host_model, spapr_set_host_model); 3331 object_property_set_description(obj, "host-model", 3332 "Host model to advertise in guest device tree"); 3333 object_property_add_str(obj, "host-serial", 3334 spapr_get_host_serial, spapr_set_host_serial); 3335 object_property_set_description(obj, "host-serial", 3336 "Host serial number to advertise in guest device tree"); 3337 } 3338 3339 static void spapr_machine_finalizefn(Object *obj) 3340 { 3341 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3342 3343 g_free(spapr->kvm_type); 3344 } 3345 3346 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3347 { 3348 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3349 PowerPCCPU *cpu = POWERPC_CPU(cs); 3350 CPUPPCState *env = &cpu->env; 3351 3352 cpu_synchronize_state(cs); 3353 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3354 if (spapr->fwnmi_system_reset_addr != -1) { 3355 uint64_t rtas_addr, addr; 3356 3357 /* get rtas addr from fdt */ 3358 rtas_addr = spapr_get_rtas_addr(); 3359 if (!rtas_addr) { 3360 qemu_system_guest_panicked(NULL); 3361 return; 3362 } 3363 3364 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3365 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3366 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3367 env->gpr[3] = addr; 3368 } 3369 ppc_cpu_do_system_reset(cs); 3370 if (spapr->fwnmi_system_reset_addr != -1) { 3371 env->nip = spapr->fwnmi_system_reset_addr; 3372 } 3373 } 3374 3375 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3376 { 3377 CPUState *cs; 3378 3379 CPU_FOREACH(cs) { 3380 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3381 } 3382 } 3383 3384 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3385 void *fdt, int *fdt_start_offset, Error **errp) 3386 { 3387 uint64_t addr; 3388 uint32_t node; 3389 3390 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3391 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3392 &error_abort); 3393 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3394 SPAPR_MEMORY_BLOCK_SIZE); 3395 return 0; 3396 } 3397 3398 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3399 bool dedicated_hp_event_source) 3400 { 3401 SpaprDrc *drc; 3402 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3403 int i; 3404 uint64_t addr = addr_start; 3405 bool hotplugged = spapr_drc_hotplugged(dev); 3406 3407 for (i = 0; i < nr_lmbs; i++) { 3408 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3409 addr / SPAPR_MEMORY_BLOCK_SIZE); 3410 g_assert(drc); 3411 3412 /* 3413 * memory_device_get_free_addr() provided a range of free addresses 3414 * that doesn't overlap with any existing mapping at pre-plug. The 3415 * corresponding LMB DRCs are thus assumed to be all attachable. 3416 */ 3417 spapr_drc_attach(drc, dev); 3418 if (!hotplugged) { 3419 spapr_drc_reset(drc); 3420 } 3421 addr += SPAPR_MEMORY_BLOCK_SIZE; 3422 } 3423 /* send hotplug notification to the 3424 * guest only in case of hotplugged memory 3425 */ 3426 if (hotplugged) { 3427 if (dedicated_hp_event_source) { 3428 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3429 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3430 g_assert(drc); 3431 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3432 nr_lmbs, 3433 spapr_drc_index(drc)); 3434 } else { 3435 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3436 nr_lmbs); 3437 } 3438 } 3439 } 3440 3441 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3442 { 3443 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3444 PCDIMMDevice *dimm = PC_DIMM(dev); 3445 uint64_t size, addr; 3446 int64_t slot; 3447 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3448 3449 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3450 3451 pc_dimm_plug(dimm, MACHINE(ms)); 3452 3453 if (!is_nvdimm) { 3454 addr = object_property_get_uint(OBJECT(dimm), 3455 PC_DIMM_ADDR_PROP, &error_abort); 3456 spapr_add_lmbs(dev, addr, size, 3457 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3458 } else { 3459 slot = object_property_get_int(OBJECT(dimm), 3460 PC_DIMM_SLOT_PROP, &error_abort); 3461 /* We should have valid slot number at this point */ 3462 g_assert(slot >= 0); 3463 spapr_add_nvdimm(dev, slot); 3464 } 3465 } 3466 3467 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3468 Error **errp) 3469 { 3470 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3471 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3472 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3473 PCDIMMDevice *dimm = PC_DIMM(dev); 3474 Error *local_err = NULL; 3475 uint64_t size; 3476 Object *memdev; 3477 hwaddr pagesize; 3478 3479 if (!smc->dr_lmb_enabled) { 3480 error_setg(errp, "Memory hotplug not supported for this machine"); 3481 return; 3482 } 3483 3484 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3485 if (local_err) { 3486 error_propagate(errp, local_err); 3487 return; 3488 } 3489 3490 if (is_nvdimm) { 3491 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3492 return; 3493 } 3494 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3495 error_setg(errp, "Hotplugged memory size must be a multiple of " 3496 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3497 return; 3498 } 3499 3500 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3501 &error_abort); 3502 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3503 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3504 return; 3505 } 3506 3507 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3508 } 3509 3510 struct SpaprDimmState { 3511 PCDIMMDevice *dimm; 3512 uint32_t nr_lmbs; 3513 QTAILQ_ENTRY(SpaprDimmState) next; 3514 }; 3515 3516 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3517 PCDIMMDevice *dimm) 3518 { 3519 SpaprDimmState *dimm_state = NULL; 3520 3521 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3522 if (dimm_state->dimm == dimm) { 3523 break; 3524 } 3525 } 3526 return dimm_state; 3527 } 3528 3529 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3530 uint32_t nr_lmbs, 3531 PCDIMMDevice *dimm) 3532 { 3533 SpaprDimmState *ds = NULL; 3534 3535 /* 3536 * If this request is for a DIMM whose removal had failed earlier 3537 * (due to guest's refusal to remove the LMBs), we would have this 3538 * dimm already in the pending_dimm_unplugs list. In that 3539 * case don't add again. 3540 */ 3541 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3542 if (!ds) { 3543 ds = g_malloc0(sizeof(SpaprDimmState)); 3544 ds->nr_lmbs = nr_lmbs; 3545 ds->dimm = dimm; 3546 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3547 } 3548 return ds; 3549 } 3550 3551 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3552 SpaprDimmState *dimm_state) 3553 { 3554 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3555 g_free(dimm_state); 3556 } 3557 3558 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3559 PCDIMMDevice *dimm) 3560 { 3561 SpaprDrc *drc; 3562 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3563 &error_abort); 3564 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3565 uint32_t avail_lmbs = 0; 3566 uint64_t addr_start, addr; 3567 int i; 3568 3569 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3570 &error_abort); 3571 3572 addr = addr_start; 3573 for (i = 0; i < nr_lmbs; i++) { 3574 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3575 addr / SPAPR_MEMORY_BLOCK_SIZE); 3576 g_assert(drc); 3577 if (drc->dev) { 3578 avail_lmbs++; 3579 } 3580 addr += SPAPR_MEMORY_BLOCK_SIZE; 3581 } 3582 3583 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3584 } 3585 3586 /* Callback to be called during DRC release. */ 3587 void spapr_lmb_release(DeviceState *dev) 3588 { 3589 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3590 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3591 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3592 3593 /* This information will get lost if a migration occurs 3594 * during the unplug process. In this case recover it. */ 3595 if (ds == NULL) { 3596 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3597 g_assert(ds); 3598 /* The DRC being examined by the caller at least must be counted */ 3599 g_assert(ds->nr_lmbs); 3600 } 3601 3602 if (--ds->nr_lmbs) { 3603 return; 3604 } 3605 3606 /* 3607 * Now that all the LMBs have been removed by the guest, call the 3608 * unplug handler chain. This can never fail. 3609 */ 3610 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3611 object_unparent(OBJECT(dev)); 3612 } 3613 3614 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3615 { 3616 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3617 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3618 3619 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3620 qdev_unrealize(dev); 3621 spapr_pending_dimm_unplugs_remove(spapr, ds); 3622 } 3623 3624 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3625 DeviceState *dev, Error **errp) 3626 { 3627 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3628 PCDIMMDevice *dimm = PC_DIMM(dev); 3629 uint32_t nr_lmbs; 3630 uint64_t size, addr_start, addr; 3631 int i; 3632 SpaprDrc *drc; 3633 3634 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3635 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3636 return; 3637 } 3638 3639 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3640 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3641 3642 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3643 &error_abort); 3644 3645 /* 3646 * An existing pending dimm state for this DIMM means that there is an 3647 * unplug operation in progress, waiting for the spapr_lmb_release 3648 * callback to complete the job (BQL can't cover that far). In this case, 3649 * bail out to avoid detaching DRCs that were already released. 3650 */ 3651 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3652 error_setg(errp, "Memory unplug already in progress for device %s", 3653 dev->id); 3654 return; 3655 } 3656 3657 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3658 3659 addr = addr_start; 3660 for (i = 0; i < nr_lmbs; i++) { 3661 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3662 addr / SPAPR_MEMORY_BLOCK_SIZE); 3663 g_assert(drc); 3664 3665 spapr_drc_detach(drc); 3666 addr += SPAPR_MEMORY_BLOCK_SIZE; 3667 } 3668 3669 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3670 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3671 g_assert(drc); 3672 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3673 nr_lmbs, spapr_drc_index(drc)); 3674 } 3675 3676 /* Callback to be called during DRC release. */ 3677 void spapr_core_release(DeviceState *dev) 3678 { 3679 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3680 3681 /* Call the unplug handler chain. This can never fail. */ 3682 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3683 object_unparent(OBJECT(dev)); 3684 } 3685 3686 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3687 { 3688 MachineState *ms = MACHINE(hotplug_dev); 3689 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3690 CPUCore *cc = CPU_CORE(dev); 3691 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3692 3693 if (smc->pre_2_10_has_unused_icps) { 3694 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3695 int i; 3696 3697 for (i = 0; i < cc->nr_threads; i++) { 3698 CPUState *cs = CPU(sc->threads[i]); 3699 3700 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3701 } 3702 } 3703 3704 assert(core_slot); 3705 core_slot->cpu = NULL; 3706 qdev_unrealize(dev); 3707 } 3708 3709 static 3710 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3711 Error **errp) 3712 { 3713 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3714 int index; 3715 SpaprDrc *drc; 3716 CPUCore *cc = CPU_CORE(dev); 3717 3718 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3719 error_setg(errp, "Unable to find CPU core with core-id: %d", 3720 cc->core_id); 3721 return; 3722 } 3723 if (index == 0) { 3724 error_setg(errp, "Boot CPU core may not be unplugged"); 3725 return; 3726 } 3727 3728 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3729 spapr_vcpu_id(spapr, cc->core_id)); 3730 g_assert(drc); 3731 3732 if (!spapr_drc_unplug_requested(drc)) { 3733 spapr_drc_detach(drc); 3734 spapr_hotplug_req_remove_by_index(drc); 3735 } 3736 } 3737 3738 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3739 void *fdt, int *fdt_start_offset, Error **errp) 3740 { 3741 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3742 CPUState *cs = CPU(core->threads[0]); 3743 PowerPCCPU *cpu = POWERPC_CPU(cs); 3744 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3745 int id = spapr_get_vcpu_id(cpu); 3746 char *nodename; 3747 int offset; 3748 3749 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3750 offset = fdt_add_subnode(fdt, 0, nodename); 3751 g_free(nodename); 3752 3753 spapr_dt_cpu(cs, fdt, offset, spapr); 3754 3755 *fdt_start_offset = offset; 3756 return 0; 3757 } 3758 3759 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3760 { 3761 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3762 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3763 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3764 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3765 CPUCore *cc = CPU_CORE(dev); 3766 CPUState *cs; 3767 SpaprDrc *drc; 3768 CPUArchId *core_slot; 3769 int index; 3770 bool hotplugged = spapr_drc_hotplugged(dev); 3771 int i; 3772 3773 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3774 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 3775 3776 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3777 spapr_vcpu_id(spapr, cc->core_id)); 3778 3779 g_assert(drc || !mc->has_hotpluggable_cpus); 3780 3781 if (drc) { 3782 /* 3783 * spapr_core_pre_plug() already buys us this is a brand new 3784 * core being plugged into a free slot. Nothing should already 3785 * be attached to the corresponding DRC. 3786 */ 3787 spapr_drc_attach(drc, dev); 3788 3789 if (hotplugged) { 3790 /* 3791 * Send hotplug notification interrupt to the guest only 3792 * in case of hotplugged CPUs. 3793 */ 3794 spapr_hotplug_req_add_by_index(drc); 3795 } else { 3796 spapr_drc_reset(drc); 3797 } 3798 } 3799 3800 core_slot->cpu = OBJECT(dev); 3801 3802 /* 3803 * Set compatibility mode to match the boot CPU, which was either set 3804 * by the machine reset code or by CAS. This really shouldn't fail at 3805 * this point. 3806 */ 3807 if (hotplugged) { 3808 for (i = 0; i < cc->nr_threads; i++) { 3809 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3810 &error_abort); 3811 } 3812 } 3813 3814 if (smc->pre_2_10_has_unused_icps) { 3815 for (i = 0; i < cc->nr_threads; i++) { 3816 cs = CPU(core->threads[i]); 3817 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3818 } 3819 } 3820 } 3821 3822 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3823 Error **errp) 3824 { 3825 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3826 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3827 CPUCore *cc = CPU_CORE(dev); 3828 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3829 const char *type = object_get_typename(OBJECT(dev)); 3830 CPUArchId *core_slot; 3831 int index; 3832 unsigned int smp_threads = machine->smp.threads; 3833 3834 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3835 error_setg(errp, "CPU hotplug not supported for this machine"); 3836 return; 3837 } 3838 3839 if (strcmp(base_core_type, type)) { 3840 error_setg(errp, "CPU core type should be %s", base_core_type); 3841 return; 3842 } 3843 3844 if (cc->core_id % smp_threads) { 3845 error_setg(errp, "invalid core id %d", cc->core_id); 3846 return; 3847 } 3848 3849 /* 3850 * In general we should have homogeneous threads-per-core, but old 3851 * (pre hotplug support) machine types allow the last core to have 3852 * reduced threads as a compatibility hack for when we allowed 3853 * total vcpus not a multiple of threads-per-core. 3854 */ 3855 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3856 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 3857 smp_threads); 3858 return; 3859 } 3860 3861 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3862 if (!core_slot) { 3863 error_setg(errp, "core id %d out of range", cc->core_id); 3864 return; 3865 } 3866 3867 if (core_slot->cpu) { 3868 error_setg(errp, "core %d already populated", cc->core_id); 3869 return; 3870 } 3871 3872 numa_cpu_pre_plug(core_slot, dev, errp); 3873 } 3874 3875 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3876 void *fdt, int *fdt_start_offset, Error **errp) 3877 { 3878 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3879 int intc_phandle; 3880 3881 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3882 if (intc_phandle <= 0) { 3883 return -1; 3884 } 3885 3886 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3887 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3888 return -1; 3889 } 3890 3891 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3892 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3893 3894 return 0; 3895 } 3896 3897 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3898 Error **errp) 3899 { 3900 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3901 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3902 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3903 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3904 SpaprDrc *drc; 3905 3906 if (dev->hotplugged && !smc->dr_phb_enabled) { 3907 error_setg(errp, "PHB hotplug not supported for this machine"); 3908 return false; 3909 } 3910 3911 if (sphb->index == (uint32_t)-1) { 3912 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3913 return false; 3914 } 3915 3916 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3917 if (drc && drc->dev) { 3918 error_setg(errp, "PHB %d already attached", sphb->index); 3919 return false; 3920 } 3921 3922 /* 3923 * This will check that sphb->index doesn't exceed the maximum number of 3924 * PHBs for the current machine type. 3925 */ 3926 return 3927 smc->phb_placement(spapr, sphb->index, 3928 &sphb->buid, &sphb->io_win_addr, 3929 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3930 windows_supported, sphb->dma_liobn, 3931 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3932 errp); 3933 } 3934 3935 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3936 { 3937 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3938 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3939 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3940 SpaprDrc *drc; 3941 bool hotplugged = spapr_drc_hotplugged(dev); 3942 3943 if (!smc->dr_phb_enabled) { 3944 return; 3945 } 3946 3947 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3948 /* hotplug hooks should check it's enabled before getting this far */ 3949 assert(drc); 3950 3951 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 3952 spapr_drc_attach(drc, dev); 3953 3954 if (hotplugged) { 3955 spapr_hotplug_req_add_by_index(drc); 3956 } else { 3957 spapr_drc_reset(drc); 3958 } 3959 } 3960 3961 void spapr_phb_release(DeviceState *dev) 3962 { 3963 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3964 3965 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3966 object_unparent(OBJECT(dev)); 3967 } 3968 3969 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3970 { 3971 qdev_unrealize(dev); 3972 } 3973 3974 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 3975 DeviceState *dev, Error **errp) 3976 { 3977 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3978 SpaprDrc *drc; 3979 3980 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3981 assert(drc); 3982 3983 if (!spapr_drc_unplug_requested(drc)) { 3984 spapr_drc_detach(drc); 3985 spapr_hotplug_req_remove_by_index(drc); 3986 } 3987 } 3988 3989 static 3990 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3991 Error **errp) 3992 { 3993 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3994 3995 if (spapr->tpm_proxy != NULL) { 3996 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 3997 return false; 3998 } 3999 4000 return true; 4001 } 4002 4003 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4004 { 4005 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4006 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4007 4008 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4009 g_assert(spapr->tpm_proxy == NULL); 4010 4011 spapr->tpm_proxy = tpm_proxy; 4012 } 4013 4014 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4015 { 4016 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4017 4018 qdev_unrealize(dev); 4019 object_unparent(OBJECT(dev)); 4020 spapr->tpm_proxy = NULL; 4021 } 4022 4023 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4024 DeviceState *dev, Error **errp) 4025 { 4026 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4027 spapr_memory_plug(hotplug_dev, dev); 4028 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4029 spapr_core_plug(hotplug_dev, dev); 4030 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4031 spapr_phb_plug(hotplug_dev, dev); 4032 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4033 spapr_tpm_proxy_plug(hotplug_dev, dev); 4034 } 4035 } 4036 4037 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4038 DeviceState *dev, Error **errp) 4039 { 4040 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4041 spapr_memory_unplug(hotplug_dev, dev); 4042 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4043 spapr_core_unplug(hotplug_dev, dev); 4044 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4045 spapr_phb_unplug(hotplug_dev, dev); 4046 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4047 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4048 } 4049 } 4050 4051 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4052 { 4053 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4054 /* 4055 * CAS will process all pending unplug requests. 4056 * 4057 * HACK: a guest could theoretically have cleared all bits in OV5, 4058 * but none of the guests we care for do. 4059 */ 4060 spapr_ovec_empty(spapr->ov5_cas); 4061 } 4062 4063 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4064 DeviceState *dev, Error **errp) 4065 { 4066 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4067 MachineClass *mc = MACHINE_GET_CLASS(sms); 4068 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4069 4070 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4071 if (spapr_memory_hot_unplug_supported(sms)) { 4072 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4073 } else { 4074 error_setg(errp, "Memory hot unplug not supported for this guest"); 4075 } 4076 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4077 if (!mc->has_hotpluggable_cpus) { 4078 error_setg(errp, "CPU hot unplug not supported on this machine"); 4079 return; 4080 } 4081 spapr_core_unplug_request(hotplug_dev, dev, errp); 4082 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4083 if (!smc->dr_phb_enabled) { 4084 error_setg(errp, "PHB hot unplug not supported on this machine"); 4085 return; 4086 } 4087 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4088 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4089 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4090 } 4091 } 4092 4093 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4094 DeviceState *dev, Error **errp) 4095 { 4096 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4097 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4098 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4099 spapr_core_pre_plug(hotplug_dev, dev, errp); 4100 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4101 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4102 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4103 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4104 } 4105 } 4106 4107 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4108 DeviceState *dev) 4109 { 4110 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4111 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4112 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4113 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4114 return HOTPLUG_HANDLER(machine); 4115 } 4116 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4117 PCIDevice *pcidev = PCI_DEVICE(dev); 4118 PCIBus *root = pci_device_root_bus(pcidev); 4119 SpaprPhbState *phb = 4120 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4121 TYPE_SPAPR_PCI_HOST_BRIDGE); 4122 4123 if (phb) { 4124 return HOTPLUG_HANDLER(phb); 4125 } 4126 } 4127 return NULL; 4128 } 4129 4130 static CpuInstanceProperties 4131 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4132 { 4133 CPUArchId *core_slot; 4134 MachineClass *mc = MACHINE_GET_CLASS(machine); 4135 4136 /* make sure possible_cpu are intialized */ 4137 mc->possible_cpu_arch_ids(machine); 4138 /* get CPU core slot containing thread that matches cpu_index */ 4139 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4140 assert(core_slot); 4141 return core_slot->props; 4142 } 4143 4144 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4145 { 4146 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4147 } 4148 4149 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4150 { 4151 int i; 4152 unsigned int smp_threads = machine->smp.threads; 4153 unsigned int smp_cpus = machine->smp.cpus; 4154 const char *core_type; 4155 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4156 MachineClass *mc = MACHINE_GET_CLASS(machine); 4157 4158 if (!mc->has_hotpluggable_cpus) { 4159 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4160 } 4161 if (machine->possible_cpus) { 4162 assert(machine->possible_cpus->len == spapr_max_cores); 4163 return machine->possible_cpus; 4164 } 4165 4166 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4167 if (!core_type) { 4168 error_report("Unable to find sPAPR CPU Core definition"); 4169 exit(1); 4170 } 4171 4172 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4173 sizeof(CPUArchId) * spapr_max_cores); 4174 machine->possible_cpus->len = spapr_max_cores; 4175 for (i = 0; i < machine->possible_cpus->len; i++) { 4176 int core_id = i * smp_threads; 4177 4178 machine->possible_cpus->cpus[i].type = core_type; 4179 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4180 machine->possible_cpus->cpus[i].arch_id = core_id; 4181 machine->possible_cpus->cpus[i].props.has_core_id = true; 4182 machine->possible_cpus->cpus[i].props.core_id = core_id; 4183 } 4184 return machine->possible_cpus; 4185 } 4186 4187 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4188 uint64_t *buid, hwaddr *pio, 4189 hwaddr *mmio32, hwaddr *mmio64, 4190 unsigned n_dma, uint32_t *liobns, 4191 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4192 { 4193 /* 4194 * New-style PHB window placement. 4195 * 4196 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4197 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4198 * windows. 4199 * 4200 * Some guest kernels can't work with MMIO windows above 1<<46 4201 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4202 * 4203 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4204 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4205 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4206 * 1TiB 64-bit MMIO windows for each PHB. 4207 */ 4208 const uint64_t base_buid = 0x800000020000000ULL; 4209 int i; 4210 4211 /* Sanity check natural alignments */ 4212 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4213 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4214 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4215 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4216 /* Sanity check bounds */ 4217 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4218 SPAPR_PCI_MEM32_WIN_SIZE); 4219 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4220 SPAPR_PCI_MEM64_WIN_SIZE); 4221 4222 if (index >= SPAPR_MAX_PHBS) { 4223 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4224 SPAPR_MAX_PHBS - 1); 4225 return false; 4226 } 4227 4228 *buid = base_buid + index; 4229 for (i = 0; i < n_dma; ++i) { 4230 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4231 } 4232 4233 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4234 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4235 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4236 4237 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4238 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4239 return true; 4240 } 4241 4242 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4243 { 4244 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4245 4246 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4247 } 4248 4249 static void spapr_ics_resend(XICSFabric *dev) 4250 { 4251 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4252 4253 ics_resend(spapr->ics); 4254 } 4255 4256 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4257 { 4258 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4259 4260 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4261 } 4262 4263 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4264 Monitor *mon) 4265 { 4266 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4267 4268 spapr_irq_print_info(spapr, mon); 4269 monitor_printf(mon, "irqchip: %s\n", 4270 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4271 } 4272 4273 /* 4274 * This is a XIVE only operation 4275 */ 4276 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4277 uint8_t nvt_blk, uint32_t nvt_idx, 4278 bool cam_ignore, uint8_t priority, 4279 uint32_t logic_serv, XiveTCTXMatch *match) 4280 { 4281 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4282 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4283 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4284 int count; 4285 4286 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4287 priority, logic_serv, match); 4288 if (count < 0) { 4289 return count; 4290 } 4291 4292 /* 4293 * When we implement the save and restore of the thread interrupt 4294 * contexts in the enter/exit CPU handlers of the machine and the 4295 * escalations in QEMU, we should be able to handle non dispatched 4296 * vCPUs. 4297 * 4298 * Until this is done, the sPAPR machine should find at least one 4299 * matching context always. 4300 */ 4301 if (count == 0) { 4302 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4303 nvt_blk, nvt_idx); 4304 } 4305 4306 return count; 4307 } 4308 4309 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4310 { 4311 return cpu->vcpu_id; 4312 } 4313 4314 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4315 { 4316 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4317 MachineState *ms = MACHINE(spapr); 4318 int vcpu_id; 4319 4320 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4321 4322 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4323 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4324 error_append_hint(errp, "Adjust the number of cpus to %d " 4325 "or try to raise the number of threads per core\n", 4326 vcpu_id * ms->smp.threads / spapr->vsmt); 4327 return false; 4328 } 4329 4330 cpu->vcpu_id = vcpu_id; 4331 return true; 4332 } 4333 4334 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4335 { 4336 CPUState *cs; 4337 4338 CPU_FOREACH(cs) { 4339 PowerPCCPU *cpu = POWERPC_CPU(cs); 4340 4341 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4342 return cpu; 4343 } 4344 } 4345 4346 return NULL; 4347 } 4348 4349 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4350 { 4351 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4352 4353 /* These are only called by TCG, KVM maintains dispatch state */ 4354 4355 spapr_cpu->prod = false; 4356 if (spapr_cpu->vpa_addr) { 4357 CPUState *cs = CPU(cpu); 4358 uint32_t dispatch; 4359 4360 dispatch = ldl_be_phys(cs->as, 4361 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4362 dispatch++; 4363 if ((dispatch & 1) != 0) { 4364 qemu_log_mask(LOG_GUEST_ERROR, 4365 "VPA: incorrect dispatch counter value for " 4366 "dispatched partition %u, correcting.\n", dispatch); 4367 dispatch++; 4368 } 4369 stl_be_phys(cs->as, 4370 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4371 } 4372 } 4373 4374 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4375 { 4376 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4377 4378 if (spapr_cpu->vpa_addr) { 4379 CPUState *cs = CPU(cpu); 4380 uint32_t dispatch; 4381 4382 dispatch = ldl_be_phys(cs->as, 4383 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4384 dispatch++; 4385 if ((dispatch & 1) != 1) { 4386 qemu_log_mask(LOG_GUEST_ERROR, 4387 "VPA: incorrect dispatch counter value for " 4388 "preempted partition %u, correcting.\n", dispatch); 4389 dispatch++; 4390 } 4391 stl_be_phys(cs->as, 4392 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4393 } 4394 } 4395 4396 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4397 { 4398 MachineClass *mc = MACHINE_CLASS(oc); 4399 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4400 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4401 NMIClass *nc = NMI_CLASS(oc); 4402 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4403 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4404 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4405 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4406 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4407 4408 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4409 mc->ignore_boot_device_suffixes = true; 4410 4411 /* 4412 * We set up the default / latest behaviour here. The class_init 4413 * functions for the specific versioned machine types can override 4414 * these details for backwards compatibility 4415 */ 4416 mc->init = spapr_machine_init; 4417 mc->reset = spapr_machine_reset; 4418 mc->block_default_type = IF_SCSI; 4419 mc->max_cpus = 1024; 4420 mc->no_parallel = 1; 4421 mc->default_boot_order = ""; 4422 mc->default_ram_size = 512 * MiB; 4423 mc->default_ram_id = "ppc_spapr.ram"; 4424 mc->default_display = "std"; 4425 mc->kvm_type = spapr_kvm_type; 4426 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4427 mc->pci_allow_0_address = true; 4428 assert(!mc->get_hotplug_handler); 4429 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4430 hc->pre_plug = spapr_machine_device_pre_plug; 4431 hc->plug = spapr_machine_device_plug; 4432 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4433 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4434 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4435 hc->unplug_request = spapr_machine_device_unplug_request; 4436 hc->unplug = spapr_machine_device_unplug; 4437 4438 smc->dr_lmb_enabled = true; 4439 smc->update_dt_enabled = true; 4440 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4441 mc->has_hotpluggable_cpus = true; 4442 mc->nvdimm_supported = true; 4443 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4444 fwc->get_dev_path = spapr_get_fw_dev_path; 4445 nc->nmi_monitor_handler = spapr_nmi; 4446 smc->phb_placement = spapr_phb_placement; 4447 vhc->hypercall = emulate_spapr_hypercall; 4448 vhc->hpt_mask = spapr_hpt_mask; 4449 vhc->map_hptes = spapr_map_hptes; 4450 vhc->unmap_hptes = spapr_unmap_hptes; 4451 vhc->hpte_set_c = spapr_hpte_set_c; 4452 vhc->hpte_set_r = spapr_hpte_set_r; 4453 vhc->get_pate = spapr_get_pate; 4454 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4455 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4456 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4457 xic->ics_get = spapr_ics_get; 4458 xic->ics_resend = spapr_ics_resend; 4459 xic->icp_get = spapr_icp_get; 4460 ispc->print_info = spapr_pic_print_info; 4461 /* Force NUMA node memory size to be a multiple of 4462 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4463 * in which LMBs are represented and hot-added 4464 */ 4465 mc->numa_mem_align_shift = 28; 4466 mc->auto_enable_numa = true; 4467 4468 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4469 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4470 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4471 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4472 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4473 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4474 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4475 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4476 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4477 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4478 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4479 spapr_caps_add_properties(smc); 4480 smc->irq = &spapr_irq_dual; 4481 smc->dr_phb_enabled = true; 4482 smc->linux_pci_probe = true; 4483 smc->smp_threads_vsmt = true; 4484 smc->nr_xirqs = SPAPR_NR_XIRQS; 4485 xfc->match_nvt = spapr_match_nvt; 4486 } 4487 4488 static const TypeInfo spapr_machine_info = { 4489 .name = TYPE_SPAPR_MACHINE, 4490 .parent = TYPE_MACHINE, 4491 .abstract = true, 4492 .instance_size = sizeof(SpaprMachineState), 4493 .instance_init = spapr_instance_init, 4494 .instance_finalize = spapr_machine_finalizefn, 4495 .class_size = sizeof(SpaprMachineClass), 4496 .class_init = spapr_machine_class_init, 4497 .interfaces = (InterfaceInfo[]) { 4498 { TYPE_FW_PATH_PROVIDER }, 4499 { TYPE_NMI }, 4500 { TYPE_HOTPLUG_HANDLER }, 4501 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4502 { TYPE_XICS_FABRIC }, 4503 { TYPE_INTERRUPT_STATS_PROVIDER }, 4504 { TYPE_XIVE_FABRIC }, 4505 { } 4506 }, 4507 }; 4508 4509 static void spapr_machine_latest_class_options(MachineClass *mc) 4510 { 4511 mc->alias = "pseries"; 4512 mc->is_default = true; 4513 } 4514 4515 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4516 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4517 void *data) \ 4518 { \ 4519 MachineClass *mc = MACHINE_CLASS(oc); \ 4520 spapr_machine_##suffix##_class_options(mc); \ 4521 if (latest) { \ 4522 spapr_machine_latest_class_options(mc); \ 4523 } \ 4524 } \ 4525 static const TypeInfo spapr_machine_##suffix##_info = { \ 4526 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4527 .parent = TYPE_SPAPR_MACHINE, \ 4528 .class_init = spapr_machine_##suffix##_class_init, \ 4529 }; \ 4530 static void spapr_machine_register_##suffix(void) \ 4531 { \ 4532 type_register(&spapr_machine_##suffix##_info); \ 4533 } \ 4534 type_init(spapr_machine_register_##suffix) 4535 4536 /* 4537 * pseries-6.0 4538 */ 4539 static void spapr_machine_6_0_class_options(MachineClass *mc) 4540 { 4541 /* Defaults for the latest behaviour inherited from the base class */ 4542 } 4543 4544 DEFINE_SPAPR_MACHINE(6_0, "6.0", true); 4545 4546 /* 4547 * pseries-5.2 4548 */ 4549 static void spapr_machine_5_2_class_options(MachineClass *mc) 4550 { 4551 spapr_machine_6_0_class_options(mc); 4552 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4553 } 4554 4555 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4556 4557 /* 4558 * pseries-5.1 4559 */ 4560 static void spapr_machine_5_1_class_options(MachineClass *mc) 4561 { 4562 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4563 4564 spapr_machine_5_2_class_options(mc); 4565 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4566 smc->pre_5_2_numa_associativity = true; 4567 } 4568 4569 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4570 4571 /* 4572 * pseries-5.0 4573 */ 4574 static void spapr_machine_5_0_class_options(MachineClass *mc) 4575 { 4576 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4577 static GlobalProperty compat[] = { 4578 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4579 }; 4580 4581 spapr_machine_5_1_class_options(mc); 4582 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4583 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4584 mc->numa_mem_supported = true; 4585 smc->pre_5_1_assoc_refpoints = true; 4586 } 4587 4588 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4589 4590 /* 4591 * pseries-4.2 4592 */ 4593 static void spapr_machine_4_2_class_options(MachineClass *mc) 4594 { 4595 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4596 4597 spapr_machine_5_0_class_options(mc); 4598 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4599 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4600 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4601 smc->rma_limit = 16 * GiB; 4602 mc->nvdimm_supported = false; 4603 } 4604 4605 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4606 4607 /* 4608 * pseries-4.1 4609 */ 4610 static void spapr_machine_4_1_class_options(MachineClass *mc) 4611 { 4612 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4613 static GlobalProperty compat[] = { 4614 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4615 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4616 }; 4617 4618 spapr_machine_4_2_class_options(mc); 4619 smc->linux_pci_probe = false; 4620 smc->smp_threads_vsmt = false; 4621 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4622 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4623 } 4624 4625 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4626 4627 /* 4628 * pseries-4.0 4629 */ 4630 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4631 uint64_t *buid, hwaddr *pio, 4632 hwaddr *mmio32, hwaddr *mmio64, 4633 unsigned n_dma, uint32_t *liobns, 4634 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4635 { 4636 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 4637 liobns, nv2gpa, nv2atsd, errp)) { 4638 return false; 4639 } 4640 4641 *nv2gpa = 0; 4642 *nv2atsd = 0; 4643 return true; 4644 } 4645 static void spapr_machine_4_0_class_options(MachineClass *mc) 4646 { 4647 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4648 4649 spapr_machine_4_1_class_options(mc); 4650 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4651 smc->phb_placement = phb_placement_4_0; 4652 smc->irq = &spapr_irq_xics; 4653 smc->pre_4_1_migration = true; 4654 } 4655 4656 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4657 4658 /* 4659 * pseries-3.1 4660 */ 4661 static void spapr_machine_3_1_class_options(MachineClass *mc) 4662 { 4663 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4664 4665 spapr_machine_4_0_class_options(mc); 4666 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4667 4668 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4669 smc->update_dt_enabled = false; 4670 smc->dr_phb_enabled = false; 4671 smc->broken_host_serial_model = true; 4672 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4673 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4674 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4675 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4676 } 4677 4678 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4679 4680 /* 4681 * pseries-3.0 4682 */ 4683 4684 static void spapr_machine_3_0_class_options(MachineClass *mc) 4685 { 4686 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4687 4688 spapr_machine_3_1_class_options(mc); 4689 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4690 4691 smc->legacy_irq_allocation = true; 4692 smc->nr_xirqs = 0x400; 4693 smc->irq = &spapr_irq_xics_legacy; 4694 } 4695 4696 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4697 4698 /* 4699 * pseries-2.12 4700 */ 4701 static void spapr_machine_2_12_class_options(MachineClass *mc) 4702 { 4703 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4704 static GlobalProperty compat[] = { 4705 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4706 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4707 }; 4708 4709 spapr_machine_3_0_class_options(mc); 4710 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4711 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4712 4713 /* We depend on kvm_enabled() to choose a default value for the 4714 * hpt-max-page-size capability. Of course we can't do it here 4715 * because this is too early and the HW accelerator isn't initialzed 4716 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4717 */ 4718 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4719 } 4720 4721 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4722 4723 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4724 { 4725 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4726 4727 spapr_machine_2_12_class_options(mc); 4728 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4729 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4730 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4731 } 4732 4733 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4734 4735 /* 4736 * pseries-2.11 4737 */ 4738 4739 static void spapr_machine_2_11_class_options(MachineClass *mc) 4740 { 4741 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4742 4743 spapr_machine_2_12_class_options(mc); 4744 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4745 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4746 } 4747 4748 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4749 4750 /* 4751 * pseries-2.10 4752 */ 4753 4754 static void spapr_machine_2_10_class_options(MachineClass *mc) 4755 { 4756 spapr_machine_2_11_class_options(mc); 4757 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4758 } 4759 4760 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4761 4762 /* 4763 * pseries-2.9 4764 */ 4765 4766 static void spapr_machine_2_9_class_options(MachineClass *mc) 4767 { 4768 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4769 static GlobalProperty compat[] = { 4770 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4771 }; 4772 4773 spapr_machine_2_10_class_options(mc); 4774 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4775 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4776 smc->pre_2_10_has_unused_icps = true; 4777 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4778 } 4779 4780 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4781 4782 /* 4783 * pseries-2.8 4784 */ 4785 4786 static void spapr_machine_2_8_class_options(MachineClass *mc) 4787 { 4788 static GlobalProperty compat[] = { 4789 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4790 }; 4791 4792 spapr_machine_2_9_class_options(mc); 4793 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4794 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4795 mc->numa_mem_align_shift = 23; 4796 } 4797 4798 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4799 4800 /* 4801 * pseries-2.7 4802 */ 4803 4804 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4805 uint64_t *buid, hwaddr *pio, 4806 hwaddr *mmio32, hwaddr *mmio64, 4807 unsigned n_dma, uint32_t *liobns, 4808 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4809 { 4810 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4811 const uint64_t base_buid = 0x800000020000000ULL; 4812 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4813 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4814 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4815 const uint32_t max_index = 255; 4816 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4817 4818 uint64_t ram_top = MACHINE(spapr)->ram_size; 4819 hwaddr phb0_base, phb_base; 4820 int i; 4821 4822 /* Do we have device memory? */ 4823 if (MACHINE(spapr)->maxram_size > ram_top) { 4824 /* Can't just use maxram_size, because there may be an 4825 * alignment gap between normal and device memory regions 4826 */ 4827 ram_top = MACHINE(spapr)->device_memory->base + 4828 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4829 } 4830 4831 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4832 4833 if (index > max_index) { 4834 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4835 max_index); 4836 return false; 4837 } 4838 4839 *buid = base_buid + index; 4840 for (i = 0; i < n_dma; ++i) { 4841 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4842 } 4843 4844 phb_base = phb0_base + index * phb_spacing; 4845 *pio = phb_base + pio_offset; 4846 *mmio32 = phb_base + mmio_offset; 4847 /* 4848 * We don't set the 64-bit MMIO window, relying on the PHB's 4849 * fallback behaviour of automatically splitting a large "32-bit" 4850 * window into contiguous 32-bit and 64-bit windows 4851 */ 4852 4853 *nv2gpa = 0; 4854 *nv2atsd = 0; 4855 return true; 4856 } 4857 4858 static void spapr_machine_2_7_class_options(MachineClass *mc) 4859 { 4860 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4861 static GlobalProperty compat[] = { 4862 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4863 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4864 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4865 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4866 }; 4867 4868 spapr_machine_2_8_class_options(mc); 4869 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4870 mc->default_machine_opts = "modern-hotplug-events=off"; 4871 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4872 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4873 smc->phb_placement = phb_placement_2_7; 4874 } 4875 4876 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4877 4878 /* 4879 * pseries-2.6 4880 */ 4881 4882 static void spapr_machine_2_6_class_options(MachineClass *mc) 4883 { 4884 static GlobalProperty compat[] = { 4885 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4886 }; 4887 4888 spapr_machine_2_7_class_options(mc); 4889 mc->has_hotpluggable_cpus = false; 4890 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4891 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4892 } 4893 4894 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4895 4896 /* 4897 * pseries-2.5 4898 */ 4899 4900 static void spapr_machine_2_5_class_options(MachineClass *mc) 4901 { 4902 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4903 static GlobalProperty compat[] = { 4904 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4905 }; 4906 4907 spapr_machine_2_6_class_options(mc); 4908 smc->use_ohci_by_default = true; 4909 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4910 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4911 } 4912 4913 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4914 4915 /* 4916 * pseries-2.4 4917 */ 4918 4919 static void spapr_machine_2_4_class_options(MachineClass *mc) 4920 { 4921 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4922 4923 spapr_machine_2_5_class_options(mc); 4924 smc->dr_lmb_enabled = false; 4925 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4926 } 4927 4928 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4929 4930 /* 4931 * pseries-2.3 4932 */ 4933 4934 static void spapr_machine_2_3_class_options(MachineClass *mc) 4935 { 4936 static GlobalProperty compat[] = { 4937 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4938 }; 4939 spapr_machine_2_4_class_options(mc); 4940 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4941 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4942 } 4943 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4944 4945 /* 4946 * pseries-2.2 4947 */ 4948 4949 static void spapr_machine_2_2_class_options(MachineClass *mc) 4950 { 4951 static GlobalProperty compat[] = { 4952 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4953 }; 4954 4955 spapr_machine_2_3_class_options(mc); 4956 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4957 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4958 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4959 } 4960 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4961 4962 /* 4963 * pseries-2.1 4964 */ 4965 4966 static void spapr_machine_2_1_class_options(MachineClass *mc) 4967 { 4968 spapr_machine_2_2_class_options(mc); 4969 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4970 } 4971 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4972 4973 static void spapr_machine_register_types(void) 4974 { 4975 type_register_static(&spapr_machine_info); 4976 } 4977 4978 type_init(spapr_machine_register_types) 4979