1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "sysemu/sysemu.h" 28 #include "hw/hw.h" 29 #include "elf.h" 30 #include "net/net.h" 31 #include "sysemu/blockdev.h" 32 #include "sysemu/cpus.h" 33 #include "sysemu/kvm.h" 34 #include "kvm_ppc.h" 35 #include "mmu-hash64.h" 36 37 #include "hw/boards.h" 38 #include "hw/ppc/ppc.h" 39 #include "hw/loader.h" 40 41 #include "hw/ppc/spapr.h" 42 #include "hw/ppc/spapr_vio.h" 43 #include "hw/pci-host/spapr.h" 44 #include "hw/ppc/xics.h" 45 #include "hw/pci/msi.h" 46 47 #include "hw/pci/pci.h" 48 49 #include "exec/address-spaces.h" 50 #include "hw/usb.h" 51 #include "qemu/config-file.h" 52 #include "qemu/error-report.h" 53 54 #include <libfdt.h> 55 56 /* SLOF memory layout: 57 * 58 * SLOF raw image loaded at 0, copies its romfs right below the flat 59 * device-tree, then position SLOF itself 31M below that 60 * 61 * So we set FW_OVERHEAD to 40MB which should account for all of that 62 * and more 63 * 64 * We load our kernel at 4M, leaving space for SLOF initial image 65 */ 66 #define FDT_MAX_SIZE 0x40000 67 #define RTAS_MAX_SIZE 0x10000 68 #define FW_MAX_SIZE 0x400000 69 #define FW_FILE_NAME "slof.bin" 70 #define FW_OVERHEAD 0x2800000 71 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 72 73 #define MIN_RMA_SLOF 128UL 74 75 #define TIMEBASE_FREQ 512000000ULL 76 77 #define MAX_CPUS 256 78 #define XICS_IRQS 1024 79 80 #define PHANDLE_XICP 0x00001111 81 82 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 83 84 sPAPREnvironment *spapr; 85 86 int spapr_allocate_irq(int hint, bool lsi) 87 { 88 int irq; 89 90 if (hint) { 91 irq = hint; 92 if (hint >= spapr->next_irq) { 93 spapr->next_irq = hint + 1; 94 } 95 /* FIXME: we should probably check for collisions somehow */ 96 } else { 97 irq = spapr->next_irq++; 98 } 99 100 /* Configure irq type */ 101 if (!xics_get_qirq(spapr->icp, irq)) { 102 return 0; 103 } 104 105 xics_set_irq_type(spapr->icp, irq, lsi); 106 107 return irq; 108 } 109 110 /* 111 * Allocate block of consequtive IRQs, returns a number of the first. 112 * If msi==true, aligns the first IRQ number to num. 113 */ 114 int spapr_allocate_irq_block(int num, bool lsi, bool msi) 115 { 116 int first = -1; 117 int i, hint = 0; 118 119 /* 120 * MSIMesage::data is used for storing VIRQ so 121 * it has to be aligned to num to support multiple 122 * MSI vectors. MSI-X is not affected by this. 123 * The hint is used for the first IRQ, the rest should 124 * be allocated continuously. 125 */ 126 if (msi) { 127 assert((num == 1) || (num == 2) || (num == 4) || 128 (num == 8) || (num == 16) || (num == 32)); 129 hint = (spapr->next_irq + num - 1) & ~(num - 1); 130 } 131 132 for (i = 0; i < num; ++i) { 133 int irq; 134 135 irq = spapr_allocate_irq(hint, lsi); 136 if (!irq) { 137 return -1; 138 } 139 140 if (0 == i) { 141 first = irq; 142 hint = 0; 143 } 144 145 /* If the above doesn't create a consecutive block then that's 146 * an internal bug */ 147 assert(irq == (first + i)); 148 } 149 150 return first; 151 } 152 153 static XICSState *try_create_xics(const char *type, int nr_servers, 154 int nr_irqs) 155 { 156 DeviceState *dev; 157 158 dev = qdev_create(NULL, type); 159 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 160 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 161 if (qdev_init(dev) < 0) { 162 return NULL; 163 } 164 165 return XICS_COMMON(dev); 166 } 167 168 static XICSState *xics_system_init(int nr_servers, int nr_irqs) 169 { 170 XICSState *icp = NULL; 171 172 if (kvm_enabled()) { 173 QemuOpts *machine_opts = qemu_get_machine_opts(); 174 bool irqchip_allowed = qemu_opt_get_bool(machine_opts, 175 "kernel_irqchip", true); 176 bool irqchip_required = qemu_opt_get_bool(machine_opts, 177 "kernel_irqchip", false); 178 if (irqchip_allowed) { 179 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs); 180 } 181 182 if (irqchip_required && !icp) { 183 perror("Failed to create in-kernel XICS\n"); 184 abort(); 185 } 186 } 187 188 if (!icp) { 189 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs); 190 } 191 192 if (!icp) { 193 perror("Failed to create XICS\n"); 194 abort(); 195 } 196 197 return icp; 198 } 199 200 static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) 201 { 202 int ret = 0, offset; 203 CPUState *cpu; 204 char cpu_model[32]; 205 int smt = kvmppc_smt_threads(); 206 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 207 208 CPU_FOREACH(cpu) { 209 DeviceClass *dc = DEVICE_GET_CLASS(cpu); 210 uint32_t associativity[] = {cpu_to_be32(0x5), 211 cpu_to_be32(0x0), 212 cpu_to_be32(0x0), 213 cpu_to_be32(0x0), 214 cpu_to_be32(cpu->numa_node), 215 cpu_to_be32(cpu->cpu_index)}; 216 217 if ((cpu->cpu_index % smt) != 0) { 218 continue; 219 } 220 221 snprintf(cpu_model, 32, "/cpus/%s@%x", dc->fw_name, 222 cpu->cpu_index); 223 224 offset = fdt_path_offset(fdt, cpu_model); 225 if (offset < 0) { 226 return offset; 227 } 228 229 if (nb_numa_nodes > 1) { 230 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 231 sizeof(associativity)); 232 if (ret < 0) { 233 return ret; 234 } 235 } 236 237 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 238 pft_size_prop, sizeof(pft_size_prop)); 239 if (ret < 0) { 240 return ret; 241 } 242 } 243 return ret; 244 } 245 246 247 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 248 size_t maxsize) 249 { 250 size_t maxcells = maxsize / sizeof(uint32_t); 251 int i, j, count; 252 uint32_t *p = prop; 253 254 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 255 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 256 257 if (!sps->page_shift) { 258 break; 259 } 260 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 261 if (sps->enc[count].page_shift == 0) { 262 break; 263 } 264 } 265 if ((p - prop) >= (maxcells - 3 - count * 2)) { 266 break; 267 } 268 *(p++) = cpu_to_be32(sps->page_shift); 269 *(p++) = cpu_to_be32(sps->slb_enc); 270 *(p++) = cpu_to_be32(count); 271 for (j = 0; j < count; j++) { 272 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 273 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 274 } 275 } 276 277 return (p - prop) * sizeof(uint32_t); 278 } 279 280 #define _FDT(exp) \ 281 do { \ 282 int ret = (exp); \ 283 if (ret < 0) { \ 284 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 285 #exp, fdt_strerror(ret)); \ 286 exit(1); \ 287 } \ 288 } while (0) 289 290 291 static void *spapr_create_fdt_skel(hwaddr initrd_base, 292 hwaddr initrd_size, 293 hwaddr kernel_size, 294 bool little_endian, 295 const char *boot_device, 296 const char *kernel_cmdline, 297 uint32_t epow_irq) 298 { 299 void *fdt; 300 CPUState *cs; 301 uint32_t start_prop = cpu_to_be32(initrd_base); 302 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 303 char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt" 304 "\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk\0hcall-set-mode"; 305 char qemu_hypertas_prop[] = "hcall-memop1"; 306 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 307 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; 308 int i, smt = kvmppc_smt_threads(); 309 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 310 311 fdt = g_malloc0(FDT_MAX_SIZE); 312 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 313 314 if (kernel_size) { 315 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 316 } 317 if (initrd_size) { 318 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 319 } 320 _FDT((fdt_finish_reservemap(fdt))); 321 322 /* Root node */ 323 _FDT((fdt_begin_node(fdt, ""))); 324 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 325 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 326 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 327 328 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 329 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 330 331 /* /chosen */ 332 _FDT((fdt_begin_node(fdt, "chosen"))); 333 334 /* Set Form1_affinity */ 335 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 336 337 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 338 _FDT((fdt_property(fdt, "linux,initrd-start", 339 &start_prop, sizeof(start_prop)))); 340 _FDT((fdt_property(fdt, "linux,initrd-end", 341 &end_prop, sizeof(end_prop)))); 342 if (kernel_size) { 343 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 344 cpu_to_be64(kernel_size) }; 345 346 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 347 if (little_endian) { 348 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 349 } 350 } 351 if (boot_device) { 352 _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device))); 353 } 354 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 355 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 356 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 357 358 _FDT((fdt_end_node(fdt))); 359 360 /* cpus */ 361 _FDT((fdt_begin_node(fdt, "cpus"))); 362 363 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 364 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 365 366 CPU_FOREACH(cs) { 367 PowerPCCPU *cpu = POWERPC_CPU(cs); 368 CPUPPCState *env = &cpu->env; 369 DeviceClass *dc = DEVICE_GET_CLASS(cs); 370 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 371 int index = cs->cpu_index; 372 uint32_t servers_prop[smp_threads]; 373 uint32_t gservers_prop[smp_threads * 2]; 374 char *nodename; 375 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 376 0xffffffff, 0xffffffff}; 377 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 378 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 379 uint32_t page_sizes_prop[64]; 380 size_t page_sizes_prop_size; 381 382 if ((index % smt) != 0) { 383 continue; 384 } 385 386 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 387 388 _FDT((fdt_begin_node(fdt, nodename))); 389 390 g_free(nodename); 391 392 _FDT((fdt_property_cell(fdt, "reg", index))); 393 _FDT((fdt_property_string(fdt, "device_type", "cpu"))); 394 395 _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); 396 _FDT((fdt_property_cell(fdt, "d-cache-block-size", 397 env->dcache_line_size))); 398 _FDT((fdt_property_cell(fdt, "d-cache-line-size", 399 env->dcache_line_size))); 400 _FDT((fdt_property_cell(fdt, "i-cache-block-size", 401 env->icache_line_size))); 402 _FDT((fdt_property_cell(fdt, "i-cache-line-size", 403 env->icache_line_size))); 404 405 if (pcc->l1_dcache_size) { 406 _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size))); 407 } else { 408 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 409 } 410 if (pcc->l1_icache_size) { 411 _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size))); 412 } else { 413 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 414 } 415 416 _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq))); 417 _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq))); 418 _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); 419 _FDT((fdt_property_string(fdt, "status", "okay"))); 420 _FDT((fdt_property(fdt, "64-bit", NULL, 0))); 421 422 /* Build interrupt servers and gservers properties */ 423 for (i = 0; i < smp_threads; i++) { 424 servers_prop[i] = cpu_to_be32(index + i); 425 /* Hack, direct the group queues back to cpu 0 */ 426 gservers_prop[i*2] = cpu_to_be32(index + i); 427 gservers_prop[i*2 + 1] = 0; 428 } 429 _FDT((fdt_property(fdt, "ibm,ppc-interrupt-server#s", 430 servers_prop, sizeof(servers_prop)))); 431 _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s", 432 gservers_prop, sizeof(gservers_prop)))); 433 434 if (env->spr_cb[SPR_PURR].oea_read) { 435 _FDT((fdt_property(fdt, "ibm,purr", NULL, 0))); 436 } 437 438 if (env->mmu_model & POWERPC_MMU_1TSEG) { 439 _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", 440 segs, sizeof(segs)))); 441 } 442 443 /* Advertise VMX/VSX (vector extensions) if available 444 * 0 / no property == no vector extensions 445 * 1 == VMX / Altivec available 446 * 2 == VSX available */ 447 if (env->insns_flags & PPC_ALTIVEC) { 448 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 449 450 _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx))); 451 } 452 453 /* Advertise DFP (Decimal Floating Point) if available 454 * 0 / no property == no DFP 455 * 1 == DFP available */ 456 if (env->insns_flags2 & PPC2_DFP) { 457 _FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); 458 } 459 460 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 461 sizeof(page_sizes_prop)); 462 if (page_sizes_prop_size) { 463 _FDT((fdt_property(fdt, "ibm,segment-page-sizes", 464 page_sizes_prop, page_sizes_prop_size))); 465 } 466 467 _FDT((fdt_end_node(fdt))); 468 } 469 470 _FDT((fdt_end_node(fdt))); 471 472 /* RTAS */ 473 _FDT((fdt_begin_node(fdt, "rtas"))); 474 475 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop, 476 sizeof(hypertas_prop)))); 477 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas_prop, 478 sizeof(qemu_hypertas_prop)))); 479 480 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 481 refpoints, sizeof(refpoints)))); 482 483 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 484 485 _FDT((fdt_end_node(fdt))); 486 487 /* interrupt controller */ 488 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 489 490 _FDT((fdt_property_string(fdt, "device_type", 491 "PowerPC-External-Interrupt-Presentation"))); 492 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 493 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 494 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 495 interrupt_server_ranges_prop, 496 sizeof(interrupt_server_ranges_prop)))); 497 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 498 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 499 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 500 501 _FDT((fdt_end_node(fdt))); 502 503 /* vdevice */ 504 _FDT((fdt_begin_node(fdt, "vdevice"))); 505 506 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 507 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 508 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 509 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 510 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 511 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 512 513 _FDT((fdt_end_node(fdt))); 514 515 /* event-sources */ 516 spapr_events_fdt_skel(fdt, epow_irq); 517 518 _FDT((fdt_end_node(fdt))); /* close root node */ 519 _FDT((fdt_finish(fdt))); 520 521 return fdt; 522 } 523 524 static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt) 525 { 526 uint32_t associativity[] = {cpu_to_be32(0x4), cpu_to_be32(0x0), 527 cpu_to_be32(0x0), cpu_to_be32(0x0), 528 cpu_to_be32(0x0)}; 529 char mem_name[32]; 530 hwaddr node0_size, mem_start, node_size; 531 uint64_t mem_reg_property[2]; 532 int i, off; 533 534 /* memory node(s) */ 535 if (nb_numa_nodes > 1 && node_mem[0] < ram_size) { 536 node0_size = node_mem[0]; 537 } else { 538 node0_size = ram_size; 539 } 540 541 /* RMA */ 542 mem_reg_property[0] = 0; 543 mem_reg_property[1] = cpu_to_be64(spapr->rma_size); 544 off = fdt_add_subnode(fdt, 0, "memory@0"); 545 _FDT(off); 546 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 547 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 548 sizeof(mem_reg_property)))); 549 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 550 sizeof(associativity)))); 551 552 /* RAM: Node 0 */ 553 if (node0_size > spapr->rma_size) { 554 mem_reg_property[0] = cpu_to_be64(spapr->rma_size); 555 mem_reg_property[1] = cpu_to_be64(node0_size - spapr->rma_size); 556 557 sprintf(mem_name, "memory@" TARGET_FMT_lx, spapr->rma_size); 558 off = fdt_add_subnode(fdt, 0, mem_name); 559 _FDT(off); 560 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 561 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 562 sizeof(mem_reg_property)))); 563 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 564 sizeof(associativity)))); 565 } 566 567 /* RAM: Node 1 and beyond */ 568 mem_start = node0_size; 569 for (i = 1; i < nb_numa_nodes; i++) { 570 mem_reg_property[0] = cpu_to_be64(mem_start); 571 if (mem_start >= ram_size) { 572 node_size = 0; 573 } else { 574 node_size = node_mem[i]; 575 if (node_size > ram_size - mem_start) { 576 node_size = ram_size - mem_start; 577 } 578 } 579 mem_reg_property[1] = cpu_to_be64(node_size); 580 associativity[3] = associativity[4] = cpu_to_be32(i); 581 sprintf(mem_name, "memory@" TARGET_FMT_lx, mem_start); 582 off = fdt_add_subnode(fdt, 0, mem_name); 583 _FDT(off); 584 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 585 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 586 sizeof(mem_reg_property)))); 587 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 588 sizeof(associativity)))); 589 mem_start += node_size; 590 } 591 592 return 0; 593 } 594 595 static void spapr_finalize_fdt(sPAPREnvironment *spapr, 596 hwaddr fdt_addr, 597 hwaddr rtas_addr, 598 hwaddr rtas_size) 599 { 600 int ret; 601 void *fdt; 602 sPAPRPHBState *phb; 603 604 fdt = g_malloc(FDT_MAX_SIZE); 605 606 /* open out the base tree into a temp buffer for the final tweaks */ 607 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 608 609 ret = spapr_populate_memory(spapr, fdt); 610 if (ret < 0) { 611 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 612 exit(1); 613 } 614 615 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 616 if (ret < 0) { 617 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 618 exit(1); 619 } 620 621 QLIST_FOREACH(phb, &spapr->phbs, list) { 622 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 623 } 624 625 if (ret < 0) { 626 fprintf(stderr, "couldn't setup PCI devices in fdt\n"); 627 exit(1); 628 } 629 630 /* RTAS */ 631 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 632 if (ret < 0) { 633 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 634 } 635 636 /* Advertise NUMA via ibm,associativity */ 637 ret = spapr_fixup_cpu_dt(fdt, spapr); 638 if (ret < 0) { 639 fprintf(stderr, "Couldn't finalize CPU device tree properties\n"); 640 } 641 642 if (!spapr->has_graphics) { 643 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 644 } 645 646 _FDT((fdt_pack(fdt))); 647 648 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 649 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n", 650 fdt_totalsize(fdt), FDT_MAX_SIZE); 651 exit(1); 652 } 653 654 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 655 656 g_free(fdt); 657 } 658 659 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 660 { 661 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 662 } 663 664 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 665 { 666 CPUPPCState *env = &cpu->env; 667 668 if (msr_pr) { 669 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 670 env->gpr[3] = H_PRIVILEGE; 671 } else { 672 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 673 } 674 } 675 676 static void spapr_reset_htab(sPAPREnvironment *spapr) 677 { 678 long shift; 679 680 /* allocate hash page table. For now we always make this 16mb, 681 * later we should probably make it scale to the size of guest 682 * RAM */ 683 684 shift = kvmppc_reset_htab(spapr->htab_shift); 685 686 if (shift > 0) { 687 /* Kernel handles htab, we don't need to allocate one */ 688 spapr->htab_shift = shift; 689 } else { 690 if (!spapr->htab) { 691 /* Allocate an htab if we don't yet have one */ 692 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); 693 } 694 695 /* And clear it */ 696 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 697 } 698 699 /* Update the RMA size if necessary */ 700 if (spapr->vrma_adjust) { 701 hwaddr node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size; 702 spapr->rma_size = kvmppc_rma_size(node0_size, spapr->htab_shift); 703 } 704 } 705 706 static void ppc_spapr_reset(void) 707 { 708 PowerPCCPU *first_ppc_cpu; 709 710 /* Reset the hash table & recalc the RMA */ 711 spapr_reset_htab(spapr); 712 713 qemu_devices_reset(); 714 715 /* Load the fdt */ 716 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 717 spapr->rtas_size); 718 719 /* Set up the entry state */ 720 first_ppc_cpu = POWERPC_CPU(first_cpu); 721 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 722 first_ppc_cpu->env.gpr[5] = 0; 723 first_cpu->halted = 0; 724 first_ppc_cpu->env.nip = spapr->entry_point; 725 726 } 727 728 static void spapr_cpu_reset(void *opaque) 729 { 730 PowerPCCPU *cpu = opaque; 731 CPUState *cs = CPU(cpu); 732 CPUPPCState *env = &cpu->env; 733 734 cpu_reset(cs); 735 736 /* All CPUs start halted. CPU0 is unhalted from the machine level 737 * reset code and the rest are explicitly started up by the guest 738 * using an RTAS call */ 739 cs->halted = 1; 740 741 env->spr[SPR_HIOR] = 0; 742 743 env->external_htab = (uint8_t *)spapr->htab; 744 if (kvm_enabled() && !env->external_htab) { 745 /* 746 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte* 747 * functions do the right thing. 748 */ 749 env->external_htab = (void *)1; 750 } 751 env->htab_base = -1; 752 env->htab_mask = HTAB_SIZE(spapr) - 1; 753 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | 754 (spapr->htab_shift - 18); 755 } 756 757 static void spapr_create_nvram(sPAPREnvironment *spapr) 758 { 759 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 760 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 761 762 if (dinfo) { 763 qdev_prop_set_drive_nofail(dev, "drive", dinfo->bdrv); 764 } 765 766 qdev_init_nofail(dev); 767 768 spapr->nvram = (struct sPAPRNVRAM *)dev; 769 } 770 771 /* Returns whether we want to use VGA or not */ 772 static int spapr_vga_init(PCIBus *pci_bus) 773 { 774 switch (vga_interface_type) { 775 case VGA_NONE: 776 case VGA_STD: 777 return pci_vga_init(pci_bus) != NULL; 778 default: 779 fprintf(stderr, "This vga model is not supported," 780 "currently it only supports -vga std\n"); 781 exit(0); 782 break; 783 } 784 } 785 786 static const VMStateDescription vmstate_spapr = { 787 .name = "spapr", 788 .version_id = 1, 789 .minimum_version_id = 1, 790 .minimum_version_id_old = 1, 791 .fields = (VMStateField []) { 792 VMSTATE_UINT32(next_irq, sPAPREnvironment), 793 794 /* RTC offset */ 795 VMSTATE_UINT64(rtc_offset, sPAPREnvironment), 796 797 VMSTATE_END_OF_LIST() 798 }, 799 }; 800 801 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 802 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 803 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 804 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 805 806 static int htab_save_setup(QEMUFile *f, void *opaque) 807 { 808 sPAPREnvironment *spapr = opaque; 809 810 /* "Iteration" header */ 811 qemu_put_be32(f, spapr->htab_shift); 812 813 if (spapr->htab) { 814 spapr->htab_save_index = 0; 815 spapr->htab_first_pass = true; 816 } else { 817 assert(kvm_enabled()); 818 819 spapr->htab_fd = kvmppc_get_htab_fd(false); 820 if (spapr->htab_fd < 0) { 821 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", 822 strerror(errno)); 823 return -1; 824 } 825 } 826 827 828 return 0; 829 } 830 831 static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr, 832 int64_t max_ns) 833 { 834 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 835 int index = spapr->htab_save_index; 836 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 837 838 assert(spapr->htab_first_pass); 839 840 do { 841 int chunkstart; 842 843 /* Consume invalid HPTEs */ 844 while ((index < htabslots) 845 && !HPTE_VALID(HPTE(spapr->htab, index))) { 846 index++; 847 CLEAN_HPTE(HPTE(spapr->htab, index)); 848 } 849 850 /* Consume valid HPTEs */ 851 chunkstart = index; 852 while ((index < htabslots) 853 && HPTE_VALID(HPTE(spapr->htab, index))) { 854 index++; 855 CLEAN_HPTE(HPTE(spapr->htab, index)); 856 } 857 858 if (index > chunkstart) { 859 int n_valid = index - chunkstart; 860 861 qemu_put_be32(f, chunkstart); 862 qemu_put_be16(f, n_valid); 863 qemu_put_be16(f, 0); 864 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 865 HASH_PTE_SIZE_64 * n_valid); 866 867 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 868 break; 869 } 870 } 871 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 872 873 if (index >= htabslots) { 874 assert(index == htabslots); 875 index = 0; 876 spapr->htab_first_pass = false; 877 } 878 spapr->htab_save_index = index; 879 } 880 881 static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, 882 int64_t max_ns) 883 { 884 bool final = max_ns < 0; 885 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 886 int examined = 0, sent = 0; 887 int index = spapr->htab_save_index; 888 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 889 890 assert(!spapr->htab_first_pass); 891 892 do { 893 int chunkstart, invalidstart; 894 895 /* Consume non-dirty HPTEs */ 896 while ((index < htabslots) 897 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 898 index++; 899 examined++; 900 } 901 902 chunkstart = index; 903 /* Consume valid dirty HPTEs */ 904 while ((index < htabslots) 905 && HPTE_DIRTY(HPTE(spapr->htab, index)) 906 && HPTE_VALID(HPTE(spapr->htab, index))) { 907 CLEAN_HPTE(HPTE(spapr->htab, index)); 908 index++; 909 examined++; 910 } 911 912 invalidstart = index; 913 /* Consume invalid dirty HPTEs */ 914 while ((index < htabslots) 915 && HPTE_DIRTY(HPTE(spapr->htab, index)) 916 && !HPTE_VALID(HPTE(spapr->htab, index))) { 917 CLEAN_HPTE(HPTE(spapr->htab, index)); 918 index++; 919 examined++; 920 } 921 922 if (index > chunkstart) { 923 int n_valid = invalidstart - chunkstart; 924 int n_invalid = index - invalidstart; 925 926 qemu_put_be32(f, chunkstart); 927 qemu_put_be16(f, n_valid); 928 qemu_put_be16(f, n_invalid); 929 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 930 HASH_PTE_SIZE_64 * n_valid); 931 sent += index - chunkstart; 932 933 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 934 break; 935 } 936 } 937 938 if (examined >= htabslots) { 939 break; 940 } 941 942 if (index >= htabslots) { 943 assert(index == htabslots); 944 index = 0; 945 } 946 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 947 948 if (index >= htabslots) { 949 assert(index == htabslots); 950 index = 0; 951 } 952 953 spapr->htab_save_index = index; 954 955 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 956 } 957 958 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 959 #define MAX_KVM_BUF_SIZE 2048 960 961 static int htab_save_iterate(QEMUFile *f, void *opaque) 962 { 963 sPAPREnvironment *spapr = opaque; 964 int rc = 0; 965 966 /* Iteration header */ 967 qemu_put_be32(f, 0); 968 969 if (!spapr->htab) { 970 assert(kvm_enabled()); 971 972 rc = kvmppc_save_htab(f, spapr->htab_fd, 973 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 974 if (rc < 0) { 975 return rc; 976 } 977 } else if (spapr->htab_first_pass) { 978 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 979 } else { 980 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 981 } 982 983 /* End marker */ 984 qemu_put_be32(f, 0); 985 qemu_put_be16(f, 0); 986 qemu_put_be16(f, 0); 987 988 return rc; 989 } 990 991 static int htab_save_complete(QEMUFile *f, void *opaque) 992 { 993 sPAPREnvironment *spapr = opaque; 994 995 /* Iteration header */ 996 qemu_put_be32(f, 0); 997 998 if (!spapr->htab) { 999 int rc; 1000 1001 assert(kvm_enabled()); 1002 1003 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); 1004 if (rc < 0) { 1005 return rc; 1006 } 1007 close(spapr->htab_fd); 1008 spapr->htab_fd = -1; 1009 } else { 1010 htab_save_later_pass(f, spapr, -1); 1011 } 1012 1013 /* End marker */ 1014 qemu_put_be32(f, 0); 1015 qemu_put_be16(f, 0); 1016 qemu_put_be16(f, 0); 1017 1018 return 0; 1019 } 1020 1021 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1022 { 1023 sPAPREnvironment *spapr = opaque; 1024 uint32_t section_hdr; 1025 int fd = -1; 1026 1027 if (version_id < 1 || version_id > 1) { 1028 fprintf(stderr, "htab_load() bad version\n"); 1029 return -EINVAL; 1030 } 1031 1032 section_hdr = qemu_get_be32(f); 1033 1034 if (section_hdr) { 1035 /* First section, just the hash shift */ 1036 if (spapr->htab_shift != section_hdr) { 1037 return -EINVAL; 1038 } 1039 return 0; 1040 } 1041 1042 if (!spapr->htab) { 1043 assert(kvm_enabled()); 1044 1045 fd = kvmppc_get_htab_fd(true); 1046 if (fd < 0) { 1047 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", 1048 strerror(errno)); 1049 } 1050 } 1051 1052 while (true) { 1053 uint32_t index; 1054 uint16_t n_valid, n_invalid; 1055 1056 index = qemu_get_be32(f); 1057 n_valid = qemu_get_be16(f); 1058 n_invalid = qemu_get_be16(f); 1059 1060 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1061 /* End of Stream */ 1062 break; 1063 } 1064 1065 if ((index + n_valid + n_invalid) > 1066 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1067 /* Bad index in stream */ 1068 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " 1069 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, 1070 spapr->htab_shift); 1071 return -EINVAL; 1072 } 1073 1074 if (spapr->htab) { 1075 if (n_valid) { 1076 qemu_get_buffer(f, HPTE(spapr->htab, index), 1077 HASH_PTE_SIZE_64 * n_valid); 1078 } 1079 if (n_invalid) { 1080 memset(HPTE(spapr->htab, index + n_valid), 0, 1081 HASH_PTE_SIZE_64 * n_invalid); 1082 } 1083 } else { 1084 int rc; 1085 1086 assert(fd >= 0); 1087 1088 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1089 if (rc < 0) { 1090 return rc; 1091 } 1092 } 1093 } 1094 1095 if (!spapr->htab) { 1096 assert(fd >= 0); 1097 close(fd); 1098 } 1099 1100 return 0; 1101 } 1102 1103 static SaveVMHandlers savevm_htab_handlers = { 1104 .save_live_setup = htab_save_setup, 1105 .save_live_iterate = htab_save_iterate, 1106 .save_live_complete = htab_save_complete, 1107 .load_state = htab_load, 1108 }; 1109 1110 /* pSeries LPAR / sPAPR hardware init */ 1111 static void ppc_spapr_init(QEMUMachineInitArgs *args) 1112 { 1113 ram_addr_t ram_size = args->ram_size; 1114 const char *cpu_model = args->cpu_model; 1115 const char *kernel_filename = args->kernel_filename; 1116 const char *kernel_cmdline = args->kernel_cmdline; 1117 const char *initrd_filename = args->initrd_filename; 1118 const char *boot_device = args->boot_order; 1119 PowerPCCPU *cpu; 1120 CPUPPCState *env; 1121 PCIHostState *phb; 1122 int i; 1123 MemoryRegion *sysmem = get_system_memory(); 1124 MemoryRegion *ram = g_new(MemoryRegion, 1); 1125 hwaddr rma_alloc_size; 1126 hwaddr node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size; 1127 uint32_t initrd_base = 0; 1128 long kernel_size = 0, initrd_size = 0; 1129 long load_limit, rtas_limit, fw_size; 1130 bool kernel_le = false; 1131 char *filename; 1132 1133 msi_supported = true; 1134 1135 spapr = g_malloc0(sizeof(*spapr)); 1136 QLIST_INIT(&spapr->phbs); 1137 1138 cpu_ppc_hypercall = emulate_spapr_hypercall; 1139 1140 /* Allocate RMA if necessary */ 1141 rma_alloc_size = kvmppc_alloc_rma("ppc_spapr.rma", sysmem); 1142 1143 if (rma_alloc_size == -1) { 1144 hw_error("qemu: Unable to create RMA\n"); 1145 exit(1); 1146 } 1147 1148 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1149 spapr->rma_size = rma_alloc_size; 1150 } else { 1151 spapr->rma_size = node0_size; 1152 1153 /* With KVM, we don't actually know whether KVM supports an 1154 * unbounded RMA (PR KVM) or is limited by the hash table size 1155 * (HV KVM using VRMA), so we always assume the latter 1156 * 1157 * In that case, we also limit the initial allocations for RTAS 1158 * etc... to 256M since we have no way to know what the VRMA size 1159 * is going to be as it depends on the size of the hash table 1160 * isn't determined yet. 1161 */ 1162 if (kvm_enabled()) { 1163 spapr->vrma_adjust = 1; 1164 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1165 } 1166 } 1167 1168 if (spapr->rma_size > node0_size) { 1169 fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n", 1170 spapr->rma_size); 1171 exit(1); 1172 } 1173 1174 /* We place the device tree and RTAS just below either the top of the RMA, 1175 * or just below 2GB, whichever is lowere, so that it can be 1176 * processed with 32-bit real mode code if necessary */ 1177 rtas_limit = MIN(spapr->rma_size, 0x80000000); 1178 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1179 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 1180 load_limit = spapr->fdt_addr - FW_OVERHEAD; 1181 1182 /* We aim for a hash table of size 1/128 the size of RAM. The 1183 * normal rule of thumb is 1/64 the size of RAM, but that's much 1184 * more than needed for the Linux guests we support. */ 1185 spapr->htab_shift = 18; /* Minimum architected size */ 1186 while (spapr->htab_shift <= 46) { 1187 if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) { 1188 break; 1189 } 1190 spapr->htab_shift++; 1191 } 1192 1193 /* Set up Interrupt Controller before we create the VCPUs */ 1194 spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads, 1195 XICS_IRQS); 1196 spapr->next_irq = XICS_IRQ_BASE; 1197 1198 /* init CPUs */ 1199 if (cpu_model == NULL) { 1200 cpu_model = kvm_enabled() ? "host" : "POWER7"; 1201 } 1202 for (i = 0; i < smp_cpus; i++) { 1203 cpu = cpu_ppc_init(cpu_model); 1204 if (cpu == NULL) { 1205 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 1206 exit(1); 1207 } 1208 env = &cpu->env; 1209 1210 /* Set time-base frequency to 512 MHz */ 1211 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 1212 1213 /* PAPR always has exception vectors in RAM not ROM. To ensure this, 1214 * MSR[IP] should never be set. 1215 */ 1216 env->msr_mask &= ~(1 << 6); 1217 1218 /* Tell KVM that we're in PAPR mode */ 1219 if (kvm_enabled()) { 1220 kvmppc_set_papr(cpu); 1221 } 1222 1223 xics_cpu_setup(spapr->icp, cpu); 1224 1225 qemu_register_reset(spapr_cpu_reset, cpu); 1226 } 1227 1228 /* allocate RAM */ 1229 spapr->ram_limit = ram_size; 1230 if (spapr->ram_limit > rma_alloc_size) { 1231 ram_addr_t nonrma_base = rma_alloc_size; 1232 ram_addr_t nonrma_size = spapr->ram_limit - rma_alloc_size; 1233 1234 memory_region_init_ram(ram, NULL, "ppc_spapr.ram", nonrma_size); 1235 vmstate_register_ram_global(ram); 1236 memory_region_add_subregion(sysmem, nonrma_base, ram); 1237 } 1238 1239 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1240 spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr, 1241 rtas_limit - spapr->rtas_addr); 1242 if (spapr->rtas_size < 0) { 1243 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1244 exit(1); 1245 } 1246 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1247 hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n", 1248 spapr->rtas_size, RTAS_MAX_SIZE); 1249 exit(1); 1250 } 1251 g_free(filename); 1252 1253 /* Set up EPOW events infrastructure */ 1254 spapr_events_init(spapr); 1255 1256 /* Set up VIO bus */ 1257 spapr->vio_bus = spapr_vio_bus_init(); 1258 1259 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1260 if (serial_hds[i]) { 1261 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1262 } 1263 } 1264 1265 /* We always have at least the nvram device on VIO */ 1266 spapr_create_nvram(spapr); 1267 1268 /* Set up PCI */ 1269 spapr_pci_msi_init(spapr, SPAPR_PCI_MSI_WINDOW); 1270 spapr_pci_rtas_init(); 1271 1272 phb = spapr_create_phb(spapr, 0); 1273 1274 for (i = 0; i < nb_nics; i++) { 1275 NICInfo *nd = &nd_table[i]; 1276 1277 if (!nd->model) { 1278 nd->model = g_strdup("ibmveth"); 1279 } 1280 1281 if (strcmp(nd->model, "ibmveth") == 0) { 1282 spapr_vlan_create(spapr->vio_bus, nd); 1283 } else { 1284 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1285 } 1286 } 1287 1288 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1289 spapr_vscsi_create(spapr->vio_bus); 1290 } 1291 1292 /* Graphics */ 1293 if (spapr_vga_init(phb->bus)) { 1294 spapr->has_graphics = true; 1295 } 1296 1297 if (usb_enabled(spapr->has_graphics)) { 1298 pci_create_simple(phb->bus, -1, "pci-ohci"); 1299 if (spapr->has_graphics) { 1300 usbdevice_create("keyboard"); 1301 usbdevice_create("mouse"); 1302 } 1303 } 1304 1305 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1306 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " 1307 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); 1308 exit(1); 1309 } 1310 1311 if (kernel_filename) { 1312 uint64_t lowaddr = 0; 1313 1314 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1315 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); 1316 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { 1317 kernel_size = load_elf(kernel_filename, 1318 translate_kernel_address, NULL, 1319 NULL, &lowaddr, NULL, 0, ELF_MACHINE, 0); 1320 kernel_le = kernel_size > 0; 1321 } 1322 if (kernel_size < 0) { 1323 fprintf(stderr, "qemu: error loading %s: %s\n", 1324 kernel_filename, load_elf_strerror(kernel_size)); 1325 exit(1); 1326 } 1327 1328 /* load initrd */ 1329 if (initrd_filename) { 1330 /* Try to locate the initrd in the gap between the kernel 1331 * and the firmware. Add a bit of space just in case 1332 */ 1333 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1334 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1335 load_limit - initrd_base); 1336 if (initrd_size < 0) { 1337 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 1338 initrd_filename); 1339 exit(1); 1340 } 1341 } else { 1342 initrd_base = 0; 1343 initrd_size = 0; 1344 } 1345 } 1346 1347 if (bios_name == NULL) { 1348 bios_name = FW_FILE_NAME; 1349 } 1350 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1351 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 1352 if (fw_size < 0) { 1353 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1354 exit(1); 1355 } 1356 g_free(filename); 1357 1358 spapr->entry_point = 0x100; 1359 1360 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 1361 register_savevm_live(NULL, "spapr/htab", -1, 1, 1362 &savevm_htab_handlers, spapr); 1363 1364 /* Prepare the device tree */ 1365 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 1366 kernel_size, kernel_le, 1367 boot_device, kernel_cmdline, 1368 spapr->epow_irq); 1369 assert(spapr->fdt_skel != NULL); 1370 } 1371 1372 static int spapr_kvm_type(const char *vm_type) 1373 { 1374 if (!vm_type) { 1375 return 0; 1376 } 1377 1378 if (!strcmp(vm_type, "HV")) { 1379 return 1; 1380 } 1381 1382 if (!strcmp(vm_type, "PR")) { 1383 return 2; 1384 } 1385 1386 error_report("Unknown kvm-type specified '%s'", vm_type); 1387 exit(1); 1388 } 1389 1390 static QEMUMachine spapr_machine = { 1391 .name = "pseries", 1392 .desc = "pSeries Logical Partition (PAPR compliant)", 1393 .is_default = 1, 1394 .init = ppc_spapr_init, 1395 .reset = ppc_spapr_reset, 1396 .block_default_type = IF_SCSI, 1397 .max_cpus = MAX_CPUS, 1398 .no_parallel = 1, 1399 .default_boot_order = NULL, 1400 .kvm_type = spapr_kvm_type, 1401 }; 1402 1403 static void spapr_machine_init(void) 1404 { 1405 qemu_register_machine(&spapr_machine); 1406 } 1407 1408 machine_init(spapr_machine_init); 1409