1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/datadir.h" 30 #include "qapi/error.h" 31 #include "qapi/qapi-events-machine.h" 32 #include "qapi/qapi-events-qdev.h" 33 #include "qapi/visitor.h" 34 #include "sysemu/sysemu.h" 35 #include "sysemu/hostmem.h" 36 #include "sysemu/numa.h" 37 #include "sysemu/qtest.h" 38 #include "sysemu/reset.h" 39 #include "sysemu/runstate.h" 40 #include "qemu/log.h" 41 #include "hw/fw-path-provider.h" 42 #include "elf.h" 43 #include "net/net.h" 44 #include "sysemu/device_tree.h" 45 #include "sysemu/cpus.h" 46 #include "sysemu/hw_accel.h" 47 #include "kvm_ppc.h" 48 #include "migration/misc.h" 49 #include "migration/qemu-file-types.h" 50 #include "migration/global_state.h" 51 #include "migration/register.h" 52 #include "migration/blocker.h" 53 #include "mmu-hash64.h" 54 #include "mmu-book3s-v3.h" 55 #include "cpu-models.h" 56 #include "hw/core/cpu.h" 57 58 #include "hw/ppc/ppc.h" 59 #include "hw/loader.h" 60 61 #include "hw/ppc/fdt.h" 62 #include "hw/ppc/spapr.h" 63 #include "hw/ppc/spapr_vio.h" 64 #include "hw/qdev-properties.h" 65 #include "hw/pci-host/spapr.h" 66 #include "hw/pci/msi.h" 67 68 #include "hw/pci/pci.h" 69 #include "hw/scsi/scsi.h" 70 #include "hw/virtio/virtio-scsi.h" 71 #include "hw/virtio/vhost-scsi-common.h" 72 73 #include "exec/ram_addr.h" 74 #include "hw/usb.h" 75 #include "qemu/config-file.h" 76 #include "qemu/error-report.h" 77 #include "trace.h" 78 #include "hw/nmi.h" 79 #include "hw/intc/intc.h" 80 81 #include "hw/ppc/spapr_cpu_core.h" 82 #include "hw/mem/memory-device.h" 83 #include "hw/ppc/spapr_tpm_proxy.h" 84 #include "hw/ppc/spapr_nvdimm.h" 85 #include "hw/ppc/spapr_numa.h" 86 #include "hw/ppc/pef.h" 87 88 #include "monitor/monitor.h" 89 90 #include <libfdt.h> 91 92 /* SLOF memory layout: 93 * 94 * SLOF raw image loaded at 0, copies its romfs right below the flat 95 * device-tree, then position SLOF itself 31M below that 96 * 97 * So we set FW_OVERHEAD to 40MB which should account for all of that 98 * and more 99 * 100 * We load our kernel at 4M, leaving space for SLOF initial image 101 */ 102 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */ 103 #define FW_MAX_SIZE 0x400000 104 #define FW_FILE_NAME "slof.bin" 105 #define FW_FILE_NAME_VOF "vof.bin" 106 #define FW_OVERHEAD 0x2800000 107 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 108 109 #define MIN_RMA_SLOF (128 * MiB) 110 111 #define PHANDLE_INTC 0x00001111 112 113 /* These two functions implement the VCPU id numbering: one to compute them 114 * all and one to identify thread 0 of a VCORE. Any change to the first one 115 * is likely to have an impact on the second one, so let's keep them close. 116 */ 117 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 118 { 119 MachineState *ms = MACHINE(spapr); 120 unsigned int smp_threads = ms->smp.threads; 121 122 assert(spapr->vsmt); 123 return 124 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 125 } 126 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 127 PowerPCCPU *cpu) 128 { 129 assert(spapr->vsmt); 130 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 131 } 132 133 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 134 { 135 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 136 * and newer QEMUs don't even have them. In both cases, we don't want 137 * to send anything on the wire. 138 */ 139 return false; 140 } 141 142 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 143 .name = "icp/server", 144 .version_id = 1, 145 .minimum_version_id = 1, 146 .needed = pre_2_10_vmstate_dummy_icp_needed, 147 .fields = (VMStateField[]) { 148 VMSTATE_UNUSED(4), /* uint32_t xirr */ 149 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 150 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 151 VMSTATE_END_OF_LIST() 152 }, 153 }; 154 155 static void pre_2_10_vmstate_register_dummy_icp(int i) 156 { 157 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 158 (void *)(uintptr_t) i); 159 } 160 161 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 162 { 163 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 164 (void *)(uintptr_t) i); 165 } 166 167 int spapr_max_server_number(SpaprMachineState *spapr) 168 { 169 MachineState *ms = MACHINE(spapr); 170 171 assert(spapr->vsmt); 172 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 173 } 174 175 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 176 int smt_threads) 177 { 178 int i, ret = 0; 179 uint32_t servers_prop[smt_threads]; 180 uint32_t gservers_prop[smt_threads * 2]; 181 int index = spapr_get_vcpu_id(cpu); 182 183 if (cpu->compat_pvr) { 184 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 185 if (ret < 0) { 186 return ret; 187 } 188 } 189 190 /* Build interrupt servers and gservers properties */ 191 for (i = 0; i < smt_threads; i++) { 192 servers_prop[i] = cpu_to_be32(index + i); 193 /* Hack, direct the group queues back to cpu 0 */ 194 gservers_prop[i*2] = cpu_to_be32(index + i); 195 gservers_prop[i*2 + 1] = 0; 196 } 197 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 198 servers_prop, sizeof(servers_prop)); 199 if (ret < 0) { 200 return ret; 201 } 202 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 203 gservers_prop, sizeof(gservers_prop)); 204 205 return ret; 206 } 207 208 static void spapr_dt_pa_features(SpaprMachineState *spapr, 209 PowerPCCPU *cpu, 210 void *fdt, int offset) 211 { 212 uint8_t pa_features_206[] = { 6, 0, 213 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 214 uint8_t pa_features_207[] = { 24, 0, 215 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 216 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 217 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 218 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 219 uint8_t pa_features_300[] = { 66, 0, 220 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 221 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 222 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 223 /* 6: DS207 */ 224 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 225 /* 16: Vector */ 226 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 227 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 228 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 229 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 230 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 231 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 232 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 233 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 235 /* 42: PM, 44: PC RA, 46: SC vec'd */ 236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 237 /* 48: SIMD, 50: QP BFP, 52: String */ 238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 239 /* 54: DecFP, 56: DecI, 58: SHA */ 240 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 241 /* 60: NM atomic, 62: RNG */ 242 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 243 }; 244 uint8_t *pa_features = NULL; 245 size_t pa_size; 246 247 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 248 pa_features = pa_features_206; 249 pa_size = sizeof(pa_features_206); 250 } 251 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 252 pa_features = pa_features_207; 253 pa_size = sizeof(pa_features_207); 254 } 255 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 256 pa_features = pa_features_300; 257 pa_size = sizeof(pa_features_300); 258 } 259 if (!pa_features) { 260 return; 261 } 262 263 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 264 /* 265 * Note: we keep CI large pages off by default because a 64K capable 266 * guest provisioned with large pages might otherwise try to map a qemu 267 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 268 * even if that qemu runs on a 4k host. 269 * We dd this bit back here if we are confident this is not an issue 270 */ 271 pa_features[3] |= 0x20; 272 } 273 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 274 pa_features[24] |= 0x80; /* Transactional memory support */ 275 } 276 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 277 /* Workaround for broken kernels that attempt (guest) radix 278 * mode when they can't handle it, if they see the radix bit set 279 * in pa-features. So hide it from them. */ 280 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 281 } 282 283 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 284 } 285 286 static hwaddr spapr_node0_size(MachineState *machine) 287 { 288 if (machine->numa_state->num_nodes) { 289 int i; 290 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 291 if (machine->numa_state->nodes[i].node_mem) { 292 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 293 machine->ram_size); 294 } 295 } 296 } 297 return machine->ram_size; 298 } 299 300 static void add_str(GString *s, const gchar *s1) 301 { 302 g_string_append_len(s, s1, strlen(s1) + 1); 303 } 304 305 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 306 hwaddr start, hwaddr size) 307 { 308 char mem_name[32]; 309 uint64_t mem_reg_property[2]; 310 int off; 311 312 mem_reg_property[0] = cpu_to_be64(start); 313 mem_reg_property[1] = cpu_to_be64(size); 314 315 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 316 off = fdt_add_subnode(fdt, 0, mem_name); 317 _FDT(off); 318 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 319 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 320 sizeof(mem_reg_property)))); 321 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 322 return off; 323 } 324 325 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 326 { 327 MemoryDeviceInfoList *info; 328 329 for (info = list; info; info = info->next) { 330 MemoryDeviceInfo *value = info->value; 331 332 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 333 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 334 335 if (addr >= pcdimm_info->addr && 336 addr < (pcdimm_info->addr + pcdimm_info->size)) { 337 return pcdimm_info->node; 338 } 339 } 340 } 341 342 return -1; 343 } 344 345 struct sPAPRDrconfCellV2 { 346 uint32_t seq_lmbs; 347 uint64_t base_addr; 348 uint32_t drc_index; 349 uint32_t aa_index; 350 uint32_t flags; 351 } QEMU_PACKED; 352 353 typedef struct DrconfCellQueue { 354 struct sPAPRDrconfCellV2 cell; 355 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 356 } DrconfCellQueue; 357 358 static DrconfCellQueue * 359 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 360 uint32_t drc_index, uint32_t aa_index, 361 uint32_t flags) 362 { 363 DrconfCellQueue *elem; 364 365 elem = g_malloc0(sizeof(*elem)); 366 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 367 elem->cell.base_addr = cpu_to_be64(base_addr); 368 elem->cell.drc_index = cpu_to_be32(drc_index); 369 elem->cell.aa_index = cpu_to_be32(aa_index); 370 elem->cell.flags = cpu_to_be32(flags); 371 372 return elem; 373 } 374 375 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 376 int offset, MemoryDeviceInfoList *dimms) 377 { 378 MachineState *machine = MACHINE(spapr); 379 uint8_t *int_buf, *cur_index; 380 int ret; 381 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 382 uint64_t addr, cur_addr, size; 383 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 384 uint64_t mem_end = machine->device_memory->base + 385 memory_region_size(&machine->device_memory->mr); 386 uint32_t node, buf_len, nr_entries = 0; 387 SpaprDrc *drc; 388 DrconfCellQueue *elem, *next; 389 MemoryDeviceInfoList *info; 390 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 391 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 392 393 /* Entry to cover RAM and the gap area */ 394 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 395 SPAPR_LMB_FLAGS_RESERVED | 396 SPAPR_LMB_FLAGS_DRC_INVALID); 397 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 398 nr_entries++; 399 400 cur_addr = machine->device_memory->base; 401 for (info = dimms; info; info = info->next) { 402 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 403 404 addr = di->addr; 405 size = di->size; 406 node = di->node; 407 408 /* 409 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 410 * area is marked hotpluggable in the next iteration for the bigger 411 * chunk including the NVDIMM occupied area. 412 */ 413 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 414 continue; 415 416 /* Entry for hot-pluggable area */ 417 if (cur_addr < addr) { 418 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 419 g_assert(drc); 420 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 421 cur_addr, spapr_drc_index(drc), -1, 0); 422 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 423 nr_entries++; 424 } 425 426 /* Entry for DIMM */ 427 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 428 g_assert(drc); 429 elem = spapr_get_drconf_cell(size / lmb_size, addr, 430 spapr_drc_index(drc), node, 431 (SPAPR_LMB_FLAGS_ASSIGNED | 432 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 433 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 434 nr_entries++; 435 cur_addr = addr + size; 436 } 437 438 /* Entry for remaining hotpluggable area */ 439 if (cur_addr < mem_end) { 440 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 441 g_assert(drc); 442 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 443 cur_addr, spapr_drc_index(drc), -1, 0); 444 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 445 nr_entries++; 446 } 447 448 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 449 int_buf = cur_index = g_malloc0(buf_len); 450 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 451 cur_index += sizeof(nr_entries); 452 453 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 454 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 455 cur_index += sizeof(elem->cell); 456 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 457 g_free(elem); 458 } 459 460 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 461 g_free(int_buf); 462 if (ret < 0) { 463 return -1; 464 } 465 return 0; 466 } 467 468 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 469 int offset, MemoryDeviceInfoList *dimms) 470 { 471 MachineState *machine = MACHINE(spapr); 472 int i, ret; 473 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 474 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 475 uint32_t nr_lmbs = (machine->device_memory->base + 476 memory_region_size(&machine->device_memory->mr)) / 477 lmb_size; 478 uint32_t *int_buf, *cur_index, buf_len; 479 480 /* 481 * Allocate enough buffer size to fit in ibm,dynamic-memory 482 */ 483 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 484 cur_index = int_buf = g_malloc0(buf_len); 485 int_buf[0] = cpu_to_be32(nr_lmbs); 486 cur_index++; 487 for (i = 0; i < nr_lmbs; i++) { 488 uint64_t addr = i * lmb_size; 489 uint32_t *dynamic_memory = cur_index; 490 491 if (i >= device_lmb_start) { 492 SpaprDrc *drc; 493 494 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 495 g_assert(drc); 496 497 dynamic_memory[0] = cpu_to_be32(addr >> 32); 498 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 499 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 500 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 501 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 502 if (memory_region_present(get_system_memory(), addr)) { 503 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 504 } else { 505 dynamic_memory[5] = cpu_to_be32(0); 506 } 507 } else { 508 /* 509 * LMB information for RMA, boot time RAM and gap b/n RAM and 510 * device memory region -- all these are marked as reserved 511 * and as having no valid DRC. 512 */ 513 dynamic_memory[0] = cpu_to_be32(addr >> 32); 514 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 515 dynamic_memory[2] = cpu_to_be32(0); 516 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 517 dynamic_memory[4] = cpu_to_be32(-1); 518 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 519 SPAPR_LMB_FLAGS_DRC_INVALID); 520 } 521 522 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 523 } 524 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 525 g_free(int_buf); 526 if (ret < 0) { 527 return -1; 528 } 529 return 0; 530 } 531 532 /* 533 * Adds ibm,dynamic-reconfiguration-memory node. 534 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 535 * of this device tree node. 536 */ 537 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 538 void *fdt) 539 { 540 MachineState *machine = MACHINE(spapr); 541 int ret, offset; 542 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 543 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 544 cpu_to_be32(lmb_size & 0xffffffff)}; 545 MemoryDeviceInfoList *dimms = NULL; 546 547 /* 548 * Don't create the node if there is no device memory 549 */ 550 if (machine->ram_size == machine->maxram_size) { 551 return 0; 552 } 553 554 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 555 556 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 557 sizeof(prop_lmb_size)); 558 if (ret < 0) { 559 return ret; 560 } 561 562 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 563 if (ret < 0) { 564 return ret; 565 } 566 567 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 568 if (ret < 0) { 569 return ret; 570 } 571 572 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 573 dimms = qmp_memory_device_list(); 574 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 575 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 576 } else { 577 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 578 } 579 qapi_free_MemoryDeviceInfoList(dimms); 580 581 if (ret < 0) { 582 return ret; 583 } 584 585 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 586 587 return ret; 588 } 589 590 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 591 { 592 MachineState *machine = MACHINE(spapr); 593 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 594 hwaddr mem_start, node_size; 595 int i, nb_nodes = machine->numa_state->num_nodes; 596 NodeInfo *nodes = machine->numa_state->nodes; 597 598 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 599 if (!nodes[i].node_mem) { 600 continue; 601 } 602 if (mem_start >= machine->ram_size) { 603 node_size = 0; 604 } else { 605 node_size = nodes[i].node_mem; 606 if (node_size > machine->ram_size - mem_start) { 607 node_size = machine->ram_size - mem_start; 608 } 609 } 610 if (!mem_start) { 611 /* spapr_machine_init() checks for rma_size <= node0_size 612 * already */ 613 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 614 mem_start += spapr->rma_size; 615 node_size -= spapr->rma_size; 616 } 617 for ( ; node_size; ) { 618 hwaddr sizetmp = pow2floor(node_size); 619 620 /* mem_start != 0 here */ 621 if (ctzl(mem_start) < ctzl(sizetmp)) { 622 sizetmp = 1ULL << ctzl(mem_start); 623 } 624 625 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 626 node_size -= sizetmp; 627 mem_start += sizetmp; 628 } 629 } 630 631 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 632 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 633 int ret; 634 635 g_assert(smc->dr_lmb_enabled); 636 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 637 if (ret) { 638 return ret; 639 } 640 } 641 642 return 0; 643 } 644 645 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 646 SpaprMachineState *spapr) 647 { 648 MachineState *ms = MACHINE(spapr); 649 PowerPCCPU *cpu = POWERPC_CPU(cs); 650 CPUPPCState *env = &cpu->env; 651 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 652 int index = spapr_get_vcpu_id(cpu); 653 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 654 0xffffffff, 0xffffffff}; 655 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 656 : SPAPR_TIMEBASE_FREQ; 657 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 658 uint32_t page_sizes_prop[64]; 659 size_t page_sizes_prop_size; 660 unsigned int smp_threads = ms->smp.threads; 661 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 662 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 663 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 664 SpaprDrc *drc; 665 int drc_index; 666 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 667 int i; 668 669 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 670 if (drc) { 671 drc_index = spapr_drc_index(drc); 672 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 673 } 674 675 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 676 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 677 678 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 679 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 680 env->dcache_line_size))); 681 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 682 env->dcache_line_size))); 683 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 684 env->icache_line_size))); 685 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 686 env->icache_line_size))); 687 688 if (pcc->l1_dcache_size) { 689 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 690 pcc->l1_dcache_size))); 691 } else { 692 warn_report("Unknown L1 dcache size for cpu"); 693 } 694 if (pcc->l1_icache_size) { 695 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 696 pcc->l1_icache_size))); 697 } else { 698 warn_report("Unknown L1 icache size for cpu"); 699 } 700 701 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 702 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 703 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 704 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 705 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 706 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 707 708 if (ppc_has_spr(cpu, SPR_PURR)) { 709 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 710 } 711 if (ppc_has_spr(cpu, SPR_PURR)) { 712 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 713 } 714 715 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 716 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 717 segs, sizeof(segs)))); 718 } 719 720 /* Advertise VSX (vector extensions) if available 721 * 1 == VMX / Altivec available 722 * 2 == VSX available 723 * 724 * Only CPUs for which we create core types in spapr_cpu_core.c 725 * are possible, and all of those have VMX */ 726 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 727 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 728 } else { 729 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 730 } 731 732 /* Advertise DFP (Decimal Floating Point) if available 733 * 0 / no property == no DFP 734 * 1 == DFP available */ 735 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 736 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 737 } 738 739 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 740 sizeof(page_sizes_prop)); 741 if (page_sizes_prop_size) { 742 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 743 page_sizes_prop, page_sizes_prop_size))); 744 } 745 746 spapr_dt_pa_features(spapr, cpu, fdt, offset); 747 748 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 749 cs->cpu_index / vcpus_per_socket))); 750 751 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 752 pft_size_prop, sizeof(pft_size_prop)))); 753 754 if (ms->numa_state->num_nodes > 1) { 755 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 756 } 757 758 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 759 760 if (pcc->radix_page_info) { 761 for (i = 0; i < pcc->radix_page_info->count; i++) { 762 radix_AP_encodings[i] = 763 cpu_to_be32(pcc->radix_page_info->entries[i]); 764 } 765 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 766 radix_AP_encodings, 767 pcc->radix_page_info->count * 768 sizeof(radix_AP_encodings[0])))); 769 } 770 771 /* 772 * We set this property to let the guest know that it can use the large 773 * decrementer and its width in bits. 774 */ 775 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 776 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 777 pcc->lrg_decr_bits))); 778 } 779 780 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 781 { 782 CPUState **rev; 783 CPUState *cs; 784 int n_cpus; 785 int cpus_offset; 786 int i; 787 788 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 789 _FDT(cpus_offset); 790 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 791 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 792 793 /* 794 * We walk the CPUs in reverse order to ensure that CPU DT nodes 795 * created by fdt_add_subnode() end up in the right order in FDT 796 * for the guest kernel the enumerate the CPUs correctly. 797 * 798 * The CPU list cannot be traversed in reverse order, so we need 799 * to do extra work. 800 */ 801 n_cpus = 0; 802 rev = NULL; 803 CPU_FOREACH(cs) { 804 rev = g_renew(CPUState *, rev, n_cpus + 1); 805 rev[n_cpus++] = cs; 806 } 807 808 for (i = n_cpus - 1; i >= 0; i--) { 809 CPUState *cs = rev[i]; 810 PowerPCCPU *cpu = POWERPC_CPU(cs); 811 int index = spapr_get_vcpu_id(cpu); 812 DeviceClass *dc = DEVICE_GET_CLASS(cs); 813 g_autofree char *nodename = NULL; 814 int offset; 815 816 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 817 continue; 818 } 819 820 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 821 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 822 _FDT(offset); 823 spapr_dt_cpu(cs, fdt, offset, spapr); 824 } 825 826 g_free(rev); 827 } 828 829 static int spapr_dt_rng(void *fdt) 830 { 831 int node; 832 int ret; 833 834 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 835 if (node <= 0) { 836 return -1; 837 } 838 ret = fdt_setprop_string(fdt, node, "device_type", 839 "ibm,platform-facilities"); 840 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 841 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 842 843 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 844 if (node <= 0) { 845 return -1; 846 } 847 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 848 849 return ret ? -1 : 0; 850 } 851 852 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 853 { 854 MachineState *ms = MACHINE(spapr); 855 int rtas; 856 GString *hypertas = g_string_sized_new(256); 857 GString *qemu_hypertas = g_string_sized_new(256); 858 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 859 memory_region_size(&MACHINE(spapr)->device_memory->mr); 860 uint32_t lrdr_capacity[] = { 861 cpu_to_be32(max_device_addr >> 32), 862 cpu_to_be32(max_device_addr & 0xffffffff), 863 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 864 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 865 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 866 }; 867 868 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 869 870 /* hypertas */ 871 add_str(hypertas, "hcall-pft"); 872 add_str(hypertas, "hcall-term"); 873 add_str(hypertas, "hcall-dabr"); 874 add_str(hypertas, "hcall-interrupt"); 875 add_str(hypertas, "hcall-tce"); 876 add_str(hypertas, "hcall-vio"); 877 add_str(hypertas, "hcall-splpar"); 878 add_str(hypertas, "hcall-join"); 879 add_str(hypertas, "hcall-bulk"); 880 add_str(hypertas, "hcall-set-mode"); 881 add_str(hypertas, "hcall-sprg0"); 882 add_str(hypertas, "hcall-copy"); 883 add_str(hypertas, "hcall-debug"); 884 add_str(hypertas, "hcall-vphn"); 885 if (spapr_get_cap(spapr, SPAPR_CAP_RPT_INVALIDATE) == SPAPR_CAP_ON) { 886 add_str(hypertas, "hcall-rpt-invalidate"); 887 } 888 889 add_str(qemu_hypertas, "hcall-memop1"); 890 891 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 892 add_str(hypertas, "hcall-multi-tce"); 893 } 894 895 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 896 add_str(hypertas, "hcall-hpt-resize"); 897 } 898 899 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 900 hypertas->str, hypertas->len)); 901 g_string_free(hypertas, TRUE); 902 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 903 qemu_hypertas->str, qemu_hypertas->len)); 904 g_string_free(qemu_hypertas, TRUE); 905 906 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 907 908 /* 909 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 910 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 911 * 912 * The system reset requirements are driven by existing Linux and PowerVM 913 * implementation which (contrary to PAPR) saves r3 in the error log 914 * structure like machine check, so Linux expects to find the saved r3 915 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 916 * does not look at the error value). 917 * 918 * System reset interrupts are not subject to interlock like machine 919 * check, so this memory area could be corrupted if the sreset is 920 * interrupted by a machine check (or vice versa) if it was shared. To 921 * prevent this, system reset uses per-CPU areas for the sreset save 922 * area. A system reset that interrupts a system reset handler could 923 * still overwrite this area, but Linux doesn't try to recover in that 924 * case anyway. 925 * 926 * The extra 8 bytes is required because Linux's FWNMI error log check 927 * is off-by-one. 928 * 929 * RTAS_MIN_SIZE is required for the RTAS blob itself. 930 */ 931 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_MIN_SIZE + 932 RTAS_ERROR_LOG_MAX + 933 ms->smp.max_cpus * sizeof(uint64_t) * 2 + 934 sizeof(uint64_t))); 935 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 936 RTAS_ERROR_LOG_MAX)); 937 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 938 RTAS_EVENT_SCAN_RATE)); 939 940 g_assert(msi_nonbroken); 941 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 942 943 /* 944 * According to PAPR, rtas ibm,os-term does not guarantee a return 945 * back to the guest cpu. 946 * 947 * While an additional ibm,extended-os-term property indicates 948 * that rtas call return will always occur. Set this property. 949 */ 950 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 951 952 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 953 lrdr_capacity, sizeof(lrdr_capacity))); 954 955 spapr_dt_rtas_tokens(fdt, rtas); 956 } 957 958 /* 959 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 960 * and the XIVE features that the guest may request and thus the valid 961 * values for bytes 23..26 of option vector 5: 962 */ 963 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 964 int chosen) 965 { 966 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 967 968 char val[2 * 4] = { 969 23, 0x00, /* XICS / XIVE mode */ 970 24, 0x00, /* Hash/Radix, filled in below. */ 971 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 972 26, 0x40, /* Radix options: GTSE == yes. */ 973 }; 974 975 if (spapr->irq->xics && spapr->irq->xive) { 976 val[1] = SPAPR_OV5_XIVE_BOTH; 977 } else if (spapr->irq->xive) { 978 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 979 } else { 980 assert(spapr->irq->xics); 981 val[1] = SPAPR_OV5_XIVE_LEGACY; 982 } 983 984 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 985 first_ppc_cpu->compat_pvr)) { 986 /* 987 * If we're in a pre POWER9 compat mode then the guest should 988 * do hash and use the legacy interrupt mode 989 */ 990 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 991 val[3] = 0x00; /* Hash */ 992 spapr_check_mmu_mode(false); 993 } else if (kvm_enabled()) { 994 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 995 val[3] = 0x80; /* OV5_MMU_BOTH */ 996 } else if (kvmppc_has_cap_mmu_radix()) { 997 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 998 } else { 999 val[3] = 0x00; /* Hash */ 1000 } 1001 } else { 1002 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1003 val[3] = 0xC0; 1004 } 1005 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1006 val, sizeof(val))); 1007 } 1008 1009 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1010 { 1011 MachineState *machine = MACHINE(spapr); 1012 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1013 int chosen; 1014 1015 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1016 1017 if (reset) { 1018 const char *boot_device = spapr->boot_device; 1019 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1020 size_t cb = 0; 1021 char *bootlist = get_boot_devices_list(&cb); 1022 1023 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1024 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1025 machine->kernel_cmdline)); 1026 } 1027 1028 if (spapr->initrd_size) { 1029 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1030 spapr->initrd_base)); 1031 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1032 spapr->initrd_base + spapr->initrd_size)); 1033 } 1034 1035 if (spapr->kernel_size) { 1036 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1037 cpu_to_be64(spapr->kernel_size) }; 1038 1039 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1040 &kprop, sizeof(kprop))); 1041 if (spapr->kernel_le) { 1042 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1043 } 1044 } 1045 if (boot_menu) { 1046 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1047 } 1048 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1049 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1050 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1051 1052 if (cb && bootlist) { 1053 int i; 1054 1055 for (i = 0; i < cb; i++) { 1056 if (bootlist[i] == '\n') { 1057 bootlist[i] = ' '; 1058 } 1059 } 1060 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1061 } 1062 1063 if (boot_device && strlen(boot_device)) { 1064 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1065 } 1066 1067 if (!spapr->has_graphics && stdout_path) { 1068 /* 1069 * "linux,stdout-path" and "stdout" properties are 1070 * deprecated by linux kernel. New platforms should only 1071 * use the "stdout-path" property. Set the new property 1072 * and continue using older property to remain compatible 1073 * with the existing firmware. 1074 */ 1075 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1076 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1077 } 1078 1079 /* 1080 * We can deal with BAR reallocation just fine, advertise it 1081 * to the guest 1082 */ 1083 if (smc->linux_pci_probe) { 1084 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1085 } 1086 1087 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1088 1089 g_free(stdout_path); 1090 g_free(bootlist); 1091 } 1092 1093 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1094 } 1095 1096 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1097 { 1098 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1099 * KVM to work under pHyp with some guest co-operation */ 1100 int hypervisor; 1101 uint8_t hypercall[16]; 1102 1103 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1104 /* indicate KVM hypercall interface */ 1105 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1106 if (kvmppc_has_cap_fixup_hcalls()) { 1107 /* 1108 * Older KVM versions with older guest kernels were broken 1109 * with the magic page, don't allow the guest to map it. 1110 */ 1111 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1112 sizeof(hypercall))) { 1113 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1114 hypercall, sizeof(hypercall))); 1115 } 1116 } 1117 } 1118 1119 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1120 { 1121 MachineState *machine = MACHINE(spapr); 1122 MachineClass *mc = MACHINE_GET_CLASS(machine); 1123 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1124 uint32_t root_drc_type_mask = 0; 1125 int ret; 1126 void *fdt; 1127 SpaprPhbState *phb; 1128 char *buf; 1129 1130 fdt = g_malloc0(space); 1131 _FDT((fdt_create_empty_tree(fdt, space))); 1132 1133 /* Root node */ 1134 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1135 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1136 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1137 1138 /* Guest UUID & Name*/ 1139 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1140 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1141 if (qemu_uuid_set) { 1142 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1143 } 1144 g_free(buf); 1145 1146 if (qemu_get_vm_name()) { 1147 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1148 qemu_get_vm_name())); 1149 } 1150 1151 /* Host Model & Serial Number */ 1152 if (spapr->host_model) { 1153 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1154 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1155 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1156 g_free(buf); 1157 } 1158 1159 if (spapr->host_serial) { 1160 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1161 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1162 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1163 g_free(buf); 1164 } 1165 1166 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1167 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1168 1169 /* /interrupt controller */ 1170 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1171 1172 ret = spapr_dt_memory(spapr, fdt); 1173 if (ret < 0) { 1174 error_report("couldn't setup memory nodes in fdt"); 1175 exit(1); 1176 } 1177 1178 /* /vdevice */ 1179 spapr_dt_vdevice(spapr->vio_bus, fdt); 1180 1181 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1182 ret = spapr_dt_rng(fdt); 1183 if (ret < 0) { 1184 error_report("could not set up rng device in the fdt"); 1185 exit(1); 1186 } 1187 } 1188 1189 QLIST_FOREACH(phb, &spapr->phbs, list) { 1190 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1191 if (ret < 0) { 1192 error_report("couldn't setup PCI devices in fdt"); 1193 exit(1); 1194 } 1195 } 1196 1197 spapr_dt_cpus(fdt, spapr); 1198 1199 /* ibm,drc-indexes and friends */ 1200 if (smc->dr_lmb_enabled) { 1201 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1202 } 1203 if (smc->dr_phb_enabled) { 1204 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1205 } 1206 if (mc->nvdimm_supported) { 1207 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1208 } 1209 if (root_drc_type_mask) { 1210 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1211 } 1212 1213 if (mc->has_hotpluggable_cpus) { 1214 int offset = fdt_path_offset(fdt, "/cpus"); 1215 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1216 if (ret < 0) { 1217 error_report("Couldn't set up CPU DR device tree properties"); 1218 exit(1); 1219 } 1220 } 1221 1222 /* /event-sources */ 1223 spapr_dt_events(spapr, fdt); 1224 1225 /* /rtas */ 1226 spapr_dt_rtas(spapr, fdt); 1227 1228 /* /chosen */ 1229 spapr_dt_chosen(spapr, fdt, reset); 1230 1231 /* /hypervisor */ 1232 if (kvm_enabled()) { 1233 spapr_dt_hypervisor(spapr, fdt); 1234 } 1235 1236 /* Build memory reserve map */ 1237 if (reset) { 1238 if (spapr->kernel_size) { 1239 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1240 spapr->kernel_size))); 1241 } 1242 if (spapr->initrd_size) { 1243 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1244 spapr->initrd_size))); 1245 } 1246 } 1247 1248 /* NVDIMM devices */ 1249 if (mc->nvdimm_supported) { 1250 spapr_dt_persistent_memory(spapr, fdt); 1251 } 1252 1253 return fdt; 1254 } 1255 1256 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1257 { 1258 SpaprMachineState *spapr = opaque; 1259 1260 return (addr & 0x0fffffff) + spapr->kernel_addr; 1261 } 1262 1263 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1264 PowerPCCPU *cpu) 1265 { 1266 CPUPPCState *env = &cpu->env; 1267 1268 /* The TCG path should also be holding the BQL at this point */ 1269 g_assert(qemu_mutex_iothread_locked()); 1270 1271 if (msr_pr) { 1272 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1273 env->gpr[3] = H_PRIVILEGE; 1274 } else { 1275 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1276 } 1277 } 1278 1279 struct LPCRSyncState { 1280 target_ulong value; 1281 target_ulong mask; 1282 }; 1283 1284 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1285 { 1286 struct LPCRSyncState *s = arg.host_ptr; 1287 PowerPCCPU *cpu = POWERPC_CPU(cs); 1288 CPUPPCState *env = &cpu->env; 1289 target_ulong lpcr; 1290 1291 cpu_synchronize_state(cs); 1292 lpcr = env->spr[SPR_LPCR]; 1293 lpcr &= ~s->mask; 1294 lpcr |= s->value; 1295 ppc_store_lpcr(cpu, lpcr); 1296 } 1297 1298 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1299 { 1300 CPUState *cs; 1301 struct LPCRSyncState s = { 1302 .value = value, 1303 .mask = mask 1304 }; 1305 CPU_FOREACH(cs) { 1306 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1307 } 1308 } 1309 1310 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1311 { 1312 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1313 1314 /* Copy PATE1:GR into PATE0:HR */ 1315 entry->dw0 = spapr->patb_entry & PATE0_HR; 1316 entry->dw1 = spapr->patb_entry; 1317 } 1318 1319 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1320 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1321 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1322 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1323 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1324 1325 /* 1326 * Get the fd to access the kernel htab, re-opening it if necessary 1327 */ 1328 static int get_htab_fd(SpaprMachineState *spapr) 1329 { 1330 Error *local_err = NULL; 1331 1332 if (spapr->htab_fd >= 0) { 1333 return spapr->htab_fd; 1334 } 1335 1336 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1337 if (spapr->htab_fd < 0) { 1338 error_report_err(local_err); 1339 } 1340 1341 return spapr->htab_fd; 1342 } 1343 1344 void close_htab_fd(SpaprMachineState *spapr) 1345 { 1346 if (spapr->htab_fd >= 0) { 1347 close(spapr->htab_fd); 1348 } 1349 spapr->htab_fd = -1; 1350 } 1351 1352 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1353 { 1354 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1355 1356 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1357 } 1358 1359 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1360 { 1361 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1362 1363 assert(kvm_enabled()); 1364 1365 if (!spapr->htab) { 1366 return 0; 1367 } 1368 1369 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1370 } 1371 1372 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1373 hwaddr ptex, int n) 1374 { 1375 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1376 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1377 1378 if (!spapr->htab) { 1379 /* 1380 * HTAB is controlled by KVM. Fetch into temporary buffer 1381 */ 1382 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1383 kvmppc_read_hptes(hptes, ptex, n); 1384 return hptes; 1385 } 1386 1387 /* 1388 * HTAB is controlled by QEMU. Just point to the internally 1389 * accessible PTEG. 1390 */ 1391 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1392 } 1393 1394 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1395 const ppc_hash_pte64_t *hptes, 1396 hwaddr ptex, int n) 1397 { 1398 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1399 1400 if (!spapr->htab) { 1401 g_free((void *)hptes); 1402 } 1403 1404 /* Nothing to do for qemu managed HPT */ 1405 } 1406 1407 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1408 uint64_t pte0, uint64_t pte1) 1409 { 1410 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1411 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1412 1413 if (!spapr->htab) { 1414 kvmppc_write_hpte(ptex, pte0, pte1); 1415 } else { 1416 if (pte0 & HPTE64_V_VALID) { 1417 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1418 /* 1419 * When setting valid, we write PTE1 first. This ensures 1420 * proper synchronization with the reading code in 1421 * ppc_hash64_pteg_search() 1422 */ 1423 smp_wmb(); 1424 stq_p(spapr->htab + offset, pte0); 1425 } else { 1426 stq_p(spapr->htab + offset, pte0); 1427 /* 1428 * When clearing it we set PTE0 first. This ensures proper 1429 * synchronization with the reading code in 1430 * ppc_hash64_pteg_search() 1431 */ 1432 smp_wmb(); 1433 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1434 } 1435 } 1436 } 1437 1438 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1439 uint64_t pte1) 1440 { 1441 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1442 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1443 1444 if (!spapr->htab) { 1445 /* There should always be a hash table when this is called */ 1446 error_report("spapr_hpte_set_c called with no hash table !"); 1447 return; 1448 } 1449 1450 /* The HW performs a non-atomic byte update */ 1451 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1452 } 1453 1454 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1455 uint64_t pte1) 1456 { 1457 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1458 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1459 1460 if (!spapr->htab) { 1461 /* There should always be a hash table when this is called */ 1462 error_report("spapr_hpte_set_r called with no hash table !"); 1463 return; 1464 } 1465 1466 /* The HW performs a non-atomic byte update */ 1467 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1468 } 1469 1470 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1471 { 1472 int shift; 1473 1474 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1475 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1476 * that's much more than is needed for Linux guests */ 1477 shift = ctz64(pow2ceil(ramsize)) - 7; 1478 shift = MAX(shift, 18); /* Minimum architected size */ 1479 shift = MIN(shift, 46); /* Maximum architected size */ 1480 return shift; 1481 } 1482 1483 void spapr_free_hpt(SpaprMachineState *spapr) 1484 { 1485 g_free(spapr->htab); 1486 spapr->htab = NULL; 1487 spapr->htab_shift = 0; 1488 close_htab_fd(spapr); 1489 } 1490 1491 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1492 { 1493 ERRP_GUARD(); 1494 long rc; 1495 1496 /* Clean up any HPT info from a previous boot */ 1497 spapr_free_hpt(spapr); 1498 1499 rc = kvmppc_reset_htab(shift); 1500 1501 if (rc == -EOPNOTSUPP) { 1502 error_setg(errp, "HPT not supported in nested guests"); 1503 return -EOPNOTSUPP; 1504 } 1505 1506 if (rc < 0) { 1507 /* kernel-side HPT needed, but couldn't allocate one */ 1508 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1509 shift); 1510 error_append_hint(errp, "Try smaller maxmem?\n"); 1511 return -errno; 1512 } else if (rc > 0) { 1513 /* kernel-side HPT allocated */ 1514 if (rc != shift) { 1515 error_setg(errp, 1516 "Requested order %d HPT, but kernel allocated order %ld", 1517 shift, rc); 1518 error_append_hint(errp, "Try smaller maxmem?\n"); 1519 return -ENOSPC; 1520 } 1521 1522 spapr->htab_shift = shift; 1523 spapr->htab = NULL; 1524 } else { 1525 /* kernel-side HPT not needed, allocate in userspace instead */ 1526 size_t size = 1ULL << shift; 1527 int i; 1528 1529 spapr->htab = qemu_memalign(size, size); 1530 memset(spapr->htab, 0, size); 1531 spapr->htab_shift = shift; 1532 1533 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1534 DIRTY_HPTE(HPTE(spapr->htab, i)); 1535 } 1536 } 1537 /* We're setting up a hash table, so that means we're not radix */ 1538 spapr->patb_entry = 0; 1539 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1540 return 0; 1541 } 1542 1543 void spapr_setup_hpt(SpaprMachineState *spapr) 1544 { 1545 int hpt_shift; 1546 1547 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1548 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1549 } else { 1550 uint64_t current_ram_size; 1551 1552 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1553 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1554 } 1555 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1556 1557 if (kvm_enabled()) { 1558 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1559 1560 /* Check our RMA fits in the possible VRMA */ 1561 if (vrma_limit < spapr->rma_size) { 1562 error_report("Unable to create %" HWADDR_PRIu 1563 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1564 spapr->rma_size / MiB, vrma_limit / MiB); 1565 exit(EXIT_FAILURE); 1566 } 1567 } 1568 } 1569 1570 void spapr_check_mmu_mode(bool guest_radix) 1571 { 1572 if (guest_radix) { 1573 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1574 error_report("Guest requested unavailable MMU mode (radix)."); 1575 exit(EXIT_FAILURE); 1576 } 1577 } else { 1578 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1579 && !kvmppc_has_cap_mmu_hash_v3()) { 1580 error_report("Guest requested unavailable MMU mode (hash)."); 1581 exit(EXIT_FAILURE); 1582 } 1583 } 1584 } 1585 1586 static void spapr_machine_reset(MachineState *machine) 1587 { 1588 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1589 PowerPCCPU *first_ppc_cpu; 1590 hwaddr fdt_addr; 1591 void *fdt; 1592 int rc; 1593 1594 pef_kvm_reset(machine->cgs, &error_fatal); 1595 spapr_caps_apply(spapr); 1596 1597 first_ppc_cpu = POWERPC_CPU(first_cpu); 1598 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1599 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1600 spapr->max_compat_pvr)) { 1601 /* 1602 * If using KVM with radix mode available, VCPUs can be started 1603 * without a HPT because KVM will start them in radix mode. 1604 * Set the GR bit in PATE so that we know there is no HPT. 1605 */ 1606 spapr->patb_entry = PATE1_GR; 1607 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1608 } else { 1609 spapr_setup_hpt(spapr); 1610 } 1611 1612 qemu_devices_reset(); 1613 1614 spapr_ovec_cleanup(spapr->ov5_cas); 1615 spapr->ov5_cas = spapr_ovec_new(); 1616 1617 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1618 1619 /* 1620 * This is fixing some of the default configuration of the XIVE 1621 * devices. To be called after the reset of the machine devices. 1622 */ 1623 spapr_irq_reset(spapr, &error_fatal); 1624 1625 /* 1626 * There is no CAS under qtest. Simulate one to please the code that 1627 * depends on spapr->ov5_cas. This is especially needed to test device 1628 * unplug, so we do that before resetting the DRCs. 1629 */ 1630 if (qtest_enabled()) { 1631 spapr_ovec_cleanup(spapr->ov5_cas); 1632 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1633 } 1634 1635 /* DRC reset may cause a device to be unplugged. This will cause troubles 1636 * if this device is used by another device (eg, a running vhost backend 1637 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1638 * situations, we reset DRCs after all devices have been reset. 1639 */ 1640 spapr_drc_reset_all(spapr); 1641 1642 spapr_clear_pending_events(spapr); 1643 1644 /* 1645 * We place the device tree just below either the top of the RMA, 1646 * or just below 2GB, whichever is lower, so that it can be 1647 * processed with 32-bit real mode code if necessary 1648 */ 1649 fdt_addr = MIN(spapr->rma_size, FDT_MAX_ADDR) - FDT_MAX_SIZE; 1650 1651 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1652 if (spapr->vof) { 1653 spapr_vof_reset(spapr, fdt, &error_fatal); 1654 /* 1655 * Do not pack the FDT as the client may change properties. 1656 * VOF client does not expect the FDT so we do not load it to the VM. 1657 */ 1658 } else { 1659 rc = fdt_pack(fdt); 1660 /* Should only fail if we've built a corrupted tree */ 1661 assert(rc == 0); 1662 1663 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 1664 0, fdt_addr, 0); 1665 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1666 } 1667 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1668 1669 g_free(spapr->fdt_blob); 1670 spapr->fdt_size = fdt_totalsize(fdt); 1671 spapr->fdt_initial_size = spapr->fdt_size; 1672 spapr->fdt_blob = fdt; 1673 1674 /* Set up the entry state */ 1675 first_ppc_cpu->env.gpr[5] = 0; 1676 1677 spapr->fwnmi_system_reset_addr = -1; 1678 spapr->fwnmi_machine_check_addr = -1; 1679 spapr->fwnmi_machine_check_interlock = -1; 1680 1681 /* Signal all vCPUs waiting on this condition */ 1682 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1683 1684 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1685 } 1686 1687 static void spapr_create_nvram(SpaprMachineState *spapr) 1688 { 1689 DeviceState *dev = qdev_new("spapr-nvram"); 1690 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1691 1692 if (dinfo) { 1693 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1694 &error_fatal); 1695 } 1696 1697 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1698 1699 spapr->nvram = (struct SpaprNvram *)dev; 1700 } 1701 1702 static void spapr_rtc_create(SpaprMachineState *spapr) 1703 { 1704 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1705 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1706 &error_fatal, NULL); 1707 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1708 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1709 "date"); 1710 } 1711 1712 /* Returns whether we want to use VGA or not */ 1713 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1714 { 1715 switch (vga_interface_type) { 1716 case VGA_NONE: 1717 return false; 1718 case VGA_DEVICE: 1719 return true; 1720 case VGA_STD: 1721 case VGA_VIRTIO: 1722 case VGA_CIRRUS: 1723 return pci_vga_init(pci_bus) != NULL; 1724 default: 1725 error_setg(errp, 1726 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1727 return false; 1728 } 1729 } 1730 1731 static int spapr_pre_load(void *opaque) 1732 { 1733 int rc; 1734 1735 rc = spapr_caps_pre_load(opaque); 1736 if (rc) { 1737 return rc; 1738 } 1739 1740 return 0; 1741 } 1742 1743 static int spapr_post_load(void *opaque, int version_id) 1744 { 1745 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1746 int err = 0; 1747 1748 err = spapr_caps_post_migration(spapr); 1749 if (err) { 1750 return err; 1751 } 1752 1753 /* 1754 * In earlier versions, there was no separate qdev for the PAPR 1755 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1756 * So when migrating from those versions, poke the incoming offset 1757 * value into the RTC device 1758 */ 1759 if (version_id < 3) { 1760 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1761 if (err) { 1762 return err; 1763 } 1764 } 1765 1766 if (kvm_enabled() && spapr->patb_entry) { 1767 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1768 bool radix = !!(spapr->patb_entry & PATE1_GR); 1769 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1770 1771 /* 1772 * Update LPCR:HR and UPRT as they may not be set properly in 1773 * the stream 1774 */ 1775 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1776 LPCR_HR | LPCR_UPRT); 1777 1778 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1779 if (err) { 1780 error_report("Process table config unsupported by the host"); 1781 return -EINVAL; 1782 } 1783 } 1784 1785 err = spapr_irq_post_load(spapr, version_id); 1786 if (err) { 1787 return err; 1788 } 1789 1790 return err; 1791 } 1792 1793 static int spapr_pre_save(void *opaque) 1794 { 1795 int rc; 1796 1797 rc = spapr_caps_pre_save(opaque); 1798 if (rc) { 1799 return rc; 1800 } 1801 1802 return 0; 1803 } 1804 1805 static bool version_before_3(void *opaque, int version_id) 1806 { 1807 return version_id < 3; 1808 } 1809 1810 static bool spapr_pending_events_needed(void *opaque) 1811 { 1812 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1813 return !QTAILQ_EMPTY(&spapr->pending_events); 1814 } 1815 1816 static const VMStateDescription vmstate_spapr_event_entry = { 1817 .name = "spapr_event_log_entry", 1818 .version_id = 1, 1819 .minimum_version_id = 1, 1820 .fields = (VMStateField[]) { 1821 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1822 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1823 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1824 NULL, extended_length), 1825 VMSTATE_END_OF_LIST() 1826 }, 1827 }; 1828 1829 static const VMStateDescription vmstate_spapr_pending_events = { 1830 .name = "spapr_pending_events", 1831 .version_id = 1, 1832 .minimum_version_id = 1, 1833 .needed = spapr_pending_events_needed, 1834 .fields = (VMStateField[]) { 1835 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1836 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1837 VMSTATE_END_OF_LIST() 1838 }, 1839 }; 1840 1841 static bool spapr_ov5_cas_needed(void *opaque) 1842 { 1843 SpaprMachineState *spapr = opaque; 1844 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1845 bool cas_needed; 1846 1847 /* Prior to the introduction of SpaprOptionVector, we had two option 1848 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1849 * Both of these options encode machine topology into the device-tree 1850 * in such a way that the now-booted OS should still be able to interact 1851 * appropriately with QEMU regardless of what options were actually 1852 * negotiatied on the source side. 1853 * 1854 * As such, we can avoid migrating the CAS-negotiated options if these 1855 * are the only options available on the current machine/platform. 1856 * Since these are the only options available for pseries-2.7 and 1857 * earlier, this allows us to maintain old->new/new->old migration 1858 * compatibility. 1859 * 1860 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1861 * via default pseries-2.8 machines and explicit command-line parameters. 1862 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1863 * of the actual CAS-negotiated values to continue working properly. For 1864 * example, availability of memory unplug depends on knowing whether 1865 * OV5_HP_EVT was negotiated via CAS. 1866 * 1867 * Thus, for any cases where the set of available CAS-negotiatable 1868 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1869 * include the CAS-negotiated options in the migration stream, unless 1870 * if they affect boot time behaviour only. 1871 */ 1872 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1873 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1874 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1875 1876 /* We need extra information if we have any bits outside the mask 1877 * defined above */ 1878 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1879 1880 spapr_ovec_cleanup(ov5_mask); 1881 1882 return cas_needed; 1883 } 1884 1885 static const VMStateDescription vmstate_spapr_ov5_cas = { 1886 .name = "spapr_option_vector_ov5_cas", 1887 .version_id = 1, 1888 .minimum_version_id = 1, 1889 .needed = spapr_ov5_cas_needed, 1890 .fields = (VMStateField[]) { 1891 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1892 vmstate_spapr_ovec, SpaprOptionVector), 1893 VMSTATE_END_OF_LIST() 1894 }, 1895 }; 1896 1897 static bool spapr_patb_entry_needed(void *opaque) 1898 { 1899 SpaprMachineState *spapr = opaque; 1900 1901 return !!spapr->patb_entry; 1902 } 1903 1904 static const VMStateDescription vmstate_spapr_patb_entry = { 1905 .name = "spapr_patb_entry", 1906 .version_id = 1, 1907 .minimum_version_id = 1, 1908 .needed = spapr_patb_entry_needed, 1909 .fields = (VMStateField[]) { 1910 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1911 VMSTATE_END_OF_LIST() 1912 }, 1913 }; 1914 1915 static bool spapr_irq_map_needed(void *opaque) 1916 { 1917 SpaprMachineState *spapr = opaque; 1918 1919 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1920 } 1921 1922 static const VMStateDescription vmstate_spapr_irq_map = { 1923 .name = "spapr_irq_map", 1924 .version_id = 1, 1925 .minimum_version_id = 1, 1926 .needed = spapr_irq_map_needed, 1927 .fields = (VMStateField[]) { 1928 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1929 VMSTATE_END_OF_LIST() 1930 }, 1931 }; 1932 1933 static bool spapr_dtb_needed(void *opaque) 1934 { 1935 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1936 1937 return smc->update_dt_enabled; 1938 } 1939 1940 static int spapr_dtb_pre_load(void *opaque) 1941 { 1942 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1943 1944 g_free(spapr->fdt_blob); 1945 spapr->fdt_blob = NULL; 1946 spapr->fdt_size = 0; 1947 1948 return 0; 1949 } 1950 1951 static const VMStateDescription vmstate_spapr_dtb = { 1952 .name = "spapr_dtb", 1953 .version_id = 1, 1954 .minimum_version_id = 1, 1955 .needed = spapr_dtb_needed, 1956 .pre_load = spapr_dtb_pre_load, 1957 .fields = (VMStateField[]) { 1958 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1959 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1960 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1961 fdt_size), 1962 VMSTATE_END_OF_LIST() 1963 }, 1964 }; 1965 1966 static bool spapr_fwnmi_needed(void *opaque) 1967 { 1968 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1969 1970 return spapr->fwnmi_machine_check_addr != -1; 1971 } 1972 1973 static int spapr_fwnmi_pre_save(void *opaque) 1974 { 1975 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1976 1977 /* 1978 * Check if machine check handling is in progress and print a 1979 * warning message. 1980 */ 1981 if (spapr->fwnmi_machine_check_interlock != -1) { 1982 warn_report("A machine check is being handled during migration. The" 1983 "handler may run and log hardware error on the destination"); 1984 } 1985 1986 return 0; 1987 } 1988 1989 static const VMStateDescription vmstate_spapr_fwnmi = { 1990 .name = "spapr_fwnmi", 1991 .version_id = 1, 1992 .minimum_version_id = 1, 1993 .needed = spapr_fwnmi_needed, 1994 .pre_save = spapr_fwnmi_pre_save, 1995 .fields = (VMStateField[]) { 1996 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 1997 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 1998 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 1999 VMSTATE_END_OF_LIST() 2000 }, 2001 }; 2002 2003 static const VMStateDescription vmstate_spapr = { 2004 .name = "spapr", 2005 .version_id = 3, 2006 .minimum_version_id = 1, 2007 .pre_load = spapr_pre_load, 2008 .post_load = spapr_post_load, 2009 .pre_save = spapr_pre_save, 2010 .fields = (VMStateField[]) { 2011 /* used to be @next_irq */ 2012 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2013 2014 /* RTC offset */ 2015 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2016 2017 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2018 VMSTATE_END_OF_LIST() 2019 }, 2020 .subsections = (const VMStateDescription*[]) { 2021 &vmstate_spapr_ov5_cas, 2022 &vmstate_spapr_patb_entry, 2023 &vmstate_spapr_pending_events, 2024 &vmstate_spapr_cap_htm, 2025 &vmstate_spapr_cap_vsx, 2026 &vmstate_spapr_cap_dfp, 2027 &vmstate_spapr_cap_cfpc, 2028 &vmstate_spapr_cap_sbbc, 2029 &vmstate_spapr_cap_ibs, 2030 &vmstate_spapr_cap_hpt_maxpagesize, 2031 &vmstate_spapr_irq_map, 2032 &vmstate_spapr_cap_nested_kvm_hv, 2033 &vmstate_spapr_dtb, 2034 &vmstate_spapr_cap_large_decr, 2035 &vmstate_spapr_cap_ccf_assist, 2036 &vmstate_spapr_cap_fwnmi, 2037 &vmstate_spapr_fwnmi, 2038 &vmstate_spapr_cap_rpt_invalidate, 2039 NULL 2040 } 2041 }; 2042 2043 static int htab_save_setup(QEMUFile *f, void *opaque) 2044 { 2045 SpaprMachineState *spapr = opaque; 2046 2047 /* "Iteration" header */ 2048 if (!spapr->htab_shift) { 2049 qemu_put_be32(f, -1); 2050 } else { 2051 qemu_put_be32(f, spapr->htab_shift); 2052 } 2053 2054 if (spapr->htab) { 2055 spapr->htab_save_index = 0; 2056 spapr->htab_first_pass = true; 2057 } else { 2058 if (spapr->htab_shift) { 2059 assert(kvm_enabled()); 2060 } 2061 } 2062 2063 2064 return 0; 2065 } 2066 2067 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2068 int chunkstart, int n_valid, int n_invalid) 2069 { 2070 qemu_put_be32(f, chunkstart); 2071 qemu_put_be16(f, n_valid); 2072 qemu_put_be16(f, n_invalid); 2073 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2074 HASH_PTE_SIZE_64 * n_valid); 2075 } 2076 2077 static void htab_save_end_marker(QEMUFile *f) 2078 { 2079 qemu_put_be32(f, 0); 2080 qemu_put_be16(f, 0); 2081 qemu_put_be16(f, 0); 2082 } 2083 2084 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2085 int64_t max_ns) 2086 { 2087 bool has_timeout = max_ns != -1; 2088 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2089 int index = spapr->htab_save_index; 2090 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2091 2092 assert(spapr->htab_first_pass); 2093 2094 do { 2095 int chunkstart; 2096 2097 /* Consume invalid HPTEs */ 2098 while ((index < htabslots) 2099 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2100 CLEAN_HPTE(HPTE(spapr->htab, index)); 2101 index++; 2102 } 2103 2104 /* Consume valid HPTEs */ 2105 chunkstart = index; 2106 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2107 && HPTE_VALID(HPTE(spapr->htab, index))) { 2108 CLEAN_HPTE(HPTE(spapr->htab, index)); 2109 index++; 2110 } 2111 2112 if (index > chunkstart) { 2113 int n_valid = index - chunkstart; 2114 2115 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2116 2117 if (has_timeout && 2118 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2119 break; 2120 } 2121 } 2122 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2123 2124 if (index >= htabslots) { 2125 assert(index == htabslots); 2126 index = 0; 2127 spapr->htab_first_pass = false; 2128 } 2129 spapr->htab_save_index = index; 2130 } 2131 2132 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2133 int64_t max_ns) 2134 { 2135 bool final = max_ns < 0; 2136 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2137 int examined = 0, sent = 0; 2138 int index = spapr->htab_save_index; 2139 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2140 2141 assert(!spapr->htab_first_pass); 2142 2143 do { 2144 int chunkstart, invalidstart; 2145 2146 /* Consume non-dirty HPTEs */ 2147 while ((index < htabslots) 2148 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2149 index++; 2150 examined++; 2151 } 2152 2153 chunkstart = index; 2154 /* Consume valid dirty HPTEs */ 2155 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2156 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2157 && HPTE_VALID(HPTE(spapr->htab, index))) { 2158 CLEAN_HPTE(HPTE(spapr->htab, index)); 2159 index++; 2160 examined++; 2161 } 2162 2163 invalidstart = index; 2164 /* Consume invalid dirty HPTEs */ 2165 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2166 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2167 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2168 CLEAN_HPTE(HPTE(spapr->htab, index)); 2169 index++; 2170 examined++; 2171 } 2172 2173 if (index > chunkstart) { 2174 int n_valid = invalidstart - chunkstart; 2175 int n_invalid = index - invalidstart; 2176 2177 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2178 sent += index - chunkstart; 2179 2180 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2181 break; 2182 } 2183 } 2184 2185 if (examined >= htabslots) { 2186 break; 2187 } 2188 2189 if (index >= htabslots) { 2190 assert(index == htabslots); 2191 index = 0; 2192 } 2193 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2194 2195 if (index >= htabslots) { 2196 assert(index == htabslots); 2197 index = 0; 2198 } 2199 2200 spapr->htab_save_index = index; 2201 2202 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2203 } 2204 2205 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2206 #define MAX_KVM_BUF_SIZE 2048 2207 2208 static int htab_save_iterate(QEMUFile *f, void *opaque) 2209 { 2210 SpaprMachineState *spapr = opaque; 2211 int fd; 2212 int rc = 0; 2213 2214 /* Iteration header */ 2215 if (!spapr->htab_shift) { 2216 qemu_put_be32(f, -1); 2217 return 1; 2218 } else { 2219 qemu_put_be32(f, 0); 2220 } 2221 2222 if (!spapr->htab) { 2223 assert(kvm_enabled()); 2224 2225 fd = get_htab_fd(spapr); 2226 if (fd < 0) { 2227 return fd; 2228 } 2229 2230 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2231 if (rc < 0) { 2232 return rc; 2233 } 2234 } else if (spapr->htab_first_pass) { 2235 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2236 } else { 2237 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2238 } 2239 2240 htab_save_end_marker(f); 2241 2242 return rc; 2243 } 2244 2245 static int htab_save_complete(QEMUFile *f, void *opaque) 2246 { 2247 SpaprMachineState *spapr = opaque; 2248 int fd; 2249 2250 /* Iteration header */ 2251 if (!spapr->htab_shift) { 2252 qemu_put_be32(f, -1); 2253 return 0; 2254 } else { 2255 qemu_put_be32(f, 0); 2256 } 2257 2258 if (!spapr->htab) { 2259 int rc; 2260 2261 assert(kvm_enabled()); 2262 2263 fd = get_htab_fd(spapr); 2264 if (fd < 0) { 2265 return fd; 2266 } 2267 2268 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2269 if (rc < 0) { 2270 return rc; 2271 } 2272 } else { 2273 if (spapr->htab_first_pass) { 2274 htab_save_first_pass(f, spapr, -1); 2275 } 2276 htab_save_later_pass(f, spapr, -1); 2277 } 2278 2279 /* End marker */ 2280 htab_save_end_marker(f); 2281 2282 return 0; 2283 } 2284 2285 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2286 { 2287 SpaprMachineState *spapr = opaque; 2288 uint32_t section_hdr; 2289 int fd = -1; 2290 Error *local_err = NULL; 2291 2292 if (version_id < 1 || version_id > 1) { 2293 error_report("htab_load() bad version"); 2294 return -EINVAL; 2295 } 2296 2297 section_hdr = qemu_get_be32(f); 2298 2299 if (section_hdr == -1) { 2300 spapr_free_hpt(spapr); 2301 return 0; 2302 } 2303 2304 if (section_hdr) { 2305 int ret; 2306 2307 /* First section gives the htab size */ 2308 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2309 if (ret < 0) { 2310 error_report_err(local_err); 2311 return ret; 2312 } 2313 return 0; 2314 } 2315 2316 if (!spapr->htab) { 2317 assert(kvm_enabled()); 2318 2319 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2320 if (fd < 0) { 2321 error_report_err(local_err); 2322 return fd; 2323 } 2324 } 2325 2326 while (true) { 2327 uint32_t index; 2328 uint16_t n_valid, n_invalid; 2329 2330 index = qemu_get_be32(f); 2331 n_valid = qemu_get_be16(f); 2332 n_invalid = qemu_get_be16(f); 2333 2334 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2335 /* End of Stream */ 2336 break; 2337 } 2338 2339 if ((index + n_valid + n_invalid) > 2340 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2341 /* Bad index in stream */ 2342 error_report( 2343 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2344 index, n_valid, n_invalid, spapr->htab_shift); 2345 return -EINVAL; 2346 } 2347 2348 if (spapr->htab) { 2349 if (n_valid) { 2350 qemu_get_buffer(f, HPTE(spapr->htab, index), 2351 HASH_PTE_SIZE_64 * n_valid); 2352 } 2353 if (n_invalid) { 2354 memset(HPTE(spapr->htab, index + n_valid), 0, 2355 HASH_PTE_SIZE_64 * n_invalid); 2356 } 2357 } else { 2358 int rc; 2359 2360 assert(fd >= 0); 2361 2362 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2363 &local_err); 2364 if (rc < 0) { 2365 error_report_err(local_err); 2366 return rc; 2367 } 2368 } 2369 } 2370 2371 if (!spapr->htab) { 2372 assert(fd >= 0); 2373 close(fd); 2374 } 2375 2376 return 0; 2377 } 2378 2379 static void htab_save_cleanup(void *opaque) 2380 { 2381 SpaprMachineState *spapr = opaque; 2382 2383 close_htab_fd(spapr); 2384 } 2385 2386 static SaveVMHandlers savevm_htab_handlers = { 2387 .save_setup = htab_save_setup, 2388 .save_live_iterate = htab_save_iterate, 2389 .save_live_complete_precopy = htab_save_complete, 2390 .save_cleanup = htab_save_cleanup, 2391 .load_state = htab_load, 2392 }; 2393 2394 static void spapr_boot_set(void *opaque, const char *boot_device, 2395 Error **errp) 2396 { 2397 SpaprMachineState *spapr = SPAPR_MACHINE(opaque); 2398 2399 g_free(spapr->boot_device); 2400 spapr->boot_device = g_strdup(boot_device); 2401 } 2402 2403 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2404 { 2405 MachineState *machine = MACHINE(spapr); 2406 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2407 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2408 int i; 2409 2410 for (i = 0; i < nr_lmbs; i++) { 2411 uint64_t addr; 2412 2413 addr = i * lmb_size + machine->device_memory->base; 2414 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2415 addr / lmb_size); 2416 } 2417 } 2418 2419 /* 2420 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2421 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2422 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2423 */ 2424 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2425 { 2426 int i; 2427 2428 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2429 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2430 " is not aligned to %" PRIu64 " MiB", 2431 machine->ram_size, 2432 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2433 return; 2434 } 2435 2436 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2437 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2438 " is not aligned to %" PRIu64 " MiB", 2439 machine->ram_size, 2440 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2441 return; 2442 } 2443 2444 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2445 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2446 error_setg(errp, 2447 "Node %d memory size 0x%" PRIx64 2448 " is not aligned to %" PRIu64 " MiB", 2449 i, machine->numa_state->nodes[i].node_mem, 2450 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2451 return; 2452 } 2453 } 2454 } 2455 2456 /* find cpu slot in machine->possible_cpus by core_id */ 2457 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2458 { 2459 int index = id / ms->smp.threads; 2460 2461 if (index >= ms->possible_cpus->len) { 2462 return NULL; 2463 } 2464 if (idx) { 2465 *idx = index; 2466 } 2467 return &ms->possible_cpus->cpus[index]; 2468 } 2469 2470 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2471 { 2472 MachineState *ms = MACHINE(spapr); 2473 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2474 Error *local_err = NULL; 2475 bool vsmt_user = !!spapr->vsmt; 2476 int kvm_smt = kvmppc_smt_threads(); 2477 int ret; 2478 unsigned int smp_threads = ms->smp.threads; 2479 2480 if (!kvm_enabled() && (smp_threads > 1)) { 2481 error_setg(errp, "TCG cannot support more than 1 thread/core " 2482 "on a pseries machine"); 2483 return; 2484 } 2485 if (!is_power_of_2(smp_threads)) { 2486 error_setg(errp, "Cannot support %d threads/core on a pseries " 2487 "machine because it must be a power of 2", smp_threads); 2488 return; 2489 } 2490 2491 /* Detemine the VSMT mode to use: */ 2492 if (vsmt_user) { 2493 if (spapr->vsmt < smp_threads) { 2494 error_setg(errp, "Cannot support VSMT mode %d" 2495 " because it must be >= threads/core (%d)", 2496 spapr->vsmt, smp_threads); 2497 return; 2498 } 2499 /* In this case, spapr->vsmt has been set by the command line */ 2500 } else if (!smc->smp_threads_vsmt) { 2501 /* 2502 * Default VSMT value is tricky, because we need it to be as 2503 * consistent as possible (for migration), but this requires 2504 * changing it for at least some existing cases. We pick 8 as 2505 * the value that we'd get with KVM on POWER8, the 2506 * overwhelmingly common case in production systems. 2507 */ 2508 spapr->vsmt = MAX(8, smp_threads); 2509 } else { 2510 spapr->vsmt = smp_threads; 2511 } 2512 2513 /* KVM: If necessary, set the SMT mode: */ 2514 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2515 ret = kvmppc_set_smt_threads(spapr->vsmt); 2516 if (ret) { 2517 /* Looks like KVM isn't able to change VSMT mode */ 2518 error_setg(&local_err, 2519 "Failed to set KVM's VSMT mode to %d (errno %d)", 2520 spapr->vsmt, ret); 2521 /* We can live with that if the default one is big enough 2522 * for the number of threads, and a submultiple of the one 2523 * we want. In this case we'll waste some vcpu ids, but 2524 * behaviour will be correct */ 2525 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2526 warn_report_err(local_err); 2527 } else { 2528 if (!vsmt_user) { 2529 error_append_hint(&local_err, 2530 "On PPC, a VM with %d threads/core" 2531 " on a host with %d threads/core" 2532 " requires the use of VSMT mode %d.\n", 2533 smp_threads, kvm_smt, spapr->vsmt); 2534 } 2535 kvmppc_error_append_smt_possible_hint(&local_err); 2536 error_propagate(errp, local_err); 2537 } 2538 } 2539 } 2540 /* else TCG: nothing to do currently */ 2541 } 2542 2543 static void spapr_init_cpus(SpaprMachineState *spapr) 2544 { 2545 MachineState *machine = MACHINE(spapr); 2546 MachineClass *mc = MACHINE_GET_CLASS(machine); 2547 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2548 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2549 const CPUArchIdList *possible_cpus; 2550 unsigned int smp_cpus = machine->smp.cpus; 2551 unsigned int smp_threads = machine->smp.threads; 2552 unsigned int max_cpus = machine->smp.max_cpus; 2553 int boot_cores_nr = smp_cpus / smp_threads; 2554 int i; 2555 2556 possible_cpus = mc->possible_cpu_arch_ids(machine); 2557 if (mc->has_hotpluggable_cpus) { 2558 if (smp_cpus % smp_threads) { 2559 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2560 smp_cpus, smp_threads); 2561 exit(1); 2562 } 2563 if (max_cpus % smp_threads) { 2564 error_report("max_cpus (%u) must be multiple of threads (%u)", 2565 max_cpus, smp_threads); 2566 exit(1); 2567 } 2568 } else { 2569 if (max_cpus != smp_cpus) { 2570 error_report("This machine version does not support CPU hotplug"); 2571 exit(1); 2572 } 2573 boot_cores_nr = possible_cpus->len; 2574 } 2575 2576 if (smc->pre_2_10_has_unused_icps) { 2577 int i; 2578 2579 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2580 /* Dummy entries get deregistered when real ICPState objects 2581 * are registered during CPU core hotplug. 2582 */ 2583 pre_2_10_vmstate_register_dummy_icp(i); 2584 } 2585 } 2586 2587 for (i = 0; i < possible_cpus->len; i++) { 2588 int core_id = i * smp_threads; 2589 2590 if (mc->has_hotpluggable_cpus) { 2591 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2592 spapr_vcpu_id(spapr, core_id)); 2593 } 2594 2595 if (i < boot_cores_nr) { 2596 Object *core = object_new(type); 2597 int nr_threads = smp_threads; 2598 2599 /* Handle the partially filled core for older machine types */ 2600 if ((i + 1) * smp_threads >= smp_cpus) { 2601 nr_threads = smp_cpus - i * smp_threads; 2602 } 2603 2604 object_property_set_int(core, "nr-threads", nr_threads, 2605 &error_fatal); 2606 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2607 &error_fatal); 2608 qdev_realize(DEVICE(core), NULL, &error_fatal); 2609 2610 object_unref(core); 2611 } 2612 } 2613 } 2614 2615 static PCIHostState *spapr_create_default_phb(void) 2616 { 2617 DeviceState *dev; 2618 2619 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2620 qdev_prop_set_uint32(dev, "index", 0); 2621 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2622 2623 return PCI_HOST_BRIDGE(dev); 2624 } 2625 2626 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2627 { 2628 MachineState *machine = MACHINE(spapr); 2629 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2630 hwaddr rma_size = machine->ram_size; 2631 hwaddr node0_size = spapr_node0_size(machine); 2632 2633 /* RMA has to fit in the first NUMA node */ 2634 rma_size = MIN(rma_size, node0_size); 2635 2636 /* 2637 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2638 * never exceed that 2639 */ 2640 rma_size = MIN(rma_size, 1 * TiB); 2641 2642 /* 2643 * Clamp the RMA size based on machine type. This is for 2644 * migration compatibility with older qemu versions, which limited 2645 * the RMA size for complicated and mostly bad reasons. 2646 */ 2647 if (smc->rma_limit) { 2648 rma_size = MIN(rma_size, smc->rma_limit); 2649 } 2650 2651 if (rma_size < MIN_RMA_SLOF) { 2652 error_setg(errp, 2653 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2654 "ldMiB guest RMA (Real Mode Area memory)", 2655 MIN_RMA_SLOF / MiB); 2656 return 0; 2657 } 2658 2659 return rma_size; 2660 } 2661 2662 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2663 { 2664 MachineState *machine = MACHINE(spapr); 2665 int i; 2666 2667 for (i = 0; i < machine->ram_slots; i++) { 2668 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2669 } 2670 } 2671 2672 /* pSeries LPAR / sPAPR hardware init */ 2673 static void spapr_machine_init(MachineState *machine) 2674 { 2675 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2676 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2677 MachineClass *mc = MACHINE_GET_CLASS(machine); 2678 const char *bios_default = spapr->vof ? FW_FILE_NAME_VOF : FW_FILE_NAME; 2679 const char *bios_name = machine->firmware ?: bios_default; 2680 const char *kernel_filename = machine->kernel_filename; 2681 const char *initrd_filename = machine->initrd_filename; 2682 PCIHostState *phb; 2683 int i; 2684 MemoryRegion *sysmem = get_system_memory(); 2685 long load_limit, fw_size; 2686 char *filename; 2687 Error *resize_hpt_err = NULL; 2688 2689 /* 2690 * if Secure VM (PEF) support is configured, then initialize it 2691 */ 2692 pef_kvm_init(machine->cgs, &error_fatal); 2693 2694 msi_nonbroken = true; 2695 2696 QLIST_INIT(&spapr->phbs); 2697 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2698 2699 /* Determine capabilities to run with */ 2700 spapr_caps_init(spapr); 2701 2702 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2703 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2704 /* 2705 * If the user explicitly requested a mode we should either 2706 * supply it, or fail completely (which we do below). But if 2707 * it's not set explicitly, we reset our mode to something 2708 * that works 2709 */ 2710 if (resize_hpt_err) { 2711 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2712 error_free(resize_hpt_err); 2713 resize_hpt_err = NULL; 2714 } else { 2715 spapr->resize_hpt = smc->resize_hpt_default; 2716 } 2717 } 2718 2719 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2720 2721 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2722 /* 2723 * User requested HPT resize, but this host can't supply it. Bail out 2724 */ 2725 error_report_err(resize_hpt_err); 2726 exit(1); 2727 } 2728 error_free(resize_hpt_err); 2729 2730 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2731 2732 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2733 load_limit = MIN(spapr->rma_size, FDT_MAX_ADDR) - FW_OVERHEAD; 2734 2735 /* 2736 * VSMT must be set in order to be able to compute VCPU ids, ie to 2737 * call spapr_max_server_number() or spapr_vcpu_id(). 2738 */ 2739 spapr_set_vsmt_mode(spapr, &error_fatal); 2740 2741 /* Set up Interrupt Controller before we create the VCPUs */ 2742 spapr_irq_init(spapr, &error_fatal); 2743 2744 /* Set up containers for ibm,client-architecture-support negotiated options 2745 */ 2746 spapr->ov5 = spapr_ovec_new(); 2747 spapr->ov5_cas = spapr_ovec_new(); 2748 2749 if (smc->dr_lmb_enabled) { 2750 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2751 spapr_validate_node_memory(machine, &error_fatal); 2752 } 2753 2754 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2755 2756 /* advertise support for dedicated HP event source to guests */ 2757 if (spapr->use_hotplug_event_source) { 2758 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2759 } 2760 2761 /* advertise support for HPT resizing */ 2762 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2763 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2764 } 2765 2766 /* advertise support for ibm,dyamic-memory-v2 */ 2767 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2768 2769 /* advertise XIVE on POWER9 machines */ 2770 if (spapr->irq->xive) { 2771 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2772 } 2773 2774 /* init CPUs */ 2775 spapr_init_cpus(spapr); 2776 2777 spapr->gpu_numa_id = spapr_numa_initial_nvgpu_numa_id(machine); 2778 2779 /* Init numa_assoc_array */ 2780 spapr_numa_associativity_init(spapr, machine); 2781 2782 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2783 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2784 spapr->max_compat_pvr)) { 2785 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2786 /* KVM and TCG always allow GTSE with radix... */ 2787 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2788 } 2789 /* ... but not with hash (currently). */ 2790 2791 if (kvm_enabled()) { 2792 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2793 kvmppc_enable_logical_ci_hcalls(); 2794 kvmppc_enable_set_mode_hcall(); 2795 2796 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2797 kvmppc_enable_clear_ref_mod_hcalls(); 2798 2799 /* Enable H_PAGE_INIT */ 2800 kvmppc_enable_h_page_init(); 2801 } 2802 2803 /* map RAM */ 2804 memory_region_add_subregion(sysmem, 0, machine->ram); 2805 2806 /* always allocate the device memory information */ 2807 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2808 2809 /* initialize hotplug memory address space */ 2810 if (machine->ram_size < machine->maxram_size) { 2811 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2812 /* 2813 * Limit the number of hotpluggable memory slots to half the number 2814 * slots that KVM supports, leaving the other half for PCI and other 2815 * devices. However ensure that number of slots doesn't drop below 32. 2816 */ 2817 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2818 SPAPR_MAX_RAM_SLOTS; 2819 2820 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2821 max_memslots = SPAPR_MAX_RAM_SLOTS; 2822 } 2823 if (machine->ram_slots > max_memslots) { 2824 error_report("Specified number of memory slots %" 2825 PRIu64" exceeds max supported %d", 2826 machine->ram_slots, max_memslots); 2827 exit(1); 2828 } 2829 2830 machine->device_memory->base = ROUND_UP(machine->ram_size, 2831 SPAPR_DEVICE_MEM_ALIGN); 2832 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2833 "device-memory", device_mem_size); 2834 memory_region_add_subregion(sysmem, machine->device_memory->base, 2835 &machine->device_memory->mr); 2836 } 2837 2838 if (smc->dr_lmb_enabled) { 2839 spapr_create_lmb_dr_connectors(spapr); 2840 } 2841 2842 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2843 /* Create the error string for live migration blocker */ 2844 error_setg(&spapr->fwnmi_migration_blocker, 2845 "A machine check is being handled during migration. The handler" 2846 "may run and log hardware error on the destination"); 2847 } 2848 2849 if (mc->nvdimm_supported) { 2850 spapr_create_nvdimm_dr_connectors(spapr); 2851 } 2852 2853 /* Set up RTAS event infrastructure */ 2854 spapr_events_init(spapr); 2855 2856 /* Set up the RTC RTAS interfaces */ 2857 spapr_rtc_create(spapr); 2858 2859 /* Set up VIO bus */ 2860 spapr->vio_bus = spapr_vio_bus_init(); 2861 2862 for (i = 0; serial_hd(i); i++) { 2863 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2864 } 2865 2866 /* We always have at least the nvram device on VIO */ 2867 spapr_create_nvram(spapr); 2868 2869 /* 2870 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2871 * connectors (described in root DT node's "ibm,drc-types" property) 2872 * are pre-initialized here. additional child connectors (such as 2873 * connectors for a PHBs PCI slots) are added as needed during their 2874 * parent's realization. 2875 */ 2876 if (smc->dr_phb_enabled) { 2877 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2878 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2879 } 2880 } 2881 2882 /* Set up PCI */ 2883 spapr_pci_rtas_init(); 2884 2885 phb = spapr_create_default_phb(); 2886 2887 for (i = 0; i < nb_nics; i++) { 2888 NICInfo *nd = &nd_table[i]; 2889 2890 if (!nd->model) { 2891 nd->model = g_strdup("spapr-vlan"); 2892 } 2893 2894 if (g_str_equal(nd->model, "spapr-vlan") || 2895 g_str_equal(nd->model, "ibmveth")) { 2896 spapr_vlan_create(spapr->vio_bus, nd); 2897 } else { 2898 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2899 } 2900 } 2901 2902 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2903 spapr_vscsi_create(spapr->vio_bus); 2904 } 2905 2906 /* Graphics */ 2907 if (spapr_vga_init(phb->bus, &error_fatal)) { 2908 spapr->has_graphics = true; 2909 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2910 } 2911 2912 if (machine->usb) { 2913 if (smc->use_ohci_by_default) { 2914 pci_create_simple(phb->bus, -1, "pci-ohci"); 2915 } else { 2916 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2917 } 2918 2919 if (spapr->has_graphics) { 2920 USBBus *usb_bus = usb_bus_find(-1); 2921 2922 usb_create_simple(usb_bus, "usb-kbd"); 2923 usb_create_simple(usb_bus, "usb-mouse"); 2924 } 2925 } 2926 2927 if (kernel_filename) { 2928 spapr->kernel_size = load_elf(kernel_filename, NULL, 2929 translate_kernel_address, spapr, 2930 NULL, NULL, NULL, NULL, 1, 2931 PPC_ELF_MACHINE, 0, 0); 2932 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2933 spapr->kernel_size = load_elf(kernel_filename, NULL, 2934 translate_kernel_address, spapr, 2935 NULL, NULL, NULL, NULL, 0, 2936 PPC_ELF_MACHINE, 0, 0); 2937 spapr->kernel_le = spapr->kernel_size > 0; 2938 } 2939 if (spapr->kernel_size < 0) { 2940 error_report("error loading %s: %s", kernel_filename, 2941 load_elf_strerror(spapr->kernel_size)); 2942 exit(1); 2943 } 2944 2945 /* load initrd */ 2946 if (initrd_filename) { 2947 /* Try to locate the initrd in the gap between the kernel 2948 * and the firmware. Add a bit of space just in case 2949 */ 2950 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2951 + 0x1ffff) & ~0xffff; 2952 spapr->initrd_size = load_image_targphys(initrd_filename, 2953 spapr->initrd_base, 2954 load_limit 2955 - spapr->initrd_base); 2956 if (spapr->initrd_size < 0) { 2957 error_report("could not load initial ram disk '%s'", 2958 initrd_filename); 2959 exit(1); 2960 } 2961 } 2962 } 2963 2964 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2965 if (!filename) { 2966 error_report("Could not find LPAR firmware '%s'", bios_name); 2967 exit(1); 2968 } 2969 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2970 if (fw_size <= 0) { 2971 error_report("Could not load LPAR firmware '%s'", filename); 2972 exit(1); 2973 } 2974 g_free(filename); 2975 2976 /* FIXME: Should register things through the MachineState's qdev 2977 * interface, this is a legacy from the sPAPREnvironment structure 2978 * which predated MachineState but had a similar function */ 2979 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2980 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 2981 &savevm_htab_handlers, spapr); 2982 2983 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 2984 2985 qemu_register_boot_set(spapr_boot_set, spapr); 2986 2987 /* 2988 * Nothing needs to be done to resume a suspended guest because 2989 * suspending does not change the machine state, so no need for 2990 * a ->wakeup method. 2991 */ 2992 qemu_register_wakeup_support(); 2993 2994 if (kvm_enabled()) { 2995 /* to stop and start vmclock */ 2996 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2997 &spapr->tb); 2998 2999 kvmppc_spapr_enable_inkernel_multitce(); 3000 } 3001 3002 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3003 if (spapr->vof) { 3004 spapr->vof->fw_size = fw_size; /* for claim() on itself */ 3005 spapr_register_hypercall(KVMPPC_H_VOF_CLIENT, spapr_h_vof_client); 3006 } 3007 } 3008 3009 #define DEFAULT_KVM_TYPE "auto" 3010 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3011 { 3012 /* 3013 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3014 * accomodate the 'HV' and 'PV' formats that exists in the 3015 * wild. The 'auto' mode is being introduced already as 3016 * lower-case, thus we don't need to bother checking for 3017 * "AUTO". 3018 */ 3019 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3020 return 0; 3021 } 3022 3023 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3024 return 1; 3025 } 3026 3027 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3028 return 2; 3029 } 3030 3031 error_report("Unknown kvm-type specified '%s'", vm_type); 3032 exit(1); 3033 } 3034 3035 /* 3036 * Implementation of an interface to adjust firmware path 3037 * for the bootindex property handling. 3038 */ 3039 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3040 DeviceState *dev) 3041 { 3042 #define CAST(type, obj, name) \ 3043 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3044 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3045 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3046 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3047 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3048 3049 if (d) { 3050 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3051 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3052 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3053 3054 if (spapr) { 3055 /* 3056 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3057 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3058 * 0x8000 | (target << 8) | (bus << 5) | lun 3059 * (see the "Logical unit addressing format" table in SAM5) 3060 */ 3061 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3062 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3063 (uint64_t)id << 48); 3064 } else if (virtio) { 3065 /* 3066 * We use SRP luns of the form 01000000 | (target << 8) | lun 3067 * in the top 32 bits of the 64-bit LUN 3068 * Note: the quote above is from SLOF and it is wrong, 3069 * the actual binding is: 3070 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3071 */ 3072 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3073 if (d->lun >= 256) { 3074 /* Use the LUN "flat space addressing method" */ 3075 id |= 0x4000; 3076 } 3077 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3078 (uint64_t)id << 32); 3079 } else if (usb) { 3080 /* 3081 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3082 * in the top 32 bits of the 64-bit LUN 3083 */ 3084 unsigned usb_port = atoi(usb->port->path); 3085 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3086 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3087 (uint64_t)id << 32); 3088 } 3089 } 3090 3091 /* 3092 * SLOF probes the USB devices, and if it recognizes that the device is a 3093 * storage device, it changes its name to "storage" instead of "usb-host", 3094 * and additionally adds a child node for the SCSI LUN, so the correct 3095 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3096 */ 3097 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3098 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3099 if (usb_device_is_scsi_storage(usbdev)) { 3100 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3101 } 3102 } 3103 3104 if (phb) { 3105 /* Replace "pci" with "pci@800000020000000" */ 3106 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3107 } 3108 3109 if (vsc) { 3110 /* Same logic as virtio above */ 3111 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3112 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3113 } 3114 3115 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3116 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3117 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3118 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3119 } 3120 3121 if (pcidev) { 3122 return spapr_pci_fw_dev_name(pcidev); 3123 } 3124 3125 return NULL; 3126 } 3127 3128 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3129 { 3130 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3131 3132 return g_strdup(spapr->kvm_type); 3133 } 3134 3135 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3136 { 3137 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3138 3139 g_free(spapr->kvm_type); 3140 spapr->kvm_type = g_strdup(value); 3141 } 3142 3143 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3144 { 3145 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3146 3147 return spapr->use_hotplug_event_source; 3148 } 3149 3150 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3151 Error **errp) 3152 { 3153 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3154 3155 spapr->use_hotplug_event_source = value; 3156 } 3157 3158 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3159 { 3160 return true; 3161 } 3162 3163 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3164 { 3165 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3166 3167 switch (spapr->resize_hpt) { 3168 case SPAPR_RESIZE_HPT_DEFAULT: 3169 return g_strdup("default"); 3170 case SPAPR_RESIZE_HPT_DISABLED: 3171 return g_strdup("disabled"); 3172 case SPAPR_RESIZE_HPT_ENABLED: 3173 return g_strdup("enabled"); 3174 case SPAPR_RESIZE_HPT_REQUIRED: 3175 return g_strdup("required"); 3176 } 3177 g_assert_not_reached(); 3178 } 3179 3180 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3181 { 3182 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3183 3184 if (strcmp(value, "default") == 0) { 3185 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3186 } else if (strcmp(value, "disabled") == 0) { 3187 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3188 } else if (strcmp(value, "enabled") == 0) { 3189 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3190 } else if (strcmp(value, "required") == 0) { 3191 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3192 } else { 3193 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3194 } 3195 } 3196 3197 static bool spapr_get_vof(Object *obj, Error **errp) 3198 { 3199 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3200 3201 return spapr->vof != NULL; 3202 } 3203 3204 static void spapr_set_vof(Object *obj, bool value, Error **errp) 3205 { 3206 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3207 3208 if (spapr->vof) { 3209 vof_cleanup(spapr->vof); 3210 g_free(spapr->vof); 3211 spapr->vof = NULL; 3212 } 3213 if (!value) { 3214 return; 3215 } 3216 spapr->vof = g_malloc0(sizeof(*spapr->vof)); 3217 } 3218 3219 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3220 { 3221 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3222 3223 if (spapr->irq == &spapr_irq_xics_legacy) { 3224 return g_strdup("legacy"); 3225 } else if (spapr->irq == &spapr_irq_xics) { 3226 return g_strdup("xics"); 3227 } else if (spapr->irq == &spapr_irq_xive) { 3228 return g_strdup("xive"); 3229 } else if (spapr->irq == &spapr_irq_dual) { 3230 return g_strdup("dual"); 3231 } 3232 g_assert_not_reached(); 3233 } 3234 3235 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3236 { 3237 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3238 3239 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3240 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3241 return; 3242 } 3243 3244 /* The legacy IRQ backend can not be set */ 3245 if (strcmp(value, "xics") == 0) { 3246 spapr->irq = &spapr_irq_xics; 3247 } else if (strcmp(value, "xive") == 0) { 3248 spapr->irq = &spapr_irq_xive; 3249 } else if (strcmp(value, "dual") == 0) { 3250 spapr->irq = &spapr_irq_dual; 3251 } else { 3252 error_setg(errp, "Bad value for \"ic-mode\" property"); 3253 } 3254 } 3255 3256 static char *spapr_get_host_model(Object *obj, Error **errp) 3257 { 3258 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3259 3260 return g_strdup(spapr->host_model); 3261 } 3262 3263 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3264 { 3265 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3266 3267 g_free(spapr->host_model); 3268 spapr->host_model = g_strdup(value); 3269 } 3270 3271 static char *spapr_get_host_serial(Object *obj, Error **errp) 3272 { 3273 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3274 3275 return g_strdup(spapr->host_serial); 3276 } 3277 3278 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3279 { 3280 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3281 3282 g_free(spapr->host_serial); 3283 spapr->host_serial = g_strdup(value); 3284 } 3285 3286 static void spapr_instance_init(Object *obj) 3287 { 3288 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3289 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3290 MachineState *ms = MACHINE(spapr); 3291 MachineClass *mc = MACHINE_GET_CLASS(ms); 3292 3293 /* 3294 * NVDIMM support went live in 5.1 without considering that, in 3295 * other archs, the user needs to enable NVDIMM support with the 3296 * 'nvdimm' machine option and the default behavior is NVDIMM 3297 * support disabled. It is too late to roll back to the standard 3298 * behavior without breaking 5.1 guests. 3299 */ 3300 if (mc->nvdimm_supported) { 3301 ms->nvdimms_state->is_enabled = true; 3302 } 3303 3304 spapr->htab_fd = -1; 3305 spapr->use_hotplug_event_source = true; 3306 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3307 object_property_add_str(obj, "kvm-type", 3308 spapr_get_kvm_type, spapr_set_kvm_type); 3309 object_property_set_description(obj, "kvm-type", 3310 "Specifies the KVM virtualization mode (auto," 3311 " hv, pr). Defaults to 'auto'. This mode will use" 3312 " any available KVM module loaded in the host," 3313 " where kvm_hv takes precedence if both kvm_hv and" 3314 " kvm_pr are loaded."); 3315 object_property_add_bool(obj, "modern-hotplug-events", 3316 spapr_get_modern_hotplug_events, 3317 spapr_set_modern_hotplug_events); 3318 object_property_set_description(obj, "modern-hotplug-events", 3319 "Use dedicated hotplug event mechanism in" 3320 " place of standard EPOW events when possible" 3321 " (required for memory hot-unplug support)"); 3322 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3323 "Maximum permitted CPU compatibility mode"); 3324 3325 object_property_add_str(obj, "resize-hpt", 3326 spapr_get_resize_hpt, spapr_set_resize_hpt); 3327 object_property_set_description(obj, "resize-hpt", 3328 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3329 object_property_add_uint32_ptr(obj, "vsmt", 3330 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3331 object_property_set_description(obj, "vsmt", 3332 "Virtual SMT: KVM behaves as if this were" 3333 " the host's SMT mode"); 3334 3335 object_property_add_bool(obj, "vfio-no-msix-emulation", 3336 spapr_get_msix_emulation, NULL); 3337 3338 object_property_add_uint64_ptr(obj, "kernel-addr", 3339 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3340 object_property_set_description(obj, "kernel-addr", 3341 stringify(KERNEL_LOAD_ADDR) 3342 " for -kernel is the default"); 3343 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3344 3345 object_property_add_bool(obj, "x-vof", spapr_get_vof, spapr_set_vof); 3346 object_property_set_description(obj, "x-vof", 3347 "Enable Virtual Open Firmware (experimental)"); 3348 3349 /* The machine class defines the default interrupt controller mode */ 3350 spapr->irq = smc->irq; 3351 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3352 spapr_set_ic_mode); 3353 object_property_set_description(obj, "ic-mode", 3354 "Specifies the interrupt controller mode (xics, xive, dual)"); 3355 3356 object_property_add_str(obj, "host-model", 3357 spapr_get_host_model, spapr_set_host_model); 3358 object_property_set_description(obj, "host-model", 3359 "Host model to advertise in guest device tree"); 3360 object_property_add_str(obj, "host-serial", 3361 spapr_get_host_serial, spapr_set_host_serial); 3362 object_property_set_description(obj, "host-serial", 3363 "Host serial number to advertise in guest device tree"); 3364 } 3365 3366 static void spapr_machine_finalizefn(Object *obj) 3367 { 3368 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3369 3370 g_free(spapr->kvm_type); 3371 } 3372 3373 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3374 { 3375 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3376 PowerPCCPU *cpu = POWERPC_CPU(cs); 3377 CPUPPCState *env = &cpu->env; 3378 3379 cpu_synchronize_state(cs); 3380 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3381 if (spapr->fwnmi_system_reset_addr != -1) { 3382 uint64_t rtas_addr, addr; 3383 3384 /* get rtas addr from fdt */ 3385 rtas_addr = spapr_get_rtas_addr(); 3386 if (!rtas_addr) { 3387 qemu_system_guest_panicked(NULL); 3388 return; 3389 } 3390 3391 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3392 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3393 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3394 env->gpr[3] = addr; 3395 } 3396 ppc_cpu_do_system_reset(cs); 3397 if (spapr->fwnmi_system_reset_addr != -1) { 3398 env->nip = spapr->fwnmi_system_reset_addr; 3399 } 3400 } 3401 3402 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3403 { 3404 CPUState *cs; 3405 3406 CPU_FOREACH(cs) { 3407 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3408 } 3409 } 3410 3411 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3412 void *fdt, int *fdt_start_offset, Error **errp) 3413 { 3414 uint64_t addr; 3415 uint32_t node; 3416 3417 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3418 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3419 &error_abort); 3420 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3421 SPAPR_MEMORY_BLOCK_SIZE); 3422 return 0; 3423 } 3424 3425 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3426 bool dedicated_hp_event_source) 3427 { 3428 SpaprDrc *drc; 3429 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3430 int i; 3431 uint64_t addr = addr_start; 3432 bool hotplugged = spapr_drc_hotplugged(dev); 3433 3434 for (i = 0; i < nr_lmbs; i++) { 3435 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3436 addr / SPAPR_MEMORY_BLOCK_SIZE); 3437 g_assert(drc); 3438 3439 /* 3440 * memory_device_get_free_addr() provided a range of free addresses 3441 * that doesn't overlap with any existing mapping at pre-plug. The 3442 * corresponding LMB DRCs are thus assumed to be all attachable. 3443 */ 3444 spapr_drc_attach(drc, dev); 3445 if (!hotplugged) { 3446 spapr_drc_reset(drc); 3447 } 3448 addr += SPAPR_MEMORY_BLOCK_SIZE; 3449 } 3450 /* send hotplug notification to the 3451 * guest only in case of hotplugged memory 3452 */ 3453 if (hotplugged) { 3454 if (dedicated_hp_event_source) { 3455 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3456 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3457 g_assert(drc); 3458 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3459 nr_lmbs, 3460 spapr_drc_index(drc)); 3461 } else { 3462 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3463 nr_lmbs); 3464 } 3465 } 3466 } 3467 3468 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3469 { 3470 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3471 PCDIMMDevice *dimm = PC_DIMM(dev); 3472 uint64_t size, addr; 3473 int64_t slot; 3474 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3475 3476 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3477 3478 pc_dimm_plug(dimm, MACHINE(ms)); 3479 3480 if (!is_nvdimm) { 3481 addr = object_property_get_uint(OBJECT(dimm), 3482 PC_DIMM_ADDR_PROP, &error_abort); 3483 spapr_add_lmbs(dev, addr, size, 3484 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3485 } else { 3486 slot = object_property_get_int(OBJECT(dimm), 3487 PC_DIMM_SLOT_PROP, &error_abort); 3488 /* We should have valid slot number at this point */ 3489 g_assert(slot >= 0); 3490 spapr_add_nvdimm(dev, slot); 3491 } 3492 } 3493 3494 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3495 Error **errp) 3496 { 3497 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3498 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3499 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3500 PCDIMMDevice *dimm = PC_DIMM(dev); 3501 Error *local_err = NULL; 3502 uint64_t size; 3503 Object *memdev; 3504 hwaddr pagesize; 3505 3506 if (!smc->dr_lmb_enabled) { 3507 error_setg(errp, "Memory hotplug not supported for this machine"); 3508 return; 3509 } 3510 3511 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3512 if (local_err) { 3513 error_propagate(errp, local_err); 3514 return; 3515 } 3516 3517 if (is_nvdimm) { 3518 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3519 return; 3520 } 3521 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3522 error_setg(errp, "Hotplugged memory size must be a multiple of " 3523 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3524 return; 3525 } 3526 3527 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3528 &error_abort); 3529 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3530 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3531 return; 3532 } 3533 3534 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3535 } 3536 3537 struct SpaprDimmState { 3538 PCDIMMDevice *dimm; 3539 uint32_t nr_lmbs; 3540 QTAILQ_ENTRY(SpaprDimmState) next; 3541 }; 3542 3543 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3544 PCDIMMDevice *dimm) 3545 { 3546 SpaprDimmState *dimm_state = NULL; 3547 3548 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3549 if (dimm_state->dimm == dimm) { 3550 break; 3551 } 3552 } 3553 return dimm_state; 3554 } 3555 3556 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3557 uint32_t nr_lmbs, 3558 PCDIMMDevice *dimm) 3559 { 3560 SpaprDimmState *ds = NULL; 3561 3562 /* 3563 * If this request is for a DIMM whose removal had failed earlier 3564 * (due to guest's refusal to remove the LMBs), we would have this 3565 * dimm already in the pending_dimm_unplugs list. In that 3566 * case don't add again. 3567 */ 3568 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3569 if (!ds) { 3570 ds = g_malloc0(sizeof(SpaprDimmState)); 3571 ds->nr_lmbs = nr_lmbs; 3572 ds->dimm = dimm; 3573 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3574 } 3575 return ds; 3576 } 3577 3578 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3579 SpaprDimmState *dimm_state) 3580 { 3581 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3582 g_free(dimm_state); 3583 } 3584 3585 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3586 PCDIMMDevice *dimm) 3587 { 3588 SpaprDrc *drc; 3589 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3590 &error_abort); 3591 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3592 uint32_t avail_lmbs = 0; 3593 uint64_t addr_start, addr; 3594 int i; 3595 3596 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3597 &error_abort); 3598 3599 addr = addr_start; 3600 for (i = 0; i < nr_lmbs; i++) { 3601 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3602 addr / SPAPR_MEMORY_BLOCK_SIZE); 3603 g_assert(drc); 3604 if (drc->dev) { 3605 avail_lmbs++; 3606 } 3607 addr += SPAPR_MEMORY_BLOCK_SIZE; 3608 } 3609 3610 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3611 } 3612 3613 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev) 3614 { 3615 SpaprDimmState *ds; 3616 PCDIMMDevice *dimm; 3617 SpaprDrc *drc; 3618 uint32_t nr_lmbs; 3619 uint64_t size, addr_start, addr; 3620 g_autofree char *qapi_error = NULL; 3621 int i; 3622 3623 if (!dev) { 3624 return; 3625 } 3626 3627 dimm = PC_DIMM(dev); 3628 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3629 3630 /* 3631 * 'ds == NULL' would mean that the DIMM doesn't have a pending 3632 * unplug state, but one of its DRC is marked as unplug_requested. 3633 * This is bad and weird enough to g_assert() out. 3634 */ 3635 g_assert(ds); 3636 3637 spapr_pending_dimm_unplugs_remove(spapr, ds); 3638 3639 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3640 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3641 3642 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3643 &error_abort); 3644 3645 addr = addr_start; 3646 for (i = 0; i < nr_lmbs; i++) { 3647 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3648 addr / SPAPR_MEMORY_BLOCK_SIZE); 3649 g_assert(drc); 3650 3651 drc->unplug_requested = false; 3652 addr += SPAPR_MEMORY_BLOCK_SIZE; 3653 } 3654 3655 /* 3656 * Tell QAPI that something happened and the memory 3657 * hotunplug wasn't successful. Keep sending 3658 * MEM_UNPLUG_ERROR even while sending 3659 * DEVICE_UNPLUG_GUEST_ERROR until the deprecation of 3660 * MEM_UNPLUG_ERROR is due. 3661 */ 3662 qapi_error = g_strdup_printf("Memory hotunplug rejected by the guest " 3663 "for device %s", dev->id); 3664 3665 qapi_event_send_mem_unplug_error(dev->id ? : "", qapi_error); 3666 3667 qapi_event_send_device_unplug_guest_error(!!dev->id, dev->id, 3668 dev->canonical_path); 3669 } 3670 3671 /* Callback to be called during DRC release. */ 3672 void spapr_lmb_release(DeviceState *dev) 3673 { 3674 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3675 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3676 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3677 3678 /* This information will get lost if a migration occurs 3679 * during the unplug process. In this case recover it. */ 3680 if (ds == NULL) { 3681 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3682 g_assert(ds); 3683 /* The DRC being examined by the caller at least must be counted */ 3684 g_assert(ds->nr_lmbs); 3685 } 3686 3687 if (--ds->nr_lmbs) { 3688 return; 3689 } 3690 3691 /* 3692 * Now that all the LMBs have been removed by the guest, call the 3693 * unplug handler chain. This can never fail. 3694 */ 3695 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3696 object_unparent(OBJECT(dev)); 3697 } 3698 3699 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3700 { 3701 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3702 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3703 3704 /* We really shouldn't get this far without anything to unplug */ 3705 g_assert(ds); 3706 3707 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3708 qdev_unrealize(dev); 3709 spapr_pending_dimm_unplugs_remove(spapr, ds); 3710 } 3711 3712 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3713 DeviceState *dev, Error **errp) 3714 { 3715 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3716 PCDIMMDevice *dimm = PC_DIMM(dev); 3717 uint32_t nr_lmbs; 3718 uint64_t size, addr_start, addr; 3719 int i; 3720 SpaprDrc *drc; 3721 3722 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3723 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3724 return; 3725 } 3726 3727 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3728 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3729 3730 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3731 &error_abort); 3732 3733 /* 3734 * An existing pending dimm state for this DIMM means that there is an 3735 * unplug operation in progress, waiting for the spapr_lmb_release 3736 * callback to complete the job (BQL can't cover that far). In this case, 3737 * bail out to avoid detaching DRCs that were already released. 3738 */ 3739 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3740 error_setg(errp, "Memory unplug already in progress for device %s", 3741 dev->id); 3742 return; 3743 } 3744 3745 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3746 3747 addr = addr_start; 3748 for (i = 0; i < nr_lmbs; i++) { 3749 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3750 addr / SPAPR_MEMORY_BLOCK_SIZE); 3751 g_assert(drc); 3752 3753 spapr_drc_unplug_request(drc); 3754 addr += SPAPR_MEMORY_BLOCK_SIZE; 3755 } 3756 3757 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3758 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3759 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3760 nr_lmbs, spapr_drc_index(drc)); 3761 } 3762 3763 /* Callback to be called during DRC release. */ 3764 void spapr_core_release(DeviceState *dev) 3765 { 3766 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3767 3768 /* Call the unplug handler chain. This can never fail. */ 3769 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3770 object_unparent(OBJECT(dev)); 3771 } 3772 3773 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3774 { 3775 MachineState *ms = MACHINE(hotplug_dev); 3776 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3777 CPUCore *cc = CPU_CORE(dev); 3778 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3779 3780 if (smc->pre_2_10_has_unused_icps) { 3781 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3782 int i; 3783 3784 for (i = 0; i < cc->nr_threads; i++) { 3785 CPUState *cs = CPU(sc->threads[i]); 3786 3787 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3788 } 3789 } 3790 3791 assert(core_slot); 3792 core_slot->cpu = NULL; 3793 qdev_unrealize(dev); 3794 } 3795 3796 static 3797 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3798 Error **errp) 3799 { 3800 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3801 int index; 3802 SpaprDrc *drc; 3803 CPUCore *cc = CPU_CORE(dev); 3804 3805 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3806 error_setg(errp, "Unable to find CPU core with core-id: %d", 3807 cc->core_id); 3808 return; 3809 } 3810 if (index == 0) { 3811 error_setg(errp, "Boot CPU core may not be unplugged"); 3812 return; 3813 } 3814 3815 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3816 spapr_vcpu_id(spapr, cc->core_id)); 3817 g_assert(drc); 3818 3819 if (!spapr_drc_unplug_requested(drc)) { 3820 spapr_drc_unplug_request(drc); 3821 } 3822 3823 /* 3824 * spapr_hotplug_req_remove_by_index is left unguarded, out of the 3825 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ 3826 * pulses removing the same CPU. Otherwise, in an failed hotunplug 3827 * attempt (e.g. the kernel will refuse to remove the last online 3828 * CPU), we will never attempt it again because unplug_requested 3829 * will still be 'true' in that case. 3830 */ 3831 spapr_hotplug_req_remove_by_index(drc); 3832 } 3833 3834 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3835 void *fdt, int *fdt_start_offset, Error **errp) 3836 { 3837 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3838 CPUState *cs = CPU(core->threads[0]); 3839 PowerPCCPU *cpu = POWERPC_CPU(cs); 3840 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3841 int id = spapr_get_vcpu_id(cpu); 3842 g_autofree char *nodename = NULL; 3843 int offset; 3844 3845 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3846 offset = fdt_add_subnode(fdt, 0, nodename); 3847 3848 spapr_dt_cpu(cs, fdt, offset, spapr); 3849 3850 /* 3851 * spapr_dt_cpu() does not fill the 'name' property in the 3852 * CPU node. The function is called during boot process, before 3853 * and after CAS, and overwriting the 'name' property written 3854 * by SLOF is not allowed. 3855 * 3856 * Write it manually after spapr_dt_cpu(). This makes the hotplug 3857 * CPUs more compatible with the coldplugged ones, which have 3858 * the 'name' property. Linux Kernel also relies on this 3859 * property to identify CPU nodes. 3860 */ 3861 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 3862 3863 *fdt_start_offset = offset; 3864 return 0; 3865 } 3866 3867 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3868 { 3869 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3870 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3871 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3872 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3873 CPUCore *cc = CPU_CORE(dev); 3874 CPUState *cs; 3875 SpaprDrc *drc; 3876 CPUArchId *core_slot; 3877 int index; 3878 bool hotplugged = spapr_drc_hotplugged(dev); 3879 int i; 3880 3881 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3882 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 3883 3884 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3885 spapr_vcpu_id(spapr, cc->core_id)); 3886 3887 g_assert(drc || !mc->has_hotpluggable_cpus); 3888 3889 if (drc) { 3890 /* 3891 * spapr_core_pre_plug() already buys us this is a brand new 3892 * core being plugged into a free slot. Nothing should already 3893 * be attached to the corresponding DRC. 3894 */ 3895 spapr_drc_attach(drc, dev); 3896 3897 if (hotplugged) { 3898 /* 3899 * Send hotplug notification interrupt to the guest only 3900 * in case of hotplugged CPUs. 3901 */ 3902 spapr_hotplug_req_add_by_index(drc); 3903 } else { 3904 spapr_drc_reset(drc); 3905 } 3906 } 3907 3908 core_slot->cpu = OBJECT(dev); 3909 3910 /* 3911 * Set compatibility mode to match the boot CPU, which was either set 3912 * by the machine reset code or by CAS. This really shouldn't fail at 3913 * this point. 3914 */ 3915 if (hotplugged) { 3916 for (i = 0; i < cc->nr_threads; i++) { 3917 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3918 &error_abort); 3919 } 3920 } 3921 3922 if (smc->pre_2_10_has_unused_icps) { 3923 for (i = 0; i < cc->nr_threads; i++) { 3924 cs = CPU(core->threads[i]); 3925 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3926 } 3927 } 3928 } 3929 3930 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3931 Error **errp) 3932 { 3933 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3934 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3935 CPUCore *cc = CPU_CORE(dev); 3936 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3937 const char *type = object_get_typename(OBJECT(dev)); 3938 CPUArchId *core_slot; 3939 int index; 3940 unsigned int smp_threads = machine->smp.threads; 3941 3942 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3943 error_setg(errp, "CPU hotplug not supported for this machine"); 3944 return; 3945 } 3946 3947 if (strcmp(base_core_type, type)) { 3948 error_setg(errp, "CPU core type should be %s", base_core_type); 3949 return; 3950 } 3951 3952 if (cc->core_id % smp_threads) { 3953 error_setg(errp, "invalid core id %d", cc->core_id); 3954 return; 3955 } 3956 3957 /* 3958 * In general we should have homogeneous threads-per-core, but old 3959 * (pre hotplug support) machine types allow the last core to have 3960 * reduced threads as a compatibility hack for when we allowed 3961 * total vcpus not a multiple of threads-per-core. 3962 */ 3963 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3964 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 3965 smp_threads); 3966 return; 3967 } 3968 3969 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3970 if (!core_slot) { 3971 error_setg(errp, "core id %d out of range", cc->core_id); 3972 return; 3973 } 3974 3975 if (core_slot->cpu) { 3976 error_setg(errp, "core %d already populated", cc->core_id); 3977 return; 3978 } 3979 3980 numa_cpu_pre_plug(core_slot, dev, errp); 3981 } 3982 3983 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3984 void *fdt, int *fdt_start_offset, Error **errp) 3985 { 3986 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3987 int intc_phandle; 3988 3989 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3990 if (intc_phandle <= 0) { 3991 return -1; 3992 } 3993 3994 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3995 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3996 return -1; 3997 } 3998 3999 /* generally SLOF creates these, for hotplug it's up to QEMU */ 4000 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 4001 4002 return 0; 4003 } 4004 4005 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4006 Error **errp) 4007 { 4008 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4009 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4010 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4011 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 4012 SpaprDrc *drc; 4013 4014 if (dev->hotplugged && !smc->dr_phb_enabled) { 4015 error_setg(errp, "PHB hotplug not supported for this machine"); 4016 return false; 4017 } 4018 4019 if (sphb->index == (uint32_t)-1) { 4020 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 4021 return false; 4022 } 4023 4024 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4025 if (drc && drc->dev) { 4026 error_setg(errp, "PHB %d already attached", sphb->index); 4027 return false; 4028 } 4029 4030 /* 4031 * This will check that sphb->index doesn't exceed the maximum number of 4032 * PHBs for the current machine type. 4033 */ 4034 return 4035 smc->phb_placement(spapr, sphb->index, 4036 &sphb->buid, &sphb->io_win_addr, 4037 &sphb->mem_win_addr, &sphb->mem64_win_addr, 4038 windows_supported, sphb->dma_liobn, 4039 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 4040 errp); 4041 } 4042 4043 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4044 { 4045 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4046 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4047 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4048 SpaprDrc *drc; 4049 bool hotplugged = spapr_drc_hotplugged(dev); 4050 4051 if (!smc->dr_phb_enabled) { 4052 return; 4053 } 4054 4055 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4056 /* hotplug hooks should check it's enabled before getting this far */ 4057 assert(drc); 4058 4059 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 4060 spapr_drc_attach(drc, dev); 4061 4062 if (hotplugged) { 4063 spapr_hotplug_req_add_by_index(drc); 4064 } else { 4065 spapr_drc_reset(drc); 4066 } 4067 } 4068 4069 void spapr_phb_release(DeviceState *dev) 4070 { 4071 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4072 4073 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4074 object_unparent(OBJECT(dev)); 4075 } 4076 4077 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4078 { 4079 qdev_unrealize(dev); 4080 } 4081 4082 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4083 DeviceState *dev, Error **errp) 4084 { 4085 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4086 SpaprDrc *drc; 4087 4088 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4089 assert(drc); 4090 4091 if (!spapr_drc_unplug_requested(drc)) { 4092 spapr_drc_unplug_request(drc); 4093 spapr_hotplug_req_remove_by_index(drc); 4094 } else { 4095 error_setg(errp, 4096 "PCI Host Bridge unplug already in progress for device %s", 4097 dev->id); 4098 } 4099 } 4100 4101 static 4102 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4103 Error **errp) 4104 { 4105 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4106 4107 if (spapr->tpm_proxy != NULL) { 4108 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4109 return false; 4110 } 4111 4112 return true; 4113 } 4114 4115 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4116 { 4117 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4118 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4119 4120 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4121 g_assert(spapr->tpm_proxy == NULL); 4122 4123 spapr->tpm_proxy = tpm_proxy; 4124 } 4125 4126 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4127 { 4128 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4129 4130 qdev_unrealize(dev); 4131 object_unparent(OBJECT(dev)); 4132 spapr->tpm_proxy = NULL; 4133 } 4134 4135 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4136 DeviceState *dev, Error **errp) 4137 { 4138 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4139 spapr_memory_plug(hotplug_dev, dev); 4140 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4141 spapr_core_plug(hotplug_dev, dev); 4142 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4143 spapr_phb_plug(hotplug_dev, dev); 4144 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4145 spapr_tpm_proxy_plug(hotplug_dev, dev); 4146 } 4147 } 4148 4149 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4150 DeviceState *dev, Error **errp) 4151 { 4152 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4153 spapr_memory_unplug(hotplug_dev, dev); 4154 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4155 spapr_core_unplug(hotplug_dev, dev); 4156 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4157 spapr_phb_unplug(hotplug_dev, dev); 4158 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4159 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4160 } 4161 } 4162 4163 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4164 { 4165 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4166 /* 4167 * CAS will process all pending unplug requests. 4168 * 4169 * HACK: a guest could theoretically have cleared all bits in OV5, 4170 * but none of the guests we care for do. 4171 */ 4172 spapr_ovec_empty(spapr->ov5_cas); 4173 } 4174 4175 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4176 DeviceState *dev, Error **errp) 4177 { 4178 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4179 MachineClass *mc = MACHINE_GET_CLASS(sms); 4180 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4181 4182 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4183 if (spapr_memory_hot_unplug_supported(sms)) { 4184 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4185 } else { 4186 error_setg(errp, "Memory hot unplug not supported for this guest"); 4187 } 4188 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4189 if (!mc->has_hotpluggable_cpus) { 4190 error_setg(errp, "CPU hot unplug not supported on this machine"); 4191 return; 4192 } 4193 spapr_core_unplug_request(hotplug_dev, dev, errp); 4194 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4195 if (!smc->dr_phb_enabled) { 4196 error_setg(errp, "PHB hot unplug not supported on this machine"); 4197 return; 4198 } 4199 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4200 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4201 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4202 } 4203 } 4204 4205 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4206 DeviceState *dev, Error **errp) 4207 { 4208 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4209 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4210 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4211 spapr_core_pre_plug(hotplug_dev, dev, errp); 4212 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4213 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4214 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4215 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4216 } 4217 } 4218 4219 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4220 DeviceState *dev) 4221 { 4222 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4223 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4224 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4225 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4226 return HOTPLUG_HANDLER(machine); 4227 } 4228 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4229 PCIDevice *pcidev = PCI_DEVICE(dev); 4230 PCIBus *root = pci_device_root_bus(pcidev); 4231 SpaprPhbState *phb = 4232 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4233 TYPE_SPAPR_PCI_HOST_BRIDGE); 4234 4235 if (phb) { 4236 return HOTPLUG_HANDLER(phb); 4237 } 4238 } 4239 return NULL; 4240 } 4241 4242 static CpuInstanceProperties 4243 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4244 { 4245 CPUArchId *core_slot; 4246 MachineClass *mc = MACHINE_GET_CLASS(machine); 4247 4248 /* make sure possible_cpu are intialized */ 4249 mc->possible_cpu_arch_ids(machine); 4250 /* get CPU core slot containing thread that matches cpu_index */ 4251 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4252 assert(core_slot); 4253 return core_slot->props; 4254 } 4255 4256 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4257 { 4258 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4259 } 4260 4261 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4262 { 4263 int i; 4264 unsigned int smp_threads = machine->smp.threads; 4265 unsigned int smp_cpus = machine->smp.cpus; 4266 const char *core_type; 4267 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4268 MachineClass *mc = MACHINE_GET_CLASS(machine); 4269 4270 if (!mc->has_hotpluggable_cpus) { 4271 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4272 } 4273 if (machine->possible_cpus) { 4274 assert(machine->possible_cpus->len == spapr_max_cores); 4275 return machine->possible_cpus; 4276 } 4277 4278 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4279 if (!core_type) { 4280 error_report("Unable to find sPAPR CPU Core definition"); 4281 exit(1); 4282 } 4283 4284 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4285 sizeof(CPUArchId) * spapr_max_cores); 4286 machine->possible_cpus->len = spapr_max_cores; 4287 for (i = 0; i < machine->possible_cpus->len; i++) { 4288 int core_id = i * smp_threads; 4289 4290 machine->possible_cpus->cpus[i].type = core_type; 4291 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4292 machine->possible_cpus->cpus[i].arch_id = core_id; 4293 machine->possible_cpus->cpus[i].props.has_core_id = true; 4294 machine->possible_cpus->cpus[i].props.core_id = core_id; 4295 } 4296 return machine->possible_cpus; 4297 } 4298 4299 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4300 uint64_t *buid, hwaddr *pio, 4301 hwaddr *mmio32, hwaddr *mmio64, 4302 unsigned n_dma, uint32_t *liobns, 4303 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4304 { 4305 /* 4306 * New-style PHB window placement. 4307 * 4308 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4309 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4310 * windows. 4311 * 4312 * Some guest kernels can't work with MMIO windows above 1<<46 4313 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4314 * 4315 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4316 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4317 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4318 * 1TiB 64-bit MMIO windows for each PHB. 4319 */ 4320 const uint64_t base_buid = 0x800000020000000ULL; 4321 int i; 4322 4323 /* Sanity check natural alignments */ 4324 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4325 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4326 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4327 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4328 /* Sanity check bounds */ 4329 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4330 SPAPR_PCI_MEM32_WIN_SIZE); 4331 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4332 SPAPR_PCI_MEM64_WIN_SIZE); 4333 4334 if (index >= SPAPR_MAX_PHBS) { 4335 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4336 SPAPR_MAX_PHBS - 1); 4337 return false; 4338 } 4339 4340 *buid = base_buid + index; 4341 for (i = 0; i < n_dma; ++i) { 4342 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4343 } 4344 4345 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4346 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4347 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4348 4349 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4350 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4351 return true; 4352 } 4353 4354 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4355 { 4356 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4357 4358 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4359 } 4360 4361 static void spapr_ics_resend(XICSFabric *dev) 4362 { 4363 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4364 4365 ics_resend(spapr->ics); 4366 } 4367 4368 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4369 { 4370 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4371 4372 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4373 } 4374 4375 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4376 Monitor *mon) 4377 { 4378 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4379 4380 spapr_irq_print_info(spapr, mon); 4381 monitor_printf(mon, "irqchip: %s\n", 4382 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4383 } 4384 4385 /* 4386 * This is a XIVE only operation 4387 */ 4388 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4389 uint8_t nvt_blk, uint32_t nvt_idx, 4390 bool cam_ignore, uint8_t priority, 4391 uint32_t logic_serv, XiveTCTXMatch *match) 4392 { 4393 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4394 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4395 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4396 int count; 4397 4398 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4399 priority, logic_serv, match); 4400 if (count < 0) { 4401 return count; 4402 } 4403 4404 /* 4405 * When we implement the save and restore of the thread interrupt 4406 * contexts in the enter/exit CPU handlers of the machine and the 4407 * escalations in QEMU, we should be able to handle non dispatched 4408 * vCPUs. 4409 * 4410 * Until this is done, the sPAPR machine should find at least one 4411 * matching context always. 4412 */ 4413 if (count == 0) { 4414 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4415 nvt_blk, nvt_idx); 4416 } 4417 4418 return count; 4419 } 4420 4421 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4422 { 4423 return cpu->vcpu_id; 4424 } 4425 4426 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4427 { 4428 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4429 MachineState *ms = MACHINE(spapr); 4430 int vcpu_id; 4431 4432 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4433 4434 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4435 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4436 error_append_hint(errp, "Adjust the number of cpus to %d " 4437 "or try to raise the number of threads per core\n", 4438 vcpu_id * ms->smp.threads / spapr->vsmt); 4439 return false; 4440 } 4441 4442 cpu->vcpu_id = vcpu_id; 4443 return true; 4444 } 4445 4446 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4447 { 4448 CPUState *cs; 4449 4450 CPU_FOREACH(cs) { 4451 PowerPCCPU *cpu = POWERPC_CPU(cs); 4452 4453 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4454 return cpu; 4455 } 4456 } 4457 4458 return NULL; 4459 } 4460 4461 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4462 { 4463 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4464 4465 /* These are only called by TCG, KVM maintains dispatch state */ 4466 4467 spapr_cpu->prod = false; 4468 if (spapr_cpu->vpa_addr) { 4469 CPUState *cs = CPU(cpu); 4470 uint32_t dispatch; 4471 4472 dispatch = ldl_be_phys(cs->as, 4473 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4474 dispatch++; 4475 if ((dispatch & 1) != 0) { 4476 qemu_log_mask(LOG_GUEST_ERROR, 4477 "VPA: incorrect dispatch counter value for " 4478 "dispatched partition %u, correcting.\n", dispatch); 4479 dispatch++; 4480 } 4481 stl_be_phys(cs->as, 4482 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4483 } 4484 } 4485 4486 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4487 { 4488 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4489 4490 if (spapr_cpu->vpa_addr) { 4491 CPUState *cs = CPU(cpu); 4492 uint32_t dispatch; 4493 4494 dispatch = ldl_be_phys(cs->as, 4495 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4496 dispatch++; 4497 if ((dispatch & 1) != 1) { 4498 qemu_log_mask(LOG_GUEST_ERROR, 4499 "VPA: incorrect dispatch counter value for " 4500 "preempted partition %u, correcting.\n", dispatch); 4501 dispatch++; 4502 } 4503 stl_be_phys(cs->as, 4504 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4505 } 4506 } 4507 4508 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4509 { 4510 MachineClass *mc = MACHINE_CLASS(oc); 4511 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4512 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4513 NMIClass *nc = NMI_CLASS(oc); 4514 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4515 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4516 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4517 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4518 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4519 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); 4520 4521 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4522 mc->ignore_boot_device_suffixes = true; 4523 4524 /* 4525 * We set up the default / latest behaviour here. The class_init 4526 * functions for the specific versioned machine types can override 4527 * these details for backwards compatibility 4528 */ 4529 mc->init = spapr_machine_init; 4530 mc->reset = spapr_machine_reset; 4531 mc->block_default_type = IF_SCSI; 4532 4533 /* 4534 * Setting max_cpus to INT32_MAX. Both KVM and TCG max_cpus values 4535 * should be limited by the host capability instead of hardcoded. 4536 * max_cpus for KVM guests will be checked in kvm_init(), and TCG 4537 * guests are welcome to have as many CPUs as the host are capable 4538 * of emulate. 4539 */ 4540 mc->max_cpus = INT32_MAX; 4541 4542 mc->no_parallel = 1; 4543 mc->default_boot_order = ""; 4544 mc->default_ram_size = 512 * MiB; 4545 mc->default_ram_id = "ppc_spapr.ram"; 4546 mc->default_display = "std"; 4547 mc->kvm_type = spapr_kvm_type; 4548 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4549 mc->pci_allow_0_address = true; 4550 assert(!mc->get_hotplug_handler); 4551 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4552 hc->pre_plug = spapr_machine_device_pre_plug; 4553 hc->plug = spapr_machine_device_plug; 4554 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4555 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4556 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4557 hc->unplug_request = spapr_machine_device_unplug_request; 4558 hc->unplug = spapr_machine_device_unplug; 4559 4560 smc->dr_lmb_enabled = true; 4561 smc->update_dt_enabled = true; 4562 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4563 mc->has_hotpluggable_cpus = true; 4564 mc->nvdimm_supported = true; 4565 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4566 fwc->get_dev_path = spapr_get_fw_dev_path; 4567 nc->nmi_monitor_handler = spapr_nmi; 4568 smc->phb_placement = spapr_phb_placement; 4569 vhc->hypercall = emulate_spapr_hypercall; 4570 vhc->hpt_mask = spapr_hpt_mask; 4571 vhc->map_hptes = spapr_map_hptes; 4572 vhc->unmap_hptes = spapr_unmap_hptes; 4573 vhc->hpte_set_c = spapr_hpte_set_c; 4574 vhc->hpte_set_r = spapr_hpte_set_r; 4575 vhc->get_pate = spapr_get_pate; 4576 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4577 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4578 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4579 xic->ics_get = spapr_ics_get; 4580 xic->ics_resend = spapr_ics_resend; 4581 xic->icp_get = spapr_icp_get; 4582 ispc->print_info = spapr_pic_print_info; 4583 /* Force NUMA node memory size to be a multiple of 4584 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4585 * in which LMBs are represented and hot-added 4586 */ 4587 mc->numa_mem_align_shift = 28; 4588 mc->auto_enable_numa = true; 4589 4590 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4591 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4592 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4593 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4594 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4595 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4596 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4597 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4598 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4599 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4600 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4601 smc->default_caps.caps[SPAPR_CAP_RPT_INVALIDATE] = SPAPR_CAP_OFF; 4602 spapr_caps_add_properties(smc); 4603 smc->irq = &spapr_irq_dual; 4604 smc->dr_phb_enabled = true; 4605 smc->linux_pci_probe = true; 4606 smc->smp_threads_vsmt = true; 4607 smc->nr_xirqs = SPAPR_NR_XIRQS; 4608 xfc->match_nvt = spapr_match_nvt; 4609 vmc->client_architecture_support = spapr_vof_client_architecture_support; 4610 vmc->quiesce = spapr_vof_quiesce; 4611 vmc->setprop = spapr_vof_setprop; 4612 } 4613 4614 static const TypeInfo spapr_machine_info = { 4615 .name = TYPE_SPAPR_MACHINE, 4616 .parent = TYPE_MACHINE, 4617 .abstract = true, 4618 .instance_size = sizeof(SpaprMachineState), 4619 .instance_init = spapr_instance_init, 4620 .instance_finalize = spapr_machine_finalizefn, 4621 .class_size = sizeof(SpaprMachineClass), 4622 .class_init = spapr_machine_class_init, 4623 .interfaces = (InterfaceInfo[]) { 4624 { TYPE_FW_PATH_PROVIDER }, 4625 { TYPE_NMI }, 4626 { TYPE_HOTPLUG_HANDLER }, 4627 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4628 { TYPE_XICS_FABRIC }, 4629 { TYPE_INTERRUPT_STATS_PROVIDER }, 4630 { TYPE_XIVE_FABRIC }, 4631 { TYPE_VOF_MACHINE_IF }, 4632 { } 4633 }, 4634 }; 4635 4636 static void spapr_machine_latest_class_options(MachineClass *mc) 4637 { 4638 mc->alias = "pseries"; 4639 mc->is_default = true; 4640 } 4641 4642 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4643 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4644 void *data) \ 4645 { \ 4646 MachineClass *mc = MACHINE_CLASS(oc); \ 4647 spapr_machine_##suffix##_class_options(mc); \ 4648 if (latest) { \ 4649 spapr_machine_latest_class_options(mc); \ 4650 } \ 4651 } \ 4652 static const TypeInfo spapr_machine_##suffix##_info = { \ 4653 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4654 .parent = TYPE_SPAPR_MACHINE, \ 4655 .class_init = spapr_machine_##suffix##_class_init, \ 4656 }; \ 4657 static void spapr_machine_register_##suffix(void) \ 4658 { \ 4659 type_register(&spapr_machine_##suffix##_info); \ 4660 } \ 4661 type_init(spapr_machine_register_##suffix) 4662 4663 /* 4664 * pseries-6.2 4665 */ 4666 static void spapr_machine_6_2_class_options(MachineClass *mc) 4667 { 4668 /* Defaults for the latest behaviour inherited from the base class */ 4669 } 4670 4671 DEFINE_SPAPR_MACHINE(6_2, "6.2", true); 4672 4673 /* 4674 * pseries-6.1 4675 */ 4676 static void spapr_machine_6_1_class_options(MachineClass *mc) 4677 { 4678 spapr_machine_6_2_class_options(mc); 4679 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 4680 } 4681 4682 DEFINE_SPAPR_MACHINE(6_1, "6.1", false); 4683 4684 /* 4685 * pseries-6.0 4686 */ 4687 static void spapr_machine_6_0_class_options(MachineClass *mc) 4688 { 4689 spapr_machine_6_1_class_options(mc); 4690 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 4691 } 4692 4693 DEFINE_SPAPR_MACHINE(6_0, "6.0", false); 4694 4695 /* 4696 * pseries-5.2 4697 */ 4698 static void spapr_machine_5_2_class_options(MachineClass *mc) 4699 { 4700 spapr_machine_6_0_class_options(mc); 4701 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4702 } 4703 4704 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4705 4706 /* 4707 * pseries-5.1 4708 */ 4709 static void spapr_machine_5_1_class_options(MachineClass *mc) 4710 { 4711 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4712 4713 spapr_machine_5_2_class_options(mc); 4714 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4715 smc->pre_5_2_numa_associativity = true; 4716 } 4717 4718 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4719 4720 /* 4721 * pseries-5.0 4722 */ 4723 static void spapr_machine_5_0_class_options(MachineClass *mc) 4724 { 4725 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4726 static GlobalProperty compat[] = { 4727 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4728 }; 4729 4730 spapr_machine_5_1_class_options(mc); 4731 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4732 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4733 mc->numa_mem_supported = true; 4734 smc->pre_5_1_assoc_refpoints = true; 4735 } 4736 4737 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4738 4739 /* 4740 * pseries-4.2 4741 */ 4742 static void spapr_machine_4_2_class_options(MachineClass *mc) 4743 { 4744 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4745 4746 spapr_machine_5_0_class_options(mc); 4747 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4748 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4749 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4750 smc->rma_limit = 16 * GiB; 4751 mc->nvdimm_supported = false; 4752 } 4753 4754 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4755 4756 /* 4757 * pseries-4.1 4758 */ 4759 static void spapr_machine_4_1_class_options(MachineClass *mc) 4760 { 4761 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4762 static GlobalProperty compat[] = { 4763 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4764 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4765 }; 4766 4767 spapr_machine_4_2_class_options(mc); 4768 smc->linux_pci_probe = false; 4769 smc->smp_threads_vsmt = false; 4770 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4771 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4772 } 4773 4774 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4775 4776 /* 4777 * pseries-4.0 4778 */ 4779 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4780 uint64_t *buid, hwaddr *pio, 4781 hwaddr *mmio32, hwaddr *mmio64, 4782 unsigned n_dma, uint32_t *liobns, 4783 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4784 { 4785 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 4786 liobns, nv2gpa, nv2atsd, errp)) { 4787 return false; 4788 } 4789 4790 *nv2gpa = 0; 4791 *nv2atsd = 0; 4792 return true; 4793 } 4794 static void spapr_machine_4_0_class_options(MachineClass *mc) 4795 { 4796 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4797 4798 spapr_machine_4_1_class_options(mc); 4799 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4800 smc->phb_placement = phb_placement_4_0; 4801 smc->irq = &spapr_irq_xics; 4802 smc->pre_4_1_migration = true; 4803 } 4804 4805 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4806 4807 /* 4808 * pseries-3.1 4809 */ 4810 static void spapr_machine_3_1_class_options(MachineClass *mc) 4811 { 4812 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4813 4814 spapr_machine_4_0_class_options(mc); 4815 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4816 4817 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4818 smc->update_dt_enabled = false; 4819 smc->dr_phb_enabled = false; 4820 smc->broken_host_serial_model = true; 4821 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4822 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4823 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4824 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4825 } 4826 4827 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4828 4829 /* 4830 * pseries-3.0 4831 */ 4832 4833 static void spapr_machine_3_0_class_options(MachineClass *mc) 4834 { 4835 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4836 4837 spapr_machine_3_1_class_options(mc); 4838 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4839 4840 smc->legacy_irq_allocation = true; 4841 smc->nr_xirqs = 0x400; 4842 smc->irq = &spapr_irq_xics_legacy; 4843 } 4844 4845 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4846 4847 /* 4848 * pseries-2.12 4849 */ 4850 static void spapr_machine_2_12_class_options(MachineClass *mc) 4851 { 4852 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4853 static GlobalProperty compat[] = { 4854 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4855 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4856 }; 4857 4858 spapr_machine_3_0_class_options(mc); 4859 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4860 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4861 4862 /* We depend on kvm_enabled() to choose a default value for the 4863 * hpt-max-page-size capability. Of course we can't do it here 4864 * because this is too early and the HW accelerator isn't initialzed 4865 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4866 */ 4867 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4868 } 4869 4870 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4871 4872 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4873 { 4874 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4875 4876 spapr_machine_2_12_class_options(mc); 4877 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4878 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4879 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4880 } 4881 4882 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4883 4884 /* 4885 * pseries-2.11 4886 */ 4887 4888 static void spapr_machine_2_11_class_options(MachineClass *mc) 4889 { 4890 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4891 4892 spapr_machine_2_12_class_options(mc); 4893 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4894 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4895 } 4896 4897 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4898 4899 /* 4900 * pseries-2.10 4901 */ 4902 4903 static void spapr_machine_2_10_class_options(MachineClass *mc) 4904 { 4905 spapr_machine_2_11_class_options(mc); 4906 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4907 } 4908 4909 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4910 4911 /* 4912 * pseries-2.9 4913 */ 4914 4915 static void spapr_machine_2_9_class_options(MachineClass *mc) 4916 { 4917 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4918 static GlobalProperty compat[] = { 4919 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4920 }; 4921 4922 spapr_machine_2_10_class_options(mc); 4923 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4924 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4925 smc->pre_2_10_has_unused_icps = true; 4926 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4927 } 4928 4929 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4930 4931 /* 4932 * pseries-2.8 4933 */ 4934 4935 static void spapr_machine_2_8_class_options(MachineClass *mc) 4936 { 4937 static GlobalProperty compat[] = { 4938 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4939 }; 4940 4941 spapr_machine_2_9_class_options(mc); 4942 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4943 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4944 mc->numa_mem_align_shift = 23; 4945 } 4946 4947 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4948 4949 /* 4950 * pseries-2.7 4951 */ 4952 4953 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4954 uint64_t *buid, hwaddr *pio, 4955 hwaddr *mmio32, hwaddr *mmio64, 4956 unsigned n_dma, uint32_t *liobns, 4957 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4958 { 4959 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4960 const uint64_t base_buid = 0x800000020000000ULL; 4961 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4962 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4963 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4964 const uint32_t max_index = 255; 4965 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4966 4967 uint64_t ram_top = MACHINE(spapr)->ram_size; 4968 hwaddr phb0_base, phb_base; 4969 int i; 4970 4971 /* Do we have device memory? */ 4972 if (MACHINE(spapr)->maxram_size > ram_top) { 4973 /* Can't just use maxram_size, because there may be an 4974 * alignment gap between normal and device memory regions 4975 */ 4976 ram_top = MACHINE(spapr)->device_memory->base + 4977 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4978 } 4979 4980 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4981 4982 if (index > max_index) { 4983 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4984 max_index); 4985 return false; 4986 } 4987 4988 *buid = base_buid + index; 4989 for (i = 0; i < n_dma; ++i) { 4990 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4991 } 4992 4993 phb_base = phb0_base + index * phb_spacing; 4994 *pio = phb_base + pio_offset; 4995 *mmio32 = phb_base + mmio_offset; 4996 /* 4997 * We don't set the 64-bit MMIO window, relying on the PHB's 4998 * fallback behaviour of automatically splitting a large "32-bit" 4999 * window into contiguous 32-bit and 64-bit windows 5000 */ 5001 5002 *nv2gpa = 0; 5003 *nv2atsd = 0; 5004 return true; 5005 } 5006 5007 static void spapr_machine_2_7_class_options(MachineClass *mc) 5008 { 5009 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5010 static GlobalProperty compat[] = { 5011 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 5012 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 5013 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 5014 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 5015 }; 5016 5017 spapr_machine_2_8_class_options(mc); 5018 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 5019 mc->default_machine_opts = "modern-hotplug-events=off"; 5020 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 5021 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5022 smc->phb_placement = phb_placement_2_7; 5023 } 5024 5025 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 5026 5027 /* 5028 * pseries-2.6 5029 */ 5030 5031 static void spapr_machine_2_6_class_options(MachineClass *mc) 5032 { 5033 static GlobalProperty compat[] = { 5034 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 5035 }; 5036 5037 spapr_machine_2_7_class_options(mc); 5038 mc->has_hotpluggable_cpus = false; 5039 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 5040 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5041 } 5042 5043 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 5044 5045 /* 5046 * pseries-2.5 5047 */ 5048 5049 static void spapr_machine_2_5_class_options(MachineClass *mc) 5050 { 5051 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5052 static GlobalProperty compat[] = { 5053 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 5054 }; 5055 5056 spapr_machine_2_6_class_options(mc); 5057 smc->use_ohci_by_default = true; 5058 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 5059 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5060 } 5061 5062 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 5063 5064 /* 5065 * pseries-2.4 5066 */ 5067 5068 static void spapr_machine_2_4_class_options(MachineClass *mc) 5069 { 5070 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5071 5072 spapr_machine_2_5_class_options(mc); 5073 smc->dr_lmb_enabled = false; 5074 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 5075 } 5076 5077 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 5078 5079 /* 5080 * pseries-2.3 5081 */ 5082 5083 static void spapr_machine_2_3_class_options(MachineClass *mc) 5084 { 5085 static GlobalProperty compat[] = { 5086 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 5087 }; 5088 spapr_machine_2_4_class_options(mc); 5089 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 5090 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5091 } 5092 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 5093 5094 /* 5095 * pseries-2.2 5096 */ 5097 5098 static void spapr_machine_2_2_class_options(MachineClass *mc) 5099 { 5100 static GlobalProperty compat[] = { 5101 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 5102 }; 5103 5104 spapr_machine_2_3_class_options(mc); 5105 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 5106 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5107 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 5108 } 5109 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 5110 5111 /* 5112 * pseries-2.1 5113 */ 5114 5115 static void spapr_machine_2_1_class_options(MachineClass *mc) 5116 { 5117 spapr_machine_2_2_class_options(mc); 5118 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 5119 } 5120 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 5121 5122 static void spapr_machine_register_types(void) 5123 { 5124 type_register_static(&spapr_machine_info); 5125 } 5126 5127 type_init(spapr_machine_register_types) 5128