1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/numa.h" 31 #include "hw/hw.h" 32 #include "qemu/log.h" 33 #include "hw/fw-path-provider.h" 34 #include "elf.h" 35 #include "net/net.h" 36 #include "sysemu/device_tree.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/misc.h" 42 #include "migration/global_state.h" 43 #include "migration/register.h" 44 #include "mmu-hash64.h" 45 #include "mmu-book3s-v3.h" 46 #include "qom/cpu.h" 47 48 #include "hw/boards.h" 49 #include "hw/ppc/ppc.h" 50 #include "hw/loader.h" 51 52 #include "hw/ppc/fdt.h" 53 #include "hw/ppc/spapr.h" 54 #include "hw/ppc/spapr_vio.h" 55 #include "hw/pci-host/spapr.h" 56 #include "hw/ppc/xics.h" 57 #include "hw/pci/msi.h" 58 59 #include "hw/pci/pci.h" 60 #include "hw/scsi/scsi.h" 61 #include "hw/virtio/virtio-scsi.h" 62 #include "hw/virtio/vhost-scsi-common.h" 63 64 #include "exec/address-spaces.h" 65 #include "hw/usb.h" 66 #include "qemu/config-file.h" 67 #include "qemu/error-report.h" 68 #include "trace.h" 69 #include "hw/nmi.h" 70 #include "hw/intc/intc.h" 71 72 #include "hw/compat.h" 73 #include "qemu/cutils.h" 74 #include "hw/ppc/spapr_cpu_core.h" 75 #include "qmp-commands.h" 76 77 #include <libfdt.h> 78 79 /* SLOF memory layout: 80 * 81 * SLOF raw image loaded at 0, copies its romfs right below the flat 82 * device-tree, then position SLOF itself 31M below that 83 * 84 * So we set FW_OVERHEAD to 40MB which should account for all of that 85 * and more 86 * 87 * We load our kernel at 4M, leaving space for SLOF initial image 88 */ 89 #define FDT_MAX_SIZE 0x100000 90 #define RTAS_MAX_SIZE 0x10000 91 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 92 #define FW_MAX_SIZE 0x400000 93 #define FW_FILE_NAME "slof.bin" 94 #define FW_OVERHEAD 0x2800000 95 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 96 97 #define MIN_RMA_SLOF 128UL 98 99 #define PHANDLE_XICP 0x00001111 100 101 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 102 103 static ICSState *spapr_ics_create(sPAPRMachineState *spapr, 104 const char *type_ics, 105 int nr_irqs, Error **errp) 106 { 107 Error *local_err = NULL; 108 Object *obj; 109 110 obj = object_new(type_ics); 111 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); 112 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), 113 &error_abort); 114 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); 115 if (local_err) { 116 goto error; 117 } 118 object_property_set_bool(obj, true, "realized", &local_err); 119 if (local_err) { 120 goto error; 121 } 122 123 return ICS_SIMPLE(obj); 124 125 error: 126 error_propagate(errp, local_err); 127 return NULL; 128 } 129 130 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 131 { 132 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 133 * and newer QEMUs don't even have them. In both cases, we don't want 134 * to send anything on the wire. 135 */ 136 return false; 137 } 138 139 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 140 .name = "icp/server", 141 .version_id = 1, 142 .minimum_version_id = 1, 143 .needed = pre_2_10_vmstate_dummy_icp_needed, 144 .fields = (VMStateField[]) { 145 VMSTATE_UNUSED(4), /* uint32_t xirr */ 146 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 147 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 148 VMSTATE_END_OF_LIST() 149 }, 150 }; 151 152 static void pre_2_10_vmstate_register_dummy_icp(int i) 153 { 154 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 155 (void *)(uintptr_t) i); 156 } 157 158 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 159 { 160 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 161 (void *)(uintptr_t) i); 162 } 163 164 static inline int xics_max_server_number(void) 165 { 166 return DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), smp_threads); 167 } 168 169 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) 170 { 171 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 172 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 173 174 if (kvm_enabled()) { 175 if (machine_kernel_irqchip_allowed(machine) && 176 !xics_kvm_init(spapr, errp)) { 177 spapr->icp_type = TYPE_KVM_ICP; 178 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp); 179 } 180 if (machine_kernel_irqchip_required(machine) && !spapr->ics) { 181 error_prepend(errp, "kernel_irqchip requested but unavailable: "); 182 return; 183 } 184 } 185 186 if (!spapr->ics) { 187 xics_spapr_init(spapr); 188 spapr->icp_type = TYPE_ICP; 189 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp); 190 if (!spapr->ics) { 191 return; 192 } 193 } 194 195 if (smc->pre_2_10_has_unused_icps) { 196 int i; 197 198 for (i = 0; i < xics_max_server_number(); i++) { 199 /* Dummy entries get deregistered when real ICPState objects 200 * are registered during CPU core hotplug. 201 */ 202 pre_2_10_vmstate_register_dummy_icp(i); 203 } 204 } 205 } 206 207 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 208 int smt_threads) 209 { 210 int i, ret = 0; 211 uint32_t servers_prop[smt_threads]; 212 uint32_t gservers_prop[smt_threads * 2]; 213 int index = ppc_get_vcpu_dt_id(cpu); 214 215 if (cpu->compat_pvr) { 216 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 217 if (ret < 0) { 218 return ret; 219 } 220 } 221 222 /* Build interrupt servers and gservers properties */ 223 for (i = 0; i < smt_threads; i++) { 224 servers_prop[i] = cpu_to_be32(index + i); 225 /* Hack, direct the group queues back to cpu 0 */ 226 gservers_prop[i*2] = cpu_to_be32(index + i); 227 gservers_prop[i*2 + 1] = 0; 228 } 229 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 230 servers_prop, sizeof(servers_prop)); 231 if (ret < 0) { 232 return ret; 233 } 234 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 235 gservers_prop, sizeof(gservers_prop)); 236 237 return ret; 238 } 239 240 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 241 { 242 int index = ppc_get_vcpu_dt_id(cpu); 243 uint32_t associativity[] = {cpu_to_be32(0x5), 244 cpu_to_be32(0x0), 245 cpu_to_be32(0x0), 246 cpu_to_be32(0x0), 247 cpu_to_be32(cpu->node_id), 248 cpu_to_be32(index)}; 249 250 /* Advertise NUMA via ibm,associativity */ 251 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 252 sizeof(associativity)); 253 } 254 255 /* Populate the "ibm,pa-features" property */ 256 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset, 257 bool legacy_guest) 258 { 259 uint8_t pa_features_206[] = { 6, 0, 260 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 261 uint8_t pa_features_207[] = { 24, 0, 262 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 263 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 264 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 265 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 266 uint8_t pa_features_300[] = { 66, 0, 267 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 268 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 269 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 270 /* 6: DS207 */ 271 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 272 /* 16: Vector */ 273 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 274 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 275 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 276 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 277 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 278 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 279 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 280 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 281 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 282 /* 42: PM, 44: PC RA, 46: SC vec'd */ 283 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 284 /* 48: SIMD, 50: QP BFP, 52: String */ 285 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 286 /* 54: DecFP, 56: DecI, 58: SHA */ 287 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 288 /* 60: NM atomic, 62: RNG */ 289 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 290 }; 291 uint8_t *pa_features; 292 size_t pa_size; 293 294 switch (POWERPC_MMU_VER(env->mmu_model)) { 295 case POWERPC_MMU_VER_2_06: 296 pa_features = pa_features_206; 297 pa_size = sizeof(pa_features_206); 298 break; 299 case POWERPC_MMU_VER_2_07: 300 pa_features = pa_features_207; 301 pa_size = sizeof(pa_features_207); 302 break; 303 case POWERPC_MMU_VER_3_00: 304 pa_features = pa_features_300; 305 pa_size = sizeof(pa_features_300); 306 break; 307 default: 308 return; 309 } 310 311 if (env->ci_large_pages) { 312 /* 313 * Note: we keep CI large pages off by default because a 64K capable 314 * guest provisioned with large pages might otherwise try to map a qemu 315 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 316 * even if that qemu runs on a 4k host. 317 * We dd this bit back here if we are confident this is not an issue 318 */ 319 pa_features[3] |= 0x20; 320 } 321 if (kvmppc_has_cap_htm() && pa_size > 24) { 322 pa_features[24] |= 0x80; /* Transactional memory support */ 323 } 324 if (legacy_guest && pa_size > 40) { 325 /* Workaround for broken kernels that attempt (guest) radix 326 * mode when they can't handle it, if they see the radix bit set 327 * in pa-features. So hide it from them. */ 328 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 329 } 330 331 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 332 } 333 334 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 335 { 336 int ret = 0, offset, cpus_offset; 337 CPUState *cs; 338 char cpu_model[32]; 339 int smt = kvmppc_smt_threads(); 340 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 341 342 CPU_FOREACH(cs) { 343 PowerPCCPU *cpu = POWERPC_CPU(cs); 344 CPUPPCState *env = &cpu->env; 345 DeviceClass *dc = DEVICE_GET_CLASS(cs); 346 int index = ppc_get_vcpu_dt_id(cpu); 347 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 348 349 if ((index % smt) != 0) { 350 continue; 351 } 352 353 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 354 355 cpus_offset = fdt_path_offset(fdt, "/cpus"); 356 if (cpus_offset < 0) { 357 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 358 "cpus"); 359 if (cpus_offset < 0) { 360 return cpus_offset; 361 } 362 } 363 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 364 if (offset < 0) { 365 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 366 if (offset < 0) { 367 return offset; 368 } 369 } 370 371 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 372 pft_size_prop, sizeof(pft_size_prop)); 373 if (ret < 0) { 374 return ret; 375 } 376 377 if (nb_numa_nodes > 1) { 378 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 379 if (ret < 0) { 380 return ret; 381 } 382 } 383 384 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 385 if (ret < 0) { 386 return ret; 387 } 388 389 spapr_populate_pa_features(env, fdt, offset, 390 spapr->cas_legacy_guest_workaround); 391 } 392 return ret; 393 } 394 395 static hwaddr spapr_node0_size(void) 396 { 397 MachineState *machine = MACHINE(qdev_get_machine()); 398 399 if (nb_numa_nodes) { 400 int i; 401 for (i = 0; i < nb_numa_nodes; ++i) { 402 if (numa_info[i].node_mem) { 403 return MIN(pow2floor(numa_info[i].node_mem), 404 machine->ram_size); 405 } 406 } 407 } 408 return machine->ram_size; 409 } 410 411 static void add_str(GString *s, const gchar *s1) 412 { 413 g_string_append_len(s, s1, strlen(s1) + 1); 414 } 415 416 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 417 hwaddr size) 418 { 419 uint32_t associativity[] = { 420 cpu_to_be32(0x4), /* length */ 421 cpu_to_be32(0x0), cpu_to_be32(0x0), 422 cpu_to_be32(0x0), cpu_to_be32(nodeid) 423 }; 424 char mem_name[32]; 425 uint64_t mem_reg_property[2]; 426 int off; 427 428 mem_reg_property[0] = cpu_to_be64(start); 429 mem_reg_property[1] = cpu_to_be64(size); 430 431 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 432 off = fdt_add_subnode(fdt, 0, mem_name); 433 _FDT(off); 434 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 435 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 436 sizeof(mem_reg_property)))); 437 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 438 sizeof(associativity)))); 439 return off; 440 } 441 442 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 443 { 444 MachineState *machine = MACHINE(spapr); 445 hwaddr mem_start, node_size; 446 int i, nb_nodes = nb_numa_nodes; 447 NodeInfo *nodes = numa_info; 448 NodeInfo ramnode; 449 450 /* No NUMA nodes, assume there is just one node with whole RAM */ 451 if (!nb_numa_nodes) { 452 nb_nodes = 1; 453 ramnode.node_mem = machine->ram_size; 454 nodes = &ramnode; 455 } 456 457 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 458 if (!nodes[i].node_mem) { 459 continue; 460 } 461 if (mem_start >= machine->ram_size) { 462 node_size = 0; 463 } else { 464 node_size = nodes[i].node_mem; 465 if (node_size > machine->ram_size - mem_start) { 466 node_size = machine->ram_size - mem_start; 467 } 468 } 469 if (!mem_start) { 470 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 471 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 472 mem_start += spapr->rma_size; 473 node_size -= spapr->rma_size; 474 } 475 for ( ; node_size; ) { 476 hwaddr sizetmp = pow2floor(node_size); 477 478 /* mem_start != 0 here */ 479 if (ctzl(mem_start) < ctzl(sizetmp)) { 480 sizetmp = 1ULL << ctzl(mem_start); 481 } 482 483 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 484 node_size -= sizetmp; 485 mem_start += sizetmp; 486 } 487 } 488 489 return 0; 490 } 491 492 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 493 sPAPRMachineState *spapr) 494 { 495 PowerPCCPU *cpu = POWERPC_CPU(cs); 496 CPUPPCState *env = &cpu->env; 497 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 498 int index = ppc_get_vcpu_dt_id(cpu); 499 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 500 0xffffffff, 0xffffffff}; 501 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 502 : SPAPR_TIMEBASE_FREQ; 503 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 504 uint32_t page_sizes_prop[64]; 505 size_t page_sizes_prop_size; 506 uint32_t vcpus_per_socket = smp_threads * smp_cores; 507 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 508 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 509 sPAPRDRConnector *drc; 510 int drc_index; 511 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 512 int i; 513 514 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 515 if (drc) { 516 drc_index = spapr_drc_index(drc); 517 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 518 } 519 520 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 521 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 522 523 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 524 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 525 env->dcache_line_size))); 526 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 527 env->dcache_line_size))); 528 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 529 env->icache_line_size))); 530 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 531 env->icache_line_size))); 532 533 if (pcc->l1_dcache_size) { 534 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 535 pcc->l1_dcache_size))); 536 } else { 537 error_report("Warning: Unknown L1 dcache size for cpu"); 538 } 539 if (pcc->l1_icache_size) { 540 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 541 pcc->l1_icache_size))); 542 } else { 543 error_report("Warning: Unknown L1 icache size for cpu"); 544 } 545 546 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 547 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 548 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 549 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 550 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 551 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 552 553 if (env->spr_cb[SPR_PURR].oea_read) { 554 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 555 } 556 557 if (env->mmu_model & POWERPC_MMU_1TSEG) { 558 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 559 segs, sizeof(segs)))); 560 } 561 562 /* Advertise VMX/VSX (vector extensions) if available 563 * 0 / no property == no vector extensions 564 * 1 == VMX / Altivec available 565 * 2 == VSX available */ 566 if (env->insns_flags & PPC_ALTIVEC) { 567 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 568 569 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 570 } 571 572 /* Advertise DFP (Decimal Floating Point) if available 573 * 0 / no property == no DFP 574 * 1 == DFP available */ 575 if (env->insns_flags2 & PPC2_DFP) { 576 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 577 } 578 579 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 580 sizeof(page_sizes_prop)); 581 if (page_sizes_prop_size) { 582 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 583 page_sizes_prop, page_sizes_prop_size))); 584 } 585 586 spapr_populate_pa_features(env, fdt, offset, false); 587 588 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 589 cs->cpu_index / vcpus_per_socket))); 590 591 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 592 pft_size_prop, sizeof(pft_size_prop)))); 593 594 if (nb_numa_nodes > 1) { 595 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 596 } 597 598 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 599 600 if (pcc->radix_page_info) { 601 for (i = 0; i < pcc->radix_page_info->count; i++) { 602 radix_AP_encodings[i] = 603 cpu_to_be32(pcc->radix_page_info->entries[i]); 604 } 605 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 606 radix_AP_encodings, 607 pcc->radix_page_info->count * 608 sizeof(radix_AP_encodings[0])))); 609 } 610 } 611 612 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 613 { 614 CPUState *cs; 615 int cpus_offset; 616 char *nodename; 617 int smt = kvmppc_smt_threads(); 618 619 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 620 _FDT(cpus_offset); 621 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 622 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 623 624 /* 625 * We walk the CPUs in reverse order to ensure that CPU DT nodes 626 * created by fdt_add_subnode() end up in the right order in FDT 627 * for the guest kernel the enumerate the CPUs correctly. 628 */ 629 CPU_FOREACH_REVERSE(cs) { 630 PowerPCCPU *cpu = POWERPC_CPU(cs); 631 int index = ppc_get_vcpu_dt_id(cpu); 632 DeviceClass *dc = DEVICE_GET_CLASS(cs); 633 int offset; 634 635 if ((index % smt) != 0) { 636 continue; 637 } 638 639 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 640 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 641 g_free(nodename); 642 _FDT(offset); 643 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 644 } 645 646 } 647 648 /* 649 * Adds ibm,dynamic-reconfiguration-memory node. 650 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 651 * of this device tree node. 652 */ 653 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 654 { 655 MachineState *machine = MACHINE(spapr); 656 int ret, i, offset; 657 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 658 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 659 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 660 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 661 memory_region_size(&spapr->hotplug_memory.mr)) / 662 lmb_size; 663 uint32_t *int_buf, *cur_index, buf_len; 664 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 665 666 /* 667 * Don't create the node if there is no hotpluggable memory 668 */ 669 if (machine->ram_size == machine->maxram_size) { 670 return 0; 671 } 672 673 /* 674 * Allocate enough buffer size to fit in ibm,dynamic-memory 675 * or ibm,associativity-lookup-arrays 676 */ 677 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 678 * sizeof(uint32_t); 679 cur_index = int_buf = g_malloc0(buf_len); 680 681 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 682 683 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 684 sizeof(prop_lmb_size)); 685 if (ret < 0) { 686 goto out; 687 } 688 689 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 690 if (ret < 0) { 691 goto out; 692 } 693 694 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 695 if (ret < 0) { 696 goto out; 697 } 698 699 /* ibm,dynamic-memory */ 700 int_buf[0] = cpu_to_be32(nr_lmbs); 701 cur_index++; 702 for (i = 0; i < nr_lmbs; i++) { 703 uint64_t addr = i * lmb_size; 704 uint32_t *dynamic_memory = cur_index; 705 706 if (i >= hotplug_lmb_start) { 707 sPAPRDRConnector *drc; 708 709 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 710 g_assert(drc); 711 712 dynamic_memory[0] = cpu_to_be32(addr >> 32); 713 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 714 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 715 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 716 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 717 if (memory_region_present(get_system_memory(), addr)) { 718 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 719 } else { 720 dynamic_memory[5] = cpu_to_be32(0); 721 } 722 } else { 723 /* 724 * LMB information for RMA, boot time RAM and gap b/n RAM and 725 * hotplug memory region -- all these are marked as reserved 726 * and as having no valid DRC. 727 */ 728 dynamic_memory[0] = cpu_to_be32(addr >> 32); 729 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 730 dynamic_memory[2] = cpu_to_be32(0); 731 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 732 dynamic_memory[4] = cpu_to_be32(-1); 733 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 734 SPAPR_LMB_FLAGS_DRC_INVALID); 735 } 736 737 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 738 } 739 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 740 if (ret < 0) { 741 goto out; 742 } 743 744 /* ibm,associativity-lookup-arrays */ 745 cur_index = int_buf; 746 int_buf[0] = cpu_to_be32(nr_nodes); 747 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 748 cur_index += 2; 749 for (i = 0; i < nr_nodes; i++) { 750 uint32_t associativity[] = { 751 cpu_to_be32(0x0), 752 cpu_to_be32(0x0), 753 cpu_to_be32(0x0), 754 cpu_to_be32(i) 755 }; 756 memcpy(cur_index, associativity, sizeof(associativity)); 757 cur_index += 4; 758 } 759 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 760 (cur_index - int_buf) * sizeof(uint32_t)); 761 out: 762 g_free(int_buf); 763 return ret; 764 } 765 766 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 767 sPAPROptionVector *ov5_updates) 768 { 769 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 770 int ret = 0, offset; 771 772 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 773 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 774 g_assert(smc->dr_lmb_enabled); 775 ret = spapr_populate_drconf_memory(spapr, fdt); 776 if (ret) { 777 goto out; 778 } 779 } 780 781 offset = fdt_path_offset(fdt, "/chosen"); 782 if (offset < 0) { 783 offset = fdt_add_subnode(fdt, 0, "chosen"); 784 if (offset < 0) { 785 return offset; 786 } 787 } 788 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 789 "ibm,architecture-vec-5"); 790 791 out: 792 return ret; 793 } 794 795 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 796 target_ulong addr, target_ulong size, 797 sPAPROptionVector *ov5_updates) 798 { 799 void *fdt, *fdt_skel; 800 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 801 802 size -= sizeof(hdr); 803 804 /* Create sceleton */ 805 fdt_skel = g_malloc0(size); 806 _FDT((fdt_create(fdt_skel, size))); 807 _FDT((fdt_begin_node(fdt_skel, ""))); 808 _FDT((fdt_end_node(fdt_skel))); 809 _FDT((fdt_finish(fdt_skel))); 810 fdt = g_malloc0(size); 811 _FDT((fdt_open_into(fdt_skel, fdt, size))); 812 g_free(fdt_skel); 813 814 /* Fixup cpu nodes */ 815 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 816 817 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 818 return -1; 819 } 820 821 /* Pack resulting tree */ 822 _FDT((fdt_pack(fdt))); 823 824 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 825 trace_spapr_cas_failed(size); 826 return -1; 827 } 828 829 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 830 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 831 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 832 g_free(fdt); 833 834 return 0; 835 } 836 837 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 838 { 839 int rtas; 840 GString *hypertas = g_string_sized_new(256); 841 GString *qemu_hypertas = g_string_sized_new(256); 842 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 843 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 844 memory_region_size(&spapr->hotplug_memory.mr); 845 uint32_t lrdr_capacity[] = { 846 cpu_to_be32(max_hotplug_addr >> 32), 847 cpu_to_be32(max_hotplug_addr & 0xffffffff), 848 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 849 cpu_to_be32(max_cpus / smp_threads), 850 }; 851 852 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 853 854 /* hypertas */ 855 add_str(hypertas, "hcall-pft"); 856 add_str(hypertas, "hcall-term"); 857 add_str(hypertas, "hcall-dabr"); 858 add_str(hypertas, "hcall-interrupt"); 859 add_str(hypertas, "hcall-tce"); 860 add_str(hypertas, "hcall-vio"); 861 add_str(hypertas, "hcall-splpar"); 862 add_str(hypertas, "hcall-bulk"); 863 add_str(hypertas, "hcall-set-mode"); 864 add_str(hypertas, "hcall-sprg0"); 865 add_str(hypertas, "hcall-copy"); 866 add_str(hypertas, "hcall-debug"); 867 add_str(qemu_hypertas, "hcall-memop1"); 868 869 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 870 add_str(hypertas, "hcall-multi-tce"); 871 } 872 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 873 hypertas->str, hypertas->len)); 874 g_string_free(hypertas, TRUE); 875 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 876 qemu_hypertas->str, qemu_hypertas->len)); 877 g_string_free(qemu_hypertas, TRUE); 878 879 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 880 refpoints, sizeof(refpoints))); 881 882 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 883 RTAS_ERROR_LOG_MAX)); 884 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 885 RTAS_EVENT_SCAN_RATE)); 886 887 if (msi_nonbroken) { 888 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 889 } 890 891 /* 892 * According to PAPR, rtas ibm,os-term does not guarantee a return 893 * back to the guest cpu. 894 * 895 * While an additional ibm,extended-os-term property indicates 896 * that rtas call return will always occur. Set this property. 897 */ 898 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 899 900 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 901 lrdr_capacity, sizeof(lrdr_capacity))); 902 903 spapr_dt_rtas_tokens(fdt, rtas); 904 } 905 906 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features 907 * that the guest may request and thus the valid values for bytes 24..26 of 908 * option vector 5: */ 909 static void spapr_dt_ov5_platform_support(void *fdt, int chosen) 910 { 911 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 912 913 char val[2 * 3] = { 914 24, 0x00, /* Hash/Radix, filled in below. */ 915 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 916 26, 0x40, /* Radix options: GTSE == yes. */ 917 }; 918 919 if (kvm_enabled()) { 920 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 921 val[1] = 0x80; /* OV5_MMU_BOTH */ 922 } else if (kvmppc_has_cap_mmu_radix()) { 923 val[1] = 0x40; /* OV5_MMU_RADIX_300 */ 924 } else { 925 val[1] = 0x00; /* Hash */ 926 } 927 } else { 928 if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) { 929 /* V3 MMU supports both hash and radix (with dynamic switching) */ 930 val[1] = 0xC0; 931 } else { 932 /* Otherwise we can only do hash */ 933 val[1] = 0x00; 934 } 935 } 936 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 937 val, sizeof(val))); 938 } 939 940 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 941 { 942 MachineState *machine = MACHINE(spapr); 943 int chosen; 944 const char *boot_device = machine->boot_order; 945 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 946 size_t cb = 0; 947 char *bootlist = get_boot_devices_list(&cb, true); 948 949 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 950 951 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 952 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 953 spapr->initrd_base)); 954 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 955 spapr->initrd_base + spapr->initrd_size)); 956 957 if (spapr->kernel_size) { 958 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 959 cpu_to_be64(spapr->kernel_size) }; 960 961 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 962 &kprop, sizeof(kprop))); 963 if (spapr->kernel_le) { 964 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 965 } 966 } 967 if (boot_menu) { 968 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 969 } 970 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 971 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 972 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 973 974 if (cb && bootlist) { 975 int i; 976 977 for (i = 0; i < cb; i++) { 978 if (bootlist[i] == '\n') { 979 bootlist[i] = ' '; 980 } 981 } 982 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 983 } 984 985 if (boot_device && strlen(boot_device)) { 986 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 987 } 988 989 if (!spapr->has_graphics && stdout_path) { 990 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 991 } 992 993 spapr_dt_ov5_platform_support(fdt, chosen); 994 995 g_free(stdout_path); 996 g_free(bootlist); 997 } 998 999 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 1000 { 1001 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1002 * KVM to work under pHyp with some guest co-operation */ 1003 int hypervisor; 1004 uint8_t hypercall[16]; 1005 1006 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1007 /* indicate KVM hypercall interface */ 1008 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1009 if (kvmppc_has_cap_fixup_hcalls()) { 1010 /* 1011 * Older KVM versions with older guest kernels were broken 1012 * with the magic page, don't allow the guest to map it. 1013 */ 1014 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1015 sizeof(hypercall))) { 1016 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1017 hypercall, sizeof(hypercall))); 1018 } 1019 } 1020 } 1021 1022 static void *spapr_build_fdt(sPAPRMachineState *spapr, 1023 hwaddr rtas_addr, 1024 hwaddr rtas_size) 1025 { 1026 MachineState *machine = MACHINE(qdev_get_machine()); 1027 MachineClass *mc = MACHINE_GET_CLASS(machine); 1028 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1029 int ret; 1030 void *fdt; 1031 sPAPRPHBState *phb; 1032 char *buf; 1033 1034 fdt = g_malloc0(FDT_MAX_SIZE); 1035 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1036 1037 /* Root node */ 1038 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1039 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1040 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1041 1042 /* 1043 * Add info to guest to indentify which host is it being run on 1044 * and what is the uuid of the guest 1045 */ 1046 if (kvmppc_get_host_model(&buf)) { 1047 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1048 g_free(buf); 1049 } 1050 if (kvmppc_get_host_serial(&buf)) { 1051 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1052 g_free(buf); 1053 } 1054 1055 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1056 1057 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1058 if (qemu_uuid_set) { 1059 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1060 } 1061 g_free(buf); 1062 1063 if (qemu_get_vm_name()) { 1064 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1065 qemu_get_vm_name())); 1066 } 1067 1068 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1069 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1070 1071 /* /interrupt controller */ 1072 spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP); 1073 1074 ret = spapr_populate_memory(spapr, fdt); 1075 if (ret < 0) { 1076 error_report("couldn't setup memory nodes in fdt"); 1077 exit(1); 1078 } 1079 1080 /* /vdevice */ 1081 spapr_dt_vdevice(spapr->vio_bus, fdt); 1082 1083 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1084 ret = spapr_rng_populate_dt(fdt); 1085 if (ret < 0) { 1086 error_report("could not set up rng device in the fdt"); 1087 exit(1); 1088 } 1089 } 1090 1091 QLIST_FOREACH(phb, &spapr->phbs, list) { 1092 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 1093 if (ret < 0) { 1094 error_report("couldn't setup PCI devices in fdt"); 1095 exit(1); 1096 } 1097 } 1098 1099 /* cpus */ 1100 spapr_populate_cpus_dt_node(fdt, spapr); 1101 1102 if (smc->dr_lmb_enabled) { 1103 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1104 } 1105 1106 if (mc->has_hotpluggable_cpus) { 1107 int offset = fdt_path_offset(fdt, "/cpus"); 1108 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1109 SPAPR_DR_CONNECTOR_TYPE_CPU); 1110 if (ret < 0) { 1111 error_report("Couldn't set up CPU DR device tree properties"); 1112 exit(1); 1113 } 1114 } 1115 1116 /* /event-sources */ 1117 spapr_dt_events(spapr, fdt); 1118 1119 /* /rtas */ 1120 spapr_dt_rtas(spapr, fdt); 1121 1122 /* /chosen */ 1123 spapr_dt_chosen(spapr, fdt); 1124 1125 /* /hypervisor */ 1126 if (kvm_enabled()) { 1127 spapr_dt_hypervisor(spapr, fdt); 1128 } 1129 1130 /* Build memory reserve map */ 1131 if (spapr->kernel_size) { 1132 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1133 } 1134 if (spapr->initrd_size) { 1135 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1136 } 1137 1138 /* ibm,client-architecture-support updates */ 1139 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1140 if (ret < 0) { 1141 error_report("couldn't setup CAS properties fdt"); 1142 exit(1); 1143 } 1144 1145 return fdt; 1146 } 1147 1148 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1149 { 1150 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1151 } 1152 1153 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1154 PowerPCCPU *cpu) 1155 { 1156 CPUPPCState *env = &cpu->env; 1157 1158 /* The TCG path should also be holding the BQL at this point */ 1159 g_assert(qemu_mutex_iothread_locked()); 1160 1161 if (msr_pr) { 1162 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1163 env->gpr[3] = H_PRIVILEGE; 1164 } else { 1165 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1166 } 1167 } 1168 1169 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1170 { 1171 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1172 1173 return spapr->patb_entry; 1174 } 1175 1176 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1177 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1178 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1179 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1180 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1181 1182 /* 1183 * Get the fd to access the kernel htab, re-opening it if necessary 1184 */ 1185 static int get_htab_fd(sPAPRMachineState *spapr) 1186 { 1187 if (spapr->htab_fd >= 0) { 1188 return spapr->htab_fd; 1189 } 1190 1191 spapr->htab_fd = kvmppc_get_htab_fd(false); 1192 if (spapr->htab_fd < 0) { 1193 error_report("Unable to open fd for reading hash table from KVM: %s", 1194 strerror(errno)); 1195 } 1196 1197 return spapr->htab_fd; 1198 } 1199 1200 void close_htab_fd(sPAPRMachineState *spapr) 1201 { 1202 if (spapr->htab_fd >= 0) { 1203 close(spapr->htab_fd); 1204 } 1205 spapr->htab_fd = -1; 1206 } 1207 1208 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1209 { 1210 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1211 1212 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1213 } 1214 1215 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1216 hwaddr ptex, int n) 1217 { 1218 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1219 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1220 1221 if (!spapr->htab) { 1222 /* 1223 * HTAB is controlled by KVM. Fetch into temporary buffer 1224 */ 1225 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1226 kvmppc_read_hptes(hptes, ptex, n); 1227 return hptes; 1228 } 1229 1230 /* 1231 * HTAB is controlled by QEMU. Just point to the internally 1232 * accessible PTEG. 1233 */ 1234 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1235 } 1236 1237 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1238 const ppc_hash_pte64_t *hptes, 1239 hwaddr ptex, int n) 1240 { 1241 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1242 1243 if (!spapr->htab) { 1244 g_free((void *)hptes); 1245 } 1246 1247 /* Nothing to do for qemu managed HPT */ 1248 } 1249 1250 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1251 uint64_t pte0, uint64_t pte1) 1252 { 1253 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1254 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1255 1256 if (!spapr->htab) { 1257 kvmppc_write_hpte(ptex, pte0, pte1); 1258 } else { 1259 stq_p(spapr->htab + offset, pte0); 1260 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1261 } 1262 } 1263 1264 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1265 { 1266 int shift; 1267 1268 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1269 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1270 * that's much more than is needed for Linux guests */ 1271 shift = ctz64(pow2ceil(ramsize)) - 7; 1272 shift = MAX(shift, 18); /* Minimum architected size */ 1273 shift = MIN(shift, 46); /* Maximum architected size */ 1274 return shift; 1275 } 1276 1277 void spapr_free_hpt(sPAPRMachineState *spapr) 1278 { 1279 g_free(spapr->htab); 1280 spapr->htab = NULL; 1281 spapr->htab_shift = 0; 1282 close_htab_fd(spapr); 1283 } 1284 1285 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1286 Error **errp) 1287 { 1288 long rc; 1289 1290 /* Clean up any HPT info from a previous boot */ 1291 spapr_free_hpt(spapr); 1292 1293 rc = kvmppc_reset_htab(shift); 1294 if (rc < 0) { 1295 /* kernel-side HPT needed, but couldn't allocate one */ 1296 error_setg_errno(errp, errno, 1297 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1298 shift); 1299 /* This is almost certainly fatal, but if the caller really 1300 * wants to carry on with shift == 0, it's welcome to try */ 1301 } else if (rc > 0) { 1302 /* kernel-side HPT allocated */ 1303 if (rc != shift) { 1304 error_setg(errp, 1305 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1306 shift, rc); 1307 } 1308 1309 spapr->htab_shift = shift; 1310 spapr->htab = NULL; 1311 } else { 1312 /* kernel-side HPT not needed, allocate in userspace instead */ 1313 size_t size = 1ULL << shift; 1314 int i; 1315 1316 spapr->htab = qemu_memalign(size, size); 1317 if (!spapr->htab) { 1318 error_setg_errno(errp, errno, 1319 "Could not allocate HPT of order %d", shift); 1320 return; 1321 } 1322 1323 memset(spapr->htab, 0, size); 1324 spapr->htab_shift = shift; 1325 1326 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1327 DIRTY_HPTE(HPTE(spapr->htab, i)); 1328 } 1329 } 1330 } 1331 1332 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1333 { 1334 spapr_reallocate_hpt(spapr, 1335 spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size), 1336 &error_fatal); 1337 if (spapr->vrma_adjust) { 1338 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1339 spapr->htab_shift); 1340 } 1341 /* We're setting up a hash table, so that means we're not radix */ 1342 spapr->patb_entry = 0; 1343 } 1344 1345 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1346 { 1347 bool matched = false; 1348 1349 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1350 matched = true; 1351 } 1352 1353 if (!matched) { 1354 error_report("Device %s is not supported by this machine yet.", 1355 qdev_fw_name(DEVICE(sbdev))); 1356 exit(1); 1357 } 1358 } 1359 1360 static void ppc_spapr_reset(void) 1361 { 1362 MachineState *machine = MACHINE(qdev_get_machine()); 1363 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1364 PowerPCCPU *first_ppc_cpu; 1365 uint32_t rtas_limit; 1366 hwaddr rtas_addr, fdt_addr; 1367 void *fdt; 1368 int rc; 1369 1370 /* Check for unknown sysbus devices */ 1371 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1372 1373 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()) { 1374 /* If using KVM with radix mode available, VCPUs can be started 1375 * without a HPT because KVM will start them in radix mode. 1376 * Set the GR bit in PATB so that we know there is no HPT. */ 1377 spapr->patb_entry = PATBE1_GR; 1378 } else { 1379 spapr_setup_hpt_and_vrma(spapr); 1380 } 1381 1382 qemu_devices_reset(); 1383 1384 /* 1385 * We place the device tree and RTAS just below either the top of the RMA, 1386 * or just below 2GB, whichever is lowere, so that it can be 1387 * processed with 32-bit real mode code if necessary 1388 */ 1389 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1390 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1391 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1392 1393 /* if this reset wasn't generated by CAS, we should reset our 1394 * negotiated options and start from scratch */ 1395 if (!spapr->cas_reboot) { 1396 spapr_ovec_cleanup(spapr->ov5_cas); 1397 spapr->ov5_cas = spapr_ovec_new(); 1398 1399 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1400 } 1401 1402 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1403 1404 spapr_load_rtas(spapr, fdt, rtas_addr); 1405 1406 rc = fdt_pack(fdt); 1407 1408 /* Should only fail if we've built a corrupted tree */ 1409 assert(rc == 0); 1410 1411 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1412 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1413 fdt_totalsize(fdt), FDT_MAX_SIZE); 1414 exit(1); 1415 } 1416 1417 /* Load the fdt */ 1418 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1419 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1420 g_free(fdt); 1421 1422 /* Set up the entry state */ 1423 first_ppc_cpu = POWERPC_CPU(first_cpu); 1424 first_ppc_cpu->env.gpr[3] = fdt_addr; 1425 first_ppc_cpu->env.gpr[5] = 0; 1426 first_cpu->halted = 0; 1427 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1428 1429 spapr->cas_reboot = false; 1430 } 1431 1432 static void spapr_create_nvram(sPAPRMachineState *spapr) 1433 { 1434 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1435 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1436 1437 if (dinfo) { 1438 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1439 &error_fatal); 1440 } 1441 1442 qdev_init_nofail(dev); 1443 1444 spapr->nvram = (struct sPAPRNVRAM *)dev; 1445 } 1446 1447 static void spapr_rtc_create(sPAPRMachineState *spapr) 1448 { 1449 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1450 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1451 &error_fatal); 1452 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1453 &error_fatal); 1454 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1455 "date", &error_fatal); 1456 } 1457 1458 /* Returns whether we want to use VGA or not */ 1459 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1460 { 1461 switch (vga_interface_type) { 1462 case VGA_NONE: 1463 return false; 1464 case VGA_DEVICE: 1465 return true; 1466 case VGA_STD: 1467 case VGA_VIRTIO: 1468 return pci_vga_init(pci_bus) != NULL; 1469 default: 1470 error_setg(errp, 1471 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1472 return false; 1473 } 1474 } 1475 1476 static int spapr_post_load(void *opaque, int version_id) 1477 { 1478 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1479 int err = 0; 1480 1481 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1482 CPUState *cs; 1483 CPU_FOREACH(cs) { 1484 PowerPCCPU *cpu = POWERPC_CPU(cs); 1485 icp_resend(ICP(cpu->intc)); 1486 } 1487 } 1488 1489 /* In earlier versions, there was no separate qdev for the PAPR 1490 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1491 * So when migrating from those versions, poke the incoming offset 1492 * value into the RTC device */ 1493 if (version_id < 3) { 1494 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1495 } 1496 1497 if (spapr->patb_entry) { 1498 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1499 bool radix = !!(spapr->patb_entry & PATBE1_GR); 1500 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1501 1502 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1503 if (err) { 1504 error_report("Process table config unsupported by the host"); 1505 return -EINVAL; 1506 } 1507 } 1508 1509 return err; 1510 } 1511 1512 static bool version_before_3(void *opaque, int version_id) 1513 { 1514 return version_id < 3; 1515 } 1516 1517 static bool spapr_ov5_cas_needed(void *opaque) 1518 { 1519 sPAPRMachineState *spapr = opaque; 1520 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1521 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1522 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1523 bool cas_needed; 1524 1525 /* Prior to the introduction of sPAPROptionVector, we had two option 1526 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1527 * Both of these options encode machine topology into the device-tree 1528 * in such a way that the now-booted OS should still be able to interact 1529 * appropriately with QEMU regardless of what options were actually 1530 * negotiatied on the source side. 1531 * 1532 * As such, we can avoid migrating the CAS-negotiated options if these 1533 * are the only options available on the current machine/platform. 1534 * Since these are the only options available for pseries-2.7 and 1535 * earlier, this allows us to maintain old->new/new->old migration 1536 * compatibility. 1537 * 1538 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1539 * via default pseries-2.8 machines and explicit command-line parameters. 1540 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1541 * of the actual CAS-negotiated values to continue working properly. For 1542 * example, availability of memory unplug depends on knowing whether 1543 * OV5_HP_EVT was negotiated via CAS. 1544 * 1545 * Thus, for any cases where the set of available CAS-negotiatable 1546 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1547 * include the CAS-negotiated options in the migration stream. 1548 */ 1549 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1550 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1551 1552 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1553 * the mask itself since in the future it's possible "legacy" bits may be 1554 * removed via machine options, which could generate a false positive 1555 * that breaks migration. 1556 */ 1557 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1558 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1559 1560 spapr_ovec_cleanup(ov5_mask); 1561 spapr_ovec_cleanup(ov5_legacy); 1562 spapr_ovec_cleanup(ov5_removed); 1563 1564 return cas_needed; 1565 } 1566 1567 static const VMStateDescription vmstate_spapr_ov5_cas = { 1568 .name = "spapr_option_vector_ov5_cas", 1569 .version_id = 1, 1570 .minimum_version_id = 1, 1571 .needed = spapr_ov5_cas_needed, 1572 .fields = (VMStateField[]) { 1573 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1574 vmstate_spapr_ovec, sPAPROptionVector), 1575 VMSTATE_END_OF_LIST() 1576 }, 1577 }; 1578 1579 static bool spapr_patb_entry_needed(void *opaque) 1580 { 1581 sPAPRMachineState *spapr = opaque; 1582 1583 return !!spapr->patb_entry; 1584 } 1585 1586 static const VMStateDescription vmstate_spapr_patb_entry = { 1587 .name = "spapr_patb_entry", 1588 .version_id = 1, 1589 .minimum_version_id = 1, 1590 .needed = spapr_patb_entry_needed, 1591 .fields = (VMStateField[]) { 1592 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1593 VMSTATE_END_OF_LIST() 1594 }, 1595 }; 1596 1597 static const VMStateDescription vmstate_spapr = { 1598 .name = "spapr", 1599 .version_id = 3, 1600 .minimum_version_id = 1, 1601 .post_load = spapr_post_load, 1602 .fields = (VMStateField[]) { 1603 /* used to be @next_irq */ 1604 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1605 1606 /* RTC offset */ 1607 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1608 1609 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1610 VMSTATE_END_OF_LIST() 1611 }, 1612 .subsections = (const VMStateDescription*[]) { 1613 &vmstate_spapr_ov5_cas, 1614 &vmstate_spapr_patb_entry, 1615 NULL 1616 } 1617 }; 1618 1619 static int htab_save_setup(QEMUFile *f, void *opaque) 1620 { 1621 sPAPRMachineState *spapr = opaque; 1622 1623 /* "Iteration" header */ 1624 if (!spapr->htab_shift) { 1625 qemu_put_be32(f, -1); 1626 } else { 1627 qemu_put_be32(f, spapr->htab_shift); 1628 } 1629 1630 if (spapr->htab) { 1631 spapr->htab_save_index = 0; 1632 spapr->htab_first_pass = true; 1633 } else { 1634 if (spapr->htab_shift) { 1635 assert(kvm_enabled()); 1636 } 1637 } 1638 1639 1640 return 0; 1641 } 1642 1643 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1644 int64_t max_ns) 1645 { 1646 bool has_timeout = max_ns != -1; 1647 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1648 int index = spapr->htab_save_index; 1649 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1650 1651 assert(spapr->htab_first_pass); 1652 1653 do { 1654 int chunkstart; 1655 1656 /* Consume invalid HPTEs */ 1657 while ((index < htabslots) 1658 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1659 CLEAN_HPTE(HPTE(spapr->htab, index)); 1660 index++; 1661 } 1662 1663 /* Consume valid HPTEs */ 1664 chunkstart = index; 1665 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1666 && HPTE_VALID(HPTE(spapr->htab, index))) { 1667 CLEAN_HPTE(HPTE(spapr->htab, index)); 1668 index++; 1669 } 1670 1671 if (index > chunkstart) { 1672 int n_valid = index - chunkstart; 1673 1674 qemu_put_be32(f, chunkstart); 1675 qemu_put_be16(f, n_valid); 1676 qemu_put_be16(f, 0); 1677 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1678 HASH_PTE_SIZE_64 * n_valid); 1679 1680 if (has_timeout && 1681 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1682 break; 1683 } 1684 } 1685 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1686 1687 if (index >= htabslots) { 1688 assert(index == htabslots); 1689 index = 0; 1690 spapr->htab_first_pass = false; 1691 } 1692 spapr->htab_save_index = index; 1693 } 1694 1695 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1696 int64_t max_ns) 1697 { 1698 bool final = max_ns < 0; 1699 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1700 int examined = 0, sent = 0; 1701 int index = spapr->htab_save_index; 1702 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1703 1704 assert(!spapr->htab_first_pass); 1705 1706 do { 1707 int chunkstart, invalidstart; 1708 1709 /* Consume non-dirty HPTEs */ 1710 while ((index < htabslots) 1711 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1712 index++; 1713 examined++; 1714 } 1715 1716 chunkstart = index; 1717 /* Consume valid dirty HPTEs */ 1718 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1719 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1720 && HPTE_VALID(HPTE(spapr->htab, index))) { 1721 CLEAN_HPTE(HPTE(spapr->htab, index)); 1722 index++; 1723 examined++; 1724 } 1725 1726 invalidstart = index; 1727 /* Consume invalid dirty HPTEs */ 1728 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1729 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1730 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1731 CLEAN_HPTE(HPTE(spapr->htab, index)); 1732 index++; 1733 examined++; 1734 } 1735 1736 if (index > chunkstart) { 1737 int n_valid = invalidstart - chunkstart; 1738 int n_invalid = index - invalidstart; 1739 1740 qemu_put_be32(f, chunkstart); 1741 qemu_put_be16(f, n_valid); 1742 qemu_put_be16(f, n_invalid); 1743 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1744 HASH_PTE_SIZE_64 * n_valid); 1745 sent += index - chunkstart; 1746 1747 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1748 break; 1749 } 1750 } 1751 1752 if (examined >= htabslots) { 1753 break; 1754 } 1755 1756 if (index >= htabslots) { 1757 assert(index == htabslots); 1758 index = 0; 1759 } 1760 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1761 1762 if (index >= htabslots) { 1763 assert(index == htabslots); 1764 index = 0; 1765 } 1766 1767 spapr->htab_save_index = index; 1768 1769 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1770 } 1771 1772 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1773 #define MAX_KVM_BUF_SIZE 2048 1774 1775 static int htab_save_iterate(QEMUFile *f, void *opaque) 1776 { 1777 sPAPRMachineState *spapr = opaque; 1778 int fd; 1779 int rc = 0; 1780 1781 /* Iteration header */ 1782 if (!spapr->htab_shift) { 1783 qemu_put_be32(f, -1); 1784 return 0; 1785 } else { 1786 qemu_put_be32(f, 0); 1787 } 1788 1789 if (!spapr->htab) { 1790 assert(kvm_enabled()); 1791 1792 fd = get_htab_fd(spapr); 1793 if (fd < 0) { 1794 return fd; 1795 } 1796 1797 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1798 if (rc < 0) { 1799 return rc; 1800 } 1801 } else if (spapr->htab_first_pass) { 1802 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1803 } else { 1804 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1805 } 1806 1807 /* End marker */ 1808 qemu_put_be32(f, 0); 1809 qemu_put_be16(f, 0); 1810 qemu_put_be16(f, 0); 1811 1812 return rc; 1813 } 1814 1815 static int htab_save_complete(QEMUFile *f, void *opaque) 1816 { 1817 sPAPRMachineState *spapr = opaque; 1818 int fd; 1819 1820 /* Iteration header */ 1821 if (!spapr->htab_shift) { 1822 qemu_put_be32(f, -1); 1823 return 0; 1824 } else { 1825 qemu_put_be32(f, 0); 1826 } 1827 1828 if (!spapr->htab) { 1829 int rc; 1830 1831 assert(kvm_enabled()); 1832 1833 fd = get_htab_fd(spapr); 1834 if (fd < 0) { 1835 return fd; 1836 } 1837 1838 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1839 if (rc < 0) { 1840 return rc; 1841 } 1842 } else { 1843 if (spapr->htab_first_pass) { 1844 htab_save_first_pass(f, spapr, -1); 1845 } 1846 htab_save_later_pass(f, spapr, -1); 1847 } 1848 1849 /* End marker */ 1850 qemu_put_be32(f, 0); 1851 qemu_put_be16(f, 0); 1852 qemu_put_be16(f, 0); 1853 1854 return 0; 1855 } 1856 1857 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1858 { 1859 sPAPRMachineState *spapr = opaque; 1860 uint32_t section_hdr; 1861 int fd = -1; 1862 1863 if (version_id < 1 || version_id > 1) { 1864 error_report("htab_load() bad version"); 1865 return -EINVAL; 1866 } 1867 1868 section_hdr = qemu_get_be32(f); 1869 1870 if (section_hdr == -1) { 1871 spapr_free_hpt(spapr); 1872 return 0; 1873 } 1874 1875 if (section_hdr) { 1876 Error *local_err = NULL; 1877 1878 /* First section gives the htab size */ 1879 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1880 if (local_err) { 1881 error_report_err(local_err); 1882 return -EINVAL; 1883 } 1884 return 0; 1885 } 1886 1887 if (!spapr->htab) { 1888 assert(kvm_enabled()); 1889 1890 fd = kvmppc_get_htab_fd(true); 1891 if (fd < 0) { 1892 error_report("Unable to open fd to restore KVM hash table: %s", 1893 strerror(errno)); 1894 } 1895 } 1896 1897 while (true) { 1898 uint32_t index; 1899 uint16_t n_valid, n_invalid; 1900 1901 index = qemu_get_be32(f); 1902 n_valid = qemu_get_be16(f); 1903 n_invalid = qemu_get_be16(f); 1904 1905 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1906 /* End of Stream */ 1907 break; 1908 } 1909 1910 if ((index + n_valid + n_invalid) > 1911 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1912 /* Bad index in stream */ 1913 error_report( 1914 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1915 index, n_valid, n_invalid, spapr->htab_shift); 1916 return -EINVAL; 1917 } 1918 1919 if (spapr->htab) { 1920 if (n_valid) { 1921 qemu_get_buffer(f, HPTE(spapr->htab, index), 1922 HASH_PTE_SIZE_64 * n_valid); 1923 } 1924 if (n_invalid) { 1925 memset(HPTE(spapr->htab, index + n_valid), 0, 1926 HASH_PTE_SIZE_64 * n_invalid); 1927 } 1928 } else { 1929 int rc; 1930 1931 assert(fd >= 0); 1932 1933 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1934 if (rc < 0) { 1935 return rc; 1936 } 1937 } 1938 } 1939 1940 if (!spapr->htab) { 1941 assert(fd >= 0); 1942 close(fd); 1943 } 1944 1945 return 0; 1946 } 1947 1948 static void htab_save_cleanup(void *opaque) 1949 { 1950 sPAPRMachineState *spapr = opaque; 1951 1952 close_htab_fd(spapr); 1953 } 1954 1955 static SaveVMHandlers savevm_htab_handlers = { 1956 .save_setup = htab_save_setup, 1957 .save_live_iterate = htab_save_iterate, 1958 .save_live_complete_precopy = htab_save_complete, 1959 .save_cleanup = htab_save_cleanup, 1960 .load_state = htab_load, 1961 }; 1962 1963 static void spapr_boot_set(void *opaque, const char *boot_device, 1964 Error **errp) 1965 { 1966 MachineState *machine = MACHINE(qdev_get_machine()); 1967 machine->boot_order = g_strdup(boot_device); 1968 } 1969 1970 /* 1971 * Reset routine for LMB DR devices. 1972 * 1973 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1974 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1975 * when it walks all its children devices. LMB devices reset occurs 1976 * as part of spapr_ppc_reset(). 1977 */ 1978 static void spapr_drc_reset(void *opaque) 1979 { 1980 sPAPRDRConnector *drc = opaque; 1981 DeviceState *d = DEVICE(drc); 1982 1983 if (d) { 1984 device_reset(d); 1985 } 1986 } 1987 1988 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1989 { 1990 MachineState *machine = MACHINE(spapr); 1991 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1992 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1993 int i; 1994 1995 for (i = 0; i < nr_lmbs; i++) { 1996 sPAPRDRConnector *drc; 1997 uint64_t addr; 1998 1999 addr = i * lmb_size + spapr->hotplug_memory.base; 2000 drc = spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2001 addr/lmb_size); 2002 qemu_register_reset(spapr_drc_reset, drc); 2003 } 2004 } 2005 2006 /* 2007 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2008 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2009 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2010 */ 2011 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2012 { 2013 int i; 2014 2015 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2016 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2017 " is not aligned to %llu MiB", 2018 machine->ram_size, 2019 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2020 return; 2021 } 2022 2023 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2024 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2025 " is not aligned to %llu MiB", 2026 machine->ram_size, 2027 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2028 return; 2029 } 2030 2031 for (i = 0; i < nb_numa_nodes; i++) { 2032 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2033 error_setg(errp, 2034 "Node %d memory size 0x%" PRIx64 2035 " is not aligned to %llu MiB", 2036 i, numa_info[i].node_mem, 2037 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2038 return; 2039 } 2040 } 2041 } 2042 2043 /* find cpu slot in machine->possible_cpus by core_id */ 2044 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2045 { 2046 int index = id / smp_threads; 2047 2048 if (index >= ms->possible_cpus->len) { 2049 return NULL; 2050 } 2051 if (idx) { 2052 *idx = index; 2053 } 2054 return &ms->possible_cpus->cpus[index]; 2055 } 2056 2057 static void spapr_init_cpus(sPAPRMachineState *spapr) 2058 { 2059 MachineState *machine = MACHINE(spapr); 2060 MachineClass *mc = MACHINE_GET_CLASS(machine); 2061 char *type = spapr_get_cpu_core_type(machine->cpu_model); 2062 int smt = kvmppc_smt_threads(); 2063 const CPUArchIdList *possible_cpus; 2064 int boot_cores_nr = smp_cpus / smp_threads; 2065 int i; 2066 2067 if (!type) { 2068 error_report("Unable to find sPAPR CPU Core definition"); 2069 exit(1); 2070 } 2071 2072 possible_cpus = mc->possible_cpu_arch_ids(machine); 2073 if (mc->has_hotpluggable_cpus) { 2074 if (smp_cpus % smp_threads) { 2075 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2076 smp_cpus, smp_threads); 2077 exit(1); 2078 } 2079 if (max_cpus % smp_threads) { 2080 error_report("max_cpus (%u) must be multiple of threads (%u)", 2081 max_cpus, smp_threads); 2082 exit(1); 2083 } 2084 } else { 2085 if (max_cpus != smp_cpus) { 2086 error_report("This machine version does not support CPU hotplug"); 2087 exit(1); 2088 } 2089 boot_cores_nr = possible_cpus->len; 2090 } 2091 2092 for (i = 0; i < possible_cpus->len; i++) { 2093 int core_id = i * smp_threads; 2094 2095 if (mc->has_hotpluggable_cpus) { 2096 sPAPRDRConnector *drc = 2097 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2098 (core_id / smp_threads) * smt); 2099 2100 qemu_register_reset(spapr_drc_reset, drc); 2101 } 2102 2103 if (i < boot_cores_nr) { 2104 Object *core = object_new(type); 2105 int nr_threads = smp_threads; 2106 2107 /* Handle the partially filled core for older machine types */ 2108 if ((i + 1) * smp_threads >= smp_cpus) { 2109 nr_threads = smp_cpus - i * smp_threads; 2110 } 2111 2112 object_property_set_int(core, nr_threads, "nr-threads", 2113 &error_fatal); 2114 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2115 &error_fatal); 2116 object_property_set_bool(core, true, "realized", &error_fatal); 2117 } 2118 } 2119 g_free(type); 2120 } 2121 2122 /* pSeries LPAR / sPAPR hardware init */ 2123 static void ppc_spapr_init(MachineState *machine) 2124 { 2125 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2126 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2127 const char *kernel_filename = machine->kernel_filename; 2128 const char *initrd_filename = machine->initrd_filename; 2129 PCIHostState *phb; 2130 int i; 2131 MemoryRegion *sysmem = get_system_memory(); 2132 MemoryRegion *ram = g_new(MemoryRegion, 1); 2133 MemoryRegion *rma_region; 2134 void *rma = NULL; 2135 hwaddr rma_alloc_size; 2136 hwaddr node0_size = spapr_node0_size(); 2137 long load_limit, fw_size; 2138 char *filename; 2139 2140 msi_nonbroken = true; 2141 2142 QLIST_INIT(&spapr->phbs); 2143 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2144 2145 /* Allocate RMA if necessary */ 2146 rma_alloc_size = kvmppc_alloc_rma(&rma); 2147 2148 if (rma_alloc_size == -1) { 2149 error_report("Unable to create RMA"); 2150 exit(1); 2151 } 2152 2153 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 2154 spapr->rma_size = rma_alloc_size; 2155 } else { 2156 spapr->rma_size = node0_size; 2157 2158 /* With KVM, we don't actually know whether KVM supports an 2159 * unbounded RMA (PR KVM) or is limited by the hash table size 2160 * (HV KVM using VRMA), so we always assume the latter 2161 * 2162 * In that case, we also limit the initial allocations for RTAS 2163 * etc... to 256M since we have no way to know what the VRMA size 2164 * is going to be as it depends on the size of the hash table 2165 * isn't determined yet. 2166 */ 2167 if (kvm_enabled()) { 2168 spapr->vrma_adjust = 1; 2169 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2170 } 2171 2172 /* Actually we don't support unbounded RMA anymore since we 2173 * added proper emulation of HV mode. The max we can get is 2174 * 16G which also happens to be what we configure for PAPR 2175 * mode so make sure we don't do anything bigger than that 2176 */ 2177 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2178 } 2179 2180 if (spapr->rma_size > node0_size) { 2181 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2182 spapr->rma_size); 2183 exit(1); 2184 } 2185 2186 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2187 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2188 2189 /* Set up Interrupt Controller before we create the VCPUs */ 2190 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); 2191 2192 /* Set up containers for ibm,client-set-architecture negotiated options */ 2193 spapr->ov5 = spapr_ovec_new(); 2194 spapr->ov5_cas = spapr_ovec_new(); 2195 2196 if (smc->dr_lmb_enabled) { 2197 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2198 spapr_validate_node_memory(machine, &error_fatal); 2199 } 2200 2201 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2202 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) { 2203 /* KVM and TCG always allow GTSE with radix... */ 2204 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2205 } 2206 /* ... but not with hash (currently). */ 2207 2208 /* advertise support for dedicated HP event source to guests */ 2209 if (spapr->use_hotplug_event_source) { 2210 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2211 } 2212 2213 /* init CPUs */ 2214 if (machine->cpu_model == NULL) { 2215 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; 2216 } 2217 2218 spapr_cpu_parse_features(spapr); 2219 2220 spapr_init_cpus(spapr); 2221 2222 if (kvm_enabled()) { 2223 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2224 kvmppc_enable_logical_ci_hcalls(); 2225 kvmppc_enable_set_mode_hcall(); 2226 2227 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2228 kvmppc_enable_clear_ref_mod_hcalls(); 2229 } 2230 2231 /* allocate RAM */ 2232 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2233 machine->ram_size); 2234 memory_region_add_subregion(sysmem, 0, ram); 2235 2236 if (rma_alloc_size && rma) { 2237 rma_region = g_new(MemoryRegion, 1); 2238 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 2239 rma_alloc_size, rma); 2240 vmstate_register_ram_global(rma_region); 2241 memory_region_add_subregion(sysmem, 0, rma_region); 2242 } 2243 2244 /* initialize hotplug memory address space */ 2245 if (machine->ram_size < machine->maxram_size) { 2246 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2247 /* 2248 * Limit the number of hotpluggable memory slots to half the number 2249 * slots that KVM supports, leaving the other half for PCI and other 2250 * devices. However ensure that number of slots doesn't drop below 32. 2251 */ 2252 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2253 SPAPR_MAX_RAM_SLOTS; 2254 2255 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2256 max_memslots = SPAPR_MAX_RAM_SLOTS; 2257 } 2258 if (machine->ram_slots > max_memslots) { 2259 error_report("Specified number of memory slots %" 2260 PRIu64" exceeds max supported %d", 2261 machine->ram_slots, max_memslots); 2262 exit(1); 2263 } 2264 2265 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2266 SPAPR_HOTPLUG_MEM_ALIGN); 2267 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2268 "hotplug-memory", hotplug_mem_size); 2269 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2270 &spapr->hotplug_memory.mr); 2271 } 2272 2273 if (smc->dr_lmb_enabled) { 2274 spapr_create_lmb_dr_connectors(spapr); 2275 } 2276 2277 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2278 if (!filename) { 2279 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2280 exit(1); 2281 } 2282 spapr->rtas_size = get_image_size(filename); 2283 if (spapr->rtas_size < 0) { 2284 error_report("Could not get size of LPAR rtas '%s'", filename); 2285 exit(1); 2286 } 2287 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2288 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2289 error_report("Could not load LPAR rtas '%s'", filename); 2290 exit(1); 2291 } 2292 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2293 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2294 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2295 exit(1); 2296 } 2297 g_free(filename); 2298 2299 /* Set up RTAS event infrastructure */ 2300 spapr_events_init(spapr); 2301 2302 /* Set up the RTC RTAS interfaces */ 2303 spapr_rtc_create(spapr); 2304 2305 /* Set up VIO bus */ 2306 spapr->vio_bus = spapr_vio_bus_init(); 2307 2308 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 2309 if (serial_hds[i]) { 2310 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 2311 } 2312 } 2313 2314 /* We always have at least the nvram device on VIO */ 2315 spapr_create_nvram(spapr); 2316 2317 /* Set up PCI */ 2318 spapr_pci_rtas_init(); 2319 2320 phb = spapr_create_phb(spapr, 0); 2321 2322 for (i = 0; i < nb_nics; i++) { 2323 NICInfo *nd = &nd_table[i]; 2324 2325 if (!nd->model) { 2326 nd->model = g_strdup("ibmveth"); 2327 } 2328 2329 if (strcmp(nd->model, "ibmveth") == 0) { 2330 spapr_vlan_create(spapr->vio_bus, nd); 2331 } else { 2332 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2333 } 2334 } 2335 2336 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2337 spapr_vscsi_create(spapr->vio_bus); 2338 } 2339 2340 /* Graphics */ 2341 if (spapr_vga_init(phb->bus, &error_fatal)) { 2342 spapr->has_graphics = true; 2343 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2344 } 2345 2346 if (machine->usb) { 2347 if (smc->use_ohci_by_default) { 2348 pci_create_simple(phb->bus, -1, "pci-ohci"); 2349 } else { 2350 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2351 } 2352 2353 if (spapr->has_graphics) { 2354 USBBus *usb_bus = usb_bus_find(-1); 2355 2356 usb_create_simple(usb_bus, "usb-kbd"); 2357 usb_create_simple(usb_bus, "usb-mouse"); 2358 } 2359 } 2360 2361 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2362 error_report( 2363 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2364 MIN_RMA_SLOF); 2365 exit(1); 2366 } 2367 2368 if (kernel_filename) { 2369 uint64_t lowaddr = 0; 2370 2371 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2372 NULL, NULL, &lowaddr, NULL, 1, 2373 PPC_ELF_MACHINE, 0, 0); 2374 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2375 spapr->kernel_size = load_elf(kernel_filename, 2376 translate_kernel_address, NULL, NULL, 2377 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2378 0, 0); 2379 spapr->kernel_le = spapr->kernel_size > 0; 2380 } 2381 if (spapr->kernel_size < 0) { 2382 error_report("error loading %s: %s", kernel_filename, 2383 load_elf_strerror(spapr->kernel_size)); 2384 exit(1); 2385 } 2386 2387 /* load initrd */ 2388 if (initrd_filename) { 2389 /* Try to locate the initrd in the gap between the kernel 2390 * and the firmware. Add a bit of space just in case 2391 */ 2392 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2393 + 0x1ffff) & ~0xffff; 2394 spapr->initrd_size = load_image_targphys(initrd_filename, 2395 spapr->initrd_base, 2396 load_limit 2397 - spapr->initrd_base); 2398 if (spapr->initrd_size < 0) { 2399 error_report("could not load initial ram disk '%s'", 2400 initrd_filename); 2401 exit(1); 2402 } 2403 } 2404 } 2405 2406 if (bios_name == NULL) { 2407 bios_name = FW_FILE_NAME; 2408 } 2409 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2410 if (!filename) { 2411 error_report("Could not find LPAR firmware '%s'", bios_name); 2412 exit(1); 2413 } 2414 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2415 if (fw_size <= 0) { 2416 error_report("Could not load LPAR firmware '%s'", filename); 2417 exit(1); 2418 } 2419 g_free(filename); 2420 2421 /* FIXME: Should register things through the MachineState's qdev 2422 * interface, this is a legacy from the sPAPREnvironment structure 2423 * which predated MachineState but had a similar function */ 2424 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2425 register_savevm_live(NULL, "spapr/htab", -1, 1, 2426 &savevm_htab_handlers, spapr); 2427 2428 qemu_register_boot_set(spapr_boot_set, spapr); 2429 2430 if (kvm_enabled()) { 2431 /* to stop and start vmclock */ 2432 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2433 &spapr->tb); 2434 2435 kvmppc_spapr_enable_inkernel_multitce(); 2436 } 2437 } 2438 2439 static int spapr_kvm_type(const char *vm_type) 2440 { 2441 if (!vm_type) { 2442 return 0; 2443 } 2444 2445 if (!strcmp(vm_type, "HV")) { 2446 return 1; 2447 } 2448 2449 if (!strcmp(vm_type, "PR")) { 2450 return 2; 2451 } 2452 2453 error_report("Unknown kvm-type specified '%s'", vm_type); 2454 exit(1); 2455 } 2456 2457 /* 2458 * Implementation of an interface to adjust firmware path 2459 * for the bootindex property handling. 2460 */ 2461 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2462 DeviceState *dev) 2463 { 2464 #define CAST(type, obj, name) \ 2465 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2466 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2467 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2468 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 2469 2470 if (d) { 2471 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2472 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2473 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2474 2475 if (spapr) { 2476 /* 2477 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2478 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2479 * in the top 16 bits of the 64-bit LUN 2480 */ 2481 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2482 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2483 (uint64_t)id << 48); 2484 } else if (virtio) { 2485 /* 2486 * We use SRP luns of the form 01000000 | (target << 8) | lun 2487 * in the top 32 bits of the 64-bit LUN 2488 * Note: the quote above is from SLOF and it is wrong, 2489 * the actual binding is: 2490 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2491 */ 2492 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2493 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2494 (uint64_t)id << 32); 2495 } else if (usb) { 2496 /* 2497 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2498 * in the top 32 bits of the 64-bit LUN 2499 */ 2500 unsigned usb_port = atoi(usb->port->path); 2501 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2502 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2503 (uint64_t)id << 32); 2504 } 2505 } 2506 2507 /* 2508 * SLOF probes the USB devices, and if it recognizes that the device is a 2509 * storage device, it changes its name to "storage" instead of "usb-host", 2510 * and additionally adds a child node for the SCSI LUN, so the correct 2511 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2512 */ 2513 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2514 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2515 if (usb_host_dev_is_scsi_storage(usbdev)) { 2516 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2517 } 2518 } 2519 2520 if (phb) { 2521 /* Replace "pci" with "pci@800000020000000" */ 2522 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2523 } 2524 2525 if (vsc) { 2526 /* Same logic as virtio above */ 2527 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 2528 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 2529 } 2530 2531 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 2532 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 2533 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 2534 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 2535 } 2536 2537 return NULL; 2538 } 2539 2540 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2541 { 2542 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2543 2544 return g_strdup(spapr->kvm_type); 2545 } 2546 2547 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2548 { 2549 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2550 2551 g_free(spapr->kvm_type); 2552 spapr->kvm_type = g_strdup(value); 2553 } 2554 2555 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2556 { 2557 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2558 2559 return spapr->use_hotplug_event_source; 2560 } 2561 2562 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2563 Error **errp) 2564 { 2565 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2566 2567 spapr->use_hotplug_event_source = value; 2568 } 2569 2570 static void spapr_machine_initfn(Object *obj) 2571 { 2572 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2573 2574 spapr->htab_fd = -1; 2575 spapr->use_hotplug_event_source = true; 2576 object_property_add_str(obj, "kvm-type", 2577 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2578 object_property_set_description(obj, "kvm-type", 2579 "Specifies the KVM virtualization mode (HV, PR)", 2580 NULL); 2581 object_property_add_bool(obj, "modern-hotplug-events", 2582 spapr_get_modern_hotplug_events, 2583 spapr_set_modern_hotplug_events, 2584 NULL); 2585 object_property_set_description(obj, "modern-hotplug-events", 2586 "Use dedicated hotplug event mechanism in" 2587 " place of standard EPOW events when possible" 2588 " (required for memory hot-unplug support)", 2589 NULL); 2590 2591 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 2592 "Maximum permitted CPU compatibility mode", 2593 &error_fatal); 2594 } 2595 2596 static void spapr_machine_finalizefn(Object *obj) 2597 { 2598 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2599 2600 g_free(spapr->kvm_type); 2601 } 2602 2603 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 2604 { 2605 cpu_synchronize_state(cs); 2606 ppc_cpu_do_system_reset(cs); 2607 } 2608 2609 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2610 { 2611 CPUState *cs; 2612 2613 CPU_FOREACH(cs) { 2614 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 2615 } 2616 } 2617 2618 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2619 uint32_t node, bool dedicated_hp_event_source, 2620 Error **errp) 2621 { 2622 sPAPRDRConnector *drc; 2623 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2624 int i, fdt_offset, fdt_size; 2625 void *fdt; 2626 uint64_t addr = addr_start; 2627 2628 for (i = 0; i < nr_lmbs; i++) { 2629 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2630 addr / SPAPR_MEMORY_BLOCK_SIZE); 2631 g_assert(drc); 2632 2633 fdt = create_device_tree(&fdt_size); 2634 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2635 SPAPR_MEMORY_BLOCK_SIZE); 2636 2637 spapr_drc_attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2638 addr += SPAPR_MEMORY_BLOCK_SIZE; 2639 } 2640 /* send hotplug notification to the 2641 * guest only in case of hotplugged memory 2642 */ 2643 if (dev->hotplugged) { 2644 if (dedicated_hp_event_source) { 2645 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2646 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2647 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2648 nr_lmbs, 2649 spapr_drc_index(drc)); 2650 } else { 2651 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 2652 nr_lmbs); 2653 } 2654 } 2655 } 2656 2657 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2658 uint32_t node, Error **errp) 2659 { 2660 Error *local_err = NULL; 2661 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2662 PCDIMMDevice *dimm = PC_DIMM(dev); 2663 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2664 MemoryRegion *mr = ddc->get_memory_region(dimm); 2665 uint64_t align = memory_region_get_alignment(mr); 2666 uint64_t size = memory_region_size(mr); 2667 uint64_t addr; 2668 2669 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2670 if (local_err) { 2671 goto out; 2672 } 2673 2674 addr = object_property_get_uint(OBJECT(dimm), 2675 PC_DIMM_ADDR_PROP, &local_err); 2676 if (local_err) { 2677 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2678 goto out; 2679 } 2680 2681 spapr_add_lmbs(dev, addr, size, node, 2682 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 2683 &error_abort); 2684 2685 out: 2686 error_propagate(errp, local_err); 2687 } 2688 2689 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2690 Error **errp) 2691 { 2692 PCDIMMDevice *dimm = PC_DIMM(dev); 2693 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2694 MemoryRegion *mr = ddc->get_memory_region(dimm); 2695 uint64_t size = memory_region_size(mr); 2696 char *mem_dev; 2697 2698 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2699 error_setg(errp, "Hotplugged memory size must be a multiple of " 2700 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2701 return; 2702 } 2703 2704 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 2705 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 2706 error_setg(errp, "Memory backend has bad page size. " 2707 "Use 'memory-backend-file' with correct mem-path."); 2708 goto out; 2709 } 2710 2711 out: 2712 g_free(mem_dev); 2713 } 2714 2715 struct sPAPRDIMMState { 2716 PCDIMMDevice *dimm; 2717 uint32_t nr_lmbs; 2718 QTAILQ_ENTRY(sPAPRDIMMState) next; 2719 }; 2720 2721 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 2722 PCDIMMDevice *dimm) 2723 { 2724 sPAPRDIMMState *dimm_state = NULL; 2725 2726 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 2727 if (dimm_state->dimm == dimm) { 2728 break; 2729 } 2730 } 2731 return dimm_state; 2732 } 2733 2734 static void spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 2735 sPAPRDIMMState *dimm_state) 2736 { 2737 g_assert(!spapr_pending_dimm_unplugs_find(spapr, dimm_state->dimm)); 2738 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, dimm_state, next); 2739 } 2740 2741 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 2742 sPAPRDIMMState *dimm_state) 2743 { 2744 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 2745 g_free(dimm_state); 2746 } 2747 2748 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 2749 PCDIMMDevice *dimm) 2750 { 2751 sPAPRDRConnector *drc; 2752 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2753 MemoryRegion *mr = ddc->get_memory_region(dimm); 2754 uint64_t size = memory_region_size(mr); 2755 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2756 uint32_t avail_lmbs = 0; 2757 uint64_t addr_start, addr; 2758 int i; 2759 sPAPRDIMMState *ds; 2760 2761 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 2762 &error_abort); 2763 2764 addr = addr_start; 2765 for (i = 0; i < nr_lmbs; i++) { 2766 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2767 addr / SPAPR_MEMORY_BLOCK_SIZE); 2768 g_assert(drc); 2769 if (drc->dev) { 2770 avail_lmbs++; 2771 } 2772 addr += SPAPR_MEMORY_BLOCK_SIZE; 2773 } 2774 2775 ds = g_malloc0(sizeof(sPAPRDIMMState)); 2776 ds->nr_lmbs = avail_lmbs; 2777 ds->dimm = dimm; 2778 spapr_pending_dimm_unplugs_add(ms, ds); 2779 return ds; 2780 } 2781 2782 /* Callback to be called during DRC release. */ 2783 void spapr_lmb_release(DeviceState *dev) 2784 { 2785 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 2786 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 2787 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 2788 2789 /* This information will get lost if a migration occurs 2790 * during the unplug process. In this case recover it. */ 2791 if (ds == NULL) { 2792 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 2793 /* The DRC being examined by the caller at least must be counted */ 2794 g_assert(ds->nr_lmbs); 2795 } 2796 2797 if (--ds->nr_lmbs) { 2798 return; 2799 } 2800 2801 spapr_pending_dimm_unplugs_remove(spapr, ds); 2802 2803 /* 2804 * Now that all the LMBs have been removed by the guest, call the 2805 * pc-dimm unplug handler to cleanup up the pc-dimm device. 2806 */ 2807 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2808 } 2809 2810 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2811 Error **errp) 2812 { 2813 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2814 PCDIMMDevice *dimm = PC_DIMM(dev); 2815 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2816 MemoryRegion *mr = ddc->get_memory_region(dimm); 2817 2818 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2819 object_unparent(OBJECT(dev)); 2820 } 2821 2822 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 2823 DeviceState *dev, Error **errp) 2824 { 2825 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 2826 Error *local_err = NULL; 2827 PCDIMMDevice *dimm = PC_DIMM(dev); 2828 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2829 MemoryRegion *mr = ddc->get_memory_region(dimm); 2830 uint64_t size = memory_region_size(mr); 2831 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2832 uint64_t addr_start, addr; 2833 int i; 2834 sPAPRDRConnector *drc; 2835 sPAPRDIMMState *ds; 2836 2837 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 2838 &local_err); 2839 if (local_err) { 2840 goto out; 2841 } 2842 2843 ds = g_malloc0(sizeof(sPAPRDIMMState)); 2844 ds->nr_lmbs = nr_lmbs; 2845 ds->dimm = dimm; 2846 spapr_pending_dimm_unplugs_add(spapr, ds); 2847 2848 addr = addr_start; 2849 for (i = 0; i < nr_lmbs; i++) { 2850 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2851 addr / SPAPR_MEMORY_BLOCK_SIZE); 2852 g_assert(drc); 2853 2854 spapr_drc_detach(drc, dev, errp); 2855 addr += SPAPR_MEMORY_BLOCK_SIZE; 2856 } 2857 2858 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2859 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2860 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2861 nr_lmbs, spapr_drc_index(drc)); 2862 out: 2863 error_propagate(errp, local_err); 2864 } 2865 2866 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 2867 sPAPRMachineState *spapr) 2868 { 2869 PowerPCCPU *cpu = POWERPC_CPU(cs); 2870 DeviceClass *dc = DEVICE_GET_CLASS(cs); 2871 int id = ppc_get_vcpu_dt_id(cpu); 2872 void *fdt; 2873 int offset, fdt_size; 2874 char *nodename; 2875 2876 fdt = create_device_tree(&fdt_size); 2877 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 2878 offset = fdt_add_subnode(fdt, 0, nodename); 2879 2880 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 2881 g_free(nodename); 2882 2883 *fdt_offset = offset; 2884 return fdt; 2885 } 2886 2887 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2888 Error **errp) 2889 { 2890 MachineState *ms = MACHINE(qdev_get_machine()); 2891 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 2892 CPUCore *cc = CPU_CORE(dev); 2893 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 2894 2895 if (smc->pre_2_10_has_unused_icps) { 2896 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 2897 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc)); 2898 const char *typename = object_class_get_name(scc->cpu_class); 2899 size_t size = object_type_get_instance_size(typename); 2900 int i; 2901 2902 for (i = 0; i < cc->nr_threads; i++) { 2903 CPUState *cs = CPU(sc->threads + i * size); 2904 2905 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 2906 } 2907 } 2908 2909 assert(core_slot); 2910 core_slot->cpu = NULL; 2911 object_unparent(OBJECT(dev)); 2912 } 2913 2914 /* Callback to be called during DRC release. */ 2915 void spapr_core_release(DeviceState *dev) 2916 { 2917 HotplugHandler *hotplug_ctrl; 2918 2919 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2920 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2921 } 2922 2923 static 2924 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 2925 Error **errp) 2926 { 2927 int index; 2928 sPAPRDRConnector *drc; 2929 Error *local_err = NULL; 2930 CPUCore *cc = CPU_CORE(dev); 2931 int smt = kvmppc_smt_threads(); 2932 2933 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 2934 error_setg(errp, "Unable to find CPU core with core-id: %d", 2935 cc->core_id); 2936 return; 2937 } 2938 if (index == 0) { 2939 error_setg(errp, "Boot CPU core may not be unplugged"); 2940 return; 2941 } 2942 2943 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); 2944 g_assert(drc); 2945 2946 spapr_drc_detach(drc, dev, &local_err); 2947 if (local_err) { 2948 error_propagate(errp, local_err); 2949 return; 2950 } 2951 2952 spapr_hotplug_req_remove_by_index(drc); 2953 } 2954 2955 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2956 Error **errp) 2957 { 2958 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 2959 MachineClass *mc = MACHINE_GET_CLASS(spapr); 2960 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 2961 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 2962 CPUCore *cc = CPU_CORE(dev); 2963 CPUState *cs = CPU(core->threads); 2964 sPAPRDRConnector *drc; 2965 Error *local_err = NULL; 2966 void *fdt = NULL; 2967 int fdt_offset = 0; 2968 int smt = kvmppc_smt_threads(); 2969 CPUArchId *core_slot; 2970 int index; 2971 2972 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2973 if (!core_slot) { 2974 error_setg(errp, "Unable to find CPU core with core-id: %d", 2975 cc->core_id); 2976 return; 2977 } 2978 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); 2979 2980 g_assert(drc || !mc->has_hotpluggable_cpus); 2981 2982 /* 2983 * Setup CPU DT entries only for hotplugged CPUs. For boot time or 2984 * coldplugged CPUs DT entries are setup in spapr_build_fdt(). 2985 */ 2986 if (dev->hotplugged) { 2987 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 2988 } 2989 2990 if (drc) { 2991 spapr_drc_attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, 2992 &local_err); 2993 if (local_err) { 2994 g_free(fdt); 2995 error_propagate(errp, local_err); 2996 return; 2997 } 2998 } 2999 3000 if (dev->hotplugged) { 3001 /* 3002 * Send hotplug notification interrupt to the guest only in case 3003 * of hotplugged CPUs. 3004 */ 3005 spapr_hotplug_req_add_by_index(drc); 3006 } 3007 core_slot->cpu = OBJECT(dev); 3008 3009 if (smc->pre_2_10_has_unused_icps) { 3010 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc)); 3011 const char *typename = object_class_get_name(scc->cpu_class); 3012 size_t size = object_type_get_instance_size(typename); 3013 int i; 3014 3015 for (i = 0; i < cc->nr_threads; i++) { 3016 sPAPRCPUCore *sc = SPAPR_CPU_CORE(dev); 3017 void *obj = sc->threads + i * size; 3018 3019 cs = CPU(obj); 3020 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3021 } 3022 } 3023 } 3024 3025 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3026 Error **errp) 3027 { 3028 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3029 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3030 Error *local_err = NULL; 3031 CPUCore *cc = CPU_CORE(dev); 3032 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model); 3033 const char *type = object_get_typename(OBJECT(dev)); 3034 CPUArchId *core_slot; 3035 int index; 3036 3037 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3038 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3039 goto out; 3040 } 3041 3042 if (strcmp(base_core_type, type)) { 3043 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3044 goto out; 3045 } 3046 3047 if (cc->core_id % smp_threads) { 3048 error_setg(&local_err, "invalid core id %d", cc->core_id); 3049 goto out; 3050 } 3051 3052 /* 3053 * In general we should have homogeneous threads-per-core, but old 3054 * (pre hotplug support) machine types allow the last core to have 3055 * reduced threads as a compatibility hack for when we allowed 3056 * total vcpus not a multiple of threads-per-core. 3057 */ 3058 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3059 error_setg(errp, "invalid nr-threads %d, must be %d", 3060 cc->nr_threads, smp_threads); 3061 return; 3062 } 3063 3064 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3065 if (!core_slot) { 3066 error_setg(&local_err, "core id %d out of range", cc->core_id); 3067 goto out; 3068 } 3069 3070 if (core_slot->cpu) { 3071 error_setg(&local_err, "core %d already populated", cc->core_id); 3072 goto out; 3073 } 3074 3075 numa_cpu_pre_plug(core_slot, dev, &local_err); 3076 3077 out: 3078 g_free(base_core_type); 3079 error_propagate(errp, local_err); 3080 } 3081 3082 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3083 DeviceState *dev, Error **errp) 3084 { 3085 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 3086 3087 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3088 int node; 3089 3090 if (!smc->dr_lmb_enabled) { 3091 error_setg(errp, "Memory hotplug not supported for this machine"); 3092 return; 3093 } 3094 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 3095 if (*errp) { 3096 return; 3097 } 3098 if (node < 0 || node >= MAX_NODES) { 3099 error_setg(errp, "Invaild node %d", node); 3100 return; 3101 } 3102 3103 /* 3104 * Currently PowerPC kernel doesn't allow hot-adding memory to 3105 * memory-less node, but instead will silently add the memory 3106 * to the first node that has some memory. This causes two 3107 * unexpected behaviours for the user. 3108 * 3109 * - Memory gets hotplugged to a different node than what the user 3110 * specified. 3111 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 3112 * to memory-less node, a reboot will set things accordingly 3113 * and the previously hotplugged memory now ends in the right node. 3114 * This appears as if some memory moved from one node to another. 3115 * 3116 * So until kernel starts supporting memory hotplug to memory-less 3117 * nodes, just prevent such attempts upfront in QEMU. 3118 */ 3119 if (nb_numa_nodes && !numa_info[node].node_mem) { 3120 error_setg(errp, "Can't hotplug memory to memory-less node %d", 3121 node); 3122 return; 3123 } 3124 3125 spapr_memory_plug(hotplug_dev, dev, node, errp); 3126 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3127 spapr_core_plug(hotplug_dev, dev, errp); 3128 } 3129 } 3130 3131 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 3132 DeviceState *dev, Error **errp) 3133 { 3134 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 3135 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 3136 3137 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3138 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3139 spapr_memory_unplug(hotplug_dev, dev, errp); 3140 } else { 3141 error_setg(errp, "Memory hot unplug not supported for this guest"); 3142 } 3143 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3144 if (!mc->has_hotpluggable_cpus) { 3145 error_setg(errp, "CPU hot unplug not supported on this machine"); 3146 return; 3147 } 3148 spapr_core_unplug(hotplug_dev, dev, errp); 3149 } 3150 } 3151 3152 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3153 DeviceState *dev, Error **errp) 3154 { 3155 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 3156 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 3157 3158 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3159 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3160 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3161 } else { 3162 /* NOTE: this means there is a window after guest reset, prior to 3163 * CAS negotiation, where unplug requests will fail due to the 3164 * capability not being detected yet. This is a bit different than 3165 * the case with PCI unplug, where the events will be queued and 3166 * eventually handled by the guest after boot 3167 */ 3168 error_setg(errp, "Memory hot unplug not supported for this guest"); 3169 } 3170 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3171 if (!mc->has_hotpluggable_cpus) { 3172 error_setg(errp, "CPU hot unplug not supported on this machine"); 3173 return; 3174 } 3175 spapr_core_unplug_request(hotplug_dev, dev, errp); 3176 } 3177 } 3178 3179 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3180 DeviceState *dev, Error **errp) 3181 { 3182 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3183 spapr_memory_pre_plug(hotplug_dev, dev, errp); 3184 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3185 spapr_core_pre_plug(hotplug_dev, dev, errp); 3186 } 3187 } 3188 3189 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3190 DeviceState *dev) 3191 { 3192 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3193 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3194 return HOTPLUG_HANDLER(machine); 3195 } 3196 return NULL; 3197 } 3198 3199 static CpuInstanceProperties 3200 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3201 { 3202 CPUArchId *core_slot; 3203 MachineClass *mc = MACHINE_GET_CLASS(machine); 3204 3205 /* make sure possible_cpu are intialized */ 3206 mc->possible_cpu_arch_ids(machine); 3207 /* get CPU core slot containing thread that matches cpu_index */ 3208 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3209 assert(core_slot); 3210 return core_slot->props; 3211 } 3212 3213 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3214 { 3215 int i; 3216 int spapr_max_cores = max_cpus / smp_threads; 3217 MachineClass *mc = MACHINE_GET_CLASS(machine); 3218 3219 if (!mc->has_hotpluggable_cpus) { 3220 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3221 } 3222 if (machine->possible_cpus) { 3223 assert(machine->possible_cpus->len == spapr_max_cores); 3224 return machine->possible_cpus; 3225 } 3226 3227 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3228 sizeof(CPUArchId) * spapr_max_cores); 3229 machine->possible_cpus->len = spapr_max_cores; 3230 for (i = 0; i < machine->possible_cpus->len; i++) { 3231 int core_id = i * smp_threads; 3232 3233 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3234 machine->possible_cpus->cpus[i].arch_id = core_id; 3235 machine->possible_cpus->cpus[i].props.has_core_id = true; 3236 machine->possible_cpus->cpus[i].props.core_id = core_id; 3237 3238 /* default distribution of CPUs over NUMA nodes */ 3239 if (nb_numa_nodes) { 3240 /* preset values but do not enable them i.e. 'has_node_id = false', 3241 * numa init code will enable them later if manual mapping wasn't 3242 * present on CLI */ 3243 machine->possible_cpus->cpus[i].props.node_id = 3244 core_id / smp_threads / smp_cores % nb_numa_nodes; 3245 } 3246 } 3247 return machine->possible_cpus; 3248 } 3249 3250 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3251 uint64_t *buid, hwaddr *pio, 3252 hwaddr *mmio32, hwaddr *mmio64, 3253 unsigned n_dma, uint32_t *liobns, Error **errp) 3254 { 3255 /* 3256 * New-style PHB window placement. 3257 * 3258 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3259 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3260 * windows. 3261 * 3262 * Some guest kernels can't work with MMIO windows above 1<<46 3263 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3264 * 3265 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3266 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3267 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3268 * 1TiB 64-bit MMIO windows for each PHB. 3269 */ 3270 const uint64_t base_buid = 0x800000020000000ULL; 3271 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3272 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3273 int i; 3274 3275 /* Sanity check natural alignments */ 3276 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3277 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3278 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3279 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3280 /* Sanity check bounds */ 3281 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3282 SPAPR_PCI_MEM32_WIN_SIZE); 3283 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3284 SPAPR_PCI_MEM64_WIN_SIZE); 3285 3286 if (index >= SPAPR_MAX_PHBS) { 3287 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3288 SPAPR_MAX_PHBS - 1); 3289 return; 3290 } 3291 3292 *buid = base_buid + index; 3293 for (i = 0; i < n_dma; ++i) { 3294 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3295 } 3296 3297 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3298 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3299 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3300 } 3301 3302 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3303 { 3304 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3305 3306 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3307 } 3308 3309 static void spapr_ics_resend(XICSFabric *dev) 3310 { 3311 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3312 3313 ics_resend(spapr->ics); 3314 } 3315 3316 static ICPState *spapr_icp_get(XICSFabric *xi, int cpu_dt_id) 3317 { 3318 PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id); 3319 3320 return cpu ? ICP(cpu->intc) : NULL; 3321 } 3322 3323 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3324 Monitor *mon) 3325 { 3326 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3327 CPUState *cs; 3328 3329 CPU_FOREACH(cs) { 3330 PowerPCCPU *cpu = POWERPC_CPU(cs); 3331 3332 icp_pic_print_info(ICP(cpu->intc), mon); 3333 } 3334 3335 ics_pic_print_info(spapr->ics, mon); 3336 } 3337 3338 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3339 { 3340 MachineClass *mc = MACHINE_CLASS(oc); 3341 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3342 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3343 NMIClass *nc = NMI_CLASS(oc); 3344 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3345 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3346 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3347 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3348 3349 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3350 3351 /* 3352 * We set up the default / latest behaviour here. The class_init 3353 * functions for the specific versioned machine types can override 3354 * these details for backwards compatibility 3355 */ 3356 mc->init = ppc_spapr_init; 3357 mc->reset = ppc_spapr_reset; 3358 mc->block_default_type = IF_SCSI; 3359 mc->max_cpus = 1024; 3360 mc->no_parallel = 1; 3361 mc->default_boot_order = ""; 3362 mc->default_ram_size = 512 * M_BYTE; 3363 mc->kvm_type = spapr_kvm_type; 3364 mc->has_dynamic_sysbus = true; 3365 mc->pci_allow_0_address = true; 3366 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3367 hc->pre_plug = spapr_machine_device_pre_plug; 3368 hc->plug = spapr_machine_device_plug; 3369 hc->unplug = spapr_machine_device_unplug; 3370 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 3371 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3372 hc->unplug_request = spapr_machine_device_unplug_request; 3373 3374 smc->dr_lmb_enabled = true; 3375 smc->tcg_default_cpu = "POWER8"; 3376 mc->has_hotpluggable_cpus = true; 3377 fwc->get_dev_path = spapr_get_fw_dev_path; 3378 nc->nmi_monitor_handler = spapr_nmi; 3379 smc->phb_placement = spapr_phb_placement; 3380 vhc->hypercall = emulate_spapr_hypercall; 3381 vhc->hpt_mask = spapr_hpt_mask; 3382 vhc->map_hptes = spapr_map_hptes; 3383 vhc->unmap_hptes = spapr_unmap_hptes; 3384 vhc->store_hpte = spapr_store_hpte; 3385 vhc->get_patbe = spapr_get_patbe; 3386 xic->ics_get = spapr_ics_get; 3387 xic->ics_resend = spapr_ics_resend; 3388 xic->icp_get = spapr_icp_get; 3389 ispc->print_info = spapr_pic_print_info; 3390 /* Force NUMA node memory size to be a multiple of 3391 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 3392 * in which LMBs are represented and hot-added 3393 */ 3394 mc->numa_mem_align_shift = 28; 3395 } 3396 3397 static const TypeInfo spapr_machine_info = { 3398 .name = TYPE_SPAPR_MACHINE, 3399 .parent = TYPE_MACHINE, 3400 .abstract = true, 3401 .instance_size = sizeof(sPAPRMachineState), 3402 .instance_init = spapr_machine_initfn, 3403 .instance_finalize = spapr_machine_finalizefn, 3404 .class_size = sizeof(sPAPRMachineClass), 3405 .class_init = spapr_machine_class_init, 3406 .interfaces = (InterfaceInfo[]) { 3407 { TYPE_FW_PATH_PROVIDER }, 3408 { TYPE_NMI }, 3409 { TYPE_HOTPLUG_HANDLER }, 3410 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3411 { TYPE_XICS_FABRIC }, 3412 { TYPE_INTERRUPT_STATS_PROVIDER }, 3413 { } 3414 }, 3415 }; 3416 3417 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3418 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3419 void *data) \ 3420 { \ 3421 MachineClass *mc = MACHINE_CLASS(oc); \ 3422 spapr_machine_##suffix##_class_options(mc); \ 3423 if (latest) { \ 3424 mc->alias = "pseries"; \ 3425 mc->is_default = 1; \ 3426 } \ 3427 } \ 3428 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3429 { \ 3430 MachineState *machine = MACHINE(obj); \ 3431 spapr_machine_##suffix##_instance_options(machine); \ 3432 } \ 3433 static const TypeInfo spapr_machine_##suffix##_info = { \ 3434 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3435 .parent = TYPE_SPAPR_MACHINE, \ 3436 .class_init = spapr_machine_##suffix##_class_init, \ 3437 .instance_init = spapr_machine_##suffix##_instance_init, \ 3438 }; \ 3439 static void spapr_machine_register_##suffix(void) \ 3440 { \ 3441 type_register(&spapr_machine_##suffix##_info); \ 3442 } \ 3443 type_init(spapr_machine_register_##suffix) 3444 3445 /* 3446 * pseries-2.10 3447 */ 3448 static void spapr_machine_2_10_instance_options(MachineState *machine) 3449 { 3450 } 3451 3452 static void spapr_machine_2_10_class_options(MachineClass *mc) 3453 { 3454 /* Defaults for the latest behaviour inherited from the base class */ 3455 } 3456 3457 DEFINE_SPAPR_MACHINE(2_10, "2.10", true); 3458 3459 /* 3460 * pseries-2.9 3461 */ 3462 #define SPAPR_COMPAT_2_9 \ 3463 HW_COMPAT_2_9 \ 3464 { \ 3465 .driver = TYPE_POWERPC_CPU, \ 3466 .property = "pre-2.10-migration", \ 3467 .value = "on", \ 3468 }, \ 3469 3470 static void spapr_machine_2_9_instance_options(MachineState *machine) 3471 { 3472 spapr_machine_2_10_instance_options(machine); 3473 } 3474 3475 static void spapr_machine_2_9_class_options(MachineClass *mc) 3476 { 3477 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3478 3479 spapr_machine_2_10_class_options(mc); 3480 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); 3481 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 3482 smc->pre_2_10_has_unused_icps = true; 3483 } 3484 3485 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 3486 3487 /* 3488 * pseries-2.8 3489 */ 3490 #define SPAPR_COMPAT_2_8 \ 3491 HW_COMPAT_2_8 \ 3492 { \ 3493 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3494 .property = "pcie-extended-configuration-space", \ 3495 .value = "off", \ 3496 }, 3497 3498 static void spapr_machine_2_8_instance_options(MachineState *machine) 3499 { 3500 spapr_machine_2_9_instance_options(machine); 3501 } 3502 3503 static void spapr_machine_2_8_class_options(MachineClass *mc) 3504 { 3505 spapr_machine_2_9_class_options(mc); 3506 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 3507 mc->numa_mem_align_shift = 23; 3508 } 3509 3510 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 3511 3512 /* 3513 * pseries-2.7 3514 */ 3515 #define SPAPR_COMPAT_2_7 \ 3516 HW_COMPAT_2_7 \ 3517 { \ 3518 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3519 .property = "mem_win_size", \ 3520 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 3521 }, \ 3522 { \ 3523 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3524 .property = "mem64_win_size", \ 3525 .value = "0", \ 3526 }, \ 3527 { \ 3528 .driver = TYPE_POWERPC_CPU, \ 3529 .property = "pre-2.8-migration", \ 3530 .value = "on", \ 3531 }, \ 3532 { \ 3533 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3534 .property = "pre-2.8-migration", \ 3535 .value = "on", \ 3536 }, 3537 3538 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 3539 uint64_t *buid, hwaddr *pio, 3540 hwaddr *mmio32, hwaddr *mmio64, 3541 unsigned n_dma, uint32_t *liobns, Error **errp) 3542 { 3543 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 3544 const uint64_t base_buid = 0x800000020000000ULL; 3545 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 3546 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 3547 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 3548 const uint32_t max_index = 255; 3549 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 3550 3551 uint64_t ram_top = MACHINE(spapr)->ram_size; 3552 hwaddr phb0_base, phb_base; 3553 int i; 3554 3555 /* Do we have hotpluggable memory? */ 3556 if (MACHINE(spapr)->maxram_size > ram_top) { 3557 /* Can't just use maxram_size, because there may be an 3558 * alignment gap between normal and hotpluggable memory 3559 * regions */ 3560 ram_top = spapr->hotplug_memory.base + 3561 memory_region_size(&spapr->hotplug_memory.mr); 3562 } 3563 3564 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 3565 3566 if (index > max_index) { 3567 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 3568 max_index); 3569 return; 3570 } 3571 3572 *buid = base_buid + index; 3573 for (i = 0; i < n_dma; ++i) { 3574 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3575 } 3576 3577 phb_base = phb0_base + index * phb_spacing; 3578 *pio = phb_base + pio_offset; 3579 *mmio32 = phb_base + mmio_offset; 3580 /* 3581 * We don't set the 64-bit MMIO window, relying on the PHB's 3582 * fallback behaviour of automatically splitting a large "32-bit" 3583 * window into contiguous 32-bit and 64-bit windows 3584 */ 3585 } 3586 3587 static void spapr_machine_2_7_instance_options(MachineState *machine) 3588 { 3589 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 3590 3591 spapr_machine_2_8_instance_options(machine); 3592 spapr->use_hotplug_event_source = false; 3593 } 3594 3595 static void spapr_machine_2_7_class_options(MachineClass *mc) 3596 { 3597 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3598 3599 spapr_machine_2_8_class_options(mc); 3600 smc->tcg_default_cpu = "POWER7"; 3601 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 3602 smc->phb_placement = phb_placement_2_7; 3603 } 3604 3605 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 3606 3607 /* 3608 * pseries-2.6 3609 */ 3610 #define SPAPR_COMPAT_2_6 \ 3611 HW_COMPAT_2_6 \ 3612 { \ 3613 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3614 .property = "ddw",\ 3615 .value = stringify(off),\ 3616 }, 3617 3618 static void spapr_machine_2_6_instance_options(MachineState *machine) 3619 { 3620 spapr_machine_2_7_instance_options(machine); 3621 } 3622 3623 static void spapr_machine_2_6_class_options(MachineClass *mc) 3624 { 3625 spapr_machine_2_7_class_options(mc); 3626 mc->has_hotpluggable_cpus = false; 3627 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 3628 } 3629 3630 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 3631 3632 /* 3633 * pseries-2.5 3634 */ 3635 #define SPAPR_COMPAT_2_5 \ 3636 HW_COMPAT_2_5 \ 3637 { \ 3638 .driver = "spapr-vlan", \ 3639 .property = "use-rx-buffer-pools", \ 3640 .value = "off", \ 3641 }, 3642 3643 static void spapr_machine_2_5_instance_options(MachineState *machine) 3644 { 3645 spapr_machine_2_6_instance_options(machine); 3646 } 3647 3648 static void spapr_machine_2_5_class_options(MachineClass *mc) 3649 { 3650 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3651 3652 spapr_machine_2_6_class_options(mc); 3653 smc->use_ohci_by_default = true; 3654 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 3655 } 3656 3657 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 3658 3659 /* 3660 * pseries-2.4 3661 */ 3662 #define SPAPR_COMPAT_2_4 \ 3663 HW_COMPAT_2_4 3664 3665 static void spapr_machine_2_4_instance_options(MachineState *machine) 3666 { 3667 spapr_machine_2_5_instance_options(machine); 3668 } 3669 3670 static void spapr_machine_2_4_class_options(MachineClass *mc) 3671 { 3672 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3673 3674 spapr_machine_2_5_class_options(mc); 3675 smc->dr_lmb_enabled = false; 3676 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 3677 } 3678 3679 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 3680 3681 /* 3682 * pseries-2.3 3683 */ 3684 #define SPAPR_COMPAT_2_3 \ 3685 HW_COMPAT_2_3 \ 3686 {\ 3687 .driver = "spapr-pci-host-bridge",\ 3688 .property = "dynamic-reconfiguration",\ 3689 .value = "off",\ 3690 }, 3691 3692 static void spapr_machine_2_3_instance_options(MachineState *machine) 3693 { 3694 spapr_machine_2_4_instance_options(machine); 3695 } 3696 3697 static void spapr_machine_2_3_class_options(MachineClass *mc) 3698 { 3699 spapr_machine_2_4_class_options(mc); 3700 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 3701 } 3702 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 3703 3704 /* 3705 * pseries-2.2 3706 */ 3707 3708 #define SPAPR_COMPAT_2_2 \ 3709 HW_COMPAT_2_2 \ 3710 {\ 3711 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3712 .property = "mem_win_size",\ 3713 .value = "0x20000000",\ 3714 }, 3715 3716 static void spapr_machine_2_2_instance_options(MachineState *machine) 3717 { 3718 spapr_machine_2_3_instance_options(machine); 3719 machine->suppress_vmdesc = true; 3720 } 3721 3722 static void spapr_machine_2_2_class_options(MachineClass *mc) 3723 { 3724 spapr_machine_2_3_class_options(mc); 3725 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 3726 } 3727 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 3728 3729 /* 3730 * pseries-2.1 3731 */ 3732 #define SPAPR_COMPAT_2_1 \ 3733 HW_COMPAT_2_1 3734 3735 static void spapr_machine_2_1_instance_options(MachineState *machine) 3736 { 3737 spapr_machine_2_2_instance_options(machine); 3738 } 3739 3740 static void spapr_machine_2_1_class_options(MachineClass *mc) 3741 { 3742 spapr_machine_2_2_class_options(mc); 3743 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 3744 } 3745 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 3746 3747 static void spapr_machine_register_types(void) 3748 { 3749 type_register_static(&spapr_machine_info); 3750 } 3751 3752 type_init(spapr_machine_register_types) 3753