1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/numa.h" 31 #include "hw/hw.h" 32 #include "qemu/log.h" 33 #include "hw/fw-path-provider.h" 34 #include "elf.h" 35 #include "net/net.h" 36 #include "sysemu/device_tree.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/migration.h" 42 #include "mmu-hash64.h" 43 #include "mmu-book3s-v3.h" 44 #include "qom/cpu.h" 45 46 #include "hw/boards.h" 47 #include "hw/ppc/ppc.h" 48 #include "hw/loader.h" 49 50 #include "hw/ppc/fdt.h" 51 #include "hw/ppc/spapr.h" 52 #include "hw/ppc/spapr_vio.h" 53 #include "hw/pci-host/spapr.h" 54 #include "hw/ppc/xics.h" 55 #include "hw/pci/msi.h" 56 57 #include "hw/pci/pci.h" 58 #include "hw/scsi/scsi.h" 59 #include "hw/virtio/virtio-scsi.h" 60 61 #include "exec/address-spaces.h" 62 #include "hw/usb.h" 63 #include "qemu/config-file.h" 64 #include "qemu/error-report.h" 65 #include "trace.h" 66 #include "hw/nmi.h" 67 #include "hw/intc/intc.h" 68 69 #include "hw/compat.h" 70 #include "qemu/cutils.h" 71 #include "hw/ppc/spapr_cpu_core.h" 72 #include "qmp-commands.h" 73 74 #include <libfdt.h> 75 76 /* SLOF memory layout: 77 * 78 * SLOF raw image loaded at 0, copies its romfs right below the flat 79 * device-tree, then position SLOF itself 31M below that 80 * 81 * So we set FW_OVERHEAD to 40MB which should account for all of that 82 * and more 83 * 84 * We load our kernel at 4M, leaving space for SLOF initial image 85 */ 86 #define FDT_MAX_SIZE 0x100000 87 #define RTAS_MAX_SIZE 0x10000 88 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 89 #define FW_MAX_SIZE 0x400000 90 #define FW_FILE_NAME "slof.bin" 91 #define FW_OVERHEAD 0x2800000 92 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 93 94 #define MIN_RMA_SLOF 128UL 95 96 #define PHANDLE_XICP 0x00001111 97 98 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 99 100 static int try_create_xics(sPAPRMachineState *spapr, const char *type_ics, 101 const char *type_icp, int nr_servers, 102 int nr_irqs, Error **errp) 103 { 104 XICSFabric *xi = XICS_FABRIC(spapr); 105 Error *err = NULL, *local_err = NULL; 106 ICSState *ics = NULL; 107 108 ics = ICS_SIMPLE(object_new(type_ics)); 109 object_property_add_child(OBJECT(spapr), "ics", OBJECT(ics), NULL); 110 object_property_set_int(OBJECT(ics), nr_irqs, "nr-irqs", &err); 111 object_property_add_const_link(OBJECT(ics), "xics", OBJECT(xi), NULL); 112 object_property_set_bool(OBJECT(ics), true, "realized", &local_err); 113 error_propagate(&err, local_err); 114 if (err) { 115 error_propagate(errp, err); 116 return -1; 117 } 118 119 spapr->nr_servers = nr_servers; 120 spapr->ics = ics; 121 spapr->icp_type = type_icp; 122 return 0; 123 } 124 125 static int xics_system_init(MachineState *machine, 126 int nr_servers, int nr_irqs, Error **errp) 127 { 128 int rc = -1; 129 130 if (kvm_enabled()) { 131 Error *err = NULL; 132 133 if (machine_kernel_irqchip_allowed(machine) && 134 !xics_kvm_init(SPAPR_MACHINE(machine), errp)) { 135 rc = try_create_xics(SPAPR_MACHINE(machine), TYPE_ICS_KVM, 136 TYPE_KVM_ICP, nr_servers, nr_irqs, &err); 137 } 138 if (machine_kernel_irqchip_required(machine) && rc < 0) { 139 error_reportf_err(err, 140 "kernel_irqchip requested but unavailable: "); 141 } else { 142 error_free(err); 143 } 144 } 145 146 if (rc < 0) { 147 xics_spapr_init(SPAPR_MACHINE(machine), errp); 148 rc = try_create_xics(SPAPR_MACHINE(machine), TYPE_ICS_SIMPLE, 149 TYPE_ICP, nr_servers, nr_irqs, errp); 150 } 151 152 return rc; 153 } 154 155 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 156 int smt_threads) 157 { 158 int i, ret = 0; 159 uint32_t servers_prop[smt_threads]; 160 uint32_t gservers_prop[smt_threads * 2]; 161 int index = ppc_get_vcpu_dt_id(cpu); 162 163 if (cpu->compat_pvr) { 164 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 165 if (ret < 0) { 166 return ret; 167 } 168 } 169 170 /* Build interrupt servers and gservers properties */ 171 for (i = 0; i < smt_threads; i++) { 172 servers_prop[i] = cpu_to_be32(index + i); 173 /* Hack, direct the group queues back to cpu 0 */ 174 gservers_prop[i*2] = cpu_to_be32(index + i); 175 gservers_prop[i*2 + 1] = 0; 176 } 177 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 178 servers_prop, sizeof(servers_prop)); 179 if (ret < 0) { 180 return ret; 181 } 182 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 183 gservers_prop, sizeof(gservers_prop)); 184 185 return ret; 186 } 187 188 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) 189 { 190 int ret = 0; 191 PowerPCCPU *cpu = POWERPC_CPU(cs); 192 int index = ppc_get_vcpu_dt_id(cpu); 193 uint32_t associativity[] = {cpu_to_be32(0x5), 194 cpu_to_be32(0x0), 195 cpu_to_be32(0x0), 196 cpu_to_be32(0x0), 197 cpu_to_be32(cs->numa_node), 198 cpu_to_be32(index)}; 199 200 /* Advertise NUMA via ibm,associativity */ 201 if (nb_numa_nodes > 1) { 202 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 203 sizeof(associativity)); 204 } 205 206 return ret; 207 } 208 209 /* Populate the "ibm,pa-features" property */ 210 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset, 211 bool legacy_guest) 212 { 213 uint8_t pa_features_206[] = { 6, 0, 214 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 215 uint8_t pa_features_207[] = { 24, 0, 216 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 217 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 218 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 219 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 220 uint8_t pa_features_300[] = { 66, 0, 221 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 222 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 223 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 224 /* 6: DS207 */ 225 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 226 /* 16: Vector */ 227 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 228 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 229 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ 230 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 231 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 232 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 233 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 234 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 236 /* 42: PM, 44: PC RA, 46: SC vec'd */ 237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 238 /* 48: SIMD, 50: QP BFP, 52: String */ 239 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 240 /* 54: DecFP, 56: DecI, 58: SHA */ 241 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 242 /* 60: NM atomic, 62: RNG */ 243 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 244 }; 245 uint8_t *pa_features; 246 size_t pa_size; 247 248 switch (POWERPC_MMU_VER(env->mmu_model)) { 249 case POWERPC_MMU_VER_2_06: 250 pa_features = pa_features_206; 251 pa_size = sizeof(pa_features_206); 252 break; 253 case POWERPC_MMU_VER_2_07: 254 pa_features = pa_features_207; 255 pa_size = sizeof(pa_features_207); 256 break; 257 case POWERPC_MMU_VER_3_00: 258 pa_features = pa_features_300; 259 pa_size = sizeof(pa_features_300); 260 break; 261 default: 262 return; 263 } 264 265 if (env->ci_large_pages) { 266 /* 267 * Note: we keep CI large pages off by default because a 64K capable 268 * guest provisioned with large pages might otherwise try to map a qemu 269 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 270 * even if that qemu runs on a 4k host. 271 * We dd this bit back here if we are confident this is not an issue 272 */ 273 pa_features[3] |= 0x20; 274 } 275 if (kvmppc_has_cap_htm() && pa_size > 24) { 276 pa_features[24] |= 0x80; /* Transactional memory support */ 277 } 278 if (legacy_guest && pa_size > 40) { 279 /* Workaround for broken kernels that attempt (guest) radix 280 * mode when they can't handle it, if they see the radix bit set 281 * in pa-features. So hide it from them. */ 282 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 283 } 284 285 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 286 } 287 288 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 289 { 290 int ret = 0, offset, cpus_offset; 291 CPUState *cs; 292 char cpu_model[32]; 293 int smt = kvmppc_smt_threads(); 294 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 295 296 CPU_FOREACH(cs) { 297 PowerPCCPU *cpu = POWERPC_CPU(cs); 298 CPUPPCState *env = &cpu->env; 299 DeviceClass *dc = DEVICE_GET_CLASS(cs); 300 int index = ppc_get_vcpu_dt_id(cpu); 301 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 302 303 if ((index % smt) != 0) { 304 continue; 305 } 306 307 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 308 309 cpus_offset = fdt_path_offset(fdt, "/cpus"); 310 if (cpus_offset < 0) { 311 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 312 "cpus"); 313 if (cpus_offset < 0) { 314 return cpus_offset; 315 } 316 } 317 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 318 if (offset < 0) { 319 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 320 if (offset < 0) { 321 return offset; 322 } 323 } 324 325 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 326 pft_size_prop, sizeof(pft_size_prop)); 327 if (ret < 0) { 328 return ret; 329 } 330 331 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); 332 if (ret < 0) { 333 return ret; 334 } 335 336 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 337 if (ret < 0) { 338 return ret; 339 } 340 341 spapr_populate_pa_features(env, fdt, offset, 342 spapr->cas_legacy_guest_workaround); 343 } 344 return ret; 345 } 346 347 static hwaddr spapr_node0_size(void) 348 { 349 MachineState *machine = MACHINE(qdev_get_machine()); 350 351 if (nb_numa_nodes) { 352 int i; 353 for (i = 0; i < nb_numa_nodes; ++i) { 354 if (numa_info[i].node_mem) { 355 return MIN(pow2floor(numa_info[i].node_mem), 356 machine->ram_size); 357 } 358 } 359 } 360 return machine->ram_size; 361 } 362 363 static void add_str(GString *s, const gchar *s1) 364 { 365 g_string_append_len(s, s1, strlen(s1) + 1); 366 } 367 368 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 369 hwaddr size) 370 { 371 uint32_t associativity[] = { 372 cpu_to_be32(0x4), /* length */ 373 cpu_to_be32(0x0), cpu_to_be32(0x0), 374 cpu_to_be32(0x0), cpu_to_be32(nodeid) 375 }; 376 char mem_name[32]; 377 uint64_t mem_reg_property[2]; 378 int off; 379 380 mem_reg_property[0] = cpu_to_be64(start); 381 mem_reg_property[1] = cpu_to_be64(size); 382 383 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 384 off = fdt_add_subnode(fdt, 0, mem_name); 385 _FDT(off); 386 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 387 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 388 sizeof(mem_reg_property)))); 389 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 390 sizeof(associativity)))); 391 return off; 392 } 393 394 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 395 { 396 MachineState *machine = MACHINE(spapr); 397 hwaddr mem_start, node_size; 398 int i, nb_nodes = nb_numa_nodes; 399 NodeInfo *nodes = numa_info; 400 NodeInfo ramnode; 401 402 /* No NUMA nodes, assume there is just one node with whole RAM */ 403 if (!nb_numa_nodes) { 404 nb_nodes = 1; 405 ramnode.node_mem = machine->ram_size; 406 nodes = &ramnode; 407 } 408 409 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 410 if (!nodes[i].node_mem) { 411 continue; 412 } 413 if (mem_start >= machine->ram_size) { 414 node_size = 0; 415 } else { 416 node_size = nodes[i].node_mem; 417 if (node_size > machine->ram_size - mem_start) { 418 node_size = machine->ram_size - mem_start; 419 } 420 } 421 if (!mem_start) { 422 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 423 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 424 mem_start += spapr->rma_size; 425 node_size -= spapr->rma_size; 426 } 427 for ( ; node_size; ) { 428 hwaddr sizetmp = pow2floor(node_size); 429 430 /* mem_start != 0 here */ 431 if (ctzl(mem_start) < ctzl(sizetmp)) { 432 sizetmp = 1ULL << ctzl(mem_start); 433 } 434 435 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 436 node_size -= sizetmp; 437 mem_start += sizetmp; 438 } 439 } 440 441 return 0; 442 } 443 444 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 445 sPAPRMachineState *spapr) 446 { 447 PowerPCCPU *cpu = POWERPC_CPU(cs); 448 CPUPPCState *env = &cpu->env; 449 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 450 int index = ppc_get_vcpu_dt_id(cpu); 451 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 452 0xffffffff, 0xffffffff}; 453 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 454 : SPAPR_TIMEBASE_FREQ; 455 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 456 uint32_t page_sizes_prop[64]; 457 size_t page_sizes_prop_size; 458 uint32_t vcpus_per_socket = smp_threads * smp_cores; 459 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 460 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 461 sPAPRDRConnector *drc; 462 sPAPRDRConnectorClass *drck; 463 int drc_index; 464 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 465 int i; 466 467 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index); 468 if (drc) { 469 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 470 drc_index = drck->get_index(drc); 471 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 472 } 473 474 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 475 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 476 477 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 478 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 479 env->dcache_line_size))); 480 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 481 env->dcache_line_size))); 482 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 483 env->icache_line_size))); 484 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 485 env->icache_line_size))); 486 487 if (pcc->l1_dcache_size) { 488 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 489 pcc->l1_dcache_size))); 490 } else { 491 error_report("Warning: Unknown L1 dcache size for cpu"); 492 } 493 if (pcc->l1_icache_size) { 494 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 495 pcc->l1_icache_size))); 496 } else { 497 error_report("Warning: Unknown L1 icache size for cpu"); 498 } 499 500 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 501 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 502 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 503 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 504 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 505 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 506 507 if (env->spr_cb[SPR_PURR].oea_read) { 508 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 509 } 510 511 if (env->mmu_model & POWERPC_MMU_1TSEG) { 512 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 513 segs, sizeof(segs)))); 514 } 515 516 /* Advertise VMX/VSX (vector extensions) if available 517 * 0 / no property == no vector extensions 518 * 1 == VMX / Altivec available 519 * 2 == VSX available */ 520 if (env->insns_flags & PPC_ALTIVEC) { 521 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 522 523 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 524 } 525 526 /* Advertise DFP (Decimal Floating Point) if available 527 * 0 / no property == no DFP 528 * 1 == DFP available */ 529 if (env->insns_flags2 & PPC2_DFP) { 530 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 531 } 532 533 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 534 sizeof(page_sizes_prop)); 535 if (page_sizes_prop_size) { 536 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 537 page_sizes_prop, page_sizes_prop_size))); 538 } 539 540 spapr_populate_pa_features(env, fdt, offset, false); 541 542 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 543 cs->cpu_index / vcpus_per_socket))); 544 545 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 546 pft_size_prop, sizeof(pft_size_prop)))); 547 548 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); 549 550 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 551 552 if (pcc->radix_page_info) { 553 for (i = 0; i < pcc->radix_page_info->count; i++) { 554 radix_AP_encodings[i] = 555 cpu_to_be32(pcc->radix_page_info->entries[i]); 556 } 557 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 558 radix_AP_encodings, 559 pcc->radix_page_info->count * 560 sizeof(radix_AP_encodings[0])))); 561 } 562 } 563 564 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 565 { 566 CPUState *cs; 567 int cpus_offset; 568 char *nodename; 569 int smt = kvmppc_smt_threads(); 570 571 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 572 _FDT(cpus_offset); 573 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 574 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 575 576 /* 577 * We walk the CPUs in reverse order to ensure that CPU DT nodes 578 * created by fdt_add_subnode() end up in the right order in FDT 579 * for the guest kernel the enumerate the CPUs correctly. 580 */ 581 CPU_FOREACH_REVERSE(cs) { 582 PowerPCCPU *cpu = POWERPC_CPU(cs); 583 int index = ppc_get_vcpu_dt_id(cpu); 584 DeviceClass *dc = DEVICE_GET_CLASS(cs); 585 int offset; 586 587 if ((index % smt) != 0) { 588 continue; 589 } 590 591 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 592 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 593 g_free(nodename); 594 _FDT(offset); 595 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 596 } 597 598 } 599 600 /* 601 * Adds ibm,dynamic-reconfiguration-memory node. 602 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 603 * of this device tree node. 604 */ 605 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 606 { 607 MachineState *machine = MACHINE(spapr); 608 int ret, i, offset; 609 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 610 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 611 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 612 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 613 memory_region_size(&spapr->hotplug_memory.mr)) / 614 lmb_size; 615 uint32_t *int_buf, *cur_index, buf_len; 616 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 617 618 /* 619 * Don't create the node if there is no hotpluggable memory 620 */ 621 if (machine->ram_size == machine->maxram_size) { 622 return 0; 623 } 624 625 /* 626 * Allocate enough buffer size to fit in ibm,dynamic-memory 627 * or ibm,associativity-lookup-arrays 628 */ 629 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 630 * sizeof(uint32_t); 631 cur_index = int_buf = g_malloc0(buf_len); 632 633 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 634 635 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 636 sizeof(prop_lmb_size)); 637 if (ret < 0) { 638 goto out; 639 } 640 641 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 642 if (ret < 0) { 643 goto out; 644 } 645 646 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 647 if (ret < 0) { 648 goto out; 649 } 650 651 /* ibm,dynamic-memory */ 652 int_buf[0] = cpu_to_be32(nr_lmbs); 653 cur_index++; 654 for (i = 0; i < nr_lmbs; i++) { 655 uint64_t addr = i * lmb_size; 656 uint32_t *dynamic_memory = cur_index; 657 658 if (i >= hotplug_lmb_start) { 659 sPAPRDRConnector *drc; 660 sPAPRDRConnectorClass *drck; 661 662 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i); 663 g_assert(drc); 664 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 665 666 dynamic_memory[0] = cpu_to_be32(addr >> 32); 667 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 668 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); 669 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 670 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 671 if (memory_region_present(get_system_memory(), addr)) { 672 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 673 } else { 674 dynamic_memory[5] = cpu_to_be32(0); 675 } 676 } else { 677 /* 678 * LMB information for RMA, boot time RAM and gap b/n RAM and 679 * hotplug memory region -- all these are marked as reserved 680 * and as having no valid DRC. 681 */ 682 dynamic_memory[0] = cpu_to_be32(addr >> 32); 683 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 684 dynamic_memory[2] = cpu_to_be32(0); 685 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 686 dynamic_memory[4] = cpu_to_be32(-1); 687 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 688 SPAPR_LMB_FLAGS_DRC_INVALID); 689 } 690 691 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 692 } 693 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 694 if (ret < 0) { 695 goto out; 696 } 697 698 /* ibm,associativity-lookup-arrays */ 699 cur_index = int_buf; 700 int_buf[0] = cpu_to_be32(nr_nodes); 701 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 702 cur_index += 2; 703 for (i = 0; i < nr_nodes; i++) { 704 uint32_t associativity[] = { 705 cpu_to_be32(0x0), 706 cpu_to_be32(0x0), 707 cpu_to_be32(0x0), 708 cpu_to_be32(i) 709 }; 710 memcpy(cur_index, associativity, sizeof(associativity)); 711 cur_index += 4; 712 } 713 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 714 (cur_index - int_buf) * sizeof(uint32_t)); 715 out: 716 g_free(int_buf); 717 return ret; 718 } 719 720 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 721 sPAPROptionVector *ov5_updates) 722 { 723 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 724 int ret = 0, offset; 725 726 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 727 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 728 g_assert(smc->dr_lmb_enabled); 729 ret = spapr_populate_drconf_memory(spapr, fdt); 730 if (ret) { 731 goto out; 732 } 733 } 734 735 offset = fdt_path_offset(fdt, "/chosen"); 736 if (offset < 0) { 737 offset = fdt_add_subnode(fdt, 0, "chosen"); 738 if (offset < 0) { 739 return offset; 740 } 741 } 742 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 743 "ibm,architecture-vec-5"); 744 745 out: 746 return ret; 747 } 748 749 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 750 target_ulong addr, target_ulong size, 751 sPAPROptionVector *ov5_updates) 752 { 753 void *fdt, *fdt_skel; 754 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 755 756 size -= sizeof(hdr); 757 758 /* Create sceleton */ 759 fdt_skel = g_malloc0(size); 760 _FDT((fdt_create(fdt_skel, size))); 761 _FDT((fdt_begin_node(fdt_skel, ""))); 762 _FDT((fdt_end_node(fdt_skel))); 763 _FDT((fdt_finish(fdt_skel))); 764 fdt = g_malloc0(size); 765 _FDT((fdt_open_into(fdt_skel, fdt, size))); 766 g_free(fdt_skel); 767 768 /* Fixup cpu nodes */ 769 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 770 771 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 772 return -1; 773 } 774 775 /* Pack resulting tree */ 776 _FDT((fdt_pack(fdt))); 777 778 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 779 trace_spapr_cas_failed(size); 780 return -1; 781 } 782 783 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 784 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 785 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 786 g_free(fdt); 787 788 return 0; 789 } 790 791 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 792 { 793 int rtas; 794 GString *hypertas = g_string_sized_new(256); 795 GString *qemu_hypertas = g_string_sized_new(256); 796 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 797 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 798 memory_region_size(&spapr->hotplug_memory.mr); 799 uint32_t lrdr_capacity[] = { 800 cpu_to_be32(max_hotplug_addr >> 32), 801 cpu_to_be32(max_hotplug_addr & 0xffffffff), 802 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 803 cpu_to_be32(max_cpus / smp_threads), 804 }; 805 806 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 807 808 /* hypertas */ 809 add_str(hypertas, "hcall-pft"); 810 add_str(hypertas, "hcall-term"); 811 add_str(hypertas, "hcall-dabr"); 812 add_str(hypertas, "hcall-interrupt"); 813 add_str(hypertas, "hcall-tce"); 814 add_str(hypertas, "hcall-vio"); 815 add_str(hypertas, "hcall-splpar"); 816 add_str(hypertas, "hcall-bulk"); 817 add_str(hypertas, "hcall-set-mode"); 818 add_str(hypertas, "hcall-sprg0"); 819 add_str(hypertas, "hcall-copy"); 820 add_str(hypertas, "hcall-debug"); 821 add_str(qemu_hypertas, "hcall-memop1"); 822 823 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 824 add_str(hypertas, "hcall-multi-tce"); 825 } 826 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 827 hypertas->str, hypertas->len)); 828 g_string_free(hypertas, TRUE); 829 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 830 qemu_hypertas->str, qemu_hypertas->len)); 831 g_string_free(qemu_hypertas, TRUE); 832 833 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 834 refpoints, sizeof(refpoints))); 835 836 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 837 RTAS_ERROR_LOG_MAX)); 838 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 839 RTAS_EVENT_SCAN_RATE)); 840 841 if (msi_nonbroken) { 842 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 843 } 844 845 /* 846 * According to PAPR, rtas ibm,os-term does not guarantee a return 847 * back to the guest cpu. 848 * 849 * While an additional ibm,extended-os-term property indicates 850 * that rtas call return will always occur. Set this property. 851 */ 852 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 853 854 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 855 lrdr_capacity, sizeof(lrdr_capacity))); 856 857 spapr_dt_rtas_tokens(fdt, rtas); 858 } 859 860 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features 861 * that the guest may request and thus the valid values for bytes 24..26 of 862 * option vector 5: */ 863 static void spapr_dt_ov5_platform_support(void *fdt, int chosen) 864 { 865 char val[2 * 3] = { 866 24, 0x00, /* Hash/Radix, filled in below. */ 867 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 868 26, 0x40, /* Radix options: GTSE == yes. */ 869 }; 870 871 if (kvm_enabled()) { 872 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 873 val[1] = 0x80; /* OV5_MMU_BOTH */ 874 } else if (kvmppc_has_cap_mmu_radix()) { 875 val[1] = 0x40; /* OV5_MMU_RADIX_300 */ 876 } else { 877 val[1] = 0x00; /* Hash */ 878 } 879 } else { 880 /* TODO: TCG case, hash */ 881 val[1] = 0x00; 882 } 883 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 884 val, sizeof(val))); 885 } 886 887 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 888 { 889 MachineState *machine = MACHINE(spapr); 890 int chosen; 891 const char *boot_device = machine->boot_order; 892 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 893 size_t cb = 0; 894 char *bootlist = get_boot_devices_list(&cb, true); 895 896 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 897 898 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 899 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 900 spapr->initrd_base)); 901 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 902 spapr->initrd_base + spapr->initrd_size)); 903 904 if (spapr->kernel_size) { 905 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 906 cpu_to_be64(spapr->kernel_size) }; 907 908 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 909 &kprop, sizeof(kprop))); 910 if (spapr->kernel_le) { 911 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 912 } 913 } 914 if (boot_menu) { 915 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 916 } 917 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 918 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 919 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 920 921 if (cb && bootlist) { 922 int i; 923 924 for (i = 0; i < cb; i++) { 925 if (bootlist[i] == '\n') { 926 bootlist[i] = ' '; 927 } 928 } 929 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 930 } 931 932 if (boot_device && strlen(boot_device)) { 933 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 934 } 935 936 if (!spapr->has_graphics && stdout_path) { 937 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 938 } 939 940 spapr_dt_ov5_platform_support(fdt, chosen); 941 942 g_free(stdout_path); 943 g_free(bootlist); 944 } 945 946 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 947 { 948 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 949 * KVM to work under pHyp with some guest co-operation */ 950 int hypervisor; 951 uint8_t hypercall[16]; 952 953 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 954 /* indicate KVM hypercall interface */ 955 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 956 if (kvmppc_has_cap_fixup_hcalls()) { 957 /* 958 * Older KVM versions with older guest kernels were broken 959 * with the magic page, don't allow the guest to map it. 960 */ 961 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 962 sizeof(hypercall))) { 963 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 964 hypercall, sizeof(hypercall))); 965 } 966 } 967 } 968 969 static void *spapr_build_fdt(sPAPRMachineState *spapr, 970 hwaddr rtas_addr, 971 hwaddr rtas_size) 972 { 973 MachineState *machine = MACHINE(qdev_get_machine()); 974 MachineClass *mc = MACHINE_GET_CLASS(machine); 975 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 976 int ret; 977 void *fdt; 978 sPAPRPHBState *phb; 979 char *buf; 980 981 fdt = g_malloc0(FDT_MAX_SIZE); 982 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 983 984 /* Root node */ 985 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 986 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 987 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 988 989 /* 990 * Add info to guest to indentify which host is it being run on 991 * and what is the uuid of the guest 992 */ 993 if (kvmppc_get_host_model(&buf)) { 994 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 995 g_free(buf); 996 } 997 if (kvmppc_get_host_serial(&buf)) { 998 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 999 g_free(buf); 1000 } 1001 1002 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1003 1004 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1005 if (qemu_uuid_set) { 1006 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1007 } 1008 g_free(buf); 1009 1010 if (qemu_get_vm_name()) { 1011 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1012 qemu_get_vm_name())); 1013 } 1014 1015 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1016 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1017 1018 /* /interrupt controller */ 1019 spapr_dt_xics(spapr->nr_servers, fdt, PHANDLE_XICP); 1020 1021 ret = spapr_populate_memory(spapr, fdt); 1022 if (ret < 0) { 1023 error_report("couldn't setup memory nodes in fdt"); 1024 exit(1); 1025 } 1026 1027 /* /vdevice */ 1028 spapr_dt_vdevice(spapr->vio_bus, fdt); 1029 1030 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1031 ret = spapr_rng_populate_dt(fdt); 1032 if (ret < 0) { 1033 error_report("could not set up rng device in the fdt"); 1034 exit(1); 1035 } 1036 } 1037 1038 QLIST_FOREACH(phb, &spapr->phbs, list) { 1039 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 1040 if (ret < 0) { 1041 error_report("couldn't setup PCI devices in fdt"); 1042 exit(1); 1043 } 1044 } 1045 1046 /* cpus */ 1047 spapr_populate_cpus_dt_node(fdt, spapr); 1048 1049 if (smc->dr_lmb_enabled) { 1050 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1051 } 1052 1053 if (mc->has_hotpluggable_cpus) { 1054 int offset = fdt_path_offset(fdt, "/cpus"); 1055 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1056 SPAPR_DR_CONNECTOR_TYPE_CPU); 1057 if (ret < 0) { 1058 error_report("Couldn't set up CPU DR device tree properties"); 1059 exit(1); 1060 } 1061 } 1062 1063 /* /event-sources */ 1064 spapr_dt_events(spapr, fdt); 1065 1066 /* /rtas */ 1067 spapr_dt_rtas(spapr, fdt); 1068 1069 /* /chosen */ 1070 spapr_dt_chosen(spapr, fdt); 1071 1072 /* /hypervisor */ 1073 if (kvm_enabled()) { 1074 spapr_dt_hypervisor(spapr, fdt); 1075 } 1076 1077 /* Build memory reserve map */ 1078 if (spapr->kernel_size) { 1079 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1080 } 1081 if (spapr->initrd_size) { 1082 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1083 } 1084 1085 /* ibm,client-architecture-support updates */ 1086 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1087 if (ret < 0) { 1088 error_report("couldn't setup CAS properties fdt"); 1089 exit(1); 1090 } 1091 1092 return fdt; 1093 } 1094 1095 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1096 { 1097 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1098 } 1099 1100 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1101 PowerPCCPU *cpu) 1102 { 1103 CPUPPCState *env = &cpu->env; 1104 1105 /* The TCG path should also be holding the BQL at this point */ 1106 g_assert(qemu_mutex_iothread_locked()); 1107 1108 if (msr_pr) { 1109 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1110 env->gpr[3] = H_PRIVILEGE; 1111 } else { 1112 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1113 } 1114 } 1115 1116 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1117 { 1118 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1119 1120 return spapr->patb_entry; 1121 } 1122 1123 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1124 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1125 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1126 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1127 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1128 1129 /* 1130 * Get the fd to access the kernel htab, re-opening it if necessary 1131 */ 1132 static int get_htab_fd(sPAPRMachineState *spapr) 1133 { 1134 if (spapr->htab_fd >= 0) { 1135 return spapr->htab_fd; 1136 } 1137 1138 spapr->htab_fd = kvmppc_get_htab_fd(false); 1139 if (spapr->htab_fd < 0) { 1140 error_report("Unable to open fd for reading hash table from KVM: %s", 1141 strerror(errno)); 1142 } 1143 1144 return spapr->htab_fd; 1145 } 1146 1147 void close_htab_fd(sPAPRMachineState *spapr) 1148 { 1149 if (spapr->htab_fd >= 0) { 1150 close(spapr->htab_fd); 1151 } 1152 spapr->htab_fd = -1; 1153 } 1154 1155 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1156 { 1157 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1158 1159 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1160 } 1161 1162 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1163 hwaddr ptex, int n) 1164 { 1165 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1166 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1167 1168 if (!spapr->htab) { 1169 /* 1170 * HTAB is controlled by KVM. Fetch into temporary buffer 1171 */ 1172 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1173 kvmppc_read_hptes(hptes, ptex, n); 1174 return hptes; 1175 } 1176 1177 /* 1178 * HTAB is controlled by QEMU. Just point to the internally 1179 * accessible PTEG. 1180 */ 1181 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1182 } 1183 1184 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1185 const ppc_hash_pte64_t *hptes, 1186 hwaddr ptex, int n) 1187 { 1188 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1189 1190 if (!spapr->htab) { 1191 g_free((void *)hptes); 1192 } 1193 1194 /* Nothing to do for qemu managed HPT */ 1195 } 1196 1197 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1198 uint64_t pte0, uint64_t pte1) 1199 { 1200 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1201 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1202 1203 if (!spapr->htab) { 1204 kvmppc_write_hpte(ptex, pte0, pte1); 1205 } else { 1206 stq_p(spapr->htab + offset, pte0); 1207 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1208 } 1209 } 1210 1211 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1212 { 1213 int shift; 1214 1215 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1216 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1217 * that's much more than is needed for Linux guests */ 1218 shift = ctz64(pow2ceil(ramsize)) - 7; 1219 shift = MAX(shift, 18); /* Minimum architected size */ 1220 shift = MIN(shift, 46); /* Maximum architected size */ 1221 return shift; 1222 } 1223 1224 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1225 Error **errp) 1226 { 1227 long rc; 1228 1229 /* Clean up any HPT info from a previous boot */ 1230 g_free(spapr->htab); 1231 spapr->htab = NULL; 1232 spapr->htab_shift = 0; 1233 close_htab_fd(spapr); 1234 1235 rc = kvmppc_reset_htab(shift); 1236 if (rc < 0) { 1237 /* kernel-side HPT needed, but couldn't allocate one */ 1238 error_setg_errno(errp, errno, 1239 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1240 shift); 1241 /* This is almost certainly fatal, but if the caller really 1242 * wants to carry on with shift == 0, it's welcome to try */ 1243 } else if (rc > 0) { 1244 /* kernel-side HPT allocated */ 1245 if (rc != shift) { 1246 error_setg(errp, 1247 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1248 shift, rc); 1249 } 1250 1251 spapr->htab_shift = shift; 1252 spapr->htab = NULL; 1253 } else { 1254 /* kernel-side HPT not needed, allocate in userspace instead */ 1255 size_t size = 1ULL << shift; 1256 int i; 1257 1258 spapr->htab = qemu_memalign(size, size); 1259 if (!spapr->htab) { 1260 error_setg_errno(errp, errno, 1261 "Could not allocate HPT of order %d", shift); 1262 return; 1263 } 1264 1265 memset(spapr->htab, 0, size); 1266 spapr->htab_shift = shift; 1267 1268 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1269 DIRTY_HPTE(HPTE(spapr->htab, i)); 1270 } 1271 } 1272 } 1273 1274 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1275 { 1276 spapr_reallocate_hpt(spapr, 1277 spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size), 1278 &error_fatal); 1279 if (spapr->vrma_adjust) { 1280 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1281 spapr->htab_shift); 1282 } 1283 /* We're setting up a hash table, so that means we're not radix */ 1284 spapr->patb_entry = 0; 1285 } 1286 1287 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1288 { 1289 bool matched = false; 1290 1291 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1292 matched = true; 1293 } 1294 1295 if (!matched) { 1296 error_report("Device %s is not supported by this machine yet.", 1297 qdev_fw_name(DEVICE(sbdev))); 1298 exit(1); 1299 } 1300 } 1301 1302 static void ppc_spapr_reset(void) 1303 { 1304 MachineState *machine = MACHINE(qdev_get_machine()); 1305 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1306 PowerPCCPU *first_ppc_cpu; 1307 uint32_t rtas_limit; 1308 hwaddr rtas_addr, fdt_addr; 1309 void *fdt; 1310 int rc; 1311 1312 /* Check for unknown sysbus devices */ 1313 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1314 1315 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()) { 1316 /* If using KVM with radix mode available, VCPUs can be started 1317 * without a HPT because KVM will start them in radix mode. 1318 * Set the GR bit in PATB so that we know there is no HPT. */ 1319 spapr->patb_entry = PATBE1_GR; 1320 } else { 1321 spapr->patb_entry = 0; 1322 spapr_setup_hpt_and_vrma(spapr); 1323 } 1324 1325 qemu_devices_reset(); 1326 1327 /* 1328 * We place the device tree and RTAS just below either the top of the RMA, 1329 * or just below 2GB, whichever is lowere, so that it can be 1330 * processed with 32-bit real mode code if necessary 1331 */ 1332 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1333 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1334 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1335 1336 /* if this reset wasn't generated by CAS, we should reset our 1337 * negotiated options and start from scratch */ 1338 if (!spapr->cas_reboot) { 1339 spapr_ovec_cleanup(spapr->ov5_cas); 1340 spapr->ov5_cas = spapr_ovec_new(); 1341 } 1342 1343 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1344 1345 spapr_load_rtas(spapr, fdt, rtas_addr); 1346 1347 rc = fdt_pack(fdt); 1348 1349 /* Should only fail if we've built a corrupted tree */ 1350 assert(rc == 0); 1351 1352 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1353 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1354 fdt_totalsize(fdt), FDT_MAX_SIZE); 1355 exit(1); 1356 } 1357 1358 /* Load the fdt */ 1359 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1360 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1361 g_free(fdt); 1362 1363 /* Set up the entry state */ 1364 first_ppc_cpu = POWERPC_CPU(first_cpu); 1365 first_ppc_cpu->env.gpr[3] = fdt_addr; 1366 first_ppc_cpu->env.gpr[5] = 0; 1367 first_cpu->halted = 0; 1368 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1369 1370 spapr->cas_reboot = false; 1371 } 1372 1373 static void spapr_create_nvram(sPAPRMachineState *spapr) 1374 { 1375 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1376 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1377 1378 if (dinfo) { 1379 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1380 &error_fatal); 1381 } 1382 1383 qdev_init_nofail(dev); 1384 1385 spapr->nvram = (struct sPAPRNVRAM *)dev; 1386 } 1387 1388 static void spapr_rtc_create(sPAPRMachineState *spapr) 1389 { 1390 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1391 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1392 &error_fatal); 1393 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1394 &error_fatal); 1395 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1396 "date", &error_fatal); 1397 } 1398 1399 /* Returns whether we want to use VGA or not */ 1400 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1401 { 1402 switch (vga_interface_type) { 1403 case VGA_NONE: 1404 return false; 1405 case VGA_DEVICE: 1406 return true; 1407 case VGA_STD: 1408 case VGA_VIRTIO: 1409 return pci_vga_init(pci_bus) != NULL; 1410 default: 1411 error_setg(errp, 1412 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1413 return false; 1414 } 1415 } 1416 1417 static int spapr_post_load(void *opaque, int version_id) 1418 { 1419 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1420 int err = 0; 1421 1422 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1423 CPUState *cs; 1424 CPU_FOREACH(cs) { 1425 PowerPCCPU *cpu = POWERPC_CPU(cs); 1426 icp_resend(ICP(cpu->intc)); 1427 } 1428 } 1429 1430 /* In earlier versions, there was no separate qdev for the PAPR 1431 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1432 * So when migrating from those versions, poke the incoming offset 1433 * value into the RTC device */ 1434 if (version_id < 3) { 1435 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1436 } 1437 1438 return err; 1439 } 1440 1441 static bool version_before_3(void *opaque, int version_id) 1442 { 1443 return version_id < 3; 1444 } 1445 1446 static bool spapr_ov5_cas_needed(void *opaque) 1447 { 1448 sPAPRMachineState *spapr = opaque; 1449 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1450 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1451 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1452 bool cas_needed; 1453 1454 /* Prior to the introduction of sPAPROptionVector, we had two option 1455 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1456 * Both of these options encode machine topology into the device-tree 1457 * in such a way that the now-booted OS should still be able to interact 1458 * appropriately with QEMU regardless of what options were actually 1459 * negotiatied on the source side. 1460 * 1461 * As such, we can avoid migrating the CAS-negotiated options if these 1462 * are the only options available on the current machine/platform. 1463 * Since these are the only options available for pseries-2.7 and 1464 * earlier, this allows us to maintain old->new/new->old migration 1465 * compatibility. 1466 * 1467 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1468 * via default pseries-2.8 machines and explicit command-line parameters. 1469 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1470 * of the actual CAS-negotiated values to continue working properly. For 1471 * example, availability of memory unplug depends on knowing whether 1472 * OV5_HP_EVT was negotiated via CAS. 1473 * 1474 * Thus, for any cases where the set of available CAS-negotiatable 1475 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1476 * include the CAS-negotiated options in the migration stream. 1477 */ 1478 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1479 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1480 1481 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1482 * the mask itself since in the future it's possible "legacy" bits may be 1483 * removed via machine options, which could generate a false positive 1484 * that breaks migration. 1485 */ 1486 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1487 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1488 1489 spapr_ovec_cleanup(ov5_mask); 1490 spapr_ovec_cleanup(ov5_legacy); 1491 spapr_ovec_cleanup(ov5_removed); 1492 1493 return cas_needed; 1494 } 1495 1496 static const VMStateDescription vmstate_spapr_ov5_cas = { 1497 .name = "spapr_option_vector_ov5_cas", 1498 .version_id = 1, 1499 .minimum_version_id = 1, 1500 .needed = spapr_ov5_cas_needed, 1501 .fields = (VMStateField[]) { 1502 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1503 vmstate_spapr_ovec, sPAPROptionVector), 1504 VMSTATE_END_OF_LIST() 1505 }, 1506 }; 1507 1508 static bool spapr_patb_entry_needed(void *opaque) 1509 { 1510 sPAPRMachineState *spapr = opaque; 1511 1512 return !!spapr->patb_entry; 1513 } 1514 1515 static const VMStateDescription vmstate_spapr_patb_entry = { 1516 .name = "spapr_patb_entry", 1517 .version_id = 1, 1518 .minimum_version_id = 1, 1519 .needed = spapr_patb_entry_needed, 1520 .fields = (VMStateField[]) { 1521 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1522 VMSTATE_END_OF_LIST() 1523 }, 1524 }; 1525 1526 static const VMStateDescription vmstate_spapr = { 1527 .name = "spapr", 1528 .version_id = 3, 1529 .minimum_version_id = 1, 1530 .post_load = spapr_post_load, 1531 .fields = (VMStateField[]) { 1532 /* used to be @next_irq */ 1533 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1534 1535 /* RTC offset */ 1536 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1537 1538 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1539 VMSTATE_END_OF_LIST() 1540 }, 1541 .subsections = (const VMStateDescription*[]) { 1542 &vmstate_spapr_ov5_cas, 1543 &vmstate_spapr_patb_entry, 1544 NULL 1545 } 1546 }; 1547 1548 static int htab_save_setup(QEMUFile *f, void *opaque) 1549 { 1550 sPAPRMachineState *spapr = opaque; 1551 1552 /* "Iteration" header */ 1553 qemu_put_be32(f, spapr->htab_shift); 1554 1555 if (spapr->htab) { 1556 spapr->htab_save_index = 0; 1557 spapr->htab_first_pass = true; 1558 } else { 1559 assert(kvm_enabled()); 1560 } 1561 1562 1563 return 0; 1564 } 1565 1566 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1567 int64_t max_ns) 1568 { 1569 bool has_timeout = max_ns != -1; 1570 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1571 int index = spapr->htab_save_index; 1572 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1573 1574 assert(spapr->htab_first_pass); 1575 1576 do { 1577 int chunkstart; 1578 1579 /* Consume invalid HPTEs */ 1580 while ((index < htabslots) 1581 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1582 CLEAN_HPTE(HPTE(spapr->htab, index)); 1583 index++; 1584 } 1585 1586 /* Consume valid HPTEs */ 1587 chunkstart = index; 1588 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1589 && HPTE_VALID(HPTE(spapr->htab, index))) { 1590 CLEAN_HPTE(HPTE(spapr->htab, index)); 1591 index++; 1592 } 1593 1594 if (index > chunkstart) { 1595 int n_valid = index - chunkstart; 1596 1597 qemu_put_be32(f, chunkstart); 1598 qemu_put_be16(f, n_valid); 1599 qemu_put_be16(f, 0); 1600 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1601 HASH_PTE_SIZE_64 * n_valid); 1602 1603 if (has_timeout && 1604 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1605 break; 1606 } 1607 } 1608 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1609 1610 if (index >= htabslots) { 1611 assert(index == htabslots); 1612 index = 0; 1613 spapr->htab_first_pass = false; 1614 } 1615 spapr->htab_save_index = index; 1616 } 1617 1618 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1619 int64_t max_ns) 1620 { 1621 bool final = max_ns < 0; 1622 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1623 int examined = 0, sent = 0; 1624 int index = spapr->htab_save_index; 1625 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1626 1627 assert(!spapr->htab_first_pass); 1628 1629 do { 1630 int chunkstart, invalidstart; 1631 1632 /* Consume non-dirty HPTEs */ 1633 while ((index < htabslots) 1634 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1635 index++; 1636 examined++; 1637 } 1638 1639 chunkstart = index; 1640 /* Consume valid dirty HPTEs */ 1641 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1642 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1643 && HPTE_VALID(HPTE(spapr->htab, index))) { 1644 CLEAN_HPTE(HPTE(spapr->htab, index)); 1645 index++; 1646 examined++; 1647 } 1648 1649 invalidstart = index; 1650 /* Consume invalid dirty HPTEs */ 1651 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1652 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1653 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1654 CLEAN_HPTE(HPTE(spapr->htab, index)); 1655 index++; 1656 examined++; 1657 } 1658 1659 if (index > chunkstart) { 1660 int n_valid = invalidstart - chunkstart; 1661 int n_invalid = index - invalidstart; 1662 1663 qemu_put_be32(f, chunkstart); 1664 qemu_put_be16(f, n_valid); 1665 qemu_put_be16(f, n_invalid); 1666 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1667 HASH_PTE_SIZE_64 * n_valid); 1668 sent += index - chunkstart; 1669 1670 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1671 break; 1672 } 1673 } 1674 1675 if (examined >= htabslots) { 1676 break; 1677 } 1678 1679 if (index >= htabslots) { 1680 assert(index == htabslots); 1681 index = 0; 1682 } 1683 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1684 1685 if (index >= htabslots) { 1686 assert(index == htabslots); 1687 index = 0; 1688 } 1689 1690 spapr->htab_save_index = index; 1691 1692 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1693 } 1694 1695 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1696 #define MAX_KVM_BUF_SIZE 2048 1697 1698 static int htab_save_iterate(QEMUFile *f, void *opaque) 1699 { 1700 sPAPRMachineState *spapr = opaque; 1701 int fd; 1702 int rc = 0; 1703 1704 /* Iteration header */ 1705 qemu_put_be32(f, 0); 1706 1707 if (!spapr->htab) { 1708 assert(kvm_enabled()); 1709 1710 fd = get_htab_fd(spapr); 1711 if (fd < 0) { 1712 return fd; 1713 } 1714 1715 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1716 if (rc < 0) { 1717 return rc; 1718 } 1719 } else if (spapr->htab_first_pass) { 1720 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1721 } else { 1722 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1723 } 1724 1725 /* End marker */ 1726 qemu_put_be32(f, 0); 1727 qemu_put_be16(f, 0); 1728 qemu_put_be16(f, 0); 1729 1730 return rc; 1731 } 1732 1733 static int htab_save_complete(QEMUFile *f, void *opaque) 1734 { 1735 sPAPRMachineState *spapr = opaque; 1736 int fd; 1737 1738 /* Iteration header */ 1739 qemu_put_be32(f, 0); 1740 1741 if (!spapr->htab) { 1742 int rc; 1743 1744 assert(kvm_enabled()); 1745 1746 fd = get_htab_fd(spapr); 1747 if (fd < 0) { 1748 return fd; 1749 } 1750 1751 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1752 if (rc < 0) { 1753 return rc; 1754 } 1755 } else { 1756 if (spapr->htab_first_pass) { 1757 htab_save_first_pass(f, spapr, -1); 1758 } 1759 htab_save_later_pass(f, spapr, -1); 1760 } 1761 1762 /* End marker */ 1763 qemu_put_be32(f, 0); 1764 qemu_put_be16(f, 0); 1765 qemu_put_be16(f, 0); 1766 1767 return 0; 1768 } 1769 1770 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1771 { 1772 sPAPRMachineState *spapr = opaque; 1773 uint32_t section_hdr; 1774 int fd = -1; 1775 1776 if (version_id < 1 || version_id > 1) { 1777 error_report("htab_load() bad version"); 1778 return -EINVAL; 1779 } 1780 1781 section_hdr = qemu_get_be32(f); 1782 1783 if (section_hdr) { 1784 Error *local_err = NULL; 1785 1786 /* First section gives the htab size */ 1787 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1788 if (local_err) { 1789 error_report_err(local_err); 1790 return -EINVAL; 1791 } 1792 return 0; 1793 } 1794 1795 if (!spapr->htab) { 1796 assert(kvm_enabled()); 1797 1798 fd = kvmppc_get_htab_fd(true); 1799 if (fd < 0) { 1800 error_report("Unable to open fd to restore KVM hash table: %s", 1801 strerror(errno)); 1802 } 1803 } 1804 1805 while (true) { 1806 uint32_t index; 1807 uint16_t n_valid, n_invalid; 1808 1809 index = qemu_get_be32(f); 1810 n_valid = qemu_get_be16(f); 1811 n_invalid = qemu_get_be16(f); 1812 1813 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1814 /* End of Stream */ 1815 break; 1816 } 1817 1818 if ((index + n_valid + n_invalid) > 1819 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1820 /* Bad index in stream */ 1821 error_report( 1822 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1823 index, n_valid, n_invalid, spapr->htab_shift); 1824 return -EINVAL; 1825 } 1826 1827 if (spapr->htab) { 1828 if (n_valid) { 1829 qemu_get_buffer(f, HPTE(spapr->htab, index), 1830 HASH_PTE_SIZE_64 * n_valid); 1831 } 1832 if (n_invalid) { 1833 memset(HPTE(spapr->htab, index + n_valid), 0, 1834 HASH_PTE_SIZE_64 * n_invalid); 1835 } 1836 } else { 1837 int rc; 1838 1839 assert(fd >= 0); 1840 1841 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1842 if (rc < 0) { 1843 return rc; 1844 } 1845 } 1846 } 1847 1848 if (!spapr->htab) { 1849 assert(fd >= 0); 1850 close(fd); 1851 } 1852 1853 return 0; 1854 } 1855 1856 static void htab_cleanup(void *opaque) 1857 { 1858 sPAPRMachineState *spapr = opaque; 1859 1860 close_htab_fd(spapr); 1861 } 1862 1863 static SaveVMHandlers savevm_htab_handlers = { 1864 .save_live_setup = htab_save_setup, 1865 .save_live_iterate = htab_save_iterate, 1866 .save_live_complete_precopy = htab_save_complete, 1867 .cleanup = htab_cleanup, 1868 .load_state = htab_load, 1869 }; 1870 1871 static void spapr_boot_set(void *opaque, const char *boot_device, 1872 Error **errp) 1873 { 1874 MachineState *machine = MACHINE(qdev_get_machine()); 1875 machine->boot_order = g_strdup(boot_device); 1876 } 1877 1878 /* 1879 * Reset routine for LMB DR devices. 1880 * 1881 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1882 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1883 * when it walks all its children devices. LMB devices reset occurs 1884 * as part of spapr_ppc_reset(). 1885 */ 1886 static void spapr_drc_reset(void *opaque) 1887 { 1888 sPAPRDRConnector *drc = opaque; 1889 DeviceState *d = DEVICE(drc); 1890 1891 if (d) { 1892 device_reset(d); 1893 } 1894 } 1895 1896 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1897 { 1898 MachineState *machine = MACHINE(spapr); 1899 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1900 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1901 int i; 1902 1903 for (i = 0; i < nr_lmbs; i++) { 1904 sPAPRDRConnector *drc; 1905 uint64_t addr; 1906 1907 addr = i * lmb_size + spapr->hotplug_memory.base; 1908 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, 1909 addr/lmb_size); 1910 qemu_register_reset(spapr_drc_reset, drc); 1911 } 1912 } 1913 1914 /* 1915 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1916 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1917 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1918 */ 1919 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 1920 { 1921 int i; 1922 1923 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1924 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 1925 " is not aligned to %llu MiB", 1926 machine->ram_size, 1927 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1928 return; 1929 } 1930 1931 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1932 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 1933 " is not aligned to %llu MiB", 1934 machine->ram_size, 1935 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1936 return; 1937 } 1938 1939 for (i = 0; i < nb_numa_nodes; i++) { 1940 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 1941 error_setg(errp, 1942 "Node %d memory size 0x%" PRIx64 1943 " is not aligned to %llu MiB", 1944 i, numa_info[i].node_mem, 1945 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1946 return; 1947 } 1948 } 1949 } 1950 1951 /* find cpu slot in machine->possible_cpus by core_id */ 1952 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 1953 { 1954 int index = id / smp_threads; 1955 1956 if (index >= ms->possible_cpus->len) { 1957 return NULL; 1958 } 1959 if (idx) { 1960 *idx = index; 1961 } 1962 return &ms->possible_cpus->cpus[index]; 1963 } 1964 1965 static void spapr_init_cpus(sPAPRMachineState *spapr) 1966 { 1967 MachineState *machine = MACHINE(spapr); 1968 MachineClass *mc = MACHINE_GET_CLASS(machine); 1969 char *type = spapr_get_cpu_core_type(machine->cpu_model); 1970 int smt = kvmppc_smt_threads(); 1971 const CPUArchIdList *possible_cpus; 1972 int boot_cores_nr = smp_cpus / smp_threads; 1973 int i; 1974 1975 if (!type) { 1976 error_report("Unable to find sPAPR CPU Core definition"); 1977 exit(1); 1978 } 1979 1980 possible_cpus = mc->possible_cpu_arch_ids(machine); 1981 if (mc->has_hotpluggable_cpus) { 1982 if (smp_cpus % smp_threads) { 1983 error_report("smp_cpus (%u) must be multiple of threads (%u)", 1984 smp_cpus, smp_threads); 1985 exit(1); 1986 } 1987 if (max_cpus % smp_threads) { 1988 error_report("max_cpus (%u) must be multiple of threads (%u)", 1989 max_cpus, smp_threads); 1990 exit(1); 1991 } 1992 } else { 1993 if (max_cpus != smp_cpus) { 1994 error_report("This machine version does not support CPU hotplug"); 1995 exit(1); 1996 } 1997 boot_cores_nr = possible_cpus->len; 1998 } 1999 2000 for (i = 0; i < possible_cpus->len; i++) { 2001 int core_id = i * smp_threads; 2002 2003 if (mc->has_hotpluggable_cpus) { 2004 sPAPRDRConnector *drc = 2005 spapr_dr_connector_new(OBJECT(spapr), 2006 SPAPR_DR_CONNECTOR_TYPE_CPU, 2007 (core_id / smp_threads) * smt); 2008 2009 qemu_register_reset(spapr_drc_reset, drc); 2010 } 2011 2012 if (i < boot_cores_nr) { 2013 Object *core = object_new(type); 2014 int nr_threads = smp_threads; 2015 2016 /* Handle the partially filled core for older machine types */ 2017 if ((i + 1) * smp_threads >= smp_cpus) { 2018 nr_threads = smp_cpus - i * smp_threads; 2019 } 2020 2021 object_property_set_int(core, nr_threads, "nr-threads", 2022 &error_fatal); 2023 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2024 &error_fatal); 2025 object_property_set_bool(core, true, "realized", &error_fatal); 2026 } 2027 } 2028 g_free(type); 2029 } 2030 2031 /* pSeries LPAR / sPAPR hardware init */ 2032 static void ppc_spapr_init(MachineState *machine) 2033 { 2034 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2035 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2036 const char *kernel_filename = machine->kernel_filename; 2037 const char *initrd_filename = machine->initrd_filename; 2038 PCIHostState *phb; 2039 int i; 2040 MemoryRegion *sysmem = get_system_memory(); 2041 MemoryRegion *ram = g_new(MemoryRegion, 1); 2042 MemoryRegion *rma_region; 2043 void *rma = NULL; 2044 hwaddr rma_alloc_size; 2045 hwaddr node0_size = spapr_node0_size(); 2046 long load_limit, fw_size; 2047 char *filename; 2048 int smt = kvmppc_smt_threads(); 2049 2050 msi_nonbroken = true; 2051 2052 QLIST_INIT(&spapr->phbs); 2053 2054 /* Allocate RMA if necessary */ 2055 rma_alloc_size = kvmppc_alloc_rma(&rma); 2056 2057 if (rma_alloc_size == -1) { 2058 error_report("Unable to create RMA"); 2059 exit(1); 2060 } 2061 2062 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 2063 spapr->rma_size = rma_alloc_size; 2064 } else { 2065 spapr->rma_size = node0_size; 2066 2067 /* With KVM, we don't actually know whether KVM supports an 2068 * unbounded RMA (PR KVM) or is limited by the hash table size 2069 * (HV KVM using VRMA), so we always assume the latter 2070 * 2071 * In that case, we also limit the initial allocations for RTAS 2072 * etc... to 256M since we have no way to know what the VRMA size 2073 * is going to be as it depends on the size of the hash table 2074 * isn't determined yet. 2075 */ 2076 if (kvm_enabled()) { 2077 spapr->vrma_adjust = 1; 2078 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2079 } 2080 2081 /* Actually we don't support unbounded RMA anymore since we 2082 * added proper emulation of HV mode. The max we can get is 2083 * 16G which also happens to be what we configure for PAPR 2084 * mode so make sure we don't do anything bigger than that 2085 */ 2086 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2087 } 2088 2089 if (spapr->rma_size > node0_size) { 2090 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2091 spapr->rma_size); 2092 exit(1); 2093 } 2094 2095 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2096 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2097 2098 /* Set up Interrupt Controller before we create the VCPUs */ 2099 xics_system_init(machine, DIV_ROUND_UP(max_cpus * smt, smp_threads), 2100 XICS_IRQS_SPAPR, &error_fatal); 2101 2102 /* Set up containers for ibm,client-set-architecture negotiated options */ 2103 spapr->ov5 = spapr_ovec_new(); 2104 spapr->ov5_cas = spapr_ovec_new(); 2105 2106 if (smc->dr_lmb_enabled) { 2107 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2108 spapr_validate_node_memory(machine, &error_fatal); 2109 } 2110 2111 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2112 if (kvmppc_has_cap_mmu_radix()) { 2113 /* KVM always allows GTSE with radix... */ 2114 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2115 } 2116 /* ... but not with hash (currently). */ 2117 2118 /* advertise support for dedicated HP event source to guests */ 2119 if (spapr->use_hotplug_event_source) { 2120 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2121 } 2122 2123 /* init CPUs */ 2124 if (machine->cpu_model == NULL) { 2125 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; 2126 } 2127 2128 ppc_cpu_parse_features(machine->cpu_model); 2129 2130 spapr_init_cpus(spapr); 2131 2132 if (kvm_enabled()) { 2133 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2134 kvmppc_enable_logical_ci_hcalls(); 2135 kvmppc_enable_set_mode_hcall(); 2136 2137 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2138 kvmppc_enable_clear_ref_mod_hcalls(); 2139 } 2140 2141 /* allocate RAM */ 2142 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2143 machine->ram_size); 2144 memory_region_add_subregion(sysmem, 0, ram); 2145 2146 if (rma_alloc_size && rma) { 2147 rma_region = g_new(MemoryRegion, 1); 2148 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 2149 rma_alloc_size, rma); 2150 vmstate_register_ram_global(rma_region); 2151 memory_region_add_subregion(sysmem, 0, rma_region); 2152 } 2153 2154 /* initialize hotplug memory address space */ 2155 if (machine->ram_size < machine->maxram_size) { 2156 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2157 /* 2158 * Limit the number of hotpluggable memory slots to half the number 2159 * slots that KVM supports, leaving the other half for PCI and other 2160 * devices. However ensure that number of slots doesn't drop below 32. 2161 */ 2162 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2163 SPAPR_MAX_RAM_SLOTS; 2164 2165 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2166 max_memslots = SPAPR_MAX_RAM_SLOTS; 2167 } 2168 if (machine->ram_slots > max_memslots) { 2169 error_report("Specified number of memory slots %" 2170 PRIu64" exceeds max supported %d", 2171 machine->ram_slots, max_memslots); 2172 exit(1); 2173 } 2174 2175 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2176 SPAPR_HOTPLUG_MEM_ALIGN); 2177 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2178 "hotplug-memory", hotplug_mem_size); 2179 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2180 &spapr->hotplug_memory.mr); 2181 } 2182 2183 if (smc->dr_lmb_enabled) { 2184 spapr_create_lmb_dr_connectors(spapr); 2185 } 2186 2187 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2188 if (!filename) { 2189 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2190 exit(1); 2191 } 2192 spapr->rtas_size = get_image_size(filename); 2193 if (spapr->rtas_size < 0) { 2194 error_report("Could not get size of LPAR rtas '%s'", filename); 2195 exit(1); 2196 } 2197 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2198 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2199 error_report("Could not load LPAR rtas '%s'", filename); 2200 exit(1); 2201 } 2202 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2203 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2204 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2205 exit(1); 2206 } 2207 g_free(filename); 2208 2209 /* Set up RTAS event infrastructure */ 2210 spapr_events_init(spapr); 2211 2212 /* Set up the RTC RTAS interfaces */ 2213 spapr_rtc_create(spapr); 2214 2215 /* Set up VIO bus */ 2216 spapr->vio_bus = spapr_vio_bus_init(); 2217 2218 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 2219 if (serial_hds[i]) { 2220 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 2221 } 2222 } 2223 2224 /* We always have at least the nvram device on VIO */ 2225 spapr_create_nvram(spapr); 2226 2227 /* Set up PCI */ 2228 spapr_pci_rtas_init(); 2229 2230 phb = spapr_create_phb(spapr, 0); 2231 2232 for (i = 0; i < nb_nics; i++) { 2233 NICInfo *nd = &nd_table[i]; 2234 2235 if (!nd->model) { 2236 nd->model = g_strdup("ibmveth"); 2237 } 2238 2239 if (strcmp(nd->model, "ibmveth") == 0) { 2240 spapr_vlan_create(spapr->vio_bus, nd); 2241 } else { 2242 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2243 } 2244 } 2245 2246 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2247 spapr_vscsi_create(spapr->vio_bus); 2248 } 2249 2250 /* Graphics */ 2251 if (spapr_vga_init(phb->bus, &error_fatal)) { 2252 spapr->has_graphics = true; 2253 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2254 } 2255 2256 if (machine->usb) { 2257 if (smc->use_ohci_by_default) { 2258 pci_create_simple(phb->bus, -1, "pci-ohci"); 2259 } else { 2260 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2261 } 2262 2263 if (spapr->has_graphics) { 2264 USBBus *usb_bus = usb_bus_find(-1); 2265 2266 usb_create_simple(usb_bus, "usb-kbd"); 2267 usb_create_simple(usb_bus, "usb-mouse"); 2268 } 2269 } 2270 2271 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2272 error_report( 2273 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2274 MIN_RMA_SLOF); 2275 exit(1); 2276 } 2277 2278 if (kernel_filename) { 2279 uint64_t lowaddr = 0; 2280 2281 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2282 NULL, NULL, &lowaddr, NULL, 1, 2283 PPC_ELF_MACHINE, 0, 0); 2284 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2285 spapr->kernel_size = load_elf(kernel_filename, 2286 translate_kernel_address, NULL, NULL, 2287 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2288 0, 0); 2289 spapr->kernel_le = spapr->kernel_size > 0; 2290 } 2291 if (spapr->kernel_size < 0) { 2292 error_report("error loading %s: %s", kernel_filename, 2293 load_elf_strerror(spapr->kernel_size)); 2294 exit(1); 2295 } 2296 2297 /* load initrd */ 2298 if (initrd_filename) { 2299 /* Try to locate the initrd in the gap between the kernel 2300 * and the firmware. Add a bit of space just in case 2301 */ 2302 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2303 + 0x1ffff) & ~0xffff; 2304 spapr->initrd_size = load_image_targphys(initrd_filename, 2305 spapr->initrd_base, 2306 load_limit 2307 - spapr->initrd_base); 2308 if (spapr->initrd_size < 0) { 2309 error_report("could not load initial ram disk '%s'", 2310 initrd_filename); 2311 exit(1); 2312 } 2313 } 2314 } 2315 2316 if (bios_name == NULL) { 2317 bios_name = FW_FILE_NAME; 2318 } 2319 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2320 if (!filename) { 2321 error_report("Could not find LPAR firmware '%s'", bios_name); 2322 exit(1); 2323 } 2324 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2325 if (fw_size <= 0) { 2326 error_report("Could not load LPAR firmware '%s'", filename); 2327 exit(1); 2328 } 2329 g_free(filename); 2330 2331 /* FIXME: Should register things through the MachineState's qdev 2332 * interface, this is a legacy from the sPAPREnvironment structure 2333 * which predated MachineState but had a similar function */ 2334 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2335 register_savevm_live(NULL, "spapr/htab", -1, 1, 2336 &savevm_htab_handlers, spapr); 2337 2338 /* used by RTAS */ 2339 QTAILQ_INIT(&spapr->ccs_list); 2340 qemu_register_reset(spapr_ccs_reset_hook, spapr); 2341 2342 qemu_register_boot_set(spapr_boot_set, spapr); 2343 2344 if (kvm_enabled()) { 2345 /* to stop and start vmclock */ 2346 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2347 &spapr->tb); 2348 2349 kvmppc_spapr_enable_inkernel_multitce(); 2350 } 2351 } 2352 2353 static int spapr_kvm_type(const char *vm_type) 2354 { 2355 if (!vm_type) { 2356 return 0; 2357 } 2358 2359 if (!strcmp(vm_type, "HV")) { 2360 return 1; 2361 } 2362 2363 if (!strcmp(vm_type, "PR")) { 2364 return 2; 2365 } 2366 2367 error_report("Unknown kvm-type specified '%s'", vm_type); 2368 exit(1); 2369 } 2370 2371 /* 2372 * Implementation of an interface to adjust firmware path 2373 * for the bootindex property handling. 2374 */ 2375 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2376 DeviceState *dev) 2377 { 2378 #define CAST(type, obj, name) \ 2379 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2380 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2381 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2382 2383 if (d) { 2384 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2385 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2386 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2387 2388 if (spapr) { 2389 /* 2390 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2391 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2392 * in the top 16 bits of the 64-bit LUN 2393 */ 2394 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2395 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2396 (uint64_t)id << 48); 2397 } else if (virtio) { 2398 /* 2399 * We use SRP luns of the form 01000000 | (target << 8) | lun 2400 * in the top 32 bits of the 64-bit LUN 2401 * Note: the quote above is from SLOF and it is wrong, 2402 * the actual binding is: 2403 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2404 */ 2405 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2406 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2407 (uint64_t)id << 32); 2408 } else if (usb) { 2409 /* 2410 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2411 * in the top 32 bits of the 64-bit LUN 2412 */ 2413 unsigned usb_port = atoi(usb->port->path); 2414 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2415 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2416 (uint64_t)id << 32); 2417 } 2418 } 2419 2420 /* 2421 * SLOF probes the USB devices, and if it recognizes that the device is a 2422 * storage device, it changes its name to "storage" instead of "usb-host", 2423 * and additionally adds a child node for the SCSI LUN, so the correct 2424 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2425 */ 2426 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2427 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2428 if (usb_host_dev_is_scsi_storage(usbdev)) { 2429 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2430 } 2431 } 2432 2433 if (phb) { 2434 /* Replace "pci" with "pci@800000020000000" */ 2435 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2436 } 2437 2438 return NULL; 2439 } 2440 2441 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2442 { 2443 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2444 2445 return g_strdup(spapr->kvm_type); 2446 } 2447 2448 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2449 { 2450 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2451 2452 g_free(spapr->kvm_type); 2453 spapr->kvm_type = g_strdup(value); 2454 } 2455 2456 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2457 { 2458 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2459 2460 return spapr->use_hotplug_event_source; 2461 } 2462 2463 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2464 Error **errp) 2465 { 2466 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2467 2468 spapr->use_hotplug_event_source = value; 2469 } 2470 2471 static void spapr_machine_initfn(Object *obj) 2472 { 2473 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2474 2475 spapr->htab_fd = -1; 2476 spapr->use_hotplug_event_source = true; 2477 object_property_add_str(obj, "kvm-type", 2478 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2479 object_property_set_description(obj, "kvm-type", 2480 "Specifies the KVM virtualization mode (HV, PR)", 2481 NULL); 2482 object_property_add_bool(obj, "modern-hotplug-events", 2483 spapr_get_modern_hotplug_events, 2484 spapr_set_modern_hotplug_events, 2485 NULL); 2486 object_property_set_description(obj, "modern-hotplug-events", 2487 "Use dedicated hotplug event mechanism in" 2488 " place of standard EPOW events when possible" 2489 " (required for memory hot-unplug support)", 2490 NULL); 2491 } 2492 2493 static void spapr_machine_finalizefn(Object *obj) 2494 { 2495 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2496 2497 g_free(spapr->kvm_type); 2498 } 2499 2500 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 2501 { 2502 cpu_synchronize_state(cs); 2503 ppc_cpu_do_system_reset(cs); 2504 } 2505 2506 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2507 { 2508 CPUState *cs; 2509 2510 CPU_FOREACH(cs) { 2511 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 2512 } 2513 } 2514 2515 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2516 uint32_t node, bool dedicated_hp_event_source, 2517 Error **errp) 2518 { 2519 sPAPRDRConnector *drc; 2520 sPAPRDRConnectorClass *drck; 2521 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2522 int i, fdt_offset, fdt_size; 2523 void *fdt; 2524 uint64_t addr = addr_start; 2525 2526 for (i = 0; i < nr_lmbs; i++) { 2527 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2528 addr/SPAPR_MEMORY_BLOCK_SIZE); 2529 g_assert(drc); 2530 2531 fdt = create_device_tree(&fdt_size); 2532 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2533 SPAPR_MEMORY_BLOCK_SIZE); 2534 2535 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2536 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2537 addr += SPAPR_MEMORY_BLOCK_SIZE; 2538 if (!dev->hotplugged) { 2539 /* guests expect coldplugged LMBs to be pre-allocated */ 2540 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2541 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2542 } 2543 } 2544 /* send hotplug notification to the 2545 * guest only in case of hotplugged memory 2546 */ 2547 if (dev->hotplugged) { 2548 if (dedicated_hp_event_source) { 2549 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2550 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2551 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2552 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2553 nr_lmbs, 2554 drck->get_index(drc)); 2555 } else { 2556 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 2557 nr_lmbs); 2558 } 2559 } 2560 } 2561 2562 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2563 uint32_t node, Error **errp) 2564 { 2565 Error *local_err = NULL; 2566 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2567 PCDIMMDevice *dimm = PC_DIMM(dev); 2568 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2569 MemoryRegion *mr = ddc->get_memory_region(dimm); 2570 uint64_t align = memory_region_get_alignment(mr); 2571 uint64_t size = memory_region_size(mr); 2572 uint64_t addr; 2573 char *mem_dev; 2574 2575 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2576 error_setg(&local_err, "Hotplugged memory size must be a multiple of " 2577 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 2578 goto out; 2579 } 2580 2581 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 2582 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 2583 error_setg(&local_err, "Memory backend has bad page size. " 2584 "Use 'memory-backend-file' with correct mem-path."); 2585 goto out; 2586 } 2587 2588 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2589 if (local_err) { 2590 goto out; 2591 } 2592 2593 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2594 if (local_err) { 2595 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2596 goto out; 2597 } 2598 2599 spapr_add_lmbs(dev, addr, size, node, 2600 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 2601 &error_abort); 2602 2603 out: 2604 error_propagate(errp, local_err); 2605 } 2606 2607 typedef struct sPAPRDIMMState { 2608 uint32_t nr_lmbs; 2609 } sPAPRDIMMState; 2610 2611 static void spapr_lmb_release(DeviceState *dev, void *opaque) 2612 { 2613 sPAPRDIMMState *ds = (sPAPRDIMMState *)opaque; 2614 HotplugHandler *hotplug_ctrl; 2615 2616 if (--ds->nr_lmbs) { 2617 return; 2618 } 2619 2620 g_free(ds); 2621 2622 /* 2623 * Now that all the LMBs have been removed by the guest, call the 2624 * pc-dimm unplug handler to cleanup up the pc-dimm device. 2625 */ 2626 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2627 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2628 } 2629 2630 static void spapr_del_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2631 Error **errp) 2632 { 2633 sPAPRDRConnector *drc; 2634 sPAPRDRConnectorClass *drck; 2635 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2636 int i; 2637 sPAPRDIMMState *ds = g_malloc0(sizeof(sPAPRDIMMState)); 2638 uint64_t addr = addr_start; 2639 2640 ds->nr_lmbs = nr_lmbs; 2641 for (i = 0; i < nr_lmbs; i++) { 2642 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2643 addr / SPAPR_MEMORY_BLOCK_SIZE); 2644 g_assert(drc); 2645 2646 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2647 drck->detach(drc, dev, spapr_lmb_release, ds, errp); 2648 addr += SPAPR_MEMORY_BLOCK_SIZE; 2649 } 2650 2651 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2652 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2653 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2654 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2655 nr_lmbs, 2656 drck->get_index(drc)); 2657 } 2658 2659 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2660 Error **errp) 2661 { 2662 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2663 PCDIMMDevice *dimm = PC_DIMM(dev); 2664 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2665 MemoryRegion *mr = ddc->get_memory_region(dimm); 2666 2667 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2668 object_unparent(OBJECT(dev)); 2669 } 2670 2671 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 2672 DeviceState *dev, Error **errp) 2673 { 2674 Error *local_err = NULL; 2675 PCDIMMDevice *dimm = PC_DIMM(dev); 2676 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2677 MemoryRegion *mr = ddc->get_memory_region(dimm); 2678 uint64_t size = memory_region_size(mr); 2679 uint64_t addr; 2680 2681 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2682 if (local_err) { 2683 goto out; 2684 } 2685 2686 spapr_del_lmbs(dev, addr, size, &error_abort); 2687 out: 2688 error_propagate(errp, local_err); 2689 } 2690 2691 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 2692 sPAPRMachineState *spapr) 2693 { 2694 PowerPCCPU *cpu = POWERPC_CPU(cs); 2695 DeviceClass *dc = DEVICE_GET_CLASS(cs); 2696 int id = ppc_get_vcpu_dt_id(cpu); 2697 void *fdt; 2698 int offset, fdt_size; 2699 char *nodename; 2700 2701 fdt = create_device_tree(&fdt_size); 2702 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 2703 offset = fdt_add_subnode(fdt, 0, nodename); 2704 2705 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 2706 g_free(nodename); 2707 2708 *fdt_offset = offset; 2709 return fdt; 2710 } 2711 2712 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2713 Error **errp) 2714 { 2715 MachineState *ms = MACHINE(qdev_get_machine()); 2716 CPUCore *cc = CPU_CORE(dev); 2717 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 2718 2719 core_slot->cpu = NULL; 2720 object_unparent(OBJECT(dev)); 2721 } 2722 2723 static void spapr_core_release(DeviceState *dev, void *opaque) 2724 { 2725 HotplugHandler *hotplug_ctrl; 2726 2727 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2728 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2729 } 2730 2731 static 2732 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 2733 Error **errp) 2734 { 2735 int index; 2736 sPAPRDRConnector *drc; 2737 sPAPRDRConnectorClass *drck; 2738 Error *local_err = NULL; 2739 CPUCore *cc = CPU_CORE(dev); 2740 int smt = kvmppc_smt_threads(); 2741 2742 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 2743 error_setg(errp, "Unable to find CPU core with core-id: %d", 2744 cc->core_id); 2745 return; 2746 } 2747 if (index == 0) { 2748 error_setg(errp, "Boot CPU core may not be unplugged"); 2749 return; 2750 } 2751 2752 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2753 g_assert(drc); 2754 2755 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2756 drck->detach(drc, dev, spapr_core_release, NULL, &local_err); 2757 if (local_err) { 2758 error_propagate(errp, local_err); 2759 return; 2760 } 2761 2762 spapr_hotplug_req_remove_by_index(drc); 2763 } 2764 2765 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2766 Error **errp) 2767 { 2768 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 2769 MachineClass *mc = MACHINE_GET_CLASS(spapr); 2770 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 2771 CPUCore *cc = CPU_CORE(dev); 2772 CPUState *cs = CPU(core->threads); 2773 sPAPRDRConnector *drc; 2774 Error *local_err = NULL; 2775 void *fdt = NULL; 2776 int fdt_offset = 0; 2777 int smt = kvmppc_smt_threads(); 2778 CPUArchId *core_slot; 2779 int index; 2780 2781 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2782 if (!core_slot) { 2783 error_setg(errp, "Unable to find CPU core with core-id: %d", 2784 cc->core_id); 2785 return; 2786 } 2787 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2788 2789 g_assert(drc || !mc->has_hotpluggable_cpus); 2790 2791 /* 2792 * Setup CPU DT entries only for hotplugged CPUs. For boot time or 2793 * coldplugged CPUs DT entries are setup in spapr_build_fdt(). 2794 */ 2795 if (dev->hotplugged) { 2796 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 2797 } 2798 2799 if (drc) { 2800 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2801 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err); 2802 if (local_err) { 2803 g_free(fdt); 2804 error_propagate(errp, local_err); 2805 return; 2806 } 2807 } 2808 2809 if (dev->hotplugged) { 2810 /* 2811 * Send hotplug notification interrupt to the guest only in case 2812 * of hotplugged CPUs. 2813 */ 2814 spapr_hotplug_req_add_by_index(drc); 2815 } else { 2816 /* 2817 * Set the right DRC states for cold plugged CPU. 2818 */ 2819 if (drc) { 2820 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2821 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2822 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2823 } 2824 } 2825 core_slot->cpu = OBJECT(dev); 2826 } 2827 2828 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2829 Error **errp) 2830 { 2831 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 2832 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 2833 Error *local_err = NULL; 2834 CPUCore *cc = CPU_CORE(dev); 2835 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model); 2836 const char *type = object_get_typename(OBJECT(dev)); 2837 CPUArchId *core_slot; 2838 int index; 2839 2840 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 2841 error_setg(&local_err, "CPU hotplug not supported for this machine"); 2842 goto out; 2843 } 2844 2845 if (strcmp(base_core_type, type)) { 2846 error_setg(&local_err, "CPU core type should be %s", base_core_type); 2847 goto out; 2848 } 2849 2850 if (cc->core_id % smp_threads) { 2851 error_setg(&local_err, "invalid core id %d", cc->core_id); 2852 goto out; 2853 } 2854 2855 if (cc->nr_threads != smp_threads) { 2856 error_setg(errp, "invalid nr-threads %d, must be %d", 2857 cc->nr_threads, smp_threads); 2858 return; 2859 } 2860 2861 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2862 if (!core_slot) { 2863 error_setg(&local_err, "core id %d out of range", cc->core_id); 2864 goto out; 2865 } 2866 2867 if (core_slot->cpu) { 2868 error_setg(&local_err, "core %d already populated", cc->core_id); 2869 goto out; 2870 } 2871 2872 out: 2873 g_free(base_core_type); 2874 error_propagate(errp, local_err); 2875 } 2876 2877 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 2878 DeviceState *dev, Error **errp) 2879 { 2880 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2881 2882 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2883 int node; 2884 2885 if (!smc->dr_lmb_enabled) { 2886 error_setg(errp, "Memory hotplug not supported for this machine"); 2887 return; 2888 } 2889 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 2890 if (*errp) { 2891 return; 2892 } 2893 if (node < 0 || node >= MAX_NODES) { 2894 error_setg(errp, "Invaild node %d", node); 2895 return; 2896 } 2897 2898 /* 2899 * Currently PowerPC kernel doesn't allow hot-adding memory to 2900 * memory-less node, but instead will silently add the memory 2901 * to the first node that has some memory. This causes two 2902 * unexpected behaviours for the user. 2903 * 2904 * - Memory gets hotplugged to a different node than what the user 2905 * specified. 2906 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 2907 * to memory-less node, a reboot will set things accordingly 2908 * and the previously hotplugged memory now ends in the right node. 2909 * This appears as if some memory moved from one node to another. 2910 * 2911 * So until kernel starts supporting memory hotplug to memory-less 2912 * nodes, just prevent such attempts upfront in QEMU. 2913 */ 2914 if (nb_numa_nodes && !numa_info[node].node_mem) { 2915 error_setg(errp, "Can't hotplug memory to memory-less node %d", 2916 node); 2917 return; 2918 } 2919 2920 spapr_memory_plug(hotplug_dev, dev, node, errp); 2921 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2922 spapr_core_plug(hotplug_dev, dev, errp); 2923 } 2924 } 2925 2926 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 2927 DeviceState *dev, Error **errp) 2928 { 2929 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2930 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2931 2932 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2933 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2934 spapr_memory_unplug(hotplug_dev, dev, errp); 2935 } else { 2936 error_setg(errp, "Memory hot unplug not supported for this guest"); 2937 } 2938 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2939 if (!mc->has_hotpluggable_cpus) { 2940 error_setg(errp, "CPU hot unplug not supported on this machine"); 2941 return; 2942 } 2943 spapr_core_unplug(hotplug_dev, dev, errp); 2944 } 2945 } 2946 2947 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 2948 DeviceState *dev, Error **errp) 2949 { 2950 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2951 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2952 2953 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2954 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2955 spapr_memory_unplug_request(hotplug_dev, dev, errp); 2956 } else { 2957 /* NOTE: this means there is a window after guest reset, prior to 2958 * CAS negotiation, where unplug requests will fail due to the 2959 * capability not being detected yet. This is a bit different than 2960 * the case with PCI unplug, where the events will be queued and 2961 * eventually handled by the guest after boot 2962 */ 2963 error_setg(errp, "Memory hot unplug not supported for this guest"); 2964 } 2965 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2966 if (!mc->has_hotpluggable_cpus) { 2967 error_setg(errp, "CPU hot unplug not supported on this machine"); 2968 return; 2969 } 2970 spapr_core_unplug_request(hotplug_dev, dev, errp); 2971 } 2972 } 2973 2974 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 2975 DeviceState *dev, Error **errp) 2976 { 2977 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2978 spapr_core_pre_plug(hotplug_dev, dev, errp); 2979 } 2980 } 2981 2982 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 2983 DeviceState *dev) 2984 { 2985 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2986 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2987 return HOTPLUG_HANDLER(machine); 2988 } 2989 return NULL; 2990 } 2991 2992 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index) 2993 { 2994 /* Allocate to NUMA nodes on a "socket" basis (not that concept of 2995 * socket means much for the paravirtualized PAPR platform) */ 2996 return cpu_index / smp_threads / smp_cores; 2997 } 2998 2999 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3000 { 3001 int i; 3002 int spapr_max_cores = max_cpus / smp_threads; 3003 MachineClass *mc = MACHINE_GET_CLASS(machine); 3004 3005 if (!mc->has_hotpluggable_cpus) { 3006 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3007 } 3008 if (machine->possible_cpus) { 3009 assert(machine->possible_cpus->len == spapr_max_cores); 3010 return machine->possible_cpus; 3011 } 3012 3013 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3014 sizeof(CPUArchId) * spapr_max_cores); 3015 machine->possible_cpus->len = spapr_max_cores; 3016 for (i = 0; i < machine->possible_cpus->len; i++) { 3017 int core_id = i * smp_threads; 3018 3019 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3020 machine->possible_cpus->cpus[i].arch_id = core_id; 3021 machine->possible_cpus->cpus[i].props.has_core_id = true; 3022 machine->possible_cpus->cpus[i].props.core_id = core_id; 3023 /* TODO: add 'has_node/node' here to describe 3024 to which node core belongs */ 3025 } 3026 return machine->possible_cpus; 3027 } 3028 3029 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3030 uint64_t *buid, hwaddr *pio, 3031 hwaddr *mmio32, hwaddr *mmio64, 3032 unsigned n_dma, uint32_t *liobns, Error **errp) 3033 { 3034 /* 3035 * New-style PHB window placement. 3036 * 3037 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3038 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3039 * windows. 3040 * 3041 * Some guest kernels can't work with MMIO windows above 1<<46 3042 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3043 * 3044 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3045 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3046 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3047 * 1TiB 64-bit MMIO windows for each PHB. 3048 */ 3049 const uint64_t base_buid = 0x800000020000000ULL; 3050 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3051 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3052 int i; 3053 3054 /* Sanity check natural alignments */ 3055 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3056 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3057 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3058 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3059 /* Sanity check bounds */ 3060 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3061 SPAPR_PCI_MEM32_WIN_SIZE); 3062 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3063 SPAPR_PCI_MEM64_WIN_SIZE); 3064 3065 if (index >= SPAPR_MAX_PHBS) { 3066 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3067 SPAPR_MAX_PHBS - 1); 3068 return; 3069 } 3070 3071 *buid = base_buid + index; 3072 for (i = 0; i < n_dma; ++i) { 3073 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3074 } 3075 3076 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3077 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3078 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3079 } 3080 3081 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3082 { 3083 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3084 3085 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3086 } 3087 3088 static void spapr_ics_resend(XICSFabric *dev) 3089 { 3090 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3091 3092 ics_resend(spapr->ics); 3093 } 3094 3095 static ICPState *spapr_icp_get(XICSFabric *xi, int cpu_dt_id) 3096 { 3097 PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id); 3098 3099 return cpu ? ICP(cpu->intc) : NULL; 3100 } 3101 3102 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3103 Monitor *mon) 3104 { 3105 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3106 CPUState *cs; 3107 3108 CPU_FOREACH(cs) { 3109 PowerPCCPU *cpu = POWERPC_CPU(cs); 3110 3111 icp_pic_print_info(ICP(cpu->intc), mon); 3112 } 3113 3114 ics_pic_print_info(spapr->ics, mon); 3115 } 3116 3117 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3118 { 3119 MachineClass *mc = MACHINE_CLASS(oc); 3120 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3121 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3122 NMIClass *nc = NMI_CLASS(oc); 3123 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3124 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3125 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3126 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3127 3128 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3129 3130 /* 3131 * We set up the default / latest behaviour here. The class_init 3132 * functions for the specific versioned machine types can override 3133 * these details for backwards compatibility 3134 */ 3135 mc->init = ppc_spapr_init; 3136 mc->reset = ppc_spapr_reset; 3137 mc->block_default_type = IF_SCSI; 3138 mc->max_cpus = 1024; 3139 mc->no_parallel = 1; 3140 mc->default_boot_order = ""; 3141 mc->default_ram_size = 512 * M_BYTE; 3142 mc->kvm_type = spapr_kvm_type; 3143 mc->has_dynamic_sysbus = true; 3144 mc->pci_allow_0_address = true; 3145 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3146 hc->pre_plug = spapr_machine_device_pre_plug; 3147 hc->plug = spapr_machine_device_plug; 3148 hc->unplug = spapr_machine_device_unplug; 3149 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; 3150 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3151 hc->unplug_request = spapr_machine_device_unplug_request; 3152 3153 smc->dr_lmb_enabled = true; 3154 smc->tcg_default_cpu = "POWER8"; 3155 mc->has_hotpluggable_cpus = true; 3156 fwc->get_dev_path = spapr_get_fw_dev_path; 3157 nc->nmi_monitor_handler = spapr_nmi; 3158 smc->phb_placement = spapr_phb_placement; 3159 vhc->hypercall = emulate_spapr_hypercall; 3160 vhc->hpt_mask = spapr_hpt_mask; 3161 vhc->map_hptes = spapr_map_hptes; 3162 vhc->unmap_hptes = spapr_unmap_hptes; 3163 vhc->store_hpte = spapr_store_hpte; 3164 vhc->get_patbe = spapr_get_patbe; 3165 xic->ics_get = spapr_ics_get; 3166 xic->ics_resend = spapr_ics_resend; 3167 xic->icp_get = spapr_icp_get; 3168 ispc->print_info = spapr_pic_print_info; 3169 /* Force NUMA node memory size to be a multiple of 3170 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 3171 * in which LMBs are represented and hot-added 3172 */ 3173 mc->numa_mem_align_shift = 28; 3174 } 3175 3176 static const TypeInfo spapr_machine_info = { 3177 .name = TYPE_SPAPR_MACHINE, 3178 .parent = TYPE_MACHINE, 3179 .abstract = true, 3180 .instance_size = sizeof(sPAPRMachineState), 3181 .instance_init = spapr_machine_initfn, 3182 .instance_finalize = spapr_machine_finalizefn, 3183 .class_size = sizeof(sPAPRMachineClass), 3184 .class_init = spapr_machine_class_init, 3185 .interfaces = (InterfaceInfo[]) { 3186 { TYPE_FW_PATH_PROVIDER }, 3187 { TYPE_NMI }, 3188 { TYPE_HOTPLUG_HANDLER }, 3189 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3190 { TYPE_XICS_FABRIC }, 3191 { TYPE_INTERRUPT_STATS_PROVIDER }, 3192 { } 3193 }, 3194 }; 3195 3196 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3197 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3198 void *data) \ 3199 { \ 3200 MachineClass *mc = MACHINE_CLASS(oc); \ 3201 spapr_machine_##suffix##_class_options(mc); \ 3202 if (latest) { \ 3203 mc->alias = "pseries"; \ 3204 mc->is_default = 1; \ 3205 } \ 3206 } \ 3207 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3208 { \ 3209 MachineState *machine = MACHINE(obj); \ 3210 spapr_machine_##suffix##_instance_options(machine); \ 3211 } \ 3212 static const TypeInfo spapr_machine_##suffix##_info = { \ 3213 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3214 .parent = TYPE_SPAPR_MACHINE, \ 3215 .class_init = spapr_machine_##suffix##_class_init, \ 3216 .instance_init = spapr_machine_##suffix##_instance_init, \ 3217 }; \ 3218 static void spapr_machine_register_##suffix(void) \ 3219 { \ 3220 type_register(&spapr_machine_##suffix##_info); \ 3221 } \ 3222 type_init(spapr_machine_register_##suffix) 3223 3224 /* 3225 * pseries-2.10 3226 */ 3227 static void spapr_machine_2_10_instance_options(MachineState *machine) 3228 { 3229 } 3230 3231 static void spapr_machine_2_10_class_options(MachineClass *mc) 3232 { 3233 /* Defaults for the latest behaviour inherited from the base class */ 3234 } 3235 3236 DEFINE_SPAPR_MACHINE(2_10, "2.10", true); 3237 3238 /* 3239 * pseries-2.9 3240 */ 3241 #define SPAPR_COMPAT_2_9 \ 3242 HW_COMPAT_2_9 3243 3244 static void spapr_machine_2_9_instance_options(MachineState *machine) 3245 { 3246 spapr_machine_2_10_instance_options(machine); 3247 } 3248 3249 static void spapr_machine_2_9_class_options(MachineClass *mc) 3250 { 3251 spapr_machine_2_10_class_options(mc); 3252 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); 3253 } 3254 3255 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 3256 3257 /* 3258 * pseries-2.8 3259 */ 3260 #define SPAPR_COMPAT_2_8 \ 3261 HW_COMPAT_2_8 \ 3262 { \ 3263 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3264 .property = "pcie-extended-configuration-space", \ 3265 .value = "off", \ 3266 }, 3267 3268 static void spapr_machine_2_8_instance_options(MachineState *machine) 3269 { 3270 spapr_machine_2_9_instance_options(machine); 3271 } 3272 3273 static void spapr_machine_2_8_class_options(MachineClass *mc) 3274 { 3275 spapr_machine_2_9_class_options(mc); 3276 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 3277 mc->numa_mem_align_shift = 23; 3278 } 3279 3280 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 3281 3282 /* 3283 * pseries-2.7 3284 */ 3285 #define SPAPR_COMPAT_2_7 \ 3286 HW_COMPAT_2_7 \ 3287 { \ 3288 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3289 .property = "mem_win_size", \ 3290 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 3291 }, \ 3292 { \ 3293 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3294 .property = "mem64_win_size", \ 3295 .value = "0", \ 3296 }, \ 3297 { \ 3298 .driver = TYPE_POWERPC_CPU, \ 3299 .property = "pre-2.8-migration", \ 3300 .value = "on", \ 3301 }, \ 3302 { \ 3303 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3304 .property = "pre-2.8-migration", \ 3305 .value = "on", \ 3306 }, 3307 3308 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 3309 uint64_t *buid, hwaddr *pio, 3310 hwaddr *mmio32, hwaddr *mmio64, 3311 unsigned n_dma, uint32_t *liobns, Error **errp) 3312 { 3313 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 3314 const uint64_t base_buid = 0x800000020000000ULL; 3315 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 3316 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 3317 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 3318 const uint32_t max_index = 255; 3319 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 3320 3321 uint64_t ram_top = MACHINE(spapr)->ram_size; 3322 hwaddr phb0_base, phb_base; 3323 int i; 3324 3325 /* Do we have hotpluggable memory? */ 3326 if (MACHINE(spapr)->maxram_size > ram_top) { 3327 /* Can't just use maxram_size, because there may be an 3328 * alignment gap between normal and hotpluggable memory 3329 * regions */ 3330 ram_top = spapr->hotplug_memory.base + 3331 memory_region_size(&spapr->hotplug_memory.mr); 3332 } 3333 3334 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 3335 3336 if (index > max_index) { 3337 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 3338 max_index); 3339 return; 3340 } 3341 3342 *buid = base_buid + index; 3343 for (i = 0; i < n_dma; ++i) { 3344 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3345 } 3346 3347 phb_base = phb0_base + index * phb_spacing; 3348 *pio = phb_base + pio_offset; 3349 *mmio32 = phb_base + mmio_offset; 3350 /* 3351 * We don't set the 64-bit MMIO window, relying on the PHB's 3352 * fallback behaviour of automatically splitting a large "32-bit" 3353 * window into contiguous 32-bit and 64-bit windows 3354 */ 3355 } 3356 3357 static void spapr_machine_2_7_instance_options(MachineState *machine) 3358 { 3359 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 3360 3361 spapr_machine_2_8_instance_options(machine); 3362 spapr->use_hotplug_event_source = false; 3363 } 3364 3365 static void spapr_machine_2_7_class_options(MachineClass *mc) 3366 { 3367 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3368 3369 spapr_machine_2_8_class_options(mc); 3370 smc->tcg_default_cpu = "POWER7"; 3371 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 3372 smc->phb_placement = phb_placement_2_7; 3373 } 3374 3375 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 3376 3377 /* 3378 * pseries-2.6 3379 */ 3380 #define SPAPR_COMPAT_2_6 \ 3381 HW_COMPAT_2_6 \ 3382 { \ 3383 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3384 .property = "ddw",\ 3385 .value = stringify(off),\ 3386 }, 3387 3388 static void spapr_machine_2_6_instance_options(MachineState *machine) 3389 { 3390 spapr_machine_2_7_instance_options(machine); 3391 } 3392 3393 static void spapr_machine_2_6_class_options(MachineClass *mc) 3394 { 3395 spapr_machine_2_7_class_options(mc); 3396 mc->has_hotpluggable_cpus = false; 3397 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 3398 } 3399 3400 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 3401 3402 /* 3403 * pseries-2.5 3404 */ 3405 #define SPAPR_COMPAT_2_5 \ 3406 HW_COMPAT_2_5 \ 3407 { \ 3408 .driver = "spapr-vlan", \ 3409 .property = "use-rx-buffer-pools", \ 3410 .value = "off", \ 3411 }, 3412 3413 static void spapr_machine_2_5_instance_options(MachineState *machine) 3414 { 3415 spapr_machine_2_6_instance_options(machine); 3416 } 3417 3418 static void spapr_machine_2_5_class_options(MachineClass *mc) 3419 { 3420 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3421 3422 spapr_machine_2_6_class_options(mc); 3423 smc->use_ohci_by_default = true; 3424 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 3425 } 3426 3427 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 3428 3429 /* 3430 * pseries-2.4 3431 */ 3432 #define SPAPR_COMPAT_2_4 \ 3433 HW_COMPAT_2_4 3434 3435 static void spapr_machine_2_4_instance_options(MachineState *machine) 3436 { 3437 spapr_machine_2_5_instance_options(machine); 3438 } 3439 3440 static void spapr_machine_2_4_class_options(MachineClass *mc) 3441 { 3442 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3443 3444 spapr_machine_2_5_class_options(mc); 3445 smc->dr_lmb_enabled = false; 3446 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 3447 } 3448 3449 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 3450 3451 /* 3452 * pseries-2.3 3453 */ 3454 #define SPAPR_COMPAT_2_3 \ 3455 HW_COMPAT_2_3 \ 3456 {\ 3457 .driver = "spapr-pci-host-bridge",\ 3458 .property = "dynamic-reconfiguration",\ 3459 .value = "off",\ 3460 }, 3461 3462 static void spapr_machine_2_3_instance_options(MachineState *machine) 3463 { 3464 spapr_machine_2_4_instance_options(machine); 3465 savevm_skip_section_footers(); 3466 global_state_set_optional(); 3467 savevm_skip_configuration(); 3468 } 3469 3470 static void spapr_machine_2_3_class_options(MachineClass *mc) 3471 { 3472 spapr_machine_2_4_class_options(mc); 3473 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 3474 } 3475 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 3476 3477 /* 3478 * pseries-2.2 3479 */ 3480 3481 #define SPAPR_COMPAT_2_2 \ 3482 HW_COMPAT_2_2 \ 3483 {\ 3484 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3485 .property = "mem_win_size",\ 3486 .value = "0x20000000",\ 3487 }, 3488 3489 static void spapr_machine_2_2_instance_options(MachineState *machine) 3490 { 3491 spapr_machine_2_3_instance_options(machine); 3492 machine->suppress_vmdesc = true; 3493 } 3494 3495 static void spapr_machine_2_2_class_options(MachineClass *mc) 3496 { 3497 spapr_machine_2_3_class_options(mc); 3498 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 3499 } 3500 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 3501 3502 /* 3503 * pseries-2.1 3504 */ 3505 #define SPAPR_COMPAT_2_1 \ 3506 HW_COMPAT_2_1 3507 3508 static void spapr_machine_2_1_instance_options(MachineState *machine) 3509 { 3510 spapr_machine_2_2_instance_options(machine); 3511 } 3512 3513 static void spapr_machine_2_1_class_options(MachineClass *mc) 3514 { 3515 spapr_machine_2_2_class_options(mc); 3516 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 3517 } 3518 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 3519 3520 static void spapr_machine_register_types(void) 3521 { 3522 type_register_static(&spapr_machine_info); 3523 } 3524 3525 type_init(spapr_machine_register_types) 3526