1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "sysemu/sysemu.h" 28 #include "hw/hw.h" 29 #include "elf.h" 30 #include "net/net.h" 31 #include "sysemu/blockdev.h" 32 #include "sysemu/cpus.h" 33 #include "sysemu/kvm.h" 34 #include "kvm_ppc.h" 35 #include "mmu-hash64.h" 36 37 #include "hw/boards.h" 38 #include "hw/ppc/ppc.h" 39 #include "hw/loader.h" 40 41 #include "hw/ppc/spapr.h" 42 #include "hw/ppc/spapr_vio.h" 43 #include "hw/pci-host/spapr.h" 44 #include "hw/ppc/xics.h" 45 #include "hw/pci/msi.h" 46 47 #include "hw/pci/pci.h" 48 49 #include "exec/address-spaces.h" 50 #include "hw/usb.h" 51 #include "qemu/config-file.h" 52 53 #include <libfdt.h> 54 55 /* SLOF memory layout: 56 * 57 * SLOF raw image loaded at 0, copies its romfs right below the flat 58 * device-tree, then position SLOF itself 31M below that 59 * 60 * So we set FW_OVERHEAD to 40MB which should account for all of that 61 * and more 62 * 63 * We load our kernel at 4M, leaving space for SLOF initial image 64 */ 65 #define FDT_MAX_SIZE 0x40000 66 #define RTAS_MAX_SIZE 0x10000 67 #define FW_MAX_SIZE 0x400000 68 #define FW_FILE_NAME "slof.bin" 69 #define FW_OVERHEAD 0x2800000 70 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 71 72 #define MIN_RMA_SLOF 128UL 73 74 #define TIMEBASE_FREQ 512000000ULL 75 76 #define MAX_CPUS 256 77 #define XICS_IRQS 1024 78 79 #define PHANDLE_XICP 0x00001111 80 81 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 82 83 sPAPREnvironment *spapr; 84 85 int spapr_allocate_irq(int hint, bool lsi) 86 { 87 int irq; 88 89 if (hint) { 90 irq = hint; 91 if (hint >= spapr->next_irq) { 92 spapr->next_irq = hint + 1; 93 } 94 /* FIXME: we should probably check for collisions somehow */ 95 } else { 96 irq = spapr->next_irq++; 97 } 98 99 /* Configure irq type */ 100 if (!xics_get_qirq(spapr->icp, irq)) { 101 return 0; 102 } 103 104 xics_set_irq_type(spapr->icp, irq, lsi); 105 106 return irq; 107 } 108 109 /* 110 * Allocate block of consequtive IRQs, returns a number of the first. 111 * If msi==true, aligns the first IRQ number to num. 112 */ 113 int spapr_allocate_irq_block(int num, bool lsi, bool msi) 114 { 115 int first = -1; 116 int i, hint = 0; 117 118 /* 119 * MSIMesage::data is used for storing VIRQ so 120 * it has to be aligned to num to support multiple 121 * MSI vectors. MSI-X is not affected by this. 122 * The hint is used for the first IRQ, the rest should 123 * be allocated continuously. 124 */ 125 if (msi) { 126 assert((num == 1) || (num == 2) || (num == 4) || 127 (num == 8) || (num == 16) || (num == 32)); 128 hint = (spapr->next_irq + num - 1) & ~(num - 1); 129 } 130 131 for (i = 0; i < num; ++i) { 132 int irq; 133 134 irq = spapr_allocate_irq(hint, lsi); 135 if (!irq) { 136 return -1; 137 } 138 139 if (0 == i) { 140 first = irq; 141 hint = 0; 142 } 143 144 /* If the above doesn't create a consecutive block then that's 145 * an internal bug */ 146 assert(irq == (first + i)); 147 } 148 149 return first; 150 } 151 152 static XICSState *try_create_xics(const char *type, int nr_servers, 153 int nr_irqs) 154 { 155 DeviceState *dev; 156 157 dev = qdev_create(NULL, type); 158 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 159 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 160 if (qdev_init(dev) < 0) { 161 return NULL; 162 } 163 164 return XICS_COMMON(dev); 165 } 166 167 static XICSState *xics_system_init(int nr_servers, int nr_irqs) 168 { 169 XICSState *icp = NULL; 170 171 if (kvm_enabled()) { 172 QemuOpts *machine_opts = qemu_get_machine_opts(); 173 bool irqchip_allowed = qemu_opt_get_bool(machine_opts, 174 "kernel_irqchip", true); 175 bool irqchip_required = qemu_opt_get_bool(machine_opts, 176 "kernel_irqchip", false); 177 if (irqchip_allowed) { 178 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs); 179 } 180 181 if (irqchip_required && !icp) { 182 perror("Failed to create in-kernel XICS\n"); 183 abort(); 184 } 185 } 186 187 if (!icp) { 188 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs); 189 } 190 191 if (!icp) { 192 perror("Failed to create XICS\n"); 193 abort(); 194 } 195 196 return icp; 197 } 198 199 static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) 200 { 201 int ret = 0, offset; 202 CPUState *cpu; 203 char cpu_model[32]; 204 int smt = kvmppc_smt_threads(); 205 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 206 207 CPU_FOREACH(cpu) { 208 DeviceClass *dc = DEVICE_GET_CLASS(cpu); 209 uint32_t associativity[] = {cpu_to_be32(0x5), 210 cpu_to_be32(0x0), 211 cpu_to_be32(0x0), 212 cpu_to_be32(0x0), 213 cpu_to_be32(cpu->numa_node), 214 cpu_to_be32(cpu->cpu_index)}; 215 216 if ((cpu->cpu_index % smt) != 0) { 217 continue; 218 } 219 220 snprintf(cpu_model, 32, "/cpus/%s@%x", dc->fw_name, 221 cpu->cpu_index); 222 223 offset = fdt_path_offset(fdt, cpu_model); 224 if (offset < 0) { 225 return offset; 226 } 227 228 if (nb_numa_nodes > 1) { 229 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 230 sizeof(associativity)); 231 if (ret < 0) { 232 return ret; 233 } 234 } 235 236 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 237 pft_size_prop, sizeof(pft_size_prop)); 238 if (ret < 0) { 239 return ret; 240 } 241 } 242 return ret; 243 } 244 245 246 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 247 size_t maxsize) 248 { 249 size_t maxcells = maxsize / sizeof(uint32_t); 250 int i, j, count; 251 uint32_t *p = prop; 252 253 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 254 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 255 256 if (!sps->page_shift) { 257 break; 258 } 259 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 260 if (sps->enc[count].page_shift == 0) { 261 break; 262 } 263 } 264 if ((p - prop) >= (maxcells - 3 - count * 2)) { 265 break; 266 } 267 *(p++) = cpu_to_be32(sps->page_shift); 268 *(p++) = cpu_to_be32(sps->slb_enc); 269 *(p++) = cpu_to_be32(count); 270 for (j = 0; j < count; j++) { 271 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 272 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 273 } 274 } 275 276 return (p - prop) * sizeof(uint32_t); 277 } 278 279 #define _FDT(exp) \ 280 do { \ 281 int ret = (exp); \ 282 if (ret < 0) { \ 283 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 284 #exp, fdt_strerror(ret)); \ 285 exit(1); \ 286 } \ 287 } while (0) 288 289 290 static void *spapr_create_fdt_skel(hwaddr initrd_base, 291 hwaddr initrd_size, 292 hwaddr kernel_size, 293 bool little_endian, 294 const char *boot_device, 295 const char *kernel_cmdline, 296 uint32_t epow_irq) 297 { 298 void *fdt; 299 CPUState *cs; 300 uint32_t start_prop = cpu_to_be32(initrd_base); 301 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 302 char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt" 303 "\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk\0hcall-set-mode"; 304 char qemu_hypertas_prop[] = "hcall-memop1"; 305 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 306 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; 307 int i, smt = kvmppc_smt_threads(); 308 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 309 310 fdt = g_malloc0(FDT_MAX_SIZE); 311 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 312 313 if (kernel_size) { 314 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 315 } 316 if (initrd_size) { 317 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 318 } 319 _FDT((fdt_finish_reservemap(fdt))); 320 321 /* Root node */ 322 _FDT((fdt_begin_node(fdt, ""))); 323 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 324 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 325 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 326 327 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 328 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 329 330 /* /chosen */ 331 _FDT((fdt_begin_node(fdt, "chosen"))); 332 333 /* Set Form1_affinity */ 334 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 335 336 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 337 _FDT((fdt_property(fdt, "linux,initrd-start", 338 &start_prop, sizeof(start_prop)))); 339 _FDT((fdt_property(fdt, "linux,initrd-end", 340 &end_prop, sizeof(end_prop)))); 341 if (kernel_size) { 342 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 343 cpu_to_be64(kernel_size) }; 344 345 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 346 if (little_endian) { 347 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 348 } 349 } 350 if (boot_device) { 351 _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device))); 352 } 353 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 354 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 355 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 356 357 _FDT((fdt_end_node(fdt))); 358 359 /* cpus */ 360 _FDT((fdt_begin_node(fdt, "cpus"))); 361 362 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 363 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 364 365 CPU_FOREACH(cs) { 366 PowerPCCPU *cpu = POWERPC_CPU(cs); 367 CPUPPCState *env = &cpu->env; 368 DeviceClass *dc = DEVICE_GET_CLASS(cs); 369 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 370 int index = cs->cpu_index; 371 uint32_t servers_prop[smp_threads]; 372 uint32_t gservers_prop[smp_threads * 2]; 373 char *nodename; 374 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 375 0xffffffff, 0xffffffff}; 376 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 377 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 378 uint32_t page_sizes_prop[64]; 379 size_t page_sizes_prop_size; 380 381 if ((index % smt) != 0) { 382 continue; 383 } 384 385 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 386 387 _FDT((fdt_begin_node(fdt, nodename))); 388 389 g_free(nodename); 390 391 _FDT((fdt_property_cell(fdt, "reg", index))); 392 _FDT((fdt_property_string(fdt, "device_type", "cpu"))); 393 394 _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); 395 _FDT((fdt_property_cell(fdt, "d-cache-block-size", 396 env->dcache_line_size))); 397 _FDT((fdt_property_cell(fdt, "d-cache-line-size", 398 env->dcache_line_size))); 399 _FDT((fdt_property_cell(fdt, "i-cache-block-size", 400 env->icache_line_size))); 401 _FDT((fdt_property_cell(fdt, "i-cache-line-size", 402 env->icache_line_size))); 403 404 if (pcc->l1_dcache_size) { 405 _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size))); 406 } else { 407 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 408 } 409 if (pcc->l1_icache_size) { 410 _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size))); 411 } else { 412 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 413 } 414 415 _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq))); 416 _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq))); 417 _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); 418 _FDT((fdt_property_string(fdt, "status", "okay"))); 419 _FDT((fdt_property(fdt, "64-bit", NULL, 0))); 420 421 /* Build interrupt servers and gservers properties */ 422 for (i = 0; i < smp_threads; i++) { 423 servers_prop[i] = cpu_to_be32(index + i); 424 /* Hack, direct the group queues back to cpu 0 */ 425 gservers_prop[i*2] = cpu_to_be32(index + i); 426 gservers_prop[i*2 + 1] = 0; 427 } 428 _FDT((fdt_property(fdt, "ibm,ppc-interrupt-server#s", 429 servers_prop, sizeof(servers_prop)))); 430 _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s", 431 gservers_prop, sizeof(gservers_prop)))); 432 433 if (env->spr_cb[SPR_PURR].oea_read) { 434 _FDT((fdt_property(fdt, "ibm,purr", NULL, 0))); 435 } 436 437 if (env->mmu_model & POWERPC_MMU_1TSEG) { 438 _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", 439 segs, sizeof(segs)))); 440 } 441 442 /* Advertise VMX/VSX (vector extensions) if available 443 * 0 / no property == no vector extensions 444 * 1 == VMX / Altivec available 445 * 2 == VSX available */ 446 if (env->insns_flags & PPC_ALTIVEC) { 447 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 448 449 _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx))); 450 } 451 452 /* Advertise DFP (Decimal Floating Point) if available 453 * 0 / no property == no DFP 454 * 1 == DFP available */ 455 if (env->insns_flags2 & PPC2_DFP) { 456 _FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); 457 } 458 459 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 460 sizeof(page_sizes_prop)); 461 if (page_sizes_prop_size) { 462 _FDT((fdt_property(fdt, "ibm,segment-page-sizes", 463 page_sizes_prop, page_sizes_prop_size))); 464 } 465 466 _FDT((fdt_end_node(fdt))); 467 } 468 469 _FDT((fdt_end_node(fdt))); 470 471 /* RTAS */ 472 _FDT((fdt_begin_node(fdt, "rtas"))); 473 474 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop, 475 sizeof(hypertas_prop)))); 476 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas_prop, 477 sizeof(qemu_hypertas_prop)))); 478 479 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 480 refpoints, sizeof(refpoints)))); 481 482 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 483 484 _FDT((fdt_end_node(fdt))); 485 486 /* interrupt controller */ 487 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 488 489 _FDT((fdt_property_string(fdt, "device_type", 490 "PowerPC-External-Interrupt-Presentation"))); 491 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 492 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 493 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 494 interrupt_server_ranges_prop, 495 sizeof(interrupt_server_ranges_prop)))); 496 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 497 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 498 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 499 500 _FDT((fdt_end_node(fdt))); 501 502 /* vdevice */ 503 _FDT((fdt_begin_node(fdt, "vdevice"))); 504 505 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 506 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 507 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 508 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 509 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 510 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 511 512 _FDT((fdt_end_node(fdt))); 513 514 /* event-sources */ 515 spapr_events_fdt_skel(fdt, epow_irq); 516 517 _FDT((fdt_end_node(fdt))); /* close root node */ 518 _FDT((fdt_finish(fdt))); 519 520 return fdt; 521 } 522 523 static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt) 524 { 525 uint32_t associativity[] = {cpu_to_be32(0x4), cpu_to_be32(0x0), 526 cpu_to_be32(0x0), cpu_to_be32(0x0), 527 cpu_to_be32(0x0)}; 528 char mem_name[32]; 529 hwaddr node0_size, mem_start; 530 uint64_t mem_reg_property[2]; 531 int i, off; 532 533 /* memory node(s) */ 534 node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size; 535 if (spapr->rma_size > node0_size) { 536 spapr->rma_size = node0_size; 537 } 538 539 /* RMA */ 540 mem_reg_property[0] = 0; 541 mem_reg_property[1] = cpu_to_be64(spapr->rma_size); 542 off = fdt_add_subnode(fdt, 0, "memory@0"); 543 _FDT(off); 544 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 545 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 546 sizeof(mem_reg_property)))); 547 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 548 sizeof(associativity)))); 549 550 /* RAM: Node 0 */ 551 if (node0_size > spapr->rma_size) { 552 mem_reg_property[0] = cpu_to_be64(spapr->rma_size); 553 mem_reg_property[1] = cpu_to_be64(node0_size - spapr->rma_size); 554 555 sprintf(mem_name, "memory@" TARGET_FMT_lx, spapr->rma_size); 556 off = fdt_add_subnode(fdt, 0, mem_name); 557 _FDT(off); 558 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 559 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 560 sizeof(mem_reg_property)))); 561 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 562 sizeof(associativity)))); 563 } 564 565 /* RAM: Node 1 and beyond */ 566 mem_start = node0_size; 567 for (i = 1; i < nb_numa_nodes; i++) { 568 mem_reg_property[0] = cpu_to_be64(mem_start); 569 mem_reg_property[1] = cpu_to_be64(node_mem[i]); 570 associativity[3] = associativity[4] = cpu_to_be32(i); 571 sprintf(mem_name, "memory@" TARGET_FMT_lx, mem_start); 572 off = fdt_add_subnode(fdt, 0, mem_name); 573 _FDT(off); 574 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 575 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 576 sizeof(mem_reg_property)))); 577 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 578 sizeof(associativity)))); 579 mem_start += node_mem[i]; 580 } 581 582 return 0; 583 } 584 585 static void spapr_finalize_fdt(sPAPREnvironment *spapr, 586 hwaddr fdt_addr, 587 hwaddr rtas_addr, 588 hwaddr rtas_size) 589 { 590 int ret; 591 void *fdt; 592 sPAPRPHBState *phb; 593 594 fdt = g_malloc(FDT_MAX_SIZE); 595 596 /* open out the base tree into a temp buffer for the final tweaks */ 597 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 598 599 ret = spapr_populate_memory(spapr, fdt); 600 if (ret < 0) { 601 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 602 exit(1); 603 } 604 605 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 606 if (ret < 0) { 607 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 608 exit(1); 609 } 610 611 QLIST_FOREACH(phb, &spapr->phbs, list) { 612 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 613 } 614 615 if (ret < 0) { 616 fprintf(stderr, "couldn't setup PCI devices in fdt\n"); 617 exit(1); 618 } 619 620 /* RTAS */ 621 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 622 if (ret < 0) { 623 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 624 } 625 626 /* Advertise NUMA via ibm,associativity */ 627 ret = spapr_fixup_cpu_dt(fdt, spapr); 628 if (ret < 0) { 629 fprintf(stderr, "Couldn't finalize CPU device tree properties\n"); 630 } 631 632 if (!spapr->has_graphics) { 633 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 634 } 635 636 _FDT((fdt_pack(fdt))); 637 638 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 639 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n", 640 fdt_totalsize(fdt), FDT_MAX_SIZE); 641 exit(1); 642 } 643 644 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 645 646 g_free(fdt); 647 } 648 649 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 650 { 651 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 652 } 653 654 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 655 { 656 CPUPPCState *env = &cpu->env; 657 658 if (msr_pr) { 659 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 660 env->gpr[3] = H_PRIVILEGE; 661 } else { 662 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 663 } 664 } 665 666 static void spapr_reset_htab(sPAPREnvironment *spapr) 667 { 668 long shift; 669 670 /* allocate hash page table. For now we always make this 16mb, 671 * later we should probably make it scale to the size of guest 672 * RAM */ 673 674 shift = kvmppc_reset_htab(spapr->htab_shift); 675 676 if (shift > 0) { 677 /* Kernel handles htab, we don't need to allocate one */ 678 spapr->htab_shift = shift; 679 } else { 680 if (!spapr->htab) { 681 /* Allocate an htab if we don't yet have one */ 682 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); 683 } 684 685 /* And clear it */ 686 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 687 } 688 689 /* Update the RMA size if necessary */ 690 if (spapr->vrma_adjust) { 691 spapr->rma_size = kvmppc_rma_size(ram_size, spapr->htab_shift); 692 } 693 } 694 695 static void ppc_spapr_reset(void) 696 { 697 PowerPCCPU *first_ppc_cpu; 698 699 /* Reset the hash table & recalc the RMA */ 700 spapr_reset_htab(spapr); 701 702 qemu_devices_reset(); 703 704 /* Load the fdt */ 705 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 706 spapr->rtas_size); 707 708 /* Set up the entry state */ 709 first_ppc_cpu = POWERPC_CPU(first_cpu); 710 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 711 first_ppc_cpu->env.gpr[5] = 0; 712 first_cpu->halted = 0; 713 first_ppc_cpu->env.nip = spapr->entry_point; 714 715 } 716 717 static void spapr_cpu_reset(void *opaque) 718 { 719 PowerPCCPU *cpu = opaque; 720 CPUState *cs = CPU(cpu); 721 CPUPPCState *env = &cpu->env; 722 723 cpu_reset(cs); 724 725 /* All CPUs start halted. CPU0 is unhalted from the machine level 726 * reset code and the rest are explicitly started up by the guest 727 * using an RTAS call */ 728 cs->halted = 1; 729 730 env->spr[SPR_HIOR] = 0; 731 732 env->external_htab = (uint8_t *)spapr->htab; 733 env->htab_base = -1; 734 env->htab_mask = HTAB_SIZE(spapr) - 1; 735 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | 736 (spapr->htab_shift - 18); 737 } 738 739 static void spapr_create_nvram(sPAPREnvironment *spapr) 740 { 741 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 742 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 743 744 if (dinfo) { 745 qdev_prop_set_drive_nofail(dev, "drive", dinfo->bdrv); 746 } 747 748 qdev_init_nofail(dev); 749 750 spapr->nvram = (struct sPAPRNVRAM *)dev; 751 } 752 753 /* Returns whether we want to use VGA or not */ 754 static int spapr_vga_init(PCIBus *pci_bus) 755 { 756 switch (vga_interface_type) { 757 case VGA_NONE: 758 case VGA_STD: 759 return pci_vga_init(pci_bus) != NULL; 760 default: 761 fprintf(stderr, "This vga model is not supported," 762 "currently it only supports -vga std\n"); 763 exit(0); 764 break; 765 } 766 } 767 768 static const VMStateDescription vmstate_spapr = { 769 .name = "spapr", 770 .version_id = 1, 771 .minimum_version_id = 1, 772 .minimum_version_id_old = 1, 773 .fields = (VMStateField []) { 774 VMSTATE_UINT32(next_irq, sPAPREnvironment), 775 776 /* RTC offset */ 777 VMSTATE_UINT64(rtc_offset, sPAPREnvironment), 778 779 VMSTATE_END_OF_LIST() 780 }, 781 }; 782 783 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 784 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 785 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 786 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 787 788 static int htab_save_setup(QEMUFile *f, void *opaque) 789 { 790 sPAPREnvironment *spapr = opaque; 791 792 /* "Iteration" header */ 793 qemu_put_be32(f, spapr->htab_shift); 794 795 if (spapr->htab) { 796 spapr->htab_save_index = 0; 797 spapr->htab_first_pass = true; 798 } else { 799 assert(kvm_enabled()); 800 801 spapr->htab_fd = kvmppc_get_htab_fd(false); 802 if (spapr->htab_fd < 0) { 803 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", 804 strerror(errno)); 805 return -1; 806 } 807 } 808 809 810 return 0; 811 } 812 813 static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr, 814 int64_t max_ns) 815 { 816 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 817 int index = spapr->htab_save_index; 818 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 819 820 assert(spapr->htab_first_pass); 821 822 do { 823 int chunkstart; 824 825 /* Consume invalid HPTEs */ 826 while ((index < htabslots) 827 && !HPTE_VALID(HPTE(spapr->htab, index))) { 828 index++; 829 CLEAN_HPTE(HPTE(spapr->htab, index)); 830 } 831 832 /* Consume valid HPTEs */ 833 chunkstart = index; 834 while ((index < htabslots) 835 && HPTE_VALID(HPTE(spapr->htab, index))) { 836 index++; 837 CLEAN_HPTE(HPTE(spapr->htab, index)); 838 } 839 840 if (index > chunkstart) { 841 int n_valid = index - chunkstart; 842 843 qemu_put_be32(f, chunkstart); 844 qemu_put_be16(f, n_valid); 845 qemu_put_be16(f, 0); 846 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 847 HASH_PTE_SIZE_64 * n_valid); 848 849 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 850 break; 851 } 852 } 853 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 854 855 if (index >= htabslots) { 856 assert(index == htabslots); 857 index = 0; 858 spapr->htab_first_pass = false; 859 } 860 spapr->htab_save_index = index; 861 } 862 863 static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, 864 int64_t max_ns) 865 { 866 bool final = max_ns < 0; 867 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 868 int examined = 0, sent = 0; 869 int index = spapr->htab_save_index; 870 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 871 872 assert(!spapr->htab_first_pass); 873 874 do { 875 int chunkstart, invalidstart; 876 877 /* Consume non-dirty HPTEs */ 878 while ((index < htabslots) 879 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 880 index++; 881 examined++; 882 } 883 884 chunkstart = index; 885 /* Consume valid dirty HPTEs */ 886 while ((index < htabslots) 887 && HPTE_DIRTY(HPTE(spapr->htab, index)) 888 && HPTE_VALID(HPTE(spapr->htab, index))) { 889 CLEAN_HPTE(HPTE(spapr->htab, index)); 890 index++; 891 examined++; 892 } 893 894 invalidstart = index; 895 /* Consume invalid dirty HPTEs */ 896 while ((index < htabslots) 897 && HPTE_DIRTY(HPTE(spapr->htab, index)) 898 && !HPTE_VALID(HPTE(spapr->htab, index))) { 899 CLEAN_HPTE(HPTE(spapr->htab, index)); 900 index++; 901 examined++; 902 } 903 904 if (index > chunkstart) { 905 int n_valid = invalidstart - chunkstart; 906 int n_invalid = index - invalidstart; 907 908 qemu_put_be32(f, chunkstart); 909 qemu_put_be16(f, n_valid); 910 qemu_put_be16(f, n_invalid); 911 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 912 HASH_PTE_SIZE_64 * n_valid); 913 sent += index - chunkstart; 914 915 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 916 break; 917 } 918 } 919 920 if (examined >= htabslots) { 921 break; 922 } 923 924 if (index >= htabslots) { 925 assert(index == htabslots); 926 index = 0; 927 } 928 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 929 930 if (index >= htabslots) { 931 assert(index == htabslots); 932 index = 0; 933 } 934 935 spapr->htab_save_index = index; 936 937 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 938 } 939 940 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 941 #define MAX_KVM_BUF_SIZE 2048 942 943 static int htab_save_iterate(QEMUFile *f, void *opaque) 944 { 945 sPAPREnvironment *spapr = opaque; 946 int rc = 0; 947 948 /* Iteration header */ 949 qemu_put_be32(f, 0); 950 951 if (!spapr->htab) { 952 assert(kvm_enabled()); 953 954 rc = kvmppc_save_htab(f, spapr->htab_fd, 955 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 956 if (rc < 0) { 957 return rc; 958 } 959 } else if (spapr->htab_first_pass) { 960 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 961 } else { 962 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 963 } 964 965 /* End marker */ 966 qemu_put_be32(f, 0); 967 qemu_put_be16(f, 0); 968 qemu_put_be16(f, 0); 969 970 return rc; 971 } 972 973 static int htab_save_complete(QEMUFile *f, void *opaque) 974 { 975 sPAPREnvironment *spapr = opaque; 976 977 /* Iteration header */ 978 qemu_put_be32(f, 0); 979 980 if (!spapr->htab) { 981 int rc; 982 983 assert(kvm_enabled()); 984 985 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); 986 if (rc < 0) { 987 return rc; 988 } 989 close(spapr->htab_fd); 990 spapr->htab_fd = -1; 991 } else { 992 htab_save_later_pass(f, spapr, -1); 993 } 994 995 /* End marker */ 996 qemu_put_be32(f, 0); 997 qemu_put_be16(f, 0); 998 qemu_put_be16(f, 0); 999 1000 return 0; 1001 } 1002 1003 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1004 { 1005 sPAPREnvironment *spapr = opaque; 1006 uint32_t section_hdr; 1007 int fd = -1; 1008 1009 if (version_id < 1 || version_id > 1) { 1010 fprintf(stderr, "htab_load() bad version\n"); 1011 return -EINVAL; 1012 } 1013 1014 section_hdr = qemu_get_be32(f); 1015 1016 if (section_hdr) { 1017 /* First section, just the hash shift */ 1018 if (spapr->htab_shift != section_hdr) { 1019 return -EINVAL; 1020 } 1021 return 0; 1022 } 1023 1024 if (!spapr->htab) { 1025 assert(kvm_enabled()); 1026 1027 fd = kvmppc_get_htab_fd(true); 1028 if (fd < 0) { 1029 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", 1030 strerror(errno)); 1031 } 1032 } 1033 1034 while (true) { 1035 uint32_t index; 1036 uint16_t n_valid, n_invalid; 1037 1038 index = qemu_get_be32(f); 1039 n_valid = qemu_get_be16(f); 1040 n_invalid = qemu_get_be16(f); 1041 1042 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1043 /* End of Stream */ 1044 break; 1045 } 1046 1047 if ((index + n_valid + n_invalid) > 1048 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1049 /* Bad index in stream */ 1050 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " 1051 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, 1052 spapr->htab_shift); 1053 return -EINVAL; 1054 } 1055 1056 if (spapr->htab) { 1057 if (n_valid) { 1058 qemu_get_buffer(f, HPTE(spapr->htab, index), 1059 HASH_PTE_SIZE_64 * n_valid); 1060 } 1061 if (n_invalid) { 1062 memset(HPTE(spapr->htab, index + n_valid), 0, 1063 HASH_PTE_SIZE_64 * n_invalid); 1064 } 1065 } else { 1066 int rc; 1067 1068 assert(fd >= 0); 1069 1070 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1071 if (rc < 0) { 1072 return rc; 1073 } 1074 } 1075 } 1076 1077 if (!spapr->htab) { 1078 assert(fd >= 0); 1079 close(fd); 1080 } 1081 1082 return 0; 1083 } 1084 1085 static SaveVMHandlers savevm_htab_handlers = { 1086 .save_live_setup = htab_save_setup, 1087 .save_live_iterate = htab_save_iterate, 1088 .save_live_complete = htab_save_complete, 1089 .load_state = htab_load, 1090 }; 1091 1092 /* pSeries LPAR / sPAPR hardware init */ 1093 static void ppc_spapr_init(QEMUMachineInitArgs *args) 1094 { 1095 ram_addr_t ram_size = args->ram_size; 1096 const char *cpu_model = args->cpu_model; 1097 const char *kernel_filename = args->kernel_filename; 1098 const char *kernel_cmdline = args->kernel_cmdline; 1099 const char *initrd_filename = args->initrd_filename; 1100 const char *boot_device = args->boot_order; 1101 PowerPCCPU *cpu; 1102 CPUPPCState *env; 1103 PCIHostState *phb; 1104 int i; 1105 MemoryRegion *sysmem = get_system_memory(); 1106 MemoryRegion *ram = g_new(MemoryRegion, 1); 1107 hwaddr rma_alloc_size; 1108 uint32_t initrd_base = 0; 1109 long kernel_size = 0, initrd_size = 0; 1110 long load_limit, rtas_limit, fw_size; 1111 bool kernel_le = false; 1112 char *filename; 1113 1114 msi_supported = true; 1115 1116 spapr = g_malloc0(sizeof(*spapr)); 1117 QLIST_INIT(&spapr->phbs); 1118 1119 cpu_ppc_hypercall = emulate_spapr_hypercall; 1120 1121 /* Allocate RMA if necessary */ 1122 rma_alloc_size = kvmppc_alloc_rma("ppc_spapr.rma", sysmem); 1123 1124 if (rma_alloc_size == -1) { 1125 hw_error("qemu: Unable to create RMA\n"); 1126 exit(1); 1127 } 1128 1129 if (rma_alloc_size && (rma_alloc_size < ram_size)) { 1130 spapr->rma_size = rma_alloc_size; 1131 } else { 1132 spapr->rma_size = ram_size; 1133 1134 /* With KVM, we don't actually know whether KVM supports an 1135 * unbounded RMA (PR KVM) or is limited by the hash table size 1136 * (HV KVM using VRMA), so we always assume the latter 1137 * 1138 * In that case, we also limit the initial allocations for RTAS 1139 * etc... to 256M since we have no way to know what the VRMA size 1140 * is going to be as it depends on the size of the hash table 1141 * isn't determined yet. 1142 */ 1143 if (kvm_enabled()) { 1144 spapr->vrma_adjust = 1; 1145 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1146 } 1147 } 1148 1149 /* We place the device tree and RTAS just below either the top of the RMA, 1150 * or just below 2GB, whichever is lowere, so that it can be 1151 * processed with 32-bit real mode code if necessary */ 1152 rtas_limit = MIN(spapr->rma_size, 0x80000000); 1153 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1154 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 1155 load_limit = spapr->fdt_addr - FW_OVERHEAD; 1156 1157 /* We aim for a hash table of size 1/128 the size of RAM. The 1158 * normal rule of thumb is 1/64 the size of RAM, but that's much 1159 * more than needed for the Linux guests we support. */ 1160 spapr->htab_shift = 18; /* Minimum architected size */ 1161 while (spapr->htab_shift <= 46) { 1162 if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) { 1163 break; 1164 } 1165 spapr->htab_shift++; 1166 } 1167 1168 /* Set up Interrupt Controller before we create the VCPUs */ 1169 spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads, 1170 XICS_IRQS); 1171 spapr->next_irq = XICS_IRQ_BASE; 1172 1173 /* init CPUs */ 1174 if (cpu_model == NULL) { 1175 cpu_model = kvm_enabled() ? "host" : "POWER7"; 1176 } 1177 for (i = 0; i < smp_cpus; i++) { 1178 cpu = cpu_ppc_init(cpu_model); 1179 if (cpu == NULL) { 1180 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 1181 exit(1); 1182 } 1183 env = &cpu->env; 1184 1185 /* Set time-base frequency to 512 MHz */ 1186 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 1187 1188 /* PAPR always has exception vectors in RAM not ROM. To ensure this, 1189 * MSR[IP] should never be set. 1190 */ 1191 env->msr_mask &= ~(1 << 6); 1192 1193 /* Tell KVM that we're in PAPR mode */ 1194 if (kvm_enabled()) { 1195 kvmppc_set_papr(cpu); 1196 } 1197 1198 xics_cpu_setup(spapr->icp, cpu); 1199 1200 qemu_register_reset(spapr_cpu_reset, cpu); 1201 } 1202 1203 /* allocate RAM */ 1204 spapr->ram_limit = ram_size; 1205 if (spapr->ram_limit > rma_alloc_size) { 1206 ram_addr_t nonrma_base = rma_alloc_size; 1207 ram_addr_t nonrma_size = spapr->ram_limit - rma_alloc_size; 1208 1209 memory_region_init_ram(ram, NULL, "ppc_spapr.ram", nonrma_size); 1210 vmstate_register_ram_global(ram); 1211 memory_region_add_subregion(sysmem, nonrma_base, ram); 1212 } 1213 1214 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1215 spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr, 1216 rtas_limit - spapr->rtas_addr); 1217 if (spapr->rtas_size < 0) { 1218 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1219 exit(1); 1220 } 1221 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1222 hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n", 1223 spapr->rtas_size, RTAS_MAX_SIZE); 1224 exit(1); 1225 } 1226 g_free(filename); 1227 1228 /* Set up EPOW events infrastructure */ 1229 spapr_events_init(spapr); 1230 1231 /* Set up VIO bus */ 1232 spapr->vio_bus = spapr_vio_bus_init(); 1233 1234 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1235 if (serial_hds[i]) { 1236 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1237 } 1238 } 1239 1240 /* We always have at least the nvram device on VIO */ 1241 spapr_create_nvram(spapr); 1242 1243 /* Set up PCI */ 1244 spapr_pci_msi_init(spapr, SPAPR_PCI_MSI_WINDOW); 1245 spapr_pci_rtas_init(); 1246 1247 phb = spapr_create_phb(spapr, 0); 1248 1249 for (i = 0; i < nb_nics; i++) { 1250 NICInfo *nd = &nd_table[i]; 1251 1252 if (!nd->model) { 1253 nd->model = g_strdup("ibmveth"); 1254 } 1255 1256 if (strcmp(nd->model, "ibmveth") == 0) { 1257 spapr_vlan_create(spapr->vio_bus, nd); 1258 } else { 1259 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1260 } 1261 } 1262 1263 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1264 spapr_vscsi_create(spapr->vio_bus); 1265 } 1266 1267 /* Graphics */ 1268 if (spapr_vga_init(phb->bus)) { 1269 spapr->has_graphics = true; 1270 } 1271 1272 if (usb_enabled(spapr->has_graphics)) { 1273 pci_create_simple(phb->bus, -1, "pci-ohci"); 1274 if (spapr->has_graphics) { 1275 usbdevice_create("keyboard"); 1276 usbdevice_create("mouse"); 1277 } 1278 } 1279 1280 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1281 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " 1282 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); 1283 exit(1); 1284 } 1285 1286 if (kernel_filename) { 1287 uint64_t lowaddr = 0; 1288 1289 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1290 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); 1291 if (kernel_size < 0) { 1292 kernel_size = load_elf(kernel_filename, 1293 translate_kernel_address, NULL, 1294 NULL, &lowaddr, NULL, 0, ELF_MACHINE, 0); 1295 kernel_le = kernel_size > 0; 1296 } 1297 if (kernel_size < 0) { 1298 kernel_size = load_image_targphys(kernel_filename, 1299 KERNEL_LOAD_ADDR, 1300 load_limit - KERNEL_LOAD_ADDR); 1301 } 1302 if (kernel_size < 0) { 1303 fprintf(stderr, "qemu: could not load kernel '%s'\n", 1304 kernel_filename); 1305 exit(1); 1306 } 1307 1308 /* load initrd */ 1309 if (initrd_filename) { 1310 /* Try to locate the initrd in the gap between the kernel 1311 * and the firmware. Add a bit of space just in case 1312 */ 1313 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1314 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1315 load_limit - initrd_base); 1316 if (initrd_size < 0) { 1317 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 1318 initrd_filename); 1319 exit(1); 1320 } 1321 } else { 1322 initrd_base = 0; 1323 initrd_size = 0; 1324 } 1325 } 1326 1327 if (bios_name == NULL) { 1328 bios_name = FW_FILE_NAME; 1329 } 1330 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1331 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 1332 if (fw_size < 0) { 1333 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1334 exit(1); 1335 } 1336 g_free(filename); 1337 1338 spapr->entry_point = 0x100; 1339 1340 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 1341 register_savevm_live(NULL, "spapr/htab", -1, 1, 1342 &savevm_htab_handlers, spapr); 1343 1344 /* Prepare the device tree */ 1345 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 1346 kernel_size, kernel_le, 1347 boot_device, kernel_cmdline, 1348 spapr->epow_irq); 1349 assert(spapr->fdt_skel != NULL); 1350 } 1351 1352 static QEMUMachine spapr_machine = { 1353 .name = "pseries", 1354 .desc = "pSeries Logical Partition (PAPR compliant)", 1355 .is_default = 1, 1356 .init = ppc_spapr_init, 1357 .reset = ppc_spapr_reset, 1358 .block_default_type = IF_SCSI, 1359 .max_cpus = MAX_CPUS, 1360 .no_parallel = 1, 1361 .default_boot_order = NULL, 1362 }; 1363 1364 static void spapr_machine_init(void) 1365 { 1366 qemu_register_machine(&spapr_machine); 1367 } 1368 1369 machine_init(spapr_machine_init); 1370