1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/numa.h" 32 #include "hw/hw.h" 33 #include "qemu/log.h" 34 #include "hw/fw-path-provider.h" 35 #include "elf.h" 36 #include "net/net.h" 37 #include "sysemu/device_tree.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/misc.h" 42 #include "migration/global_state.h" 43 #include "migration/register.h" 44 #include "mmu-hash64.h" 45 #include "mmu-book3s-v3.h" 46 #include "cpu-models.h" 47 #include "qom/cpu.h" 48 49 #include "hw/boards.h" 50 #include "hw/ppc/ppc.h" 51 #include "hw/loader.h" 52 53 #include "hw/ppc/fdt.h" 54 #include "hw/ppc/spapr.h" 55 #include "hw/ppc/spapr_vio.h" 56 #include "hw/pci-host/spapr.h" 57 #include "hw/pci/msi.h" 58 59 #include "hw/pci/pci.h" 60 #include "hw/scsi/scsi.h" 61 #include "hw/virtio/virtio-scsi.h" 62 #include "hw/virtio/vhost-scsi-common.h" 63 64 #include "exec/address-spaces.h" 65 #include "exec/ram_addr.h" 66 #include "hw/usb.h" 67 #include "qemu/config-file.h" 68 #include "qemu/error-report.h" 69 #include "trace.h" 70 #include "hw/nmi.h" 71 #include "hw/intc/intc.h" 72 73 #include "hw/compat.h" 74 #include "qemu/cutils.h" 75 #include "hw/ppc/spapr_cpu_core.h" 76 #include "hw/mem/memory-device.h" 77 78 #include <libfdt.h> 79 80 /* SLOF memory layout: 81 * 82 * SLOF raw image loaded at 0, copies its romfs right below the flat 83 * device-tree, then position SLOF itself 31M below that 84 * 85 * So we set FW_OVERHEAD to 40MB which should account for all of that 86 * and more 87 * 88 * We load our kernel at 4M, leaving space for SLOF initial image 89 */ 90 #define FDT_MAX_SIZE 0x100000 91 #define RTAS_MAX_SIZE 0x10000 92 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 93 #define FW_MAX_SIZE 0x400000 94 #define FW_FILE_NAME "slof.bin" 95 #define FW_OVERHEAD 0x2800000 96 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 97 98 #define MIN_RMA_SLOF 128UL 99 100 #define PHANDLE_XICP 0x00001111 101 102 /* These two functions implement the VCPU id numbering: one to compute them 103 * all and one to identify thread 0 of a VCORE. Any change to the first one 104 * is likely to have an impact on the second one, so let's keep them close. 105 */ 106 static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index) 107 { 108 assert(spapr->vsmt); 109 return 110 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 111 } 112 static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr, 113 PowerPCCPU *cpu) 114 { 115 assert(spapr->vsmt); 116 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 117 } 118 119 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 120 { 121 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 122 * and newer QEMUs don't even have them. In both cases, we don't want 123 * to send anything on the wire. 124 */ 125 return false; 126 } 127 128 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 129 .name = "icp/server", 130 .version_id = 1, 131 .minimum_version_id = 1, 132 .needed = pre_2_10_vmstate_dummy_icp_needed, 133 .fields = (VMStateField[]) { 134 VMSTATE_UNUSED(4), /* uint32_t xirr */ 135 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 136 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 137 VMSTATE_END_OF_LIST() 138 }, 139 }; 140 141 static void pre_2_10_vmstate_register_dummy_icp(int i) 142 { 143 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 144 (void *)(uintptr_t) i); 145 } 146 147 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 148 { 149 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 150 (void *)(uintptr_t) i); 151 } 152 153 static int xics_max_server_number(sPAPRMachineState *spapr) 154 { 155 assert(spapr->vsmt); 156 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads); 157 } 158 159 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 160 int smt_threads) 161 { 162 int i, ret = 0; 163 uint32_t servers_prop[smt_threads]; 164 uint32_t gservers_prop[smt_threads * 2]; 165 int index = spapr_get_vcpu_id(cpu); 166 167 if (cpu->compat_pvr) { 168 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 169 if (ret < 0) { 170 return ret; 171 } 172 } 173 174 /* Build interrupt servers and gservers properties */ 175 for (i = 0; i < smt_threads; i++) { 176 servers_prop[i] = cpu_to_be32(index + i); 177 /* Hack, direct the group queues back to cpu 0 */ 178 gservers_prop[i*2] = cpu_to_be32(index + i); 179 gservers_prop[i*2 + 1] = 0; 180 } 181 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 182 servers_prop, sizeof(servers_prop)); 183 if (ret < 0) { 184 return ret; 185 } 186 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 187 gservers_prop, sizeof(gservers_prop)); 188 189 return ret; 190 } 191 192 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 193 { 194 int index = spapr_get_vcpu_id(cpu); 195 uint32_t associativity[] = {cpu_to_be32(0x5), 196 cpu_to_be32(0x0), 197 cpu_to_be32(0x0), 198 cpu_to_be32(0x0), 199 cpu_to_be32(cpu->node_id), 200 cpu_to_be32(index)}; 201 202 /* Advertise NUMA via ibm,associativity */ 203 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 204 sizeof(associativity)); 205 } 206 207 /* Populate the "ibm,pa-features" property */ 208 static void spapr_populate_pa_features(sPAPRMachineState *spapr, 209 PowerPCCPU *cpu, 210 void *fdt, int offset, 211 bool legacy_guest) 212 { 213 uint8_t pa_features_206[] = { 6, 0, 214 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 215 uint8_t pa_features_207[] = { 24, 0, 216 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 217 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 218 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 219 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 220 uint8_t pa_features_300[] = { 66, 0, 221 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 222 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 223 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 224 /* 6: DS207 */ 225 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 226 /* 16: Vector */ 227 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 228 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 229 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 230 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 231 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 232 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 233 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 234 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 236 /* 42: PM, 44: PC RA, 46: SC vec'd */ 237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 238 /* 48: SIMD, 50: QP BFP, 52: String */ 239 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 240 /* 54: DecFP, 56: DecI, 58: SHA */ 241 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 242 /* 60: NM atomic, 62: RNG */ 243 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 244 }; 245 uint8_t *pa_features = NULL; 246 size_t pa_size; 247 248 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 249 pa_features = pa_features_206; 250 pa_size = sizeof(pa_features_206); 251 } 252 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 253 pa_features = pa_features_207; 254 pa_size = sizeof(pa_features_207); 255 } 256 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 257 pa_features = pa_features_300; 258 pa_size = sizeof(pa_features_300); 259 } 260 if (!pa_features) { 261 return; 262 } 263 264 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 265 /* 266 * Note: we keep CI large pages off by default because a 64K capable 267 * guest provisioned with large pages might otherwise try to map a qemu 268 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 269 * even if that qemu runs on a 4k host. 270 * We dd this bit back here if we are confident this is not an issue 271 */ 272 pa_features[3] |= 0x20; 273 } 274 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 275 pa_features[24] |= 0x80; /* Transactional memory support */ 276 } 277 if (legacy_guest && pa_size > 40) { 278 /* Workaround for broken kernels that attempt (guest) radix 279 * mode when they can't handle it, if they see the radix bit set 280 * in pa-features. So hide it from them. */ 281 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 282 } 283 284 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 285 } 286 287 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 288 { 289 int ret = 0, offset, cpus_offset; 290 CPUState *cs; 291 char cpu_model[32]; 292 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 293 294 CPU_FOREACH(cs) { 295 PowerPCCPU *cpu = POWERPC_CPU(cs); 296 DeviceClass *dc = DEVICE_GET_CLASS(cs); 297 int index = spapr_get_vcpu_id(cpu); 298 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 299 300 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 301 continue; 302 } 303 304 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 305 306 cpus_offset = fdt_path_offset(fdt, "/cpus"); 307 if (cpus_offset < 0) { 308 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 309 if (cpus_offset < 0) { 310 return cpus_offset; 311 } 312 } 313 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 314 if (offset < 0) { 315 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 316 if (offset < 0) { 317 return offset; 318 } 319 } 320 321 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 322 pft_size_prop, sizeof(pft_size_prop)); 323 if (ret < 0) { 324 return ret; 325 } 326 327 if (nb_numa_nodes > 1) { 328 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 329 if (ret < 0) { 330 return ret; 331 } 332 } 333 334 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 335 if (ret < 0) { 336 return ret; 337 } 338 339 spapr_populate_pa_features(spapr, cpu, fdt, offset, 340 spapr->cas_legacy_guest_workaround); 341 } 342 return ret; 343 } 344 345 static hwaddr spapr_node0_size(MachineState *machine) 346 { 347 if (nb_numa_nodes) { 348 int i; 349 for (i = 0; i < nb_numa_nodes; ++i) { 350 if (numa_info[i].node_mem) { 351 return MIN(pow2floor(numa_info[i].node_mem), 352 machine->ram_size); 353 } 354 } 355 } 356 return machine->ram_size; 357 } 358 359 static void add_str(GString *s, const gchar *s1) 360 { 361 g_string_append_len(s, s1, strlen(s1) + 1); 362 } 363 364 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 365 hwaddr size) 366 { 367 uint32_t associativity[] = { 368 cpu_to_be32(0x4), /* length */ 369 cpu_to_be32(0x0), cpu_to_be32(0x0), 370 cpu_to_be32(0x0), cpu_to_be32(nodeid) 371 }; 372 char mem_name[32]; 373 uint64_t mem_reg_property[2]; 374 int off; 375 376 mem_reg_property[0] = cpu_to_be64(start); 377 mem_reg_property[1] = cpu_to_be64(size); 378 379 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 380 off = fdt_add_subnode(fdt, 0, mem_name); 381 _FDT(off); 382 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 383 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 384 sizeof(mem_reg_property)))); 385 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 386 sizeof(associativity)))); 387 return off; 388 } 389 390 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 391 { 392 MachineState *machine = MACHINE(spapr); 393 hwaddr mem_start, node_size; 394 int i, nb_nodes = nb_numa_nodes; 395 NodeInfo *nodes = numa_info; 396 NodeInfo ramnode; 397 398 /* No NUMA nodes, assume there is just one node with whole RAM */ 399 if (!nb_numa_nodes) { 400 nb_nodes = 1; 401 ramnode.node_mem = machine->ram_size; 402 nodes = &ramnode; 403 } 404 405 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 406 if (!nodes[i].node_mem) { 407 continue; 408 } 409 if (mem_start >= machine->ram_size) { 410 node_size = 0; 411 } else { 412 node_size = nodes[i].node_mem; 413 if (node_size > machine->ram_size - mem_start) { 414 node_size = machine->ram_size - mem_start; 415 } 416 } 417 if (!mem_start) { 418 /* spapr_machine_init() checks for rma_size <= node0_size 419 * already */ 420 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 421 mem_start += spapr->rma_size; 422 node_size -= spapr->rma_size; 423 } 424 for ( ; node_size; ) { 425 hwaddr sizetmp = pow2floor(node_size); 426 427 /* mem_start != 0 here */ 428 if (ctzl(mem_start) < ctzl(sizetmp)) { 429 sizetmp = 1ULL << ctzl(mem_start); 430 } 431 432 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 433 node_size -= sizetmp; 434 mem_start += sizetmp; 435 } 436 } 437 438 return 0; 439 } 440 441 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 442 sPAPRMachineState *spapr) 443 { 444 PowerPCCPU *cpu = POWERPC_CPU(cs); 445 CPUPPCState *env = &cpu->env; 446 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 447 int index = spapr_get_vcpu_id(cpu); 448 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 449 0xffffffff, 0xffffffff}; 450 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 451 : SPAPR_TIMEBASE_FREQ; 452 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 453 uint32_t page_sizes_prop[64]; 454 size_t page_sizes_prop_size; 455 uint32_t vcpus_per_socket = smp_threads * smp_cores; 456 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 457 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 458 sPAPRDRConnector *drc; 459 int drc_index; 460 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 461 int i; 462 463 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 464 if (drc) { 465 drc_index = spapr_drc_index(drc); 466 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 467 } 468 469 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 470 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 471 472 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 473 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 474 env->dcache_line_size))); 475 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 476 env->dcache_line_size))); 477 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 478 env->icache_line_size))); 479 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 480 env->icache_line_size))); 481 482 if (pcc->l1_dcache_size) { 483 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 484 pcc->l1_dcache_size))); 485 } else { 486 warn_report("Unknown L1 dcache size for cpu"); 487 } 488 if (pcc->l1_icache_size) { 489 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 490 pcc->l1_icache_size))); 491 } else { 492 warn_report("Unknown L1 icache size for cpu"); 493 } 494 495 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 496 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 497 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 498 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 499 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 500 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 501 502 if (env->spr_cb[SPR_PURR].oea_read) { 503 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 504 } 505 506 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 507 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 508 segs, sizeof(segs)))); 509 } 510 511 /* Advertise VSX (vector extensions) if available 512 * 1 == VMX / Altivec available 513 * 2 == VSX available 514 * 515 * Only CPUs for which we create core types in spapr_cpu_core.c 516 * are possible, and all of those have VMX */ 517 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 518 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 519 } else { 520 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 521 } 522 523 /* Advertise DFP (Decimal Floating Point) if available 524 * 0 / no property == no DFP 525 * 1 == DFP available */ 526 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 527 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 528 } 529 530 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 531 sizeof(page_sizes_prop)); 532 if (page_sizes_prop_size) { 533 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 534 page_sizes_prop, page_sizes_prop_size))); 535 } 536 537 spapr_populate_pa_features(spapr, cpu, fdt, offset, false); 538 539 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 540 cs->cpu_index / vcpus_per_socket))); 541 542 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 543 pft_size_prop, sizeof(pft_size_prop)))); 544 545 if (nb_numa_nodes > 1) { 546 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 547 } 548 549 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 550 551 if (pcc->radix_page_info) { 552 for (i = 0; i < pcc->radix_page_info->count; i++) { 553 radix_AP_encodings[i] = 554 cpu_to_be32(pcc->radix_page_info->entries[i]); 555 } 556 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 557 radix_AP_encodings, 558 pcc->radix_page_info->count * 559 sizeof(radix_AP_encodings[0])))); 560 } 561 } 562 563 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 564 { 565 CPUState **rev; 566 CPUState *cs; 567 int n_cpus; 568 int cpus_offset; 569 char *nodename; 570 int i; 571 572 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 573 _FDT(cpus_offset); 574 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 575 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 576 577 /* 578 * We walk the CPUs in reverse order to ensure that CPU DT nodes 579 * created by fdt_add_subnode() end up in the right order in FDT 580 * for the guest kernel the enumerate the CPUs correctly. 581 * 582 * The CPU list cannot be traversed in reverse order, so we need 583 * to do extra work. 584 */ 585 n_cpus = 0; 586 rev = NULL; 587 CPU_FOREACH(cs) { 588 rev = g_renew(CPUState *, rev, n_cpus + 1); 589 rev[n_cpus++] = cs; 590 } 591 592 for (i = n_cpus - 1; i >= 0; i--) { 593 CPUState *cs = rev[i]; 594 PowerPCCPU *cpu = POWERPC_CPU(cs); 595 int index = spapr_get_vcpu_id(cpu); 596 DeviceClass *dc = DEVICE_GET_CLASS(cs); 597 int offset; 598 599 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 600 continue; 601 } 602 603 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 604 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 605 g_free(nodename); 606 _FDT(offset); 607 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 608 } 609 610 g_free(rev); 611 } 612 613 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 614 { 615 MemoryDeviceInfoList *info; 616 617 for (info = list; info; info = info->next) { 618 MemoryDeviceInfo *value = info->value; 619 620 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 621 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 622 623 if (addr >= pcdimm_info->addr && 624 addr < (pcdimm_info->addr + pcdimm_info->size)) { 625 return pcdimm_info->node; 626 } 627 } 628 } 629 630 return -1; 631 } 632 633 struct sPAPRDrconfCellV2 { 634 uint32_t seq_lmbs; 635 uint64_t base_addr; 636 uint32_t drc_index; 637 uint32_t aa_index; 638 uint32_t flags; 639 } QEMU_PACKED; 640 641 typedef struct DrconfCellQueue { 642 struct sPAPRDrconfCellV2 cell; 643 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 644 } DrconfCellQueue; 645 646 static DrconfCellQueue * 647 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 648 uint32_t drc_index, uint32_t aa_index, 649 uint32_t flags) 650 { 651 DrconfCellQueue *elem; 652 653 elem = g_malloc0(sizeof(*elem)); 654 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 655 elem->cell.base_addr = cpu_to_be64(base_addr); 656 elem->cell.drc_index = cpu_to_be32(drc_index); 657 elem->cell.aa_index = cpu_to_be32(aa_index); 658 elem->cell.flags = cpu_to_be32(flags); 659 660 return elem; 661 } 662 663 /* ibm,dynamic-memory-v2 */ 664 static int spapr_populate_drmem_v2(sPAPRMachineState *spapr, void *fdt, 665 int offset, MemoryDeviceInfoList *dimms) 666 { 667 MachineState *machine = MACHINE(spapr); 668 uint8_t *int_buf, *cur_index, buf_len; 669 int ret; 670 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 671 uint64_t addr, cur_addr, size; 672 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 673 uint64_t mem_end = machine->device_memory->base + 674 memory_region_size(&machine->device_memory->mr); 675 uint32_t node, nr_entries = 0; 676 sPAPRDRConnector *drc; 677 DrconfCellQueue *elem, *next; 678 MemoryDeviceInfoList *info; 679 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 680 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 681 682 /* Entry to cover RAM and the gap area */ 683 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 684 SPAPR_LMB_FLAGS_RESERVED | 685 SPAPR_LMB_FLAGS_DRC_INVALID); 686 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 687 nr_entries++; 688 689 cur_addr = machine->device_memory->base; 690 for (info = dimms; info; info = info->next) { 691 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 692 693 addr = di->addr; 694 size = di->size; 695 node = di->node; 696 697 /* Entry for hot-pluggable area */ 698 if (cur_addr < addr) { 699 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 700 g_assert(drc); 701 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 702 cur_addr, spapr_drc_index(drc), -1, 0); 703 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 704 nr_entries++; 705 } 706 707 /* Entry for DIMM */ 708 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 709 g_assert(drc); 710 elem = spapr_get_drconf_cell(size / lmb_size, addr, 711 spapr_drc_index(drc), node, 712 SPAPR_LMB_FLAGS_ASSIGNED); 713 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 714 nr_entries++; 715 cur_addr = addr + size; 716 } 717 718 /* Entry for remaining hotpluggable area */ 719 if (cur_addr < mem_end) { 720 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 721 g_assert(drc); 722 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 723 cur_addr, spapr_drc_index(drc), -1, 0); 724 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 725 nr_entries++; 726 } 727 728 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 729 int_buf = cur_index = g_malloc0(buf_len); 730 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 731 cur_index += sizeof(nr_entries); 732 733 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 734 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 735 cur_index += sizeof(elem->cell); 736 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 737 g_free(elem); 738 } 739 740 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 741 g_free(int_buf); 742 if (ret < 0) { 743 return -1; 744 } 745 return 0; 746 } 747 748 /* ibm,dynamic-memory */ 749 static int spapr_populate_drmem_v1(sPAPRMachineState *spapr, void *fdt, 750 int offset, MemoryDeviceInfoList *dimms) 751 { 752 MachineState *machine = MACHINE(spapr); 753 int i, ret; 754 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 755 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 756 uint32_t nr_lmbs = (machine->device_memory->base + 757 memory_region_size(&machine->device_memory->mr)) / 758 lmb_size; 759 uint32_t *int_buf, *cur_index, buf_len; 760 761 /* 762 * Allocate enough buffer size to fit in ibm,dynamic-memory 763 */ 764 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 765 cur_index = int_buf = g_malloc0(buf_len); 766 int_buf[0] = cpu_to_be32(nr_lmbs); 767 cur_index++; 768 for (i = 0; i < nr_lmbs; i++) { 769 uint64_t addr = i * lmb_size; 770 uint32_t *dynamic_memory = cur_index; 771 772 if (i >= device_lmb_start) { 773 sPAPRDRConnector *drc; 774 775 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 776 g_assert(drc); 777 778 dynamic_memory[0] = cpu_to_be32(addr >> 32); 779 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 780 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 781 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 782 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 783 if (memory_region_present(get_system_memory(), addr)) { 784 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 785 } else { 786 dynamic_memory[5] = cpu_to_be32(0); 787 } 788 } else { 789 /* 790 * LMB information for RMA, boot time RAM and gap b/n RAM and 791 * device memory region -- all these are marked as reserved 792 * and as having no valid DRC. 793 */ 794 dynamic_memory[0] = cpu_to_be32(addr >> 32); 795 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 796 dynamic_memory[2] = cpu_to_be32(0); 797 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 798 dynamic_memory[4] = cpu_to_be32(-1); 799 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 800 SPAPR_LMB_FLAGS_DRC_INVALID); 801 } 802 803 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 804 } 805 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 806 g_free(int_buf); 807 if (ret < 0) { 808 return -1; 809 } 810 return 0; 811 } 812 813 /* 814 * Adds ibm,dynamic-reconfiguration-memory node. 815 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 816 * of this device tree node. 817 */ 818 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 819 { 820 MachineState *machine = MACHINE(spapr); 821 int ret, i, offset; 822 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 823 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 824 uint32_t *int_buf, *cur_index, buf_len; 825 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 826 MemoryDeviceInfoList *dimms = NULL; 827 828 /* 829 * Don't create the node if there is no device memory 830 */ 831 if (machine->ram_size == machine->maxram_size) { 832 return 0; 833 } 834 835 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 836 837 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 838 sizeof(prop_lmb_size)); 839 if (ret < 0) { 840 return ret; 841 } 842 843 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 844 if (ret < 0) { 845 return ret; 846 } 847 848 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 849 if (ret < 0) { 850 return ret; 851 } 852 853 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 854 dimms = qmp_memory_device_list(); 855 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 856 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 857 } else { 858 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 859 } 860 qapi_free_MemoryDeviceInfoList(dimms); 861 862 if (ret < 0) { 863 return ret; 864 } 865 866 /* ibm,associativity-lookup-arrays */ 867 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 868 cur_index = int_buf = g_malloc0(buf_len); 869 870 cur_index = int_buf; 871 int_buf[0] = cpu_to_be32(nr_nodes); 872 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 873 cur_index += 2; 874 for (i = 0; i < nr_nodes; i++) { 875 uint32_t associativity[] = { 876 cpu_to_be32(0x0), 877 cpu_to_be32(0x0), 878 cpu_to_be32(0x0), 879 cpu_to_be32(i) 880 }; 881 memcpy(cur_index, associativity, sizeof(associativity)); 882 cur_index += 4; 883 } 884 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 885 (cur_index - int_buf) * sizeof(uint32_t)); 886 g_free(int_buf); 887 888 return ret; 889 } 890 891 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 892 sPAPROptionVector *ov5_updates) 893 { 894 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 895 int ret = 0, offset; 896 897 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 898 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 899 g_assert(smc->dr_lmb_enabled); 900 ret = spapr_populate_drconf_memory(spapr, fdt); 901 if (ret) { 902 goto out; 903 } 904 } 905 906 offset = fdt_path_offset(fdt, "/chosen"); 907 if (offset < 0) { 908 offset = fdt_add_subnode(fdt, 0, "chosen"); 909 if (offset < 0) { 910 return offset; 911 } 912 } 913 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 914 "ibm,architecture-vec-5"); 915 916 out: 917 return ret; 918 } 919 920 static bool spapr_hotplugged_dev_before_cas(void) 921 { 922 Object *drc_container, *obj; 923 ObjectProperty *prop; 924 ObjectPropertyIterator iter; 925 926 drc_container = container_get(object_get_root(), "/dr-connector"); 927 object_property_iter_init(&iter, drc_container); 928 while ((prop = object_property_iter_next(&iter))) { 929 if (!strstart(prop->type, "link<", NULL)) { 930 continue; 931 } 932 obj = object_property_get_link(drc_container, prop->name, NULL); 933 if (spapr_drc_needed(obj)) { 934 return true; 935 } 936 } 937 return false; 938 } 939 940 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 941 target_ulong addr, target_ulong size, 942 sPAPROptionVector *ov5_updates) 943 { 944 void *fdt, *fdt_skel; 945 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 946 947 if (spapr_hotplugged_dev_before_cas()) { 948 return 1; 949 } 950 951 if (size < sizeof(hdr) || size > FW_MAX_SIZE) { 952 error_report("SLOF provided an unexpected CAS buffer size " 953 TARGET_FMT_lu " (min: %zu, max: %u)", 954 size, sizeof(hdr), FW_MAX_SIZE); 955 exit(EXIT_FAILURE); 956 } 957 958 size -= sizeof(hdr); 959 960 /* Create skeleton */ 961 fdt_skel = g_malloc0(size); 962 _FDT((fdt_create(fdt_skel, size))); 963 _FDT((fdt_finish_reservemap(fdt_skel))); 964 _FDT((fdt_begin_node(fdt_skel, ""))); 965 _FDT((fdt_end_node(fdt_skel))); 966 _FDT((fdt_finish(fdt_skel))); 967 fdt = g_malloc0(size); 968 _FDT((fdt_open_into(fdt_skel, fdt, size))); 969 g_free(fdt_skel); 970 971 /* Fixup cpu nodes */ 972 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 973 974 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 975 return -1; 976 } 977 978 /* Pack resulting tree */ 979 _FDT((fdt_pack(fdt))); 980 981 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 982 trace_spapr_cas_failed(size); 983 return -1; 984 } 985 986 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 987 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 988 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 989 g_free(fdt); 990 991 return 0; 992 } 993 994 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 995 { 996 int rtas; 997 GString *hypertas = g_string_sized_new(256); 998 GString *qemu_hypertas = g_string_sized_new(256); 999 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 1000 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 1001 memory_region_size(&MACHINE(spapr)->device_memory->mr); 1002 uint32_t lrdr_capacity[] = { 1003 cpu_to_be32(max_device_addr >> 32), 1004 cpu_to_be32(max_device_addr & 0xffffffff), 1005 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 1006 cpu_to_be32(max_cpus / smp_threads), 1007 }; 1008 uint32_t maxdomains[] = { 1009 cpu_to_be32(4), 1010 cpu_to_be32(0), 1011 cpu_to_be32(0), 1012 cpu_to_be32(0), 1013 cpu_to_be32(nb_numa_nodes ? nb_numa_nodes - 1 : 0), 1014 }; 1015 1016 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 1017 1018 /* hypertas */ 1019 add_str(hypertas, "hcall-pft"); 1020 add_str(hypertas, "hcall-term"); 1021 add_str(hypertas, "hcall-dabr"); 1022 add_str(hypertas, "hcall-interrupt"); 1023 add_str(hypertas, "hcall-tce"); 1024 add_str(hypertas, "hcall-vio"); 1025 add_str(hypertas, "hcall-splpar"); 1026 add_str(hypertas, "hcall-bulk"); 1027 add_str(hypertas, "hcall-set-mode"); 1028 add_str(hypertas, "hcall-sprg0"); 1029 add_str(hypertas, "hcall-copy"); 1030 add_str(hypertas, "hcall-debug"); 1031 add_str(qemu_hypertas, "hcall-memop1"); 1032 1033 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 1034 add_str(hypertas, "hcall-multi-tce"); 1035 } 1036 1037 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 1038 add_str(hypertas, "hcall-hpt-resize"); 1039 } 1040 1041 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 1042 hypertas->str, hypertas->len)); 1043 g_string_free(hypertas, TRUE); 1044 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 1045 qemu_hypertas->str, qemu_hypertas->len)); 1046 g_string_free(qemu_hypertas, TRUE); 1047 1048 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 1049 refpoints, sizeof(refpoints))); 1050 1051 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 1052 maxdomains, sizeof(maxdomains))); 1053 1054 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 1055 RTAS_ERROR_LOG_MAX)); 1056 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 1057 RTAS_EVENT_SCAN_RATE)); 1058 1059 g_assert(msi_nonbroken); 1060 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 1061 1062 /* 1063 * According to PAPR, rtas ibm,os-term does not guarantee a return 1064 * back to the guest cpu. 1065 * 1066 * While an additional ibm,extended-os-term property indicates 1067 * that rtas call return will always occur. Set this property. 1068 */ 1069 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1070 1071 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1072 lrdr_capacity, sizeof(lrdr_capacity))); 1073 1074 spapr_dt_rtas_tokens(fdt, rtas); 1075 } 1076 1077 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features 1078 * that the guest may request and thus the valid values for bytes 24..26 of 1079 * option vector 5: */ 1080 static void spapr_dt_ov5_platform_support(void *fdt, int chosen) 1081 { 1082 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1083 1084 char val[2 * 4] = { 1085 23, 0x00, /* Xive mode, filled in below. */ 1086 24, 0x00, /* Hash/Radix, filled in below. */ 1087 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1088 26, 0x40, /* Radix options: GTSE == yes. */ 1089 }; 1090 1091 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1092 first_ppc_cpu->compat_pvr)) { 1093 /* If we're in a pre POWER9 compat mode then the guest should do hash */ 1094 val[3] = 0x00; /* Hash */ 1095 } else if (kvm_enabled()) { 1096 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1097 val[3] = 0x80; /* OV5_MMU_BOTH */ 1098 } else if (kvmppc_has_cap_mmu_radix()) { 1099 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1100 } else { 1101 val[3] = 0x00; /* Hash */ 1102 } 1103 } else { 1104 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1105 val[3] = 0xC0; 1106 } 1107 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1108 val, sizeof(val))); 1109 } 1110 1111 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 1112 { 1113 MachineState *machine = MACHINE(spapr); 1114 int chosen; 1115 const char *boot_device = machine->boot_order; 1116 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1117 size_t cb = 0; 1118 char *bootlist = get_boot_devices_list(&cb); 1119 1120 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1121 1122 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 1123 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1124 spapr->initrd_base)); 1125 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1126 spapr->initrd_base + spapr->initrd_size)); 1127 1128 if (spapr->kernel_size) { 1129 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1130 cpu_to_be64(spapr->kernel_size) }; 1131 1132 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1133 &kprop, sizeof(kprop))); 1134 if (spapr->kernel_le) { 1135 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1136 } 1137 } 1138 if (boot_menu) { 1139 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1140 } 1141 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1142 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1143 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1144 1145 if (cb && bootlist) { 1146 int i; 1147 1148 for (i = 0; i < cb; i++) { 1149 if (bootlist[i] == '\n') { 1150 bootlist[i] = ' '; 1151 } 1152 } 1153 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1154 } 1155 1156 if (boot_device && strlen(boot_device)) { 1157 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1158 } 1159 1160 if (!spapr->has_graphics && stdout_path) { 1161 /* 1162 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1163 * kernel. New platforms should only use the "stdout-path" property. Set 1164 * the new property and continue using older property to remain 1165 * compatible with the existing firmware. 1166 */ 1167 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1168 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1169 } 1170 1171 spapr_dt_ov5_platform_support(fdt, chosen); 1172 1173 g_free(stdout_path); 1174 g_free(bootlist); 1175 } 1176 1177 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 1178 { 1179 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1180 * KVM to work under pHyp with some guest co-operation */ 1181 int hypervisor; 1182 uint8_t hypercall[16]; 1183 1184 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1185 /* indicate KVM hypercall interface */ 1186 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1187 if (kvmppc_has_cap_fixup_hcalls()) { 1188 /* 1189 * Older KVM versions with older guest kernels were broken 1190 * with the magic page, don't allow the guest to map it. 1191 */ 1192 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1193 sizeof(hypercall))) { 1194 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1195 hypercall, sizeof(hypercall))); 1196 } 1197 } 1198 } 1199 1200 static void *spapr_build_fdt(sPAPRMachineState *spapr, 1201 hwaddr rtas_addr, 1202 hwaddr rtas_size) 1203 { 1204 MachineState *machine = MACHINE(spapr); 1205 MachineClass *mc = MACHINE_GET_CLASS(machine); 1206 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1207 int ret; 1208 void *fdt; 1209 sPAPRPHBState *phb; 1210 char *buf; 1211 1212 fdt = g_malloc0(FDT_MAX_SIZE); 1213 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1214 1215 /* Root node */ 1216 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1217 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1218 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1219 1220 /* 1221 * Add info to guest to indentify which host is it being run on 1222 * and what is the uuid of the guest 1223 */ 1224 if (kvmppc_get_host_model(&buf)) { 1225 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1226 g_free(buf); 1227 } 1228 if (kvmppc_get_host_serial(&buf)) { 1229 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1230 g_free(buf); 1231 } 1232 1233 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1234 1235 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1236 if (qemu_uuid_set) { 1237 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1238 } 1239 g_free(buf); 1240 1241 if (qemu_get_vm_name()) { 1242 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1243 qemu_get_vm_name())); 1244 } 1245 1246 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1247 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1248 1249 /* /interrupt controller */ 1250 spapr_dt_xics(xics_max_server_number(spapr), fdt, PHANDLE_XICP); 1251 1252 ret = spapr_populate_memory(spapr, fdt); 1253 if (ret < 0) { 1254 error_report("couldn't setup memory nodes in fdt"); 1255 exit(1); 1256 } 1257 1258 /* /vdevice */ 1259 spapr_dt_vdevice(spapr->vio_bus, fdt); 1260 1261 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1262 ret = spapr_rng_populate_dt(fdt); 1263 if (ret < 0) { 1264 error_report("could not set up rng device in the fdt"); 1265 exit(1); 1266 } 1267 } 1268 1269 QLIST_FOREACH(phb, &spapr->phbs, list) { 1270 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt, smc->irq->nr_msis); 1271 if (ret < 0) { 1272 error_report("couldn't setup PCI devices in fdt"); 1273 exit(1); 1274 } 1275 } 1276 1277 /* cpus */ 1278 spapr_populate_cpus_dt_node(fdt, spapr); 1279 1280 if (smc->dr_lmb_enabled) { 1281 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1282 } 1283 1284 if (mc->has_hotpluggable_cpus) { 1285 int offset = fdt_path_offset(fdt, "/cpus"); 1286 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1287 SPAPR_DR_CONNECTOR_TYPE_CPU); 1288 if (ret < 0) { 1289 error_report("Couldn't set up CPU DR device tree properties"); 1290 exit(1); 1291 } 1292 } 1293 1294 /* /event-sources */ 1295 spapr_dt_events(spapr, fdt); 1296 1297 /* /rtas */ 1298 spapr_dt_rtas(spapr, fdt); 1299 1300 /* /chosen */ 1301 spapr_dt_chosen(spapr, fdt); 1302 1303 /* /hypervisor */ 1304 if (kvm_enabled()) { 1305 spapr_dt_hypervisor(spapr, fdt); 1306 } 1307 1308 /* Build memory reserve map */ 1309 if (spapr->kernel_size) { 1310 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1311 } 1312 if (spapr->initrd_size) { 1313 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1314 } 1315 1316 /* ibm,client-architecture-support updates */ 1317 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1318 if (ret < 0) { 1319 error_report("couldn't setup CAS properties fdt"); 1320 exit(1); 1321 } 1322 1323 return fdt; 1324 } 1325 1326 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1327 { 1328 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1329 } 1330 1331 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1332 PowerPCCPU *cpu) 1333 { 1334 CPUPPCState *env = &cpu->env; 1335 1336 /* The TCG path should also be holding the BQL at this point */ 1337 g_assert(qemu_mutex_iothread_locked()); 1338 1339 if (msr_pr) { 1340 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1341 env->gpr[3] = H_PRIVILEGE; 1342 } else { 1343 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1344 } 1345 } 1346 1347 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1348 { 1349 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1350 1351 return spapr->patb_entry; 1352 } 1353 1354 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1355 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1356 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1357 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1358 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1359 1360 /* 1361 * Get the fd to access the kernel htab, re-opening it if necessary 1362 */ 1363 static int get_htab_fd(sPAPRMachineState *spapr) 1364 { 1365 Error *local_err = NULL; 1366 1367 if (spapr->htab_fd >= 0) { 1368 return spapr->htab_fd; 1369 } 1370 1371 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1372 if (spapr->htab_fd < 0) { 1373 error_report_err(local_err); 1374 } 1375 1376 return spapr->htab_fd; 1377 } 1378 1379 void close_htab_fd(sPAPRMachineState *spapr) 1380 { 1381 if (spapr->htab_fd >= 0) { 1382 close(spapr->htab_fd); 1383 } 1384 spapr->htab_fd = -1; 1385 } 1386 1387 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1388 { 1389 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1390 1391 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1392 } 1393 1394 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1395 { 1396 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1397 1398 assert(kvm_enabled()); 1399 1400 if (!spapr->htab) { 1401 return 0; 1402 } 1403 1404 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1405 } 1406 1407 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1408 hwaddr ptex, int n) 1409 { 1410 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1411 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1412 1413 if (!spapr->htab) { 1414 /* 1415 * HTAB is controlled by KVM. Fetch into temporary buffer 1416 */ 1417 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1418 kvmppc_read_hptes(hptes, ptex, n); 1419 return hptes; 1420 } 1421 1422 /* 1423 * HTAB is controlled by QEMU. Just point to the internally 1424 * accessible PTEG. 1425 */ 1426 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1427 } 1428 1429 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1430 const ppc_hash_pte64_t *hptes, 1431 hwaddr ptex, int n) 1432 { 1433 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1434 1435 if (!spapr->htab) { 1436 g_free((void *)hptes); 1437 } 1438 1439 /* Nothing to do for qemu managed HPT */ 1440 } 1441 1442 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1443 uint64_t pte0, uint64_t pte1) 1444 { 1445 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1446 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1447 1448 if (!spapr->htab) { 1449 kvmppc_write_hpte(ptex, pte0, pte1); 1450 } else { 1451 stq_p(spapr->htab + offset, pte0); 1452 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1453 } 1454 } 1455 1456 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1457 { 1458 int shift; 1459 1460 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1461 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1462 * that's much more than is needed for Linux guests */ 1463 shift = ctz64(pow2ceil(ramsize)) - 7; 1464 shift = MAX(shift, 18); /* Minimum architected size */ 1465 shift = MIN(shift, 46); /* Maximum architected size */ 1466 return shift; 1467 } 1468 1469 void spapr_free_hpt(sPAPRMachineState *spapr) 1470 { 1471 g_free(spapr->htab); 1472 spapr->htab = NULL; 1473 spapr->htab_shift = 0; 1474 close_htab_fd(spapr); 1475 } 1476 1477 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1478 Error **errp) 1479 { 1480 long rc; 1481 1482 /* Clean up any HPT info from a previous boot */ 1483 spapr_free_hpt(spapr); 1484 1485 rc = kvmppc_reset_htab(shift); 1486 if (rc < 0) { 1487 /* kernel-side HPT needed, but couldn't allocate one */ 1488 error_setg_errno(errp, errno, 1489 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1490 shift); 1491 /* This is almost certainly fatal, but if the caller really 1492 * wants to carry on with shift == 0, it's welcome to try */ 1493 } else if (rc > 0) { 1494 /* kernel-side HPT allocated */ 1495 if (rc != shift) { 1496 error_setg(errp, 1497 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1498 shift, rc); 1499 } 1500 1501 spapr->htab_shift = shift; 1502 spapr->htab = NULL; 1503 } else { 1504 /* kernel-side HPT not needed, allocate in userspace instead */ 1505 size_t size = 1ULL << shift; 1506 int i; 1507 1508 spapr->htab = qemu_memalign(size, size); 1509 if (!spapr->htab) { 1510 error_setg_errno(errp, errno, 1511 "Could not allocate HPT of order %d", shift); 1512 return; 1513 } 1514 1515 memset(spapr->htab, 0, size); 1516 spapr->htab_shift = shift; 1517 1518 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1519 DIRTY_HPTE(HPTE(spapr->htab, i)); 1520 } 1521 } 1522 /* We're setting up a hash table, so that means we're not radix */ 1523 spapr->patb_entry = 0; 1524 } 1525 1526 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1527 { 1528 int hpt_shift; 1529 1530 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1531 || (spapr->cas_reboot 1532 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1533 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1534 } else { 1535 uint64_t current_ram_size; 1536 1537 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1538 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1539 } 1540 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1541 1542 if (spapr->vrma_adjust) { 1543 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1544 spapr->htab_shift); 1545 } 1546 } 1547 1548 static int spapr_reset_drcs(Object *child, void *opaque) 1549 { 1550 sPAPRDRConnector *drc = 1551 (sPAPRDRConnector *) object_dynamic_cast(child, 1552 TYPE_SPAPR_DR_CONNECTOR); 1553 1554 if (drc) { 1555 spapr_drc_reset(drc); 1556 } 1557 1558 return 0; 1559 } 1560 1561 static void spapr_machine_reset(void) 1562 { 1563 MachineState *machine = MACHINE(qdev_get_machine()); 1564 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1565 PowerPCCPU *first_ppc_cpu; 1566 uint32_t rtas_limit; 1567 hwaddr rtas_addr, fdt_addr; 1568 void *fdt; 1569 int rc; 1570 1571 spapr_caps_apply(spapr); 1572 1573 first_ppc_cpu = POWERPC_CPU(first_cpu); 1574 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1575 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1576 spapr->max_compat_pvr)) { 1577 /* If using KVM with radix mode available, VCPUs can be started 1578 * without a HPT because KVM will start them in radix mode. 1579 * Set the GR bit in PATB so that we know there is no HPT. */ 1580 spapr->patb_entry = PATBE1_GR; 1581 } else { 1582 spapr_setup_hpt_and_vrma(spapr); 1583 } 1584 1585 /* if this reset wasn't generated by CAS, we should reset our 1586 * negotiated options and start from scratch */ 1587 if (!spapr->cas_reboot) { 1588 spapr_ovec_cleanup(spapr->ov5_cas); 1589 spapr->ov5_cas = spapr_ovec_new(); 1590 1591 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); 1592 } 1593 1594 if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 1595 spapr_irq_msi_reset(spapr); 1596 } 1597 1598 qemu_devices_reset(); 1599 1600 /* DRC reset may cause a device to be unplugged. This will cause troubles 1601 * if this device is used by another device (eg, a running vhost backend 1602 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1603 * situations, we reset DRCs after all devices have been reset. 1604 */ 1605 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1606 1607 spapr_clear_pending_events(spapr); 1608 1609 /* 1610 * We place the device tree and RTAS just below either the top of the RMA, 1611 * or just below 2GB, whichever is lowere, so that it can be 1612 * processed with 32-bit real mode code if necessary 1613 */ 1614 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1615 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1616 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1617 1618 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1619 1620 spapr_load_rtas(spapr, fdt, rtas_addr); 1621 1622 rc = fdt_pack(fdt); 1623 1624 /* Should only fail if we've built a corrupted tree */ 1625 assert(rc == 0); 1626 1627 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1628 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1629 fdt_totalsize(fdt), FDT_MAX_SIZE); 1630 exit(1); 1631 } 1632 1633 /* Load the fdt */ 1634 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1635 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1636 g_free(fdt); 1637 1638 /* Set up the entry state */ 1639 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); 1640 first_ppc_cpu->env.gpr[5] = 0; 1641 1642 spapr->cas_reboot = false; 1643 } 1644 1645 static void spapr_create_nvram(sPAPRMachineState *spapr) 1646 { 1647 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1648 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1649 1650 if (dinfo) { 1651 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1652 &error_fatal); 1653 } 1654 1655 qdev_init_nofail(dev); 1656 1657 spapr->nvram = (struct sPAPRNVRAM *)dev; 1658 } 1659 1660 static void spapr_rtc_create(sPAPRMachineState *spapr) 1661 { 1662 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1663 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1664 &error_fatal); 1665 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1666 &error_fatal); 1667 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1668 "date", &error_fatal); 1669 } 1670 1671 /* Returns whether we want to use VGA or not */ 1672 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1673 { 1674 switch (vga_interface_type) { 1675 case VGA_NONE: 1676 return false; 1677 case VGA_DEVICE: 1678 return true; 1679 case VGA_STD: 1680 case VGA_VIRTIO: 1681 return pci_vga_init(pci_bus) != NULL; 1682 default: 1683 error_setg(errp, 1684 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1685 return false; 1686 } 1687 } 1688 1689 static int spapr_pre_load(void *opaque) 1690 { 1691 int rc; 1692 1693 rc = spapr_caps_pre_load(opaque); 1694 if (rc) { 1695 return rc; 1696 } 1697 1698 return 0; 1699 } 1700 1701 static int spapr_post_load(void *opaque, int version_id) 1702 { 1703 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1704 int err = 0; 1705 1706 err = spapr_caps_post_migration(spapr); 1707 if (err) { 1708 return err; 1709 } 1710 1711 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1712 CPUState *cs; 1713 CPU_FOREACH(cs) { 1714 PowerPCCPU *cpu = POWERPC_CPU(cs); 1715 icp_resend(ICP(cpu->intc)); 1716 } 1717 } 1718 1719 /* In earlier versions, there was no separate qdev for the PAPR 1720 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1721 * So when migrating from those versions, poke the incoming offset 1722 * value into the RTC device */ 1723 if (version_id < 3) { 1724 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1725 } 1726 1727 if (kvm_enabled() && spapr->patb_entry) { 1728 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1729 bool radix = !!(spapr->patb_entry & PATBE1_GR); 1730 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1731 1732 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1733 if (err) { 1734 error_report("Process table config unsupported by the host"); 1735 return -EINVAL; 1736 } 1737 } 1738 1739 return err; 1740 } 1741 1742 static int spapr_pre_save(void *opaque) 1743 { 1744 int rc; 1745 1746 rc = spapr_caps_pre_save(opaque); 1747 if (rc) { 1748 return rc; 1749 } 1750 1751 return 0; 1752 } 1753 1754 static bool version_before_3(void *opaque, int version_id) 1755 { 1756 return version_id < 3; 1757 } 1758 1759 static bool spapr_pending_events_needed(void *opaque) 1760 { 1761 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1762 return !QTAILQ_EMPTY(&spapr->pending_events); 1763 } 1764 1765 static const VMStateDescription vmstate_spapr_event_entry = { 1766 .name = "spapr_event_log_entry", 1767 .version_id = 1, 1768 .minimum_version_id = 1, 1769 .fields = (VMStateField[]) { 1770 VMSTATE_UINT32(summary, sPAPREventLogEntry), 1771 VMSTATE_UINT32(extended_length, sPAPREventLogEntry), 1772 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, 1773 NULL, extended_length), 1774 VMSTATE_END_OF_LIST() 1775 }, 1776 }; 1777 1778 static const VMStateDescription vmstate_spapr_pending_events = { 1779 .name = "spapr_pending_events", 1780 .version_id = 1, 1781 .minimum_version_id = 1, 1782 .needed = spapr_pending_events_needed, 1783 .fields = (VMStateField[]) { 1784 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, 1785 vmstate_spapr_event_entry, sPAPREventLogEntry, next), 1786 VMSTATE_END_OF_LIST() 1787 }, 1788 }; 1789 1790 static bool spapr_ov5_cas_needed(void *opaque) 1791 { 1792 sPAPRMachineState *spapr = opaque; 1793 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1794 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1795 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1796 bool cas_needed; 1797 1798 /* Prior to the introduction of sPAPROptionVector, we had two option 1799 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1800 * Both of these options encode machine topology into the device-tree 1801 * in such a way that the now-booted OS should still be able to interact 1802 * appropriately with QEMU regardless of what options were actually 1803 * negotiatied on the source side. 1804 * 1805 * As such, we can avoid migrating the CAS-negotiated options if these 1806 * are the only options available on the current machine/platform. 1807 * Since these are the only options available for pseries-2.7 and 1808 * earlier, this allows us to maintain old->new/new->old migration 1809 * compatibility. 1810 * 1811 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1812 * via default pseries-2.8 machines and explicit command-line parameters. 1813 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1814 * of the actual CAS-negotiated values to continue working properly. For 1815 * example, availability of memory unplug depends on knowing whether 1816 * OV5_HP_EVT was negotiated via CAS. 1817 * 1818 * Thus, for any cases where the set of available CAS-negotiatable 1819 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1820 * include the CAS-negotiated options in the migration stream, unless 1821 * if they affect boot time behaviour only. 1822 */ 1823 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1824 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1825 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1826 1827 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1828 * the mask itself since in the future it's possible "legacy" bits may be 1829 * removed via machine options, which could generate a false positive 1830 * that breaks migration. 1831 */ 1832 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1833 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1834 1835 spapr_ovec_cleanup(ov5_mask); 1836 spapr_ovec_cleanup(ov5_legacy); 1837 spapr_ovec_cleanup(ov5_removed); 1838 1839 return cas_needed; 1840 } 1841 1842 static const VMStateDescription vmstate_spapr_ov5_cas = { 1843 .name = "spapr_option_vector_ov5_cas", 1844 .version_id = 1, 1845 .minimum_version_id = 1, 1846 .needed = spapr_ov5_cas_needed, 1847 .fields = (VMStateField[]) { 1848 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1849 vmstate_spapr_ovec, sPAPROptionVector), 1850 VMSTATE_END_OF_LIST() 1851 }, 1852 }; 1853 1854 static bool spapr_patb_entry_needed(void *opaque) 1855 { 1856 sPAPRMachineState *spapr = opaque; 1857 1858 return !!spapr->patb_entry; 1859 } 1860 1861 static const VMStateDescription vmstate_spapr_patb_entry = { 1862 .name = "spapr_patb_entry", 1863 .version_id = 1, 1864 .minimum_version_id = 1, 1865 .needed = spapr_patb_entry_needed, 1866 .fields = (VMStateField[]) { 1867 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1868 VMSTATE_END_OF_LIST() 1869 }, 1870 }; 1871 1872 static bool spapr_irq_map_needed(void *opaque) 1873 { 1874 sPAPRMachineState *spapr = opaque; 1875 1876 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1877 } 1878 1879 static const VMStateDescription vmstate_spapr_irq_map = { 1880 .name = "spapr_irq_map", 1881 .version_id = 1, 1882 .minimum_version_id = 1, 1883 .needed = spapr_irq_map_needed, 1884 .fields = (VMStateField[]) { 1885 VMSTATE_BITMAP(irq_map, sPAPRMachineState, 0, irq_map_nr), 1886 VMSTATE_END_OF_LIST() 1887 }, 1888 }; 1889 1890 static const VMStateDescription vmstate_spapr = { 1891 .name = "spapr", 1892 .version_id = 3, 1893 .minimum_version_id = 1, 1894 .pre_load = spapr_pre_load, 1895 .post_load = spapr_post_load, 1896 .pre_save = spapr_pre_save, 1897 .fields = (VMStateField[]) { 1898 /* used to be @next_irq */ 1899 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1900 1901 /* RTC offset */ 1902 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1903 1904 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1905 VMSTATE_END_OF_LIST() 1906 }, 1907 .subsections = (const VMStateDescription*[]) { 1908 &vmstate_spapr_ov5_cas, 1909 &vmstate_spapr_patb_entry, 1910 &vmstate_spapr_pending_events, 1911 &vmstate_spapr_cap_htm, 1912 &vmstate_spapr_cap_vsx, 1913 &vmstate_spapr_cap_dfp, 1914 &vmstate_spapr_cap_cfpc, 1915 &vmstate_spapr_cap_sbbc, 1916 &vmstate_spapr_cap_ibs, 1917 &vmstate_spapr_irq_map, 1918 NULL 1919 } 1920 }; 1921 1922 static int htab_save_setup(QEMUFile *f, void *opaque) 1923 { 1924 sPAPRMachineState *spapr = opaque; 1925 1926 /* "Iteration" header */ 1927 if (!spapr->htab_shift) { 1928 qemu_put_be32(f, -1); 1929 } else { 1930 qemu_put_be32(f, spapr->htab_shift); 1931 } 1932 1933 if (spapr->htab) { 1934 spapr->htab_save_index = 0; 1935 spapr->htab_first_pass = true; 1936 } else { 1937 if (spapr->htab_shift) { 1938 assert(kvm_enabled()); 1939 } 1940 } 1941 1942 1943 return 0; 1944 } 1945 1946 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr, 1947 int chunkstart, int n_valid, int n_invalid) 1948 { 1949 qemu_put_be32(f, chunkstart); 1950 qemu_put_be16(f, n_valid); 1951 qemu_put_be16(f, n_invalid); 1952 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1953 HASH_PTE_SIZE_64 * n_valid); 1954 } 1955 1956 static void htab_save_end_marker(QEMUFile *f) 1957 { 1958 qemu_put_be32(f, 0); 1959 qemu_put_be16(f, 0); 1960 qemu_put_be16(f, 0); 1961 } 1962 1963 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1964 int64_t max_ns) 1965 { 1966 bool has_timeout = max_ns != -1; 1967 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1968 int index = spapr->htab_save_index; 1969 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1970 1971 assert(spapr->htab_first_pass); 1972 1973 do { 1974 int chunkstart; 1975 1976 /* Consume invalid HPTEs */ 1977 while ((index < htabslots) 1978 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1979 CLEAN_HPTE(HPTE(spapr->htab, index)); 1980 index++; 1981 } 1982 1983 /* Consume valid HPTEs */ 1984 chunkstart = index; 1985 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1986 && HPTE_VALID(HPTE(spapr->htab, index))) { 1987 CLEAN_HPTE(HPTE(spapr->htab, index)); 1988 index++; 1989 } 1990 1991 if (index > chunkstart) { 1992 int n_valid = index - chunkstart; 1993 1994 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 1995 1996 if (has_timeout && 1997 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1998 break; 1999 } 2000 } 2001 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2002 2003 if (index >= htabslots) { 2004 assert(index == htabslots); 2005 index = 0; 2006 spapr->htab_first_pass = false; 2007 } 2008 spapr->htab_save_index = index; 2009 } 2010 2011 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 2012 int64_t max_ns) 2013 { 2014 bool final = max_ns < 0; 2015 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2016 int examined = 0, sent = 0; 2017 int index = spapr->htab_save_index; 2018 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2019 2020 assert(!spapr->htab_first_pass); 2021 2022 do { 2023 int chunkstart, invalidstart; 2024 2025 /* Consume non-dirty HPTEs */ 2026 while ((index < htabslots) 2027 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2028 index++; 2029 examined++; 2030 } 2031 2032 chunkstart = index; 2033 /* Consume valid dirty HPTEs */ 2034 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2035 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2036 && HPTE_VALID(HPTE(spapr->htab, index))) { 2037 CLEAN_HPTE(HPTE(spapr->htab, index)); 2038 index++; 2039 examined++; 2040 } 2041 2042 invalidstart = index; 2043 /* Consume invalid dirty HPTEs */ 2044 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2045 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2046 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2047 CLEAN_HPTE(HPTE(spapr->htab, index)); 2048 index++; 2049 examined++; 2050 } 2051 2052 if (index > chunkstart) { 2053 int n_valid = invalidstart - chunkstart; 2054 int n_invalid = index - invalidstart; 2055 2056 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2057 sent += index - chunkstart; 2058 2059 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2060 break; 2061 } 2062 } 2063 2064 if (examined >= htabslots) { 2065 break; 2066 } 2067 2068 if (index >= htabslots) { 2069 assert(index == htabslots); 2070 index = 0; 2071 } 2072 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2073 2074 if (index >= htabslots) { 2075 assert(index == htabslots); 2076 index = 0; 2077 } 2078 2079 spapr->htab_save_index = index; 2080 2081 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2082 } 2083 2084 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2085 #define MAX_KVM_BUF_SIZE 2048 2086 2087 static int htab_save_iterate(QEMUFile *f, void *opaque) 2088 { 2089 sPAPRMachineState *spapr = opaque; 2090 int fd; 2091 int rc = 0; 2092 2093 /* Iteration header */ 2094 if (!spapr->htab_shift) { 2095 qemu_put_be32(f, -1); 2096 return 1; 2097 } else { 2098 qemu_put_be32(f, 0); 2099 } 2100 2101 if (!spapr->htab) { 2102 assert(kvm_enabled()); 2103 2104 fd = get_htab_fd(spapr); 2105 if (fd < 0) { 2106 return fd; 2107 } 2108 2109 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2110 if (rc < 0) { 2111 return rc; 2112 } 2113 } else if (spapr->htab_first_pass) { 2114 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2115 } else { 2116 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2117 } 2118 2119 htab_save_end_marker(f); 2120 2121 return rc; 2122 } 2123 2124 static int htab_save_complete(QEMUFile *f, void *opaque) 2125 { 2126 sPAPRMachineState *spapr = opaque; 2127 int fd; 2128 2129 /* Iteration header */ 2130 if (!spapr->htab_shift) { 2131 qemu_put_be32(f, -1); 2132 return 0; 2133 } else { 2134 qemu_put_be32(f, 0); 2135 } 2136 2137 if (!spapr->htab) { 2138 int rc; 2139 2140 assert(kvm_enabled()); 2141 2142 fd = get_htab_fd(spapr); 2143 if (fd < 0) { 2144 return fd; 2145 } 2146 2147 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2148 if (rc < 0) { 2149 return rc; 2150 } 2151 } else { 2152 if (spapr->htab_first_pass) { 2153 htab_save_first_pass(f, spapr, -1); 2154 } 2155 htab_save_later_pass(f, spapr, -1); 2156 } 2157 2158 /* End marker */ 2159 htab_save_end_marker(f); 2160 2161 return 0; 2162 } 2163 2164 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2165 { 2166 sPAPRMachineState *spapr = opaque; 2167 uint32_t section_hdr; 2168 int fd = -1; 2169 Error *local_err = NULL; 2170 2171 if (version_id < 1 || version_id > 1) { 2172 error_report("htab_load() bad version"); 2173 return -EINVAL; 2174 } 2175 2176 section_hdr = qemu_get_be32(f); 2177 2178 if (section_hdr == -1) { 2179 spapr_free_hpt(spapr); 2180 return 0; 2181 } 2182 2183 if (section_hdr) { 2184 /* First section gives the htab size */ 2185 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2186 if (local_err) { 2187 error_report_err(local_err); 2188 return -EINVAL; 2189 } 2190 return 0; 2191 } 2192 2193 if (!spapr->htab) { 2194 assert(kvm_enabled()); 2195 2196 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2197 if (fd < 0) { 2198 error_report_err(local_err); 2199 return fd; 2200 } 2201 } 2202 2203 while (true) { 2204 uint32_t index; 2205 uint16_t n_valid, n_invalid; 2206 2207 index = qemu_get_be32(f); 2208 n_valid = qemu_get_be16(f); 2209 n_invalid = qemu_get_be16(f); 2210 2211 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2212 /* End of Stream */ 2213 break; 2214 } 2215 2216 if ((index + n_valid + n_invalid) > 2217 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2218 /* Bad index in stream */ 2219 error_report( 2220 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2221 index, n_valid, n_invalid, spapr->htab_shift); 2222 return -EINVAL; 2223 } 2224 2225 if (spapr->htab) { 2226 if (n_valid) { 2227 qemu_get_buffer(f, HPTE(spapr->htab, index), 2228 HASH_PTE_SIZE_64 * n_valid); 2229 } 2230 if (n_invalid) { 2231 memset(HPTE(spapr->htab, index + n_valid), 0, 2232 HASH_PTE_SIZE_64 * n_invalid); 2233 } 2234 } else { 2235 int rc; 2236 2237 assert(fd >= 0); 2238 2239 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2240 if (rc < 0) { 2241 return rc; 2242 } 2243 } 2244 } 2245 2246 if (!spapr->htab) { 2247 assert(fd >= 0); 2248 close(fd); 2249 } 2250 2251 return 0; 2252 } 2253 2254 static void htab_save_cleanup(void *opaque) 2255 { 2256 sPAPRMachineState *spapr = opaque; 2257 2258 close_htab_fd(spapr); 2259 } 2260 2261 static SaveVMHandlers savevm_htab_handlers = { 2262 .save_setup = htab_save_setup, 2263 .save_live_iterate = htab_save_iterate, 2264 .save_live_complete_precopy = htab_save_complete, 2265 .save_cleanup = htab_save_cleanup, 2266 .load_state = htab_load, 2267 }; 2268 2269 static void spapr_boot_set(void *opaque, const char *boot_device, 2270 Error **errp) 2271 { 2272 MachineState *machine = MACHINE(opaque); 2273 machine->boot_order = g_strdup(boot_device); 2274 } 2275 2276 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 2277 { 2278 MachineState *machine = MACHINE(spapr); 2279 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2280 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2281 int i; 2282 2283 for (i = 0; i < nr_lmbs; i++) { 2284 uint64_t addr; 2285 2286 addr = i * lmb_size + machine->device_memory->base; 2287 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2288 addr / lmb_size); 2289 } 2290 } 2291 2292 /* 2293 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2294 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2295 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2296 */ 2297 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2298 { 2299 int i; 2300 2301 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2302 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2303 " is not aligned to %" PRIu64 " MiB", 2304 machine->ram_size, 2305 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2306 return; 2307 } 2308 2309 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2310 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2311 " is not aligned to %" PRIu64 " MiB", 2312 machine->ram_size, 2313 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2314 return; 2315 } 2316 2317 for (i = 0; i < nb_numa_nodes; i++) { 2318 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2319 error_setg(errp, 2320 "Node %d memory size 0x%" PRIx64 2321 " is not aligned to %" PRIu64 " MiB", 2322 i, numa_info[i].node_mem, 2323 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2324 return; 2325 } 2326 } 2327 } 2328 2329 /* find cpu slot in machine->possible_cpus by core_id */ 2330 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2331 { 2332 int index = id / smp_threads; 2333 2334 if (index >= ms->possible_cpus->len) { 2335 return NULL; 2336 } 2337 if (idx) { 2338 *idx = index; 2339 } 2340 return &ms->possible_cpus->cpus[index]; 2341 } 2342 2343 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) 2344 { 2345 Error *local_err = NULL; 2346 bool vsmt_user = !!spapr->vsmt; 2347 int kvm_smt = kvmppc_smt_threads(); 2348 int ret; 2349 2350 if (!kvm_enabled() && (smp_threads > 1)) { 2351 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2352 "on a pseries machine"); 2353 goto out; 2354 } 2355 if (!is_power_of_2(smp_threads)) { 2356 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2357 "machine because it must be a power of 2", smp_threads); 2358 goto out; 2359 } 2360 2361 /* Detemine the VSMT mode to use: */ 2362 if (vsmt_user) { 2363 if (spapr->vsmt < smp_threads) { 2364 error_setg(&local_err, "Cannot support VSMT mode %d" 2365 " because it must be >= threads/core (%d)", 2366 spapr->vsmt, smp_threads); 2367 goto out; 2368 } 2369 /* In this case, spapr->vsmt has been set by the command line */ 2370 } else { 2371 /* 2372 * Default VSMT value is tricky, because we need it to be as 2373 * consistent as possible (for migration), but this requires 2374 * changing it for at least some existing cases. We pick 8 as 2375 * the value that we'd get with KVM on POWER8, the 2376 * overwhelmingly common case in production systems. 2377 */ 2378 spapr->vsmt = MAX(8, smp_threads); 2379 } 2380 2381 /* KVM: If necessary, set the SMT mode: */ 2382 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2383 ret = kvmppc_set_smt_threads(spapr->vsmt); 2384 if (ret) { 2385 /* Looks like KVM isn't able to change VSMT mode */ 2386 error_setg(&local_err, 2387 "Failed to set KVM's VSMT mode to %d (errno %d)", 2388 spapr->vsmt, ret); 2389 /* We can live with that if the default one is big enough 2390 * for the number of threads, and a submultiple of the one 2391 * we want. In this case we'll waste some vcpu ids, but 2392 * behaviour will be correct */ 2393 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2394 warn_report_err(local_err); 2395 local_err = NULL; 2396 goto out; 2397 } else { 2398 if (!vsmt_user) { 2399 error_append_hint(&local_err, 2400 "On PPC, a VM with %d threads/core" 2401 " on a host with %d threads/core" 2402 " requires the use of VSMT mode %d.\n", 2403 smp_threads, kvm_smt, spapr->vsmt); 2404 } 2405 kvmppc_hint_smt_possible(&local_err); 2406 goto out; 2407 } 2408 } 2409 } 2410 /* else TCG: nothing to do currently */ 2411 out: 2412 error_propagate(errp, local_err); 2413 } 2414 2415 static void spapr_init_cpus(sPAPRMachineState *spapr) 2416 { 2417 MachineState *machine = MACHINE(spapr); 2418 MachineClass *mc = MACHINE_GET_CLASS(machine); 2419 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2420 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2421 const CPUArchIdList *possible_cpus; 2422 int boot_cores_nr = smp_cpus / smp_threads; 2423 int i; 2424 2425 possible_cpus = mc->possible_cpu_arch_ids(machine); 2426 if (mc->has_hotpluggable_cpus) { 2427 if (smp_cpus % smp_threads) { 2428 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2429 smp_cpus, smp_threads); 2430 exit(1); 2431 } 2432 if (max_cpus % smp_threads) { 2433 error_report("max_cpus (%u) must be multiple of threads (%u)", 2434 max_cpus, smp_threads); 2435 exit(1); 2436 } 2437 } else { 2438 if (max_cpus != smp_cpus) { 2439 error_report("This machine version does not support CPU hotplug"); 2440 exit(1); 2441 } 2442 boot_cores_nr = possible_cpus->len; 2443 } 2444 2445 /* VSMT must be set in order to be able to compute VCPU ids, ie to 2446 * call xics_max_server_number() or spapr_vcpu_id(). 2447 */ 2448 spapr_set_vsmt_mode(spapr, &error_fatal); 2449 2450 if (smc->pre_2_10_has_unused_icps) { 2451 int i; 2452 2453 for (i = 0; i < xics_max_server_number(spapr); i++) { 2454 /* Dummy entries get deregistered when real ICPState objects 2455 * are registered during CPU core hotplug. 2456 */ 2457 pre_2_10_vmstate_register_dummy_icp(i); 2458 } 2459 } 2460 2461 for (i = 0; i < possible_cpus->len; i++) { 2462 int core_id = i * smp_threads; 2463 2464 if (mc->has_hotpluggable_cpus) { 2465 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2466 spapr_vcpu_id(spapr, core_id)); 2467 } 2468 2469 if (i < boot_cores_nr) { 2470 Object *core = object_new(type); 2471 int nr_threads = smp_threads; 2472 2473 /* Handle the partially filled core for older machine types */ 2474 if ((i + 1) * smp_threads >= smp_cpus) { 2475 nr_threads = smp_cpus - i * smp_threads; 2476 } 2477 2478 object_property_set_int(core, nr_threads, "nr-threads", 2479 &error_fatal); 2480 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2481 &error_fatal); 2482 object_property_set_bool(core, true, "realized", &error_fatal); 2483 2484 object_unref(core); 2485 } 2486 } 2487 } 2488 2489 /* pSeries LPAR / sPAPR hardware init */ 2490 static void spapr_machine_init(MachineState *machine) 2491 { 2492 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2493 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2494 const char *kernel_filename = machine->kernel_filename; 2495 const char *initrd_filename = machine->initrd_filename; 2496 PCIHostState *phb; 2497 int i; 2498 MemoryRegion *sysmem = get_system_memory(); 2499 MemoryRegion *ram = g_new(MemoryRegion, 1); 2500 hwaddr node0_size = spapr_node0_size(machine); 2501 long load_limit, fw_size; 2502 char *filename; 2503 Error *resize_hpt_err = NULL; 2504 2505 msi_nonbroken = true; 2506 2507 QLIST_INIT(&spapr->phbs); 2508 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2509 2510 /* Determine capabilities to run with */ 2511 spapr_caps_init(spapr); 2512 2513 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2514 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2515 /* 2516 * If the user explicitly requested a mode we should either 2517 * supply it, or fail completely (which we do below). But if 2518 * it's not set explicitly, we reset our mode to something 2519 * that works 2520 */ 2521 if (resize_hpt_err) { 2522 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2523 error_free(resize_hpt_err); 2524 resize_hpt_err = NULL; 2525 } else { 2526 spapr->resize_hpt = smc->resize_hpt_default; 2527 } 2528 } 2529 2530 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2531 2532 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2533 /* 2534 * User requested HPT resize, but this host can't supply it. Bail out 2535 */ 2536 error_report_err(resize_hpt_err); 2537 exit(1); 2538 } 2539 2540 spapr->rma_size = node0_size; 2541 2542 /* With KVM, we don't actually know whether KVM supports an 2543 * unbounded RMA (PR KVM) or is limited by the hash table size 2544 * (HV KVM using VRMA), so we always assume the latter 2545 * 2546 * In that case, we also limit the initial allocations for RTAS 2547 * etc... to 256M since we have no way to know what the VRMA size 2548 * is going to be as it depends on the size of the hash table 2549 * which isn't determined yet. 2550 */ 2551 if (kvm_enabled()) { 2552 spapr->vrma_adjust = 1; 2553 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2554 } 2555 2556 /* Actually we don't support unbounded RMA anymore since we added 2557 * proper emulation of HV mode. The max we can get is 16G which 2558 * also happens to be what we configure for PAPR mode so make sure 2559 * we don't do anything bigger than that 2560 */ 2561 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2562 2563 if (spapr->rma_size > node0_size) { 2564 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2565 spapr->rma_size); 2566 exit(1); 2567 } 2568 2569 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2570 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2571 2572 /* Set up Interrupt Controller before we create the VCPUs */ 2573 smc->irq->init(spapr, &error_fatal); 2574 2575 /* Set up containers for ibm,client-architecture-support negotiated options 2576 */ 2577 spapr->ov5 = spapr_ovec_new(); 2578 spapr->ov5_cas = spapr_ovec_new(); 2579 2580 if (smc->dr_lmb_enabled) { 2581 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2582 spapr_validate_node_memory(machine, &error_fatal); 2583 } 2584 2585 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2586 2587 /* advertise support for dedicated HP event source to guests */ 2588 if (spapr->use_hotplug_event_source) { 2589 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2590 } 2591 2592 /* advertise support for HPT resizing */ 2593 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2594 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2595 } 2596 2597 /* advertise support for ibm,dyamic-memory-v2 */ 2598 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2599 2600 /* init CPUs */ 2601 spapr_init_cpus(spapr); 2602 2603 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2604 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2605 spapr->max_compat_pvr)) { 2606 /* KVM and TCG always allow GTSE with radix... */ 2607 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2608 } 2609 /* ... but not with hash (currently). */ 2610 2611 if (kvm_enabled()) { 2612 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2613 kvmppc_enable_logical_ci_hcalls(); 2614 kvmppc_enable_set_mode_hcall(); 2615 2616 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2617 kvmppc_enable_clear_ref_mod_hcalls(); 2618 } 2619 2620 /* allocate RAM */ 2621 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2622 machine->ram_size); 2623 memory_region_add_subregion(sysmem, 0, ram); 2624 2625 /* always allocate the device memory information */ 2626 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2627 2628 /* initialize hotplug memory address space */ 2629 if (machine->ram_size < machine->maxram_size) { 2630 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2631 /* 2632 * Limit the number of hotpluggable memory slots to half the number 2633 * slots that KVM supports, leaving the other half for PCI and other 2634 * devices. However ensure that number of slots doesn't drop below 32. 2635 */ 2636 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2637 SPAPR_MAX_RAM_SLOTS; 2638 2639 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2640 max_memslots = SPAPR_MAX_RAM_SLOTS; 2641 } 2642 if (machine->ram_slots > max_memslots) { 2643 error_report("Specified number of memory slots %" 2644 PRIu64" exceeds max supported %d", 2645 machine->ram_slots, max_memslots); 2646 exit(1); 2647 } 2648 2649 machine->device_memory->base = ROUND_UP(machine->ram_size, 2650 SPAPR_DEVICE_MEM_ALIGN); 2651 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2652 "device-memory", device_mem_size); 2653 memory_region_add_subregion(sysmem, machine->device_memory->base, 2654 &machine->device_memory->mr); 2655 } 2656 2657 if (smc->dr_lmb_enabled) { 2658 spapr_create_lmb_dr_connectors(spapr); 2659 } 2660 2661 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2662 if (!filename) { 2663 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2664 exit(1); 2665 } 2666 spapr->rtas_size = get_image_size(filename); 2667 if (spapr->rtas_size < 0) { 2668 error_report("Could not get size of LPAR rtas '%s'", filename); 2669 exit(1); 2670 } 2671 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2672 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2673 error_report("Could not load LPAR rtas '%s'", filename); 2674 exit(1); 2675 } 2676 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2677 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2678 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2679 exit(1); 2680 } 2681 g_free(filename); 2682 2683 /* Set up RTAS event infrastructure */ 2684 spapr_events_init(spapr); 2685 2686 /* Set up the RTC RTAS interfaces */ 2687 spapr_rtc_create(spapr); 2688 2689 /* Set up VIO bus */ 2690 spapr->vio_bus = spapr_vio_bus_init(); 2691 2692 for (i = 0; i < serial_max_hds(); i++) { 2693 if (serial_hd(i)) { 2694 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2695 } 2696 } 2697 2698 /* We always have at least the nvram device on VIO */ 2699 spapr_create_nvram(spapr); 2700 2701 /* Set up PCI */ 2702 spapr_pci_rtas_init(); 2703 2704 phb = spapr_create_phb(spapr, 0); 2705 2706 for (i = 0; i < nb_nics; i++) { 2707 NICInfo *nd = &nd_table[i]; 2708 2709 if (!nd->model) { 2710 nd->model = g_strdup("spapr-vlan"); 2711 } 2712 2713 if (g_str_equal(nd->model, "spapr-vlan") || 2714 g_str_equal(nd->model, "ibmveth")) { 2715 spapr_vlan_create(spapr->vio_bus, nd); 2716 } else { 2717 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2718 } 2719 } 2720 2721 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2722 spapr_vscsi_create(spapr->vio_bus); 2723 } 2724 2725 /* Graphics */ 2726 if (spapr_vga_init(phb->bus, &error_fatal)) { 2727 spapr->has_graphics = true; 2728 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2729 } 2730 2731 if (machine->usb) { 2732 if (smc->use_ohci_by_default) { 2733 pci_create_simple(phb->bus, -1, "pci-ohci"); 2734 } else { 2735 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2736 } 2737 2738 if (spapr->has_graphics) { 2739 USBBus *usb_bus = usb_bus_find(-1); 2740 2741 usb_create_simple(usb_bus, "usb-kbd"); 2742 usb_create_simple(usb_bus, "usb-mouse"); 2743 } 2744 } 2745 2746 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) { 2747 error_report( 2748 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2749 MIN_RMA_SLOF); 2750 exit(1); 2751 } 2752 2753 if (kernel_filename) { 2754 uint64_t lowaddr = 0; 2755 2756 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2757 NULL, NULL, &lowaddr, NULL, 1, 2758 PPC_ELF_MACHINE, 0, 0); 2759 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2760 spapr->kernel_size = load_elf(kernel_filename, 2761 translate_kernel_address, NULL, NULL, 2762 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2763 0, 0); 2764 spapr->kernel_le = spapr->kernel_size > 0; 2765 } 2766 if (spapr->kernel_size < 0) { 2767 error_report("error loading %s: %s", kernel_filename, 2768 load_elf_strerror(spapr->kernel_size)); 2769 exit(1); 2770 } 2771 2772 /* load initrd */ 2773 if (initrd_filename) { 2774 /* Try to locate the initrd in the gap between the kernel 2775 * and the firmware. Add a bit of space just in case 2776 */ 2777 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2778 + 0x1ffff) & ~0xffff; 2779 spapr->initrd_size = load_image_targphys(initrd_filename, 2780 spapr->initrd_base, 2781 load_limit 2782 - spapr->initrd_base); 2783 if (spapr->initrd_size < 0) { 2784 error_report("could not load initial ram disk '%s'", 2785 initrd_filename); 2786 exit(1); 2787 } 2788 } 2789 } 2790 2791 if (bios_name == NULL) { 2792 bios_name = FW_FILE_NAME; 2793 } 2794 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2795 if (!filename) { 2796 error_report("Could not find LPAR firmware '%s'", bios_name); 2797 exit(1); 2798 } 2799 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2800 if (fw_size <= 0) { 2801 error_report("Could not load LPAR firmware '%s'", filename); 2802 exit(1); 2803 } 2804 g_free(filename); 2805 2806 /* FIXME: Should register things through the MachineState's qdev 2807 * interface, this is a legacy from the sPAPREnvironment structure 2808 * which predated MachineState but had a similar function */ 2809 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2810 register_savevm_live(NULL, "spapr/htab", -1, 1, 2811 &savevm_htab_handlers, spapr); 2812 2813 qemu_register_boot_set(spapr_boot_set, spapr); 2814 2815 if (kvm_enabled()) { 2816 /* to stop and start vmclock */ 2817 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2818 &spapr->tb); 2819 2820 kvmppc_spapr_enable_inkernel_multitce(); 2821 } 2822 } 2823 2824 static int spapr_kvm_type(const char *vm_type) 2825 { 2826 if (!vm_type) { 2827 return 0; 2828 } 2829 2830 if (!strcmp(vm_type, "HV")) { 2831 return 1; 2832 } 2833 2834 if (!strcmp(vm_type, "PR")) { 2835 return 2; 2836 } 2837 2838 error_report("Unknown kvm-type specified '%s'", vm_type); 2839 exit(1); 2840 } 2841 2842 /* 2843 * Implementation of an interface to adjust firmware path 2844 * for the bootindex property handling. 2845 */ 2846 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2847 DeviceState *dev) 2848 { 2849 #define CAST(type, obj, name) \ 2850 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2851 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2852 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2853 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 2854 2855 if (d) { 2856 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2857 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2858 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2859 2860 if (spapr) { 2861 /* 2862 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2863 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2864 * in the top 16 bits of the 64-bit LUN 2865 */ 2866 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2867 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2868 (uint64_t)id << 48); 2869 } else if (virtio) { 2870 /* 2871 * We use SRP luns of the form 01000000 | (target << 8) | lun 2872 * in the top 32 bits of the 64-bit LUN 2873 * Note: the quote above is from SLOF and it is wrong, 2874 * the actual binding is: 2875 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2876 */ 2877 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2878 if (d->lun >= 256) { 2879 /* Use the LUN "flat space addressing method" */ 2880 id |= 0x4000; 2881 } 2882 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2883 (uint64_t)id << 32); 2884 } else if (usb) { 2885 /* 2886 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2887 * in the top 32 bits of the 64-bit LUN 2888 */ 2889 unsigned usb_port = atoi(usb->port->path); 2890 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2891 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2892 (uint64_t)id << 32); 2893 } 2894 } 2895 2896 /* 2897 * SLOF probes the USB devices, and if it recognizes that the device is a 2898 * storage device, it changes its name to "storage" instead of "usb-host", 2899 * and additionally adds a child node for the SCSI LUN, so the correct 2900 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2901 */ 2902 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2903 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2904 if (usb_host_dev_is_scsi_storage(usbdev)) { 2905 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2906 } 2907 } 2908 2909 if (phb) { 2910 /* Replace "pci" with "pci@800000020000000" */ 2911 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2912 } 2913 2914 if (vsc) { 2915 /* Same logic as virtio above */ 2916 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 2917 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 2918 } 2919 2920 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 2921 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 2922 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 2923 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 2924 } 2925 2926 return NULL; 2927 } 2928 2929 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2930 { 2931 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2932 2933 return g_strdup(spapr->kvm_type); 2934 } 2935 2936 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2937 { 2938 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2939 2940 g_free(spapr->kvm_type); 2941 spapr->kvm_type = g_strdup(value); 2942 } 2943 2944 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2945 { 2946 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2947 2948 return spapr->use_hotplug_event_source; 2949 } 2950 2951 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2952 Error **errp) 2953 { 2954 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2955 2956 spapr->use_hotplug_event_source = value; 2957 } 2958 2959 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 2960 { 2961 return true; 2962 } 2963 2964 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 2965 { 2966 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2967 2968 switch (spapr->resize_hpt) { 2969 case SPAPR_RESIZE_HPT_DEFAULT: 2970 return g_strdup("default"); 2971 case SPAPR_RESIZE_HPT_DISABLED: 2972 return g_strdup("disabled"); 2973 case SPAPR_RESIZE_HPT_ENABLED: 2974 return g_strdup("enabled"); 2975 case SPAPR_RESIZE_HPT_REQUIRED: 2976 return g_strdup("required"); 2977 } 2978 g_assert_not_reached(); 2979 } 2980 2981 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 2982 { 2983 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2984 2985 if (strcmp(value, "default") == 0) { 2986 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 2987 } else if (strcmp(value, "disabled") == 0) { 2988 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2989 } else if (strcmp(value, "enabled") == 0) { 2990 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 2991 } else if (strcmp(value, "required") == 0) { 2992 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 2993 } else { 2994 error_setg(errp, "Bad value for \"resize-hpt\" property"); 2995 } 2996 } 2997 2998 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 2999 void *opaque, Error **errp) 3000 { 3001 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3002 } 3003 3004 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3005 void *opaque, Error **errp) 3006 { 3007 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3008 } 3009 3010 static void spapr_instance_init(Object *obj) 3011 { 3012 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3013 3014 spapr->htab_fd = -1; 3015 spapr->use_hotplug_event_source = true; 3016 object_property_add_str(obj, "kvm-type", 3017 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3018 object_property_set_description(obj, "kvm-type", 3019 "Specifies the KVM virtualization mode (HV, PR)", 3020 NULL); 3021 object_property_add_bool(obj, "modern-hotplug-events", 3022 spapr_get_modern_hotplug_events, 3023 spapr_set_modern_hotplug_events, 3024 NULL); 3025 object_property_set_description(obj, "modern-hotplug-events", 3026 "Use dedicated hotplug event mechanism in" 3027 " place of standard EPOW events when possible" 3028 " (required for memory hot-unplug support)", 3029 NULL); 3030 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3031 "Maximum permitted CPU compatibility mode", 3032 &error_fatal); 3033 3034 object_property_add_str(obj, "resize-hpt", 3035 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3036 object_property_set_description(obj, "resize-hpt", 3037 "Resizing of the Hash Page Table (enabled, disabled, required)", 3038 NULL); 3039 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3040 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3041 object_property_set_description(obj, "vsmt", 3042 "Virtual SMT: KVM behaves as if this were" 3043 " the host's SMT mode", &error_abort); 3044 object_property_add_bool(obj, "vfio-no-msix-emulation", 3045 spapr_get_msix_emulation, NULL, NULL); 3046 } 3047 3048 static void spapr_machine_finalizefn(Object *obj) 3049 { 3050 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3051 3052 g_free(spapr->kvm_type); 3053 } 3054 3055 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3056 { 3057 cpu_synchronize_state(cs); 3058 ppc_cpu_do_system_reset(cs); 3059 } 3060 3061 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3062 { 3063 CPUState *cs; 3064 3065 CPU_FOREACH(cs) { 3066 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3067 } 3068 } 3069 3070 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3071 uint32_t node, bool dedicated_hp_event_source, 3072 Error **errp) 3073 { 3074 sPAPRDRConnector *drc; 3075 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3076 int i, fdt_offset, fdt_size; 3077 void *fdt; 3078 uint64_t addr = addr_start; 3079 bool hotplugged = spapr_drc_hotplugged(dev); 3080 Error *local_err = NULL; 3081 3082 for (i = 0; i < nr_lmbs; i++) { 3083 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3084 addr / SPAPR_MEMORY_BLOCK_SIZE); 3085 g_assert(drc); 3086 3087 fdt = create_device_tree(&fdt_size); 3088 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 3089 SPAPR_MEMORY_BLOCK_SIZE); 3090 3091 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3092 if (local_err) { 3093 while (addr > addr_start) { 3094 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3095 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3096 addr / SPAPR_MEMORY_BLOCK_SIZE); 3097 spapr_drc_detach(drc); 3098 } 3099 g_free(fdt); 3100 error_propagate(errp, local_err); 3101 return; 3102 } 3103 if (!hotplugged) { 3104 spapr_drc_reset(drc); 3105 } 3106 addr += SPAPR_MEMORY_BLOCK_SIZE; 3107 } 3108 /* send hotplug notification to the 3109 * guest only in case of hotplugged memory 3110 */ 3111 if (hotplugged) { 3112 if (dedicated_hp_event_source) { 3113 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3114 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3115 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3116 nr_lmbs, 3117 spapr_drc_index(drc)); 3118 } else { 3119 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3120 nr_lmbs); 3121 } 3122 } 3123 } 3124 3125 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3126 Error **errp) 3127 { 3128 Error *local_err = NULL; 3129 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3130 PCDIMMDevice *dimm = PC_DIMM(dev); 3131 uint64_t size, addr; 3132 uint32_t node; 3133 3134 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3135 3136 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3137 if (local_err) { 3138 goto out; 3139 } 3140 3141 addr = object_property_get_uint(OBJECT(dimm), 3142 PC_DIMM_ADDR_PROP, &local_err); 3143 if (local_err) { 3144 goto out_unplug; 3145 } 3146 3147 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, 3148 &error_abort); 3149 spapr_add_lmbs(dev, addr, size, node, 3150 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3151 &local_err); 3152 if (local_err) { 3153 goto out_unplug; 3154 } 3155 3156 return; 3157 3158 out_unplug: 3159 pc_dimm_unplug(dimm, MACHINE(ms)); 3160 out: 3161 error_propagate(errp, local_err); 3162 } 3163 3164 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3165 Error **errp) 3166 { 3167 const sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3168 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3169 PCDIMMDevice *dimm = PC_DIMM(dev); 3170 Error *local_err = NULL; 3171 uint64_t size; 3172 Object *memdev; 3173 hwaddr pagesize; 3174 3175 if (!smc->dr_lmb_enabled) { 3176 error_setg(errp, "Memory hotplug not supported for this machine"); 3177 return; 3178 } 3179 3180 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3181 if (local_err) { 3182 error_propagate(errp, local_err); 3183 return; 3184 } 3185 3186 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3187 error_setg(errp, "Hotplugged memory size must be a multiple of " 3188 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3189 return; 3190 } 3191 3192 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3193 &error_abort); 3194 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3195 spapr_check_pagesize(spapr, pagesize, &local_err); 3196 if (local_err) { 3197 error_propagate(errp, local_err); 3198 return; 3199 } 3200 3201 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3202 } 3203 3204 struct sPAPRDIMMState { 3205 PCDIMMDevice *dimm; 3206 uint32_t nr_lmbs; 3207 QTAILQ_ENTRY(sPAPRDIMMState) next; 3208 }; 3209 3210 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 3211 PCDIMMDevice *dimm) 3212 { 3213 sPAPRDIMMState *dimm_state = NULL; 3214 3215 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3216 if (dimm_state->dimm == dimm) { 3217 break; 3218 } 3219 } 3220 return dimm_state; 3221 } 3222 3223 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 3224 uint32_t nr_lmbs, 3225 PCDIMMDevice *dimm) 3226 { 3227 sPAPRDIMMState *ds = NULL; 3228 3229 /* 3230 * If this request is for a DIMM whose removal had failed earlier 3231 * (due to guest's refusal to remove the LMBs), we would have this 3232 * dimm already in the pending_dimm_unplugs list. In that 3233 * case don't add again. 3234 */ 3235 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3236 if (!ds) { 3237 ds = g_malloc0(sizeof(sPAPRDIMMState)); 3238 ds->nr_lmbs = nr_lmbs; 3239 ds->dimm = dimm; 3240 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3241 } 3242 return ds; 3243 } 3244 3245 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 3246 sPAPRDIMMState *dimm_state) 3247 { 3248 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3249 g_free(dimm_state); 3250 } 3251 3252 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 3253 PCDIMMDevice *dimm) 3254 { 3255 sPAPRDRConnector *drc; 3256 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3257 &error_abort); 3258 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3259 uint32_t avail_lmbs = 0; 3260 uint64_t addr_start, addr; 3261 int i; 3262 3263 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3264 &error_abort); 3265 3266 addr = addr_start; 3267 for (i = 0; i < nr_lmbs; i++) { 3268 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3269 addr / SPAPR_MEMORY_BLOCK_SIZE); 3270 g_assert(drc); 3271 if (drc->dev) { 3272 avail_lmbs++; 3273 } 3274 addr += SPAPR_MEMORY_BLOCK_SIZE; 3275 } 3276 3277 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3278 } 3279 3280 /* Callback to be called during DRC release. */ 3281 void spapr_lmb_release(DeviceState *dev) 3282 { 3283 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3284 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3285 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3286 3287 /* This information will get lost if a migration occurs 3288 * during the unplug process. In this case recover it. */ 3289 if (ds == NULL) { 3290 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3291 g_assert(ds); 3292 /* The DRC being examined by the caller at least must be counted */ 3293 g_assert(ds->nr_lmbs); 3294 } 3295 3296 if (--ds->nr_lmbs) { 3297 return; 3298 } 3299 3300 /* 3301 * Now that all the LMBs have been removed by the guest, call the 3302 * unplug handler chain. This can never fail. 3303 */ 3304 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3305 } 3306 3307 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3308 { 3309 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3310 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3311 3312 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3313 object_unparent(OBJECT(dev)); 3314 spapr_pending_dimm_unplugs_remove(spapr, ds); 3315 } 3316 3317 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3318 DeviceState *dev, Error **errp) 3319 { 3320 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3321 Error *local_err = NULL; 3322 PCDIMMDevice *dimm = PC_DIMM(dev); 3323 uint32_t nr_lmbs; 3324 uint64_t size, addr_start, addr; 3325 int i; 3326 sPAPRDRConnector *drc; 3327 3328 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3329 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3330 3331 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3332 &local_err); 3333 if (local_err) { 3334 goto out; 3335 } 3336 3337 /* 3338 * An existing pending dimm state for this DIMM means that there is an 3339 * unplug operation in progress, waiting for the spapr_lmb_release 3340 * callback to complete the job (BQL can't cover that far). In this case, 3341 * bail out to avoid detaching DRCs that were already released. 3342 */ 3343 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3344 error_setg(&local_err, 3345 "Memory unplug already in progress for device %s", 3346 dev->id); 3347 goto out; 3348 } 3349 3350 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3351 3352 addr = addr_start; 3353 for (i = 0; i < nr_lmbs; i++) { 3354 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3355 addr / SPAPR_MEMORY_BLOCK_SIZE); 3356 g_assert(drc); 3357 3358 spapr_drc_detach(drc); 3359 addr += SPAPR_MEMORY_BLOCK_SIZE; 3360 } 3361 3362 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3363 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3364 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3365 nr_lmbs, spapr_drc_index(drc)); 3366 out: 3367 error_propagate(errp, local_err); 3368 } 3369 3370 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 3371 sPAPRMachineState *spapr) 3372 { 3373 PowerPCCPU *cpu = POWERPC_CPU(cs); 3374 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3375 int id = spapr_get_vcpu_id(cpu); 3376 void *fdt; 3377 int offset, fdt_size; 3378 char *nodename; 3379 3380 fdt = create_device_tree(&fdt_size); 3381 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3382 offset = fdt_add_subnode(fdt, 0, nodename); 3383 3384 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3385 g_free(nodename); 3386 3387 *fdt_offset = offset; 3388 return fdt; 3389 } 3390 3391 /* Callback to be called during DRC release. */ 3392 void spapr_core_release(DeviceState *dev) 3393 { 3394 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3395 3396 /* Call the unplug handler chain. This can never fail. */ 3397 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3398 } 3399 3400 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3401 { 3402 MachineState *ms = MACHINE(hotplug_dev); 3403 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3404 CPUCore *cc = CPU_CORE(dev); 3405 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3406 3407 if (smc->pre_2_10_has_unused_icps) { 3408 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3409 int i; 3410 3411 for (i = 0; i < cc->nr_threads; i++) { 3412 CPUState *cs = CPU(sc->threads[i]); 3413 3414 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3415 } 3416 } 3417 3418 assert(core_slot); 3419 core_slot->cpu = NULL; 3420 object_unparent(OBJECT(dev)); 3421 } 3422 3423 static 3424 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3425 Error **errp) 3426 { 3427 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3428 int index; 3429 sPAPRDRConnector *drc; 3430 CPUCore *cc = CPU_CORE(dev); 3431 3432 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3433 error_setg(errp, "Unable to find CPU core with core-id: %d", 3434 cc->core_id); 3435 return; 3436 } 3437 if (index == 0) { 3438 error_setg(errp, "Boot CPU core may not be unplugged"); 3439 return; 3440 } 3441 3442 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3443 spapr_vcpu_id(spapr, cc->core_id)); 3444 g_assert(drc); 3445 3446 spapr_drc_detach(drc); 3447 3448 spapr_hotplug_req_remove_by_index(drc); 3449 } 3450 3451 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3452 Error **errp) 3453 { 3454 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3455 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3456 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3457 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3458 CPUCore *cc = CPU_CORE(dev); 3459 CPUState *cs = CPU(core->threads[0]); 3460 sPAPRDRConnector *drc; 3461 Error *local_err = NULL; 3462 CPUArchId *core_slot; 3463 int index; 3464 bool hotplugged = spapr_drc_hotplugged(dev); 3465 3466 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3467 if (!core_slot) { 3468 error_setg(errp, "Unable to find CPU core with core-id: %d", 3469 cc->core_id); 3470 return; 3471 } 3472 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3473 spapr_vcpu_id(spapr, cc->core_id)); 3474 3475 g_assert(drc || !mc->has_hotpluggable_cpus); 3476 3477 if (drc) { 3478 void *fdt; 3479 int fdt_offset; 3480 3481 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 3482 3483 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3484 if (local_err) { 3485 g_free(fdt); 3486 error_propagate(errp, local_err); 3487 return; 3488 } 3489 3490 if (hotplugged) { 3491 /* 3492 * Send hotplug notification interrupt to the guest only 3493 * in case of hotplugged CPUs. 3494 */ 3495 spapr_hotplug_req_add_by_index(drc); 3496 } else { 3497 spapr_drc_reset(drc); 3498 } 3499 } 3500 3501 core_slot->cpu = OBJECT(dev); 3502 3503 if (smc->pre_2_10_has_unused_icps) { 3504 int i; 3505 3506 for (i = 0; i < cc->nr_threads; i++) { 3507 cs = CPU(core->threads[i]); 3508 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3509 } 3510 } 3511 } 3512 3513 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3514 Error **errp) 3515 { 3516 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3517 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3518 Error *local_err = NULL; 3519 CPUCore *cc = CPU_CORE(dev); 3520 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3521 const char *type = object_get_typename(OBJECT(dev)); 3522 CPUArchId *core_slot; 3523 int index; 3524 3525 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3526 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3527 goto out; 3528 } 3529 3530 if (strcmp(base_core_type, type)) { 3531 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3532 goto out; 3533 } 3534 3535 if (cc->core_id % smp_threads) { 3536 error_setg(&local_err, "invalid core id %d", cc->core_id); 3537 goto out; 3538 } 3539 3540 /* 3541 * In general we should have homogeneous threads-per-core, but old 3542 * (pre hotplug support) machine types allow the last core to have 3543 * reduced threads as a compatibility hack for when we allowed 3544 * total vcpus not a multiple of threads-per-core. 3545 */ 3546 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3547 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3548 cc->nr_threads, smp_threads); 3549 goto out; 3550 } 3551 3552 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3553 if (!core_slot) { 3554 error_setg(&local_err, "core id %d out of range", cc->core_id); 3555 goto out; 3556 } 3557 3558 if (core_slot->cpu) { 3559 error_setg(&local_err, "core %d already populated", cc->core_id); 3560 goto out; 3561 } 3562 3563 numa_cpu_pre_plug(core_slot, dev, &local_err); 3564 3565 out: 3566 error_propagate(errp, local_err); 3567 } 3568 3569 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3570 DeviceState *dev, Error **errp) 3571 { 3572 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3573 spapr_memory_plug(hotplug_dev, dev, errp); 3574 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3575 spapr_core_plug(hotplug_dev, dev, errp); 3576 } 3577 } 3578 3579 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 3580 DeviceState *dev, Error **errp) 3581 { 3582 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3583 spapr_memory_unplug(hotplug_dev, dev); 3584 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3585 spapr_core_unplug(hotplug_dev, dev); 3586 } 3587 } 3588 3589 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3590 DeviceState *dev, Error **errp) 3591 { 3592 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3593 MachineClass *mc = MACHINE_GET_CLASS(sms); 3594 3595 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3596 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3597 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3598 } else { 3599 /* NOTE: this means there is a window after guest reset, prior to 3600 * CAS negotiation, where unplug requests will fail due to the 3601 * capability not being detected yet. This is a bit different than 3602 * the case with PCI unplug, where the events will be queued and 3603 * eventually handled by the guest after boot 3604 */ 3605 error_setg(errp, "Memory hot unplug not supported for this guest"); 3606 } 3607 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3608 if (!mc->has_hotpluggable_cpus) { 3609 error_setg(errp, "CPU hot unplug not supported on this machine"); 3610 return; 3611 } 3612 spapr_core_unplug_request(hotplug_dev, dev, errp); 3613 } 3614 } 3615 3616 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3617 DeviceState *dev, Error **errp) 3618 { 3619 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3620 spapr_memory_pre_plug(hotplug_dev, dev, errp); 3621 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3622 spapr_core_pre_plug(hotplug_dev, dev, errp); 3623 } 3624 } 3625 3626 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3627 DeviceState *dev) 3628 { 3629 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3630 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3631 return HOTPLUG_HANDLER(machine); 3632 } 3633 return NULL; 3634 } 3635 3636 static CpuInstanceProperties 3637 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3638 { 3639 CPUArchId *core_slot; 3640 MachineClass *mc = MACHINE_GET_CLASS(machine); 3641 3642 /* make sure possible_cpu are intialized */ 3643 mc->possible_cpu_arch_ids(machine); 3644 /* get CPU core slot containing thread that matches cpu_index */ 3645 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3646 assert(core_slot); 3647 return core_slot->props; 3648 } 3649 3650 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 3651 { 3652 return idx / smp_cores % nb_numa_nodes; 3653 } 3654 3655 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3656 { 3657 int i; 3658 const char *core_type; 3659 int spapr_max_cores = max_cpus / smp_threads; 3660 MachineClass *mc = MACHINE_GET_CLASS(machine); 3661 3662 if (!mc->has_hotpluggable_cpus) { 3663 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3664 } 3665 if (machine->possible_cpus) { 3666 assert(machine->possible_cpus->len == spapr_max_cores); 3667 return machine->possible_cpus; 3668 } 3669 3670 core_type = spapr_get_cpu_core_type(machine->cpu_type); 3671 if (!core_type) { 3672 error_report("Unable to find sPAPR CPU Core definition"); 3673 exit(1); 3674 } 3675 3676 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3677 sizeof(CPUArchId) * spapr_max_cores); 3678 machine->possible_cpus->len = spapr_max_cores; 3679 for (i = 0; i < machine->possible_cpus->len; i++) { 3680 int core_id = i * smp_threads; 3681 3682 machine->possible_cpus->cpus[i].type = core_type; 3683 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3684 machine->possible_cpus->cpus[i].arch_id = core_id; 3685 machine->possible_cpus->cpus[i].props.has_core_id = true; 3686 machine->possible_cpus->cpus[i].props.core_id = core_id; 3687 } 3688 return machine->possible_cpus; 3689 } 3690 3691 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3692 uint64_t *buid, hwaddr *pio, 3693 hwaddr *mmio32, hwaddr *mmio64, 3694 unsigned n_dma, uint32_t *liobns, Error **errp) 3695 { 3696 /* 3697 * New-style PHB window placement. 3698 * 3699 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3700 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3701 * windows. 3702 * 3703 * Some guest kernels can't work with MMIO windows above 1<<46 3704 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3705 * 3706 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3707 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3708 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3709 * 1TiB 64-bit MMIO windows for each PHB. 3710 */ 3711 const uint64_t base_buid = 0x800000020000000ULL; 3712 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3713 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3714 int i; 3715 3716 /* Sanity check natural alignments */ 3717 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3718 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3719 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3720 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3721 /* Sanity check bounds */ 3722 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3723 SPAPR_PCI_MEM32_WIN_SIZE); 3724 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3725 SPAPR_PCI_MEM64_WIN_SIZE); 3726 3727 if (index >= SPAPR_MAX_PHBS) { 3728 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3729 SPAPR_MAX_PHBS - 1); 3730 return; 3731 } 3732 3733 *buid = base_buid + index; 3734 for (i = 0; i < n_dma; ++i) { 3735 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3736 } 3737 3738 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3739 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3740 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3741 } 3742 3743 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3744 { 3745 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3746 3747 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3748 } 3749 3750 static void spapr_ics_resend(XICSFabric *dev) 3751 { 3752 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3753 3754 ics_resend(spapr->ics); 3755 } 3756 3757 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 3758 { 3759 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 3760 3761 return cpu ? ICP(cpu->intc) : NULL; 3762 } 3763 3764 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3765 Monitor *mon) 3766 { 3767 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3768 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3769 3770 smc->irq->print_info(spapr, mon); 3771 } 3772 3773 int spapr_get_vcpu_id(PowerPCCPU *cpu) 3774 { 3775 return cpu->vcpu_id; 3776 } 3777 3778 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 3779 { 3780 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3781 int vcpu_id; 3782 3783 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 3784 3785 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 3786 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 3787 error_append_hint(errp, "Adjust the number of cpus to %d " 3788 "or try to raise the number of threads per core\n", 3789 vcpu_id * smp_threads / spapr->vsmt); 3790 return; 3791 } 3792 3793 cpu->vcpu_id = vcpu_id; 3794 } 3795 3796 PowerPCCPU *spapr_find_cpu(int vcpu_id) 3797 { 3798 CPUState *cs; 3799 3800 CPU_FOREACH(cs) { 3801 PowerPCCPU *cpu = POWERPC_CPU(cs); 3802 3803 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 3804 return cpu; 3805 } 3806 } 3807 3808 return NULL; 3809 } 3810 3811 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3812 { 3813 MachineClass *mc = MACHINE_CLASS(oc); 3814 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3815 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3816 NMIClass *nc = NMI_CLASS(oc); 3817 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3818 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3819 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3820 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3821 3822 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3823 mc->ignore_boot_device_suffixes = true; 3824 3825 /* 3826 * We set up the default / latest behaviour here. The class_init 3827 * functions for the specific versioned machine types can override 3828 * these details for backwards compatibility 3829 */ 3830 mc->init = spapr_machine_init; 3831 mc->reset = spapr_machine_reset; 3832 mc->block_default_type = IF_SCSI; 3833 mc->max_cpus = 1024; 3834 mc->no_parallel = 1; 3835 mc->default_boot_order = ""; 3836 mc->default_ram_size = 512 * MiB; 3837 mc->default_display = "std"; 3838 mc->kvm_type = spapr_kvm_type; 3839 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 3840 mc->pci_allow_0_address = true; 3841 assert(!mc->get_hotplug_handler); 3842 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3843 hc->pre_plug = spapr_machine_device_pre_plug; 3844 hc->plug = spapr_machine_device_plug; 3845 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 3846 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 3847 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3848 hc->unplug_request = spapr_machine_device_unplug_request; 3849 hc->unplug = spapr_machine_device_unplug; 3850 3851 smc->dr_lmb_enabled = true; 3852 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 3853 mc->has_hotpluggable_cpus = true; 3854 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 3855 fwc->get_dev_path = spapr_get_fw_dev_path; 3856 nc->nmi_monitor_handler = spapr_nmi; 3857 smc->phb_placement = spapr_phb_placement; 3858 vhc->hypercall = emulate_spapr_hypercall; 3859 vhc->hpt_mask = spapr_hpt_mask; 3860 vhc->map_hptes = spapr_map_hptes; 3861 vhc->unmap_hptes = spapr_unmap_hptes; 3862 vhc->store_hpte = spapr_store_hpte; 3863 vhc->get_patbe = spapr_get_patbe; 3864 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 3865 xic->ics_get = spapr_ics_get; 3866 xic->ics_resend = spapr_ics_resend; 3867 xic->icp_get = spapr_icp_get; 3868 ispc->print_info = spapr_pic_print_info; 3869 /* Force NUMA node memory size to be a multiple of 3870 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 3871 * in which LMBs are represented and hot-added 3872 */ 3873 mc->numa_mem_align_shift = 28; 3874 3875 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 3876 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 3877 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 3878 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 3879 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 3880 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 3881 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 3882 spapr_caps_add_properties(smc, &error_abort); 3883 smc->irq = &spapr_irq_xics; 3884 } 3885 3886 static const TypeInfo spapr_machine_info = { 3887 .name = TYPE_SPAPR_MACHINE, 3888 .parent = TYPE_MACHINE, 3889 .abstract = true, 3890 .instance_size = sizeof(sPAPRMachineState), 3891 .instance_init = spapr_instance_init, 3892 .instance_finalize = spapr_machine_finalizefn, 3893 .class_size = sizeof(sPAPRMachineClass), 3894 .class_init = spapr_machine_class_init, 3895 .interfaces = (InterfaceInfo[]) { 3896 { TYPE_FW_PATH_PROVIDER }, 3897 { TYPE_NMI }, 3898 { TYPE_HOTPLUG_HANDLER }, 3899 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3900 { TYPE_XICS_FABRIC }, 3901 { TYPE_INTERRUPT_STATS_PROVIDER }, 3902 { } 3903 }, 3904 }; 3905 3906 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3907 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3908 void *data) \ 3909 { \ 3910 MachineClass *mc = MACHINE_CLASS(oc); \ 3911 spapr_machine_##suffix##_class_options(mc); \ 3912 if (latest) { \ 3913 mc->alias = "pseries"; \ 3914 mc->is_default = 1; \ 3915 } \ 3916 } \ 3917 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3918 { \ 3919 MachineState *machine = MACHINE(obj); \ 3920 spapr_machine_##suffix##_instance_options(machine); \ 3921 } \ 3922 static const TypeInfo spapr_machine_##suffix##_info = { \ 3923 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3924 .parent = TYPE_SPAPR_MACHINE, \ 3925 .class_init = spapr_machine_##suffix##_class_init, \ 3926 .instance_init = spapr_machine_##suffix##_instance_init, \ 3927 }; \ 3928 static void spapr_machine_register_##suffix(void) \ 3929 { \ 3930 type_register(&spapr_machine_##suffix##_info); \ 3931 } \ 3932 type_init(spapr_machine_register_##suffix) 3933 3934 /* 3935 * pseries-3.1 3936 */ 3937 static void spapr_machine_3_1_instance_options(MachineState *machine) 3938 { 3939 } 3940 3941 static void spapr_machine_3_1_class_options(MachineClass *mc) 3942 { 3943 /* Defaults for the latest behaviour inherited from the base class */ 3944 } 3945 3946 DEFINE_SPAPR_MACHINE(3_1, "3.1", true); 3947 3948 /* 3949 * pseries-3.0 3950 */ 3951 #define SPAPR_COMPAT_3_0 \ 3952 HW_COMPAT_3_0 3953 3954 static void spapr_machine_3_0_instance_options(MachineState *machine) 3955 { 3956 spapr_machine_3_1_instance_options(machine); 3957 } 3958 3959 static void spapr_machine_3_0_class_options(MachineClass *mc) 3960 { 3961 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3962 3963 spapr_machine_3_1_class_options(mc); 3964 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_3_0); 3965 3966 smc->legacy_irq_allocation = true; 3967 smc->irq = &spapr_irq_xics_legacy; 3968 } 3969 3970 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 3971 3972 /* 3973 * pseries-2.12 3974 */ 3975 #define SPAPR_COMPAT_2_12 \ 3976 HW_COMPAT_2_12 \ 3977 { \ 3978 .driver = TYPE_POWERPC_CPU, \ 3979 .property = "pre-3.0-migration", \ 3980 .value = "on", \ 3981 }, \ 3982 { \ 3983 .driver = TYPE_SPAPR_CPU_CORE, \ 3984 .property = "pre-3.0-migration", \ 3985 .value = "on", \ 3986 }, 3987 3988 static void spapr_machine_2_12_instance_options(MachineState *machine) 3989 { 3990 spapr_machine_3_0_instance_options(machine); 3991 } 3992 3993 static void spapr_machine_2_12_class_options(MachineClass *mc) 3994 { 3995 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3996 3997 spapr_machine_3_0_class_options(mc); 3998 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_12); 3999 4000 /* We depend on kvm_enabled() to choose a default value for the 4001 * hpt-max-page-size capability. Of course we can't do it here 4002 * because this is too early and the HW accelerator isn't initialzed 4003 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4004 */ 4005 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4006 } 4007 4008 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4009 4010 static void spapr_machine_2_12_sxxm_instance_options(MachineState *machine) 4011 { 4012 spapr_machine_2_12_instance_options(machine); 4013 } 4014 4015 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4016 { 4017 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4018 4019 spapr_machine_2_12_class_options(mc); 4020 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4021 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4022 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4023 } 4024 4025 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4026 4027 /* 4028 * pseries-2.11 4029 */ 4030 #define SPAPR_COMPAT_2_11 \ 4031 HW_COMPAT_2_11 4032 4033 static void spapr_machine_2_11_instance_options(MachineState *machine) 4034 { 4035 spapr_machine_2_12_instance_options(machine); 4036 } 4037 4038 static void spapr_machine_2_11_class_options(MachineClass *mc) 4039 { 4040 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4041 4042 spapr_machine_2_12_class_options(mc); 4043 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4044 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11); 4045 } 4046 4047 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4048 4049 /* 4050 * pseries-2.10 4051 */ 4052 #define SPAPR_COMPAT_2_10 \ 4053 HW_COMPAT_2_10 4054 4055 static void spapr_machine_2_10_instance_options(MachineState *machine) 4056 { 4057 spapr_machine_2_11_instance_options(machine); 4058 } 4059 4060 static void spapr_machine_2_10_class_options(MachineClass *mc) 4061 { 4062 spapr_machine_2_11_class_options(mc); 4063 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10); 4064 } 4065 4066 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4067 4068 /* 4069 * pseries-2.9 4070 */ 4071 #define SPAPR_COMPAT_2_9 \ 4072 HW_COMPAT_2_9 \ 4073 { \ 4074 .driver = TYPE_POWERPC_CPU, \ 4075 .property = "pre-2.10-migration", \ 4076 .value = "on", \ 4077 }, \ 4078 4079 static void spapr_machine_2_9_instance_options(MachineState *machine) 4080 { 4081 spapr_machine_2_10_instance_options(machine); 4082 } 4083 4084 static void spapr_machine_2_9_class_options(MachineClass *mc) 4085 { 4086 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4087 4088 spapr_machine_2_10_class_options(mc); 4089 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); 4090 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4091 smc->pre_2_10_has_unused_icps = true; 4092 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4093 } 4094 4095 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4096 4097 /* 4098 * pseries-2.8 4099 */ 4100 #define SPAPR_COMPAT_2_8 \ 4101 HW_COMPAT_2_8 \ 4102 { \ 4103 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4104 .property = "pcie-extended-configuration-space", \ 4105 .value = "off", \ 4106 }, 4107 4108 static void spapr_machine_2_8_instance_options(MachineState *machine) 4109 { 4110 spapr_machine_2_9_instance_options(machine); 4111 } 4112 4113 static void spapr_machine_2_8_class_options(MachineClass *mc) 4114 { 4115 spapr_machine_2_9_class_options(mc); 4116 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 4117 mc->numa_mem_align_shift = 23; 4118 } 4119 4120 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4121 4122 /* 4123 * pseries-2.7 4124 */ 4125 #define SPAPR_COMPAT_2_7 \ 4126 HW_COMPAT_2_7 \ 4127 { \ 4128 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4129 .property = "mem_win_size", \ 4130 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 4131 }, \ 4132 { \ 4133 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4134 .property = "mem64_win_size", \ 4135 .value = "0", \ 4136 }, \ 4137 { \ 4138 .driver = TYPE_POWERPC_CPU, \ 4139 .property = "pre-2.8-migration", \ 4140 .value = "on", \ 4141 }, \ 4142 { \ 4143 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4144 .property = "pre-2.8-migration", \ 4145 .value = "on", \ 4146 }, 4147 4148 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 4149 uint64_t *buid, hwaddr *pio, 4150 hwaddr *mmio32, hwaddr *mmio64, 4151 unsigned n_dma, uint32_t *liobns, Error **errp) 4152 { 4153 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4154 const uint64_t base_buid = 0x800000020000000ULL; 4155 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4156 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4157 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4158 const uint32_t max_index = 255; 4159 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4160 4161 uint64_t ram_top = MACHINE(spapr)->ram_size; 4162 hwaddr phb0_base, phb_base; 4163 int i; 4164 4165 /* Do we have device memory? */ 4166 if (MACHINE(spapr)->maxram_size > ram_top) { 4167 /* Can't just use maxram_size, because there may be an 4168 * alignment gap between normal and device memory regions 4169 */ 4170 ram_top = MACHINE(spapr)->device_memory->base + 4171 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4172 } 4173 4174 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4175 4176 if (index > max_index) { 4177 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4178 max_index); 4179 return; 4180 } 4181 4182 *buid = base_buid + index; 4183 for (i = 0; i < n_dma; ++i) { 4184 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4185 } 4186 4187 phb_base = phb0_base + index * phb_spacing; 4188 *pio = phb_base + pio_offset; 4189 *mmio32 = phb_base + mmio_offset; 4190 /* 4191 * We don't set the 64-bit MMIO window, relying on the PHB's 4192 * fallback behaviour of automatically splitting a large "32-bit" 4193 * window into contiguous 32-bit and 64-bit windows 4194 */ 4195 } 4196 4197 static void spapr_machine_2_7_instance_options(MachineState *machine) 4198 { 4199 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 4200 4201 spapr_machine_2_8_instance_options(machine); 4202 spapr->use_hotplug_event_source = false; 4203 } 4204 4205 static void spapr_machine_2_7_class_options(MachineClass *mc) 4206 { 4207 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4208 4209 spapr_machine_2_8_class_options(mc); 4210 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4211 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 4212 smc->phb_placement = phb_placement_2_7; 4213 } 4214 4215 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4216 4217 /* 4218 * pseries-2.6 4219 */ 4220 #define SPAPR_COMPAT_2_6 \ 4221 HW_COMPAT_2_6 \ 4222 { \ 4223 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 4224 .property = "ddw",\ 4225 .value = stringify(off),\ 4226 }, 4227 4228 static void spapr_machine_2_6_instance_options(MachineState *machine) 4229 { 4230 spapr_machine_2_7_instance_options(machine); 4231 } 4232 4233 static void spapr_machine_2_6_class_options(MachineClass *mc) 4234 { 4235 spapr_machine_2_7_class_options(mc); 4236 mc->has_hotpluggable_cpus = false; 4237 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 4238 } 4239 4240 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4241 4242 /* 4243 * pseries-2.5 4244 */ 4245 #define SPAPR_COMPAT_2_5 \ 4246 HW_COMPAT_2_5 \ 4247 { \ 4248 .driver = "spapr-vlan", \ 4249 .property = "use-rx-buffer-pools", \ 4250 .value = "off", \ 4251 }, 4252 4253 static void spapr_machine_2_5_instance_options(MachineState *machine) 4254 { 4255 spapr_machine_2_6_instance_options(machine); 4256 } 4257 4258 static void spapr_machine_2_5_class_options(MachineClass *mc) 4259 { 4260 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4261 4262 spapr_machine_2_6_class_options(mc); 4263 smc->use_ohci_by_default = true; 4264 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 4265 } 4266 4267 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4268 4269 /* 4270 * pseries-2.4 4271 */ 4272 #define SPAPR_COMPAT_2_4 \ 4273 HW_COMPAT_2_4 4274 4275 static void spapr_machine_2_4_instance_options(MachineState *machine) 4276 { 4277 spapr_machine_2_5_instance_options(machine); 4278 } 4279 4280 static void spapr_machine_2_4_class_options(MachineClass *mc) 4281 { 4282 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4283 4284 spapr_machine_2_5_class_options(mc); 4285 smc->dr_lmb_enabled = false; 4286 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 4287 } 4288 4289 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4290 4291 /* 4292 * pseries-2.3 4293 */ 4294 #define SPAPR_COMPAT_2_3 \ 4295 HW_COMPAT_2_3 \ 4296 {\ 4297 .driver = "spapr-pci-host-bridge",\ 4298 .property = "dynamic-reconfiguration",\ 4299 .value = "off",\ 4300 }, 4301 4302 static void spapr_machine_2_3_instance_options(MachineState *machine) 4303 { 4304 spapr_machine_2_4_instance_options(machine); 4305 } 4306 4307 static void spapr_machine_2_3_class_options(MachineClass *mc) 4308 { 4309 spapr_machine_2_4_class_options(mc); 4310 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 4311 } 4312 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4313 4314 /* 4315 * pseries-2.2 4316 */ 4317 4318 #define SPAPR_COMPAT_2_2 \ 4319 HW_COMPAT_2_2 \ 4320 {\ 4321 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 4322 .property = "mem_win_size",\ 4323 .value = "0x20000000",\ 4324 }, 4325 4326 static void spapr_machine_2_2_instance_options(MachineState *machine) 4327 { 4328 spapr_machine_2_3_instance_options(machine); 4329 machine->suppress_vmdesc = true; 4330 } 4331 4332 static void spapr_machine_2_2_class_options(MachineClass *mc) 4333 { 4334 spapr_machine_2_3_class_options(mc); 4335 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 4336 } 4337 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4338 4339 /* 4340 * pseries-2.1 4341 */ 4342 #define SPAPR_COMPAT_2_1 \ 4343 HW_COMPAT_2_1 4344 4345 static void spapr_machine_2_1_instance_options(MachineState *machine) 4346 { 4347 spapr_machine_2_2_instance_options(machine); 4348 } 4349 4350 static void spapr_machine_2_1_class_options(MachineClass *mc) 4351 { 4352 spapr_machine_2_2_class_options(mc); 4353 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 4354 } 4355 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4356 4357 static void spapr_machine_register_types(void) 4358 { 4359 type_register_static(&spapr_machine_info); 4360 } 4361 4362 type_init(spapr_machine_register_types) 4363