1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/numa.h" 32 #include "hw/hw.h" 33 #include "qemu/log.h" 34 #include "hw/fw-path-provider.h" 35 #include "elf.h" 36 #include "net/net.h" 37 #include "sysemu/device_tree.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/misc.h" 42 #include "migration/global_state.h" 43 #include "migration/register.h" 44 #include "mmu-hash64.h" 45 #include "mmu-book3s-v3.h" 46 #include "cpu-models.h" 47 #include "qom/cpu.h" 48 49 #include "hw/boards.h" 50 #include "hw/ppc/ppc.h" 51 #include "hw/loader.h" 52 53 #include "hw/ppc/fdt.h" 54 #include "hw/ppc/spapr.h" 55 #include "hw/ppc/spapr_vio.h" 56 #include "hw/pci-host/spapr.h" 57 #include "hw/pci/msi.h" 58 59 #include "hw/pci/pci.h" 60 #include "hw/scsi/scsi.h" 61 #include "hw/virtio/virtio-scsi.h" 62 #include "hw/virtio/vhost-scsi-common.h" 63 64 #include "exec/address-spaces.h" 65 #include "exec/ram_addr.h" 66 #include "hw/usb.h" 67 #include "qemu/config-file.h" 68 #include "qemu/error-report.h" 69 #include "trace.h" 70 #include "hw/nmi.h" 71 #include "hw/intc/intc.h" 72 73 #include "hw/compat.h" 74 #include "qemu/cutils.h" 75 #include "hw/ppc/spapr_cpu_core.h" 76 #include "hw/mem/memory-device.h" 77 78 #include <libfdt.h> 79 80 /* SLOF memory layout: 81 * 82 * SLOF raw image loaded at 0, copies its romfs right below the flat 83 * device-tree, then position SLOF itself 31M below that 84 * 85 * So we set FW_OVERHEAD to 40MB which should account for all of that 86 * and more 87 * 88 * We load our kernel at 4M, leaving space for SLOF initial image 89 */ 90 #define FDT_MAX_SIZE 0x100000 91 #define RTAS_MAX_SIZE 0x10000 92 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 93 #define FW_MAX_SIZE 0x400000 94 #define FW_FILE_NAME "slof.bin" 95 #define FW_OVERHEAD 0x2800000 96 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 97 98 #define MIN_RMA_SLOF 128UL 99 100 #define PHANDLE_XICP 0x00001111 101 102 /* These two functions implement the VCPU id numbering: one to compute them 103 * all and one to identify thread 0 of a VCORE. Any change to the first one 104 * is likely to have an impact on the second one, so let's keep them close. 105 */ 106 static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index) 107 { 108 assert(spapr->vsmt); 109 return 110 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 111 } 112 static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr, 113 PowerPCCPU *cpu) 114 { 115 assert(spapr->vsmt); 116 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 117 } 118 119 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 120 { 121 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 122 * and newer QEMUs don't even have them. In both cases, we don't want 123 * to send anything on the wire. 124 */ 125 return false; 126 } 127 128 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 129 .name = "icp/server", 130 .version_id = 1, 131 .minimum_version_id = 1, 132 .needed = pre_2_10_vmstate_dummy_icp_needed, 133 .fields = (VMStateField[]) { 134 VMSTATE_UNUSED(4), /* uint32_t xirr */ 135 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 136 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 137 VMSTATE_END_OF_LIST() 138 }, 139 }; 140 141 static void pre_2_10_vmstate_register_dummy_icp(int i) 142 { 143 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 144 (void *)(uintptr_t) i); 145 } 146 147 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 148 { 149 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 150 (void *)(uintptr_t) i); 151 } 152 153 static int xics_max_server_number(sPAPRMachineState *spapr) 154 { 155 assert(spapr->vsmt); 156 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads); 157 } 158 159 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 160 int smt_threads) 161 { 162 int i, ret = 0; 163 uint32_t servers_prop[smt_threads]; 164 uint32_t gservers_prop[smt_threads * 2]; 165 int index = spapr_get_vcpu_id(cpu); 166 167 if (cpu->compat_pvr) { 168 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 169 if (ret < 0) { 170 return ret; 171 } 172 } 173 174 /* Build interrupt servers and gservers properties */ 175 for (i = 0; i < smt_threads; i++) { 176 servers_prop[i] = cpu_to_be32(index + i); 177 /* Hack, direct the group queues back to cpu 0 */ 178 gservers_prop[i*2] = cpu_to_be32(index + i); 179 gservers_prop[i*2 + 1] = 0; 180 } 181 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 182 servers_prop, sizeof(servers_prop)); 183 if (ret < 0) { 184 return ret; 185 } 186 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 187 gservers_prop, sizeof(gservers_prop)); 188 189 return ret; 190 } 191 192 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 193 { 194 int index = spapr_get_vcpu_id(cpu); 195 uint32_t associativity[] = {cpu_to_be32(0x5), 196 cpu_to_be32(0x0), 197 cpu_to_be32(0x0), 198 cpu_to_be32(0x0), 199 cpu_to_be32(cpu->node_id), 200 cpu_to_be32(index)}; 201 202 /* Advertise NUMA via ibm,associativity */ 203 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 204 sizeof(associativity)); 205 } 206 207 /* Populate the "ibm,pa-features" property */ 208 static void spapr_populate_pa_features(sPAPRMachineState *spapr, 209 PowerPCCPU *cpu, 210 void *fdt, int offset, 211 bool legacy_guest) 212 { 213 uint8_t pa_features_206[] = { 6, 0, 214 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 215 uint8_t pa_features_207[] = { 24, 0, 216 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 217 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 218 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 219 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 220 uint8_t pa_features_300[] = { 66, 0, 221 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 222 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 223 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 224 /* 6: DS207 */ 225 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 226 /* 16: Vector */ 227 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 228 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 229 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 230 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 231 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 232 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 233 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 234 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 236 /* 42: PM, 44: PC RA, 46: SC vec'd */ 237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 238 /* 48: SIMD, 50: QP BFP, 52: String */ 239 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 240 /* 54: DecFP, 56: DecI, 58: SHA */ 241 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 242 /* 60: NM atomic, 62: RNG */ 243 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 244 }; 245 uint8_t *pa_features = NULL; 246 size_t pa_size; 247 248 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 249 pa_features = pa_features_206; 250 pa_size = sizeof(pa_features_206); 251 } 252 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 253 pa_features = pa_features_207; 254 pa_size = sizeof(pa_features_207); 255 } 256 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 257 pa_features = pa_features_300; 258 pa_size = sizeof(pa_features_300); 259 } 260 if (!pa_features) { 261 return; 262 } 263 264 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 265 /* 266 * Note: we keep CI large pages off by default because a 64K capable 267 * guest provisioned with large pages might otherwise try to map a qemu 268 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 269 * even if that qemu runs on a 4k host. 270 * We dd this bit back here if we are confident this is not an issue 271 */ 272 pa_features[3] |= 0x20; 273 } 274 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 275 pa_features[24] |= 0x80; /* Transactional memory support */ 276 } 277 if (legacy_guest && pa_size > 40) { 278 /* Workaround for broken kernels that attempt (guest) radix 279 * mode when they can't handle it, if they see the radix bit set 280 * in pa-features. So hide it from them. */ 281 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 282 } 283 284 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 285 } 286 287 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 288 { 289 int ret = 0, offset, cpus_offset; 290 CPUState *cs; 291 char cpu_model[32]; 292 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 293 294 CPU_FOREACH(cs) { 295 PowerPCCPU *cpu = POWERPC_CPU(cs); 296 DeviceClass *dc = DEVICE_GET_CLASS(cs); 297 int index = spapr_get_vcpu_id(cpu); 298 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 299 300 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 301 continue; 302 } 303 304 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 305 306 cpus_offset = fdt_path_offset(fdt, "/cpus"); 307 if (cpus_offset < 0) { 308 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 309 if (cpus_offset < 0) { 310 return cpus_offset; 311 } 312 } 313 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 314 if (offset < 0) { 315 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 316 if (offset < 0) { 317 return offset; 318 } 319 } 320 321 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 322 pft_size_prop, sizeof(pft_size_prop)); 323 if (ret < 0) { 324 return ret; 325 } 326 327 if (nb_numa_nodes > 1) { 328 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 329 if (ret < 0) { 330 return ret; 331 } 332 } 333 334 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 335 if (ret < 0) { 336 return ret; 337 } 338 339 spapr_populate_pa_features(spapr, cpu, fdt, offset, 340 spapr->cas_legacy_guest_workaround); 341 } 342 return ret; 343 } 344 345 static hwaddr spapr_node0_size(MachineState *machine) 346 { 347 if (nb_numa_nodes) { 348 int i; 349 for (i = 0; i < nb_numa_nodes; ++i) { 350 if (numa_info[i].node_mem) { 351 return MIN(pow2floor(numa_info[i].node_mem), 352 machine->ram_size); 353 } 354 } 355 } 356 return machine->ram_size; 357 } 358 359 static void add_str(GString *s, const gchar *s1) 360 { 361 g_string_append_len(s, s1, strlen(s1) + 1); 362 } 363 364 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 365 hwaddr size) 366 { 367 uint32_t associativity[] = { 368 cpu_to_be32(0x4), /* length */ 369 cpu_to_be32(0x0), cpu_to_be32(0x0), 370 cpu_to_be32(0x0), cpu_to_be32(nodeid) 371 }; 372 char mem_name[32]; 373 uint64_t mem_reg_property[2]; 374 int off; 375 376 mem_reg_property[0] = cpu_to_be64(start); 377 mem_reg_property[1] = cpu_to_be64(size); 378 379 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 380 off = fdt_add_subnode(fdt, 0, mem_name); 381 _FDT(off); 382 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 383 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 384 sizeof(mem_reg_property)))); 385 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 386 sizeof(associativity)))); 387 return off; 388 } 389 390 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 391 { 392 MachineState *machine = MACHINE(spapr); 393 hwaddr mem_start, node_size; 394 int i, nb_nodes = nb_numa_nodes; 395 NodeInfo *nodes = numa_info; 396 NodeInfo ramnode; 397 398 /* No NUMA nodes, assume there is just one node with whole RAM */ 399 if (!nb_numa_nodes) { 400 nb_nodes = 1; 401 ramnode.node_mem = machine->ram_size; 402 nodes = &ramnode; 403 } 404 405 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 406 if (!nodes[i].node_mem) { 407 continue; 408 } 409 if (mem_start >= machine->ram_size) { 410 node_size = 0; 411 } else { 412 node_size = nodes[i].node_mem; 413 if (node_size > machine->ram_size - mem_start) { 414 node_size = machine->ram_size - mem_start; 415 } 416 } 417 if (!mem_start) { 418 /* spapr_machine_init() checks for rma_size <= node0_size 419 * already */ 420 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 421 mem_start += spapr->rma_size; 422 node_size -= spapr->rma_size; 423 } 424 for ( ; node_size; ) { 425 hwaddr sizetmp = pow2floor(node_size); 426 427 /* mem_start != 0 here */ 428 if (ctzl(mem_start) < ctzl(sizetmp)) { 429 sizetmp = 1ULL << ctzl(mem_start); 430 } 431 432 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 433 node_size -= sizetmp; 434 mem_start += sizetmp; 435 } 436 } 437 438 return 0; 439 } 440 441 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 442 sPAPRMachineState *spapr) 443 { 444 PowerPCCPU *cpu = POWERPC_CPU(cs); 445 CPUPPCState *env = &cpu->env; 446 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 447 int index = spapr_get_vcpu_id(cpu); 448 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 449 0xffffffff, 0xffffffff}; 450 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 451 : SPAPR_TIMEBASE_FREQ; 452 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 453 uint32_t page_sizes_prop[64]; 454 size_t page_sizes_prop_size; 455 uint32_t vcpus_per_socket = smp_threads * smp_cores; 456 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 457 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 458 sPAPRDRConnector *drc; 459 int drc_index; 460 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 461 int i; 462 463 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 464 if (drc) { 465 drc_index = spapr_drc_index(drc); 466 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 467 } 468 469 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 470 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 471 472 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 473 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 474 env->dcache_line_size))); 475 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 476 env->dcache_line_size))); 477 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 478 env->icache_line_size))); 479 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 480 env->icache_line_size))); 481 482 if (pcc->l1_dcache_size) { 483 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 484 pcc->l1_dcache_size))); 485 } else { 486 warn_report("Unknown L1 dcache size for cpu"); 487 } 488 if (pcc->l1_icache_size) { 489 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 490 pcc->l1_icache_size))); 491 } else { 492 warn_report("Unknown L1 icache size for cpu"); 493 } 494 495 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 496 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 497 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 498 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 499 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 500 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 501 502 if (env->spr_cb[SPR_PURR].oea_read) { 503 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 504 } 505 506 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 507 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 508 segs, sizeof(segs)))); 509 } 510 511 /* Advertise VSX (vector extensions) if available 512 * 1 == VMX / Altivec available 513 * 2 == VSX available 514 * 515 * Only CPUs for which we create core types in spapr_cpu_core.c 516 * are possible, and all of those have VMX */ 517 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 518 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 519 } else { 520 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 521 } 522 523 /* Advertise DFP (Decimal Floating Point) if available 524 * 0 / no property == no DFP 525 * 1 == DFP available */ 526 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 527 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 528 } 529 530 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 531 sizeof(page_sizes_prop)); 532 if (page_sizes_prop_size) { 533 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 534 page_sizes_prop, page_sizes_prop_size))); 535 } 536 537 spapr_populate_pa_features(spapr, cpu, fdt, offset, false); 538 539 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 540 cs->cpu_index / vcpus_per_socket))); 541 542 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 543 pft_size_prop, sizeof(pft_size_prop)))); 544 545 if (nb_numa_nodes > 1) { 546 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 547 } 548 549 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 550 551 if (pcc->radix_page_info) { 552 for (i = 0; i < pcc->radix_page_info->count; i++) { 553 radix_AP_encodings[i] = 554 cpu_to_be32(pcc->radix_page_info->entries[i]); 555 } 556 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 557 radix_AP_encodings, 558 pcc->radix_page_info->count * 559 sizeof(radix_AP_encodings[0])))); 560 } 561 } 562 563 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 564 { 565 CPUState **rev; 566 CPUState *cs; 567 int n_cpus; 568 int cpus_offset; 569 char *nodename; 570 int i; 571 572 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 573 _FDT(cpus_offset); 574 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 575 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 576 577 /* 578 * We walk the CPUs in reverse order to ensure that CPU DT nodes 579 * created by fdt_add_subnode() end up in the right order in FDT 580 * for the guest kernel the enumerate the CPUs correctly. 581 * 582 * The CPU list cannot be traversed in reverse order, so we need 583 * to do extra work. 584 */ 585 n_cpus = 0; 586 rev = NULL; 587 CPU_FOREACH(cs) { 588 rev = g_renew(CPUState *, rev, n_cpus + 1); 589 rev[n_cpus++] = cs; 590 } 591 592 for (i = n_cpus - 1; i >= 0; i--) { 593 CPUState *cs = rev[i]; 594 PowerPCCPU *cpu = POWERPC_CPU(cs); 595 int index = spapr_get_vcpu_id(cpu); 596 DeviceClass *dc = DEVICE_GET_CLASS(cs); 597 int offset; 598 599 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 600 continue; 601 } 602 603 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 604 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 605 g_free(nodename); 606 _FDT(offset); 607 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 608 } 609 610 } 611 612 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 613 { 614 MemoryDeviceInfoList *info; 615 616 for (info = list; info; info = info->next) { 617 MemoryDeviceInfo *value = info->value; 618 619 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 620 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 621 622 if (addr >= pcdimm_info->addr && 623 addr < (pcdimm_info->addr + pcdimm_info->size)) { 624 return pcdimm_info->node; 625 } 626 } 627 } 628 629 return -1; 630 } 631 632 struct sPAPRDrconfCellV2 { 633 uint32_t seq_lmbs; 634 uint64_t base_addr; 635 uint32_t drc_index; 636 uint32_t aa_index; 637 uint32_t flags; 638 } QEMU_PACKED; 639 640 typedef struct DrconfCellQueue { 641 struct sPAPRDrconfCellV2 cell; 642 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 643 } DrconfCellQueue; 644 645 static DrconfCellQueue * 646 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 647 uint32_t drc_index, uint32_t aa_index, 648 uint32_t flags) 649 { 650 DrconfCellQueue *elem; 651 652 elem = g_malloc0(sizeof(*elem)); 653 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 654 elem->cell.base_addr = cpu_to_be64(base_addr); 655 elem->cell.drc_index = cpu_to_be32(drc_index); 656 elem->cell.aa_index = cpu_to_be32(aa_index); 657 elem->cell.flags = cpu_to_be32(flags); 658 659 return elem; 660 } 661 662 /* ibm,dynamic-memory-v2 */ 663 static int spapr_populate_drmem_v2(sPAPRMachineState *spapr, void *fdt, 664 int offset, MemoryDeviceInfoList *dimms) 665 { 666 MachineState *machine = MACHINE(spapr); 667 uint8_t *int_buf, *cur_index, buf_len; 668 int ret; 669 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 670 uint64_t addr, cur_addr, size; 671 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 672 uint64_t mem_end = machine->device_memory->base + 673 memory_region_size(&machine->device_memory->mr); 674 uint32_t node, nr_entries = 0; 675 sPAPRDRConnector *drc; 676 DrconfCellQueue *elem, *next; 677 MemoryDeviceInfoList *info; 678 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 679 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 680 681 /* Entry to cover RAM and the gap area */ 682 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 683 SPAPR_LMB_FLAGS_RESERVED | 684 SPAPR_LMB_FLAGS_DRC_INVALID); 685 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 686 nr_entries++; 687 688 cur_addr = machine->device_memory->base; 689 for (info = dimms; info; info = info->next) { 690 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 691 692 addr = di->addr; 693 size = di->size; 694 node = di->node; 695 696 /* Entry for hot-pluggable area */ 697 if (cur_addr < addr) { 698 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 699 g_assert(drc); 700 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 701 cur_addr, spapr_drc_index(drc), -1, 0); 702 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 703 nr_entries++; 704 } 705 706 /* Entry for DIMM */ 707 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 708 g_assert(drc); 709 elem = spapr_get_drconf_cell(size / lmb_size, addr, 710 spapr_drc_index(drc), node, 711 SPAPR_LMB_FLAGS_ASSIGNED); 712 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 713 nr_entries++; 714 cur_addr = addr + size; 715 } 716 717 /* Entry for remaining hotpluggable area */ 718 if (cur_addr < mem_end) { 719 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 720 g_assert(drc); 721 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 722 cur_addr, spapr_drc_index(drc), -1, 0); 723 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 724 nr_entries++; 725 } 726 727 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 728 int_buf = cur_index = g_malloc0(buf_len); 729 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 730 cur_index += sizeof(nr_entries); 731 732 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 733 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 734 cur_index += sizeof(elem->cell); 735 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 736 g_free(elem); 737 } 738 739 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 740 g_free(int_buf); 741 if (ret < 0) { 742 return -1; 743 } 744 return 0; 745 } 746 747 /* ibm,dynamic-memory */ 748 static int spapr_populate_drmem_v1(sPAPRMachineState *spapr, void *fdt, 749 int offset, MemoryDeviceInfoList *dimms) 750 { 751 MachineState *machine = MACHINE(spapr); 752 int i, ret; 753 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 754 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 755 uint32_t nr_lmbs = (machine->device_memory->base + 756 memory_region_size(&machine->device_memory->mr)) / 757 lmb_size; 758 uint32_t *int_buf, *cur_index, buf_len; 759 760 /* 761 * Allocate enough buffer size to fit in ibm,dynamic-memory 762 */ 763 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 764 cur_index = int_buf = g_malloc0(buf_len); 765 int_buf[0] = cpu_to_be32(nr_lmbs); 766 cur_index++; 767 for (i = 0; i < nr_lmbs; i++) { 768 uint64_t addr = i * lmb_size; 769 uint32_t *dynamic_memory = cur_index; 770 771 if (i >= device_lmb_start) { 772 sPAPRDRConnector *drc; 773 774 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 775 g_assert(drc); 776 777 dynamic_memory[0] = cpu_to_be32(addr >> 32); 778 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 779 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 780 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 781 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 782 if (memory_region_present(get_system_memory(), addr)) { 783 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 784 } else { 785 dynamic_memory[5] = cpu_to_be32(0); 786 } 787 } else { 788 /* 789 * LMB information for RMA, boot time RAM and gap b/n RAM and 790 * device memory region -- all these are marked as reserved 791 * and as having no valid DRC. 792 */ 793 dynamic_memory[0] = cpu_to_be32(addr >> 32); 794 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 795 dynamic_memory[2] = cpu_to_be32(0); 796 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 797 dynamic_memory[4] = cpu_to_be32(-1); 798 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 799 SPAPR_LMB_FLAGS_DRC_INVALID); 800 } 801 802 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 803 } 804 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 805 g_free(int_buf); 806 if (ret < 0) { 807 return -1; 808 } 809 return 0; 810 } 811 812 /* 813 * Adds ibm,dynamic-reconfiguration-memory node. 814 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 815 * of this device tree node. 816 */ 817 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 818 { 819 MachineState *machine = MACHINE(spapr); 820 int ret, i, offset; 821 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 822 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 823 uint32_t *int_buf, *cur_index, buf_len; 824 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 825 MemoryDeviceInfoList *dimms = NULL; 826 827 /* 828 * Don't create the node if there is no device memory 829 */ 830 if (machine->ram_size == machine->maxram_size) { 831 return 0; 832 } 833 834 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 835 836 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 837 sizeof(prop_lmb_size)); 838 if (ret < 0) { 839 return ret; 840 } 841 842 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 843 if (ret < 0) { 844 return ret; 845 } 846 847 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 848 if (ret < 0) { 849 return ret; 850 } 851 852 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 853 dimms = qmp_memory_device_list(); 854 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 855 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 856 } else { 857 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 858 } 859 qapi_free_MemoryDeviceInfoList(dimms); 860 861 if (ret < 0) { 862 return ret; 863 } 864 865 /* ibm,associativity-lookup-arrays */ 866 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 867 cur_index = int_buf = g_malloc0(buf_len); 868 869 cur_index = int_buf; 870 int_buf[0] = cpu_to_be32(nr_nodes); 871 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 872 cur_index += 2; 873 for (i = 0; i < nr_nodes; i++) { 874 uint32_t associativity[] = { 875 cpu_to_be32(0x0), 876 cpu_to_be32(0x0), 877 cpu_to_be32(0x0), 878 cpu_to_be32(i) 879 }; 880 memcpy(cur_index, associativity, sizeof(associativity)); 881 cur_index += 4; 882 } 883 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 884 (cur_index - int_buf) * sizeof(uint32_t)); 885 g_free(int_buf); 886 887 return ret; 888 } 889 890 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 891 sPAPROptionVector *ov5_updates) 892 { 893 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 894 int ret = 0, offset; 895 896 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 897 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 898 g_assert(smc->dr_lmb_enabled); 899 ret = spapr_populate_drconf_memory(spapr, fdt); 900 if (ret) { 901 goto out; 902 } 903 } 904 905 offset = fdt_path_offset(fdt, "/chosen"); 906 if (offset < 0) { 907 offset = fdt_add_subnode(fdt, 0, "chosen"); 908 if (offset < 0) { 909 return offset; 910 } 911 } 912 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 913 "ibm,architecture-vec-5"); 914 915 out: 916 return ret; 917 } 918 919 static bool spapr_hotplugged_dev_before_cas(void) 920 { 921 Object *drc_container, *obj; 922 ObjectProperty *prop; 923 ObjectPropertyIterator iter; 924 925 drc_container = container_get(object_get_root(), "/dr-connector"); 926 object_property_iter_init(&iter, drc_container); 927 while ((prop = object_property_iter_next(&iter))) { 928 if (!strstart(prop->type, "link<", NULL)) { 929 continue; 930 } 931 obj = object_property_get_link(drc_container, prop->name, NULL); 932 if (spapr_drc_needed(obj)) { 933 return true; 934 } 935 } 936 return false; 937 } 938 939 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 940 target_ulong addr, target_ulong size, 941 sPAPROptionVector *ov5_updates) 942 { 943 void *fdt, *fdt_skel; 944 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 945 946 if (spapr_hotplugged_dev_before_cas()) { 947 return 1; 948 } 949 950 if (size < sizeof(hdr) || size > FW_MAX_SIZE) { 951 error_report("SLOF provided an unexpected CAS buffer size " 952 TARGET_FMT_lu " (min: %zu, max: %u)", 953 size, sizeof(hdr), FW_MAX_SIZE); 954 exit(EXIT_FAILURE); 955 } 956 957 size -= sizeof(hdr); 958 959 /* Create skeleton */ 960 fdt_skel = g_malloc0(size); 961 _FDT((fdt_create(fdt_skel, size))); 962 _FDT((fdt_finish_reservemap(fdt_skel))); 963 _FDT((fdt_begin_node(fdt_skel, ""))); 964 _FDT((fdt_end_node(fdt_skel))); 965 _FDT((fdt_finish(fdt_skel))); 966 fdt = g_malloc0(size); 967 _FDT((fdt_open_into(fdt_skel, fdt, size))); 968 g_free(fdt_skel); 969 970 /* Fixup cpu nodes */ 971 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 972 973 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 974 return -1; 975 } 976 977 /* Pack resulting tree */ 978 _FDT((fdt_pack(fdt))); 979 980 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 981 trace_spapr_cas_failed(size); 982 return -1; 983 } 984 985 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 986 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 987 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 988 g_free(fdt); 989 990 return 0; 991 } 992 993 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 994 { 995 int rtas; 996 GString *hypertas = g_string_sized_new(256); 997 GString *qemu_hypertas = g_string_sized_new(256); 998 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 999 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 1000 memory_region_size(&MACHINE(spapr)->device_memory->mr); 1001 uint32_t lrdr_capacity[] = { 1002 cpu_to_be32(max_device_addr >> 32), 1003 cpu_to_be32(max_device_addr & 0xffffffff), 1004 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 1005 cpu_to_be32(max_cpus / smp_threads), 1006 }; 1007 uint32_t maxdomains[] = { 1008 cpu_to_be32(4), 1009 cpu_to_be32(0), 1010 cpu_to_be32(0), 1011 cpu_to_be32(0), 1012 cpu_to_be32(nb_numa_nodes ? nb_numa_nodes - 1 : 0), 1013 }; 1014 1015 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 1016 1017 /* hypertas */ 1018 add_str(hypertas, "hcall-pft"); 1019 add_str(hypertas, "hcall-term"); 1020 add_str(hypertas, "hcall-dabr"); 1021 add_str(hypertas, "hcall-interrupt"); 1022 add_str(hypertas, "hcall-tce"); 1023 add_str(hypertas, "hcall-vio"); 1024 add_str(hypertas, "hcall-splpar"); 1025 add_str(hypertas, "hcall-bulk"); 1026 add_str(hypertas, "hcall-set-mode"); 1027 add_str(hypertas, "hcall-sprg0"); 1028 add_str(hypertas, "hcall-copy"); 1029 add_str(hypertas, "hcall-debug"); 1030 add_str(qemu_hypertas, "hcall-memop1"); 1031 1032 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 1033 add_str(hypertas, "hcall-multi-tce"); 1034 } 1035 1036 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 1037 add_str(hypertas, "hcall-hpt-resize"); 1038 } 1039 1040 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 1041 hypertas->str, hypertas->len)); 1042 g_string_free(hypertas, TRUE); 1043 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 1044 qemu_hypertas->str, qemu_hypertas->len)); 1045 g_string_free(qemu_hypertas, TRUE); 1046 1047 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 1048 refpoints, sizeof(refpoints))); 1049 1050 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 1051 maxdomains, sizeof(maxdomains))); 1052 1053 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 1054 RTAS_ERROR_LOG_MAX)); 1055 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 1056 RTAS_EVENT_SCAN_RATE)); 1057 1058 g_assert(msi_nonbroken); 1059 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 1060 1061 /* 1062 * According to PAPR, rtas ibm,os-term does not guarantee a return 1063 * back to the guest cpu. 1064 * 1065 * While an additional ibm,extended-os-term property indicates 1066 * that rtas call return will always occur. Set this property. 1067 */ 1068 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1069 1070 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1071 lrdr_capacity, sizeof(lrdr_capacity))); 1072 1073 spapr_dt_rtas_tokens(fdt, rtas); 1074 } 1075 1076 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features 1077 * that the guest may request and thus the valid values for bytes 24..26 of 1078 * option vector 5: */ 1079 static void spapr_dt_ov5_platform_support(void *fdt, int chosen) 1080 { 1081 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1082 1083 char val[2 * 4] = { 1084 23, 0x00, /* Xive mode, filled in below. */ 1085 24, 0x00, /* Hash/Radix, filled in below. */ 1086 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1087 26, 0x40, /* Radix options: GTSE == yes. */ 1088 }; 1089 1090 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1091 first_ppc_cpu->compat_pvr)) { 1092 /* If we're in a pre POWER9 compat mode then the guest should do hash */ 1093 val[3] = 0x00; /* Hash */ 1094 } else if (kvm_enabled()) { 1095 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1096 val[3] = 0x80; /* OV5_MMU_BOTH */ 1097 } else if (kvmppc_has_cap_mmu_radix()) { 1098 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1099 } else { 1100 val[3] = 0x00; /* Hash */ 1101 } 1102 } else { 1103 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1104 val[3] = 0xC0; 1105 } 1106 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1107 val, sizeof(val))); 1108 } 1109 1110 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 1111 { 1112 MachineState *machine = MACHINE(spapr); 1113 int chosen; 1114 const char *boot_device = machine->boot_order; 1115 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1116 size_t cb = 0; 1117 char *bootlist = get_boot_devices_list(&cb); 1118 1119 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1120 1121 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 1122 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1123 spapr->initrd_base)); 1124 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1125 spapr->initrd_base + spapr->initrd_size)); 1126 1127 if (spapr->kernel_size) { 1128 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1129 cpu_to_be64(spapr->kernel_size) }; 1130 1131 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1132 &kprop, sizeof(kprop))); 1133 if (spapr->kernel_le) { 1134 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1135 } 1136 } 1137 if (boot_menu) { 1138 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1139 } 1140 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1141 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1142 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1143 1144 if (cb && bootlist) { 1145 int i; 1146 1147 for (i = 0; i < cb; i++) { 1148 if (bootlist[i] == '\n') { 1149 bootlist[i] = ' '; 1150 } 1151 } 1152 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1153 } 1154 1155 if (boot_device && strlen(boot_device)) { 1156 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1157 } 1158 1159 if (!spapr->has_graphics && stdout_path) { 1160 /* 1161 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1162 * kernel. New platforms should only use the "stdout-path" property. Set 1163 * the new property and continue using older property to remain 1164 * compatible with the existing firmware. 1165 */ 1166 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1167 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1168 } 1169 1170 spapr_dt_ov5_platform_support(fdt, chosen); 1171 1172 g_free(stdout_path); 1173 g_free(bootlist); 1174 } 1175 1176 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 1177 { 1178 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1179 * KVM to work under pHyp with some guest co-operation */ 1180 int hypervisor; 1181 uint8_t hypercall[16]; 1182 1183 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1184 /* indicate KVM hypercall interface */ 1185 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1186 if (kvmppc_has_cap_fixup_hcalls()) { 1187 /* 1188 * Older KVM versions with older guest kernels were broken 1189 * with the magic page, don't allow the guest to map it. 1190 */ 1191 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1192 sizeof(hypercall))) { 1193 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1194 hypercall, sizeof(hypercall))); 1195 } 1196 } 1197 } 1198 1199 static void *spapr_build_fdt(sPAPRMachineState *spapr, 1200 hwaddr rtas_addr, 1201 hwaddr rtas_size) 1202 { 1203 MachineState *machine = MACHINE(spapr); 1204 MachineClass *mc = MACHINE_GET_CLASS(machine); 1205 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1206 int ret; 1207 void *fdt; 1208 sPAPRPHBState *phb; 1209 char *buf; 1210 1211 fdt = g_malloc0(FDT_MAX_SIZE); 1212 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1213 1214 /* Root node */ 1215 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1216 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1217 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1218 1219 /* 1220 * Add info to guest to indentify which host is it being run on 1221 * and what is the uuid of the guest 1222 */ 1223 if (kvmppc_get_host_model(&buf)) { 1224 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1225 g_free(buf); 1226 } 1227 if (kvmppc_get_host_serial(&buf)) { 1228 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1229 g_free(buf); 1230 } 1231 1232 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1233 1234 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1235 if (qemu_uuid_set) { 1236 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1237 } 1238 g_free(buf); 1239 1240 if (qemu_get_vm_name()) { 1241 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1242 qemu_get_vm_name())); 1243 } 1244 1245 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1246 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1247 1248 /* /interrupt controller */ 1249 spapr_dt_xics(xics_max_server_number(spapr), fdt, PHANDLE_XICP); 1250 1251 ret = spapr_populate_memory(spapr, fdt); 1252 if (ret < 0) { 1253 error_report("couldn't setup memory nodes in fdt"); 1254 exit(1); 1255 } 1256 1257 /* /vdevice */ 1258 spapr_dt_vdevice(spapr->vio_bus, fdt); 1259 1260 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1261 ret = spapr_rng_populate_dt(fdt); 1262 if (ret < 0) { 1263 error_report("could not set up rng device in the fdt"); 1264 exit(1); 1265 } 1266 } 1267 1268 QLIST_FOREACH(phb, &spapr->phbs, list) { 1269 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 1270 if (ret < 0) { 1271 error_report("couldn't setup PCI devices in fdt"); 1272 exit(1); 1273 } 1274 } 1275 1276 /* cpus */ 1277 spapr_populate_cpus_dt_node(fdt, spapr); 1278 1279 if (smc->dr_lmb_enabled) { 1280 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1281 } 1282 1283 if (mc->has_hotpluggable_cpus) { 1284 int offset = fdt_path_offset(fdt, "/cpus"); 1285 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1286 SPAPR_DR_CONNECTOR_TYPE_CPU); 1287 if (ret < 0) { 1288 error_report("Couldn't set up CPU DR device tree properties"); 1289 exit(1); 1290 } 1291 } 1292 1293 /* /event-sources */ 1294 spapr_dt_events(spapr, fdt); 1295 1296 /* /rtas */ 1297 spapr_dt_rtas(spapr, fdt); 1298 1299 /* /chosen */ 1300 spapr_dt_chosen(spapr, fdt); 1301 1302 /* /hypervisor */ 1303 if (kvm_enabled()) { 1304 spapr_dt_hypervisor(spapr, fdt); 1305 } 1306 1307 /* Build memory reserve map */ 1308 if (spapr->kernel_size) { 1309 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1310 } 1311 if (spapr->initrd_size) { 1312 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1313 } 1314 1315 /* ibm,client-architecture-support updates */ 1316 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1317 if (ret < 0) { 1318 error_report("couldn't setup CAS properties fdt"); 1319 exit(1); 1320 } 1321 1322 return fdt; 1323 } 1324 1325 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1326 { 1327 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1328 } 1329 1330 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1331 PowerPCCPU *cpu) 1332 { 1333 CPUPPCState *env = &cpu->env; 1334 1335 /* The TCG path should also be holding the BQL at this point */ 1336 g_assert(qemu_mutex_iothread_locked()); 1337 1338 if (msr_pr) { 1339 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1340 env->gpr[3] = H_PRIVILEGE; 1341 } else { 1342 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1343 } 1344 } 1345 1346 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1347 { 1348 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1349 1350 return spapr->patb_entry; 1351 } 1352 1353 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1354 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1355 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1356 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1357 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1358 1359 /* 1360 * Get the fd to access the kernel htab, re-opening it if necessary 1361 */ 1362 static int get_htab_fd(sPAPRMachineState *spapr) 1363 { 1364 Error *local_err = NULL; 1365 1366 if (spapr->htab_fd >= 0) { 1367 return spapr->htab_fd; 1368 } 1369 1370 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1371 if (spapr->htab_fd < 0) { 1372 error_report_err(local_err); 1373 } 1374 1375 return spapr->htab_fd; 1376 } 1377 1378 void close_htab_fd(sPAPRMachineState *spapr) 1379 { 1380 if (spapr->htab_fd >= 0) { 1381 close(spapr->htab_fd); 1382 } 1383 spapr->htab_fd = -1; 1384 } 1385 1386 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1387 { 1388 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1389 1390 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1391 } 1392 1393 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1394 { 1395 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1396 1397 assert(kvm_enabled()); 1398 1399 if (!spapr->htab) { 1400 return 0; 1401 } 1402 1403 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1404 } 1405 1406 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1407 hwaddr ptex, int n) 1408 { 1409 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1410 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1411 1412 if (!spapr->htab) { 1413 /* 1414 * HTAB is controlled by KVM. Fetch into temporary buffer 1415 */ 1416 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1417 kvmppc_read_hptes(hptes, ptex, n); 1418 return hptes; 1419 } 1420 1421 /* 1422 * HTAB is controlled by QEMU. Just point to the internally 1423 * accessible PTEG. 1424 */ 1425 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1426 } 1427 1428 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1429 const ppc_hash_pte64_t *hptes, 1430 hwaddr ptex, int n) 1431 { 1432 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1433 1434 if (!spapr->htab) { 1435 g_free((void *)hptes); 1436 } 1437 1438 /* Nothing to do for qemu managed HPT */ 1439 } 1440 1441 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1442 uint64_t pte0, uint64_t pte1) 1443 { 1444 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1445 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1446 1447 if (!spapr->htab) { 1448 kvmppc_write_hpte(ptex, pte0, pte1); 1449 } else { 1450 stq_p(spapr->htab + offset, pte0); 1451 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1452 } 1453 } 1454 1455 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1456 { 1457 int shift; 1458 1459 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1460 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1461 * that's much more than is needed for Linux guests */ 1462 shift = ctz64(pow2ceil(ramsize)) - 7; 1463 shift = MAX(shift, 18); /* Minimum architected size */ 1464 shift = MIN(shift, 46); /* Maximum architected size */ 1465 return shift; 1466 } 1467 1468 void spapr_free_hpt(sPAPRMachineState *spapr) 1469 { 1470 g_free(spapr->htab); 1471 spapr->htab = NULL; 1472 spapr->htab_shift = 0; 1473 close_htab_fd(spapr); 1474 } 1475 1476 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1477 Error **errp) 1478 { 1479 long rc; 1480 1481 /* Clean up any HPT info from a previous boot */ 1482 spapr_free_hpt(spapr); 1483 1484 rc = kvmppc_reset_htab(shift); 1485 if (rc < 0) { 1486 /* kernel-side HPT needed, but couldn't allocate one */ 1487 error_setg_errno(errp, errno, 1488 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1489 shift); 1490 /* This is almost certainly fatal, but if the caller really 1491 * wants to carry on with shift == 0, it's welcome to try */ 1492 } else if (rc > 0) { 1493 /* kernel-side HPT allocated */ 1494 if (rc != shift) { 1495 error_setg(errp, 1496 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1497 shift, rc); 1498 } 1499 1500 spapr->htab_shift = shift; 1501 spapr->htab = NULL; 1502 } else { 1503 /* kernel-side HPT not needed, allocate in userspace instead */ 1504 size_t size = 1ULL << shift; 1505 int i; 1506 1507 spapr->htab = qemu_memalign(size, size); 1508 if (!spapr->htab) { 1509 error_setg_errno(errp, errno, 1510 "Could not allocate HPT of order %d", shift); 1511 return; 1512 } 1513 1514 memset(spapr->htab, 0, size); 1515 spapr->htab_shift = shift; 1516 1517 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1518 DIRTY_HPTE(HPTE(spapr->htab, i)); 1519 } 1520 } 1521 /* We're setting up a hash table, so that means we're not radix */ 1522 spapr->patb_entry = 0; 1523 } 1524 1525 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1526 { 1527 int hpt_shift; 1528 1529 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1530 || (spapr->cas_reboot 1531 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1532 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1533 } else { 1534 uint64_t current_ram_size; 1535 1536 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1537 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1538 } 1539 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1540 1541 if (spapr->vrma_adjust) { 1542 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1543 spapr->htab_shift); 1544 } 1545 } 1546 1547 static int spapr_reset_drcs(Object *child, void *opaque) 1548 { 1549 sPAPRDRConnector *drc = 1550 (sPAPRDRConnector *) object_dynamic_cast(child, 1551 TYPE_SPAPR_DR_CONNECTOR); 1552 1553 if (drc) { 1554 spapr_drc_reset(drc); 1555 } 1556 1557 return 0; 1558 } 1559 1560 static void spapr_machine_reset(void) 1561 { 1562 MachineState *machine = MACHINE(qdev_get_machine()); 1563 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1564 PowerPCCPU *first_ppc_cpu; 1565 uint32_t rtas_limit; 1566 hwaddr rtas_addr, fdt_addr; 1567 void *fdt; 1568 int rc; 1569 1570 spapr_caps_apply(spapr); 1571 1572 first_ppc_cpu = POWERPC_CPU(first_cpu); 1573 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1574 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1575 spapr->max_compat_pvr)) { 1576 /* If using KVM with radix mode available, VCPUs can be started 1577 * without a HPT because KVM will start them in radix mode. 1578 * Set the GR bit in PATB so that we know there is no HPT. */ 1579 spapr->patb_entry = PATBE1_GR; 1580 } else { 1581 spapr_setup_hpt_and_vrma(spapr); 1582 } 1583 1584 /* if this reset wasn't generated by CAS, we should reset our 1585 * negotiated options and start from scratch */ 1586 if (!spapr->cas_reboot) { 1587 spapr_ovec_cleanup(spapr->ov5_cas); 1588 spapr->ov5_cas = spapr_ovec_new(); 1589 1590 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); 1591 } 1592 1593 if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 1594 spapr_irq_msi_reset(spapr); 1595 } 1596 1597 qemu_devices_reset(); 1598 1599 /* DRC reset may cause a device to be unplugged. This will cause troubles 1600 * if this device is used by another device (eg, a running vhost backend 1601 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1602 * situations, we reset DRCs after all devices have been reset. 1603 */ 1604 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1605 1606 spapr_clear_pending_events(spapr); 1607 1608 /* 1609 * We place the device tree and RTAS just below either the top of the RMA, 1610 * or just below 2GB, whichever is lowere, so that it can be 1611 * processed with 32-bit real mode code if necessary 1612 */ 1613 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1614 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1615 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1616 1617 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1618 1619 spapr_load_rtas(spapr, fdt, rtas_addr); 1620 1621 rc = fdt_pack(fdt); 1622 1623 /* Should only fail if we've built a corrupted tree */ 1624 assert(rc == 0); 1625 1626 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1627 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1628 fdt_totalsize(fdt), FDT_MAX_SIZE); 1629 exit(1); 1630 } 1631 1632 /* Load the fdt */ 1633 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1634 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1635 g_free(fdt); 1636 1637 /* Set up the entry state */ 1638 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); 1639 first_ppc_cpu->env.gpr[5] = 0; 1640 1641 spapr->cas_reboot = false; 1642 } 1643 1644 static void spapr_create_nvram(sPAPRMachineState *spapr) 1645 { 1646 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1647 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1648 1649 if (dinfo) { 1650 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1651 &error_fatal); 1652 } 1653 1654 qdev_init_nofail(dev); 1655 1656 spapr->nvram = (struct sPAPRNVRAM *)dev; 1657 } 1658 1659 static void spapr_rtc_create(sPAPRMachineState *spapr) 1660 { 1661 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1662 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1663 &error_fatal); 1664 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1665 &error_fatal); 1666 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1667 "date", &error_fatal); 1668 } 1669 1670 /* Returns whether we want to use VGA or not */ 1671 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1672 { 1673 switch (vga_interface_type) { 1674 case VGA_NONE: 1675 return false; 1676 case VGA_DEVICE: 1677 return true; 1678 case VGA_STD: 1679 case VGA_VIRTIO: 1680 return pci_vga_init(pci_bus) != NULL; 1681 default: 1682 error_setg(errp, 1683 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1684 return false; 1685 } 1686 } 1687 1688 static int spapr_pre_load(void *opaque) 1689 { 1690 int rc; 1691 1692 rc = spapr_caps_pre_load(opaque); 1693 if (rc) { 1694 return rc; 1695 } 1696 1697 return 0; 1698 } 1699 1700 static int spapr_post_load(void *opaque, int version_id) 1701 { 1702 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1703 int err = 0; 1704 1705 err = spapr_caps_post_migration(spapr); 1706 if (err) { 1707 return err; 1708 } 1709 1710 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1711 CPUState *cs; 1712 CPU_FOREACH(cs) { 1713 PowerPCCPU *cpu = POWERPC_CPU(cs); 1714 icp_resend(ICP(cpu->intc)); 1715 } 1716 } 1717 1718 /* In earlier versions, there was no separate qdev for the PAPR 1719 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1720 * So when migrating from those versions, poke the incoming offset 1721 * value into the RTC device */ 1722 if (version_id < 3) { 1723 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1724 } 1725 1726 if (kvm_enabled() && spapr->patb_entry) { 1727 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1728 bool radix = !!(spapr->patb_entry & PATBE1_GR); 1729 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1730 1731 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1732 if (err) { 1733 error_report("Process table config unsupported by the host"); 1734 return -EINVAL; 1735 } 1736 } 1737 1738 return err; 1739 } 1740 1741 static int spapr_pre_save(void *opaque) 1742 { 1743 int rc; 1744 1745 rc = spapr_caps_pre_save(opaque); 1746 if (rc) { 1747 return rc; 1748 } 1749 1750 return 0; 1751 } 1752 1753 static bool version_before_3(void *opaque, int version_id) 1754 { 1755 return version_id < 3; 1756 } 1757 1758 static bool spapr_pending_events_needed(void *opaque) 1759 { 1760 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1761 return !QTAILQ_EMPTY(&spapr->pending_events); 1762 } 1763 1764 static const VMStateDescription vmstate_spapr_event_entry = { 1765 .name = "spapr_event_log_entry", 1766 .version_id = 1, 1767 .minimum_version_id = 1, 1768 .fields = (VMStateField[]) { 1769 VMSTATE_UINT32(summary, sPAPREventLogEntry), 1770 VMSTATE_UINT32(extended_length, sPAPREventLogEntry), 1771 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, 1772 NULL, extended_length), 1773 VMSTATE_END_OF_LIST() 1774 }, 1775 }; 1776 1777 static const VMStateDescription vmstate_spapr_pending_events = { 1778 .name = "spapr_pending_events", 1779 .version_id = 1, 1780 .minimum_version_id = 1, 1781 .needed = spapr_pending_events_needed, 1782 .fields = (VMStateField[]) { 1783 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, 1784 vmstate_spapr_event_entry, sPAPREventLogEntry, next), 1785 VMSTATE_END_OF_LIST() 1786 }, 1787 }; 1788 1789 static bool spapr_ov5_cas_needed(void *opaque) 1790 { 1791 sPAPRMachineState *spapr = opaque; 1792 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1793 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1794 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1795 bool cas_needed; 1796 1797 /* Prior to the introduction of sPAPROptionVector, we had two option 1798 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1799 * Both of these options encode machine topology into the device-tree 1800 * in such a way that the now-booted OS should still be able to interact 1801 * appropriately with QEMU regardless of what options were actually 1802 * negotiatied on the source side. 1803 * 1804 * As such, we can avoid migrating the CAS-negotiated options if these 1805 * are the only options available on the current machine/platform. 1806 * Since these are the only options available for pseries-2.7 and 1807 * earlier, this allows us to maintain old->new/new->old migration 1808 * compatibility. 1809 * 1810 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1811 * via default pseries-2.8 machines and explicit command-line parameters. 1812 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1813 * of the actual CAS-negotiated values to continue working properly. For 1814 * example, availability of memory unplug depends on knowing whether 1815 * OV5_HP_EVT was negotiated via CAS. 1816 * 1817 * Thus, for any cases where the set of available CAS-negotiatable 1818 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1819 * include the CAS-negotiated options in the migration stream, unless 1820 * if they affect boot time behaviour only. 1821 */ 1822 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1823 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1824 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1825 1826 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1827 * the mask itself since in the future it's possible "legacy" bits may be 1828 * removed via machine options, which could generate a false positive 1829 * that breaks migration. 1830 */ 1831 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1832 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1833 1834 spapr_ovec_cleanup(ov5_mask); 1835 spapr_ovec_cleanup(ov5_legacy); 1836 spapr_ovec_cleanup(ov5_removed); 1837 1838 return cas_needed; 1839 } 1840 1841 static const VMStateDescription vmstate_spapr_ov5_cas = { 1842 .name = "spapr_option_vector_ov5_cas", 1843 .version_id = 1, 1844 .minimum_version_id = 1, 1845 .needed = spapr_ov5_cas_needed, 1846 .fields = (VMStateField[]) { 1847 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1848 vmstate_spapr_ovec, sPAPROptionVector), 1849 VMSTATE_END_OF_LIST() 1850 }, 1851 }; 1852 1853 static bool spapr_patb_entry_needed(void *opaque) 1854 { 1855 sPAPRMachineState *spapr = opaque; 1856 1857 return !!spapr->patb_entry; 1858 } 1859 1860 static const VMStateDescription vmstate_spapr_patb_entry = { 1861 .name = "spapr_patb_entry", 1862 .version_id = 1, 1863 .minimum_version_id = 1, 1864 .needed = spapr_patb_entry_needed, 1865 .fields = (VMStateField[]) { 1866 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1867 VMSTATE_END_OF_LIST() 1868 }, 1869 }; 1870 1871 static bool spapr_irq_map_needed(void *opaque) 1872 { 1873 sPAPRMachineState *spapr = opaque; 1874 1875 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1876 } 1877 1878 static const VMStateDescription vmstate_spapr_irq_map = { 1879 .name = "spapr_irq_map", 1880 .version_id = 1, 1881 .minimum_version_id = 1, 1882 .needed = spapr_irq_map_needed, 1883 .fields = (VMStateField[]) { 1884 VMSTATE_BITMAP(irq_map, sPAPRMachineState, 0, irq_map_nr), 1885 VMSTATE_END_OF_LIST() 1886 }, 1887 }; 1888 1889 static const VMStateDescription vmstate_spapr = { 1890 .name = "spapr", 1891 .version_id = 3, 1892 .minimum_version_id = 1, 1893 .pre_load = spapr_pre_load, 1894 .post_load = spapr_post_load, 1895 .pre_save = spapr_pre_save, 1896 .fields = (VMStateField[]) { 1897 /* used to be @next_irq */ 1898 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1899 1900 /* RTC offset */ 1901 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1902 1903 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1904 VMSTATE_END_OF_LIST() 1905 }, 1906 .subsections = (const VMStateDescription*[]) { 1907 &vmstate_spapr_ov5_cas, 1908 &vmstate_spapr_patb_entry, 1909 &vmstate_spapr_pending_events, 1910 &vmstate_spapr_cap_htm, 1911 &vmstate_spapr_cap_vsx, 1912 &vmstate_spapr_cap_dfp, 1913 &vmstate_spapr_cap_cfpc, 1914 &vmstate_spapr_cap_sbbc, 1915 &vmstate_spapr_cap_ibs, 1916 &vmstate_spapr_irq_map, 1917 NULL 1918 } 1919 }; 1920 1921 static int htab_save_setup(QEMUFile *f, void *opaque) 1922 { 1923 sPAPRMachineState *spapr = opaque; 1924 1925 /* "Iteration" header */ 1926 if (!spapr->htab_shift) { 1927 qemu_put_be32(f, -1); 1928 } else { 1929 qemu_put_be32(f, spapr->htab_shift); 1930 } 1931 1932 if (spapr->htab) { 1933 spapr->htab_save_index = 0; 1934 spapr->htab_first_pass = true; 1935 } else { 1936 if (spapr->htab_shift) { 1937 assert(kvm_enabled()); 1938 } 1939 } 1940 1941 1942 return 0; 1943 } 1944 1945 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr, 1946 int chunkstart, int n_valid, int n_invalid) 1947 { 1948 qemu_put_be32(f, chunkstart); 1949 qemu_put_be16(f, n_valid); 1950 qemu_put_be16(f, n_invalid); 1951 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1952 HASH_PTE_SIZE_64 * n_valid); 1953 } 1954 1955 static void htab_save_end_marker(QEMUFile *f) 1956 { 1957 qemu_put_be32(f, 0); 1958 qemu_put_be16(f, 0); 1959 qemu_put_be16(f, 0); 1960 } 1961 1962 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1963 int64_t max_ns) 1964 { 1965 bool has_timeout = max_ns != -1; 1966 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1967 int index = spapr->htab_save_index; 1968 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1969 1970 assert(spapr->htab_first_pass); 1971 1972 do { 1973 int chunkstart; 1974 1975 /* Consume invalid HPTEs */ 1976 while ((index < htabslots) 1977 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1978 CLEAN_HPTE(HPTE(spapr->htab, index)); 1979 index++; 1980 } 1981 1982 /* Consume valid HPTEs */ 1983 chunkstart = index; 1984 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1985 && HPTE_VALID(HPTE(spapr->htab, index))) { 1986 CLEAN_HPTE(HPTE(spapr->htab, index)); 1987 index++; 1988 } 1989 1990 if (index > chunkstart) { 1991 int n_valid = index - chunkstart; 1992 1993 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 1994 1995 if (has_timeout && 1996 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1997 break; 1998 } 1999 } 2000 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2001 2002 if (index >= htabslots) { 2003 assert(index == htabslots); 2004 index = 0; 2005 spapr->htab_first_pass = false; 2006 } 2007 spapr->htab_save_index = index; 2008 } 2009 2010 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 2011 int64_t max_ns) 2012 { 2013 bool final = max_ns < 0; 2014 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2015 int examined = 0, sent = 0; 2016 int index = spapr->htab_save_index; 2017 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2018 2019 assert(!spapr->htab_first_pass); 2020 2021 do { 2022 int chunkstart, invalidstart; 2023 2024 /* Consume non-dirty HPTEs */ 2025 while ((index < htabslots) 2026 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2027 index++; 2028 examined++; 2029 } 2030 2031 chunkstart = index; 2032 /* Consume valid dirty HPTEs */ 2033 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2034 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2035 && HPTE_VALID(HPTE(spapr->htab, index))) { 2036 CLEAN_HPTE(HPTE(spapr->htab, index)); 2037 index++; 2038 examined++; 2039 } 2040 2041 invalidstart = index; 2042 /* Consume invalid dirty HPTEs */ 2043 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2044 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2045 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2046 CLEAN_HPTE(HPTE(spapr->htab, index)); 2047 index++; 2048 examined++; 2049 } 2050 2051 if (index > chunkstart) { 2052 int n_valid = invalidstart - chunkstart; 2053 int n_invalid = index - invalidstart; 2054 2055 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2056 sent += index - chunkstart; 2057 2058 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2059 break; 2060 } 2061 } 2062 2063 if (examined >= htabslots) { 2064 break; 2065 } 2066 2067 if (index >= htabslots) { 2068 assert(index == htabslots); 2069 index = 0; 2070 } 2071 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2072 2073 if (index >= htabslots) { 2074 assert(index == htabslots); 2075 index = 0; 2076 } 2077 2078 spapr->htab_save_index = index; 2079 2080 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2081 } 2082 2083 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2084 #define MAX_KVM_BUF_SIZE 2048 2085 2086 static int htab_save_iterate(QEMUFile *f, void *opaque) 2087 { 2088 sPAPRMachineState *spapr = opaque; 2089 int fd; 2090 int rc = 0; 2091 2092 /* Iteration header */ 2093 if (!spapr->htab_shift) { 2094 qemu_put_be32(f, -1); 2095 return 1; 2096 } else { 2097 qemu_put_be32(f, 0); 2098 } 2099 2100 if (!spapr->htab) { 2101 assert(kvm_enabled()); 2102 2103 fd = get_htab_fd(spapr); 2104 if (fd < 0) { 2105 return fd; 2106 } 2107 2108 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2109 if (rc < 0) { 2110 return rc; 2111 } 2112 } else if (spapr->htab_first_pass) { 2113 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2114 } else { 2115 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2116 } 2117 2118 htab_save_end_marker(f); 2119 2120 return rc; 2121 } 2122 2123 static int htab_save_complete(QEMUFile *f, void *opaque) 2124 { 2125 sPAPRMachineState *spapr = opaque; 2126 int fd; 2127 2128 /* Iteration header */ 2129 if (!spapr->htab_shift) { 2130 qemu_put_be32(f, -1); 2131 return 0; 2132 } else { 2133 qemu_put_be32(f, 0); 2134 } 2135 2136 if (!spapr->htab) { 2137 int rc; 2138 2139 assert(kvm_enabled()); 2140 2141 fd = get_htab_fd(spapr); 2142 if (fd < 0) { 2143 return fd; 2144 } 2145 2146 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2147 if (rc < 0) { 2148 return rc; 2149 } 2150 } else { 2151 if (spapr->htab_first_pass) { 2152 htab_save_first_pass(f, spapr, -1); 2153 } 2154 htab_save_later_pass(f, spapr, -1); 2155 } 2156 2157 /* End marker */ 2158 htab_save_end_marker(f); 2159 2160 return 0; 2161 } 2162 2163 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2164 { 2165 sPAPRMachineState *spapr = opaque; 2166 uint32_t section_hdr; 2167 int fd = -1; 2168 Error *local_err = NULL; 2169 2170 if (version_id < 1 || version_id > 1) { 2171 error_report("htab_load() bad version"); 2172 return -EINVAL; 2173 } 2174 2175 section_hdr = qemu_get_be32(f); 2176 2177 if (section_hdr == -1) { 2178 spapr_free_hpt(spapr); 2179 return 0; 2180 } 2181 2182 if (section_hdr) { 2183 /* First section gives the htab size */ 2184 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2185 if (local_err) { 2186 error_report_err(local_err); 2187 return -EINVAL; 2188 } 2189 return 0; 2190 } 2191 2192 if (!spapr->htab) { 2193 assert(kvm_enabled()); 2194 2195 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2196 if (fd < 0) { 2197 error_report_err(local_err); 2198 return fd; 2199 } 2200 } 2201 2202 while (true) { 2203 uint32_t index; 2204 uint16_t n_valid, n_invalid; 2205 2206 index = qemu_get_be32(f); 2207 n_valid = qemu_get_be16(f); 2208 n_invalid = qemu_get_be16(f); 2209 2210 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2211 /* End of Stream */ 2212 break; 2213 } 2214 2215 if ((index + n_valid + n_invalid) > 2216 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2217 /* Bad index in stream */ 2218 error_report( 2219 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2220 index, n_valid, n_invalid, spapr->htab_shift); 2221 return -EINVAL; 2222 } 2223 2224 if (spapr->htab) { 2225 if (n_valid) { 2226 qemu_get_buffer(f, HPTE(spapr->htab, index), 2227 HASH_PTE_SIZE_64 * n_valid); 2228 } 2229 if (n_invalid) { 2230 memset(HPTE(spapr->htab, index + n_valid), 0, 2231 HASH_PTE_SIZE_64 * n_invalid); 2232 } 2233 } else { 2234 int rc; 2235 2236 assert(fd >= 0); 2237 2238 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2239 if (rc < 0) { 2240 return rc; 2241 } 2242 } 2243 } 2244 2245 if (!spapr->htab) { 2246 assert(fd >= 0); 2247 close(fd); 2248 } 2249 2250 return 0; 2251 } 2252 2253 static void htab_save_cleanup(void *opaque) 2254 { 2255 sPAPRMachineState *spapr = opaque; 2256 2257 close_htab_fd(spapr); 2258 } 2259 2260 static SaveVMHandlers savevm_htab_handlers = { 2261 .save_setup = htab_save_setup, 2262 .save_live_iterate = htab_save_iterate, 2263 .save_live_complete_precopy = htab_save_complete, 2264 .save_cleanup = htab_save_cleanup, 2265 .load_state = htab_load, 2266 }; 2267 2268 static void spapr_boot_set(void *opaque, const char *boot_device, 2269 Error **errp) 2270 { 2271 MachineState *machine = MACHINE(opaque); 2272 machine->boot_order = g_strdup(boot_device); 2273 } 2274 2275 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 2276 { 2277 MachineState *machine = MACHINE(spapr); 2278 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2279 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2280 int i; 2281 2282 for (i = 0; i < nr_lmbs; i++) { 2283 uint64_t addr; 2284 2285 addr = i * lmb_size + machine->device_memory->base; 2286 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2287 addr / lmb_size); 2288 } 2289 } 2290 2291 /* 2292 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2293 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2294 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2295 */ 2296 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2297 { 2298 int i; 2299 2300 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2301 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2302 " is not aligned to %" PRIu64 " MiB", 2303 machine->ram_size, 2304 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2305 return; 2306 } 2307 2308 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2309 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2310 " is not aligned to %" PRIu64 " MiB", 2311 machine->ram_size, 2312 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2313 return; 2314 } 2315 2316 for (i = 0; i < nb_numa_nodes; i++) { 2317 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2318 error_setg(errp, 2319 "Node %d memory size 0x%" PRIx64 2320 " is not aligned to %" PRIu64 " MiB", 2321 i, numa_info[i].node_mem, 2322 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2323 return; 2324 } 2325 } 2326 } 2327 2328 /* find cpu slot in machine->possible_cpus by core_id */ 2329 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2330 { 2331 int index = id / smp_threads; 2332 2333 if (index >= ms->possible_cpus->len) { 2334 return NULL; 2335 } 2336 if (idx) { 2337 *idx = index; 2338 } 2339 return &ms->possible_cpus->cpus[index]; 2340 } 2341 2342 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) 2343 { 2344 Error *local_err = NULL; 2345 bool vsmt_user = !!spapr->vsmt; 2346 int kvm_smt = kvmppc_smt_threads(); 2347 int ret; 2348 2349 if (!kvm_enabled() && (smp_threads > 1)) { 2350 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2351 "on a pseries machine"); 2352 goto out; 2353 } 2354 if (!is_power_of_2(smp_threads)) { 2355 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2356 "machine because it must be a power of 2", smp_threads); 2357 goto out; 2358 } 2359 2360 /* Detemine the VSMT mode to use: */ 2361 if (vsmt_user) { 2362 if (spapr->vsmt < smp_threads) { 2363 error_setg(&local_err, "Cannot support VSMT mode %d" 2364 " because it must be >= threads/core (%d)", 2365 spapr->vsmt, smp_threads); 2366 goto out; 2367 } 2368 /* In this case, spapr->vsmt has been set by the command line */ 2369 } else { 2370 /* 2371 * Default VSMT value is tricky, because we need it to be as 2372 * consistent as possible (for migration), but this requires 2373 * changing it for at least some existing cases. We pick 8 as 2374 * the value that we'd get with KVM on POWER8, the 2375 * overwhelmingly common case in production systems. 2376 */ 2377 spapr->vsmt = MAX(8, smp_threads); 2378 } 2379 2380 /* KVM: If necessary, set the SMT mode: */ 2381 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2382 ret = kvmppc_set_smt_threads(spapr->vsmt); 2383 if (ret) { 2384 /* Looks like KVM isn't able to change VSMT mode */ 2385 error_setg(&local_err, 2386 "Failed to set KVM's VSMT mode to %d (errno %d)", 2387 spapr->vsmt, ret); 2388 /* We can live with that if the default one is big enough 2389 * for the number of threads, and a submultiple of the one 2390 * we want. In this case we'll waste some vcpu ids, but 2391 * behaviour will be correct */ 2392 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2393 warn_report_err(local_err); 2394 local_err = NULL; 2395 goto out; 2396 } else { 2397 if (!vsmt_user) { 2398 error_append_hint(&local_err, 2399 "On PPC, a VM with %d threads/core" 2400 " on a host with %d threads/core" 2401 " requires the use of VSMT mode %d.\n", 2402 smp_threads, kvm_smt, spapr->vsmt); 2403 } 2404 kvmppc_hint_smt_possible(&local_err); 2405 goto out; 2406 } 2407 } 2408 } 2409 /* else TCG: nothing to do currently */ 2410 out: 2411 error_propagate(errp, local_err); 2412 } 2413 2414 static void spapr_init_cpus(sPAPRMachineState *spapr) 2415 { 2416 MachineState *machine = MACHINE(spapr); 2417 MachineClass *mc = MACHINE_GET_CLASS(machine); 2418 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2419 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2420 const CPUArchIdList *possible_cpus; 2421 int boot_cores_nr = smp_cpus / smp_threads; 2422 int i; 2423 2424 possible_cpus = mc->possible_cpu_arch_ids(machine); 2425 if (mc->has_hotpluggable_cpus) { 2426 if (smp_cpus % smp_threads) { 2427 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2428 smp_cpus, smp_threads); 2429 exit(1); 2430 } 2431 if (max_cpus % smp_threads) { 2432 error_report("max_cpus (%u) must be multiple of threads (%u)", 2433 max_cpus, smp_threads); 2434 exit(1); 2435 } 2436 } else { 2437 if (max_cpus != smp_cpus) { 2438 error_report("This machine version does not support CPU hotplug"); 2439 exit(1); 2440 } 2441 boot_cores_nr = possible_cpus->len; 2442 } 2443 2444 /* VSMT must be set in order to be able to compute VCPU ids, ie to 2445 * call xics_max_server_number() or spapr_vcpu_id(). 2446 */ 2447 spapr_set_vsmt_mode(spapr, &error_fatal); 2448 2449 if (smc->pre_2_10_has_unused_icps) { 2450 int i; 2451 2452 for (i = 0; i < xics_max_server_number(spapr); i++) { 2453 /* Dummy entries get deregistered when real ICPState objects 2454 * are registered during CPU core hotplug. 2455 */ 2456 pre_2_10_vmstate_register_dummy_icp(i); 2457 } 2458 } 2459 2460 for (i = 0; i < possible_cpus->len; i++) { 2461 int core_id = i * smp_threads; 2462 2463 if (mc->has_hotpluggable_cpus) { 2464 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2465 spapr_vcpu_id(spapr, core_id)); 2466 } 2467 2468 if (i < boot_cores_nr) { 2469 Object *core = object_new(type); 2470 int nr_threads = smp_threads; 2471 2472 /* Handle the partially filled core for older machine types */ 2473 if ((i + 1) * smp_threads >= smp_cpus) { 2474 nr_threads = smp_cpus - i * smp_threads; 2475 } 2476 2477 object_property_set_int(core, nr_threads, "nr-threads", 2478 &error_fatal); 2479 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2480 &error_fatal); 2481 object_property_set_bool(core, true, "realized", &error_fatal); 2482 } 2483 } 2484 } 2485 2486 /* pSeries LPAR / sPAPR hardware init */ 2487 static void spapr_machine_init(MachineState *machine) 2488 { 2489 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2490 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2491 const char *kernel_filename = machine->kernel_filename; 2492 const char *initrd_filename = machine->initrd_filename; 2493 PCIHostState *phb; 2494 int i; 2495 MemoryRegion *sysmem = get_system_memory(); 2496 MemoryRegion *ram = g_new(MemoryRegion, 1); 2497 hwaddr node0_size = spapr_node0_size(machine); 2498 long load_limit, fw_size; 2499 char *filename; 2500 Error *resize_hpt_err = NULL; 2501 2502 msi_nonbroken = true; 2503 2504 QLIST_INIT(&spapr->phbs); 2505 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2506 2507 /* Determine capabilities to run with */ 2508 spapr_caps_init(spapr); 2509 2510 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2511 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2512 /* 2513 * If the user explicitly requested a mode we should either 2514 * supply it, or fail completely (which we do below). But if 2515 * it's not set explicitly, we reset our mode to something 2516 * that works 2517 */ 2518 if (resize_hpt_err) { 2519 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2520 error_free(resize_hpt_err); 2521 resize_hpt_err = NULL; 2522 } else { 2523 spapr->resize_hpt = smc->resize_hpt_default; 2524 } 2525 } 2526 2527 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2528 2529 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2530 /* 2531 * User requested HPT resize, but this host can't supply it. Bail out 2532 */ 2533 error_report_err(resize_hpt_err); 2534 exit(1); 2535 } 2536 2537 spapr->rma_size = node0_size; 2538 2539 /* With KVM, we don't actually know whether KVM supports an 2540 * unbounded RMA (PR KVM) or is limited by the hash table size 2541 * (HV KVM using VRMA), so we always assume the latter 2542 * 2543 * In that case, we also limit the initial allocations for RTAS 2544 * etc... to 256M since we have no way to know what the VRMA size 2545 * is going to be as it depends on the size of the hash table 2546 * which isn't determined yet. 2547 */ 2548 if (kvm_enabled()) { 2549 spapr->vrma_adjust = 1; 2550 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2551 } 2552 2553 /* Actually we don't support unbounded RMA anymore since we added 2554 * proper emulation of HV mode. The max we can get is 16G which 2555 * also happens to be what we configure for PAPR mode so make sure 2556 * we don't do anything bigger than that 2557 */ 2558 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2559 2560 if (spapr->rma_size > node0_size) { 2561 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2562 spapr->rma_size); 2563 exit(1); 2564 } 2565 2566 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2567 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2568 2569 /* Set up Interrupt Controller before we create the VCPUs */ 2570 smc->irq->init(spapr, &error_fatal); 2571 2572 /* Set up containers for ibm,client-architecture-support negotiated options 2573 */ 2574 spapr->ov5 = spapr_ovec_new(); 2575 spapr->ov5_cas = spapr_ovec_new(); 2576 2577 if (smc->dr_lmb_enabled) { 2578 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2579 spapr_validate_node_memory(machine, &error_fatal); 2580 } 2581 2582 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2583 2584 /* advertise support for dedicated HP event source to guests */ 2585 if (spapr->use_hotplug_event_source) { 2586 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2587 } 2588 2589 /* advertise support for HPT resizing */ 2590 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2591 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2592 } 2593 2594 /* advertise support for ibm,dyamic-memory-v2 */ 2595 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2596 2597 /* init CPUs */ 2598 spapr_init_cpus(spapr); 2599 2600 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2601 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2602 spapr->max_compat_pvr)) { 2603 /* KVM and TCG always allow GTSE with radix... */ 2604 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2605 } 2606 /* ... but not with hash (currently). */ 2607 2608 if (kvm_enabled()) { 2609 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2610 kvmppc_enable_logical_ci_hcalls(); 2611 kvmppc_enable_set_mode_hcall(); 2612 2613 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2614 kvmppc_enable_clear_ref_mod_hcalls(); 2615 } 2616 2617 /* allocate RAM */ 2618 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2619 machine->ram_size); 2620 memory_region_add_subregion(sysmem, 0, ram); 2621 2622 /* always allocate the device memory information */ 2623 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2624 2625 /* initialize hotplug memory address space */ 2626 if (machine->ram_size < machine->maxram_size) { 2627 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2628 /* 2629 * Limit the number of hotpluggable memory slots to half the number 2630 * slots that KVM supports, leaving the other half for PCI and other 2631 * devices. However ensure that number of slots doesn't drop below 32. 2632 */ 2633 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2634 SPAPR_MAX_RAM_SLOTS; 2635 2636 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2637 max_memslots = SPAPR_MAX_RAM_SLOTS; 2638 } 2639 if (machine->ram_slots > max_memslots) { 2640 error_report("Specified number of memory slots %" 2641 PRIu64" exceeds max supported %d", 2642 machine->ram_slots, max_memslots); 2643 exit(1); 2644 } 2645 2646 machine->device_memory->base = ROUND_UP(machine->ram_size, 2647 SPAPR_DEVICE_MEM_ALIGN); 2648 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2649 "device-memory", device_mem_size); 2650 memory_region_add_subregion(sysmem, machine->device_memory->base, 2651 &machine->device_memory->mr); 2652 } 2653 2654 if (smc->dr_lmb_enabled) { 2655 spapr_create_lmb_dr_connectors(spapr); 2656 } 2657 2658 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2659 if (!filename) { 2660 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2661 exit(1); 2662 } 2663 spapr->rtas_size = get_image_size(filename); 2664 if (spapr->rtas_size < 0) { 2665 error_report("Could not get size of LPAR rtas '%s'", filename); 2666 exit(1); 2667 } 2668 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2669 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2670 error_report("Could not load LPAR rtas '%s'", filename); 2671 exit(1); 2672 } 2673 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2674 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2675 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2676 exit(1); 2677 } 2678 g_free(filename); 2679 2680 /* Set up RTAS event infrastructure */ 2681 spapr_events_init(spapr); 2682 2683 /* Set up the RTC RTAS interfaces */ 2684 spapr_rtc_create(spapr); 2685 2686 /* Set up VIO bus */ 2687 spapr->vio_bus = spapr_vio_bus_init(); 2688 2689 for (i = 0; i < serial_max_hds(); i++) { 2690 if (serial_hd(i)) { 2691 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2692 } 2693 } 2694 2695 /* We always have at least the nvram device on VIO */ 2696 spapr_create_nvram(spapr); 2697 2698 /* Set up PCI */ 2699 spapr_pci_rtas_init(); 2700 2701 phb = spapr_create_phb(spapr, 0); 2702 2703 for (i = 0; i < nb_nics; i++) { 2704 NICInfo *nd = &nd_table[i]; 2705 2706 if (!nd->model) { 2707 nd->model = g_strdup("spapr-vlan"); 2708 } 2709 2710 if (g_str_equal(nd->model, "spapr-vlan") || 2711 g_str_equal(nd->model, "ibmveth")) { 2712 spapr_vlan_create(spapr->vio_bus, nd); 2713 } else { 2714 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2715 } 2716 } 2717 2718 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2719 spapr_vscsi_create(spapr->vio_bus); 2720 } 2721 2722 /* Graphics */ 2723 if (spapr_vga_init(phb->bus, &error_fatal)) { 2724 spapr->has_graphics = true; 2725 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2726 } 2727 2728 if (machine->usb) { 2729 if (smc->use_ohci_by_default) { 2730 pci_create_simple(phb->bus, -1, "pci-ohci"); 2731 } else { 2732 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2733 } 2734 2735 if (spapr->has_graphics) { 2736 USBBus *usb_bus = usb_bus_find(-1); 2737 2738 usb_create_simple(usb_bus, "usb-kbd"); 2739 usb_create_simple(usb_bus, "usb-mouse"); 2740 } 2741 } 2742 2743 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) { 2744 error_report( 2745 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2746 MIN_RMA_SLOF); 2747 exit(1); 2748 } 2749 2750 if (kernel_filename) { 2751 uint64_t lowaddr = 0; 2752 2753 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2754 NULL, NULL, &lowaddr, NULL, 1, 2755 PPC_ELF_MACHINE, 0, 0); 2756 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2757 spapr->kernel_size = load_elf(kernel_filename, 2758 translate_kernel_address, NULL, NULL, 2759 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2760 0, 0); 2761 spapr->kernel_le = spapr->kernel_size > 0; 2762 } 2763 if (spapr->kernel_size < 0) { 2764 error_report("error loading %s: %s", kernel_filename, 2765 load_elf_strerror(spapr->kernel_size)); 2766 exit(1); 2767 } 2768 2769 /* load initrd */ 2770 if (initrd_filename) { 2771 /* Try to locate the initrd in the gap between the kernel 2772 * and the firmware. Add a bit of space just in case 2773 */ 2774 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2775 + 0x1ffff) & ~0xffff; 2776 spapr->initrd_size = load_image_targphys(initrd_filename, 2777 spapr->initrd_base, 2778 load_limit 2779 - spapr->initrd_base); 2780 if (spapr->initrd_size < 0) { 2781 error_report("could not load initial ram disk '%s'", 2782 initrd_filename); 2783 exit(1); 2784 } 2785 } 2786 } 2787 2788 if (bios_name == NULL) { 2789 bios_name = FW_FILE_NAME; 2790 } 2791 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2792 if (!filename) { 2793 error_report("Could not find LPAR firmware '%s'", bios_name); 2794 exit(1); 2795 } 2796 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2797 if (fw_size <= 0) { 2798 error_report("Could not load LPAR firmware '%s'", filename); 2799 exit(1); 2800 } 2801 g_free(filename); 2802 2803 /* FIXME: Should register things through the MachineState's qdev 2804 * interface, this is a legacy from the sPAPREnvironment structure 2805 * which predated MachineState but had a similar function */ 2806 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2807 register_savevm_live(NULL, "spapr/htab", -1, 1, 2808 &savevm_htab_handlers, spapr); 2809 2810 qemu_register_boot_set(spapr_boot_set, spapr); 2811 2812 if (kvm_enabled()) { 2813 /* to stop and start vmclock */ 2814 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2815 &spapr->tb); 2816 2817 kvmppc_spapr_enable_inkernel_multitce(); 2818 } 2819 } 2820 2821 static int spapr_kvm_type(const char *vm_type) 2822 { 2823 if (!vm_type) { 2824 return 0; 2825 } 2826 2827 if (!strcmp(vm_type, "HV")) { 2828 return 1; 2829 } 2830 2831 if (!strcmp(vm_type, "PR")) { 2832 return 2; 2833 } 2834 2835 error_report("Unknown kvm-type specified '%s'", vm_type); 2836 exit(1); 2837 } 2838 2839 /* 2840 * Implementation of an interface to adjust firmware path 2841 * for the bootindex property handling. 2842 */ 2843 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2844 DeviceState *dev) 2845 { 2846 #define CAST(type, obj, name) \ 2847 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2848 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2849 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2850 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 2851 2852 if (d) { 2853 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2854 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2855 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2856 2857 if (spapr) { 2858 /* 2859 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2860 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2861 * in the top 16 bits of the 64-bit LUN 2862 */ 2863 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2864 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2865 (uint64_t)id << 48); 2866 } else if (virtio) { 2867 /* 2868 * We use SRP luns of the form 01000000 | (target << 8) | lun 2869 * in the top 32 bits of the 64-bit LUN 2870 * Note: the quote above is from SLOF and it is wrong, 2871 * the actual binding is: 2872 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2873 */ 2874 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2875 if (d->lun >= 256) { 2876 /* Use the LUN "flat space addressing method" */ 2877 id |= 0x4000; 2878 } 2879 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2880 (uint64_t)id << 32); 2881 } else if (usb) { 2882 /* 2883 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2884 * in the top 32 bits of the 64-bit LUN 2885 */ 2886 unsigned usb_port = atoi(usb->port->path); 2887 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2888 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2889 (uint64_t)id << 32); 2890 } 2891 } 2892 2893 /* 2894 * SLOF probes the USB devices, and if it recognizes that the device is a 2895 * storage device, it changes its name to "storage" instead of "usb-host", 2896 * and additionally adds a child node for the SCSI LUN, so the correct 2897 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2898 */ 2899 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2900 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2901 if (usb_host_dev_is_scsi_storage(usbdev)) { 2902 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2903 } 2904 } 2905 2906 if (phb) { 2907 /* Replace "pci" with "pci@800000020000000" */ 2908 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2909 } 2910 2911 if (vsc) { 2912 /* Same logic as virtio above */ 2913 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 2914 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 2915 } 2916 2917 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 2918 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 2919 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 2920 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 2921 } 2922 2923 return NULL; 2924 } 2925 2926 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2927 { 2928 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2929 2930 return g_strdup(spapr->kvm_type); 2931 } 2932 2933 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2934 { 2935 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2936 2937 g_free(spapr->kvm_type); 2938 spapr->kvm_type = g_strdup(value); 2939 } 2940 2941 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2942 { 2943 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2944 2945 return spapr->use_hotplug_event_source; 2946 } 2947 2948 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2949 Error **errp) 2950 { 2951 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2952 2953 spapr->use_hotplug_event_source = value; 2954 } 2955 2956 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 2957 { 2958 return true; 2959 } 2960 2961 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 2962 { 2963 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2964 2965 switch (spapr->resize_hpt) { 2966 case SPAPR_RESIZE_HPT_DEFAULT: 2967 return g_strdup("default"); 2968 case SPAPR_RESIZE_HPT_DISABLED: 2969 return g_strdup("disabled"); 2970 case SPAPR_RESIZE_HPT_ENABLED: 2971 return g_strdup("enabled"); 2972 case SPAPR_RESIZE_HPT_REQUIRED: 2973 return g_strdup("required"); 2974 } 2975 g_assert_not_reached(); 2976 } 2977 2978 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 2979 { 2980 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2981 2982 if (strcmp(value, "default") == 0) { 2983 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 2984 } else if (strcmp(value, "disabled") == 0) { 2985 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2986 } else if (strcmp(value, "enabled") == 0) { 2987 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 2988 } else if (strcmp(value, "required") == 0) { 2989 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 2990 } else { 2991 error_setg(errp, "Bad value for \"resize-hpt\" property"); 2992 } 2993 } 2994 2995 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 2996 void *opaque, Error **errp) 2997 { 2998 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 2999 } 3000 3001 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3002 void *opaque, Error **errp) 3003 { 3004 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3005 } 3006 3007 static void spapr_instance_init(Object *obj) 3008 { 3009 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3010 3011 spapr->htab_fd = -1; 3012 spapr->use_hotplug_event_source = true; 3013 object_property_add_str(obj, "kvm-type", 3014 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3015 object_property_set_description(obj, "kvm-type", 3016 "Specifies the KVM virtualization mode (HV, PR)", 3017 NULL); 3018 object_property_add_bool(obj, "modern-hotplug-events", 3019 spapr_get_modern_hotplug_events, 3020 spapr_set_modern_hotplug_events, 3021 NULL); 3022 object_property_set_description(obj, "modern-hotplug-events", 3023 "Use dedicated hotplug event mechanism in" 3024 " place of standard EPOW events when possible" 3025 " (required for memory hot-unplug support)", 3026 NULL); 3027 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3028 "Maximum permitted CPU compatibility mode", 3029 &error_fatal); 3030 3031 object_property_add_str(obj, "resize-hpt", 3032 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3033 object_property_set_description(obj, "resize-hpt", 3034 "Resizing of the Hash Page Table (enabled, disabled, required)", 3035 NULL); 3036 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3037 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3038 object_property_set_description(obj, "vsmt", 3039 "Virtual SMT: KVM behaves as if this were" 3040 " the host's SMT mode", &error_abort); 3041 object_property_add_bool(obj, "vfio-no-msix-emulation", 3042 spapr_get_msix_emulation, NULL, NULL); 3043 } 3044 3045 static void spapr_machine_finalizefn(Object *obj) 3046 { 3047 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3048 3049 g_free(spapr->kvm_type); 3050 } 3051 3052 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3053 { 3054 cpu_synchronize_state(cs); 3055 ppc_cpu_do_system_reset(cs); 3056 } 3057 3058 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3059 { 3060 CPUState *cs; 3061 3062 CPU_FOREACH(cs) { 3063 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3064 } 3065 } 3066 3067 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3068 uint32_t node, bool dedicated_hp_event_source, 3069 Error **errp) 3070 { 3071 sPAPRDRConnector *drc; 3072 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3073 int i, fdt_offset, fdt_size; 3074 void *fdt; 3075 uint64_t addr = addr_start; 3076 bool hotplugged = spapr_drc_hotplugged(dev); 3077 Error *local_err = NULL; 3078 3079 for (i = 0; i < nr_lmbs; i++) { 3080 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3081 addr / SPAPR_MEMORY_BLOCK_SIZE); 3082 g_assert(drc); 3083 3084 fdt = create_device_tree(&fdt_size); 3085 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 3086 SPAPR_MEMORY_BLOCK_SIZE); 3087 3088 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3089 if (local_err) { 3090 while (addr > addr_start) { 3091 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3092 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3093 addr / SPAPR_MEMORY_BLOCK_SIZE); 3094 spapr_drc_detach(drc); 3095 } 3096 g_free(fdt); 3097 error_propagate(errp, local_err); 3098 return; 3099 } 3100 if (!hotplugged) { 3101 spapr_drc_reset(drc); 3102 } 3103 addr += SPAPR_MEMORY_BLOCK_SIZE; 3104 } 3105 /* send hotplug notification to the 3106 * guest only in case of hotplugged memory 3107 */ 3108 if (hotplugged) { 3109 if (dedicated_hp_event_source) { 3110 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3111 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3112 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3113 nr_lmbs, 3114 spapr_drc_index(drc)); 3115 } else { 3116 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3117 nr_lmbs); 3118 } 3119 } 3120 } 3121 3122 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3123 Error **errp) 3124 { 3125 Error *local_err = NULL; 3126 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3127 PCDIMMDevice *dimm = PC_DIMM(dev); 3128 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3129 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3130 uint64_t size, addr; 3131 uint32_t node; 3132 3133 size = memory_region_size(mr); 3134 3135 pc_dimm_plug(dev, MACHINE(ms), &local_err); 3136 if (local_err) { 3137 goto out; 3138 } 3139 3140 addr = object_property_get_uint(OBJECT(dimm), 3141 PC_DIMM_ADDR_PROP, &local_err); 3142 if (local_err) { 3143 goto out_unplug; 3144 } 3145 3146 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, 3147 &error_abort); 3148 spapr_add_lmbs(dev, addr, size, node, 3149 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3150 &local_err); 3151 if (local_err) { 3152 goto out_unplug; 3153 } 3154 3155 return; 3156 3157 out_unplug: 3158 pc_dimm_unplug(dev, MACHINE(ms)); 3159 out: 3160 error_propagate(errp, local_err); 3161 } 3162 3163 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3164 Error **errp) 3165 { 3166 const sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3167 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3168 PCDIMMDevice *dimm = PC_DIMM(dev); 3169 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3170 Error *local_err = NULL; 3171 MemoryRegion *mr; 3172 uint64_t size; 3173 Object *memdev; 3174 hwaddr pagesize; 3175 3176 if (!smc->dr_lmb_enabled) { 3177 error_setg(errp, "Memory hotplug not supported for this machine"); 3178 return; 3179 } 3180 3181 mr = ddc->get_memory_region(dimm, errp); 3182 if (!mr) { 3183 return; 3184 } 3185 size = memory_region_size(mr); 3186 3187 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3188 error_setg(errp, "Hotplugged memory size must be a multiple of " 3189 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3190 return; 3191 } 3192 3193 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3194 &error_abort); 3195 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3196 spapr_check_pagesize(spapr, pagesize, &local_err); 3197 if (local_err) { 3198 error_propagate(errp, local_err); 3199 return; 3200 } 3201 3202 pc_dimm_pre_plug(dev, MACHINE(hotplug_dev), NULL, errp); 3203 } 3204 3205 struct sPAPRDIMMState { 3206 PCDIMMDevice *dimm; 3207 uint32_t nr_lmbs; 3208 QTAILQ_ENTRY(sPAPRDIMMState) next; 3209 }; 3210 3211 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 3212 PCDIMMDevice *dimm) 3213 { 3214 sPAPRDIMMState *dimm_state = NULL; 3215 3216 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3217 if (dimm_state->dimm == dimm) { 3218 break; 3219 } 3220 } 3221 return dimm_state; 3222 } 3223 3224 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 3225 uint32_t nr_lmbs, 3226 PCDIMMDevice *dimm) 3227 { 3228 sPAPRDIMMState *ds = NULL; 3229 3230 /* 3231 * If this request is for a DIMM whose removal had failed earlier 3232 * (due to guest's refusal to remove the LMBs), we would have this 3233 * dimm already in the pending_dimm_unplugs list. In that 3234 * case don't add again. 3235 */ 3236 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3237 if (!ds) { 3238 ds = g_malloc0(sizeof(sPAPRDIMMState)); 3239 ds->nr_lmbs = nr_lmbs; 3240 ds->dimm = dimm; 3241 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3242 } 3243 return ds; 3244 } 3245 3246 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 3247 sPAPRDIMMState *dimm_state) 3248 { 3249 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3250 g_free(dimm_state); 3251 } 3252 3253 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 3254 PCDIMMDevice *dimm) 3255 { 3256 sPAPRDRConnector *drc; 3257 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3258 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3259 uint64_t size = memory_region_size(mr); 3260 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3261 uint32_t avail_lmbs = 0; 3262 uint64_t addr_start, addr; 3263 int i; 3264 3265 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3266 &error_abort); 3267 3268 addr = addr_start; 3269 for (i = 0; i < nr_lmbs; i++) { 3270 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3271 addr / SPAPR_MEMORY_BLOCK_SIZE); 3272 g_assert(drc); 3273 if (drc->dev) { 3274 avail_lmbs++; 3275 } 3276 addr += SPAPR_MEMORY_BLOCK_SIZE; 3277 } 3278 3279 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3280 } 3281 3282 /* Callback to be called during DRC release. */ 3283 void spapr_lmb_release(DeviceState *dev) 3284 { 3285 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3286 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3287 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3288 3289 /* This information will get lost if a migration occurs 3290 * during the unplug process. In this case recover it. */ 3291 if (ds == NULL) { 3292 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3293 g_assert(ds); 3294 /* The DRC being examined by the caller at least must be counted */ 3295 g_assert(ds->nr_lmbs); 3296 } 3297 3298 if (--ds->nr_lmbs) { 3299 return; 3300 } 3301 3302 /* 3303 * Now that all the LMBs have been removed by the guest, call the 3304 * unplug handler chain. This can never fail. 3305 */ 3306 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3307 } 3308 3309 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3310 { 3311 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3312 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3313 3314 pc_dimm_unplug(dev, MACHINE(hotplug_dev)); 3315 object_unparent(OBJECT(dev)); 3316 spapr_pending_dimm_unplugs_remove(spapr, ds); 3317 } 3318 3319 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3320 DeviceState *dev, Error **errp) 3321 { 3322 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3323 Error *local_err = NULL; 3324 PCDIMMDevice *dimm = PC_DIMM(dev); 3325 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3326 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3327 uint32_t nr_lmbs; 3328 uint64_t size, addr_start, addr; 3329 int i; 3330 sPAPRDRConnector *drc; 3331 3332 size = memory_region_size(mr); 3333 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3334 3335 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3336 &local_err); 3337 if (local_err) { 3338 goto out; 3339 } 3340 3341 /* 3342 * An existing pending dimm state for this DIMM means that there is an 3343 * unplug operation in progress, waiting for the spapr_lmb_release 3344 * callback to complete the job (BQL can't cover that far). In this case, 3345 * bail out to avoid detaching DRCs that were already released. 3346 */ 3347 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3348 error_setg(&local_err, 3349 "Memory unplug already in progress for device %s", 3350 dev->id); 3351 goto out; 3352 } 3353 3354 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3355 3356 addr = addr_start; 3357 for (i = 0; i < nr_lmbs; i++) { 3358 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3359 addr / SPAPR_MEMORY_BLOCK_SIZE); 3360 g_assert(drc); 3361 3362 spapr_drc_detach(drc); 3363 addr += SPAPR_MEMORY_BLOCK_SIZE; 3364 } 3365 3366 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3367 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3368 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3369 nr_lmbs, spapr_drc_index(drc)); 3370 out: 3371 error_propagate(errp, local_err); 3372 } 3373 3374 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 3375 sPAPRMachineState *spapr) 3376 { 3377 PowerPCCPU *cpu = POWERPC_CPU(cs); 3378 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3379 int id = spapr_get_vcpu_id(cpu); 3380 void *fdt; 3381 int offset, fdt_size; 3382 char *nodename; 3383 3384 fdt = create_device_tree(&fdt_size); 3385 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3386 offset = fdt_add_subnode(fdt, 0, nodename); 3387 3388 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3389 g_free(nodename); 3390 3391 *fdt_offset = offset; 3392 return fdt; 3393 } 3394 3395 /* Callback to be called during DRC release. */ 3396 void spapr_core_release(DeviceState *dev) 3397 { 3398 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3399 3400 /* Call the unplug handler chain. This can never fail. */ 3401 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3402 } 3403 3404 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3405 { 3406 MachineState *ms = MACHINE(hotplug_dev); 3407 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3408 CPUCore *cc = CPU_CORE(dev); 3409 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3410 3411 if (smc->pre_2_10_has_unused_icps) { 3412 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3413 int i; 3414 3415 for (i = 0; i < cc->nr_threads; i++) { 3416 CPUState *cs = CPU(sc->threads[i]); 3417 3418 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3419 } 3420 } 3421 3422 assert(core_slot); 3423 core_slot->cpu = NULL; 3424 object_unparent(OBJECT(dev)); 3425 } 3426 3427 static 3428 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3429 Error **errp) 3430 { 3431 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3432 int index; 3433 sPAPRDRConnector *drc; 3434 CPUCore *cc = CPU_CORE(dev); 3435 3436 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3437 error_setg(errp, "Unable to find CPU core with core-id: %d", 3438 cc->core_id); 3439 return; 3440 } 3441 if (index == 0) { 3442 error_setg(errp, "Boot CPU core may not be unplugged"); 3443 return; 3444 } 3445 3446 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3447 spapr_vcpu_id(spapr, cc->core_id)); 3448 g_assert(drc); 3449 3450 spapr_drc_detach(drc); 3451 3452 spapr_hotplug_req_remove_by_index(drc); 3453 } 3454 3455 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3456 Error **errp) 3457 { 3458 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3459 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3460 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3461 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3462 CPUCore *cc = CPU_CORE(dev); 3463 CPUState *cs = CPU(core->threads[0]); 3464 sPAPRDRConnector *drc; 3465 Error *local_err = NULL; 3466 CPUArchId *core_slot; 3467 int index; 3468 bool hotplugged = spapr_drc_hotplugged(dev); 3469 3470 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3471 if (!core_slot) { 3472 error_setg(errp, "Unable to find CPU core with core-id: %d", 3473 cc->core_id); 3474 return; 3475 } 3476 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3477 spapr_vcpu_id(spapr, cc->core_id)); 3478 3479 g_assert(drc || !mc->has_hotpluggable_cpus); 3480 3481 if (drc) { 3482 void *fdt; 3483 int fdt_offset; 3484 3485 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 3486 3487 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3488 if (local_err) { 3489 g_free(fdt); 3490 error_propagate(errp, local_err); 3491 return; 3492 } 3493 3494 if (hotplugged) { 3495 /* 3496 * Send hotplug notification interrupt to the guest only 3497 * in case of hotplugged CPUs. 3498 */ 3499 spapr_hotplug_req_add_by_index(drc); 3500 } else { 3501 spapr_drc_reset(drc); 3502 } 3503 } 3504 3505 core_slot->cpu = OBJECT(dev); 3506 3507 if (smc->pre_2_10_has_unused_icps) { 3508 int i; 3509 3510 for (i = 0; i < cc->nr_threads; i++) { 3511 cs = CPU(core->threads[i]); 3512 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3513 } 3514 } 3515 } 3516 3517 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3518 Error **errp) 3519 { 3520 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3521 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3522 Error *local_err = NULL; 3523 CPUCore *cc = CPU_CORE(dev); 3524 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3525 const char *type = object_get_typename(OBJECT(dev)); 3526 CPUArchId *core_slot; 3527 int index; 3528 3529 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3530 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3531 goto out; 3532 } 3533 3534 if (strcmp(base_core_type, type)) { 3535 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3536 goto out; 3537 } 3538 3539 if (cc->core_id % smp_threads) { 3540 error_setg(&local_err, "invalid core id %d", cc->core_id); 3541 goto out; 3542 } 3543 3544 /* 3545 * In general we should have homogeneous threads-per-core, but old 3546 * (pre hotplug support) machine types allow the last core to have 3547 * reduced threads as a compatibility hack for when we allowed 3548 * total vcpus not a multiple of threads-per-core. 3549 */ 3550 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3551 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3552 cc->nr_threads, smp_threads); 3553 goto out; 3554 } 3555 3556 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3557 if (!core_slot) { 3558 error_setg(&local_err, "core id %d out of range", cc->core_id); 3559 goto out; 3560 } 3561 3562 if (core_slot->cpu) { 3563 error_setg(&local_err, "core %d already populated", cc->core_id); 3564 goto out; 3565 } 3566 3567 numa_cpu_pre_plug(core_slot, dev, &local_err); 3568 3569 out: 3570 error_propagate(errp, local_err); 3571 } 3572 3573 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3574 DeviceState *dev, Error **errp) 3575 { 3576 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3577 spapr_memory_plug(hotplug_dev, dev, errp); 3578 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3579 spapr_core_plug(hotplug_dev, dev, errp); 3580 } 3581 } 3582 3583 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 3584 DeviceState *dev, Error **errp) 3585 { 3586 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3587 spapr_memory_unplug(hotplug_dev, dev); 3588 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3589 spapr_core_unplug(hotplug_dev, dev); 3590 } 3591 } 3592 3593 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3594 DeviceState *dev, Error **errp) 3595 { 3596 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3597 MachineClass *mc = MACHINE_GET_CLASS(sms); 3598 3599 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3600 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3601 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3602 } else { 3603 /* NOTE: this means there is a window after guest reset, prior to 3604 * CAS negotiation, where unplug requests will fail due to the 3605 * capability not being detected yet. This is a bit different than 3606 * the case with PCI unplug, where the events will be queued and 3607 * eventually handled by the guest after boot 3608 */ 3609 error_setg(errp, "Memory hot unplug not supported for this guest"); 3610 } 3611 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3612 if (!mc->has_hotpluggable_cpus) { 3613 error_setg(errp, "CPU hot unplug not supported on this machine"); 3614 return; 3615 } 3616 spapr_core_unplug_request(hotplug_dev, dev, errp); 3617 } 3618 } 3619 3620 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3621 DeviceState *dev, Error **errp) 3622 { 3623 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3624 spapr_memory_pre_plug(hotplug_dev, dev, errp); 3625 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3626 spapr_core_pre_plug(hotplug_dev, dev, errp); 3627 } 3628 } 3629 3630 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3631 DeviceState *dev) 3632 { 3633 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3634 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3635 return HOTPLUG_HANDLER(machine); 3636 } 3637 return NULL; 3638 } 3639 3640 static CpuInstanceProperties 3641 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3642 { 3643 CPUArchId *core_slot; 3644 MachineClass *mc = MACHINE_GET_CLASS(machine); 3645 3646 /* make sure possible_cpu are intialized */ 3647 mc->possible_cpu_arch_ids(machine); 3648 /* get CPU core slot containing thread that matches cpu_index */ 3649 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3650 assert(core_slot); 3651 return core_slot->props; 3652 } 3653 3654 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 3655 { 3656 return idx / smp_cores % nb_numa_nodes; 3657 } 3658 3659 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3660 { 3661 int i; 3662 const char *core_type; 3663 int spapr_max_cores = max_cpus / smp_threads; 3664 MachineClass *mc = MACHINE_GET_CLASS(machine); 3665 3666 if (!mc->has_hotpluggable_cpus) { 3667 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3668 } 3669 if (machine->possible_cpus) { 3670 assert(machine->possible_cpus->len == spapr_max_cores); 3671 return machine->possible_cpus; 3672 } 3673 3674 core_type = spapr_get_cpu_core_type(machine->cpu_type); 3675 if (!core_type) { 3676 error_report("Unable to find sPAPR CPU Core definition"); 3677 exit(1); 3678 } 3679 3680 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3681 sizeof(CPUArchId) * spapr_max_cores); 3682 machine->possible_cpus->len = spapr_max_cores; 3683 for (i = 0; i < machine->possible_cpus->len; i++) { 3684 int core_id = i * smp_threads; 3685 3686 machine->possible_cpus->cpus[i].type = core_type; 3687 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3688 machine->possible_cpus->cpus[i].arch_id = core_id; 3689 machine->possible_cpus->cpus[i].props.has_core_id = true; 3690 machine->possible_cpus->cpus[i].props.core_id = core_id; 3691 } 3692 return machine->possible_cpus; 3693 } 3694 3695 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3696 uint64_t *buid, hwaddr *pio, 3697 hwaddr *mmio32, hwaddr *mmio64, 3698 unsigned n_dma, uint32_t *liobns, Error **errp) 3699 { 3700 /* 3701 * New-style PHB window placement. 3702 * 3703 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3704 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3705 * windows. 3706 * 3707 * Some guest kernels can't work with MMIO windows above 1<<46 3708 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3709 * 3710 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3711 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3712 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3713 * 1TiB 64-bit MMIO windows for each PHB. 3714 */ 3715 const uint64_t base_buid = 0x800000020000000ULL; 3716 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3717 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3718 int i; 3719 3720 /* Sanity check natural alignments */ 3721 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3722 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3723 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3724 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3725 /* Sanity check bounds */ 3726 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3727 SPAPR_PCI_MEM32_WIN_SIZE); 3728 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3729 SPAPR_PCI_MEM64_WIN_SIZE); 3730 3731 if (index >= SPAPR_MAX_PHBS) { 3732 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3733 SPAPR_MAX_PHBS - 1); 3734 return; 3735 } 3736 3737 *buid = base_buid + index; 3738 for (i = 0; i < n_dma; ++i) { 3739 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3740 } 3741 3742 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3743 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3744 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3745 } 3746 3747 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3748 { 3749 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3750 3751 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3752 } 3753 3754 static void spapr_ics_resend(XICSFabric *dev) 3755 { 3756 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3757 3758 ics_resend(spapr->ics); 3759 } 3760 3761 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 3762 { 3763 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 3764 3765 return cpu ? ICP(cpu->intc) : NULL; 3766 } 3767 3768 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3769 Monitor *mon) 3770 { 3771 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3772 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3773 3774 smc->irq->print_info(spapr, mon); 3775 } 3776 3777 int spapr_get_vcpu_id(PowerPCCPU *cpu) 3778 { 3779 return cpu->vcpu_id; 3780 } 3781 3782 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 3783 { 3784 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3785 int vcpu_id; 3786 3787 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 3788 3789 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 3790 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 3791 error_append_hint(errp, "Adjust the number of cpus to %d " 3792 "or try to raise the number of threads per core\n", 3793 vcpu_id * smp_threads / spapr->vsmt); 3794 return; 3795 } 3796 3797 cpu->vcpu_id = vcpu_id; 3798 } 3799 3800 PowerPCCPU *spapr_find_cpu(int vcpu_id) 3801 { 3802 CPUState *cs; 3803 3804 CPU_FOREACH(cs) { 3805 PowerPCCPU *cpu = POWERPC_CPU(cs); 3806 3807 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 3808 return cpu; 3809 } 3810 } 3811 3812 return NULL; 3813 } 3814 3815 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3816 { 3817 MachineClass *mc = MACHINE_CLASS(oc); 3818 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3819 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3820 NMIClass *nc = NMI_CLASS(oc); 3821 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3822 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3823 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3824 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3825 3826 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3827 mc->ignore_boot_device_suffixes = true; 3828 3829 /* 3830 * We set up the default / latest behaviour here. The class_init 3831 * functions for the specific versioned machine types can override 3832 * these details for backwards compatibility 3833 */ 3834 mc->init = spapr_machine_init; 3835 mc->reset = spapr_machine_reset; 3836 mc->block_default_type = IF_SCSI; 3837 mc->max_cpus = 1024; 3838 mc->no_parallel = 1; 3839 mc->default_boot_order = ""; 3840 mc->default_ram_size = 512 * MiB; 3841 mc->default_display = "std"; 3842 mc->kvm_type = spapr_kvm_type; 3843 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 3844 mc->pci_allow_0_address = true; 3845 assert(!mc->get_hotplug_handler); 3846 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3847 hc->pre_plug = spapr_machine_device_pre_plug; 3848 hc->plug = spapr_machine_device_plug; 3849 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 3850 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 3851 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3852 hc->unplug_request = spapr_machine_device_unplug_request; 3853 hc->unplug = spapr_machine_device_unplug; 3854 3855 smc->dr_lmb_enabled = true; 3856 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 3857 mc->has_hotpluggable_cpus = true; 3858 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 3859 fwc->get_dev_path = spapr_get_fw_dev_path; 3860 nc->nmi_monitor_handler = spapr_nmi; 3861 smc->phb_placement = spapr_phb_placement; 3862 vhc->hypercall = emulate_spapr_hypercall; 3863 vhc->hpt_mask = spapr_hpt_mask; 3864 vhc->map_hptes = spapr_map_hptes; 3865 vhc->unmap_hptes = spapr_unmap_hptes; 3866 vhc->store_hpte = spapr_store_hpte; 3867 vhc->get_patbe = spapr_get_patbe; 3868 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 3869 xic->ics_get = spapr_ics_get; 3870 xic->ics_resend = spapr_ics_resend; 3871 xic->icp_get = spapr_icp_get; 3872 ispc->print_info = spapr_pic_print_info; 3873 /* Force NUMA node memory size to be a multiple of 3874 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 3875 * in which LMBs are represented and hot-added 3876 */ 3877 mc->numa_mem_align_shift = 28; 3878 3879 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 3880 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 3881 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 3882 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 3883 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 3884 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 3885 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 3886 spapr_caps_add_properties(smc, &error_abort); 3887 smc->irq = &spapr_irq_xics; 3888 } 3889 3890 static const TypeInfo spapr_machine_info = { 3891 .name = TYPE_SPAPR_MACHINE, 3892 .parent = TYPE_MACHINE, 3893 .abstract = true, 3894 .instance_size = sizeof(sPAPRMachineState), 3895 .instance_init = spapr_instance_init, 3896 .instance_finalize = spapr_machine_finalizefn, 3897 .class_size = sizeof(sPAPRMachineClass), 3898 .class_init = spapr_machine_class_init, 3899 .interfaces = (InterfaceInfo[]) { 3900 { TYPE_FW_PATH_PROVIDER }, 3901 { TYPE_NMI }, 3902 { TYPE_HOTPLUG_HANDLER }, 3903 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3904 { TYPE_XICS_FABRIC }, 3905 { TYPE_INTERRUPT_STATS_PROVIDER }, 3906 { } 3907 }, 3908 }; 3909 3910 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3911 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3912 void *data) \ 3913 { \ 3914 MachineClass *mc = MACHINE_CLASS(oc); \ 3915 spapr_machine_##suffix##_class_options(mc); \ 3916 if (latest) { \ 3917 mc->alias = "pseries"; \ 3918 mc->is_default = 1; \ 3919 } \ 3920 } \ 3921 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3922 { \ 3923 MachineState *machine = MACHINE(obj); \ 3924 spapr_machine_##suffix##_instance_options(machine); \ 3925 } \ 3926 static const TypeInfo spapr_machine_##suffix##_info = { \ 3927 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3928 .parent = TYPE_SPAPR_MACHINE, \ 3929 .class_init = spapr_machine_##suffix##_class_init, \ 3930 .instance_init = spapr_machine_##suffix##_instance_init, \ 3931 }; \ 3932 static void spapr_machine_register_##suffix(void) \ 3933 { \ 3934 type_register(&spapr_machine_##suffix##_info); \ 3935 } \ 3936 type_init(spapr_machine_register_##suffix) 3937 3938 /* 3939 * pseries-3.1 3940 */ 3941 static void spapr_machine_3_1_instance_options(MachineState *machine) 3942 { 3943 } 3944 3945 static void spapr_machine_3_1_class_options(MachineClass *mc) 3946 { 3947 /* Defaults for the latest behaviour inherited from the base class */ 3948 } 3949 3950 DEFINE_SPAPR_MACHINE(3_1, "3.1", true); 3951 3952 /* 3953 * pseries-3.0 3954 */ 3955 #define SPAPR_COMPAT_3_0 \ 3956 HW_COMPAT_3_0 3957 3958 static void spapr_machine_3_0_instance_options(MachineState *machine) 3959 { 3960 spapr_machine_3_1_instance_options(machine); 3961 } 3962 3963 static void spapr_machine_3_0_class_options(MachineClass *mc) 3964 { 3965 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3966 3967 spapr_machine_3_1_class_options(mc); 3968 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_3_0); 3969 3970 smc->legacy_irq_allocation = true; 3971 } 3972 3973 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 3974 3975 /* 3976 * pseries-2.12 3977 */ 3978 #define SPAPR_COMPAT_2_12 \ 3979 HW_COMPAT_2_12 \ 3980 { \ 3981 .driver = TYPE_POWERPC_CPU, \ 3982 .property = "pre-3.0-migration", \ 3983 .value = "on", \ 3984 }, \ 3985 { \ 3986 .driver = TYPE_SPAPR_CPU_CORE, \ 3987 .property = "pre-3.0-migration", \ 3988 .value = "on", \ 3989 }, 3990 3991 static void spapr_machine_2_12_instance_options(MachineState *machine) 3992 { 3993 spapr_machine_3_0_instance_options(machine); 3994 } 3995 3996 static void spapr_machine_2_12_class_options(MachineClass *mc) 3997 { 3998 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3999 4000 spapr_machine_3_0_class_options(mc); 4001 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_12); 4002 4003 /* We depend on kvm_enabled() to choose a default value for the 4004 * hpt-max-page-size capability. Of course we can't do it here 4005 * because this is too early and the HW accelerator isn't initialzed 4006 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4007 */ 4008 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4009 } 4010 4011 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4012 4013 static void spapr_machine_2_12_sxxm_instance_options(MachineState *machine) 4014 { 4015 spapr_machine_2_12_instance_options(machine); 4016 } 4017 4018 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4019 { 4020 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4021 4022 spapr_machine_2_12_class_options(mc); 4023 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4024 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4025 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4026 } 4027 4028 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4029 4030 /* 4031 * pseries-2.11 4032 */ 4033 #define SPAPR_COMPAT_2_11 \ 4034 HW_COMPAT_2_11 4035 4036 static void spapr_machine_2_11_instance_options(MachineState *machine) 4037 { 4038 spapr_machine_2_12_instance_options(machine); 4039 } 4040 4041 static void spapr_machine_2_11_class_options(MachineClass *mc) 4042 { 4043 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4044 4045 spapr_machine_2_12_class_options(mc); 4046 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4047 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11); 4048 } 4049 4050 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4051 4052 /* 4053 * pseries-2.10 4054 */ 4055 #define SPAPR_COMPAT_2_10 \ 4056 HW_COMPAT_2_10 4057 4058 static void spapr_machine_2_10_instance_options(MachineState *machine) 4059 { 4060 spapr_machine_2_11_instance_options(machine); 4061 } 4062 4063 static void spapr_machine_2_10_class_options(MachineClass *mc) 4064 { 4065 spapr_machine_2_11_class_options(mc); 4066 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10); 4067 } 4068 4069 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4070 4071 /* 4072 * pseries-2.9 4073 */ 4074 #define SPAPR_COMPAT_2_9 \ 4075 HW_COMPAT_2_9 \ 4076 { \ 4077 .driver = TYPE_POWERPC_CPU, \ 4078 .property = "pre-2.10-migration", \ 4079 .value = "on", \ 4080 }, \ 4081 4082 static void spapr_machine_2_9_instance_options(MachineState *machine) 4083 { 4084 spapr_machine_2_10_instance_options(machine); 4085 } 4086 4087 static void spapr_machine_2_9_class_options(MachineClass *mc) 4088 { 4089 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4090 4091 spapr_machine_2_10_class_options(mc); 4092 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); 4093 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4094 smc->pre_2_10_has_unused_icps = true; 4095 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4096 } 4097 4098 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4099 4100 /* 4101 * pseries-2.8 4102 */ 4103 #define SPAPR_COMPAT_2_8 \ 4104 HW_COMPAT_2_8 \ 4105 { \ 4106 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4107 .property = "pcie-extended-configuration-space", \ 4108 .value = "off", \ 4109 }, 4110 4111 static void spapr_machine_2_8_instance_options(MachineState *machine) 4112 { 4113 spapr_machine_2_9_instance_options(machine); 4114 } 4115 4116 static void spapr_machine_2_8_class_options(MachineClass *mc) 4117 { 4118 spapr_machine_2_9_class_options(mc); 4119 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 4120 mc->numa_mem_align_shift = 23; 4121 } 4122 4123 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4124 4125 /* 4126 * pseries-2.7 4127 */ 4128 #define SPAPR_COMPAT_2_7 \ 4129 HW_COMPAT_2_7 \ 4130 { \ 4131 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4132 .property = "mem_win_size", \ 4133 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 4134 }, \ 4135 { \ 4136 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4137 .property = "mem64_win_size", \ 4138 .value = "0", \ 4139 }, \ 4140 { \ 4141 .driver = TYPE_POWERPC_CPU, \ 4142 .property = "pre-2.8-migration", \ 4143 .value = "on", \ 4144 }, \ 4145 { \ 4146 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4147 .property = "pre-2.8-migration", \ 4148 .value = "on", \ 4149 }, 4150 4151 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 4152 uint64_t *buid, hwaddr *pio, 4153 hwaddr *mmio32, hwaddr *mmio64, 4154 unsigned n_dma, uint32_t *liobns, Error **errp) 4155 { 4156 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4157 const uint64_t base_buid = 0x800000020000000ULL; 4158 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4159 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4160 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4161 const uint32_t max_index = 255; 4162 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4163 4164 uint64_t ram_top = MACHINE(spapr)->ram_size; 4165 hwaddr phb0_base, phb_base; 4166 int i; 4167 4168 /* Do we have device memory? */ 4169 if (MACHINE(spapr)->maxram_size > ram_top) { 4170 /* Can't just use maxram_size, because there may be an 4171 * alignment gap between normal and device memory regions 4172 */ 4173 ram_top = MACHINE(spapr)->device_memory->base + 4174 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4175 } 4176 4177 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4178 4179 if (index > max_index) { 4180 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4181 max_index); 4182 return; 4183 } 4184 4185 *buid = base_buid + index; 4186 for (i = 0; i < n_dma; ++i) { 4187 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4188 } 4189 4190 phb_base = phb0_base + index * phb_spacing; 4191 *pio = phb_base + pio_offset; 4192 *mmio32 = phb_base + mmio_offset; 4193 /* 4194 * We don't set the 64-bit MMIO window, relying on the PHB's 4195 * fallback behaviour of automatically splitting a large "32-bit" 4196 * window into contiguous 32-bit and 64-bit windows 4197 */ 4198 } 4199 4200 static void spapr_machine_2_7_instance_options(MachineState *machine) 4201 { 4202 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 4203 4204 spapr_machine_2_8_instance_options(machine); 4205 spapr->use_hotplug_event_source = false; 4206 } 4207 4208 static void spapr_machine_2_7_class_options(MachineClass *mc) 4209 { 4210 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4211 4212 spapr_machine_2_8_class_options(mc); 4213 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4214 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 4215 smc->phb_placement = phb_placement_2_7; 4216 } 4217 4218 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4219 4220 /* 4221 * pseries-2.6 4222 */ 4223 #define SPAPR_COMPAT_2_6 \ 4224 HW_COMPAT_2_6 \ 4225 { \ 4226 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 4227 .property = "ddw",\ 4228 .value = stringify(off),\ 4229 }, 4230 4231 static void spapr_machine_2_6_instance_options(MachineState *machine) 4232 { 4233 spapr_machine_2_7_instance_options(machine); 4234 } 4235 4236 static void spapr_machine_2_6_class_options(MachineClass *mc) 4237 { 4238 spapr_machine_2_7_class_options(mc); 4239 mc->has_hotpluggable_cpus = false; 4240 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 4241 } 4242 4243 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4244 4245 /* 4246 * pseries-2.5 4247 */ 4248 #define SPAPR_COMPAT_2_5 \ 4249 HW_COMPAT_2_5 \ 4250 { \ 4251 .driver = "spapr-vlan", \ 4252 .property = "use-rx-buffer-pools", \ 4253 .value = "off", \ 4254 }, 4255 4256 static void spapr_machine_2_5_instance_options(MachineState *machine) 4257 { 4258 spapr_machine_2_6_instance_options(machine); 4259 } 4260 4261 static void spapr_machine_2_5_class_options(MachineClass *mc) 4262 { 4263 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4264 4265 spapr_machine_2_6_class_options(mc); 4266 smc->use_ohci_by_default = true; 4267 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 4268 } 4269 4270 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4271 4272 /* 4273 * pseries-2.4 4274 */ 4275 #define SPAPR_COMPAT_2_4 \ 4276 HW_COMPAT_2_4 4277 4278 static void spapr_machine_2_4_instance_options(MachineState *machine) 4279 { 4280 spapr_machine_2_5_instance_options(machine); 4281 } 4282 4283 static void spapr_machine_2_4_class_options(MachineClass *mc) 4284 { 4285 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4286 4287 spapr_machine_2_5_class_options(mc); 4288 smc->dr_lmb_enabled = false; 4289 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 4290 } 4291 4292 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4293 4294 /* 4295 * pseries-2.3 4296 */ 4297 #define SPAPR_COMPAT_2_3 \ 4298 HW_COMPAT_2_3 \ 4299 {\ 4300 .driver = "spapr-pci-host-bridge",\ 4301 .property = "dynamic-reconfiguration",\ 4302 .value = "off",\ 4303 }, 4304 4305 static void spapr_machine_2_3_instance_options(MachineState *machine) 4306 { 4307 spapr_machine_2_4_instance_options(machine); 4308 } 4309 4310 static void spapr_machine_2_3_class_options(MachineClass *mc) 4311 { 4312 spapr_machine_2_4_class_options(mc); 4313 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 4314 } 4315 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4316 4317 /* 4318 * pseries-2.2 4319 */ 4320 4321 #define SPAPR_COMPAT_2_2 \ 4322 HW_COMPAT_2_2 \ 4323 {\ 4324 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 4325 .property = "mem_win_size",\ 4326 .value = "0x20000000",\ 4327 }, 4328 4329 static void spapr_machine_2_2_instance_options(MachineState *machine) 4330 { 4331 spapr_machine_2_3_instance_options(machine); 4332 machine->suppress_vmdesc = true; 4333 } 4334 4335 static void spapr_machine_2_2_class_options(MachineClass *mc) 4336 { 4337 spapr_machine_2_3_class_options(mc); 4338 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 4339 } 4340 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4341 4342 /* 4343 * pseries-2.1 4344 */ 4345 #define SPAPR_COMPAT_2_1 \ 4346 HW_COMPAT_2_1 4347 4348 static void spapr_machine_2_1_instance_options(MachineState *machine) 4349 { 4350 spapr_machine_2_2_instance_options(machine); 4351 } 4352 4353 static void spapr_machine_2_1_class_options(MachineClass *mc) 4354 { 4355 spapr_machine_2_2_class_options(mc); 4356 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 4357 } 4358 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4359 4360 static void spapr_machine_register_types(void) 4361 { 4362 type_register_static(&spapr_machine_info); 4363 } 4364 4365 type_init(spapr_machine_register_types) 4366