1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qapi/error.h" 30 #include "qapi/visitor.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/hostmem.h" 33 #include "sysemu/numa.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/runstate.h" 37 #include "qemu/log.h" 38 #include "hw/fw-path-provider.h" 39 #include "elf.h" 40 #include "net/net.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/cpus.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_ppc.h" 45 #include "migration/misc.h" 46 #include "migration/qemu-file-types.h" 47 #include "migration/global_state.h" 48 #include "migration/register.h" 49 #include "mmu-hash64.h" 50 #include "mmu-book3s-v3.h" 51 #include "cpu-models.h" 52 #include "hw/core/cpu.h" 53 54 #include "hw/boards.h" 55 #include "hw/ppc/ppc.h" 56 #include "hw/loader.h" 57 58 #include "hw/ppc/fdt.h" 59 #include "hw/ppc/spapr.h" 60 #include "hw/ppc/spapr_vio.h" 61 #include "hw/qdev-properties.h" 62 #include "hw/pci-host/spapr.h" 63 #include "hw/pci/msi.h" 64 65 #include "hw/pci/pci.h" 66 #include "hw/scsi/scsi.h" 67 #include "hw/virtio/virtio-scsi.h" 68 #include "hw/virtio/vhost-scsi-common.h" 69 70 #include "exec/address-spaces.h" 71 #include "exec/ram_addr.h" 72 #include "hw/usb.h" 73 #include "qemu/config-file.h" 74 #include "qemu/error-report.h" 75 #include "trace.h" 76 #include "hw/nmi.h" 77 #include "hw/intc/intc.h" 78 79 #include "qemu/cutils.h" 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 84 #include "monitor/monitor.h" 85 86 #include <libfdt.h> 87 88 /* SLOF memory layout: 89 * 90 * SLOF raw image loaded at 0, copies its romfs right below the flat 91 * device-tree, then position SLOF itself 31M below that 92 * 93 * So we set FW_OVERHEAD to 40MB which should account for all of that 94 * and more 95 * 96 * We load our kernel at 4M, leaving space for SLOF initial image 97 */ 98 #define FDT_MAX_SIZE 0x100000 99 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 100 #define FW_MAX_SIZE 0x400000 101 #define FW_FILE_NAME "slof.bin" 102 #define FW_OVERHEAD 0x2800000 103 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 104 105 #define MIN_RMA_SLOF 128UL 106 107 #define PHANDLE_INTC 0x00001111 108 109 /* These two functions implement the VCPU id numbering: one to compute them 110 * all and one to identify thread 0 of a VCORE. Any change to the first one 111 * is likely to have an impact on the second one, so let's keep them close. 112 */ 113 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 114 { 115 MachineState *ms = MACHINE(spapr); 116 unsigned int smp_threads = ms->smp.threads; 117 118 assert(spapr->vsmt); 119 return 120 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 121 } 122 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 123 PowerPCCPU *cpu) 124 { 125 assert(spapr->vsmt); 126 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 127 } 128 129 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 130 { 131 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 132 * and newer QEMUs don't even have them. In both cases, we don't want 133 * to send anything on the wire. 134 */ 135 return false; 136 } 137 138 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 139 .name = "icp/server", 140 .version_id = 1, 141 .minimum_version_id = 1, 142 .needed = pre_2_10_vmstate_dummy_icp_needed, 143 .fields = (VMStateField[]) { 144 VMSTATE_UNUSED(4), /* uint32_t xirr */ 145 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 146 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 147 VMSTATE_END_OF_LIST() 148 }, 149 }; 150 151 static void pre_2_10_vmstate_register_dummy_icp(int i) 152 { 153 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 154 (void *)(uintptr_t) i); 155 } 156 157 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 158 { 159 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 160 (void *)(uintptr_t) i); 161 } 162 163 int spapr_max_server_number(SpaprMachineState *spapr) 164 { 165 MachineState *ms = MACHINE(spapr); 166 167 assert(spapr->vsmt); 168 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 169 } 170 171 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 172 int smt_threads) 173 { 174 int i, ret = 0; 175 uint32_t servers_prop[smt_threads]; 176 uint32_t gservers_prop[smt_threads * 2]; 177 int index = spapr_get_vcpu_id(cpu); 178 179 if (cpu->compat_pvr) { 180 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 181 if (ret < 0) { 182 return ret; 183 } 184 } 185 186 /* Build interrupt servers and gservers properties */ 187 for (i = 0; i < smt_threads; i++) { 188 servers_prop[i] = cpu_to_be32(index + i); 189 /* Hack, direct the group queues back to cpu 0 */ 190 gservers_prop[i*2] = cpu_to_be32(index + i); 191 gservers_prop[i*2 + 1] = 0; 192 } 193 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 194 servers_prop, sizeof(servers_prop)); 195 if (ret < 0) { 196 return ret; 197 } 198 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 199 gservers_prop, sizeof(gservers_prop)); 200 201 return ret; 202 } 203 204 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 205 { 206 int index = spapr_get_vcpu_id(cpu); 207 uint32_t associativity[] = {cpu_to_be32(0x5), 208 cpu_to_be32(0x0), 209 cpu_to_be32(0x0), 210 cpu_to_be32(0x0), 211 cpu_to_be32(cpu->node_id), 212 cpu_to_be32(index)}; 213 214 /* Advertise NUMA via ibm,associativity */ 215 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 216 sizeof(associativity)); 217 } 218 219 /* Populate the "ibm,pa-features" property */ 220 static void spapr_populate_pa_features(SpaprMachineState *spapr, 221 PowerPCCPU *cpu, 222 void *fdt, int offset) 223 { 224 uint8_t pa_features_206[] = { 6, 0, 225 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 226 uint8_t pa_features_207[] = { 24, 0, 227 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 228 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 229 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 230 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 231 uint8_t pa_features_300[] = { 66, 0, 232 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 233 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 234 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 235 /* 6: DS207 */ 236 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 237 /* 16: Vector */ 238 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 239 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 241 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 242 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 243 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 244 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 245 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 246 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 247 /* 42: PM, 44: PC RA, 46: SC vec'd */ 248 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 249 /* 48: SIMD, 50: QP BFP, 52: String */ 250 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 251 /* 54: DecFP, 56: DecI, 58: SHA */ 252 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 253 /* 60: NM atomic, 62: RNG */ 254 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 255 }; 256 uint8_t *pa_features = NULL; 257 size_t pa_size; 258 259 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 260 pa_features = pa_features_206; 261 pa_size = sizeof(pa_features_206); 262 } 263 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 264 pa_features = pa_features_207; 265 pa_size = sizeof(pa_features_207); 266 } 267 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 268 pa_features = pa_features_300; 269 pa_size = sizeof(pa_features_300); 270 } 271 if (!pa_features) { 272 return; 273 } 274 275 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 276 /* 277 * Note: we keep CI large pages off by default because a 64K capable 278 * guest provisioned with large pages might otherwise try to map a qemu 279 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 280 * even if that qemu runs on a 4k host. 281 * We dd this bit back here if we are confident this is not an issue 282 */ 283 pa_features[3] |= 0x20; 284 } 285 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 286 pa_features[24] |= 0x80; /* Transactional memory support */ 287 } 288 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 289 /* Workaround for broken kernels that attempt (guest) radix 290 * mode when they can't handle it, if they see the radix bit set 291 * in pa-features. So hide it from them. */ 292 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 293 } 294 295 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 296 } 297 298 static hwaddr spapr_node0_size(MachineState *machine) 299 { 300 if (machine->numa_state->num_nodes) { 301 int i; 302 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 303 if (machine->numa_state->nodes[i].node_mem) { 304 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 305 machine->ram_size); 306 } 307 } 308 } 309 return machine->ram_size; 310 } 311 312 static void add_str(GString *s, const gchar *s1) 313 { 314 g_string_append_len(s, s1, strlen(s1) + 1); 315 } 316 317 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 318 hwaddr size) 319 { 320 uint32_t associativity[] = { 321 cpu_to_be32(0x4), /* length */ 322 cpu_to_be32(0x0), cpu_to_be32(0x0), 323 cpu_to_be32(0x0), cpu_to_be32(nodeid) 324 }; 325 char mem_name[32]; 326 uint64_t mem_reg_property[2]; 327 int off; 328 329 mem_reg_property[0] = cpu_to_be64(start); 330 mem_reg_property[1] = cpu_to_be64(size); 331 332 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 333 off = fdt_add_subnode(fdt, 0, mem_name); 334 _FDT(off); 335 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 336 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 337 sizeof(mem_reg_property)))); 338 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 339 sizeof(associativity)))); 340 return off; 341 } 342 343 static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt) 344 { 345 MachineState *machine = MACHINE(spapr); 346 hwaddr mem_start, node_size; 347 int i, nb_nodes = machine->numa_state->num_nodes; 348 NodeInfo *nodes = machine->numa_state->nodes; 349 350 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 351 if (!nodes[i].node_mem) { 352 continue; 353 } 354 if (mem_start >= machine->ram_size) { 355 node_size = 0; 356 } else { 357 node_size = nodes[i].node_mem; 358 if (node_size > machine->ram_size - mem_start) { 359 node_size = machine->ram_size - mem_start; 360 } 361 } 362 if (!mem_start) { 363 /* spapr_machine_init() checks for rma_size <= node0_size 364 * already */ 365 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 366 mem_start += spapr->rma_size; 367 node_size -= spapr->rma_size; 368 } 369 for ( ; node_size; ) { 370 hwaddr sizetmp = pow2floor(node_size); 371 372 /* mem_start != 0 here */ 373 if (ctzl(mem_start) < ctzl(sizetmp)) { 374 sizetmp = 1ULL << ctzl(mem_start); 375 } 376 377 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 378 node_size -= sizetmp; 379 mem_start += sizetmp; 380 } 381 } 382 383 return 0; 384 } 385 386 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 387 SpaprMachineState *spapr) 388 { 389 MachineState *ms = MACHINE(spapr); 390 PowerPCCPU *cpu = POWERPC_CPU(cs); 391 CPUPPCState *env = &cpu->env; 392 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 393 int index = spapr_get_vcpu_id(cpu); 394 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 395 0xffffffff, 0xffffffff}; 396 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 397 : SPAPR_TIMEBASE_FREQ; 398 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 399 uint32_t page_sizes_prop[64]; 400 size_t page_sizes_prop_size; 401 unsigned int smp_threads = ms->smp.threads; 402 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 403 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 404 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 405 SpaprDrc *drc; 406 int drc_index; 407 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 408 int i; 409 410 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 411 if (drc) { 412 drc_index = spapr_drc_index(drc); 413 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 414 } 415 416 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 417 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 418 419 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 420 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 421 env->dcache_line_size))); 422 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 423 env->dcache_line_size))); 424 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 425 env->icache_line_size))); 426 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 427 env->icache_line_size))); 428 429 if (pcc->l1_dcache_size) { 430 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 431 pcc->l1_dcache_size))); 432 } else { 433 warn_report("Unknown L1 dcache size for cpu"); 434 } 435 if (pcc->l1_icache_size) { 436 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 437 pcc->l1_icache_size))); 438 } else { 439 warn_report("Unknown L1 icache size for cpu"); 440 } 441 442 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 443 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 444 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 445 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 446 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 447 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 448 449 if (env->spr_cb[SPR_PURR].oea_read) { 450 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 451 } 452 if (env->spr_cb[SPR_SPURR].oea_read) { 453 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 454 } 455 456 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 457 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 458 segs, sizeof(segs)))); 459 } 460 461 /* Advertise VSX (vector extensions) if available 462 * 1 == VMX / Altivec available 463 * 2 == VSX available 464 * 465 * Only CPUs for which we create core types in spapr_cpu_core.c 466 * are possible, and all of those have VMX */ 467 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 468 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 469 } else { 470 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 471 } 472 473 /* Advertise DFP (Decimal Floating Point) if available 474 * 0 / no property == no DFP 475 * 1 == DFP available */ 476 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 477 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 478 } 479 480 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 481 sizeof(page_sizes_prop)); 482 if (page_sizes_prop_size) { 483 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 484 page_sizes_prop, page_sizes_prop_size))); 485 } 486 487 spapr_populate_pa_features(spapr, cpu, fdt, offset); 488 489 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 490 cs->cpu_index / vcpus_per_socket))); 491 492 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 493 pft_size_prop, sizeof(pft_size_prop)))); 494 495 if (ms->numa_state->num_nodes > 1) { 496 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 497 } 498 499 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 500 501 if (pcc->radix_page_info) { 502 for (i = 0; i < pcc->radix_page_info->count; i++) { 503 radix_AP_encodings[i] = 504 cpu_to_be32(pcc->radix_page_info->entries[i]); 505 } 506 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 507 radix_AP_encodings, 508 pcc->radix_page_info->count * 509 sizeof(radix_AP_encodings[0])))); 510 } 511 512 /* 513 * We set this property to let the guest know that it can use the large 514 * decrementer and its width in bits. 515 */ 516 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 517 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 518 pcc->lrg_decr_bits))); 519 } 520 521 static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spapr) 522 { 523 CPUState **rev; 524 CPUState *cs; 525 int n_cpus; 526 int cpus_offset; 527 char *nodename; 528 int i; 529 530 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 531 _FDT(cpus_offset); 532 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 533 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 534 535 /* 536 * We walk the CPUs in reverse order to ensure that CPU DT nodes 537 * created by fdt_add_subnode() end up in the right order in FDT 538 * for the guest kernel the enumerate the CPUs correctly. 539 * 540 * The CPU list cannot be traversed in reverse order, so we need 541 * to do extra work. 542 */ 543 n_cpus = 0; 544 rev = NULL; 545 CPU_FOREACH(cs) { 546 rev = g_renew(CPUState *, rev, n_cpus + 1); 547 rev[n_cpus++] = cs; 548 } 549 550 for (i = n_cpus - 1; i >= 0; i--) { 551 CPUState *cs = rev[i]; 552 PowerPCCPU *cpu = POWERPC_CPU(cs); 553 int index = spapr_get_vcpu_id(cpu); 554 DeviceClass *dc = DEVICE_GET_CLASS(cs); 555 int offset; 556 557 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 558 continue; 559 } 560 561 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 562 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 563 g_free(nodename); 564 _FDT(offset); 565 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 566 } 567 568 g_free(rev); 569 } 570 571 static int spapr_rng_populate_dt(void *fdt) 572 { 573 int node; 574 int ret; 575 576 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 577 if (node <= 0) { 578 return -1; 579 } 580 ret = fdt_setprop_string(fdt, node, "device_type", 581 "ibm,platform-facilities"); 582 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 583 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 584 585 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 586 if (node <= 0) { 587 return -1; 588 } 589 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 590 591 return ret ? -1 : 0; 592 } 593 594 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 595 { 596 MemoryDeviceInfoList *info; 597 598 for (info = list; info; info = info->next) { 599 MemoryDeviceInfo *value = info->value; 600 601 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 602 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 603 604 if (addr >= pcdimm_info->addr && 605 addr < (pcdimm_info->addr + pcdimm_info->size)) { 606 return pcdimm_info->node; 607 } 608 } 609 } 610 611 return -1; 612 } 613 614 struct sPAPRDrconfCellV2 { 615 uint32_t seq_lmbs; 616 uint64_t base_addr; 617 uint32_t drc_index; 618 uint32_t aa_index; 619 uint32_t flags; 620 } QEMU_PACKED; 621 622 typedef struct DrconfCellQueue { 623 struct sPAPRDrconfCellV2 cell; 624 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 625 } DrconfCellQueue; 626 627 static DrconfCellQueue * 628 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 629 uint32_t drc_index, uint32_t aa_index, 630 uint32_t flags) 631 { 632 DrconfCellQueue *elem; 633 634 elem = g_malloc0(sizeof(*elem)); 635 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 636 elem->cell.base_addr = cpu_to_be64(base_addr); 637 elem->cell.drc_index = cpu_to_be32(drc_index); 638 elem->cell.aa_index = cpu_to_be32(aa_index); 639 elem->cell.flags = cpu_to_be32(flags); 640 641 return elem; 642 } 643 644 /* ibm,dynamic-memory-v2 */ 645 static int spapr_populate_drmem_v2(SpaprMachineState *spapr, void *fdt, 646 int offset, MemoryDeviceInfoList *dimms) 647 { 648 MachineState *machine = MACHINE(spapr); 649 uint8_t *int_buf, *cur_index; 650 int ret; 651 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 652 uint64_t addr, cur_addr, size; 653 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 654 uint64_t mem_end = machine->device_memory->base + 655 memory_region_size(&machine->device_memory->mr); 656 uint32_t node, buf_len, nr_entries = 0; 657 SpaprDrc *drc; 658 DrconfCellQueue *elem, *next; 659 MemoryDeviceInfoList *info; 660 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 661 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 662 663 /* Entry to cover RAM and the gap area */ 664 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 665 SPAPR_LMB_FLAGS_RESERVED | 666 SPAPR_LMB_FLAGS_DRC_INVALID); 667 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 668 nr_entries++; 669 670 cur_addr = machine->device_memory->base; 671 for (info = dimms; info; info = info->next) { 672 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 673 674 addr = di->addr; 675 size = di->size; 676 node = di->node; 677 678 /* Entry for hot-pluggable area */ 679 if (cur_addr < addr) { 680 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 681 g_assert(drc); 682 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 683 cur_addr, spapr_drc_index(drc), -1, 0); 684 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 685 nr_entries++; 686 } 687 688 /* Entry for DIMM */ 689 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 690 g_assert(drc); 691 elem = spapr_get_drconf_cell(size / lmb_size, addr, 692 spapr_drc_index(drc), node, 693 SPAPR_LMB_FLAGS_ASSIGNED); 694 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 695 nr_entries++; 696 cur_addr = addr + size; 697 } 698 699 /* Entry for remaining hotpluggable area */ 700 if (cur_addr < mem_end) { 701 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 702 g_assert(drc); 703 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 704 cur_addr, spapr_drc_index(drc), -1, 0); 705 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 706 nr_entries++; 707 } 708 709 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 710 int_buf = cur_index = g_malloc0(buf_len); 711 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 712 cur_index += sizeof(nr_entries); 713 714 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 715 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 716 cur_index += sizeof(elem->cell); 717 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 718 g_free(elem); 719 } 720 721 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 722 g_free(int_buf); 723 if (ret < 0) { 724 return -1; 725 } 726 return 0; 727 } 728 729 /* ibm,dynamic-memory */ 730 static int spapr_populate_drmem_v1(SpaprMachineState *spapr, void *fdt, 731 int offset, MemoryDeviceInfoList *dimms) 732 { 733 MachineState *machine = MACHINE(spapr); 734 int i, ret; 735 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 736 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 737 uint32_t nr_lmbs = (machine->device_memory->base + 738 memory_region_size(&machine->device_memory->mr)) / 739 lmb_size; 740 uint32_t *int_buf, *cur_index, buf_len; 741 742 /* 743 * Allocate enough buffer size to fit in ibm,dynamic-memory 744 */ 745 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 746 cur_index = int_buf = g_malloc0(buf_len); 747 int_buf[0] = cpu_to_be32(nr_lmbs); 748 cur_index++; 749 for (i = 0; i < nr_lmbs; i++) { 750 uint64_t addr = i * lmb_size; 751 uint32_t *dynamic_memory = cur_index; 752 753 if (i >= device_lmb_start) { 754 SpaprDrc *drc; 755 756 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 757 g_assert(drc); 758 759 dynamic_memory[0] = cpu_to_be32(addr >> 32); 760 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 761 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 762 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 763 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 764 if (memory_region_present(get_system_memory(), addr)) { 765 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 766 } else { 767 dynamic_memory[5] = cpu_to_be32(0); 768 } 769 } else { 770 /* 771 * LMB information for RMA, boot time RAM and gap b/n RAM and 772 * device memory region -- all these are marked as reserved 773 * and as having no valid DRC. 774 */ 775 dynamic_memory[0] = cpu_to_be32(addr >> 32); 776 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 777 dynamic_memory[2] = cpu_to_be32(0); 778 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 779 dynamic_memory[4] = cpu_to_be32(-1); 780 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 781 SPAPR_LMB_FLAGS_DRC_INVALID); 782 } 783 784 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 785 } 786 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 787 g_free(int_buf); 788 if (ret < 0) { 789 return -1; 790 } 791 return 0; 792 } 793 794 /* 795 * Adds ibm,dynamic-reconfiguration-memory node. 796 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 797 * of this device tree node. 798 */ 799 static int spapr_populate_drconf_memory(SpaprMachineState *spapr, void *fdt) 800 { 801 MachineState *machine = MACHINE(spapr); 802 int nb_numa_nodes = machine->numa_state->num_nodes; 803 int ret, i, offset; 804 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 805 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 806 uint32_t *int_buf, *cur_index, buf_len; 807 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 808 MemoryDeviceInfoList *dimms = NULL; 809 810 /* 811 * Don't create the node if there is no device memory 812 */ 813 if (machine->ram_size == machine->maxram_size) { 814 return 0; 815 } 816 817 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 818 819 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 820 sizeof(prop_lmb_size)); 821 if (ret < 0) { 822 return ret; 823 } 824 825 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 826 if (ret < 0) { 827 return ret; 828 } 829 830 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 831 if (ret < 0) { 832 return ret; 833 } 834 835 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 836 dimms = qmp_memory_device_list(); 837 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 838 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 839 } else { 840 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 841 } 842 qapi_free_MemoryDeviceInfoList(dimms); 843 844 if (ret < 0) { 845 return ret; 846 } 847 848 /* ibm,associativity-lookup-arrays */ 849 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 850 cur_index = int_buf = g_malloc0(buf_len); 851 int_buf[0] = cpu_to_be32(nr_nodes); 852 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 853 cur_index += 2; 854 for (i = 0; i < nr_nodes; i++) { 855 uint32_t associativity[] = { 856 cpu_to_be32(0x0), 857 cpu_to_be32(0x0), 858 cpu_to_be32(0x0), 859 cpu_to_be32(i) 860 }; 861 memcpy(cur_index, associativity, sizeof(associativity)); 862 cur_index += 4; 863 } 864 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 865 (cur_index - int_buf) * sizeof(uint32_t)); 866 g_free(int_buf); 867 868 return ret; 869 } 870 871 static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt, 872 SpaprOptionVector *ov5_updates) 873 { 874 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 875 int ret = 0, offset; 876 877 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 878 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 879 g_assert(smc->dr_lmb_enabled); 880 ret = spapr_populate_drconf_memory(spapr, fdt); 881 if (ret) { 882 goto out; 883 } 884 } 885 886 offset = fdt_path_offset(fdt, "/chosen"); 887 if (offset < 0) { 888 offset = fdt_add_subnode(fdt, 0, "chosen"); 889 if (offset < 0) { 890 return offset; 891 } 892 } 893 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 894 "ibm,architecture-vec-5"); 895 896 out: 897 return ret; 898 } 899 900 static bool spapr_hotplugged_dev_before_cas(void) 901 { 902 Object *drc_container, *obj; 903 ObjectProperty *prop; 904 ObjectPropertyIterator iter; 905 906 drc_container = container_get(object_get_root(), "/dr-connector"); 907 object_property_iter_init(&iter, drc_container); 908 while ((prop = object_property_iter_next(&iter))) { 909 if (!strstart(prop->type, "link<", NULL)) { 910 continue; 911 } 912 obj = object_property_get_link(drc_container, prop->name, NULL); 913 if (spapr_drc_needed(obj)) { 914 return true; 915 } 916 } 917 return false; 918 } 919 920 static void *spapr_build_fdt(SpaprMachineState *spapr); 921 922 int spapr_h_cas_compose_response(SpaprMachineState *spapr, 923 target_ulong addr, target_ulong size, 924 SpaprOptionVector *ov5_updates) 925 { 926 void *fdt; 927 SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 928 929 if (spapr_hotplugged_dev_before_cas()) { 930 return 1; 931 } 932 933 if (size < sizeof(hdr) || size > FW_MAX_SIZE) { 934 error_report("SLOF provided an unexpected CAS buffer size " 935 TARGET_FMT_lu " (min: %zu, max: %u)", 936 size, sizeof(hdr), FW_MAX_SIZE); 937 exit(EXIT_FAILURE); 938 } 939 940 size -= sizeof(hdr); 941 942 fdt = spapr_build_fdt(spapr); 943 _FDT((fdt_pack(fdt))); 944 945 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 946 g_free(fdt); 947 trace_spapr_cas_failed(size); 948 return -1; 949 } 950 951 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 952 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 953 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 954 955 g_free(spapr->fdt_blob); 956 spapr->fdt_size = fdt_totalsize(fdt); 957 spapr->fdt_initial_size = spapr->fdt_size; 958 spapr->fdt_blob = fdt; 959 960 return 0; 961 } 962 963 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 964 { 965 MachineState *ms = MACHINE(spapr); 966 int rtas; 967 GString *hypertas = g_string_sized_new(256); 968 GString *qemu_hypertas = g_string_sized_new(256); 969 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 970 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 971 memory_region_size(&MACHINE(spapr)->device_memory->mr); 972 uint32_t lrdr_capacity[] = { 973 cpu_to_be32(max_device_addr >> 32), 974 cpu_to_be32(max_device_addr & 0xffffffff), 975 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 976 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 977 }; 978 uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0); 979 uint32_t maxdomains[] = { 980 cpu_to_be32(4), 981 maxdomain, 982 maxdomain, 983 maxdomain, 984 cpu_to_be32(spapr->gpu_numa_id), 985 }; 986 987 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 988 989 /* hypertas */ 990 add_str(hypertas, "hcall-pft"); 991 add_str(hypertas, "hcall-term"); 992 add_str(hypertas, "hcall-dabr"); 993 add_str(hypertas, "hcall-interrupt"); 994 add_str(hypertas, "hcall-tce"); 995 add_str(hypertas, "hcall-vio"); 996 add_str(hypertas, "hcall-splpar"); 997 add_str(hypertas, "hcall-join"); 998 add_str(hypertas, "hcall-bulk"); 999 add_str(hypertas, "hcall-set-mode"); 1000 add_str(hypertas, "hcall-sprg0"); 1001 add_str(hypertas, "hcall-copy"); 1002 add_str(hypertas, "hcall-debug"); 1003 add_str(hypertas, "hcall-vphn"); 1004 add_str(qemu_hypertas, "hcall-memop1"); 1005 1006 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 1007 add_str(hypertas, "hcall-multi-tce"); 1008 } 1009 1010 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 1011 add_str(hypertas, "hcall-hpt-resize"); 1012 } 1013 1014 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 1015 hypertas->str, hypertas->len)); 1016 g_string_free(hypertas, TRUE); 1017 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 1018 qemu_hypertas->str, qemu_hypertas->len)); 1019 g_string_free(qemu_hypertas, TRUE); 1020 1021 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 1022 refpoints, sizeof(refpoints))); 1023 1024 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 1025 maxdomains, sizeof(maxdomains))); 1026 1027 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 1028 RTAS_ERROR_LOG_MAX)); 1029 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 1030 RTAS_EVENT_SCAN_RATE)); 1031 1032 g_assert(msi_nonbroken); 1033 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 1034 1035 /* 1036 * According to PAPR, rtas ibm,os-term does not guarantee a return 1037 * back to the guest cpu. 1038 * 1039 * While an additional ibm,extended-os-term property indicates 1040 * that rtas call return will always occur. Set this property. 1041 */ 1042 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1043 1044 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1045 lrdr_capacity, sizeof(lrdr_capacity))); 1046 1047 spapr_dt_rtas_tokens(fdt, rtas); 1048 } 1049 1050 /* 1051 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 1052 * and the XIVE features that the guest may request and thus the valid 1053 * values for bytes 23..26 of option vector 5: 1054 */ 1055 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 1056 int chosen) 1057 { 1058 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1059 1060 char val[2 * 4] = { 1061 23, 0x00, /* XICS / XIVE mode */ 1062 24, 0x00, /* Hash/Radix, filled in below. */ 1063 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1064 26, 0x40, /* Radix options: GTSE == yes. */ 1065 }; 1066 1067 if (spapr->irq->xics && spapr->irq->xive) { 1068 val[1] = SPAPR_OV5_XIVE_BOTH; 1069 } else if (spapr->irq->xive) { 1070 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1071 } else { 1072 assert(spapr->irq->xics); 1073 val[1] = SPAPR_OV5_XIVE_LEGACY; 1074 } 1075 1076 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1077 first_ppc_cpu->compat_pvr)) { 1078 /* 1079 * If we're in a pre POWER9 compat mode then the guest should 1080 * do hash and use the legacy interrupt mode 1081 */ 1082 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1083 val[3] = 0x00; /* Hash */ 1084 } else if (kvm_enabled()) { 1085 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1086 val[3] = 0x80; /* OV5_MMU_BOTH */ 1087 } else if (kvmppc_has_cap_mmu_radix()) { 1088 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1089 } else { 1090 val[3] = 0x00; /* Hash */ 1091 } 1092 } else { 1093 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1094 val[3] = 0xC0; 1095 } 1096 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1097 val, sizeof(val))); 1098 } 1099 1100 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt) 1101 { 1102 MachineState *machine = MACHINE(spapr); 1103 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1104 int chosen; 1105 const char *boot_device = machine->boot_order; 1106 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1107 size_t cb = 0; 1108 char *bootlist = get_boot_devices_list(&cb); 1109 1110 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1111 1112 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1113 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1114 machine->kernel_cmdline)); 1115 } 1116 if (spapr->initrd_size) { 1117 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1118 spapr->initrd_base)); 1119 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1120 spapr->initrd_base + spapr->initrd_size)); 1121 } 1122 1123 if (spapr->kernel_size) { 1124 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1125 cpu_to_be64(spapr->kernel_size) }; 1126 1127 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1128 &kprop, sizeof(kprop))); 1129 if (spapr->kernel_le) { 1130 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1131 } 1132 } 1133 if (boot_menu) { 1134 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1135 } 1136 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1137 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1138 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1139 1140 if (cb && bootlist) { 1141 int i; 1142 1143 for (i = 0; i < cb; i++) { 1144 if (bootlist[i] == '\n') { 1145 bootlist[i] = ' '; 1146 } 1147 } 1148 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1149 } 1150 1151 if (boot_device && strlen(boot_device)) { 1152 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1153 } 1154 1155 if (!spapr->has_graphics && stdout_path) { 1156 /* 1157 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1158 * kernel. New platforms should only use the "stdout-path" property. Set 1159 * the new property and continue using older property to remain 1160 * compatible with the existing firmware. 1161 */ 1162 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1163 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1164 } 1165 1166 /* We can deal with BAR reallocation just fine, advertise it to the guest */ 1167 if (smc->linux_pci_probe) { 1168 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1169 } 1170 1171 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1172 1173 g_free(stdout_path); 1174 g_free(bootlist); 1175 } 1176 1177 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1178 { 1179 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1180 * KVM to work under pHyp with some guest co-operation */ 1181 int hypervisor; 1182 uint8_t hypercall[16]; 1183 1184 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1185 /* indicate KVM hypercall interface */ 1186 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1187 if (kvmppc_has_cap_fixup_hcalls()) { 1188 /* 1189 * Older KVM versions with older guest kernels were broken 1190 * with the magic page, don't allow the guest to map it. 1191 */ 1192 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1193 sizeof(hypercall))) { 1194 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1195 hypercall, sizeof(hypercall))); 1196 } 1197 } 1198 } 1199 1200 static void *spapr_build_fdt(SpaprMachineState *spapr) 1201 { 1202 MachineState *machine = MACHINE(spapr); 1203 MachineClass *mc = MACHINE_GET_CLASS(machine); 1204 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1205 int ret; 1206 void *fdt; 1207 SpaprPhbState *phb; 1208 char *buf; 1209 1210 fdt = g_malloc0(FDT_MAX_SIZE); 1211 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1212 1213 /* Root node */ 1214 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1215 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1216 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1217 1218 /* Guest UUID & Name*/ 1219 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1220 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1221 if (qemu_uuid_set) { 1222 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1223 } 1224 g_free(buf); 1225 1226 if (qemu_get_vm_name()) { 1227 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1228 qemu_get_vm_name())); 1229 } 1230 1231 /* Host Model & Serial Number */ 1232 if (spapr->host_model) { 1233 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1234 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1235 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1236 g_free(buf); 1237 } 1238 1239 if (spapr->host_serial) { 1240 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1241 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1242 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1243 g_free(buf); 1244 } 1245 1246 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1247 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1248 1249 /* /interrupt controller */ 1250 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1251 1252 ret = spapr_populate_memory(spapr, fdt); 1253 if (ret < 0) { 1254 error_report("couldn't setup memory nodes in fdt"); 1255 exit(1); 1256 } 1257 1258 /* /vdevice */ 1259 spapr_dt_vdevice(spapr->vio_bus, fdt); 1260 1261 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1262 ret = spapr_rng_populate_dt(fdt); 1263 if (ret < 0) { 1264 error_report("could not set up rng device in the fdt"); 1265 exit(1); 1266 } 1267 } 1268 1269 QLIST_FOREACH(phb, &spapr->phbs, list) { 1270 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1271 if (ret < 0) { 1272 error_report("couldn't setup PCI devices in fdt"); 1273 exit(1); 1274 } 1275 } 1276 1277 /* cpus */ 1278 spapr_populate_cpus_dt_node(fdt, spapr); 1279 1280 if (smc->dr_lmb_enabled) { 1281 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1282 } 1283 1284 if (mc->has_hotpluggable_cpus) { 1285 int offset = fdt_path_offset(fdt, "/cpus"); 1286 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1287 if (ret < 0) { 1288 error_report("Couldn't set up CPU DR device tree properties"); 1289 exit(1); 1290 } 1291 } 1292 1293 /* /event-sources */ 1294 spapr_dt_events(spapr, fdt); 1295 1296 /* /rtas */ 1297 spapr_dt_rtas(spapr, fdt); 1298 1299 /* /chosen */ 1300 spapr_dt_chosen(spapr, fdt); 1301 1302 /* /hypervisor */ 1303 if (kvm_enabled()) { 1304 spapr_dt_hypervisor(spapr, fdt); 1305 } 1306 1307 /* Build memory reserve map */ 1308 if (spapr->kernel_size) { 1309 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1310 } 1311 if (spapr->initrd_size) { 1312 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1313 } 1314 1315 /* ibm,client-architecture-support updates */ 1316 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1317 if (ret < 0) { 1318 error_report("couldn't setup CAS properties fdt"); 1319 exit(1); 1320 } 1321 1322 if (smc->dr_phb_enabled) { 1323 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); 1324 if (ret < 0) { 1325 error_report("Couldn't set up PHB DR device tree properties"); 1326 exit(1); 1327 } 1328 } 1329 1330 return fdt; 1331 } 1332 1333 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1334 { 1335 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1336 } 1337 1338 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1339 PowerPCCPU *cpu) 1340 { 1341 CPUPPCState *env = &cpu->env; 1342 1343 /* The TCG path should also be holding the BQL at this point */ 1344 g_assert(qemu_mutex_iothread_locked()); 1345 1346 if (msr_pr) { 1347 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1348 env->gpr[3] = H_PRIVILEGE; 1349 } else { 1350 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1351 } 1352 } 1353 1354 struct LPCRSyncState { 1355 target_ulong value; 1356 target_ulong mask; 1357 }; 1358 1359 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1360 { 1361 struct LPCRSyncState *s = arg.host_ptr; 1362 PowerPCCPU *cpu = POWERPC_CPU(cs); 1363 CPUPPCState *env = &cpu->env; 1364 target_ulong lpcr; 1365 1366 cpu_synchronize_state(cs); 1367 lpcr = env->spr[SPR_LPCR]; 1368 lpcr &= ~s->mask; 1369 lpcr |= s->value; 1370 ppc_store_lpcr(cpu, lpcr); 1371 } 1372 1373 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1374 { 1375 CPUState *cs; 1376 struct LPCRSyncState s = { 1377 .value = value, 1378 .mask = mask 1379 }; 1380 CPU_FOREACH(cs) { 1381 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1382 } 1383 } 1384 1385 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1386 { 1387 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1388 1389 /* Copy PATE1:GR into PATE0:HR */ 1390 entry->dw0 = spapr->patb_entry & PATE0_HR; 1391 entry->dw1 = spapr->patb_entry; 1392 } 1393 1394 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1395 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1396 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1397 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1398 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1399 1400 /* 1401 * Get the fd to access the kernel htab, re-opening it if necessary 1402 */ 1403 static int get_htab_fd(SpaprMachineState *spapr) 1404 { 1405 Error *local_err = NULL; 1406 1407 if (spapr->htab_fd >= 0) { 1408 return spapr->htab_fd; 1409 } 1410 1411 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1412 if (spapr->htab_fd < 0) { 1413 error_report_err(local_err); 1414 } 1415 1416 return spapr->htab_fd; 1417 } 1418 1419 void close_htab_fd(SpaprMachineState *spapr) 1420 { 1421 if (spapr->htab_fd >= 0) { 1422 close(spapr->htab_fd); 1423 } 1424 spapr->htab_fd = -1; 1425 } 1426 1427 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1428 { 1429 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1430 1431 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1432 } 1433 1434 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1435 { 1436 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1437 1438 assert(kvm_enabled()); 1439 1440 if (!spapr->htab) { 1441 return 0; 1442 } 1443 1444 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1445 } 1446 1447 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1448 hwaddr ptex, int n) 1449 { 1450 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1451 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1452 1453 if (!spapr->htab) { 1454 /* 1455 * HTAB is controlled by KVM. Fetch into temporary buffer 1456 */ 1457 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1458 kvmppc_read_hptes(hptes, ptex, n); 1459 return hptes; 1460 } 1461 1462 /* 1463 * HTAB is controlled by QEMU. Just point to the internally 1464 * accessible PTEG. 1465 */ 1466 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1467 } 1468 1469 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1470 const ppc_hash_pte64_t *hptes, 1471 hwaddr ptex, int n) 1472 { 1473 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1474 1475 if (!spapr->htab) { 1476 g_free((void *)hptes); 1477 } 1478 1479 /* Nothing to do for qemu managed HPT */ 1480 } 1481 1482 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1483 uint64_t pte0, uint64_t pte1) 1484 { 1485 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1486 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1487 1488 if (!spapr->htab) { 1489 kvmppc_write_hpte(ptex, pte0, pte1); 1490 } else { 1491 if (pte0 & HPTE64_V_VALID) { 1492 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1493 /* 1494 * When setting valid, we write PTE1 first. This ensures 1495 * proper synchronization with the reading code in 1496 * ppc_hash64_pteg_search() 1497 */ 1498 smp_wmb(); 1499 stq_p(spapr->htab + offset, pte0); 1500 } else { 1501 stq_p(spapr->htab + offset, pte0); 1502 /* 1503 * When clearing it we set PTE0 first. This ensures proper 1504 * synchronization with the reading code in 1505 * ppc_hash64_pteg_search() 1506 */ 1507 smp_wmb(); 1508 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1509 } 1510 } 1511 } 1512 1513 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1514 uint64_t pte1) 1515 { 1516 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1517 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1518 1519 if (!spapr->htab) { 1520 /* There should always be a hash table when this is called */ 1521 error_report("spapr_hpte_set_c called with no hash table !"); 1522 return; 1523 } 1524 1525 /* The HW performs a non-atomic byte update */ 1526 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1527 } 1528 1529 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1530 uint64_t pte1) 1531 { 1532 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1533 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1534 1535 if (!spapr->htab) { 1536 /* There should always be a hash table when this is called */ 1537 error_report("spapr_hpte_set_r called with no hash table !"); 1538 return; 1539 } 1540 1541 /* The HW performs a non-atomic byte update */ 1542 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1543 } 1544 1545 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1546 { 1547 int shift; 1548 1549 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1550 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1551 * that's much more than is needed for Linux guests */ 1552 shift = ctz64(pow2ceil(ramsize)) - 7; 1553 shift = MAX(shift, 18); /* Minimum architected size */ 1554 shift = MIN(shift, 46); /* Maximum architected size */ 1555 return shift; 1556 } 1557 1558 void spapr_free_hpt(SpaprMachineState *spapr) 1559 { 1560 g_free(spapr->htab); 1561 spapr->htab = NULL; 1562 spapr->htab_shift = 0; 1563 close_htab_fd(spapr); 1564 } 1565 1566 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 1567 Error **errp) 1568 { 1569 long rc; 1570 1571 /* Clean up any HPT info from a previous boot */ 1572 spapr_free_hpt(spapr); 1573 1574 rc = kvmppc_reset_htab(shift); 1575 if (rc < 0) { 1576 /* kernel-side HPT needed, but couldn't allocate one */ 1577 error_setg_errno(errp, errno, 1578 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1579 shift); 1580 /* This is almost certainly fatal, but if the caller really 1581 * wants to carry on with shift == 0, it's welcome to try */ 1582 } else if (rc > 0) { 1583 /* kernel-side HPT allocated */ 1584 if (rc != shift) { 1585 error_setg(errp, 1586 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1587 shift, rc); 1588 } 1589 1590 spapr->htab_shift = shift; 1591 spapr->htab = NULL; 1592 } else { 1593 /* kernel-side HPT not needed, allocate in userspace instead */ 1594 size_t size = 1ULL << shift; 1595 int i; 1596 1597 spapr->htab = qemu_memalign(size, size); 1598 if (!spapr->htab) { 1599 error_setg_errno(errp, errno, 1600 "Could not allocate HPT of order %d", shift); 1601 return; 1602 } 1603 1604 memset(spapr->htab, 0, size); 1605 spapr->htab_shift = shift; 1606 1607 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1608 DIRTY_HPTE(HPTE(spapr->htab, i)); 1609 } 1610 } 1611 /* We're setting up a hash table, so that means we're not radix */ 1612 spapr->patb_entry = 0; 1613 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1614 } 1615 1616 void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr) 1617 { 1618 int hpt_shift; 1619 1620 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1621 || (spapr->cas_reboot 1622 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1623 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1624 } else { 1625 uint64_t current_ram_size; 1626 1627 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1628 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1629 } 1630 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1631 1632 if (spapr->vrma_adjust) { 1633 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1634 spapr->htab_shift); 1635 } 1636 } 1637 1638 static int spapr_reset_drcs(Object *child, void *opaque) 1639 { 1640 SpaprDrc *drc = 1641 (SpaprDrc *) object_dynamic_cast(child, 1642 TYPE_SPAPR_DR_CONNECTOR); 1643 1644 if (drc) { 1645 spapr_drc_reset(drc); 1646 } 1647 1648 return 0; 1649 } 1650 1651 static void spapr_machine_reset(MachineState *machine) 1652 { 1653 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1654 PowerPCCPU *first_ppc_cpu; 1655 hwaddr fdt_addr; 1656 void *fdt; 1657 int rc; 1658 1659 spapr_caps_apply(spapr); 1660 1661 first_ppc_cpu = POWERPC_CPU(first_cpu); 1662 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1663 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1664 spapr->max_compat_pvr)) { 1665 /* 1666 * If using KVM with radix mode available, VCPUs can be started 1667 * without a HPT because KVM will start them in radix mode. 1668 * Set the GR bit in PATE so that we know there is no HPT. 1669 */ 1670 spapr->patb_entry = PATE1_GR; 1671 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1672 } else { 1673 spapr_setup_hpt_and_vrma(spapr); 1674 } 1675 1676 qemu_devices_reset(); 1677 1678 /* 1679 * If this reset wasn't generated by CAS, we should reset our 1680 * negotiated options and start from scratch 1681 */ 1682 if (!spapr->cas_reboot) { 1683 spapr_ovec_cleanup(spapr->ov5_cas); 1684 spapr->ov5_cas = spapr_ovec_new(); 1685 1686 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1687 } 1688 1689 /* 1690 * This is fixing some of the default configuration of the XIVE 1691 * devices. To be called after the reset of the machine devices. 1692 */ 1693 spapr_irq_reset(spapr, &error_fatal); 1694 1695 /* 1696 * There is no CAS under qtest. Simulate one to please the code that 1697 * depends on spapr->ov5_cas. This is especially needed to test device 1698 * unplug, so we do that before resetting the DRCs. 1699 */ 1700 if (qtest_enabled()) { 1701 spapr_ovec_cleanup(spapr->ov5_cas); 1702 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1703 } 1704 1705 /* DRC reset may cause a device to be unplugged. This will cause troubles 1706 * if this device is used by another device (eg, a running vhost backend 1707 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1708 * situations, we reset DRCs after all devices have been reset. 1709 */ 1710 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1711 1712 spapr_clear_pending_events(spapr); 1713 1714 /* 1715 * We place the device tree and RTAS just below either the top of the RMA, 1716 * or just below 2GB, whichever is lower, so that it can be 1717 * processed with 32-bit real mode code if necessary 1718 */ 1719 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1720 1721 fdt = spapr_build_fdt(spapr); 1722 1723 rc = fdt_pack(fdt); 1724 1725 /* Should only fail if we've built a corrupted tree */ 1726 assert(rc == 0); 1727 1728 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1729 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1730 fdt_totalsize(fdt), FDT_MAX_SIZE); 1731 exit(1); 1732 } 1733 1734 /* Load the fdt */ 1735 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1736 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1737 g_free(spapr->fdt_blob); 1738 spapr->fdt_size = fdt_totalsize(fdt); 1739 spapr->fdt_initial_size = spapr->fdt_size; 1740 spapr->fdt_blob = fdt; 1741 1742 /* Set up the entry state */ 1743 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); 1744 first_ppc_cpu->env.gpr[5] = 0; 1745 1746 spapr->cas_reboot = false; 1747 } 1748 1749 static void spapr_create_nvram(SpaprMachineState *spapr) 1750 { 1751 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1752 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1753 1754 if (dinfo) { 1755 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1756 &error_fatal); 1757 } 1758 1759 qdev_init_nofail(dev); 1760 1761 spapr->nvram = (struct SpaprNvram *)dev; 1762 } 1763 1764 static void spapr_rtc_create(SpaprMachineState *spapr) 1765 { 1766 object_initialize_child(OBJECT(spapr), "rtc", 1767 &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1768 &error_fatal, NULL); 1769 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1770 &error_fatal); 1771 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1772 "date", &error_fatal); 1773 } 1774 1775 /* Returns whether we want to use VGA or not */ 1776 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1777 { 1778 switch (vga_interface_type) { 1779 case VGA_NONE: 1780 return false; 1781 case VGA_DEVICE: 1782 return true; 1783 case VGA_STD: 1784 case VGA_VIRTIO: 1785 case VGA_CIRRUS: 1786 return pci_vga_init(pci_bus) != NULL; 1787 default: 1788 error_setg(errp, 1789 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1790 return false; 1791 } 1792 } 1793 1794 static int spapr_pre_load(void *opaque) 1795 { 1796 int rc; 1797 1798 rc = spapr_caps_pre_load(opaque); 1799 if (rc) { 1800 return rc; 1801 } 1802 1803 return 0; 1804 } 1805 1806 static int spapr_post_load(void *opaque, int version_id) 1807 { 1808 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1809 int err = 0; 1810 1811 err = spapr_caps_post_migration(spapr); 1812 if (err) { 1813 return err; 1814 } 1815 1816 /* 1817 * In earlier versions, there was no separate qdev for the PAPR 1818 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1819 * So when migrating from those versions, poke the incoming offset 1820 * value into the RTC device 1821 */ 1822 if (version_id < 3) { 1823 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1824 if (err) { 1825 return err; 1826 } 1827 } 1828 1829 if (kvm_enabled() && spapr->patb_entry) { 1830 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1831 bool radix = !!(spapr->patb_entry & PATE1_GR); 1832 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1833 1834 /* 1835 * Update LPCR:HR and UPRT as they may not be set properly in 1836 * the stream 1837 */ 1838 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1839 LPCR_HR | LPCR_UPRT); 1840 1841 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1842 if (err) { 1843 error_report("Process table config unsupported by the host"); 1844 return -EINVAL; 1845 } 1846 } 1847 1848 err = spapr_irq_post_load(spapr, version_id); 1849 if (err) { 1850 return err; 1851 } 1852 1853 return err; 1854 } 1855 1856 static int spapr_pre_save(void *opaque) 1857 { 1858 int rc; 1859 1860 rc = spapr_caps_pre_save(opaque); 1861 if (rc) { 1862 return rc; 1863 } 1864 1865 return 0; 1866 } 1867 1868 static bool version_before_3(void *opaque, int version_id) 1869 { 1870 return version_id < 3; 1871 } 1872 1873 static bool spapr_pending_events_needed(void *opaque) 1874 { 1875 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1876 return !QTAILQ_EMPTY(&spapr->pending_events); 1877 } 1878 1879 static const VMStateDescription vmstate_spapr_event_entry = { 1880 .name = "spapr_event_log_entry", 1881 .version_id = 1, 1882 .minimum_version_id = 1, 1883 .fields = (VMStateField[]) { 1884 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1885 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1886 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1887 NULL, extended_length), 1888 VMSTATE_END_OF_LIST() 1889 }, 1890 }; 1891 1892 static const VMStateDescription vmstate_spapr_pending_events = { 1893 .name = "spapr_pending_events", 1894 .version_id = 1, 1895 .minimum_version_id = 1, 1896 .needed = spapr_pending_events_needed, 1897 .fields = (VMStateField[]) { 1898 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1899 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1900 VMSTATE_END_OF_LIST() 1901 }, 1902 }; 1903 1904 static bool spapr_ov5_cas_needed(void *opaque) 1905 { 1906 SpaprMachineState *spapr = opaque; 1907 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1908 SpaprOptionVector *ov5_legacy = spapr_ovec_new(); 1909 SpaprOptionVector *ov5_removed = spapr_ovec_new(); 1910 bool cas_needed; 1911 1912 /* Prior to the introduction of SpaprOptionVector, we had two option 1913 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1914 * Both of these options encode machine topology into the device-tree 1915 * in such a way that the now-booted OS should still be able to interact 1916 * appropriately with QEMU regardless of what options were actually 1917 * negotiatied on the source side. 1918 * 1919 * As such, we can avoid migrating the CAS-negotiated options if these 1920 * are the only options available on the current machine/platform. 1921 * Since these are the only options available for pseries-2.7 and 1922 * earlier, this allows us to maintain old->new/new->old migration 1923 * compatibility. 1924 * 1925 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1926 * via default pseries-2.8 machines and explicit command-line parameters. 1927 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1928 * of the actual CAS-negotiated values to continue working properly. For 1929 * example, availability of memory unplug depends on knowing whether 1930 * OV5_HP_EVT was negotiated via CAS. 1931 * 1932 * Thus, for any cases where the set of available CAS-negotiatable 1933 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1934 * include the CAS-negotiated options in the migration stream, unless 1935 * if they affect boot time behaviour only. 1936 */ 1937 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1938 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1939 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1940 1941 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1942 * the mask itself since in the future it's possible "legacy" bits may be 1943 * removed via machine options, which could generate a false positive 1944 * that breaks migration. 1945 */ 1946 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1947 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1948 1949 spapr_ovec_cleanup(ov5_mask); 1950 spapr_ovec_cleanup(ov5_legacy); 1951 spapr_ovec_cleanup(ov5_removed); 1952 1953 return cas_needed; 1954 } 1955 1956 static const VMStateDescription vmstate_spapr_ov5_cas = { 1957 .name = "spapr_option_vector_ov5_cas", 1958 .version_id = 1, 1959 .minimum_version_id = 1, 1960 .needed = spapr_ov5_cas_needed, 1961 .fields = (VMStateField[]) { 1962 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1963 vmstate_spapr_ovec, SpaprOptionVector), 1964 VMSTATE_END_OF_LIST() 1965 }, 1966 }; 1967 1968 static bool spapr_patb_entry_needed(void *opaque) 1969 { 1970 SpaprMachineState *spapr = opaque; 1971 1972 return !!spapr->patb_entry; 1973 } 1974 1975 static const VMStateDescription vmstate_spapr_patb_entry = { 1976 .name = "spapr_patb_entry", 1977 .version_id = 1, 1978 .minimum_version_id = 1, 1979 .needed = spapr_patb_entry_needed, 1980 .fields = (VMStateField[]) { 1981 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1982 VMSTATE_END_OF_LIST() 1983 }, 1984 }; 1985 1986 static bool spapr_irq_map_needed(void *opaque) 1987 { 1988 SpaprMachineState *spapr = opaque; 1989 1990 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1991 } 1992 1993 static const VMStateDescription vmstate_spapr_irq_map = { 1994 .name = "spapr_irq_map", 1995 .version_id = 1, 1996 .minimum_version_id = 1, 1997 .needed = spapr_irq_map_needed, 1998 .fields = (VMStateField[]) { 1999 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 2000 VMSTATE_END_OF_LIST() 2001 }, 2002 }; 2003 2004 static bool spapr_dtb_needed(void *opaque) 2005 { 2006 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 2007 2008 return smc->update_dt_enabled; 2009 } 2010 2011 static int spapr_dtb_pre_load(void *opaque) 2012 { 2013 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2014 2015 g_free(spapr->fdt_blob); 2016 spapr->fdt_blob = NULL; 2017 spapr->fdt_size = 0; 2018 2019 return 0; 2020 } 2021 2022 static const VMStateDescription vmstate_spapr_dtb = { 2023 .name = "spapr_dtb", 2024 .version_id = 1, 2025 .minimum_version_id = 1, 2026 .needed = spapr_dtb_needed, 2027 .pre_load = spapr_dtb_pre_load, 2028 .fields = (VMStateField[]) { 2029 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 2030 VMSTATE_UINT32(fdt_size, SpaprMachineState), 2031 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 2032 fdt_size), 2033 VMSTATE_END_OF_LIST() 2034 }, 2035 }; 2036 2037 static const VMStateDescription vmstate_spapr = { 2038 .name = "spapr", 2039 .version_id = 3, 2040 .minimum_version_id = 1, 2041 .pre_load = spapr_pre_load, 2042 .post_load = spapr_post_load, 2043 .pre_save = spapr_pre_save, 2044 .fields = (VMStateField[]) { 2045 /* used to be @next_irq */ 2046 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2047 2048 /* RTC offset */ 2049 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2050 2051 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2052 VMSTATE_END_OF_LIST() 2053 }, 2054 .subsections = (const VMStateDescription*[]) { 2055 &vmstate_spapr_ov5_cas, 2056 &vmstate_spapr_patb_entry, 2057 &vmstate_spapr_pending_events, 2058 &vmstate_spapr_cap_htm, 2059 &vmstate_spapr_cap_vsx, 2060 &vmstate_spapr_cap_dfp, 2061 &vmstate_spapr_cap_cfpc, 2062 &vmstate_spapr_cap_sbbc, 2063 &vmstate_spapr_cap_ibs, 2064 &vmstate_spapr_cap_hpt_maxpagesize, 2065 &vmstate_spapr_irq_map, 2066 &vmstate_spapr_cap_nested_kvm_hv, 2067 &vmstate_spapr_dtb, 2068 &vmstate_spapr_cap_large_decr, 2069 &vmstate_spapr_cap_ccf_assist, 2070 NULL 2071 } 2072 }; 2073 2074 static int htab_save_setup(QEMUFile *f, void *opaque) 2075 { 2076 SpaprMachineState *spapr = opaque; 2077 2078 /* "Iteration" header */ 2079 if (!spapr->htab_shift) { 2080 qemu_put_be32(f, -1); 2081 } else { 2082 qemu_put_be32(f, spapr->htab_shift); 2083 } 2084 2085 if (spapr->htab) { 2086 spapr->htab_save_index = 0; 2087 spapr->htab_first_pass = true; 2088 } else { 2089 if (spapr->htab_shift) { 2090 assert(kvm_enabled()); 2091 } 2092 } 2093 2094 2095 return 0; 2096 } 2097 2098 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2099 int chunkstart, int n_valid, int n_invalid) 2100 { 2101 qemu_put_be32(f, chunkstart); 2102 qemu_put_be16(f, n_valid); 2103 qemu_put_be16(f, n_invalid); 2104 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2105 HASH_PTE_SIZE_64 * n_valid); 2106 } 2107 2108 static void htab_save_end_marker(QEMUFile *f) 2109 { 2110 qemu_put_be32(f, 0); 2111 qemu_put_be16(f, 0); 2112 qemu_put_be16(f, 0); 2113 } 2114 2115 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2116 int64_t max_ns) 2117 { 2118 bool has_timeout = max_ns != -1; 2119 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2120 int index = spapr->htab_save_index; 2121 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2122 2123 assert(spapr->htab_first_pass); 2124 2125 do { 2126 int chunkstart; 2127 2128 /* Consume invalid HPTEs */ 2129 while ((index < htabslots) 2130 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2131 CLEAN_HPTE(HPTE(spapr->htab, index)); 2132 index++; 2133 } 2134 2135 /* Consume valid HPTEs */ 2136 chunkstart = index; 2137 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2138 && HPTE_VALID(HPTE(spapr->htab, index))) { 2139 CLEAN_HPTE(HPTE(spapr->htab, index)); 2140 index++; 2141 } 2142 2143 if (index > chunkstart) { 2144 int n_valid = index - chunkstart; 2145 2146 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2147 2148 if (has_timeout && 2149 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2150 break; 2151 } 2152 } 2153 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2154 2155 if (index >= htabslots) { 2156 assert(index == htabslots); 2157 index = 0; 2158 spapr->htab_first_pass = false; 2159 } 2160 spapr->htab_save_index = index; 2161 } 2162 2163 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2164 int64_t max_ns) 2165 { 2166 bool final = max_ns < 0; 2167 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2168 int examined = 0, sent = 0; 2169 int index = spapr->htab_save_index; 2170 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2171 2172 assert(!spapr->htab_first_pass); 2173 2174 do { 2175 int chunkstart, invalidstart; 2176 2177 /* Consume non-dirty HPTEs */ 2178 while ((index < htabslots) 2179 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2180 index++; 2181 examined++; 2182 } 2183 2184 chunkstart = index; 2185 /* Consume valid dirty HPTEs */ 2186 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2187 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2188 && HPTE_VALID(HPTE(spapr->htab, index))) { 2189 CLEAN_HPTE(HPTE(spapr->htab, index)); 2190 index++; 2191 examined++; 2192 } 2193 2194 invalidstart = index; 2195 /* Consume invalid dirty HPTEs */ 2196 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2197 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2198 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2199 CLEAN_HPTE(HPTE(spapr->htab, index)); 2200 index++; 2201 examined++; 2202 } 2203 2204 if (index > chunkstart) { 2205 int n_valid = invalidstart - chunkstart; 2206 int n_invalid = index - invalidstart; 2207 2208 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2209 sent += index - chunkstart; 2210 2211 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2212 break; 2213 } 2214 } 2215 2216 if (examined >= htabslots) { 2217 break; 2218 } 2219 2220 if (index >= htabslots) { 2221 assert(index == htabslots); 2222 index = 0; 2223 } 2224 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2225 2226 if (index >= htabslots) { 2227 assert(index == htabslots); 2228 index = 0; 2229 } 2230 2231 spapr->htab_save_index = index; 2232 2233 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2234 } 2235 2236 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2237 #define MAX_KVM_BUF_SIZE 2048 2238 2239 static int htab_save_iterate(QEMUFile *f, void *opaque) 2240 { 2241 SpaprMachineState *spapr = opaque; 2242 int fd; 2243 int rc = 0; 2244 2245 /* Iteration header */ 2246 if (!spapr->htab_shift) { 2247 qemu_put_be32(f, -1); 2248 return 1; 2249 } else { 2250 qemu_put_be32(f, 0); 2251 } 2252 2253 if (!spapr->htab) { 2254 assert(kvm_enabled()); 2255 2256 fd = get_htab_fd(spapr); 2257 if (fd < 0) { 2258 return fd; 2259 } 2260 2261 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2262 if (rc < 0) { 2263 return rc; 2264 } 2265 } else if (spapr->htab_first_pass) { 2266 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2267 } else { 2268 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2269 } 2270 2271 htab_save_end_marker(f); 2272 2273 return rc; 2274 } 2275 2276 static int htab_save_complete(QEMUFile *f, void *opaque) 2277 { 2278 SpaprMachineState *spapr = opaque; 2279 int fd; 2280 2281 /* Iteration header */ 2282 if (!spapr->htab_shift) { 2283 qemu_put_be32(f, -1); 2284 return 0; 2285 } else { 2286 qemu_put_be32(f, 0); 2287 } 2288 2289 if (!spapr->htab) { 2290 int rc; 2291 2292 assert(kvm_enabled()); 2293 2294 fd = get_htab_fd(spapr); 2295 if (fd < 0) { 2296 return fd; 2297 } 2298 2299 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2300 if (rc < 0) { 2301 return rc; 2302 } 2303 } else { 2304 if (spapr->htab_first_pass) { 2305 htab_save_first_pass(f, spapr, -1); 2306 } 2307 htab_save_later_pass(f, spapr, -1); 2308 } 2309 2310 /* End marker */ 2311 htab_save_end_marker(f); 2312 2313 return 0; 2314 } 2315 2316 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2317 { 2318 SpaprMachineState *spapr = opaque; 2319 uint32_t section_hdr; 2320 int fd = -1; 2321 Error *local_err = NULL; 2322 2323 if (version_id < 1 || version_id > 1) { 2324 error_report("htab_load() bad version"); 2325 return -EINVAL; 2326 } 2327 2328 section_hdr = qemu_get_be32(f); 2329 2330 if (section_hdr == -1) { 2331 spapr_free_hpt(spapr); 2332 return 0; 2333 } 2334 2335 if (section_hdr) { 2336 /* First section gives the htab size */ 2337 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2338 if (local_err) { 2339 error_report_err(local_err); 2340 return -EINVAL; 2341 } 2342 return 0; 2343 } 2344 2345 if (!spapr->htab) { 2346 assert(kvm_enabled()); 2347 2348 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2349 if (fd < 0) { 2350 error_report_err(local_err); 2351 return fd; 2352 } 2353 } 2354 2355 while (true) { 2356 uint32_t index; 2357 uint16_t n_valid, n_invalid; 2358 2359 index = qemu_get_be32(f); 2360 n_valid = qemu_get_be16(f); 2361 n_invalid = qemu_get_be16(f); 2362 2363 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2364 /* End of Stream */ 2365 break; 2366 } 2367 2368 if ((index + n_valid + n_invalid) > 2369 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2370 /* Bad index in stream */ 2371 error_report( 2372 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2373 index, n_valid, n_invalid, spapr->htab_shift); 2374 return -EINVAL; 2375 } 2376 2377 if (spapr->htab) { 2378 if (n_valid) { 2379 qemu_get_buffer(f, HPTE(spapr->htab, index), 2380 HASH_PTE_SIZE_64 * n_valid); 2381 } 2382 if (n_invalid) { 2383 memset(HPTE(spapr->htab, index + n_valid), 0, 2384 HASH_PTE_SIZE_64 * n_invalid); 2385 } 2386 } else { 2387 int rc; 2388 2389 assert(fd >= 0); 2390 2391 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2392 if (rc < 0) { 2393 return rc; 2394 } 2395 } 2396 } 2397 2398 if (!spapr->htab) { 2399 assert(fd >= 0); 2400 close(fd); 2401 } 2402 2403 return 0; 2404 } 2405 2406 static void htab_save_cleanup(void *opaque) 2407 { 2408 SpaprMachineState *spapr = opaque; 2409 2410 close_htab_fd(spapr); 2411 } 2412 2413 static SaveVMHandlers savevm_htab_handlers = { 2414 .save_setup = htab_save_setup, 2415 .save_live_iterate = htab_save_iterate, 2416 .save_live_complete_precopy = htab_save_complete, 2417 .save_cleanup = htab_save_cleanup, 2418 .load_state = htab_load, 2419 }; 2420 2421 static void spapr_boot_set(void *opaque, const char *boot_device, 2422 Error **errp) 2423 { 2424 MachineState *machine = MACHINE(opaque); 2425 machine->boot_order = g_strdup(boot_device); 2426 } 2427 2428 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2429 { 2430 MachineState *machine = MACHINE(spapr); 2431 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2432 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2433 int i; 2434 2435 for (i = 0; i < nr_lmbs; i++) { 2436 uint64_t addr; 2437 2438 addr = i * lmb_size + machine->device_memory->base; 2439 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2440 addr / lmb_size); 2441 } 2442 } 2443 2444 /* 2445 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2446 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2447 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2448 */ 2449 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2450 { 2451 int i; 2452 2453 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2454 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2455 " is not aligned to %" PRIu64 " MiB", 2456 machine->ram_size, 2457 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2458 return; 2459 } 2460 2461 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2462 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2463 " is not aligned to %" PRIu64 " MiB", 2464 machine->ram_size, 2465 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2466 return; 2467 } 2468 2469 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2470 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2471 error_setg(errp, 2472 "Node %d memory size 0x%" PRIx64 2473 " is not aligned to %" PRIu64 " MiB", 2474 i, machine->numa_state->nodes[i].node_mem, 2475 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2476 return; 2477 } 2478 } 2479 } 2480 2481 /* find cpu slot in machine->possible_cpus by core_id */ 2482 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2483 { 2484 int index = id / ms->smp.threads; 2485 2486 if (index >= ms->possible_cpus->len) { 2487 return NULL; 2488 } 2489 if (idx) { 2490 *idx = index; 2491 } 2492 return &ms->possible_cpus->cpus[index]; 2493 } 2494 2495 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2496 { 2497 MachineState *ms = MACHINE(spapr); 2498 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2499 Error *local_err = NULL; 2500 bool vsmt_user = !!spapr->vsmt; 2501 int kvm_smt = kvmppc_smt_threads(); 2502 int ret; 2503 unsigned int smp_threads = ms->smp.threads; 2504 2505 if (!kvm_enabled() && (smp_threads > 1)) { 2506 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2507 "on a pseries machine"); 2508 goto out; 2509 } 2510 if (!is_power_of_2(smp_threads)) { 2511 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2512 "machine because it must be a power of 2", smp_threads); 2513 goto out; 2514 } 2515 2516 /* Detemine the VSMT mode to use: */ 2517 if (vsmt_user) { 2518 if (spapr->vsmt < smp_threads) { 2519 error_setg(&local_err, "Cannot support VSMT mode %d" 2520 " because it must be >= threads/core (%d)", 2521 spapr->vsmt, smp_threads); 2522 goto out; 2523 } 2524 /* In this case, spapr->vsmt has been set by the command line */ 2525 } else if (!smc->smp_threads_vsmt) { 2526 /* 2527 * Default VSMT value is tricky, because we need it to be as 2528 * consistent as possible (for migration), but this requires 2529 * changing it for at least some existing cases. We pick 8 as 2530 * the value that we'd get with KVM on POWER8, the 2531 * overwhelmingly common case in production systems. 2532 */ 2533 spapr->vsmt = MAX(8, smp_threads); 2534 } else { 2535 spapr->vsmt = smp_threads; 2536 } 2537 2538 /* KVM: If necessary, set the SMT mode: */ 2539 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2540 ret = kvmppc_set_smt_threads(spapr->vsmt); 2541 if (ret) { 2542 /* Looks like KVM isn't able to change VSMT mode */ 2543 error_setg(&local_err, 2544 "Failed to set KVM's VSMT mode to %d (errno %d)", 2545 spapr->vsmt, ret); 2546 /* We can live with that if the default one is big enough 2547 * for the number of threads, and a submultiple of the one 2548 * we want. In this case we'll waste some vcpu ids, but 2549 * behaviour will be correct */ 2550 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2551 warn_report_err(local_err); 2552 local_err = NULL; 2553 goto out; 2554 } else { 2555 if (!vsmt_user) { 2556 error_append_hint(&local_err, 2557 "On PPC, a VM with %d threads/core" 2558 " on a host with %d threads/core" 2559 " requires the use of VSMT mode %d.\n", 2560 smp_threads, kvm_smt, spapr->vsmt); 2561 } 2562 kvmppc_hint_smt_possible(&local_err); 2563 goto out; 2564 } 2565 } 2566 } 2567 /* else TCG: nothing to do currently */ 2568 out: 2569 error_propagate(errp, local_err); 2570 } 2571 2572 static void spapr_init_cpus(SpaprMachineState *spapr) 2573 { 2574 MachineState *machine = MACHINE(spapr); 2575 MachineClass *mc = MACHINE_GET_CLASS(machine); 2576 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2577 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2578 const CPUArchIdList *possible_cpus; 2579 unsigned int smp_cpus = machine->smp.cpus; 2580 unsigned int smp_threads = machine->smp.threads; 2581 unsigned int max_cpus = machine->smp.max_cpus; 2582 int boot_cores_nr = smp_cpus / smp_threads; 2583 int i; 2584 2585 possible_cpus = mc->possible_cpu_arch_ids(machine); 2586 if (mc->has_hotpluggable_cpus) { 2587 if (smp_cpus % smp_threads) { 2588 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2589 smp_cpus, smp_threads); 2590 exit(1); 2591 } 2592 if (max_cpus % smp_threads) { 2593 error_report("max_cpus (%u) must be multiple of threads (%u)", 2594 max_cpus, smp_threads); 2595 exit(1); 2596 } 2597 } else { 2598 if (max_cpus != smp_cpus) { 2599 error_report("This machine version does not support CPU hotplug"); 2600 exit(1); 2601 } 2602 boot_cores_nr = possible_cpus->len; 2603 } 2604 2605 if (smc->pre_2_10_has_unused_icps) { 2606 int i; 2607 2608 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2609 /* Dummy entries get deregistered when real ICPState objects 2610 * are registered during CPU core hotplug. 2611 */ 2612 pre_2_10_vmstate_register_dummy_icp(i); 2613 } 2614 } 2615 2616 for (i = 0; i < possible_cpus->len; i++) { 2617 int core_id = i * smp_threads; 2618 2619 if (mc->has_hotpluggable_cpus) { 2620 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2621 spapr_vcpu_id(spapr, core_id)); 2622 } 2623 2624 if (i < boot_cores_nr) { 2625 Object *core = object_new(type); 2626 int nr_threads = smp_threads; 2627 2628 /* Handle the partially filled core for older machine types */ 2629 if ((i + 1) * smp_threads >= smp_cpus) { 2630 nr_threads = smp_cpus - i * smp_threads; 2631 } 2632 2633 object_property_set_int(core, nr_threads, "nr-threads", 2634 &error_fatal); 2635 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2636 &error_fatal); 2637 object_property_set_bool(core, true, "realized", &error_fatal); 2638 2639 object_unref(core); 2640 } 2641 } 2642 } 2643 2644 static PCIHostState *spapr_create_default_phb(void) 2645 { 2646 DeviceState *dev; 2647 2648 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 2649 qdev_prop_set_uint32(dev, "index", 0); 2650 qdev_init_nofail(dev); 2651 2652 return PCI_HOST_BRIDGE(dev); 2653 } 2654 2655 /* pSeries LPAR / sPAPR hardware init */ 2656 static void spapr_machine_init(MachineState *machine) 2657 { 2658 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2659 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2660 const char *kernel_filename = machine->kernel_filename; 2661 const char *initrd_filename = machine->initrd_filename; 2662 PCIHostState *phb; 2663 int i; 2664 MemoryRegion *sysmem = get_system_memory(); 2665 MemoryRegion *ram = g_new(MemoryRegion, 1); 2666 hwaddr node0_size = spapr_node0_size(machine); 2667 long load_limit, fw_size; 2668 char *filename; 2669 Error *resize_hpt_err = NULL; 2670 2671 msi_nonbroken = true; 2672 2673 QLIST_INIT(&spapr->phbs); 2674 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2675 2676 /* Determine capabilities to run with */ 2677 spapr_caps_init(spapr); 2678 2679 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2680 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2681 /* 2682 * If the user explicitly requested a mode we should either 2683 * supply it, or fail completely (which we do below). But if 2684 * it's not set explicitly, we reset our mode to something 2685 * that works 2686 */ 2687 if (resize_hpt_err) { 2688 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2689 error_free(resize_hpt_err); 2690 resize_hpt_err = NULL; 2691 } else { 2692 spapr->resize_hpt = smc->resize_hpt_default; 2693 } 2694 } 2695 2696 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2697 2698 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2699 /* 2700 * User requested HPT resize, but this host can't supply it. Bail out 2701 */ 2702 error_report_err(resize_hpt_err); 2703 exit(1); 2704 } 2705 2706 spapr->rma_size = node0_size; 2707 2708 /* With KVM, we don't actually know whether KVM supports an 2709 * unbounded RMA (PR KVM) or is limited by the hash table size 2710 * (HV KVM using VRMA), so we always assume the latter 2711 * 2712 * In that case, we also limit the initial allocations for RTAS 2713 * etc... to 256M since we have no way to know what the VRMA size 2714 * is going to be as it depends on the size of the hash table 2715 * which isn't determined yet. 2716 */ 2717 if (kvm_enabled()) { 2718 spapr->vrma_adjust = 1; 2719 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2720 } 2721 2722 /* Actually we don't support unbounded RMA anymore since we added 2723 * proper emulation of HV mode. The max we can get is 16G which 2724 * also happens to be what we configure for PAPR mode so make sure 2725 * we don't do anything bigger than that 2726 */ 2727 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2728 2729 if (spapr->rma_size > node0_size) { 2730 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2731 spapr->rma_size); 2732 exit(1); 2733 } 2734 2735 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2736 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2737 2738 /* 2739 * VSMT must be set in order to be able to compute VCPU ids, ie to 2740 * call spapr_max_server_number() or spapr_vcpu_id(). 2741 */ 2742 spapr_set_vsmt_mode(spapr, &error_fatal); 2743 2744 /* Set up Interrupt Controller before we create the VCPUs */ 2745 spapr_irq_init(spapr, &error_fatal); 2746 2747 /* Set up containers for ibm,client-architecture-support negotiated options 2748 */ 2749 spapr->ov5 = spapr_ovec_new(); 2750 spapr->ov5_cas = spapr_ovec_new(); 2751 2752 if (smc->dr_lmb_enabled) { 2753 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2754 spapr_validate_node_memory(machine, &error_fatal); 2755 } 2756 2757 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2758 2759 /* advertise support for dedicated HP event source to guests */ 2760 if (spapr->use_hotplug_event_source) { 2761 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2762 } 2763 2764 /* advertise support for HPT resizing */ 2765 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2766 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2767 } 2768 2769 /* advertise support for ibm,dyamic-memory-v2 */ 2770 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2771 2772 /* advertise XIVE on POWER9 machines */ 2773 if (spapr->irq->xive) { 2774 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2775 } 2776 2777 /* init CPUs */ 2778 spapr_init_cpus(spapr); 2779 2780 /* 2781 * check we don't have a memory-less/cpu-less NUMA node 2782 * Firmware relies on the existing memory/cpu topology to provide the 2783 * NUMA topology to the kernel. 2784 * And the linux kernel needs to know the NUMA topology at start 2785 * to be able to hotplug CPUs later. 2786 */ 2787 if (machine->numa_state->num_nodes) { 2788 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2789 /* check for memory-less node */ 2790 if (machine->numa_state->nodes[i].node_mem == 0) { 2791 CPUState *cs; 2792 int found = 0; 2793 /* check for cpu-less node */ 2794 CPU_FOREACH(cs) { 2795 PowerPCCPU *cpu = POWERPC_CPU(cs); 2796 if (cpu->node_id == i) { 2797 found = 1; 2798 break; 2799 } 2800 } 2801 /* memory-less and cpu-less node */ 2802 if (!found) { 2803 error_report( 2804 "Memory-less/cpu-less nodes are not supported (node %d)", 2805 i); 2806 exit(1); 2807 } 2808 } 2809 } 2810 2811 } 2812 2813 /* 2814 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2815 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2816 * called from vPHB reset handler so we initialize the counter here. 2817 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2818 * must be equally distant from any other node. 2819 * The final value of spapr->gpu_numa_id is going to be written to 2820 * max-associativity-domains in spapr_build_fdt(). 2821 */ 2822 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2823 2824 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2825 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2826 spapr->max_compat_pvr)) { 2827 /* KVM and TCG always allow GTSE with radix... */ 2828 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2829 } 2830 /* ... but not with hash (currently). */ 2831 2832 if (kvm_enabled()) { 2833 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2834 kvmppc_enable_logical_ci_hcalls(); 2835 kvmppc_enable_set_mode_hcall(); 2836 2837 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2838 kvmppc_enable_clear_ref_mod_hcalls(); 2839 2840 /* Enable H_PAGE_INIT */ 2841 kvmppc_enable_h_page_init(); 2842 } 2843 2844 /* allocate RAM */ 2845 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2846 machine->ram_size); 2847 memory_region_add_subregion(sysmem, 0, ram); 2848 2849 /* always allocate the device memory information */ 2850 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2851 2852 /* initialize hotplug memory address space */ 2853 if (machine->ram_size < machine->maxram_size) { 2854 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2855 /* 2856 * Limit the number of hotpluggable memory slots to half the number 2857 * slots that KVM supports, leaving the other half for PCI and other 2858 * devices. However ensure that number of slots doesn't drop below 32. 2859 */ 2860 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2861 SPAPR_MAX_RAM_SLOTS; 2862 2863 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2864 max_memslots = SPAPR_MAX_RAM_SLOTS; 2865 } 2866 if (machine->ram_slots > max_memslots) { 2867 error_report("Specified number of memory slots %" 2868 PRIu64" exceeds max supported %d", 2869 machine->ram_slots, max_memslots); 2870 exit(1); 2871 } 2872 2873 machine->device_memory->base = ROUND_UP(machine->ram_size, 2874 SPAPR_DEVICE_MEM_ALIGN); 2875 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2876 "device-memory", device_mem_size); 2877 memory_region_add_subregion(sysmem, machine->device_memory->base, 2878 &machine->device_memory->mr); 2879 } 2880 2881 if (smc->dr_lmb_enabled) { 2882 spapr_create_lmb_dr_connectors(spapr); 2883 } 2884 2885 /* Set up RTAS event infrastructure */ 2886 spapr_events_init(spapr); 2887 2888 /* Set up the RTC RTAS interfaces */ 2889 spapr_rtc_create(spapr); 2890 2891 /* Set up VIO bus */ 2892 spapr->vio_bus = spapr_vio_bus_init(); 2893 2894 for (i = 0; i < serial_max_hds(); i++) { 2895 if (serial_hd(i)) { 2896 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2897 } 2898 } 2899 2900 /* We always have at least the nvram device on VIO */ 2901 spapr_create_nvram(spapr); 2902 2903 /* 2904 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2905 * connectors (described in root DT node's "ibm,drc-types" property) 2906 * are pre-initialized here. additional child connectors (such as 2907 * connectors for a PHBs PCI slots) are added as needed during their 2908 * parent's realization. 2909 */ 2910 if (smc->dr_phb_enabled) { 2911 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2912 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2913 } 2914 } 2915 2916 /* Set up PCI */ 2917 spapr_pci_rtas_init(); 2918 2919 phb = spapr_create_default_phb(); 2920 2921 for (i = 0; i < nb_nics; i++) { 2922 NICInfo *nd = &nd_table[i]; 2923 2924 if (!nd->model) { 2925 nd->model = g_strdup("spapr-vlan"); 2926 } 2927 2928 if (g_str_equal(nd->model, "spapr-vlan") || 2929 g_str_equal(nd->model, "ibmveth")) { 2930 spapr_vlan_create(spapr->vio_bus, nd); 2931 } else { 2932 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2933 } 2934 } 2935 2936 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2937 spapr_vscsi_create(spapr->vio_bus); 2938 } 2939 2940 /* Graphics */ 2941 if (spapr_vga_init(phb->bus, &error_fatal)) { 2942 spapr->has_graphics = true; 2943 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2944 } 2945 2946 if (machine->usb) { 2947 if (smc->use_ohci_by_default) { 2948 pci_create_simple(phb->bus, -1, "pci-ohci"); 2949 } else { 2950 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2951 } 2952 2953 if (spapr->has_graphics) { 2954 USBBus *usb_bus = usb_bus_find(-1); 2955 2956 usb_create_simple(usb_bus, "usb-kbd"); 2957 usb_create_simple(usb_bus, "usb-mouse"); 2958 } 2959 } 2960 2961 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) { 2962 error_report( 2963 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2964 MIN_RMA_SLOF); 2965 exit(1); 2966 } 2967 2968 if (kernel_filename) { 2969 uint64_t lowaddr = 0; 2970 2971 spapr->kernel_size = load_elf(kernel_filename, NULL, 2972 translate_kernel_address, NULL, 2973 NULL, &lowaddr, NULL, 1, 2974 PPC_ELF_MACHINE, 0, 0); 2975 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2976 spapr->kernel_size = load_elf(kernel_filename, NULL, 2977 translate_kernel_address, NULL, NULL, 2978 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2979 0, 0); 2980 spapr->kernel_le = spapr->kernel_size > 0; 2981 } 2982 if (spapr->kernel_size < 0) { 2983 error_report("error loading %s: %s", kernel_filename, 2984 load_elf_strerror(spapr->kernel_size)); 2985 exit(1); 2986 } 2987 2988 /* load initrd */ 2989 if (initrd_filename) { 2990 /* Try to locate the initrd in the gap between the kernel 2991 * and the firmware. Add a bit of space just in case 2992 */ 2993 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2994 + 0x1ffff) & ~0xffff; 2995 spapr->initrd_size = load_image_targphys(initrd_filename, 2996 spapr->initrd_base, 2997 load_limit 2998 - spapr->initrd_base); 2999 if (spapr->initrd_size < 0) { 3000 error_report("could not load initial ram disk '%s'", 3001 initrd_filename); 3002 exit(1); 3003 } 3004 } 3005 } 3006 3007 if (bios_name == NULL) { 3008 bios_name = FW_FILE_NAME; 3009 } 3010 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 3011 if (!filename) { 3012 error_report("Could not find LPAR firmware '%s'", bios_name); 3013 exit(1); 3014 } 3015 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 3016 if (fw_size <= 0) { 3017 error_report("Could not load LPAR firmware '%s'", filename); 3018 exit(1); 3019 } 3020 g_free(filename); 3021 3022 /* FIXME: Should register things through the MachineState's qdev 3023 * interface, this is a legacy from the sPAPREnvironment structure 3024 * which predated MachineState but had a similar function */ 3025 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3026 register_savevm_live("spapr/htab", -1, 1, 3027 &savevm_htab_handlers, spapr); 3028 3029 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine), 3030 &error_fatal); 3031 3032 qemu_register_boot_set(spapr_boot_set, spapr); 3033 3034 /* 3035 * Nothing needs to be done to resume a suspended guest because 3036 * suspending does not change the machine state, so no need for 3037 * a ->wakeup method. 3038 */ 3039 qemu_register_wakeup_support(); 3040 3041 if (kvm_enabled()) { 3042 /* to stop and start vmclock */ 3043 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3044 &spapr->tb); 3045 3046 kvmppc_spapr_enable_inkernel_multitce(); 3047 } 3048 } 3049 3050 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3051 { 3052 if (!vm_type) { 3053 return 0; 3054 } 3055 3056 if (!strcmp(vm_type, "HV")) { 3057 return 1; 3058 } 3059 3060 if (!strcmp(vm_type, "PR")) { 3061 return 2; 3062 } 3063 3064 error_report("Unknown kvm-type specified '%s'", vm_type); 3065 exit(1); 3066 } 3067 3068 /* 3069 * Implementation of an interface to adjust firmware path 3070 * for the bootindex property handling. 3071 */ 3072 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3073 DeviceState *dev) 3074 { 3075 #define CAST(type, obj, name) \ 3076 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3077 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3078 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3079 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3080 3081 if (d) { 3082 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3083 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3084 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3085 3086 if (spapr) { 3087 /* 3088 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3089 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3090 * 0x8000 | (target << 8) | (bus << 5) | lun 3091 * (see the "Logical unit addressing format" table in SAM5) 3092 */ 3093 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3094 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3095 (uint64_t)id << 48); 3096 } else if (virtio) { 3097 /* 3098 * We use SRP luns of the form 01000000 | (target << 8) | lun 3099 * in the top 32 bits of the 64-bit LUN 3100 * Note: the quote above is from SLOF and it is wrong, 3101 * the actual binding is: 3102 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3103 */ 3104 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3105 if (d->lun >= 256) { 3106 /* Use the LUN "flat space addressing method" */ 3107 id |= 0x4000; 3108 } 3109 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3110 (uint64_t)id << 32); 3111 } else if (usb) { 3112 /* 3113 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3114 * in the top 32 bits of the 64-bit LUN 3115 */ 3116 unsigned usb_port = atoi(usb->port->path); 3117 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3118 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3119 (uint64_t)id << 32); 3120 } 3121 } 3122 3123 /* 3124 * SLOF probes the USB devices, and if it recognizes that the device is a 3125 * storage device, it changes its name to "storage" instead of "usb-host", 3126 * and additionally adds a child node for the SCSI LUN, so the correct 3127 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3128 */ 3129 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3130 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3131 if (usb_host_dev_is_scsi_storage(usbdev)) { 3132 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3133 } 3134 } 3135 3136 if (phb) { 3137 /* Replace "pci" with "pci@800000020000000" */ 3138 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3139 } 3140 3141 if (vsc) { 3142 /* Same logic as virtio above */ 3143 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3144 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3145 } 3146 3147 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3148 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3149 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3150 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3151 } 3152 3153 return NULL; 3154 } 3155 3156 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3157 { 3158 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3159 3160 return g_strdup(spapr->kvm_type); 3161 } 3162 3163 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3164 { 3165 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3166 3167 g_free(spapr->kvm_type); 3168 spapr->kvm_type = g_strdup(value); 3169 } 3170 3171 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3172 { 3173 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3174 3175 return spapr->use_hotplug_event_source; 3176 } 3177 3178 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3179 Error **errp) 3180 { 3181 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3182 3183 spapr->use_hotplug_event_source = value; 3184 } 3185 3186 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3187 { 3188 return true; 3189 } 3190 3191 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3192 { 3193 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3194 3195 switch (spapr->resize_hpt) { 3196 case SPAPR_RESIZE_HPT_DEFAULT: 3197 return g_strdup("default"); 3198 case SPAPR_RESIZE_HPT_DISABLED: 3199 return g_strdup("disabled"); 3200 case SPAPR_RESIZE_HPT_ENABLED: 3201 return g_strdup("enabled"); 3202 case SPAPR_RESIZE_HPT_REQUIRED: 3203 return g_strdup("required"); 3204 } 3205 g_assert_not_reached(); 3206 } 3207 3208 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3209 { 3210 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3211 3212 if (strcmp(value, "default") == 0) { 3213 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3214 } else if (strcmp(value, "disabled") == 0) { 3215 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3216 } else if (strcmp(value, "enabled") == 0) { 3217 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3218 } else if (strcmp(value, "required") == 0) { 3219 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3220 } else { 3221 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3222 } 3223 } 3224 3225 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3226 void *opaque, Error **errp) 3227 { 3228 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3229 } 3230 3231 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3232 void *opaque, Error **errp) 3233 { 3234 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3235 } 3236 3237 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3238 { 3239 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3240 3241 if (spapr->irq == &spapr_irq_xics_legacy) { 3242 return g_strdup("legacy"); 3243 } else if (spapr->irq == &spapr_irq_xics) { 3244 return g_strdup("xics"); 3245 } else if (spapr->irq == &spapr_irq_xive) { 3246 return g_strdup("xive"); 3247 } else if (spapr->irq == &spapr_irq_dual) { 3248 return g_strdup("dual"); 3249 } 3250 g_assert_not_reached(); 3251 } 3252 3253 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3254 { 3255 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3256 3257 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3258 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3259 return; 3260 } 3261 3262 /* The legacy IRQ backend can not be set */ 3263 if (strcmp(value, "xics") == 0) { 3264 spapr->irq = &spapr_irq_xics; 3265 } else if (strcmp(value, "xive") == 0) { 3266 spapr->irq = &spapr_irq_xive; 3267 } else if (strcmp(value, "dual") == 0) { 3268 spapr->irq = &spapr_irq_dual; 3269 } else { 3270 error_setg(errp, "Bad value for \"ic-mode\" property"); 3271 } 3272 } 3273 3274 static char *spapr_get_host_model(Object *obj, Error **errp) 3275 { 3276 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3277 3278 return g_strdup(spapr->host_model); 3279 } 3280 3281 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3282 { 3283 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3284 3285 g_free(spapr->host_model); 3286 spapr->host_model = g_strdup(value); 3287 } 3288 3289 static char *spapr_get_host_serial(Object *obj, Error **errp) 3290 { 3291 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3292 3293 return g_strdup(spapr->host_serial); 3294 } 3295 3296 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3297 { 3298 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3299 3300 g_free(spapr->host_serial); 3301 spapr->host_serial = g_strdup(value); 3302 } 3303 3304 static void spapr_instance_init(Object *obj) 3305 { 3306 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3307 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3308 3309 spapr->htab_fd = -1; 3310 spapr->use_hotplug_event_source = true; 3311 object_property_add_str(obj, "kvm-type", 3312 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3313 object_property_set_description(obj, "kvm-type", 3314 "Specifies the KVM virtualization mode (HV, PR)", 3315 NULL); 3316 object_property_add_bool(obj, "modern-hotplug-events", 3317 spapr_get_modern_hotplug_events, 3318 spapr_set_modern_hotplug_events, 3319 NULL); 3320 object_property_set_description(obj, "modern-hotplug-events", 3321 "Use dedicated hotplug event mechanism in" 3322 " place of standard EPOW events when possible" 3323 " (required for memory hot-unplug support)", 3324 NULL); 3325 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3326 "Maximum permitted CPU compatibility mode", 3327 &error_fatal); 3328 3329 object_property_add_str(obj, "resize-hpt", 3330 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3331 object_property_set_description(obj, "resize-hpt", 3332 "Resizing of the Hash Page Table (enabled, disabled, required)", 3333 NULL); 3334 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3335 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3336 object_property_set_description(obj, "vsmt", 3337 "Virtual SMT: KVM behaves as if this were" 3338 " the host's SMT mode", &error_abort); 3339 object_property_add_bool(obj, "vfio-no-msix-emulation", 3340 spapr_get_msix_emulation, NULL, NULL); 3341 3342 /* The machine class defines the default interrupt controller mode */ 3343 spapr->irq = smc->irq; 3344 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3345 spapr_set_ic_mode, NULL); 3346 object_property_set_description(obj, "ic-mode", 3347 "Specifies the interrupt controller mode (xics, xive, dual)", 3348 NULL); 3349 3350 object_property_add_str(obj, "host-model", 3351 spapr_get_host_model, spapr_set_host_model, 3352 &error_abort); 3353 object_property_set_description(obj, "host-model", 3354 "Host model to advertise in guest device tree", &error_abort); 3355 object_property_add_str(obj, "host-serial", 3356 spapr_get_host_serial, spapr_set_host_serial, 3357 &error_abort); 3358 object_property_set_description(obj, "host-serial", 3359 "Host serial number to advertise in guest device tree", &error_abort); 3360 } 3361 3362 static void spapr_machine_finalizefn(Object *obj) 3363 { 3364 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3365 3366 g_free(spapr->kvm_type); 3367 } 3368 3369 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3370 { 3371 cpu_synchronize_state(cs); 3372 ppc_cpu_do_system_reset(cs); 3373 } 3374 3375 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3376 { 3377 CPUState *cs; 3378 3379 CPU_FOREACH(cs) { 3380 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3381 } 3382 } 3383 3384 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3385 void *fdt, int *fdt_start_offset, Error **errp) 3386 { 3387 uint64_t addr; 3388 uint32_t node; 3389 3390 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3391 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3392 &error_abort); 3393 *fdt_start_offset = spapr_populate_memory_node(fdt, node, addr, 3394 SPAPR_MEMORY_BLOCK_SIZE); 3395 return 0; 3396 } 3397 3398 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3399 bool dedicated_hp_event_source, Error **errp) 3400 { 3401 SpaprDrc *drc; 3402 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3403 int i; 3404 uint64_t addr = addr_start; 3405 bool hotplugged = spapr_drc_hotplugged(dev); 3406 Error *local_err = NULL; 3407 3408 for (i = 0; i < nr_lmbs; i++) { 3409 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3410 addr / SPAPR_MEMORY_BLOCK_SIZE); 3411 g_assert(drc); 3412 3413 spapr_drc_attach(drc, dev, &local_err); 3414 if (local_err) { 3415 while (addr > addr_start) { 3416 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3417 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3418 addr / SPAPR_MEMORY_BLOCK_SIZE); 3419 spapr_drc_detach(drc); 3420 } 3421 error_propagate(errp, local_err); 3422 return; 3423 } 3424 if (!hotplugged) { 3425 spapr_drc_reset(drc); 3426 } 3427 addr += SPAPR_MEMORY_BLOCK_SIZE; 3428 } 3429 /* send hotplug notification to the 3430 * guest only in case of hotplugged memory 3431 */ 3432 if (hotplugged) { 3433 if (dedicated_hp_event_source) { 3434 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3435 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3436 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3437 nr_lmbs, 3438 spapr_drc_index(drc)); 3439 } else { 3440 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3441 nr_lmbs); 3442 } 3443 } 3444 } 3445 3446 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3447 Error **errp) 3448 { 3449 Error *local_err = NULL; 3450 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3451 PCDIMMDevice *dimm = PC_DIMM(dev); 3452 uint64_t size, addr; 3453 3454 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3455 3456 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3457 if (local_err) { 3458 goto out; 3459 } 3460 3461 addr = object_property_get_uint(OBJECT(dimm), 3462 PC_DIMM_ADDR_PROP, &local_err); 3463 if (local_err) { 3464 goto out_unplug; 3465 } 3466 3467 spapr_add_lmbs(dev, addr, size, spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3468 &local_err); 3469 if (local_err) { 3470 goto out_unplug; 3471 } 3472 3473 return; 3474 3475 out_unplug: 3476 pc_dimm_unplug(dimm, MACHINE(ms)); 3477 out: 3478 error_propagate(errp, local_err); 3479 } 3480 3481 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3482 Error **errp) 3483 { 3484 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3485 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3486 PCDIMMDevice *dimm = PC_DIMM(dev); 3487 Error *local_err = NULL; 3488 uint64_t size; 3489 Object *memdev; 3490 hwaddr pagesize; 3491 3492 if (!smc->dr_lmb_enabled) { 3493 error_setg(errp, "Memory hotplug not supported for this machine"); 3494 return; 3495 } 3496 3497 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3498 if (local_err) { 3499 error_propagate(errp, local_err); 3500 return; 3501 } 3502 3503 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3504 error_setg(errp, "Hotplugged memory size must be a multiple of " 3505 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3506 return; 3507 } 3508 3509 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3510 &error_abort); 3511 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3512 spapr_check_pagesize(spapr, pagesize, &local_err); 3513 if (local_err) { 3514 error_propagate(errp, local_err); 3515 return; 3516 } 3517 3518 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3519 } 3520 3521 struct SpaprDimmState { 3522 PCDIMMDevice *dimm; 3523 uint32_t nr_lmbs; 3524 QTAILQ_ENTRY(SpaprDimmState) next; 3525 }; 3526 3527 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3528 PCDIMMDevice *dimm) 3529 { 3530 SpaprDimmState *dimm_state = NULL; 3531 3532 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3533 if (dimm_state->dimm == dimm) { 3534 break; 3535 } 3536 } 3537 return dimm_state; 3538 } 3539 3540 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3541 uint32_t nr_lmbs, 3542 PCDIMMDevice *dimm) 3543 { 3544 SpaprDimmState *ds = NULL; 3545 3546 /* 3547 * If this request is for a DIMM whose removal had failed earlier 3548 * (due to guest's refusal to remove the LMBs), we would have this 3549 * dimm already in the pending_dimm_unplugs list. In that 3550 * case don't add again. 3551 */ 3552 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3553 if (!ds) { 3554 ds = g_malloc0(sizeof(SpaprDimmState)); 3555 ds->nr_lmbs = nr_lmbs; 3556 ds->dimm = dimm; 3557 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3558 } 3559 return ds; 3560 } 3561 3562 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3563 SpaprDimmState *dimm_state) 3564 { 3565 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3566 g_free(dimm_state); 3567 } 3568 3569 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3570 PCDIMMDevice *dimm) 3571 { 3572 SpaprDrc *drc; 3573 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3574 &error_abort); 3575 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3576 uint32_t avail_lmbs = 0; 3577 uint64_t addr_start, addr; 3578 int i; 3579 3580 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3581 &error_abort); 3582 3583 addr = addr_start; 3584 for (i = 0; i < nr_lmbs; i++) { 3585 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3586 addr / SPAPR_MEMORY_BLOCK_SIZE); 3587 g_assert(drc); 3588 if (drc->dev) { 3589 avail_lmbs++; 3590 } 3591 addr += SPAPR_MEMORY_BLOCK_SIZE; 3592 } 3593 3594 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3595 } 3596 3597 /* Callback to be called during DRC release. */ 3598 void spapr_lmb_release(DeviceState *dev) 3599 { 3600 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3601 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3602 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3603 3604 /* This information will get lost if a migration occurs 3605 * during the unplug process. In this case recover it. */ 3606 if (ds == NULL) { 3607 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3608 g_assert(ds); 3609 /* The DRC being examined by the caller at least must be counted */ 3610 g_assert(ds->nr_lmbs); 3611 } 3612 3613 if (--ds->nr_lmbs) { 3614 return; 3615 } 3616 3617 /* 3618 * Now that all the LMBs have been removed by the guest, call the 3619 * unplug handler chain. This can never fail. 3620 */ 3621 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3622 object_unparent(OBJECT(dev)); 3623 } 3624 3625 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3626 { 3627 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3628 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3629 3630 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3631 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3632 spapr_pending_dimm_unplugs_remove(spapr, ds); 3633 } 3634 3635 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3636 DeviceState *dev, Error **errp) 3637 { 3638 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3639 Error *local_err = NULL; 3640 PCDIMMDevice *dimm = PC_DIMM(dev); 3641 uint32_t nr_lmbs; 3642 uint64_t size, addr_start, addr; 3643 int i; 3644 SpaprDrc *drc; 3645 3646 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3647 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3648 3649 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3650 &local_err); 3651 if (local_err) { 3652 goto out; 3653 } 3654 3655 /* 3656 * An existing pending dimm state for this DIMM means that there is an 3657 * unplug operation in progress, waiting for the spapr_lmb_release 3658 * callback to complete the job (BQL can't cover that far). In this case, 3659 * bail out to avoid detaching DRCs that were already released. 3660 */ 3661 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3662 error_setg(&local_err, 3663 "Memory unplug already in progress for device %s", 3664 dev->id); 3665 goto out; 3666 } 3667 3668 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3669 3670 addr = addr_start; 3671 for (i = 0; i < nr_lmbs; i++) { 3672 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3673 addr / SPAPR_MEMORY_BLOCK_SIZE); 3674 g_assert(drc); 3675 3676 spapr_drc_detach(drc); 3677 addr += SPAPR_MEMORY_BLOCK_SIZE; 3678 } 3679 3680 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3681 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3682 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3683 nr_lmbs, spapr_drc_index(drc)); 3684 out: 3685 error_propagate(errp, local_err); 3686 } 3687 3688 /* Callback to be called during DRC release. */ 3689 void spapr_core_release(DeviceState *dev) 3690 { 3691 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3692 3693 /* Call the unplug handler chain. This can never fail. */ 3694 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3695 object_unparent(OBJECT(dev)); 3696 } 3697 3698 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3699 { 3700 MachineState *ms = MACHINE(hotplug_dev); 3701 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3702 CPUCore *cc = CPU_CORE(dev); 3703 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3704 3705 if (smc->pre_2_10_has_unused_icps) { 3706 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3707 int i; 3708 3709 for (i = 0; i < cc->nr_threads; i++) { 3710 CPUState *cs = CPU(sc->threads[i]); 3711 3712 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3713 } 3714 } 3715 3716 assert(core_slot); 3717 core_slot->cpu = NULL; 3718 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3719 } 3720 3721 static 3722 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3723 Error **errp) 3724 { 3725 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3726 int index; 3727 SpaprDrc *drc; 3728 CPUCore *cc = CPU_CORE(dev); 3729 3730 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3731 error_setg(errp, "Unable to find CPU core with core-id: %d", 3732 cc->core_id); 3733 return; 3734 } 3735 if (index == 0) { 3736 error_setg(errp, "Boot CPU core may not be unplugged"); 3737 return; 3738 } 3739 3740 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3741 spapr_vcpu_id(spapr, cc->core_id)); 3742 g_assert(drc); 3743 3744 if (!spapr_drc_unplug_requested(drc)) { 3745 spapr_drc_detach(drc); 3746 spapr_hotplug_req_remove_by_index(drc); 3747 } 3748 } 3749 3750 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3751 void *fdt, int *fdt_start_offset, Error **errp) 3752 { 3753 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3754 CPUState *cs = CPU(core->threads[0]); 3755 PowerPCCPU *cpu = POWERPC_CPU(cs); 3756 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3757 int id = spapr_get_vcpu_id(cpu); 3758 char *nodename; 3759 int offset; 3760 3761 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3762 offset = fdt_add_subnode(fdt, 0, nodename); 3763 g_free(nodename); 3764 3765 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3766 3767 *fdt_start_offset = offset; 3768 return 0; 3769 } 3770 3771 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3772 Error **errp) 3773 { 3774 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3775 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3776 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3777 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3778 CPUCore *cc = CPU_CORE(dev); 3779 CPUState *cs; 3780 SpaprDrc *drc; 3781 Error *local_err = NULL; 3782 CPUArchId *core_slot; 3783 int index; 3784 bool hotplugged = spapr_drc_hotplugged(dev); 3785 int i; 3786 3787 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3788 if (!core_slot) { 3789 error_setg(errp, "Unable to find CPU core with core-id: %d", 3790 cc->core_id); 3791 return; 3792 } 3793 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3794 spapr_vcpu_id(spapr, cc->core_id)); 3795 3796 g_assert(drc || !mc->has_hotpluggable_cpus); 3797 3798 if (drc) { 3799 spapr_drc_attach(drc, dev, &local_err); 3800 if (local_err) { 3801 error_propagate(errp, local_err); 3802 return; 3803 } 3804 3805 if (hotplugged) { 3806 /* 3807 * Send hotplug notification interrupt to the guest only 3808 * in case of hotplugged CPUs. 3809 */ 3810 spapr_hotplug_req_add_by_index(drc); 3811 } else { 3812 spapr_drc_reset(drc); 3813 } 3814 } 3815 3816 core_slot->cpu = OBJECT(dev); 3817 3818 if (smc->pre_2_10_has_unused_icps) { 3819 for (i = 0; i < cc->nr_threads; i++) { 3820 cs = CPU(core->threads[i]); 3821 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3822 } 3823 } 3824 3825 /* 3826 * Set compatibility mode to match the boot CPU, which was either set 3827 * by the machine reset code or by CAS. 3828 */ 3829 if (hotplugged) { 3830 for (i = 0; i < cc->nr_threads; i++) { 3831 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3832 &local_err); 3833 if (local_err) { 3834 error_propagate(errp, local_err); 3835 return; 3836 } 3837 } 3838 } 3839 } 3840 3841 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3842 Error **errp) 3843 { 3844 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3845 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3846 Error *local_err = NULL; 3847 CPUCore *cc = CPU_CORE(dev); 3848 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3849 const char *type = object_get_typename(OBJECT(dev)); 3850 CPUArchId *core_slot; 3851 int index; 3852 unsigned int smp_threads = machine->smp.threads; 3853 3854 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3855 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3856 goto out; 3857 } 3858 3859 if (strcmp(base_core_type, type)) { 3860 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3861 goto out; 3862 } 3863 3864 if (cc->core_id % smp_threads) { 3865 error_setg(&local_err, "invalid core id %d", cc->core_id); 3866 goto out; 3867 } 3868 3869 /* 3870 * In general we should have homogeneous threads-per-core, but old 3871 * (pre hotplug support) machine types allow the last core to have 3872 * reduced threads as a compatibility hack for when we allowed 3873 * total vcpus not a multiple of threads-per-core. 3874 */ 3875 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3876 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3877 cc->nr_threads, smp_threads); 3878 goto out; 3879 } 3880 3881 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3882 if (!core_slot) { 3883 error_setg(&local_err, "core id %d out of range", cc->core_id); 3884 goto out; 3885 } 3886 3887 if (core_slot->cpu) { 3888 error_setg(&local_err, "core %d already populated", cc->core_id); 3889 goto out; 3890 } 3891 3892 numa_cpu_pre_plug(core_slot, dev, &local_err); 3893 3894 out: 3895 error_propagate(errp, local_err); 3896 } 3897 3898 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3899 void *fdt, int *fdt_start_offset, Error **errp) 3900 { 3901 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3902 int intc_phandle; 3903 3904 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3905 if (intc_phandle <= 0) { 3906 return -1; 3907 } 3908 3909 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3910 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3911 return -1; 3912 } 3913 3914 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3915 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3916 3917 return 0; 3918 } 3919 3920 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3921 Error **errp) 3922 { 3923 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3924 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3925 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3926 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3927 3928 if (dev->hotplugged && !smc->dr_phb_enabled) { 3929 error_setg(errp, "PHB hotplug not supported for this machine"); 3930 return; 3931 } 3932 3933 if (sphb->index == (uint32_t)-1) { 3934 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3935 return; 3936 } 3937 3938 /* 3939 * This will check that sphb->index doesn't exceed the maximum number of 3940 * PHBs for the current machine type. 3941 */ 3942 smc->phb_placement(spapr, sphb->index, 3943 &sphb->buid, &sphb->io_win_addr, 3944 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3945 windows_supported, sphb->dma_liobn, 3946 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3947 errp); 3948 } 3949 3950 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3951 Error **errp) 3952 { 3953 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3954 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3955 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3956 SpaprDrc *drc; 3957 bool hotplugged = spapr_drc_hotplugged(dev); 3958 Error *local_err = NULL; 3959 3960 if (!smc->dr_phb_enabled) { 3961 return; 3962 } 3963 3964 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3965 /* hotplug hooks should check it's enabled before getting this far */ 3966 assert(drc); 3967 3968 spapr_drc_attach(drc, DEVICE(dev), &local_err); 3969 if (local_err) { 3970 error_propagate(errp, local_err); 3971 return; 3972 } 3973 3974 if (hotplugged) { 3975 spapr_hotplug_req_add_by_index(drc); 3976 } else { 3977 spapr_drc_reset(drc); 3978 } 3979 } 3980 3981 void spapr_phb_release(DeviceState *dev) 3982 { 3983 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3984 3985 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3986 object_unparent(OBJECT(dev)); 3987 } 3988 3989 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3990 { 3991 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3992 } 3993 3994 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 3995 DeviceState *dev, Error **errp) 3996 { 3997 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3998 SpaprDrc *drc; 3999 4000 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4001 assert(drc); 4002 4003 if (!spapr_drc_unplug_requested(drc)) { 4004 spapr_drc_detach(drc); 4005 spapr_hotplug_req_remove_by_index(drc); 4006 } 4007 } 4008 4009 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4010 Error **errp) 4011 { 4012 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4013 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4014 4015 if (spapr->tpm_proxy != NULL) { 4016 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4017 return; 4018 } 4019 4020 spapr->tpm_proxy = tpm_proxy; 4021 } 4022 4023 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4024 { 4025 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4026 4027 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 4028 object_unparent(OBJECT(dev)); 4029 spapr->tpm_proxy = NULL; 4030 } 4031 4032 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4033 DeviceState *dev, Error **errp) 4034 { 4035 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4036 spapr_memory_plug(hotplug_dev, dev, errp); 4037 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4038 spapr_core_plug(hotplug_dev, dev, errp); 4039 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4040 spapr_phb_plug(hotplug_dev, dev, errp); 4041 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4042 spapr_tpm_proxy_plug(hotplug_dev, dev, errp); 4043 } 4044 } 4045 4046 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4047 DeviceState *dev, Error **errp) 4048 { 4049 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4050 spapr_memory_unplug(hotplug_dev, dev); 4051 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4052 spapr_core_unplug(hotplug_dev, dev); 4053 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4054 spapr_phb_unplug(hotplug_dev, dev); 4055 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4056 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4057 } 4058 } 4059 4060 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4061 DeviceState *dev, Error **errp) 4062 { 4063 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4064 MachineClass *mc = MACHINE_GET_CLASS(sms); 4065 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4066 4067 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4068 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 4069 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4070 } else { 4071 /* NOTE: this means there is a window after guest reset, prior to 4072 * CAS negotiation, where unplug requests will fail due to the 4073 * capability not being detected yet. This is a bit different than 4074 * the case with PCI unplug, where the events will be queued and 4075 * eventually handled by the guest after boot 4076 */ 4077 error_setg(errp, "Memory hot unplug not supported for this guest"); 4078 } 4079 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4080 if (!mc->has_hotpluggable_cpus) { 4081 error_setg(errp, "CPU hot unplug not supported on this machine"); 4082 return; 4083 } 4084 spapr_core_unplug_request(hotplug_dev, dev, errp); 4085 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4086 if (!smc->dr_phb_enabled) { 4087 error_setg(errp, "PHB hot unplug not supported on this machine"); 4088 return; 4089 } 4090 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4091 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4092 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4093 } 4094 } 4095 4096 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4097 DeviceState *dev, Error **errp) 4098 { 4099 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4100 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4101 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4102 spapr_core_pre_plug(hotplug_dev, dev, errp); 4103 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4104 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4105 } 4106 } 4107 4108 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4109 DeviceState *dev) 4110 { 4111 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4112 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4113 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4114 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4115 return HOTPLUG_HANDLER(machine); 4116 } 4117 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4118 PCIDevice *pcidev = PCI_DEVICE(dev); 4119 PCIBus *root = pci_device_root_bus(pcidev); 4120 SpaprPhbState *phb = 4121 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4122 TYPE_SPAPR_PCI_HOST_BRIDGE); 4123 4124 if (phb) { 4125 return HOTPLUG_HANDLER(phb); 4126 } 4127 } 4128 return NULL; 4129 } 4130 4131 static CpuInstanceProperties 4132 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4133 { 4134 CPUArchId *core_slot; 4135 MachineClass *mc = MACHINE_GET_CLASS(machine); 4136 4137 /* make sure possible_cpu are intialized */ 4138 mc->possible_cpu_arch_ids(machine); 4139 /* get CPU core slot containing thread that matches cpu_index */ 4140 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4141 assert(core_slot); 4142 return core_slot->props; 4143 } 4144 4145 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4146 { 4147 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4148 } 4149 4150 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4151 { 4152 int i; 4153 unsigned int smp_threads = machine->smp.threads; 4154 unsigned int smp_cpus = machine->smp.cpus; 4155 const char *core_type; 4156 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4157 MachineClass *mc = MACHINE_GET_CLASS(machine); 4158 4159 if (!mc->has_hotpluggable_cpus) { 4160 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4161 } 4162 if (machine->possible_cpus) { 4163 assert(machine->possible_cpus->len == spapr_max_cores); 4164 return machine->possible_cpus; 4165 } 4166 4167 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4168 if (!core_type) { 4169 error_report("Unable to find sPAPR CPU Core definition"); 4170 exit(1); 4171 } 4172 4173 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4174 sizeof(CPUArchId) * spapr_max_cores); 4175 machine->possible_cpus->len = spapr_max_cores; 4176 for (i = 0; i < machine->possible_cpus->len; i++) { 4177 int core_id = i * smp_threads; 4178 4179 machine->possible_cpus->cpus[i].type = core_type; 4180 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4181 machine->possible_cpus->cpus[i].arch_id = core_id; 4182 machine->possible_cpus->cpus[i].props.has_core_id = true; 4183 machine->possible_cpus->cpus[i].props.core_id = core_id; 4184 } 4185 return machine->possible_cpus; 4186 } 4187 4188 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4189 uint64_t *buid, hwaddr *pio, 4190 hwaddr *mmio32, hwaddr *mmio64, 4191 unsigned n_dma, uint32_t *liobns, 4192 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4193 { 4194 /* 4195 * New-style PHB window placement. 4196 * 4197 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4198 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4199 * windows. 4200 * 4201 * Some guest kernels can't work with MMIO windows above 1<<46 4202 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4203 * 4204 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4205 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4206 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4207 * 1TiB 64-bit MMIO windows for each PHB. 4208 */ 4209 const uint64_t base_buid = 0x800000020000000ULL; 4210 int i; 4211 4212 /* Sanity check natural alignments */ 4213 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4214 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4215 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4216 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4217 /* Sanity check bounds */ 4218 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4219 SPAPR_PCI_MEM32_WIN_SIZE); 4220 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4221 SPAPR_PCI_MEM64_WIN_SIZE); 4222 4223 if (index >= SPAPR_MAX_PHBS) { 4224 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4225 SPAPR_MAX_PHBS - 1); 4226 return; 4227 } 4228 4229 *buid = base_buid + index; 4230 for (i = 0; i < n_dma; ++i) { 4231 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4232 } 4233 4234 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4235 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4236 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4237 4238 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4239 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4240 } 4241 4242 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4243 { 4244 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4245 4246 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4247 } 4248 4249 static void spapr_ics_resend(XICSFabric *dev) 4250 { 4251 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4252 4253 ics_resend(spapr->ics); 4254 } 4255 4256 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4257 { 4258 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4259 4260 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4261 } 4262 4263 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4264 Monitor *mon) 4265 { 4266 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4267 4268 spapr_irq_print_info(spapr, mon); 4269 monitor_printf(mon, "irqchip: %s\n", 4270 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4271 } 4272 4273 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4274 { 4275 return cpu->vcpu_id; 4276 } 4277 4278 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4279 { 4280 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4281 MachineState *ms = MACHINE(spapr); 4282 int vcpu_id; 4283 4284 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4285 4286 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4287 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4288 error_append_hint(errp, "Adjust the number of cpus to %d " 4289 "or try to raise the number of threads per core\n", 4290 vcpu_id * ms->smp.threads / spapr->vsmt); 4291 return; 4292 } 4293 4294 cpu->vcpu_id = vcpu_id; 4295 } 4296 4297 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4298 { 4299 CPUState *cs; 4300 4301 CPU_FOREACH(cs) { 4302 PowerPCCPU *cpu = POWERPC_CPU(cs); 4303 4304 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4305 return cpu; 4306 } 4307 } 4308 4309 return NULL; 4310 } 4311 4312 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4313 { 4314 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4315 4316 /* These are only called by TCG, KVM maintains dispatch state */ 4317 4318 spapr_cpu->prod = false; 4319 if (spapr_cpu->vpa_addr) { 4320 CPUState *cs = CPU(cpu); 4321 uint32_t dispatch; 4322 4323 dispatch = ldl_be_phys(cs->as, 4324 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4325 dispatch++; 4326 if ((dispatch & 1) != 0) { 4327 qemu_log_mask(LOG_GUEST_ERROR, 4328 "VPA: incorrect dispatch counter value for " 4329 "dispatched partition %u, correcting.\n", dispatch); 4330 dispatch++; 4331 } 4332 stl_be_phys(cs->as, 4333 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4334 } 4335 } 4336 4337 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4338 { 4339 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4340 4341 if (spapr_cpu->vpa_addr) { 4342 CPUState *cs = CPU(cpu); 4343 uint32_t dispatch; 4344 4345 dispatch = ldl_be_phys(cs->as, 4346 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4347 dispatch++; 4348 if ((dispatch & 1) != 1) { 4349 qemu_log_mask(LOG_GUEST_ERROR, 4350 "VPA: incorrect dispatch counter value for " 4351 "preempted partition %u, correcting.\n", dispatch); 4352 dispatch++; 4353 } 4354 stl_be_phys(cs->as, 4355 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4356 } 4357 } 4358 4359 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4360 { 4361 MachineClass *mc = MACHINE_CLASS(oc); 4362 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4363 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4364 NMIClass *nc = NMI_CLASS(oc); 4365 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4366 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4367 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4368 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4369 4370 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4371 mc->ignore_boot_device_suffixes = true; 4372 4373 /* 4374 * We set up the default / latest behaviour here. The class_init 4375 * functions for the specific versioned machine types can override 4376 * these details for backwards compatibility 4377 */ 4378 mc->init = spapr_machine_init; 4379 mc->reset = spapr_machine_reset; 4380 mc->block_default_type = IF_SCSI; 4381 mc->max_cpus = 1024; 4382 mc->no_parallel = 1; 4383 mc->default_boot_order = ""; 4384 mc->default_ram_size = 512 * MiB; 4385 mc->default_display = "std"; 4386 mc->kvm_type = spapr_kvm_type; 4387 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4388 mc->pci_allow_0_address = true; 4389 assert(!mc->get_hotplug_handler); 4390 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4391 hc->pre_plug = spapr_machine_device_pre_plug; 4392 hc->plug = spapr_machine_device_plug; 4393 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4394 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4395 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4396 hc->unplug_request = spapr_machine_device_unplug_request; 4397 hc->unplug = spapr_machine_device_unplug; 4398 4399 smc->dr_lmb_enabled = true; 4400 smc->update_dt_enabled = true; 4401 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4402 mc->has_hotpluggable_cpus = true; 4403 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4404 fwc->get_dev_path = spapr_get_fw_dev_path; 4405 nc->nmi_monitor_handler = spapr_nmi; 4406 smc->phb_placement = spapr_phb_placement; 4407 vhc->hypercall = emulate_spapr_hypercall; 4408 vhc->hpt_mask = spapr_hpt_mask; 4409 vhc->map_hptes = spapr_map_hptes; 4410 vhc->unmap_hptes = spapr_unmap_hptes; 4411 vhc->hpte_set_c = spapr_hpte_set_c; 4412 vhc->hpte_set_r = spapr_hpte_set_r; 4413 vhc->get_pate = spapr_get_pate; 4414 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4415 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4416 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4417 xic->ics_get = spapr_ics_get; 4418 xic->ics_resend = spapr_ics_resend; 4419 xic->icp_get = spapr_icp_get; 4420 ispc->print_info = spapr_pic_print_info; 4421 /* Force NUMA node memory size to be a multiple of 4422 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4423 * in which LMBs are represented and hot-added 4424 */ 4425 mc->numa_mem_align_shift = 28; 4426 mc->numa_mem_supported = true; 4427 mc->auto_enable_numa = true; 4428 4429 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4430 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4431 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4432 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4433 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4434 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4435 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4436 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4437 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4438 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4439 spapr_caps_add_properties(smc, &error_abort); 4440 smc->irq = &spapr_irq_dual; 4441 smc->dr_phb_enabled = true; 4442 smc->linux_pci_probe = true; 4443 smc->smp_threads_vsmt = true; 4444 smc->nr_xirqs = SPAPR_NR_XIRQS; 4445 } 4446 4447 static const TypeInfo spapr_machine_info = { 4448 .name = TYPE_SPAPR_MACHINE, 4449 .parent = TYPE_MACHINE, 4450 .abstract = true, 4451 .instance_size = sizeof(SpaprMachineState), 4452 .instance_init = spapr_instance_init, 4453 .instance_finalize = spapr_machine_finalizefn, 4454 .class_size = sizeof(SpaprMachineClass), 4455 .class_init = spapr_machine_class_init, 4456 .interfaces = (InterfaceInfo[]) { 4457 { TYPE_FW_PATH_PROVIDER }, 4458 { TYPE_NMI }, 4459 { TYPE_HOTPLUG_HANDLER }, 4460 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4461 { TYPE_XICS_FABRIC }, 4462 { TYPE_INTERRUPT_STATS_PROVIDER }, 4463 { } 4464 }, 4465 }; 4466 4467 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4468 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4469 void *data) \ 4470 { \ 4471 MachineClass *mc = MACHINE_CLASS(oc); \ 4472 spapr_machine_##suffix##_class_options(mc); \ 4473 if (latest) { \ 4474 mc->alias = "pseries"; \ 4475 mc->is_default = 1; \ 4476 } \ 4477 } \ 4478 static const TypeInfo spapr_machine_##suffix##_info = { \ 4479 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4480 .parent = TYPE_SPAPR_MACHINE, \ 4481 .class_init = spapr_machine_##suffix##_class_init, \ 4482 }; \ 4483 static void spapr_machine_register_##suffix(void) \ 4484 { \ 4485 type_register(&spapr_machine_##suffix##_info); \ 4486 } \ 4487 type_init(spapr_machine_register_##suffix) 4488 4489 /* 4490 * pseries-4.2 4491 */ 4492 static void spapr_machine_4_2_class_options(MachineClass *mc) 4493 { 4494 /* Defaults for the latest behaviour inherited from the base class */ 4495 } 4496 4497 DEFINE_SPAPR_MACHINE(4_2, "4.2", true); 4498 4499 /* 4500 * pseries-4.1 4501 */ 4502 static void spapr_machine_4_1_class_options(MachineClass *mc) 4503 { 4504 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4505 static GlobalProperty compat[] = { 4506 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4507 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4508 }; 4509 4510 spapr_machine_4_2_class_options(mc); 4511 smc->linux_pci_probe = false; 4512 smc->smp_threads_vsmt = false; 4513 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4514 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4515 } 4516 4517 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4518 4519 /* 4520 * pseries-4.0 4521 */ 4522 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4523 uint64_t *buid, hwaddr *pio, 4524 hwaddr *mmio32, hwaddr *mmio64, 4525 unsigned n_dma, uint32_t *liobns, 4526 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4527 { 4528 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, 4529 nv2gpa, nv2atsd, errp); 4530 *nv2gpa = 0; 4531 *nv2atsd = 0; 4532 } 4533 4534 static void spapr_machine_4_0_class_options(MachineClass *mc) 4535 { 4536 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4537 4538 spapr_machine_4_1_class_options(mc); 4539 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4540 smc->phb_placement = phb_placement_4_0; 4541 smc->irq = &spapr_irq_xics; 4542 smc->pre_4_1_migration = true; 4543 } 4544 4545 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4546 4547 /* 4548 * pseries-3.1 4549 */ 4550 static void spapr_machine_3_1_class_options(MachineClass *mc) 4551 { 4552 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4553 4554 spapr_machine_4_0_class_options(mc); 4555 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4556 4557 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4558 smc->update_dt_enabled = false; 4559 smc->dr_phb_enabled = false; 4560 smc->broken_host_serial_model = true; 4561 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4562 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4563 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4564 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4565 } 4566 4567 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4568 4569 /* 4570 * pseries-3.0 4571 */ 4572 4573 static void spapr_machine_3_0_class_options(MachineClass *mc) 4574 { 4575 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4576 4577 spapr_machine_3_1_class_options(mc); 4578 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4579 4580 smc->legacy_irq_allocation = true; 4581 smc->nr_xirqs = 0x400; 4582 smc->irq = &spapr_irq_xics_legacy; 4583 } 4584 4585 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4586 4587 /* 4588 * pseries-2.12 4589 */ 4590 static void spapr_machine_2_12_class_options(MachineClass *mc) 4591 { 4592 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4593 static GlobalProperty compat[] = { 4594 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4595 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4596 }; 4597 4598 spapr_machine_3_0_class_options(mc); 4599 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4600 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4601 4602 /* We depend on kvm_enabled() to choose a default value for the 4603 * hpt-max-page-size capability. Of course we can't do it here 4604 * because this is too early and the HW accelerator isn't initialzed 4605 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4606 */ 4607 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4608 } 4609 4610 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4611 4612 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4613 { 4614 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4615 4616 spapr_machine_2_12_class_options(mc); 4617 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4618 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4619 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4620 } 4621 4622 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4623 4624 /* 4625 * pseries-2.11 4626 */ 4627 4628 static void spapr_machine_2_11_class_options(MachineClass *mc) 4629 { 4630 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4631 4632 spapr_machine_2_12_class_options(mc); 4633 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4634 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4635 } 4636 4637 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4638 4639 /* 4640 * pseries-2.10 4641 */ 4642 4643 static void spapr_machine_2_10_class_options(MachineClass *mc) 4644 { 4645 spapr_machine_2_11_class_options(mc); 4646 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4647 } 4648 4649 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4650 4651 /* 4652 * pseries-2.9 4653 */ 4654 4655 static void spapr_machine_2_9_class_options(MachineClass *mc) 4656 { 4657 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4658 static GlobalProperty compat[] = { 4659 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4660 }; 4661 4662 spapr_machine_2_10_class_options(mc); 4663 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4664 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4665 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4666 smc->pre_2_10_has_unused_icps = true; 4667 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4668 } 4669 4670 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4671 4672 /* 4673 * pseries-2.8 4674 */ 4675 4676 static void spapr_machine_2_8_class_options(MachineClass *mc) 4677 { 4678 static GlobalProperty compat[] = { 4679 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4680 }; 4681 4682 spapr_machine_2_9_class_options(mc); 4683 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4684 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4685 mc->numa_mem_align_shift = 23; 4686 } 4687 4688 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4689 4690 /* 4691 * pseries-2.7 4692 */ 4693 4694 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4695 uint64_t *buid, hwaddr *pio, 4696 hwaddr *mmio32, hwaddr *mmio64, 4697 unsigned n_dma, uint32_t *liobns, 4698 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4699 { 4700 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4701 const uint64_t base_buid = 0x800000020000000ULL; 4702 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4703 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4704 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4705 const uint32_t max_index = 255; 4706 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4707 4708 uint64_t ram_top = MACHINE(spapr)->ram_size; 4709 hwaddr phb0_base, phb_base; 4710 int i; 4711 4712 /* Do we have device memory? */ 4713 if (MACHINE(spapr)->maxram_size > ram_top) { 4714 /* Can't just use maxram_size, because there may be an 4715 * alignment gap between normal and device memory regions 4716 */ 4717 ram_top = MACHINE(spapr)->device_memory->base + 4718 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4719 } 4720 4721 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4722 4723 if (index > max_index) { 4724 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4725 max_index); 4726 return; 4727 } 4728 4729 *buid = base_buid + index; 4730 for (i = 0; i < n_dma; ++i) { 4731 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4732 } 4733 4734 phb_base = phb0_base + index * phb_spacing; 4735 *pio = phb_base + pio_offset; 4736 *mmio32 = phb_base + mmio_offset; 4737 /* 4738 * We don't set the 64-bit MMIO window, relying on the PHB's 4739 * fallback behaviour of automatically splitting a large "32-bit" 4740 * window into contiguous 32-bit and 64-bit windows 4741 */ 4742 4743 *nv2gpa = 0; 4744 *nv2atsd = 0; 4745 } 4746 4747 static void spapr_machine_2_7_class_options(MachineClass *mc) 4748 { 4749 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4750 static GlobalProperty compat[] = { 4751 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4752 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4753 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4754 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4755 }; 4756 4757 spapr_machine_2_8_class_options(mc); 4758 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4759 mc->default_machine_opts = "modern-hotplug-events=off"; 4760 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4761 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4762 smc->phb_placement = phb_placement_2_7; 4763 } 4764 4765 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4766 4767 /* 4768 * pseries-2.6 4769 */ 4770 4771 static void spapr_machine_2_6_class_options(MachineClass *mc) 4772 { 4773 static GlobalProperty compat[] = { 4774 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4775 }; 4776 4777 spapr_machine_2_7_class_options(mc); 4778 mc->has_hotpluggable_cpus = false; 4779 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4780 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4781 } 4782 4783 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4784 4785 /* 4786 * pseries-2.5 4787 */ 4788 4789 static void spapr_machine_2_5_class_options(MachineClass *mc) 4790 { 4791 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4792 static GlobalProperty compat[] = { 4793 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4794 }; 4795 4796 spapr_machine_2_6_class_options(mc); 4797 smc->use_ohci_by_default = true; 4798 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4799 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4800 } 4801 4802 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4803 4804 /* 4805 * pseries-2.4 4806 */ 4807 4808 static void spapr_machine_2_4_class_options(MachineClass *mc) 4809 { 4810 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4811 4812 spapr_machine_2_5_class_options(mc); 4813 smc->dr_lmb_enabled = false; 4814 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4815 } 4816 4817 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4818 4819 /* 4820 * pseries-2.3 4821 */ 4822 4823 static void spapr_machine_2_3_class_options(MachineClass *mc) 4824 { 4825 static GlobalProperty compat[] = { 4826 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4827 }; 4828 spapr_machine_2_4_class_options(mc); 4829 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4830 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4831 } 4832 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4833 4834 /* 4835 * pseries-2.2 4836 */ 4837 4838 static void spapr_machine_2_2_class_options(MachineClass *mc) 4839 { 4840 static GlobalProperty compat[] = { 4841 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4842 }; 4843 4844 spapr_machine_2_3_class_options(mc); 4845 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4846 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4847 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4848 } 4849 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4850 4851 /* 4852 * pseries-2.1 4853 */ 4854 4855 static void spapr_machine_2_1_class_options(MachineClass *mc) 4856 { 4857 spapr_machine_2_2_class_options(mc); 4858 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4859 } 4860 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4861 4862 static void spapr_machine_register_types(void) 4863 { 4864 type_register_static(&spapr_machine_info); 4865 } 4866 4867 type_init(spapr_machine_register_types) 4868