1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/numa.h" 32 #include "hw/hw.h" 33 #include "qemu/log.h" 34 #include "hw/fw-path-provider.h" 35 #include "elf.h" 36 #include "net/net.h" 37 #include "sysemu/device_tree.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/misc.h" 42 #include "migration/global_state.h" 43 #include "migration/register.h" 44 #include "mmu-hash64.h" 45 #include "mmu-book3s-v3.h" 46 #include "cpu-models.h" 47 #include "qom/cpu.h" 48 49 #include "hw/boards.h" 50 #include "hw/ppc/ppc.h" 51 #include "hw/loader.h" 52 53 #include "hw/ppc/fdt.h" 54 #include "hw/ppc/spapr.h" 55 #include "hw/ppc/spapr_vio.h" 56 #include "hw/pci-host/spapr.h" 57 #include "hw/ppc/xics.h" 58 #include "hw/pci/msi.h" 59 60 #include "hw/pci/pci.h" 61 #include "hw/scsi/scsi.h" 62 #include "hw/virtio/virtio-scsi.h" 63 #include "hw/virtio/vhost-scsi-common.h" 64 65 #include "exec/address-spaces.h" 66 #include "exec/ram_addr.h" 67 #include "hw/usb.h" 68 #include "qemu/config-file.h" 69 #include "qemu/error-report.h" 70 #include "trace.h" 71 #include "hw/nmi.h" 72 #include "hw/intc/intc.h" 73 74 #include "hw/compat.h" 75 #include "qemu/cutils.h" 76 #include "hw/ppc/spapr_cpu_core.h" 77 #include "hw/mem/memory-device.h" 78 79 #include <libfdt.h> 80 81 /* SLOF memory layout: 82 * 83 * SLOF raw image loaded at 0, copies its romfs right below the flat 84 * device-tree, then position SLOF itself 31M below that 85 * 86 * So we set FW_OVERHEAD to 40MB which should account for all of that 87 * and more 88 * 89 * We load our kernel at 4M, leaving space for SLOF initial image 90 */ 91 #define FDT_MAX_SIZE 0x100000 92 #define RTAS_MAX_SIZE 0x10000 93 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 94 #define FW_MAX_SIZE 0x400000 95 #define FW_FILE_NAME "slof.bin" 96 #define FW_OVERHEAD 0x2800000 97 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 98 99 #define MIN_RMA_SLOF 128UL 100 101 #define PHANDLE_XICP 0x00001111 102 103 /* These two functions implement the VCPU id numbering: one to compute them 104 * all and one to identify thread 0 of a VCORE. Any change to the first one 105 * is likely to have an impact on the second one, so let's keep them close. 106 */ 107 static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index) 108 { 109 assert(spapr->vsmt); 110 return 111 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 112 } 113 static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr, 114 PowerPCCPU *cpu) 115 { 116 assert(spapr->vsmt); 117 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 118 } 119 120 static ICSState *spapr_ics_create(sPAPRMachineState *spapr, 121 const char *type_ics, 122 int nr_irqs, Error **errp) 123 { 124 Error *local_err = NULL; 125 Object *obj; 126 127 obj = object_new(type_ics); 128 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); 129 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), 130 &error_abort); 131 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); 132 if (local_err) { 133 goto error; 134 } 135 object_property_set_bool(obj, true, "realized", &local_err); 136 if (local_err) { 137 goto error; 138 } 139 140 return ICS_BASE(obj); 141 142 error: 143 error_propagate(errp, local_err); 144 return NULL; 145 } 146 147 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 148 { 149 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 150 * and newer QEMUs don't even have them. In both cases, we don't want 151 * to send anything on the wire. 152 */ 153 return false; 154 } 155 156 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 157 .name = "icp/server", 158 .version_id = 1, 159 .minimum_version_id = 1, 160 .needed = pre_2_10_vmstate_dummy_icp_needed, 161 .fields = (VMStateField[]) { 162 VMSTATE_UNUSED(4), /* uint32_t xirr */ 163 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 164 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 165 VMSTATE_END_OF_LIST() 166 }, 167 }; 168 169 static void pre_2_10_vmstate_register_dummy_icp(int i) 170 { 171 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 172 (void *)(uintptr_t) i); 173 } 174 175 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 176 { 177 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 178 (void *)(uintptr_t) i); 179 } 180 181 static int xics_max_server_number(sPAPRMachineState *spapr) 182 { 183 assert(spapr->vsmt); 184 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads); 185 } 186 187 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) 188 { 189 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 190 Error *local_err = NULL; 191 192 if (kvm_enabled()) { 193 if (machine_kernel_irqchip_allowed(machine) && 194 !xics_kvm_init(spapr, &local_err)) { 195 spapr->icp_type = TYPE_KVM_ICP; 196 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, 197 &local_err); 198 } 199 if (machine_kernel_irqchip_required(machine) && !spapr->ics) { 200 error_prepend(&local_err, 201 "kernel_irqchip requested but unavailable: "); 202 goto error; 203 } 204 error_free(local_err); 205 local_err = NULL; 206 } 207 208 if (!spapr->ics) { 209 xics_spapr_init(spapr); 210 spapr->icp_type = TYPE_ICP; 211 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, 212 &local_err); 213 } 214 215 error: 216 error_propagate(errp, local_err); 217 } 218 219 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 220 int smt_threads) 221 { 222 int i, ret = 0; 223 uint32_t servers_prop[smt_threads]; 224 uint32_t gservers_prop[smt_threads * 2]; 225 int index = spapr_get_vcpu_id(cpu); 226 227 if (cpu->compat_pvr) { 228 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 229 if (ret < 0) { 230 return ret; 231 } 232 } 233 234 /* Build interrupt servers and gservers properties */ 235 for (i = 0; i < smt_threads; i++) { 236 servers_prop[i] = cpu_to_be32(index + i); 237 /* Hack, direct the group queues back to cpu 0 */ 238 gservers_prop[i*2] = cpu_to_be32(index + i); 239 gservers_prop[i*2 + 1] = 0; 240 } 241 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 242 servers_prop, sizeof(servers_prop)); 243 if (ret < 0) { 244 return ret; 245 } 246 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 247 gservers_prop, sizeof(gservers_prop)); 248 249 return ret; 250 } 251 252 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 253 { 254 int index = spapr_get_vcpu_id(cpu); 255 uint32_t associativity[] = {cpu_to_be32(0x5), 256 cpu_to_be32(0x0), 257 cpu_to_be32(0x0), 258 cpu_to_be32(0x0), 259 cpu_to_be32(cpu->node_id), 260 cpu_to_be32(index)}; 261 262 /* Advertise NUMA via ibm,associativity */ 263 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 264 sizeof(associativity)); 265 } 266 267 /* Populate the "ibm,pa-features" property */ 268 static void spapr_populate_pa_features(sPAPRMachineState *spapr, 269 PowerPCCPU *cpu, 270 void *fdt, int offset, 271 bool legacy_guest) 272 { 273 uint8_t pa_features_206[] = { 6, 0, 274 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 275 uint8_t pa_features_207[] = { 24, 0, 276 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 277 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 278 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 279 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 280 uint8_t pa_features_300[] = { 66, 0, 281 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 282 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 283 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 284 /* 6: DS207 */ 285 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 286 /* 16: Vector */ 287 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 288 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 289 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 290 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 291 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 292 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 293 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 294 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 295 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 296 /* 42: PM, 44: PC RA, 46: SC vec'd */ 297 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 298 /* 48: SIMD, 50: QP BFP, 52: String */ 299 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 300 /* 54: DecFP, 56: DecI, 58: SHA */ 301 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 302 /* 60: NM atomic, 62: RNG */ 303 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 304 }; 305 uint8_t *pa_features = NULL; 306 size_t pa_size; 307 308 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 309 pa_features = pa_features_206; 310 pa_size = sizeof(pa_features_206); 311 } 312 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 313 pa_features = pa_features_207; 314 pa_size = sizeof(pa_features_207); 315 } 316 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 317 pa_features = pa_features_300; 318 pa_size = sizeof(pa_features_300); 319 } 320 if (!pa_features) { 321 return; 322 } 323 324 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 325 /* 326 * Note: we keep CI large pages off by default because a 64K capable 327 * guest provisioned with large pages might otherwise try to map a qemu 328 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 329 * even if that qemu runs on a 4k host. 330 * We dd this bit back here if we are confident this is not an issue 331 */ 332 pa_features[3] |= 0x20; 333 } 334 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 335 pa_features[24] |= 0x80; /* Transactional memory support */ 336 } 337 if (legacy_guest && pa_size > 40) { 338 /* Workaround for broken kernels that attempt (guest) radix 339 * mode when they can't handle it, if they see the radix bit set 340 * in pa-features. So hide it from them. */ 341 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 342 } 343 344 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 345 } 346 347 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 348 { 349 int ret = 0, offset, cpus_offset; 350 CPUState *cs; 351 char cpu_model[32]; 352 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 353 354 CPU_FOREACH(cs) { 355 PowerPCCPU *cpu = POWERPC_CPU(cs); 356 DeviceClass *dc = DEVICE_GET_CLASS(cs); 357 int index = spapr_get_vcpu_id(cpu); 358 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 359 360 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 361 continue; 362 } 363 364 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 365 366 cpus_offset = fdt_path_offset(fdt, "/cpus"); 367 if (cpus_offset < 0) { 368 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 369 if (cpus_offset < 0) { 370 return cpus_offset; 371 } 372 } 373 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 374 if (offset < 0) { 375 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 376 if (offset < 0) { 377 return offset; 378 } 379 } 380 381 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 382 pft_size_prop, sizeof(pft_size_prop)); 383 if (ret < 0) { 384 return ret; 385 } 386 387 if (nb_numa_nodes > 1) { 388 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 389 if (ret < 0) { 390 return ret; 391 } 392 } 393 394 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 395 if (ret < 0) { 396 return ret; 397 } 398 399 spapr_populate_pa_features(spapr, cpu, fdt, offset, 400 spapr->cas_legacy_guest_workaround); 401 } 402 return ret; 403 } 404 405 static hwaddr spapr_node0_size(MachineState *machine) 406 { 407 if (nb_numa_nodes) { 408 int i; 409 for (i = 0; i < nb_numa_nodes; ++i) { 410 if (numa_info[i].node_mem) { 411 return MIN(pow2floor(numa_info[i].node_mem), 412 machine->ram_size); 413 } 414 } 415 } 416 return machine->ram_size; 417 } 418 419 static void add_str(GString *s, const gchar *s1) 420 { 421 g_string_append_len(s, s1, strlen(s1) + 1); 422 } 423 424 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 425 hwaddr size) 426 { 427 uint32_t associativity[] = { 428 cpu_to_be32(0x4), /* length */ 429 cpu_to_be32(0x0), cpu_to_be32(0x0), 430 cpu_to_be32(0x0), cpu_to_be32(nodeid) 431 }; 432 char mem_name[32]; 433 uint64_t mem_reg_property[2]; 434 int off; 435 436 mem_reg_property[0] = cpu_to_be64(start); 437 mem_reg_property[1] = cpu_to_be64(size); 438 439 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 440 off = fdt_add_subnode(fdt, 0, mem_name); 441 _FDT(off); 442 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 443 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 444 sizeof(mem_reg_property)))); 445 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 446 sizeof(associativity)))); 447 return off; 448 } 449 450 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 451 { 452 MachineState *machine = MACHINE(spapr); 453 hwaddr mem_start, node_size; 454 int i, nb_nodes = nb_numa_nodes; 455 NodeInfo *nodes = numa_info; 456 NodeInfo ramnode; 457 458 /* No NUMA nodes, assume there is just one node with whole RAM */ 459 if (!nb_numa_nodes) { 460 nb_nodes = 1; 461 ramnode.node_mem = machine->ram_size; 462 nodes = &ramnode; 463 } 464 465 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 466 if (!nodes[i].node_mem) { 467 continue; 468 } 469 if (mem_start >= machine->ram_size) { 470 node_size = 0; 471 } else { 472 node_size = nodes[i].node_mem; 473 if (node_size > machine->ram_size - mem_start) { 474 node_size = machine->ram_size - mem_start; 475 } 476 } 477 if (!mem_start) { 478 /* spapr_machine_init() checks for rma_size <= node0_size 479 * already */ 480 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 481 mem_start += spapr->rma_size; 482 node_size -= spapr->rma_size; 483 } 484 for ( ; node_size; ) { 485 hwaddr sizetmp = pow2floor(node_size); 486 487 /* mem_start != 0 here */ 488 if (ctzl(mem_start) < ctzl(sizetmp)) { 489 sizetmp = 1ULL << ctzl(mem_start); 490 } 491 492 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 493 node_size -= sizetmp; 494 mem_start += sizetmp; 495 } 496 } 497 498 return 0; 499 } 500 501 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 502 sPAPRMachineState *spapr) 503 { 504 PowerPCCPU *cpu = POWERPC_CPU(cs); 505 CPUPPCState *env = &cpu->env; 506 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 507 int index = spapr_get_vcpu_id(cpu); 508 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 509 0xffffffff, 0xffffffff}; 510 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 511 : SPAPR_TIMEBASE_FREQ; 512 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 513 uint32_t page_sizes_prop[64]; 514 size_t page_sizes_prop_size; 515 uint32_t vcpus_per_socket = smp_threads * smp_cores; 516 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 517 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 518 sPAPRDRConnector *drc; 519 int drc_index; 520 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 521 int i; 522 523 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 524 if (drc) { 525 drc_index = spapr_drc_index(drc); 526 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 527 } 528 529 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 530 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 531 532 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 533 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 534 env->dcache_line_size))); 535 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 536 env->dcache_line_size))); 537 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 538 env->icache_line_size))); 539 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 540 env->icache_line_size))); 541 542 if (pcc->l1_dcache_size) { 543 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 544 pcc->l1_dcache_size))); 545 } else { 546 warn_report("Unknown L1 dcache size for cpu"); 547 } 548 if (pcc->l1_icache_size) { 549 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 550 pcc->l1_icache_size))); 551 } else { 552 warn_report("Unknown L1 icache size for cpu"); 553 } 554 555 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 556 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 557 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 558 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 559 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 560 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 561 562 if (env->spr_cb[SPR_PURR].oea_read) { 563 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 564 } 565 566 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 567 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 568 segs, sizeof(segs)))); 569 } 570 571 /* Advertise VSX (vector extensions) if available 572 * 1 == VMX / Altivec available 573 * 2 == VSX available 574 * 575 * Only CPUs for which we create core types in spapr_cpu_core.c 576 * are possible, and all of those have VMX */ 577 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 578 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 579 } else { 580 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 581 } 582 583 /* Advertise DFP (Decimal Floating Point) if available 584 * 0 / no property == no DFP 585 * 1 == DFP available */ 586 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 587 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 588 } 589 590 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 591 sizeof(page_sizes_prop)); 592 if (page_sizes_prop_size) { 593 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 594 page_sizes_prop, page_sizes_prop_size))); 595 } 596 597 spapr_populate_pa_features(spapr, cpu, fdt, offset, false); 598 599 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 600 cs->cpu_index / vcpus_per_socket))); 601 602 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 603 pft_size_prop, sizeof(pft_size_prop)))); 604 605 if (nb_numa_nodes > 1) { 606 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 607 } 608 609 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 610 611 if (pcc->radix_page_info) { 612 for (i = 0; i < pcc->radix_page_info->count; i++) { 613 radix_AP_encodings[i] = 614 cpu_to_be32(pcc->radix_page_info->entries[i]); 615 } 616 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 617 radix_AP_encodings, 618 pcc->radix_page_info->count * 619 sizeof(radix_AP_encodings[0])))); 620 } 621 } 622 623 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 624 { 625 CPUState **rev; 626 CPUState *cs; 627 int n_cpus; 628 int cpus_offset; 629 char *nodename; 630 int i; 631 632 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 633 _FDT(cpus_offset); 634 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 635 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 636 637 /* 638 * We walk the CPUs in reverse order to ensure that CPU DT nodes 639 * created by fdt_add_subnode() end up in the right order in FDT 640 * for the guest kernel the enumerate the CPUs correctly. 641 * 642 * The CPU list cannot be traversed in reverse order, so we need 643 * to do extra work. 644 */ 645 n_cpus = 0; 646 rev = NULL; 647 CPU_FOREACH(cs) { 648 rev = g_renew(CPUState *, rev, n_cpus + 1); 649 rev[n_cpus++] = cs; 650 } 651 652 for (i = n_cpus - 1; i >= 0; i--) { 653 CPUState *cs = rev[i]; 654 PowerPCCPU *cpu = POWERPC_CPU(cs); 655 int index = spapr_get_vcpu_id(cpu); 656 DeviceClass *dc = DEVICE_GET_CLASS(cs); 657 int offset; 658 659 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 660 continue; 661 } 662 663 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 664 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 665 g_free(nodename); 666 _FDT(offset); 667 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 668 } 669 670 } 671 672 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 673 { 674 MemoryDeviceInfoList *info; 675 676 for (info = list; info; info = info->next) { 677 MemoryDeviceInfo *value = info->value; 678 679 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 680 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 681 682 if (addr >= pcdimm_info->addr && 683 addr < (pcdimm_info->addr + pcdimm_info->size)) { 684 return pcdimm_info->node; 685 } 686 } 687 } 688 689 return -1; 690 } 691 692 struct sPAPRDrconfCellV2 { 693 uint32_t seq_lmbs; 694 uint64_t base_addr; 695 uint32_t drc_index; 696 uint32_t aa_index; 697 uint32_t flags; 698 } QEMU_PACKED; 699 700 typedef struct DrconfCellQueue { 701 struct sPAPRDrconfCellV2 cell; 702 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 703 } DrconfCellQueue; 704 705 static DrconfCellQueue * 706 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 707 uint32_t drc_index, uint32_t aa_index, 708 uint32_t flags) 709 { 710 DrconfCellQueue *elem; 711 712 elem = g_malloc0(sizeof(*elem)); 713 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 714 elem->cell.base_addr = cpu_to_be64(base_addr); 715 elem->cell.drc_index = cpu_to_be32(drc_index); 716 elem->cell.aa_index = cpu_to_be32(aa_index); 717 elem->cell.flags = cpu_to_be32(flags); 718 719 return elem; 720 } 721 722 /* ibm,dynamic-memory-v2 */ 723 static int spapr_populate_drmem_v2(sPAPRMachineState *spapr, void *fdt, 724 int offset, MemoryDeviceInfoList *dimms) 725 { 726 MachineState *machine = MACHINE(spapr); 727 uint8_t *int_buf, *cur_index, buf_len; 728 int ret; 729 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 730 uint64_t addr, cur_addr, size; 731 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 732 uint64_t mem_end = machine->device_memory->base + 733 memory_region_size(&machine->device_memory->mr); 734 uint32_t node, nr_entries = 0; 735 sPAPRDRConnector *drc; 736 DrconfCellQueue *elem, *next; 737 MemoryDeviceInfoList *info; 738 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 739 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 740 741 /* Entry to cover RAM and the gap area */ 742 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 743 SPAPR_LMB_FLAGS_RESERVED | 744 SPAPR_LMB_FLAGS_DRC_INVALID); 745 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 746 nr_entries++; 747 748 cur_addr = machine->device_memory->base; 749 for (info = dimms; info; info = info->next) { 750 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 751 752 addr = di->addr; 753 size = di->size; 754 node = di->node; 755 756 /* Entry for hot-pluggable area */ 757 if (cur_addr < addr) { 758 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 759 g_assert(drc); 760 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 761 cur_addr, spapr_drc_index(drc), -1, 0); 762 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 763 nr_entries++; 764 } 765 766 /* Entry for DIMM */ 767 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 768 g_assert(drc); 769 elem = spapr_get_drconf_cell(size / lmb_size, addr, 770 spapr_drc_index(drc), node, 771 SPAPR_LMB_FLAGS_ASSIGNED); 772 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 773 nr_entries++; 774 cur_addr = addr + size; 775 } 776 777 /* Entry for remaining hotpluggable area */ 778 if (cur_addr < mem_end) { 779 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 780 g_assert(drc); 781 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 782 cur_addr, spapr_drc_index(drc), -1, 0); 783 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 784 nr_entries++; 785 } 786 787 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 788 int_buf = cur_index = g_malloc0(buf_len); 789 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 790 cur_index += sizeof(nr_entries); 791 792 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 793 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 794 cur_index += sizeof(elem->cell); 795 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 796 g_free(elem); 797 } 798 799 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 800 g_free(int_buf); 801 if (ret < 0) { 802 return -1; 803 } 804 return 0; 805 } 806 807 /* ibm,dynamic-memory */ 808 static int spapr_populate_drmem_v1(sPAPRMachineState *spapr, void *fdt, 809 int offset, MemoryDeviceInfoList *dimms) 810 { 811 MachineState *machine = MACHINE(spapr); 812 int i, ret; 813 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 814 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 815 uint32_t nr_lmbs = (machine->device_memory->base + 816 memory_region_size(&machine->device_memory->mr)) / 817 lmb_size; 818 uint32_t *int_buf, *cur_index, buf_len; 819 820 /* 821 * Allocate enough buffer size to fit in ibm,dynamic-memory 822 */ 823 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 824 cur_index = int_buf = g_malloc0(buf_len); 825 int_buf[0] = cpu_to_be32(nr_lmbs); 826 cur_index++; 827 for (i = 0; i < nr_lmbs; i++) { 828 uint64_t addr = i * lmb_size; 829 uint32_t *dynamic_memory = cur_index; 830 831 if (i >= device_lmb_start) { 832 sPAPRDRConnector *drc; 833 834 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 835 g_assert(drc); 836 837 dynamic_memory[0] = cpu_to_be32(addr >> 32); 838 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 839 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 840 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 841 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 842 if (memory_region_present(get_system_memory(), addr)) { 843 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 844 } else { 845 dynamic_memory[5] = cpu_to_be32(0); 846 } 847 } else { 848 /* 849 * LMB information for RMA, boot time RAM and gap b/n RAM and 850 * device memory region -- all these are marked as reserved 851 * and as having no valid DRC. 852 */ 853 dynamic_memory[0] = cpu_to_be32(addr >> 32); 854 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 855 dynamic_memory[2] = cpu_to_be32(0); 856 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 857 dynamic_memory[4] = cpu_to_be32(-1); 858 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 859 SPAPR_LMB_FLAGS_DRC_INVALID); 860 } 861 862 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 863 } 864 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 865 g_free(int_buf); 866 if (ret < 0) { 867 return -1; 868 } 869 return 0; 870 } 871 872 /* 873 * Adds ibm,dynamic-reconfiguration-memory node. 874 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 875 * of this device tree node. 876 */ 877 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 878 { 879 MachineState *machine = MACHINE(spapr); 880 int ret, i, offset; 881 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 882 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 883 uint32_t *int_buf, *cur_index, buf_len; 884 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 885 MemoryDeviceInfoList *dimms = NULL; 886 887 /* 888 * Don't create the node if there is no device memory 889 */ 890 if (machine->ram_size == machine->maxram_size) { 891 return 0; 892 } 893 894 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 895 896 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 897 sizeof(prop_lmb_size)); 898 if (ret < 0) { 899 return ret; 900 } 901 902 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 903 if (ret < 0) { 904 return ret; 905 } 906 907 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 908 if (ret < 0) { 909 return ret; 910 } 911 912 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 913 dimms = qmp_memory_device_list(); 914 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 915 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 916 } else { 917 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 918 } 919 qapi_free_MemoryDeviceInfoList(dimms); 920 921 if (ret < 0) { 922 return ret; 923 } 924 925 /* ibm,associativity-lookup-arrays */ 926 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 927 cur_index = int_buf = g_malloc0(buf_len); 928 929 cur_index = int_buf; 930 int_buf[0] = cpu_to_be32(nr_nodes); 931 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 932 cur_index += 2; 933 for (i = 0; i < nr_nodes; i++) { 934 uint32_t associativity[] = { 935 cpu_to_be32(0x0), 936 cpu_to_be32(0x0), 937 cpu_to_be32(0x0), 938 cpu_to_be32(i) 939 }; 940 memcpy(cur_index, associativity, sizeof(associativity)); 941 cur_index += 4; 942 } 943 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 944 (cur_index - int_buf) * sizeof(uint32_t)); 945 g_free(int_buf); 946 947 return ret; 948 } 949 950 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 951 sPAPROptionVector *ov5_updates) 952 { 953 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 954 int ret = 0, offset; 955 956 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 957 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 958 g_assert(smc->dr_lmb_enabled); 959 ret = spapr_populate_drconf_memory(spapr, fdt); 960 if (ret) { 961 goto out; 962 } 963 } 964 965 offset = fdt_path_offset(fdt, "/chosen"); 966 if (offset < 0) { 967 offset = fdt_add_subnode(fdt, 0, "chosen"); 968 if (offset < 0) { 969 return offset; 970 } 971 } 972 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 973 "ibm,architecture-vec-5"); 974 975 out: 976 return ret; 977 } 978 979 static bool spapr_hotplugged_dev_before_cas(void) 980 { 981 Object *drc_container, *obj; 982 ObjectProperty *prop; 983 ObjectPropertyIterator iter; 984 985 drc_container = container_get(object_get_root(), "/dr-connector"); 986 object_property_iter_init(&iter, drc_container); 987 while ((prop = object_property_iter_next(&iter))) { 988 if (!strstart(prop->type, "link<", NULL)) { 989 continue; 990 } 991 obj = object_property_get_link(drc_container, prop->name, NULL); 992 if (spapr_drc_needed(obj)) { 993 return true; 994 } 995 } 996 return false; 997 } 998 999 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 1000 target_ulong addr, target_ulong size, 1001 sPAPROptionVector *ov5_updates) 1002 { 1003 void *fdt, *fdt_skel; 1004 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 1005 1006 if (spapr_hotplugged_dev_before_cas()) { 1007 return 1; 1008 } 1009 1010 if (size < sizeof(hdr) || size > FW_MAX_SIZE) { 1011 error_report("SLOF provided an unexpected CAS buffer size " 1012 TARGET_FMT_lu " (min: %zu, max: %u)", 1013 size, sizeof(hdr), FW_MAX_SIZE); 1014 exit(EXIT_FAILURE); 1015 } 1016 1017 size -= sizeof(hdr); 1018 1019 /* Create skeleton */ 1020 fdt_skel = g_malloc0(size); 1021 _FDT((fdt_create(fdt_skel, size))); 1022 _FDT((fdt_finish_reservemap(fdt_skel))); 1023 _FDT((fdt_begin_node(fdt_skel, ""))); 1024 _FDT((fdt_end_node(fdt_skel))); 1025 _FDT((fdt_finish(fdt_skel))); 1026 fdt = g_malloc0(size); 1027 _FDT((fdt_open_into(fdt_skel, fdt, size))); 1028 g_free(fdt_skel); 1029 1030 /* Fixup cpu nodes */ 1031 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 1032 1033 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 1034 return -1; 1035 } 1036 1037 /* Pack resulting tree */ 1038 _FDT((fdt_pack(fdt))); 1039 1040 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 1041 trace_spapr_cas_failed(size); 1042 return -1; 1043 } 1044 1045 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 1046 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 1047 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 1048 g_free(fdt); 1049 1050 return 0; 1051 } 1052 1053 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 1054 { 1055 int rtas; 1056 GString *hypertas = g_string_sized_new(256); 1057 GString *qemu_hypertas = g_string_sized_new(256); 1058 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 1059 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 1060 memory_region_size(&MACHINE(spapr)->device_memory->mr); 1061 uint32_t lrdr_capacity[] = { 1062 cpu_to_be32(max_device_addr >> 32), 1063 cpu_to_be32(max_device_addr & 0xffffffff), 1064 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 1065 cpu_to_be32(max_cpus / smp_threads), 1066 }; 1067 uint32_t maxdomains[] = { 1068 cpu_to_be32(4), 1069 cpu_to_be32(0), 1070 cpu_to_be32(0), 1071 cpu_to_be32(0), 1072 cpu_to_be32(nb_numa_nodes ? nb_numa_nodes - 1 : 0), 1073 }; 1074 1075 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 1076 1077 /* hypertas */ 1078 add_str(hypertas, "hcall-pft"); 1079 add_str(hypertas, "hcall-term"); 1080 add_str(hypertas, "hcall-dabr"); 1081 add_str(hypertas, "hcall-interrupt"); 1082 add_str(hypertas, "hcall-tce"); 1083 add_str(hypertas, "hcall-vio"); 1084 add_str(hypertas, "hcall-splpar"); 1085 add_str(hypertas, "hcall-bulk"); 1086 add_str(hypertas, "hcall-set-mode"); 1087 add_str(hypertas, "hcall-sprg0"); 1088 add_str(hypertas, "hcall-copy"); 1089 add_str(hypertas, "hcall-debug"); 1090 add_str(qemu_hypertas, "hcall-memop1"); 1091 1092 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 1093 add_str(hypertas, "hcall-multi-tce"); 1094 } 1095 1096 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 1097 add_str(hypertas, "hcall-hpt-resize"); 1098 } 1099 1100 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 1101 hypertas->str, hypertas->len)); 1102 g_string_free(hypertas, TRUE); 1103 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 1104 qemu_hypertas->str, qemu_hypertas->len)); 1105 g_string_free(qemu_hypertas, TRUE); 1106 1107 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 1108 refpoints, sizeof(refpoints))); 1109 1110 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 1111 maxdomains, sizeof(maxdomains))); 1112 1113 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 1114 RTAS_ERROR_LOG_MAX)); 1115 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 1116 RTAS_EVENT_SCAN_RATE)); 1117 1118 g_assert(msi_nonbroken); 1119 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 1120 1121 /* 1122 * According to PAPR, rtas ibm,os-term does not guarantee a return 1123 * back to the guest cpu. 1124 * 1125 * While an additional ibm,extended-os-term property indicates 1126 * that rtas call return will always occur. Set this property. 1127 */ 1128 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1129 1130 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1131 lrdr_capacity, sizeof(lrdr_capacity))); 1132 1133 spapr_dt_rtas_tokens(fdt, rtas); 1134 } 1135 1136 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features 1137 * that the guest may request and thus the valid values for bytes 24..26 of 1138 * option vector 5: */ 1139 static void spapr_dt_ov5_platform_support(void *fdt, int chosen) 1140 { 1141 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1142 1143 char val[2 * 4] = { 1144 23, 0x00, /* Xive mode, filled in below. */ 1145 24, 0x00, /* Hash/Radix, filled in below. */ 1146 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1147 26, 0x40, /* Radix options: GTSE == yes. */ 1148 }; 1149 1150 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1151 first_ppc_cpu->compat_pvr)) { 1152 /* If we're in a pre POWER9 compat mode then the guest should do hash */ 1153 val[3] = 0x00; /* Hash */ 1154 } else if (kvm_enabled()) { 1155 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1156 val[3] = 0x80; /* OV5_MMU_BOTH */ 1157 } else if (kvmppc_has_cap_mmu_radix()) { 1158 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1159 } else { 1160 val[3] = 0x00; /* Hash */ 1161 } 1162 } else { 1163 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1164 val[3] = 0xC0; 1165 } 1166 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1167 val, sizeof(val))); 1168 } 1169 1170 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 1171 { 1172 MachineState *machine = MACHINE(spapr); 1173 int chosen; 1174 const char *boot_device = machine->boot_order; 1175 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1176 size_t cb = 0; 1177 char *bootlist = get_boot_devices_list(&cb); 1178 1179 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1180 1181 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 1182 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1183 spapr->initrd_base)); 1184 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1185 spapr->initrd_base + spapr->initrd_size)); 1186 1187 if (spapr->kernel_size) { 1188 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1189 cpu_to_be64(spapr->kernel_size) }; 1190 1191 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1192 &kprop, sizeof(kprop))); 1193 if (spapr->kernel_le) { 1194 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1195 } 1196 } 1197 if (boot_menu) { 1198 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1199 } 1200 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1201 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1202 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1203 1204 if (cb && bootlist) { 1205 int i; 1206 1207 for (i = 0; i < cb; i++) { 1208 if (bootlist[i] == '\n') { 1209 bootlist[i] = ' '; 1210 } 1211 } 1212 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1213 } 1214 1215 if (boot_device && strlen(boot_device)) { 1216 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1217 } 1218 1219 if (!spapr->has_graphics && stdout_path) { 1220 /* 1221 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1222 * kernel. New platforms should only use the "stdout-path" property. Set 1223 * the new property and continue using older property to remain 1224 * compatible with the existing firmware. 1225 */ 1226 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1227 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1228 } 1229 1230 spapr_dt_ov5_platform_support(fdt, chosen); 1231 1232 g_free(stdout_path); 1233 g_free(bootlist); 1234 } 1235 1236 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 1237 { 1238 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1239 * KVM to work under pHyp with some guest co-operation */ 1240 int hypervisor; 1241 uint8_t hypercall[16]; 1242 1243 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1244 /* indicate KVM hypercall interface */ 1245 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1246 if (kvmppc_has_cap_fixup_hcalls()) { 1247 /* 1248 * Older KVM versions with older guest kernels were broken 1249 * with the magic page, don't allow the guest to map it. 1250 */ 1251 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1252 sizeof(hypercall))) { 1253 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1254 hypercall, sizeof(hypercall))); 1255 } 1256 } 1257 } 1258 1259 static void *spapr_build_fdt(sPAPRMachineState *spapr, 1260 hwaddr rtas_addr, 1261 hwaddr rtas_size) 1262 { 1263 MachineState *machine = MACHINE(spapr); 1264 MachineClass *mc = MACHINE_GET_CLASS(machine); 1265 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1266 int ret; 1267 void *fdt; 1268 sPAPRPHBState *phb; 1269 char *buf; 1270 1271 fdt = g_malloc0(FDT_MAX_SIZE); 1272 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1273 1274 /* Root node */ 1275 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1276 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1277 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1278 1279 /* 1280 * Add info to guest to indentify which host is it being run on 1281 * and what is the uuid of the guest 1282 */ 1283 if (kvmppc_get_host_model(&buf)) { 1284 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1285 g_free(buf); 1286 } 1287 if (kvmppc_get_host_serial(&buf)) { 1288 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1289 g_free(buf); 1290 } 1291 1292 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1293 1294 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1295 if (qemu_uuid_set) { 1296 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1297 } 1298 g_free(buf); 1299 1300 if (qemu_get_vm_name()) { 1301 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1302 qemu_get_vm_name())); 1303 } 1304 1305 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1306 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1307 1308 /* /interrupt controller */ 1309 spapr_dt_xics(xics_max_server_number(spapr), fdt, PHANDLE_XICP); 1310 1311 ret = spapr_populate_memory(spapr, fdt); 1312 if (ret < 0) { 1313 error_report("couldn't setup memory nodes in fdt"); 1314 exit(1); 1315 } 1316 1317 /* /vdevice */ 1318 spapr_dt_vdevice(spapr->vio_bus, fdt); 1319 1320 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1321 ret = spapr_rng_populate_dt(fdt); 1322 if (ret < 0) { 1323 error_report("could not set up rng device in the fdt"); 1324 exit(1); 1325 } 1326 } 1327 1328 QLIST_FOREACH(phb, &spapr->phbs, list) { 1329 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 1330 if (ret < 0) { 1331 error_report("couldn't setup PCI devices in fdt"); 1332 exit(1); 1333 } 1334 } 1335 1336 /* cpus */ 1337 spapr_populate_cpus_dt_node(fdt, spapr); 1338 1339 if (smc->dr_lmb_enabled) { 1340 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1341 } 1342 1343 if (mc->has_hotpluggable_cpus) { 1344 int offset = fdt_path_offset(fdt, "/cpus"); 1345 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1346 SPAPR_DR_CONNECTOR_TYPE_CPU); 1347 if (ret < 0) { 1348 error_report("Couldn't set up CPU DR device tree properties"); 1349 exit(1); 1350 } 1351 } 1352 1353 /* /event-sources */ 1354 spapr_dt_events(spapr, fdt); 1355 1356 /* /rtas */ 1357 spapr_dt_rtas(spapr, fdt); 1358 1359 /* /chosen */ 1360 spapr_dt_chosen(spapr, fdt); 1361 1362 /* /hypervisor */ 1363 if (kvm_enabled()) { 1364 spapr_dt_hypervisor(spapr, fdt); 1365 } 1366 1367 /* Build memory reserve map */ 1368 if (spapr->kernel_size) { 1369 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1370 } 1371 if (spapr->initrd_size) { 1372 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1373 } 1374 1375 /* ibm,client-architecture-support updates */ 1376 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1377 if (ret < 0) { 1378 error_report("couldn't setup CAS properties fdt"); 1379 exit(1); 1380 } 1381 1382 return fdt; 1383 } 1384 1385 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1386 { 1387 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1388 } 1389 1390 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1391 PowerPCCPU *cpu) 1392 { 1393 CPUPPCState *env = &cpu->env; 1394 1395 /* The TCG path should also be holding the BQL at this point */ 1396 g_assert(qemu_mutex_iothread_locked()); 1397 1398 if (msr_pr) { 1399 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1400 env->gpr[3] = H_PRIVILEGE; 1401 } else { 1402 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1403 } 1404 } 1405 1406 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1407 { 1408 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1409 1410 return spapr->patb_entry; 1411 } 1412 1413 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1414 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1415 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1416 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1417 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1418 1419 /* 1420 * Get the fd to access the kernel htab, re-opening it if necessary 1421 */ 1422 static int get_htab_fd(sPAPRMachineState *spapr) 1423 { 1424 Error *local_err = NULL; 1425 1426 if (spapr->htab_fd >= 0) { 1427 return spapr->htab_fd; 1428 } 1429 1430 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1431 if (spapr->htab_fd < 0) { 1432 error_report_err(local_err); 1433 } 1434 1435 return spapr->htab_fd; 1436 } 1437 1438 void close_htab_fd(sPAPRMachineState *spapr) 1439 { 1440 if (spapr->htab_fd >= 0) { 1441 close(spapr->htab_fd); 1442 } 1443 spapr->htab_fd = -1; 1444 } 1445 1446 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1447 { 1448 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1449 1450 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1451 } 1452 1453 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1454 { 1455 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1456 1457 assert(kvm_enabled()); 1458 1459 if (!spapr->htab) { 1460 return 0; 1461 } 1462 1463 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1464 } 1465 1466 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1467 hwaddr ptex, int n) 1468 { 1469 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1470 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1471 1472 if (!spapr->htab) { 1473 /* 1474 * HTAB is controlled by KVM. Fetch into temporary buffer 1475 */ 1476 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1477 kvmppc_read_hptes(hptes, ptex, n); 1478 return hptes; 1479 } 1480 1481 /* 1482 * HTAB is controlled by QEMU. Just point to the internally 1483 * accessible PTEG. 1484 */ 1485 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1486 } 1487 1488 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1489 const ppc_hash_pte64_t *hptes, 1490 hwaddr ptex, int n) 1491 { 1492 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1493 1494 if (!spapr->htab) { 1495 g_free((void *)hptes); 1496 } 1497 1498 /* Nothing to do for qemu managed HPT */ 1499 } 1500 1501 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1502 uint64_t pte0, uint64_t pte1) 1503 { 1504 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1505 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1506 1507 if (!spapr->htab) { 1508 kvmppc_write_hpte(ptex, pte0, pte1); 1509 } else { 1510 stq_p(spapr->htab + offset, pte0); 1511 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1512 } 1513 } 1514 1515 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1516 { 1517 int shift; 1518 1519 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1520 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1521 * that's much more than is needed for Linux guests */ 1522 shift = ctz64(pow2ceil(ramsize)) - 7; 1523 shift = MAX(shift, 18); /* Minimum architected size */ 1524 shift = MIN(shift, 46); /* Maximum architected size */ 1525 return shift; 1526 } 1527 1528 void spapr_free_hpt(sPAPRMachineState *spapr) 1529 { 1530 g_free(spapr->htab); 1531 spapr->htab = NULL; 1532 spapr->htab_shift = 0; 1533 close_htab_fd(spapr); 1534 } 1535 1536 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1537 Error **errp) 1538 { 1539 long rc; 1540 1541 /* Clean up any HPT info from a previous boot */ 1542 spapr_free_hpt(spapr); 1543 1544 rc = kvmppc_reset_htab(shift); 1545 if (rc < 0) { 1546 /* kernel-side HPT needed, but couldn't allocate one */ 1547 error_setg_errno(errp, errno, 1548 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1549 shift); 1550 /* This is almost certainly fatal, but if the caller really 1551 * wants to carry on with shift == 0, it's welcome to try */ 1552 } else if (rc > 0) { 1553 /* kernel-side HPT allocated */ 1554 if (rc != shift) { 1555 error_setg(errp, 1556 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1557 shift, rc); 1558 } 1559 1560 spapr->htab_shift = shift; 1561 spapr->htab = NULL; 1562 } else { 1563 /* kernel-side HPT not needed, allocate in userspace instead */ 1564 size_t size = 1ULL << shift; 1565 int i; 1566 1567 spapr->htab = qemu_memalign(size, size); 1568 if (!spapr->htab) { 1569 error_setg_errno(errp, errno, 1570 "Could not allocate HPT of order %d", shift); 1571 return; 1572 } 1573 1574 memset(spapr->htab, 0, size); 1575 spapr->htab_shift = shift; 1576 1577 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1578 DIRTY_HPTE(HPTE(spapr->htab, i)); 1579 } 1580 } 1581 /* We're setting up a hash table, so that means we're not radix */ 1582 spapr->patb_entry = 0; 1583 } 1584 1585 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1586 { 1587 int hpt_shift; 1588 1589 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1590 || (spapr->cas_reboot 1591 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1592 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1593 } else { 1594 uint64_t current_ram_size; 1595 1596 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1597 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1598 } 1599 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1600 1601 if (spapr->vrma_adjust) { 1602 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1603 spapr->htab_shift); 1604 } 1605 } 1606 1607 static int spapr_reset_drcs(Object *child, void *opaque) 1608 { 1609 sPAPRDRConnector *drc = 1610 (sPAPRDRConnector *) object_dynamic_cast(child, 1611 TYPE_SPAPR_DR_CONNECTOR); 1612 1613 if (drc) { 1614 spapr_drc_reset(drc); 1615 } 1616 1617 return 0; 1618 } 1619 1620 static void spapr_machine_reset(void) 1621 { 1622 MachineState *machine = MACHINE(qdev_get_machine()); 1623 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1624 PowerPCCPU *first_ppc_cpu; 1625 uint32_t rtas_limit; 1626 hwaddr rtas_addr, fdt_addr; 1627 void *fdt; 1628 int rc; 1629 1630 spapr_caps_apply(spapr); 1631 1632 first_ppc_cpu = POWERPC_CPU(first_cpu); 1633 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1634 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1635 spapr->max_compat_pvr)) { 1636 /* If using KVM with radix mode available, VCPUs can be started 1637 * without a HPT because KVM will start them in radix mode. 1638 * Set the GR bit in PATB so that we know there is no HPT. */ 1639 spapr->patb_entry = PATBE1_GR; 1640 } else { 1641 spapr_setup_hpt_and_vrma(spapr); 1642 } 1643 1644 /* if this reset wasn't generated by CAS, we should reset our 1645 * negotiated options and start from scratch */ 1646 if (!spapr->cas_reboot) { 1647 spapr_ovec_cleanup(spapr->ov5_cas); 1648 spapr->ov5_cas = spapr_ovec_new(); 1649 1650 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); 1651 } 1652 1653 qemu_devices_reset(); 1654 1655 /* DRC reset may cause a device to be unplugged. This will cause troubles 1656 * if this device is used by another device (eg, a running vhost backend 1657 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1658 * situations, we reset DRCs after all devices have been reset. 1659 */ 1660 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1661 1662 spapr_clear_pending_events(spapr); 1663 1664 /* 1665 * We place the device tree and RTAS just below either the top of the RMA, 1666 * or just below 2GB, whichever is lowere, so that it can be 1667 * processed with 32-bit real mode code if necessary 1668 */ 1669 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1670 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1671 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1672 1673 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1674 1675 spapr_load_rtas(spapr, fdt, rtas_addr); 1676 1677 rc = fdt_pack(fdt); 1678 1679 /* Should only fail if we've built a corrupted tree */ 1680 assert(rc == 0); 1681 1682 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1683 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1684 fdt_totalsize(fdt), FDT_MAX_SIZE); 1685 exit(1); 1686 } 1687 1688 /* Load the fdt */ 1689 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1690 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1691 g_free(fdt); 1692 1693 /* Set up the entry state */ 1694 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); 1695 first_ppc_cpu->env.gpr[5] = 0; 1696 1697 spapr->cas_reboot = false; 1698 } 1699 1700 static void spapr_create_nvram(sPAPRMachineState *spapr) 1701 { 1702 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1703 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1704 1705 if (dinfo) { 1706 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1707 &error_fatal); 1708 } 1709 1710 qdev_init_nofail(dev); 1711 1712 spapr->nvram = (struct sPAPRNVRAM *)dev; 1713 } 1714 1715 static void spapr_rtc_create(sPAPRMachineState *spapr) 1716 { 1717 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1718 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1719 &error_fatal); 1720 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1721 &error_fatal); 1722 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1723 "date", &error_fatal); 1724 } 1725 1726 /* Returns whether we want to use VGA or not */ 1727 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1728 { 1729 switch (vga_interface_type) { 1730 case VGA_NONE: 1731 return false; 1732 case VGA_DEVICE: 1733 return true; 1734 case VGA_STD: 1735 case VGA_VIRTIO: 1736 return pci_vga_init(pci_bus) != NULL; 1737 default: 1738 error_setg(errp, 1739 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1740 return false; 1741 } 1742 } 1743 1744 static int spapr_pre_load(void *opaque) 1745 { 1746 int rc; 1747 1748 rc = spapr_caps_pre_load(opaque); 1749 if (rc) { 1750 return rc; 1751 } 1752 1753 return 0; 1754 } 1755 1756 static int spapr_post_load(void *opaque, int version_id) 1757 { 1758 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1759 int err = 0; 1760 1761 err = spapr_caps_post_migration(spapr); 1762 if (err) { 1763 return err; 1764 } 1765 1766 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1767 CPUState *cs; 1768 CPU_FOREACH(cs) { 1769 PowerPCCPU *cpu = POWERPC_CPU(cs); 1770 icp_resend(ICP(cpu->intc)); 1771 } 1772 } 1773 1774 /* In earlier versions, there was no separate qdev for the PAPR 1775 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1776 * So when migrating from those versions, poke the incoming offset 1777 * value into the RTC device */ 1778 if (version_id < 3) { 1779 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1780 } 1781 1782 if (kvm_enabled() && spapr->patb_entry) { 1783 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1784 bool radix = !!(spapr->patb_entry & PATBE1_GR); 1785 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1786 1787 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1788 if (err) { 1789 error_report("Process table config unsupported by the host"); 1790 return -EINVAL; 1791 } 1792 } 1793 1794 return err; 1795 } 1796 1797 static int spapr_pre_save(void *opaque) 1798 { 1799 int rc; 1800 1801 rc = spapr_caps_pre_save(opaque); 1802 if (rc) { 1803 return rc; 1804 } 1805 1806 return 0; 1807 } 1808 1809 static bool version_before_3(void *opaque, int version_id) 1810 { 1811 return version_id < 3; 1812 } 1813 1814 static bool spapr_pending_events_needed(void *opaque) 1815 { 1816 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1817 return !QTAILQ_EMPTY(&spapr->pending_events); 1818 } 1819 1820 static const VMStateDescription vmstate_spapr_event_entry = { 1821 .name = "spapr_event_log_entry", 1822 .version_id = 1, 1823 .minimum_version_id = 1, 1824 .fields = (VMStateField[]) { 1825 VMSTATE_UINT32(summary, sPAPREventLogEntry), 1826 VMSTATE_UINT32(extended_length, sPAPREventLogEntry), 1827 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, 1828 NULL, extended_length), 1829 VMSTATE_END_OF_LIST() 1830 }, 1831 }; 1832 1833 static const VMStateDescription vmstate_spapr_pending_events = { 1834 .name = "spapr_pending_events", 1835 .version_id = 1, 1836 .minimum_version_id = 1, 1837 .needed = spapr_pending_events_needed, 1838 .fields = (VMStateField[]) { 1839 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, 1840 vmstate_spapr_event_entry, sPAPREventLogEntry, next), 1841 VMSTATE_END_OF_LIST() 1842 }, 1843 }; 1844 1845 static bool spapr_ov5_cas_needed(void *opaque) 1846 { 1847 sPAPRMachineState *spapr = opaque; 1848 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1849 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1850 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1851 bool cas_needed; 1852 1853 /* Prior to the introduction of sPAPROptionVector, we had two option 1854 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1855 * Both of these options encode machine topology into the device-tree 1856 * in such a way that the now-booted OS should still be able to interact 1857 * appropriately with QEMU regardless of what options were actually 1858 * negotiatied on the source side. 1859 * 1860 * As such, we can avoid migrating the CAS-negotiated options if these 1861 * are the only options available on the current machine/platform. 1862 * Since these are the only options available for pseries-2.7 and 1863 * earlier, this allows us to maintain old->new/new->old migration 1864 * compatibility. 1865 * 1866 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1867 * via default pseries-2.8 machines and explicit command-line parameters. 1868 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1869 * of the actual CAS-negotiated values to continue working properly. For 1870 * example, availability of memory unplug depends on knowing whether 1871 * OV5_HP_EVT was negotiated via CAS. 1872 * 1873 * Thus, for any cases where the set of available CAS-negotiatable 1874 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1875 * include the CAS-negotiated options in the migration stream, unless 1876 * if they affect boot time behaviour only. 1877 */ 1878 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1879 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1880 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1881 1882 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1883 * the mask itself since in the future it's possible "legacy" bits may be 1884 * removed via machine options, which could generate a false positive 1885 * that breaks migration. 1886 */ 1887 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1888 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1889 1890 spapr_ovec_cleanup(ov5_mask); 1891 spapr_ovec_cleanup(ov5_legacy); 1892 spapr_ovec_cleanup(ov5_removed); 1893 1894 return cas_needed; 1895 } 1896 1897 static const VMStateDescription vmstate_spapr_ov5_cas = { 1898 .name = "spapr_option_vector_ov5_cas", 1899 .version_id = 1, 1900 .minimum_version_id = 1, 1901 .needed = spapr_ov5_cas_needed, 1902 .fields = (VMStateField[]) { 1903 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1904 vmstate_spapr_ovec, sPAPROptionVector), 1905 VMSTATE_END_OF_LIST() 1906 }, 1907 }; 1908 1909 static bool spapr_patb_entry_needed(void *opaque) 1910 { 1911 sPAPRMachineState *spapr = opaque; 1912 1913 return !!spapr->patb_entry; 1914 } 1915 1916 static const VMStateDescription vmstate_spapr_patb_entry = { 1917 .name = "spapr_patb_entry", 1918 .version_id = 1, 1919 .minimum_version_id = 1, 1920 .needed = spapr_patb_entry_needed, 1921 .fields = (VMStateField[]) { 1922 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1923 VMSTATE_END_OF_LIST() 1924 }, 1925 }; 1926 1927 static const VMStateDescription vmstate_spapr = { 1928 .name = "spapr", 1929 .version_id = 3, 1930 .minimum_version_id = 1, 1931 .pre_load = spapr_pre_load, 1932 .post_load = spapr_post_load, 1933 .pre_save = spapr_pre_save, 1934 .fields = (VMStateField[]) { 1935 /* used to be @next_irq */ 1936 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1937 1938 /* RTC offset */ 1939 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1940 1941 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1942 VMSTATE_END_OF_LIST() 1943 }, 1944 .subsections = (const VMStateDescription*[]) { 1945 &vmstate_spapr_ov5_cas, 1946 &vmstate_spapr_patb_entry, 1947 &vmstate_spapr_pending_events, 1948 &vmstate_spapr_cap_htm, 1949 &vmstate_spapr_cap_vsx, 1950 &vmstate_spapr_cap_dfp, 1951 &vmstate_spapr_cap_cfpc, 1952 &vmstate_spapr_cap_sbbc, 1953 &vmstate_spapr_cap_ibs, 1954 NULL 1955 } 1956 }; 1957 1958 static int htab_save_setup(QEMUFile *f, void *opaque) 1959 { 1960 sPAPRMachineState *spapr = opaque; 1961 1962 /* "Iteration" header */ 1963 if (!spapr->htab_shift) { 1964 qemu_put_be32(f, -1); 1965 } else { 1966 qemu_put_be32(f, spapr->htab_shift); 1967 } 1968 1969 if (spapr->htab) { 1970 spapr->htab_save_index = 0; 1971 spapr->htab_first_pass = true; 1972 } else { 1973 if (spapr->htab_shift) { 1974 assert(kvm_enabled()); 1975 } 1976 } 1977 1978 1979 return 0; 1980 } 1981 1982 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr, 1983 int chunkstart, int n_valid, int n_invalid) 1984 { 1985 qemu_put_be32(f, chunkstart); 1986 qemu_put_be16(f, n_valid); 1987 qemu_put_be16(f, n_invalid); 1988 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1989 HASH_PTE_SIZE_64 * n_valid); 1990 } 1991 1992 static void htab_save_end_marker(QEMUFile *f) 1993 { 1994 qemu_put_be32(f, 0); 1995 qemu_put_be16(f, 0); 1996 qemu_put_be16(f, 0); 1997 } 1998 1999 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 2000 int64_t max_ns) 2001 { 2002 bool has_timeout = max_ns != -1; 2003 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2004 int index = spapr->htab_save_index; 2005 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2006 2007 assert(spapr->htab_first_pass); 2008 2009 do { 2010 int chunkstart; 2011 2012 /* Consume invalid HPTEs */ 2013 while ((index < htabslots) 2014 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2015 CLEAN_HPTE(HPTE(spapr->htab, index)); 2016 index++; 2017 } 2018 2019 /* Consume valid HPTEs */ 2020 chunkstart = index; 2021 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2022 && HPTE_VALID(HPTE(spapr->htab, index))) { 2023 CLEAN_HPTE(HPTE(spapr->htab, index)); 2024 index++; 2025 } 2026 2027 if (index > chunkstart) { 2028 int n_valid = index - chunkstart; 2029 2030 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2031 2032 if (has_timeout && 2033 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2034 break; 2035 } 2036 } 2037 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2038 2039 if (index >= htabslots) { 2040 assert(index == htabslots); 2041 index = 0; 2042 spapr->htab_first_pass = false; 2043 } 2044 spapr->htab_save_index = index; 2045 } 2046 2047 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 2048 int64_t max_ns) 2049 { 2050 bool final = max_ns < 0; 2051 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2052 int examined = 0, sent = 0; 2053 int index = spapr->htab_save_index; 2054 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2055 2056 assert(!spapr->htab_first_pass); 2057 2058 do { 2059 int chunkstart, invalidstart; 2060 2061 /* Consume non-dirty HPTEs */ 2062 while ((index < htabslots) 2063 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2064 index++; 2065 examined++; 2066 } 2067 2068 chunkstart = index; 2069 /* Consume valid dirty HPTEs */ 2070 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2071 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2072 && HPTE_VALID(HPTE(spapr->htab, index))) { 2073 CLEAN_HPTE(HPTE(spapr->htab, index)); 2074 index++; 2075 examined++; 2076 } 2077 2078 invalidstart = index; 2079 /* Consume invalid dirty HPTEs */ 2080 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2081 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2082 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2083 CLEAN_HPTE(HPTE(spapr->htab, index)); 2084 index++; 2085 examined++; 2086 } 2087 2088 if (index > chunkstart) { 2089 int n_valid = invalidstart - chunkstart; 2090 int n_invalid = index - invalidstart; 2091 2092 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2093 sent += index - chunkstart; 2094 2095 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2096 break; 2097 } 2098 } 2099 2100 if (examined >= htabslots) { 2101 break; 2102 } 2103 2104 if (index >= htabslots) { 2105 assert(index == htabslots); 2106 index = 0; 2107 } 2108 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2109 2110 if (index >= htabslots) { 2111 assert(index == htabslots); 2112 index = 0; 2113 } 2114 2115 spapr->htab_save_index = index; 2116 2117 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2118 } 2119 2120 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2121 #define MAX_KVM_BUF_SIZE 2048 2122 2123 static int htab_save_iterate(QEMUFile *f, void *opaque) 2124 { 2125 sPAPRMachineState *spapr = opaque; 2126 int fd; 2127 int rc = 0; 2128 2129 /* Iteration header */ 2130 if (!spapr->htab_shift) { 2131 qemu_put_be32(f, -1); 2132 return 1; 2133 } else { 2134 qemu_put_be32(f, 0); 2135 } 2136 2137 if (!spapr->htab) { 2138 assert(kvm_enabled()); 2139 2140 fd = get_htab_fd(spapr); 2141 if (fd < 0) { 2142 return fd; 2143 } 2144 2145 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2146 if (rc < 0) { 2147 return rc; 2148 } 2149 } else if (spapr->htab_first_pass) { 2150 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2151 } else { 2152 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2153 } 2154 2155 htab_save_end_marker(f); 2156 2157 return rc; 2158 } 2159 2160 static int htab_save_complete(QEMUFile *f, void *opaque) 2161 { 2162 sPAPRMachineState *spapr = opaque; 2163 int fd; 2164 2165 /* Iteration header */ 2166 if (!spapr->htab_shift) { 2167 qemu_put_be32(f, -1); 2168 return 0; 2169 } else { 2170 qemu_put_be32(f, 0); 2171 } 2172 2173 if (!spapr->htab) { 2174 int rc; 2175 2176 assert(kvm_enabled()); 2177 2178 fd = get_htab_fd(spapr); 2179 if (fd < 0) { 2180 return fd; 2181 } 2182 2183 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2184 if (rc < 0) { 2185 return rc; 2186 } 2187 } else { 2188 if (spapr->htab_first_pass) { 2189 htab_save_first_pass(f, spapr, -1); 2190 } 2191 htab_save_later_pass(f, spapr, -1); 2192 } 2193 2194 /* End marker */ 2195 htab_save_end_marker(f); 2196 2197 return 0; 2198 } 2199 2200 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2201 { 2202 sPAPRMachineState *spapr = opaque; 2203 uint32_t section_hdr; 2204 int fd = -1; 2205 Error *local_err = NULL; 2206 2207 if (version_id < 1 || version_id > 1) { 2208 error_report("htab_load() bad version"); 2209 return -EINVAL; 2210 } 2211 2212 section_hdr = qemu_get_be32(f); 2213 2214 if (section_hdr == -1) { 2215 spapr_free_hpt(spapr); 2216 return 0; 2217 } 2218 2219 if (section_hdr) { 2220 /* First section gives the htab size */ 2221 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2222 if (local_err) { 2223 error_report_err(local_err); 2224 return -EINVAL; 2225 } 2226 return 0; 2227 } 2228 2229 if (!spapr->htab) { 2230 assert(kvm_enabled()); 2231 2232 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2233 if (fd < 0) { 2234 error_report_err(local_err); 2235 return fd; 2236 } 2237 } 2238 2239 while (true) { 2240 uint32_t index; 2241 uint16_t n_valid, n_invalid; 2242 2243 index = qemu_get_be32(f); 2244 n_valid = qemu_get_be16(f); 2245 n_invalid = qemu_get_be16(f); 2246 2247 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2248 /* End of Stream */ 2249 break; 2250 } 2251 2252 if ((index + n_valid + n_invalid) > 2253 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2254 /* Bad index in stream */ 2255 error_report( 2256 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2257 index, n_valid, n_invalid, spapr->htab_shift); 2258 return -EINVAL; 2259 } 2260 2261 if (spapr->htab) { 2262 if (n_valid) { 2263 qemu_get_buffer(f, HPTE(spapr->htab, index), 2264 HASH_PTE_SIZE_64 * n_valid); 2265 } 2266 if (n_invalid) { 2267 memset(HPTE(spapr->htab, index + n_valid), 0, 2268 HASH_PTE_SIZE_64 * n_invalid); 2269 } 2270 } else { 2271 int rc; 2272 2273 assert(fd >= 0); 2274 2275 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2276 if (rc < 0) { 2277 return rc; 2278 } 2279 } 2280 } 2281 2282 if (!spapr->htab) { 2283 assert(fd >= 0); 2284 close(fd); 2285 } 2286 2287 return 0; 2288 } 2289 2290 static void htab_save_cleanup(void *opaque) 2291 { 2292 sPAPRMachineState *spapr = opaque; 2293 2294 close_htab_fd(spapr); 2295 } 2296 2297 static SaveVMHandlers savevm_htab_handlers = { 2298 .save_setup = htab_save_setup, 2299 .save_live_iterate = htab_save_iterate, 2300 .save_live_complete_precopy = htab_save_complete, 2301 .save_cleanup = htab_save_cleanup, 2302 .load_state = htab_load, 2303 }; 2304 2305 static void spapr_boot_set(void *opaque, const char *boot_device, 2306 Error **errp) 2307 { 2308 MachineState *machine = MACHINE(opaque); 2309 machine->boot_order = g_strdup(boot_device); 2310 } 2311 2312 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 2313 { 2314 MachineState *machine = MACHINE(spapr); 2315 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2316 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2317 int i; 2318 2319 for (i = 0; i < nr_lmbs; i++) { 2320 uint64_t addr; 2321 2322 addr = i * lmb_size + machine->device_memory->base; 2323 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2324 addr / lmb_size); 2325 } 2326 } 2327 2328 /* 2329 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2330 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2331 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2332 */ 2333 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2334 { 2335 int i; 2336 2337 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2338 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2339 " is not aligned to %" PRIu64 " MiB", 2340 machine->ram_size, 2341 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2342 return; 2343 } 2344 2345 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2346 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2347 " is not aligned to %" PRIu64 " MiB", 2348 machine->ram_size, 2349 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2350 return; 2351 } 2352 2353 for (i = 0; i < nb_numa_nodes; i++) { 2354 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2355 error_setg(errp, 2356 "Node %d memory size 0x%" PRIx64 2357 " is not aligned to %" PRIu64 " MiB", 2358 i, numa_info[i].node_mem, 2359 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2360 return; 2361 } 2362 } 2363 } 2364 2365 /* find cpu slot in machine->possible_cpus by core_id */ 2366 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2367 { 2368 int index = id / smp_threads; 2369 2370 if (index >= ms->possible_cpus->len) { 2371 return NULL; 2372 } 2373 if (idx) { 2374 *idx = index; 2375 } 2376 return &ms->possible_cpus->cpus[index]; 2377 } 2378 2379 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) 2380 { 2381 Error *local_err = NULL; 2382 bool vsmt_user = !!spapr->vsmt; 2383 int kvm_smt = kvmppc_smt_threads(); 2384 int ret; 2385 2386 if (!kvm_enabled() && (smp_threads > 1)) { 2387 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2388 "on a pseries machine"); 2389 goto out; 2390 } 2391 if (!is_power_of_2(smp_threads)) { 2392 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2393 "machine because it must be a power of 2", smp_threads); 2394 goto out; 2395 } 2396 2397 /* Detemine the VSMT mode to use: */ 2398 if (vsmt_user) { 2399 if (spapr->vsmt < smp_threads) { 2400 error_setg(&local_err, "Cannot support VSMT mode %d" 2401 " because it must be >= threads/core (%d)", 2402 spapr->vsmt, smp_threads); 2403 goto out; 2404 } 2405 /* In this case, spapr->vsmt has been set by the command line */ 2406 } else { 2407 /* 2408 * Default VSMT value is tricky, because we need it to be as 2409 * consistent as possible (for migration), but this requires 2410 * changing it for at least some existing cases. We pick 8 as 2411 * the value that we'd get with KVM on POWER8, the 2412 * overwhelmingly common case in production systems. 2413 */ 2414 spapr->vsmt = MAX(8, smp_threads); 2415 } 2416 2417 /* KVM: If necessary, set the SMT mode: */ 2418 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2419 ret = kvmppc_set_smt_threads(spapr->vsmt); 2420 if (ret) { 2421 /* Looks like KVM isn't able to change VSMT mode */ 2422 error_setg(&local_err, 2423 "Failed to set KVM's VSMT mode to %d (errno %d)", 2424 spapr->vsmt, ret); 2425 /* We can live with that if the default one is big enough 2426 * for the number of threads, and a submultiple of the one 2427 * we want. In this case we'll waste some vcpu ids, but 2428 * behaviour will be correct */ 2429 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2430 warn_report_err(local_err); 2431 local_err = NULL; 2432 goto out; 2433 } else { 2434 if (!vsmt_user) { 2435 error_append_hint(&local_err, 2436 "On PPC, a VM with %d threads/core" 2437 " on a host with %d threads/core" 2438 " requires the use of VSMT mode %d.\n", 2439 smp_threads, kvm_smt, spapr->vsmt); 2440 } 2441 kvmppc_hint_smt_possible(&local_err); 2442 goto out; 2443 } 2444 } 2445 } 2446 /* else TCG: nothing to do currently */ 2447 out: 2448 error_propagate(errp, local_err); 2449 } 2450 2451 static void spapr_init_cpus(sPAPRMachineState *spapr) 2452 { 2453 MachineState *machine = MACHINE(spapr); 2454 MachineClass *mc = MACHINE_GET_CLASS(machine); 2455 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2456 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2457 const CPUArchIdList *possible_cpus; 2458 int boot_cores_nr = smp_cpus / smp_threads; 2459 int i; 2460 2461 possible_cpus = mc->possible_cpu_arch_ids(machine); 2462 if (mc->has_hotpluggable_cpus) { 2463 if (smp_cpus % smp_threads) { 2464 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2465 smp_cpus, smp_threads); 2466 exit(1); 2467 } 2468 if (max_cpus % smp_threads) { 2469 error_report("max_cpus (%u) must be multiple of threads (%u)", 2470 max_cpus, smp_threads); 2471 exit(1); 2472 } 2473 } else { 2474 if (max_cpus != smp_cpus) { 2475 error_report("This machine version does not support CPU hotplug"); 2476 exit(1); 2477 } 2478 boot_cores_nr = possible_cpus->len; 2479 } 2480 2481 /* VSMT must be set in order to be able to compute VCPU ids, ie to 2482 * call xics_max_server_number() or spapr_vcpu_id(). 2483 */ 2484 spapr_set_vsmt_mode(spapr, &error_fatal); 2485 2486 if (smc->pre_2_10_has_unused_icps) { 2487 int i; 2488 2489 for (i = 0; i < xics_max_server_number(spapr); i++) { 2490 /* Dummy entries get deregistered when real ICPState objects 2491 * are registered during CPU core hotplug. 2492 */ 2493 pre_2_10_vmstate_register_dummy_icp(i); 2494 } 2495 } 2496 2497 for (i = 0; i < possible_cpus->len; i++) { 2498 int core_id = i * smp_threads; 2499 2500 if (mc->has_hotpluggable_cpus) { 2501 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2502 spapr_vcpu_id(spapr, core_id)); 2503 } 2504 2505 if (i < boot_cores_nr) { 2506 Object *core = object_new(type); 2507 int nr_threads = smp_threads; 2508 2509 /* Handle the partially filled core for older machine types */ 2510 if ((i + 1) * smp_threads >= smp_cpus) { 2511 nr_threads = smp_cpus - i * smp_threads; 2512 } 2513 2514 object_property_set_int(core, nr_threads, "nr-threads", 2515 &error_fatal); 2516 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2517 &error_fatal); 2518 object_property_set_bool(core, true, "realized", &error_fatal); 2519 } 2520 } 2521 } 2522 2523 /* pSeries LPAR / sPAPR hardware init */ 2524 static void spapr_machine_init(MachineState *machine) 2525 { 2526 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2527 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2528 const char *kernel_filename = machine->kernel_filename; 2529 const char *initrd_filename = machine->initrd_filename; 2530 PCIHostState *phb; 2531 int i; 2532 MemoryRegion *sysmem = get_system_memory(); 2533 MemoryRegion *ram = g_new(MemoryRegion, 1); 2534 hwaddr node0_size = spapr_node0_size(machine); 2535 long load_limit, fw_size; 2536 char *filename; 2537 Error *resize_hpt_err = NULL; 2538 2539 msi_nonbroken = true; 2540 2541 QLIST_INIT(&spapr->phbs); 2542 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2543 2544 /* Determine capabilities to run with */ 2545 spapr_caps_init(spapr); 2546 2547 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2548 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2549 /* 2550 * If the user explicitly requested a mode we should either 2551 * supply it, or fail completely (which we do below). But if 2552 * it's not set explicitly, we reset our mode to something 2553 * that works 2554 */ 2555 if (resize_hpt_err) { 2556 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2557 error_free(resize_hpt_err); 2558 resize_hpt_err = NULL; 2559 } else { 2560 spapr->resize_hpt = smc->resize_hpt_default; 2561 } 2562 } 2563 2564 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2565 2566 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2567 /* 2568 * User requested HPT resize, but this host can't supply it. Bail out 2569 */ 2570 error_report_err(resize_hpt_err); 2571 exit(1); 2572 } 2573 2574 spapr->rma_size = node0_size; 2575 2576 /* With KVM, we don't actually know whether KVM supports an 2577 * unbounded RMA (PR KVM) or is limited by the hash table size 2578 * (HV KVM using VRMA), so we always assume the latter 2579 * 2580 * In that case, we also limit the initial allocations for RTAS 2581 * etc... to 256M since we have no way to know what the VRMA size 2582 * is going to be as it depends on the size of the hash table 2583 * which isn't determined yet. 2584 */ 2585 if (kvm_enabled()) { 2586 spapr->vrma_adjust = 1; 2587 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2588 } 2589 2590 /* Actually we don't support unbounded RMA anymore since we added 2591 * proper emulation of HV mode. The max we can get is 16G which 2592 * also happens to be what we configure for PAPR mode so make sure 2593 * we don't do anything bigger than that 2594 */ 2595 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2596 2597 if (spapr->rma_size > node0_size) { 2598 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2599 spapr->rma_size); 2600 exit(1); 2601 } 2602 2603 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2604 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2605 2606 /* Set up Interrupt Controller before we create the VCPUs */ 2607 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); 2608 2609 /* Set up containers for ibm,client-architecture-support negotiated options 2610 */ 2611 spapr->ov5 = spapr_ovec_new(); 2612 spapr->ov5_cas = spapr_ovec_new(); 2613 2614 if (smc->dr_lmb_enabled) { 2615 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2616 spapr_validate_node_memory(machine, &error_fatal); 2617 } 2618 2619 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2620 2621 /* advertise support for dedicated HP event source to guests */ 2622 if (spapr->use_hotplug_event_source) { 2623 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2624 } 2625 2626 /* advertise support for HPT resizing */ 2627 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2628 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2629 } 2630 2631 /* advertise support for ibm,dyamic-memory-v2 */ 2632 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2633 2634 /* init CPUs */ 2635 spapr_init_cpus(spapr); 2636 2637 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2638 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2639 spapr->max_compat_pvr)) { 2640 /* KVM and TCG always allow GTSE with radix... */ 2641 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2642 } 2643 /* ... but not with hash (currently). */ 2644 2645 if (kvm_enabled()) { 2646 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2647 kvmppc_enable_logical_ci_hcalls(); 2648 kvmppc_enable_set_mode_hcall(); 2649 2650 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2651 kvmppc_enable_clear_ref_mod_hcalls(); 2652 } 2653 2654 /* allocate RAM */ 2655 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2656 machine->ram_size); 2657 memory_region_add_subregion(sysmem, 0, ram); 2658 2659 /* always allocate the device memory information */ 2660 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2661 2662 /* initialize hotplug memory address space */ 2663 if (machine->ram_size < machine->maxram_size) { 2664 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2665 /* 2666 * Limit the number of hotpluggable memory slots to half the number 2667 * slots that KVM supports, leaving the other half for PCI and other 2668 * devices. However ensure that number of slots doesn't drop below 32. 2669 */ 2670 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2671 SPAPR_MAX_RAM_SLOTS; 2672 2673 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2674 max_memslots = SPAPR_MAX_RAM_SLOTS; 2675 } 2676 if (machine->ram_slots > max_memslots) { 2677 error_report("Specified number of memory slots %" 2678 PRIu64" exceeds max supported %d", 2679 machine->ram_slots, max_memslots); 2680 exit(1); 2681 } 2682 2683 machine->device_memory->base = ROUND_UP(machine->ram_size, 2684 SPAPR_DEVICE_MEM_ALIGN); 2685 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2686 "device-memory", device_mem_size); 2687 memory_region_add_subregion(sysmem, machine->device_memory->base, 2688 &machine->device_memory->mr); 2689 } 2690 2691 if (smc->dr_lmb_enabled) { 2692 spapr_create_lmb_dr_connectors(spapr); 2693 } 2694 2695 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2696 if (!filename) { 2697 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2698 exit(1); 2699 } 2700 spapr->rtas_size = get_image_size(filename); 2701 if (spapr->rtas_size < 0) { 2702 error_report("Could not get size of LPAR rtas '%s'", filename); 2703 exit(1); 2704 } 2705 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2706 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2707 error_report("Could not load LPAR rtas '%s'", filename); 2708 exit(1); 2709 } 2710 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2711 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2712 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2713 exit(1); 2714 } 2715 g_free(filename); 2716 2717 /* Set up RTAS event infrastructure */ 2718 spapr_events_init(spapr); 2719 2720 /* Set up the RTC RTAS interfaces */ 2721 spapr_rtc_create(spapr); 2722 2723 /* Set up VIO bus */ 2724 spapr->vio_bus = spapr_vio_bus_init(); 2725 2726 for (i = 0; i < serial_max_hds(); i++) { 2727 if (serial_hd(i)) { 2728 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2729 } 2730 } 2731 2732 /* We always have at least the nvram device on VIO */ 2733 spapr_create_nvram(spapr); 2734 2735 /* Set up PCI */ 2736 spapr_pci_rtas_init(); 2737 2738 phb = spapr_create_phb(spapr, 0); 2739 2740 for (i = 0; i < nb_nics; i++) { 2741 NICInfo *nd = &nd_table[i]; 2742 2743 if (!nd->model) { 2744 nd->model = g_strdup("spapr-vlan"); 2745 } 2746 2747 if (g_str_equal(nd->model, "spapr-vlan") || 2748 g_str_equal(nd->model, "ibmveth")) { 2749 spapr_vlan_create(spapr->vio_bus, nd); 2750 } else { 2751 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2752 } 2753 } 2754 2755 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2756 spapr_vscsi_create(spapr->vio_bus); 2757 } 2758 2759 /* Graphics */ 2760 if (spapr_vga_init(phb->bus, &error_fatal)) { 2761 spapr->has_graphics = true; 2762 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2763 } 2764 2765 if (machine->usb) { 2766 if (smc->use_ohci_by_default) { 2767 pci_create_simple(phb->bus, -1, "pci-ohci"); 2768 } else { 2769 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2770 } 2771 2772 if (spapr->has_graphics) { 2773 USBBus *usb_bus = usb_bus_find(-1); 2774 2775 usb_create_simple(usb_bus, "usb-kbd"); 2776 usb_create_simple(usb_bus, "usb-mouse"); 2777 } 2778 } 2779 2780 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) { 2781 error_report( 2782 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2783 MIN_RMA_SLOF); 2784 exit(1); 2785 } 2786 2787 if (kernel_filename) { 2788 uint64_t lowaddr = 0; 2789 2790 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2791 NULL, NULL, &lowaddr, NULL, 1, 2792 PPC_ELF_MACHINE, 0, 0); 2793 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2794 spapr->kernel_size = load_elf(kernel_filename, 2795 translate_kernel_address, NULL, NULL, 2796 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2797 0, 0); 2798 spapr->kernel_le = spapr->kernel_size > 0; 2799 } 2800 if (spapr->kernel_size < 0) { 2801 error_report("error loading %s: %s", kernel_filename, 2802 load_elf_strerror(spapr->kernel_size)); 2803 exit(1); 2804 } 2805 2806 /* load initrd */ 2807 if (initrd_filename) { 2808 /* Try to locate the initrd in the gap between the kernel 2809 * and the firmware. Add a bit of space just in case 2810 */ 2811 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2812 + 0x1ffff) & ~0xffff; 2813 spapr->initrd_size = load_image_targphys(initrd_filename, 2814 spapr->initrd_base, 2815 load_limit 2816 - spapr->initrd_base); 2817 if (spapr->initrd_size < 0) { 2818 error_report("could not load initial ram disk '%s'", 2819 initrd_filename); 2820 exit(1); 2821 } 2822 } 2823 } 2824 2825 if (bios_name == NULL) { 2826 bios_name = FW_FILE_NAME; 2827 } 2828 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2829 if (!filename) { 2830 error_report("Could not find LPAR firmware '%s'", bios_name); 2831 exit(1); 2832 } 2833 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2834 if (fw_size <= 0) { 2835 error_report("Could not load LPAR firmware '%s'", filename); 2836 exit(1); 2837 } 2838 g_free(filename); 2839 2840 /* FIXME: Should register things through the MachineState's qdev 2841 * interface, this is a legacy from the sPAPREnvironment structure 2842 * which predated MachineState but had a similar function */ 2843 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2844 register_savevm_live(NULL, "spapr/htab", -1, 1, 2845 &savevm_htab_handlers, spapr); 2846 2847 qemu_register_boot_set(spapr_boot_set, spapr); 2848 2849 if (kvm_enabled()) { 2850 /* to stop and start vmclock */ 2851 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2852 &spapr->tb); 2853 2854 kvmppc_spapr_enable_inkernel_multitce(); 2855 } 2856 } 2857 2858 static int spapr_kvm_type(const char *vm_type) 2859 { 2860 if (!vm_type) { 2861 return 0; 2862 } 2863 2864 if (!strcmp(vm_type, "HV")) { 2865 return 1; 2866 } 2867 2868 if (!strcmp(vm_type, "PR")) { 2869 return 2; 2870 } 2871 2872 error_report("Unknown kvm-type specified '%s'", vm_type); 2873 exit(1); 2874 } 2875 2876 /* 2877 * Implementation of an interface to adjust firmware path 2878 * for the bootindex property handling. 2879 */ 2880 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2881 DeviceState *dev) 2882 { 2883 #define CAST(type, obj, name) \ 2884 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2885 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2886 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2887 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 2888 2889 if (d) { 2890 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2891 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2892 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2893 2894 if (spapr) { 2895 /* 2896 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2897 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2898 * in the top 16 bits of the 64-bit LUN 2899 */ 2900 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2901 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2902 (uint64_t)id << 48); 2903 } else if (virtio) { 2904 /* 2905 * We use SRP luns of the form 01000000 | (target << 8) | lun 2906 * in the top 32 bits of the 64-bit LUN 2907 * Note: the quote above is from SLOF and it is wrong, 2908 * the actual binding is: 2909 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2910 */ 2911 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2912 if (d->lun >= 256) { 2913 /* Use the LUN "flat space addressing method" */ 2914 id |= 0x4000; 2915 } 2916 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2917 (uint64_t)id << 32); 2918 } else if (usb) { 2919 /* 2920 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2921 * in the top 32 bits of the 64-bit LUN 2922 */ 2923 unsigned usb_port = atoi(usb->port->path); 2924 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2925 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2926 (uint64_t)id << 32); 2927 } 2928 } 2929 2930 /* 2931 * SLOF probes the USB devices, and if it recognizes that the device is a 2932 * storage device, it changes its name to "storage" instead of "usb-host", 2933 * and additionally adds a child node for the SCSI LUN, so the correct 2934 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2935 */ 2936 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2937 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2938 if (usb_host_dev_is_scsi_storage(usbdev)) { 2939 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2940 } 2941 } 2942 2943 if (phb) { 2944 /* Replace "pci" with "pci@800000020000000" */ 2945 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2946 } 2947 2948 if (vsc) { 2949 /* Same logic as virtio above */ 2950 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 2951 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 2952 } 2953 2954 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 2955 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 2956 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 2957 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 2958 } 2959 2960 return NULL; 2961 } 2962 2963 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2964 { 2965 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2966 2967 return g_strdup(spapr->kvm_type); 2968 } 2969 2970 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2971 { 2972 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2973 2974 g_free(spapr->kvm_type); 2975 spapr->kvm_type = g_strdup(value); 2976 } 2977 2978 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2979 { 2980 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2981 2982 return spapr->use_hotplug_event_source; 2983 } 2984 2985 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2986 Error **errp) 2987 { 2988 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2989 2990 spapr->use_hotplug_event_source = value; 2991 } 2992 2993 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 2994 { 2995 return true; 2996 } 2997 2998 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 2999 { 3000 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3001 3002 switch (spapr->resize_hpt) { 3003 case SPAPR_RESIZE_HPT_DEFAULT: 3004 return g_strdup("default"); 3005 case SPAPR_RESIZE_HPT_DISABLED: 3006 return g_strdup("disabled"); 3007 case SPAPR_RESIZE_HPT_ENABLED: 3008 return g_strdup("enabled"); 3009 case SPAPR_RESIZE_HPT_REQUIRED: 3010 return g_strdup("required"); 3011 } 3012 g_assert_not_reached(); 3013 } 3014 3015 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3016 { 3017 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3018 3019 if (strcmp(value, "default") == 0) { 3020 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3021 } else if (strcmp(value, "disabled") == 0) { 3022 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3023 } else if (strcmp(value, "enabled") == 0) { 3024 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3025 } else if (strcmp(value, "required") == 0) { 3026 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3027 } else { 3028 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3029 } 3030 } 3031 3032 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3033 void *opaque, Error **errp) 3034 { 3035 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3036 } 3037 3038 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3039 void *opaque, Error **errp) 3040 { 3041 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3042 } 3043 3044 static void spapr_instance_init(Object *obj) 3045 { 3046 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3047 3048 spapr->htab_fd = -1; 3049 spapr->use_hotplug_event_source = true; 3050 object_property_add_str(obj, "kvm-type", 3051 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3052 object_property_set_description(obj, "kvm-type", 3053 "Specifies the KVM virtualization mode (HV, PR)", 3054 NULL); 3055 object_property_add_bool(obj, "modern-hotplug-events", 3056 spapr_get_modern_hotplug_events, 3057 spapr_set_modern_hotplug_events, 3058 NULL); 3059 object_property_set_description(obj, "modern-hotplug-events", 3060 "Use dedicated hotplug event mechanism in" 3061 " place of standard EPOW events when possible" 3062 " (required for memory hot-unplug support)", 3063 NULL); 3064 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3065 "Maximum permitted CPU compatibility mode", 3066 &error_fatal); 3067 3068 object_property_add_str(obj, "resize-hpt", 3069 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3070 object_property_set_description(obj, "resize-hpt", 3071 "Resizing of the Hash Page Table (enabled, disabled, required)", 3072 NULL); 3073 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3074 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3075 object_property_set_description(obj, "vsmt", 3076 "Virtual SMT: KVM behaves as if this were" 3077 " the host's SMT mode", &error_abort); 3078 object_property_add_bool(obj, "vfio-no-msix-emulation", 3079 spapr_get_msix_emulation, NULL, NULL); 3080 } 3081 3082 static void spapr_machine_finalizefn(Object *obj) 3083 { 3084 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3085 3086 g_free(spapr->kvm_type); 3087 } 3088 3089 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3090 { 3091 cpu_synchronize_state(cs); 3092 ppc_cpu_do_system_reset(cs); 3093 } 3094 3095 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3096 { 3097 CPUState *cs; 3098 3099 CPU_FOREACH(cs) { 3100 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3101 } 3102 } 3103 3104 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3105 uint32_t node, bool dedicated_hp_event_source, 3106 Error **errp) 3107 { 3108 sPAPRDRConnector *drc; 3109 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3110 int i, fdt_offset, fdt_size; 3111 void *fdt; 3112 uint64_t addr = addr_start; 3113 bool hotplugged = spapr_drc_hotplugged(dev); 3114 Error *local_err = NULL; 3115 3116 for (i = 0; i < nr_lmbs; i++) { 3117 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3118 addr / SPAPR_MEMORY_BLOCK_SIZE); 3119 g_assert(drc); 3120 3121 fdt = create_device_tree(&fdt_size); 3122 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 3123 SPAPR_MEMORY_BLOCK_SIZE); 3124 3125 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3126 if (local_err) { 3127 while (addr > addr_start) { 3128 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3129 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3130 addr / SPAPR_MEMORY_BLOCK_SIZE); 3131 spapr_drc_detach(drc); 3132 } 3133 g_free(fdt); 3134 error_propagate(errp, local_err); 3135 return; 3136 } 3137 if (!hotplugged) { 3138 spapr_drc_reset(drc); 3139 } 3140 addr += SPAPR_MEMORY_BLOCK_SIZE; 3141 } 3142 /* send hotplug notification to the 3143 * guest only in case of hotplugged memory 3144 */ 3145 if (hotplugged) { 3146 if (dedicated_hp_event_source) { 3147 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3148 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3149 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3150 nr_lmbs, 3151 spapr_drc_index(drc)); 3152 } else { 3153 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3154 nr_lmbs); 3155 } 3156 } 3157 } 3158 3159 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3160 Error **errp) 3161 { 3162 Error *local_err = NULL; 3163 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3164 PCDIMMDevice *dimm = PC_DIMM(dev); 3165 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3166 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3167 uint64_t size, addr; 3168 uint32_t node; 3169 3170 size = memory_region_size(mr); 3171 3172 pc_dimm_plug(dev, MACHINE(ms), &local_err); 3173 if (local_err) { 3174 goto out; 3175 } 3176 3177 addr = object_property_get_uint(OBJECT(dimm), 3178 PC_DIMM_ADDR_PROP, &local_err); 3179 if (local_err) { 3180 goto out_unplug; 3181 } 3182 3183 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, 3184 &error_abort); 3185 spapr_add_lmbs(dev, addr, size, node, 3186 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3187 &local_err); 3188 if (local_err) { 3189 goto out_unplug; 3190 } 3191 3192 return; 3193 3194 out_unplug: 3195 pc_dimm_unplug(dev, MACHINE(ms)); 3196 out: 3197 error_propagate(errp, local_err); 3198 } 3199 3200 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3201 Error **errp) 3202 { 3203 const sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3204 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3205 PCDIMMDevice *dimm = PC_DIMM(dev); 3206 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3207 Error *local_err = NULL; 3208 MemoryRegion *mr; 3209 uint64_t size; 3210 Object *memdev; 3211 hwaddr pagesize; 3212 3213 if (!smc->dr_lmb_enabled) { 3214 error_setg(errp, "Memory hotplug not supported for this machine"); 3215 return; 3216 } 3217 3218 mr = ddc->get_memory_region(dimm, errp); 3219 if (!mr) { 3220 return; 3221 } 3222 size = memory_region_size(mr); 3223 3224 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3225 error_setg(errp, "Hotplugged memory size must be a multiple of " 3226 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3227 return; 3228 } 3229 3230 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3231 &error_abort); 3232 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3233 spapr_check_pagesize(spapr, pagesize, &local_err); 3234 if (local_err) { 3235 error_propagate(errp, local_err); 3236 return; 3237 } 3238 3239 pc_dimm_pre_plug(dev, MACHINE(hotplug_dev), NULL, errp); 3240 } 3241 3242 struct sPAPRDIMMState { 3243 PCDIMMDevice *dimm; 3244 uint32_t nr_lmbs; 3245 QTAILQ_ENTRY(sPAPRDIMMState) next; 3246 }; 3247 3248 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 3249 PCDIMMDevice *dimm) 3250 { 3251 sPAPRDIMMState *dimm_state = NULL; 3252 3253 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3254 if (dimm_state->dimm == dimm) { 3255 break; 3256 } 3257 } 3258 return dimm_state; 3259 } 3260 3261 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 3262 uint32_t nr_lmbs, 3263 PCDIMMDevice *dimm) 3264 { 3265 sPAPRDIMMState *ds = NULL; 3266 3267 /* 3268 * If this request is for a DIMM whose removal had failed earlier 3269 * (due to guest's refusal to remove the LMBs), we would have this 3270 * dimm already in the pending_dimm_unplugs list. In that 3271 * case don't add again. 3272 */ 3273 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3274 if (!ds) { 3275 ds = g_malloc0(sizeof(sPAPRDIMMState)); 3276 ds->nr_lmbs = nr_lmbs; 3277 ds->dimm = dimm; 3278 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3279 } 3280 return ds; 3281 } 3282 3283 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 3284 sPAPRDIMMState *dimm_state) 3285 { 3286 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3287 g_free(dimm_state); 3288 } 3289 3290 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 3291 PCDIMMDevice *dimm) 3292 { 3293 sPAPRDRConnector *drc; 3294 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3295 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3296 uint64_t size = memory_region_size(mr); 3297 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3298 uint32_t avail_lmbs = 0; 3299 uint64_t addr_start, addr; 3300 int i; 3301 3302 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3303 &error_abort); 3304 3305 addr = addr_start; 3306 for (i = 0; i < nr_lmbs; i++) { 3307 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3308 addr / SPAPR_MEMORY_BLOCK_SIZE); 3309 g_assert(drc); 3310 if (drc->dev) { 3311 avail_lmbs++; 3312 } 3313 addr += SPAPR_MEMORY_BLOCK_SIZE; 3314 } 3315 3316 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3317 } 3318 3319 /* Callback to be called during DRC release. */ 3320 void spapr_lmb_release(DeviceState *dev) 3321 { 3322 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3323 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3324 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3325 3326 /* This information will get lost if a migration occurs 3327 * during the unplug process. In this case recover it. */ 3328 if (ds == NULL) { 3329 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3330 g_assert(ds); 3331 /* The DRC being examined by the caller at least must be counted */ 3332 g_assert(ds->nr_lmbs); 3333 } 3334 3335 if (--ds->nr_lmbs) { 3336 return; 3337 } 3338 3339 /* 3340 * Now that all the LMBs have been removed by the guest, call the 3341 * unplug handler chain. This can never fail. 3342 */ 3343 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3344 } 3345 3346 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3347 { 3348 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3349 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3350 3351 pc_dimm_unplug(dev, MACHINE(hotplug_dev)); 3352 object_unparent(OBJECT(dev)); 3353 spapr_pending_dimm_unplugs_remove(spapr, ds); 3354 } 3355 3356 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3357 DeviceState *dev, Error **errp) 3358 { 3359 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3360 Error *local_err = NULL; 3361 PCDIMMDevice *dimm = PC_DIMM(dev); 3362 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3363 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3364 uint32_t nr_lmbs; 3365 uint64_t size, addr_start, addr; 3366 int i; 3367 sPAPRDRConnector *drc; 3368 3369 size = memory_region_size(mr); 3370 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3371 3372 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3373 &local_err); 3374 if (local_err) { 3375 goto out; 3376 } 3377 3378 /* 3379 * An existing pending dimm state for this DIMM means that there is an 3380 * unplug operation in progress, waiting for the spapr_lmb_release 3381 * callback to complete the job (BQL can't cover that far). In this case, 3382 * bail out to avoid detaching DRCs that were already released. 3383 */ 3384 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3385 error_setg(&local_err, 3386 "Memory unplug already in progress for device %s", 3387 dev->id); 3388 goto out; 3389 } 3390 3391 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3392 3393 addr = addr_start; 3394 for (i = 0; i < nr_lmbs; i++) { 3395 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3396 addr / SPAPR_MEMORY_BLOCK_SIZE); 3397 g_assert(drc); 3398 3399 spapr_drc_detach(drc); 3400 addr += SPAPR_MEMORY_BLOCK_SIZE; 3401 } 3402 3403 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3404 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3405 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3406 nr_lmbs, spapr_drc_index(drc)); 3407 out: 3408 error_propagate(errp, local_err); 3409 } 3410 3411 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 3412 sPAPRMachineState *spapr) 3413 { 3414 PowerPCCPU *cpu = POWERPC_CPU(cs); 3415 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3416 int id = spapr_get_vcpu_id(cpu); 3417 void *fdt; 3418 int offset, fdt_size; 3419 char *nodename; 3420 3421 fdt = create_device_tree(&fdt_size); 3422 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3423 offset = fdt_add_subnode(fdt, 0, nodename); 3424 3425 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3426 g_free(nodename); 3427 3428 *fdt_offset = offset; 3429 return fdt; 3430 } 3431 3432 /* Callback to be called during DRC release. */ 3433 void spapr_core_release(DeviceState *dev) 3434 { 3435 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3436 3437 /* Call the unplug handler chain. This can never fail. */ 3438 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3439 } 3440 3441 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3442 { 3443 MachineState *ms = MACHINE(hotplug_dev); 3444 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3445 CPUCore *cc = CPU_CORE(dev); 3446 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3447 3448 if (smc->pre_2_10_has_unused_icps) { 3449 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3450 int i; 3451 3452 for (i = 0; i < cc->nr_threads; i++) { 3453 CPUState *cs = CPU(sc->threads[i]); 3454 3455 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3456 } 3457 } 3458 3459 assert(core_slot); 3460 core_slot->cpu = NULL; 3461 object_unparent(OBJECT(dev)); 3462 } 3463 3464 static 3465 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3466 Error **errp) 3467 { 3468 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3469 int index; 3470 sPAPRDRConnector *drc; 3471 CPUCore *cc = CPU_CORE(dev); 3472 3473 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3474 error_setg(errp, "Unable to find CPU core with core-id: %d", 3475 cc->core_id); 3476 return; 3477 } 3478 if (index == 0) { 3479 error_setg(errp, "Boot CPU core may not be unplugged"); 3480 return; 3481 } 3482 3483 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3484 spapr_vcpu_id(spapr, cc->core_id)); 3485 g_assert(drc); 3486 3487 spapr_drc_detach(drc); 3488 3489 spapr_hotplug_req_remove_by_index(drc); 3490 } 3491 3492 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3493 Error **errp) 3494 { 3495 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3496 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3497 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3498 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3499 CPUCore *cc = CPU_CORE(dev); 3500 CPUState *cs = CPU(core->threads[0]); 3501 sPAPRDRConnector *drc; 3502 Error *local_err = NULL; 3503 CPUArchId *core_slot; 3504 int index; 3505 bool hotplugged = spapr_drc_hotplugged(dev); 3506 3507 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3508 if (!core_slot) { 3509 error_setg(errp, "Unable to find CPU core with core-id: %d", 3510 cc->core_id); 3511 return; 3512 } 3513 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3514 spapr_vcpu_id(spapr, cc->core_id)); 3515 3516 g_assert(drc || !mc->has_hotpluggable_cpus); 3517 3518 if (drc) { 3519 void *fdt; 3520 int fdt_offset; 3521 3522 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 3523 3524 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3525 if (local_err) { 3526 g_free(fdt); 3527 error_propagate(errp, local_err); 3528 return; 3529 } 3530 3531 if (hotplugged) { 3532 /* 3533 * Send hotplug notification interrupt to the guest only 3534 * in case of hotplugged CPUs. 3535 */ 3536 spapr_hotplug_req_add_by_index(drc); 3537 } else { 3538 spapr_drc_reset(drc); 3539 } 3540 } 3541 3542 core_slot->cpu = OBJECT(dev); 3543 3544 if (smc->pre_2_10_has_unused_icps) { 3545 int i; 3546 3547 for (i = 0; i < cc->nr_threads; i++) { 3548 cs = CPU(core->threads[i]); 3549 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3550 } 3551 } 3552 } 3553 3554 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3555 Error **errp) 3556 { 3557 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3558 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3559 Error *local_err = NULL; 3560 CPUCore *cc = CPU_CORE(dev); 3561 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3562 const char *type = object_get_typename(OBJECT(dev)); 3563 CPUArchId *core_slot; 3564 int index; 3565 3566 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3567 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3568 goto out; 3569 } 3570 3571 if (strcmp(base_core_type, type)) { 3572 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3573 goto out; 3574 } 3575 3576 if (cc->core_id % smp_threads) { 3577 error_setg(&local_err, "invalid core id %d", cc->core_id); 3578 goto out; 3579 } 3580 3581 /* 3582 * In general we should have homogeneous threads-per-core, but old 3583 * (pre hotplug support) machine types allow the last core to have 3584 * reduced threads as a compatibility hack for when we allowed 3585 * total vcpus not a multiple of threads-per-core. 3586 */ 3587 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3588 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3589 cc->nr_threads, smp_threads); 3590 goto out; 3591 } 3592 3593 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3594 if (!core_slot) { 3595 error_setg(&local_err, "core id %d out of range", cc->core_id); 3596 goto out; 3597 } 3598 3599 if (core_slot->cpu) { 3600 error_setg(&local_err, "core %d already populated", cc->core_id); 3601 goto out; 3602 } 3603 3604 numa_cpu_pre_plug(core_slot, dev, &local_err); 3605 3606 out: 3607 error_propagate(errp, local_err); 3608 } 3609 3610 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3611 DeviceState *dev, Error **errp) 3612 { 3613 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3614 spapr_memory_plug(hotplug_dev, dev, errp); 3615 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3616 spapr_core_plug(hotplug_dev, dev, errp); 3617 } 3618 } 3619 3620 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 3621 DeviceState *dev, Error **errp) 3622 { 3623 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3624 spapr_memory_unplug(hotplug_dev, dev); 3625 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3626 spapr_core_unplug(hotplug_dev, dev); 3627 } 3628 } 3629 3630 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3631 DeviceState *dev, Error **errp) 3632 { 3633 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3634 MachineClass *mc = MACHINE_GET_CLASS(sms); 3635 3636 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3637 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3638 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3639 } else { 3640 /* NOTE: this means there is a window after guest reset, prior to 3641 * CAS negotiation, where unplug requests will fail due to the 3642 * capability not being detected yet. This is a bit different than 3643 * the case with PCI unplug, where the events will be queued and 3644 * eventually handled by the guest after boot 3645 */ 3646 error_setg(errp, "Memory hot unplug not supported for this guest"); 3647 } 3648 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3649 if (!mc->has_hotpluggable_cpus) { 3650 error_setg(errp, "CPU hot unplug not supported on this machine"); 3651 return; 3652 } 3653 spapr_core_unplug_request(hotplug_dev, dev, errp); 3654 } 3655 } 3656 3657 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3658 DeviceState *dev, Error **errp) 3659 { 3660 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3661 spapr_memory_pre_plug(hotplug_dev, dev, errp); 3662 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3663 spapr_core_pre_plug(hotplug_dev, dev, errp); 3664 } 3665 } 3666 3667 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3668 DeviceState *dev) 3669 { 3670 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3671 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3672 return HOTPLUG_HANDLER(machine); 3673 } 3674 return NULL; 3675 } 3676 3677 static CpuInstanceProperties 3678 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3679 { 3680 CPUArchId *core_slot; 3681 MachineClass *mc = MACHINE_GET_CLASS(machine); 3682 3683 /* make sure possible_cpu are intialized */ 3684 mc->possible_cpu_arch_ids(machine); 3685 /* get CPU core slot containing thread that matches cpu_index */ 3686 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3687 assert(core_slot); 3688 return core_slot->props; 3689 } 3690 3691 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 3692 { 3693 return idx / smp_cores % nb_numa_nodes; 3694 } 3695 3696 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3697 { 3698 int i; 3699 const char *core_type; 3700 int spapr_max_cores = max_cpus / smp_threads; 3701 MachineClass *mc = MACHINE_GET_CLASS(machine); 3702 3703 if (!mc->has_hotpluggable_cpus) { 3704 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3705 } 3706 if (machine->possible_cpus) { 3707 assert(machine->possible_cpus->len == spapr_max_cores); 3708 return machine->possible_cpus; 3709 } 3710 3711 core_type = spapr_get_cpu_core_type(machine->cpu_type); 3712 if (!core_type) { 3713 error_report("Unable to find sPAPR CPU Core definition"); 3714 exit(1); 3715 } 3716 3717 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3718 sizeof(CPUArchId) * spapr_max_cores); 3719 machine->possible_cpus->len = spapr_max_cores; 3720 for (i = 0; i < machine->possible_cpus->len; i++) { 3721 int core_id = i * smp_threads; 3722 3723 machine->possible_cpus->cpus[i].type = core_type; 3724 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3725 machine->possible_cpus->cpus[i].arch_id = core_id; 3726 machine->possible_cpus->cpus[i].props.has_core_id = true; 3727 machine->possible_cpus->cpus[i].props.core_id = core_id; 3728 } 3729 return machine->possible_cpus; 3730 } 3731 3732 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3733 uint64_t *buid, hwaddr *pio, 3734 hwaddr *mmio32, hwaddr *mmio64, 3735 unsigned n_dma, uint32_t *liobns, Error **errp) 3736 { 3737 /* 3738 * New-style PHB window placement. 3739 * 3740 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3741 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3742 * windows. 3743 * 3744 * Some guest kernels can't work with MMIO windows above 1<<46 3745 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3746 * 3747 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3748 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3749 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3750 * 1TiB 64-bit MMIO windows for each PHB. 3751 */ 3752 const uint64_t base_buid = 0x800000020000000ULL; 3753 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3754 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3755 int i; 3756 3757 /* Sanity check natural alignments */ 3758 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3759 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3760 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3761 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3762 /* Sanity check bounds */ 3763 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3764 SPAPR_PCI_MEM32_WIN_SIZE); 3765 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3766 SPAPR_PCI_MEM64_WIN_SIZE); 3767 3768 if (index >= SPAPR_MAX_PHBS) { 3769 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3770 SPAPR_MAX_PHBS - 1); 3771 return; 3772 } 3773 3774 *buid = base_buid + index; 3775 for (i = 0; i < n_dma; ++i) { 3776 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3777 } 3778 3779 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3780 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3781 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3782 } 3783 3784 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3785 { 3786 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3787 3788 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3789 } 3790 3791 static void spapr_ics_resend(XICSFabric *dev) 3792 { 3793 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3794 3795 ics_resend(spapr->ics); 3796 } 3797 3798 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 3799 { 3800 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 3801 3802 return cpu ? ICP(cpu->intc) : NULL; 3803 } 3804 3805 #define ICS_IRQ_FREE(ics, srcno) \ 3806 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) 3807 3808 static int ics_find_free_block(ICSState *ics, int num, int alignnum) 3809 { 3810 int first, i; 3811 3812 for (first = 0; first < ics->nr_irqs; first += alignnum) { 3813 if (num > (ics->nr_irqs - first)) { 3814 return -1; 3815 } 3816 for (i = first; i < first + num; ++i) { 3817 if (!ICS_IRQ_FREE(ics, i)) { 3818 break; 3819 } 3820 } 3821 if (i == (first + num)) { 3822 return first; 3823 } 3824 } 3825 3826 return -1; 3827 } 3828 3829 int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align, Error **errp) 3830 { 3831 ICSState *ics = spapr->ics; 3832 int first = -1; 3833 3834 assert(ics); 3835 3836 /* 3837 * MSIMesage::data is used for storing VIRQ so 3838 * it has to be aligned to num to support multiple 3839 * MSI vectors. MSI-X is not affected by this. 3840 * The hint is used for the first IRQ, the rest should 3841 * be allocated continuously. 3842 */ 3843 if (align) { 3844 assert((num == 1) || (num == 2) || (num == 4) || 3845 (num == 8) || (num == 16) || (num == 32)); 3846 first = ics_find_free_block(ics, num, num); 3847 } else { 3848 first = ics_find_free_block(ics, num, 1); 3849 } 3850 3851 if (first < 0) { 3852 error_setg(errp, "can't find a free %d-IRQ block", num); 3853 return -1; 3854 } 3855 3856 return first + ics->offset; 3857 } 3858 3859 int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp) 3860 { 3861 ICSState *ics = spapr->ics; 3862 3863 assert(ics); 3864 3865 if (!ics_valid_irq(ics, irq)) { 3866 error_setg(errp, "IRQ %d is invalid", irq); 3867 return -1; 3868 } 3869 3870 if (!ICS_IRQ_FREE(ics, irq - ics->offset)) { 3871 error_setg(errp, "IRQ %d is not free", irq); 3872 return -1; 3873 } 3874 3875 ics_set_irq_type(ics, irq - ics->offset, lsi); 3876 return 0; 3877 } 3878 3879 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num) 3880 { 3881 ICSState *ics = spapr->ics; 3882 int srcno = irq - ics->offset; 3883 int i; 3884 3885 if (ics_valid_irq(ics, irq)) { 3886 trace_spapr_irq_free(0, irq, num); 3887 for (i = srcno; i < srcno + num; ++i) { 3888 if (ICS_IRQ_FREE(ics, i)) { 3889 trace_spapr_irq_free_warn(0, i + ics->offset); 3890 } 3891 memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); 3892 } 3893 } 3894 } 3895 3896 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq) 3897 { 3898 ICSState *ics = spapr->ics; 3899 3900 if (ics_valid_irq(ics, irq)) { 3901 return ics->qirqs[irq - ics->offset]; 3902 } 3903 3904 return NULL; 3905 } 3906 3907 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3908 Monitor *mon) 3909 { 3910 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3911 CPUState *cs; 3912 3913 CPU_FOREACH(cs) { 3914 PowerPCCPU *cpu = POWERPC_CPU(cs); 3915 3916 icp_pic_print_info(ICP(cpu->intc), mon); 3917 } 3918 3919 ics_pic_print_info(spapr->ics, mon); 3920 } 3921 3922 int spapr_get_vcpu_id(PowerPCCPU *cpu) 3923 { 3924 return cpu->vcpu_id; 3925 } 3926 3927 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 3928 { 3929 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3930 int vcpu_id; 3931 3932 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 3933 3934 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 3935 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 3936 error_append_hint(errp, "Adjust the number of cpus to %d " 3937 "or try to raise the number of threads per core\n", 3938 vcpu_id * smp_threads / spapr->vsmt); 3939 return; 3940 } 3941 3942 cpu->vcpu_id = vcpu_id; 3943 } 3944 3945 PowerPCCPU *spapr_find_cpu(int vcpu_id) 3946 { 3947 CPUState *cs; 3948 3949 CPU_FOREACH(cs) { 3950 PowerPCCPU *cpu = POWERPC_CPU(cs); 3951 3952 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 3953 return cpu; 3954 } 3955 } 3956 3957 return NULL; 3958 } 3959 3960 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3961 { 3962 MachineClass *mc = MACHINE_CLASS(oc); 3963 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3964 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3965 NMIClass *nc = NMI_CLASS(oc); 3966 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3967 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3968 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3969 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3970 3971 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3972 mc->ignore_boot_device_suffixes = true; 3973 3974 /* 3975 * We set up the default / latest behaviour here. The class_init 3976 * functions for the specific versioned machine types can override 3977 * these details for backwards compatibility 3978 */ 3979 mc->init = spapr_machine_init; 3980 mc->reset = spapr_machine_reset; 3981 mc->block_default_type = IF_SCSI; 3982 mc->max_cpus = 1024; 3983 mc->no_parallel = 1; 3984 mc->default_boot_order = ""; 3985 mc->default_ram_size = 512 * MiB; 3986 mc->default_display = "std"; 3987 mc->kvm_type = spapr_kvm_type; 3988 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 3989 mc->pci_allow_0_address = true; 3990 assert(!mc->get_hotplug_handler); 3991 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3992 hc->pre_plug = spapr_machine_device_pre_plug; 3993 hc->plug = spapr_machine_device_plug; 3994 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 3995 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 3996 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3997 hc->unplug_request = spapr_machine_device_unplug_request; 3998 hc->unplug = spapr_machine_device_unplug; 3999 4000 smc->dr_lmb_enabled = true; 4001 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4002 mc->has_hotpluggable_cpus = true; 4003 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4004 fwc->get_dev_path = spapr_get_fw_dev_path; 4005 nc->nmi_monitor_handler = spapr_nmi; 4006 smc->phb_placement = spapr_phb_placement; 4007 vhc->hypercall = emulate_spapr_hypercall; 4008 vhc->hpt_mask = spapr_hpt_mask; 4009 vhc->map_hptes = spapr_map_hptes; 4010 vhc->unmap_hptes = spapr_unmap_hptes; 4011 vhc->store_hpte = spapr_store_hpte; 4012 vhc->get_patbe = spapr_get_patbe; 4013 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4014 xic->ics_get = spapr_ics_get; 4015 xic->ics_resend = spapr_ics_resend; 4016 xic->icp_get = spapr_icp_get; 4017 ispc->print_info = spapr_pic_print_info; 4018 /* Force NUMA node memory size to be a multiple of 4019 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4020 * in which LMBs are represented and hot-added 4021 */ 4022 mc->numa_mem_align_shift = 28; 4023 4024 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4025 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4026 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4027 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4028 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4029 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4030 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4031 spapr_caps_add_properties(smc, &error_abort); 4032 } 4033 4034 static const TypeInfo spapr_machine_info = { 4035 .name = TYPE_SPAPR_MACHINE, 4036 .parent = TYPE_MACHINE, 4037 .abstract = true, 4038 .instance_size = sizeof(sPAPRMachineState), 4039 .instance_init = spapr_instance_init, 4040 .instance_finalize = spapr_machine_finalizefn, 4041 .class_size = sizeof(sPAPRMachineClass), 4042 .class_init = spapr_machine_class_init, 4043 .interfaces = (InterfaceInfo[]) { 4044 { TYPE_FW_PATH_PROVIDER }, 4045 { TYPE_NMI }, 4046 { TYPE_HOTPLUG_HANDLER }, 4047 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4048 { TYPE_XICS_FABRIC }, 4049 { TYPE_INTERRUPT_STATS_PROVIDER }, 4050 { } 4051 }, 4052 }; 4053 4054 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4055 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4056 void *data) \ 4057 { \ 4058 MachineClass *mc = MACHINE_CLASS(oc); \ 4059 spapr_machine_##suffix##_class_options(mc); \ 4060 if (latest) { \ 4061 mc->alias = "pseries"; \ 4062 mc->is_default = 1; \ 4063 } \ 4064 } \ 4065 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 4066 { \ 4067 MachineState *machine = MACHINE(obj); \ 4068 spapr_machine_##suffix##_instance_options(machine); \ 4069 } \ 4070 static const TypeInfo spapr_machine_##suffix##_info = { \ 4071 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4072 .parent = TYPE_SPAPR_MACHINE, \ 4073 .class_init = spapr_machine_##suffix##_class_init, \ 4074 .instance_init = spapr_machine_##suffix##_instance_init, \ 4075 }; \ 4076 static void spapr_machine_register_##suffix(void) \ 4077 { \ 4078 type_register(&spapr_machine_##suffix##_info); \ 4079 } \ 4080 type_init(spapr_machine_register_##suffix) 4081 4082 /* 4083 * pseries-3.0 4084 */ 4085 static void spapr_machine_3_0_instance_options(MachineState *machine) 4086 { 4087 } 4088 4089 static void spapr_machine_3_0_class_options(MachineClass *mc) 4090 { 4091 /* Defaults for the latest behaviour inherited from the base class */ 4092 } 4093 4094 DEFINE_SPAPR_MACHINE(3_0, "3.0", true); 4095 4096 /* 4097 * pseries-2.12 4098 */ 4099 #define SPAPR_COMPAT_2_12 \ 4100 HW_COMPAT_2_12 \ 4101 { \ 4102 .driver = TYPE_POWERPC_CPU, \ 4103 .property = "pre-3.0-migration", \ 4104 .value = "on", \ 4105 }, \ 4106 { \ 4107 .driver = TYPE_SPAPR_CPU_CORE, \ 4108 .property = "pre-3.0-migration", \ 4109 .value = "on", \ 4110 }, 4111 4112 static void spapr_machine_2_12_instance_options(MachineState *machine) 4113 { 4114 spapr_machine_3_0_instance_options(machine); 4115 } 4116 4117 static void spapr_machine_2_12_class_options(MachineClass *mc) 4118 { 4119 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4120 4121 spapr_machine_3_0_class_options(mc); 4122 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_12); 4123 4124 /* We depend on kvm_enabled() to choose a default value for the 4125 * hpt-max-page-size capability. Of course we can't do it here 4126 * because this is too early and the HW accelerator isn't initialzed 4127 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4128 */ 4129 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4130 } 4131 4132 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4133 4134 static void spapr_machine_2_12_sxxm_instance_options(MachineState *machine) 4135 { 4136 spapr_machine_2_12_instance_options(machine); 4137 } 4138 4139 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4140 { 4141 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4142 4143 spapr_machine_2_12_class_options(mc); 4144 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4145 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4146 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4147 } 4148 4149 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4150 4151 /* 4152 * pseries-2.11 4153 */ 4154 #define SPAPR_COMPAT_2_11 \ 4155 HW_COMPAT_2_11 4156 4157 static void spapr_machine_2_11_instance_options(MachineState *machine) 4158 { 4159 spapr_machine_2_12_instance_options(machine); 4160 } 4161 4162 static void spapr_machine_2_11_class_options(MachineClass *mc) 4163 { 4164 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4165 4166 spapr_machine_2_12_class_options(mc); 4167 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4168 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11); 4169 } 4170 4171 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4172 4173 /* 4174 * pseries-2.10 4175 */ 4176 #define SPAPR_COMPAT_2_10 \ 4177 HW_COMPAT_2_10 4178 4179 static void spapr_machine_2_10_instance_options(MachineState *machine) 4180 { 4181 spapr_machine_2_11_instance_options(machine); 4182 } 4183 4184 static void spapr_machine_2_10_class_options(MachineClass *mc) 4185 { 4186 spapr_machine_2_11_class_options(mc); 4187 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10); 4188 } 4189 4190 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4191 4192 /* 4193 * pseries-2.9 4194 */ 4195 #define SPAPR_COMPAT_2_9 \ 4196 HW_COMPAT_2_9 \ 4197 { \ 4198 .driver = TYPE_POWERPC_CPU, \ 4199 .property = "pre-2.10-migration", \ 4200 .value = "on", \ 4201 }, \ 4202 4203 static void spapr_machine_2_9_instance_options(MachineState *machine) 4204 { 4205 spapr_machine_2_10_instance_options(machine); 4206 } 4207 4208 static void spapr_machine_2_9_class_options(MachineClass *mc) 4209 { 4210 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4211 4212 spapr_machine_2_10_class_options(mc); 4213 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); 4214 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4215 smc->pre_2_10_has_unused_icps = true; 4216 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4217 } 4218 4219 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4220 4221 /* 4222 * pseries-2.8 4223 */ 4224 #define SPAPR_COMPAT_2_8 \ 4225 HW_COMPAT_2_8 \ 4226 { \ 4227 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4228 .property = "pcie-extended-configuration-space", \ 4229 .value = "off", \ 4230 }, 4231 4232 static void spapr_machine_2_8_instance_options(MachineState *machine) 4233 { 4234 spapr_machine_2_9_instance_options(machine); 4235 } 4236 4237 static void spapr_machine_2_8_class_options(MachineClass *mc) 4238 { 4239 spapr_machine_2_9_class_options(mc); 4240 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 4241 mc->numa_mem_align_shift = 23; 4242 } 4243 4244 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4245 4246 /* 4247 * pseries-2.7 4248 */ 4249 #define SPAPR_COMPAT_2_7 \ 4250 HW_COMPAT_2_7 \ 4251 { \ 4252 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4253 .property = "mem_win_size", \ 4254 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 4255 }, \ 4256 { \ 4257 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4258 .property = "mem64_win_size", \ 4259 .value = "0", \ 4260 }, \ 4261 { \ 4262 .driver = TYPE_POWERPC_CPU, \ 4263 .property = "pre-2.8-migration", \ 4264 .value = "on", \ 4265 }, \ 4266 { \ 4267 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4268 .property = "pre-2.8-migration", \ 4269 .value = "on", \ 4270 }, 4271 4272 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 4273 uint64_t *buid, hwaddr *pio, 4274 hwaddr *mmio32, hwaddr *mmio64, 4275 unsigned n_dma, uint32_t *liobns, Error **errp) 4276 { 4277 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4278 const uint64_t base_buid = 0x800000020000000ULL; 4279 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4280 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4281 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4282 const uint32_t max_index = 255; 4283 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4284 4285 uint64_t ram_top = MACHINE(spapr)->ram_size; 4286 hwaddr phb0_base, phb_base; 4287 int i; 4288 4289 /* Do we have device memory? */ 4290 if (MACHINE(spapr)->maxram_size > ram_top) { 4291 /* Can't just use maxram_size, because there may be an 4292 * alignment gap between normal and device memory regions 4293 */ 4294 ram_top = MACHINE(spapr)->device_memory->base + 4295 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4296 } 4297 4298 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4299 4300 if (index > max_index) { 4301 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4302 max_index); 4303 return; 4304 } 4305 4306 *buid = base_buid + index; 4307 for (i = 0; i < n_dma; ++i) { 4308 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4309 } 4310 4311 phb_base = phb0_base + index * phb_spacing; 4312 *pio = phb_base + pio_offset; 4313 *mmio32 = phb_base + mmio_offset; 4314 /* 4315 * We don't set the 64-bit MMIO window, relying on the PHB's 4316 * fallback behaviour of automatically splitting a large "32-bit" 4317 * window into contiguous 32-bit and 64-bit windows 4318 */ 4319 } 4320 4321 static void spapr_machine_2_7_instance_options(MachineState *machine) 4322 { 4323 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 4324 4325 spapr_machine_2_8_instance_options(machine); 4326 spapr->use_hotplug_event_source = false; 4327 } 4328 4329 static void spapr_machine_2_7_class_options(MachineClass *mc) 4330 { 4331 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4332 4333 spapr_machine_2_8_class_options(mc); 4334 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4335 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 4336 smc->phb_placement = phb_placement_2_7; 4337 } 4338 4339 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4340 4341 /* 4342 * pseries-2.6 4343 */ 4344 #define SPAPR_COMPAT_2_6 \ 4345 HW_COMPAT_2_6 \ 4346 { \ 4347 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 4348 .property = "ddw",\ 4349 .value = stringify(off),\ 4350 }, 4351 4352 static void spapr_machine_2_6_instance_options(MachineState *machine) 4353 { 4354 spapr_machine_2_7_instance_options(machine); 4355 } 4356 4357 static void spapr_machine_2_6_class_options(MachineClass *mc) 4358 { 4359 spapr_machine_2_7_class_options(mc); 4360 mc->has_hotpluggable_cpus = false; 4361 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 4362 } 4363 4364 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4365 4366 /* 4367 * pseries-2.5 4368 */ 4369 #define SPAPR_COMPAT_2_5 \ 4370 HW_COMPAT_2_5 \ 4371 { \ 4372 .driver = "spapr-vlan", \ 4373 .property = "use-rx-buffer-pools", \ 4374 .value = "off", \ 4375 }, 4376 4377 static void spapr_machine_2_5_instance_options(MachineState *machine) 4378 { 4379 spapr_machine_2_6_instance_options(machine); 4380 } 4381 4382 static void spapr_machine_2_5_class_options(MachineClass *mc) 4383 { 4384 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4385 4386 spapr_machine_2_6_class_options(mc); 4387 smc->use_ohci_by_default = true; 4388 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 4389 } 4390 4391 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4392 4393 /* 4394 * pseries-2.4 4395 */ 4396 #define SPAPR_COMPAT_2_4 \ 4397 HW_COMPAT_2_4 4398 4399 static void spapr_machine_2_4_instance_options(MachineState *machine) 4400 { 4401 spapr_machine_2_5_instance_options(machine); 4402 } 4403 4404 static void spapr_machine_2_4_class_options(MachineClass *mc) 4405 { 4406 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4407 4408 spapr_machine_2_5_class_options(mc); 4409 smc->dr_lmb_enabled = false; 4410 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 4411 } 4412 4413 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4414 4415 /* 4416 * pseries-2.3 4417 */ 4418 #define SPAPR_COMPAT_2_3 \ 4419 HW_COMPAT_2_3 \ 4420 {\ 4421 .driver = "spapr-pci-host-bridge",\ 4422 .property = "dynamic-reconfiguration",\ 4423 .value = "off",\ 4424 }, 4425 4426 static void spapr_machine_2_3_instance_options(MachineState *machine) 4427 { 4428 spapr_machine_2_4_instance_options(machine); 4429 } 4430 4431 static void spapr_machine_2_3_class_options(MachineClass *mc) 4432 { 4433 spapr_machine_2_4_class_options(mc); 4434 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 4435 } 4436 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4437 4438 /* 4439 * pseries-2.2 4440 */ 4441 4442 #define SPAPR_COMPAT_2_2 \ 4443 HW_COMPAT_2_2 \ 4444 {\ 4445 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 4446 .property = "mem_win_size",\ 4447 .value = "0x20000000",\ 4448 }, 4449 4450 static void spapr_machine_2_2_instance_options(MachineState *machine) 4451 { 4452 spapr_machine_2_3_instance_options(machine); 4453 machine->suppress_vmdesc = true; 4454 } 4455 4456 static void spapr_machine_2_2_class_options(MachineClass *mc) 4457 { 4458 spapr_machine_2_3_class_options(mc); 4459 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 4460 } 4461 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4462 4463 /* 4464 * pseries-2.1 4465 */ 4466 #define SPAPR_COMPAT_2_1 \ 4467 HW_COMPAT_2_1 4468 4469 static void spapr_machine_2_1_instance_options(MachineState *machine) 4470 { 4471 spapr_machine_2_2_instance_options(machine); 4472 } 4473 4474 static void spapr_machine_2_1_class_options(MachineClass *mc) 4475 { 4476 spapr_machine_2_2_class_options(mc); 4477 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 4478 } 4479 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4480 4481 static void spapr_machine_register_types(void) 4482 { 4483 type_register_static(&spapr_machine_info); 4484 } 4485 4486 type_init(spapr_machine_register_types) 4487