1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/datadir.h" 29 #include "qemu/memalign.h" 30 #include "qemu/guest-random.h" 31 #include "qapi/error.h" 32 #include "qapi/qapi-events-machine.h" 33 #include "qapi/qapi-events-qdev.h" 34 #include "qapi/visitor.h" 35 #include "sysemu/sysemu.h" 36 #include "sysemu/hostmem.h" 37 #include "sysemu/numa.h" 38 #include "sysemu/qtest.h" 39 #include "sysemu/reset.h" 40 #include "sysemu/runstate.h" 41 #include "qemu/log.h" 42 #include "hw/fw-path-provider.h" 43 #include "elf.h" 44 #include "net/net.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/cpus.h" 47 #include "sysemu/hw_accel.h" 48 #include "kvm_ppc.h" 49 #include "migration/misc.h" 50 #include "migration/qemu-file-types.h" 51 #include "migration/global_state.h" 52 #include "migration/register.h" 53 #include "migration/blocker.h" 54 #include "mmu-hash64.h" 55 #include "mmu-book3s-v3.h" 56 #include "cpu-models.h" 57 #include "hw/core/cpu.h" 58 59 #include "hw/ppc/ppc.h" 60 #include "hw/loader.h" 61 62 #include "hw/ppc/fdt.h" 63 #include "hw/ppc/spapr.h" 64 #include "hw/ppc/spapr_nested.h" 65 #include "hw/ppc/spapr_vio.h" 66 #include "hw/ppc/vof.h" 67 #include "hw/qdev-properties.h" 68 #include "hw/pci-host/spapr.h" 69 #include "hw/pci/msi.h" 70 71 #include "hw/pci/pci.h" 72 #include "hw/scsi/scsi.h" 73 #include "hw/virtio/virtio-scsi.h" 74 #include "hw/virtio/vhost-scsi-common.h" 75 76 #include "exec/ram_addr.h" 77 #include "hw/usb.h" 78 #include "qemu/config-file.h" 79 #include "qemu/error-report.h" 80 #include "trace.h" 81 #include "hw/nmi.h" 82 #include "hw/intc/intc.h" 83 84 #include "hw/ppc/spapr_cpu_core.h" 85 #include "hw/mem/memory-device.h" 86 #include "hw/ppc/spapr_tpm_proxy.h" 87 #include "hw/ppc/spapr_nvdimm.h" 88 #include "hw/ppc/spapr_numa.h" 89 #include "hw/ppc/pef.h" 90 91 #include "monitor/monitor.h" 92 93 #include <libfdt.h> 94 95 /* SLOF memory layout: 96 * 97 * SLOF raw image loaded at 0, copies its romfs right below the flat 98 * device-tree, then position SLOF itself 31M below that 99 * 100 * So we set FW_OVERHEAD to 40MB which should account for all of that 101 * and more 102 * 103 * We load our kernel at 4M, leaving space for SLOF initial image 104 */ 105 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */ 106 #define FW_MAX_SIZE 0x400000 107 #define FW_FILE_NAME "slof.bin" 108 #define FW_FILE_NAME_VOF "vof.bin" 109 #define FW_OVERHEAD 0x2800000 110 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 111 112 #define MIN_RMA_SLOF (128 * MiB) 113 114 #define PHANDLE_INTC 0x00001111 115 116 /* These two functions implement the VCPU id numbering: one to compute them 117 * all and one to identify thread 0 of a VCORE. Any change to the first one 118 * is likely to have an impact on the second one, so let's keep them close. 119 */ 120 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 121 { 122 MachineState *ms = MACHINE(spapr); 123 unsigned int smp_threads = ms->smp.threads; 124 125 assert(spapr->vsmt); 126 return 127 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 128 } 129 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 130 PowerPCCPU *cpu) 131 { 132 assert(spapr->vsmt); 133 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 134 } 135 136 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 137 { 138 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 139 * and newer QEMUs don't even have them. In both cases, we don't want 140 * to send anything on the wire. 141 */ 142 return false; 143 } 144 145 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 146 .name = "icp/server", 147 .version_id = 1, 148 .minimum_version_id = 1, 149 .needed = pre_2_10_vmstate_dummy_icp_needed, 150 .fields = (VMStateField[]) { 151 VMSTATE_UNUSED(4), /* uint32_t xirr */ 152 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 153 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 154 VMSTATE_END_OF_LIST() 155 }, 156 }; 157 158 static void pre_2_10_vmstate_register_dummy_icp(int i) 159 { 160 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 161 (void *)(uintptr_t) i); 162 } 163 164 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 165 { 166 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 167 (void *)(uintptr_t) i); 168 } 169 170 int spapr_max_server_number(SpaprMachineState *spapr) 171 { 172 MachineState *ms = MACHINE(spapr); 173 174 assert(spapr->vsmt); 175 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 176 } 177 178 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 179 int smt_threads) 180 { 181 int i, ret = 0; 182 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 183 g_autofree uint32_t *gservers_prop = g_new(uint32_t, smt_threads * 2); 184 int index = spapr_get_vcpu_id(cpu); 185 186 if (cpu->compat_pvr) { 187 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 188 if (ret < 0) { 189 return ret; 190 } 191 } 192 193 /* Build interrupt servers and gservers properties */ 194 for (i = 0; i < smt_threads; i++) { 195 servers_prop[i] = cpu_to_be32(index + i); 196 /* Hack, direct the group queues back to cpu 0 */ 197 gservers_prop[i*2] = cpu_to_be32(index + i); 198 gservers_prop[i*2 + 1] = 0; 199 } 200 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 201 servers_prop, sizeof(*servers_prop) * smt_threads); 202 if (ret < 0) { 203 return ret; 204 } 205 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 206 gservers_prop, sizeof(*gservers_prop) * smt_threads * 2); 207 208 return ret; 209 } 210 211 static void spapr_dt_pa_features(SpaprMachineState *spapr, 212 PowerPCCPU *cpu, 213 void *fdt, int offset) 214 { 215 uint8_t pa_features_206[] = { 6, 0, 216 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 217 uint8_t pa_features_207[] = { 24, 0, 218 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 219 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 220 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 221 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 222 uint8_t pa_features_300[] = { 66, 0, 223 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 224 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 225 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 226 /* 6: DS207 */ 227 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 228 /* 16: Vector */ 229 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 230 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 231 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 232 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 233 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 234 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 235 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 236 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 238 /* 42: PM, 44: PC RA, 46: SC vec'd */ 239 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 240 /* 48: SIMD, 50: QP BFP, 52: String */ 241 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 242 /* 54: DecFP, 56: DecI, 58: SHA */ 243 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 244 /* 60: NM atomic, 62: RNG */ 245 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 246 }; 247 uint8_t *pa_features = NULL; 248 size_t pa_size; 249 250 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 251 pa_features = pa_features_206; 252 pa_size = sizeof(pa_features_206); 253 } 254 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 255 pa_features = pa_features_207; 256 pa_size = sizeof(pa_features_207); 257 } 258 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 259 pa_features = pa_features_300; 260 pa_size = sizeof(pa_features_300); 261 } 262 if (!pa_features) { 263 return; 264 } 265 266 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 267 /* 268 * Note: we keep CI large pages off by default because a 64K capable 269 * guest provisioned with large pages might otherwise try to map a qemu 270 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 271 * even if that qemu runs on a 4k host. 272 * We dd this bit back here if we are confident this is not an issue 273 */ 274 pa_features[3] |= 0x20; 275 } 276 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 277 pa_features[24] |= 0x80; /* Transactional memory support */ 278 } 279 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 280 /* Workaround for broken kernels that attempt (guest) radix 281 * mode when they can't handle it, if they see the radix bit set 282 * in pa-features. So hide it from them. */ 283 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 284 } 285 286 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 287 } 288 289 static hwaddr spapr_node0_size(MachineState *machine) 290 { 291 if (machine->numa_state->num_nodes) { 292 int i; 293 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 294 if (machine->numa_state->nodes[i].node_mem) { 295 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 296 machine->ram_size); 297 } 298 } 299 } 300 return machine->ram_size; 301 } 302 303 static void add_str(GString *s, const gchar *s1) 304 { 305 g_string_append_len(s, s1, strlen(s1) + 1); 306 } 307 308 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 309 hwaddr start, hwaddr size) 310 { 311 char mem_name[32]; 312 uint64_t mem_reg_property[2]; 313 int off; 314 315 mem_reg_property[0] = cpu_to_be64(start); 316 mem_reg_property[1] = cpu_to_be64(size); 317 318 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 319 off = fdt_add_subnode(fdt, 0, mem_name); 320 _FDT(off); 321 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 322 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 323 sizeof(mem_reg_property)))); 324 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 325 return off; 326 } 327 328 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 329 { 330 MemoryDeviceInfoList *info; 331 332 for (info = list; info; info = info->next) { 333 MemoryDeviceInfo *value = info->value; 334 335 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 336 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 337 338 if (addr >= pcdimm_info->addr && 339 addr < (pcdimm_info->addr + pcdimm_info->size)) { 340 return pcdimm_info->node; 341 } 342 } 343 } 344 345 return -1; 346 } 347 348 struct sPAPRDrconfCellV2 { 349 uint32_t seq_lmbs; 350 uint64_t base_addr; 351 uint32_t drc_index; 352 uint32_t aa_index; 353 uint32_t flags; 354 } QEMU_PACKED; 355 356 typedef struct DrconfCellQueue { 357 struct sPAPRDrconfCellV2 cell; 358 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 359 } DrconfCellQueue; 360 361 static DrconfCellQueue * 362 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 363 uint32_t drc_index, uint32_t aa_index, 364 uint32_t flags) 365 { 366 DrconfCellQueue *elem; 367 368 elem = g_malloc0(sizeof(*elem)); 369 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 370 elem->cell.base_addr = cpu_to_be64(base_addr); 371 elem->cell.drc_index = cpu_to_be32(drc_index); 372 elem->cell.aa_index = cpu_to_be32(aa_index); 373 elem->cell.flags = cpu_to_be32(flags); 374 375 return elem; 376 } 377 378 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 379 int offset, MemoryDeviceInfoList *dimms) 380 { 381 MachineState *machine = MACHINE(spapr); 382 uint8_t *int_buf, *cur_index; 383 int ret; 384 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 385 uint64_t addr, cur_addr, size; 386 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 387 uint64_t mem_end = machine->device_memory->base + 388 memory_region_size(&machine->device_memory->mr); 389 uint32_t node, buf_len, nr_entries = 0; 390 SpaprDrc *drc; 391 DrconfCellQueue *elem, *next; 392 MemoryDeviceInfoList *info; 393 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 394 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 395 396 /* Entry to cover RAM and the gap area */ 397 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 398 SPAPR_LMB_FLAGS_RESERVED | 399 SPAPR_LMB_FLAGS_DRC_INVALID); 400 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 401 nr_entries++; 402 403 cur_addr = machine->device_memory->base; 404 for (info = dimms; info; info = info->next) { 405 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 406 407 addr = di->addr; 408 size = di->size; 409 node = di->node; 410 411 /* 412 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 413 * area is marked hotpluggable in the next iteration for the bigger 414 * chunk including the NVDIMM occupied area. 415 */ 416 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 417 continue; 418 419 /* Entry for hot-pluggable area */ 420 if (cur_addr < addr) { 421 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 422 g_assert(drc); 423 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 424 cur_addr, spapr_drc_index(drc), -1, 0); 425 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 426 nr_entries++; 427 } 428 429 /* Entry for DIMM */ 430 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 431 g_assert(drc); 432 elem = spapr_get_drconf_cell(size / lmb_size, addr, 433 spapr_drc_index(drc), node, 434 (SPAPR_LMB_FLAGS_ASSIGNED | 435 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 436 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 437 nr_entries++; 438 cur_addr = addr + size; 439 } 440 441 /* Entry for remaining hotpluggable area */ 442 if (cur_addr < mem_end) { 443 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 444 g_assert(drc); 445 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 446 cur_addr, spapr_drc_index(drc), -1, 0); 447 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 448 nr_entries++; 449 } 450 451 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 452 int_buf = cur_index = g_malloc0(buf_len); 453 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 454 cur_index += sizeof(nr_entries); 455 456 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 457 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 458 cur_index += sizeof(elem->cell); 459 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 460 g_free(elem); 461 } 462 463 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 464 g_free(int_buf); 465 if (ret < 0) { 466 return -1; 467 } 468 return 0; 469 } 470 471 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 472 int offset, MemoryDeviceInfoList *dimms) 473 { 474 MachineState *machine = MACHINE(spapr); 475 int i, ret; 476 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 477 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 478 uint32_t nr_lmbs = (machine->device_memory->base + 479 memory_region_size(&machine->device_memory->mr)) / 480 lmb_size; 481 uint32_t *int_buf, *cur_index, buf_len; 482 483 /* 484 * Allocate enough buffer size to fit in ibm,dynamic-memory 485 */ 486 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 487 cur_index = int_buf = g_malloc0(buf_len); 488 int_buf[0] = cpu_to_be32(nr_lmbs); 489 cur_index++; 490 for (i = 0; i < nr_lmbs; i++) { 491 uint64_t addr = i * lmb_size; 492 uint32_t *dynamic_memory = cur_index; 493 494 if (i >= device_lmb_start) { 495 SpaprDrc *drc; 496 497 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 498 g_assert(drc); 499 500 dynamic_memory[0] = cpu_to_be32(addr >> 32); 501 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 502 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 503 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 504 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 505 if (memory_region_present(get_system_memory(), addr)) { 506 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 507 } else { 508 dynamic_memory[5] = cpu_to_be32(0); 509 } 510 } else { 511 /* 512 * LMB information for RMA, boot time RAM and gap b/n RAM and 513 * device memory region -- all these are marked as reserved 514 * and as having no valid DRC. 515 */ 516 dynamic_memory[0] = cpu_to_be32(addr >> 32); 517 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 518 dynamic_memory[2] = cpu_to_be32(0); 519 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 520 dynamic_memory[4] = cpu_to_be32(-1); 521 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 522 SPAPR_LMB_FLAGS_DRC_INVALID); 523 } 524 525 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 526 } 527 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 528 g_free(int_buf); 529 if (ret < 0) { 530 return -1; 531 } 532 return 0; 533 } 534 535 /* 536 * Adds ibm,dynamic-reconfiguration-memory node. 537 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 538 * of this device tree node. 539 */ 540 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 541 void *fdt) 542 { 543 MachineState *machine = MACHINE(spapr); 544 int ret, offset; 545 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 546 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 547 cpu_to_be32(lmb_size & 0xffffffff)}; 548 MemoryDeviceInfoList *dimms = NULL; 549 550 /* Don't create the node if there is no device memory. */ 551 if (!machine->device_memory) { 552 return 0; 553 } 554 555 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 556 557 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 558 sizeof(prop_lmb_size)); 559 if (ret < 0) { 560 return ret; 561 } 562 563 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 564 if (ret < 0) { 565 return ret; 566 } 567 568 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 569 if (ret < 0) { 570 return ret; 571 } 572 573 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 574 dimms = qmp_memory_device_list(); 575 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 576 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 577 } else { 578 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 579 } 580 qapi_free_MemoryDeviceInfoList(dimms); 581 582 if (ret < 0) { 583 return ret; 584 } 585 586 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 587 588 return ret; 589 } 590 591 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 592 { 593 MachineState *machine = MACHINE(spapr); 594 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 595 hwaddr mem_start, node_size; 596 int i, nb_nodes = machine->numa_state->num_nodes; 597 NodeInfo *nodes = machine->numa_state->nodes; 598 599 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 600 if (!nodes[i].node_mem) { 601 continue; 602 } 603 if (mem_start >= machine->ram_size) { 604 node_size = 0; 605 } else { 606 node_size = nodes[i].node_mem; 607 if (node_size > machine->ram_size - mem_start) { 608 node_size = machine->ram_size - mem_start; 609 } 610 } 611 if (!mem_start) { 612 /* spapr_machine_init() checks for rma_size <= node0_size 613 * already */ 614 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 615 mem_start += spapr->rma_size; 616 node_size -= spapr->rma_size; 617 } 618 for ( ; node_size; ) { 619 hwaddr sizetmp = pow2floor(node_size); 620 621 /* mem_start != 0 here */ 622 if (ctzl(mem_start) < ctzl(sizetmp)) { 623 sizetmp = 1ULL << ctzl(mem_start); 624 } 625 626 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 627 node_size -= sizetmp; 628 mem_start += sizetmp; 629 } 630 } 631 632 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 633 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 634 int ret; 635 636 g_assert(smc->dr_lmb_enabled); 637 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 638 if (ret) { 639 return ret; 640 } 641 } 642 643 return 0; 644 } 645 646 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 647 SpaprMachineState *spapr) 648 { 649 MachineState *ms = MACHINE(spapr); 650 PowerPCCPU *cpu = POWERPC_CPU(cs); 651 CPUPPCState *env = &cpu->env; 652 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 653 int index = spapr_get_vcpu_id(cpu); 654 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 655 0xffffffff, 0xffffffff}; 656 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 657 : SPAPR_TIMEBASE_FREQ; 658 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 659 uint32_t page_sizes_prop[64]; 660 size_t page_sizes_prop_size; 661 unsigned int smp_threads = ms->smp.threads; 662 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 663 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 664 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 665 SpaprDrc *drc; 666 int drc_index; 667 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 668 int i; 669 670 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 671 if (drc) { 672 drc_index = spapr_drc_index(drc); 673 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 674 } 675 676 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 677 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 678 679 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 680 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 681 env->dcache_line_size))); 682 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 683 env->dcache_line_size))); 684 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 685 env->icache_line_size))); 686 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 687 env->icache_line_size))); 688 689 if (pcc->l1_dcache_size) { 690 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 691 pcc->l1_dcache_size))); 692 } else { 693 warn_report("Unknown L1 dcache size for cpu"); 694 } 695 if (pcc->l1_icache_size) { 696 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 697 pcc->l1_icache_size))); 698 } else { 699 warn_report("Unknown L1 icache size for cpu"); 700 } 701 702 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 703 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 704 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 705 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 706 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 707 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 708 709 if (ppc_has_spr(cpu, SPR_PURR)) { 710 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 711 } 712 if (ppc_has_spr(cpu, SPR_PURR)) { 713 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 714 } 715 716 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 717 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 718 segs, sizeof(segs)))); 719 } 720 721 /* Advertise VSX (vector extensions) if available 722 * 1 == VMX / Altivec available 723 * 2 == VSX available 724 * 725 * Only CPUs for which we create core types in spapr_cpu_core.c 726 * are possible, and all of those have VMX */ 727 if (env->insns_flags & PPC_ALTIVEC) { 728 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 729 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 730 } else { 731 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 732 } 733 } 734 735 /* Advertise DFP (Decimal Floating Point) if available 736 * 0 / no property == no DFP 737 * 1 == DFP available */ 738 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 739 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 740 } 741 742 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 743 sizeof(page_sizes_prop)); 744 if (page_sizes_prop_size) { 745 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 746 page_sizes_prop, page_sizes_prop_size))); 747 } 748 749 spapr_dt_pa_features(spapr, cpu, fdt, offset); 750 751 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 752 cs->cpu_index / vcpus_per_socket))); 753 754 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 755 pft_size_prop, sizeof(pft_size_prop)))); 756 757 if (ms->numa_state->num_nodes > 1) { 758 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 759 } 760 761 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 762 763 if (pcc->radix_page_info) { 764 for (i = 0; i < pcc->radix_page_info->count; i++) { 765 radix_AP_encodings[i] = 766 cpu_to_be32(pcc->radix_page_info->entries[i]); 767 } 768 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 769 radix_AP_encodings, 770 pcc->radix_page_info->count * 771 sizeof(radix_AP_encodings[0])))); 772 } 773 774 /* 775 * We set this property to let the guest know that it can use the large 776 * decrementer and its width in bits. 777 */ 778 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 779 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 780 pcc->lrg_decr_bits))); 781 } 782 783 static void spapr_dt_one_cpu(void *fdt, SpaprMachineState *spapr, CPUState *cs, 784 int cpus_offset) 785 { 786 PowerPCCPU *cpu = POWERPC_CPU(cs); 787 int index = spapr_get_vcpu_id(cpu); 788 DeviceClass *dc = DEVICE_GET_CLASS(cs); 789 g_autofree char *nodename = NULL; 790 int offset; 791 792 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 793 return; 794 } 795 796 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 797 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 798 _FDT(offset); 799 spapr_dt_cpu(cs, fdt, offset, spapr); 800 } 801 802 803 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 804 { 805 CPUState **rev; 806 CPUState *cs; 807 int n_cpus; 808 int cpus_offset; 809 int i; 810 811 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 812 _FDT(cpus_offset); 813 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 814 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 815 816 /* 817 * We walk the CPUs in reverse order to ensure that CPU DT nodes 818 * created by fdt_add_subnode() end up in the right order in FDT 819 * for the guest kernel the enumerate the CPUs correctly. 820 * 821 * The CPU list cannot be traversed in reverse order, so we need 822 * to do extra work. 823 */ 824 n_cpus = 0; 825 rev = NULL; 826 CPU_FOREACH(cs) { 827 rev = g_renew(CPUState *, rev, n_cpus + 1); 828 rev[n_cpus++] = cs; 829 } 830 831 for (i = n_cpus - 1; i >= 0; i--) { 832 spapr_dt_one_cpu(fdt, spapr, rev[i], cpus_offset); 833 } 834 835 g_free(rev); 836 } 837 838 static int spapr_dt_rng(void *fdt) 839 { 840 int node; 841 int ret; 842 843 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 844 if (node <= 0) { 845 return -1; 846 } 847 ret = fdt_setprop_string(fdt, node, "device_type", 848 "ibm,platform-facilities"); 849 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 850 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 851 852 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 853 if (node <= 0) { 854 return -1; 855 } 856 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 857 858 return ret ? -1 : 0; 859 } 860 861 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 862 { 863 MachineState *ms = MACHINE(spapr); 864 int rtas; 865 GString *hypertas = g_string_sized_new(256); 866 GString *qemu_hypertas = g_string_sized_new(256); 867 uint32_t lrdr_capacity[] = { 868 0, 869 0, 870 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 871 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 872 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 873 }; 874 875 /* Do we have device memory? */ 876 if (MACHINE(spapr)->device_memory) { 877 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 878 memory_region_size(&MACHINE(spapr)->device_memory->mr); 879 880 lrdr_capacity[0] = cpu_to_be32(max_device_addr >> 32); 881 lrdr_capacity[1] = cpu_to_be32(max_device_addr & 0xffffffff); 882 } 883 884 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 885 886 /* hypertas */ 887 add_str(hypertas, "hcall-pft"); 888 add_str(hypertas, "hcall-term"); 889 add_str(hypertas, "hcall-dabr"); 890 add_str(hypertas, "hcall-interrupt"); 891 add_str(hypertas, "hcall-tce"); 892 add_str(hypertas, "hcall-vio"); 893 add_str(hypertas, "hcall-splpar"); 894 add_str(hypertas, "hcall-join"); 895 add_str(hypertas, "hcall-bulk"); 896 add_str(hypertas, "hcall-set-mode"); 897 add_str(hypertas, "hcall-sprg0"); 898 add_str(hypertas, "hcall-copy"); 899 add_str(hypertas, "hcall-debug"); 900 add_str(hypertas, "hcall-vphn"); 901 if (spapr_get_cap(spapr, SPAPR_CAP_RPT_INVALIDATE) == SPAPR_CAP_ON) { 902 add_str(hypertas, "hcall-rpt-invalidate"); 903 } 904 905 add_str(qemu_hypertas, "hcall-memop1"); 906 907 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 908 add_str(hypertas, "hcall-multi-tce"); 909 } 910 911 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 912 add_str(hypertas, "hcall-hpt-resize"); 913 } 914 915 add_str(hypertas, "hcall-watchdog"); 916 917 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 918 hypertas->str, hypertas->len)); 919 g_string_free(hypertas, TRUE); 920 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 921 qemu_hypertas->str, qemu_hypertas->len)); 922 g_string_free(qemu_hypertas, TRUE); 923 924 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 925 926 /* 927 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 928 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 929 * 930 * The system reset requirements are driven by existing Linux and PowerVM 931 * implementation which (contrary to PAPR) saves r3 in the error log 932 * structure like machine check, so Linux expects to find the saved r3 933 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 934 * does not look at the error value). 935 * 936 * System reset interrupts are not subject to interlock like machine 937 * check, so this memory area could be corrupted if the sreset is 938 * interrupted by a machine check (or vice versa) if it was shared. To 939 * prevent this, system reset uses per-CPU areas for the sreset save 940 * area. A system reset that interrupts a system reset handler could 941 * still overwrite this area, but Linux doesn't try to recover in that 942 * case anyway. 943 * 944 * The extra 8 bytes is required because Linux's FWNMI error log check 945 * is off-by-one. 946 * 947 * RTAS_MIN_SIZE is required for the RTAS blob itself. 948 */ 949 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_MIN_SIZE + 950 RTAS_ERROR_LOG_MAX + 951 ms->smp.max_cpus * sizeof(uint64_t) * 2 + 952 sizeof(uint64_t))); 953 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 954 RTAS_ERROR_LOG_MAX)); 955 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 956 RTAS_EVENT_SCAN_RATE)); 957 958 g_assert(msi_nonbroken); 959 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 960 961 /* 962 * According to PAPR, rtas ibm,os-term does not guarantee a return 963 * back to the guest cpu. 964 * 965 * While an additional ibm,extended-os-term property indicates 966 * that rtas call return will always occur. Set this property. 967 */ 968 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 969 970 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 971 lrdr_capacity, sizeof(lrdr_capacity))); 972 973 spapr_dt_rtas_tokens(fdt, rtas); 974 } 975 976 /* 977 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 978 * and the XIVE features that the guest may request and thus the valid 979 * values for bytes 23..26 of option vector 5: 980 */ 981 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 982 int chosen) 983 { 984 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 985 986 char val[2 * 4] = { 987 23, 0x00, /* XICS / XIVE mode */ 988 24, 0x00, /* Hash/Radix, filled in below. */ 989 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 990 26, 0x40, /* Radix options: GTSE == yes. */ 991 }; 992 993 if (spapr->irq->xics && spapr->irq->xive) { 994 val[1] = SPAPR_OV5_XIVE_BOTH; 995 } else if (spapr->irq->xive) { 996 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 997 } else { 998 assert(spapr->irq->xics); 999 val[1] = SPAPR_OV5_XIVE_LEGACY; 1000 } 1001 1002 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1003 first_ppc_cpu->compat_pvr)) { 1004 /* 1005 * If we're in a pre POWER9 compat mode then the guest should 1006 * do hash and use the legacy interrupt mode 1007 */ 1008 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1009 val[3] = 0x00; /* Hash */ 1010 spapr_check_mmu_mode(false); 1011 } else if (kvm_enabled()) { 1012 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1013 val[3] = 0x80; /* OV5_MMU_BOTH */ 1014 } else if (kvmppc_has_cap_mmu_radix()) { 1015 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1016 } else { 1017 val[3] = 0x00; /* Hash */ 1018 } 1019 } else { 1020 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1021 val[3] = 0xC0; 1022 } 1023 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1024 val, sizeof(val))); 1025 } 1026 1027 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1028 { 1029 MachineState *machine = MACHINE(spapr); 1030 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1031 int chosen; 1032 1033 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1034 1035 if (reset) { 1036 const char *boot_device = spapr->boot_device; 1037 g_autofree char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1038 size_t cb = 0; 1039 g_autofree char *bootlist = get_boot_devices_list(&cb); 1040 1041 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1042 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1043 machine->kernel_cmdline)); 1044 } 1045 1046 if (spapr->initrd_size) { 1047 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1048 spapr->initrd_base)); 1049 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1050 spapr->initrd_base + spapr->initrd_size)); 1051 } 1052 1053 if (spapr->kernel_size) { 1054 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1055 cpu_to_be64(spapr->kernel_size) }; 1056 1057 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1058 &kprop, sizeof(kprop))); 1059 if (spapr->kernel_le) { 1060 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1061 } 1062 } 1063 if (machine->boot_config.has_menu && machine->boot_config.menu) { 1064 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", true))); 1065 } 1066 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1067 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1068 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1069 1070 if (cb && bootlist) { 1071 int i; 1072 1073 for (i = 0; i < cb; i++) { 1074 if (bootlist[i] == '\n') { 1075 bootlist[i] = ' '; 1076 } 1077 } 1078 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1079 } 1080 1081 if (boot_device && strlen(boot_device)) { 1082 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1083 } 1084 1085 if (spapr->want_stdout_path && stdout_path) { 1086 /* 1087 * "linux,stdout-path" and "stdout" properties are 1088 * deprecated by linux kernel. New platforms should only 1089 * use the "stdout-path" property. Set the new property 1090 * and continue using older property to remain compatible 1091 * with the existing firmware. 1092 */ 1093 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1094 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1095 } 1096 1097 /* 1098 * We can deal with BAR reallocation just fine, advertise it 1099 * to the guest 1100 */ 1101 if (smc->linux_pci_probe) { 1102 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1103 } 1104 1105 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1106 } 1107 1108 _FDT(fdt_setprop(fdt, chosen, "rng-seed", spapr->fdt_rng_seed, 32)); 1109 1110 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1111 } 1112 1113 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1114 { 1115 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1116 * KVM to work under pHyp with some guest co-operation */ 1117 int hypervisor; 1118 uint8_t hypercall[16]; 1119 1120 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1121 /* indicate KVM hypercall interface */ 1122 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1123 if (kvmppc_has_cap_fixup_hcalls()) { 1124 /* 1125 * Older KVM versions with older guest kernels were broken 1126 * with the magic page, don't allow the guest to map it. 1127 */ 1128 if (!kvmppc_get_hypercall(cpu_env(first_cpu), hypercall, 1129 sizeof(hypercall))) { 1130 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1131 hypercall, sizeof(hypercall))); 1132 } 1133 } 1134 } 1135 1136 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1137 { 1138 MachineState *machine = MACHINE(spapr); 1139 MachineClass *mc = MACHINE_GET_CLASS(machine); 1140 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1141 uint32_t root_drc_type_mask = 0; 1142 int ret; 1143 void *fdt; 1144 SpaprPhbState *phb; 1145 char *buf; 1146 1147 fdt = g_malloc0(space); 1148 _FDT((fdt_create_empty_tree(fdt, space))); 1149 1150 /* Root node */ 1151 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1152 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1153 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1154 1155 /* Guest UUID & Name*/ 1156 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1157 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1158 if (qemu_uuid_set) { 1159 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1160 } 1161 g_free(buf); 1162 1163 if (qemu_get_vm_name()) { 1164 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1165 qemu_get_vm_name())); 1166 } 1167 1168 /* Host Model & Serial Number */ 1169 if (spapr->host_model) { 1170 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1171 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1172 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1173 g_free(buf); 1174 } 1175 1176 if (spapr->host_serial) { 1177 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1178 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1179 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1180 g_free(buf); 1181 } 1182 1183 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1184 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1185 1186 /* /interrupt controller */ 1187 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1188 1189 ret = spapr_dt_memory(spapr, fdt); 1190 if (ret < 0) { 1191 error_report("couldn't setup memory nodes in fdt"); 1192 exit(1); 1193 } 1194 1195 /* /vdevice */ 1196 spapr_dt_vdevice(spapr->vio_bus, fdt); 1197 1198 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1199 ret = spapr_dt_rng(fdt); 1200 if (ret < 0) { 1201 error_report("could not set up rng device in the fdt"); 1202 exit(1); 1203 } 1204 } 1205 1206 QLIST_FOREACH(phb, &spapr->phbs, list) { 1207 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1208 if (ret < 0) { 1209 error_report("couldn't setup PCI devices in fdt"); 1210 exit(1); 1211 } 1212 } 1213 1214 spapr_dt_cpus(fdt, spapr); 1215 1216 /* ibm,drc-indexes and friends */ 1217 if (smc->dr_lmb_enabled) { 1218 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1219 } 1220 if (smc->dr_phb_enabled) { 1221 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1222 } 1223 if (mc->nvdimm_supported) { 1224 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1225 } 1226 if (root_drc_type_mask) { 1227 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1228 } 1229 1230 if (mc->has_hotpluggable_cpus) { 1231 int offset = fdt_path_offset(fdt, "/cpus"); 1232 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1233 if (ret < 0) { 1234 error_report("Couldn't set up CPU DR device tree properties"); 1235 exit(1); 1236 } 1237 } 1238 1239 /* /event-sources */ 1240 spapr_dt_events(spapr, fdt); 1241 1242 /* /rtas */ 1243 spapr_dt_rtas(spapr, fdt); 1244 1245 /* /chosen */ 1246 spapr_dt_chosen(spapr, fdt, reset); 1247 1248 /* /hypervisor */ 1249 if (kvm_enabled()) { 1250 spapr_dt_hypervisor(spapr, fdt); 1251 } 1252 1253 /* Build memory reserve map */ 1254 if (reset) { 1255 if (spapr->kernel_size) { 1256 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1257 spapr->kernel_size))); 1258 } 1259 if (spapr->initrd_size) { 1260 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1261 spapr->initrd_size))); 1262 } 1263 } 1264 1265 /* NVDIMM devices */ 1266 if (mc->nvdimm_supported) { 1267 spapr_dt_persistent_memory(spapr, fdt); 1268 } 1269 1270 return fdt; 1271 } 1272 1273 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1274 { 1275 SpaprMachineState *spapr = opaque; 1276 1277 return (addr & 0x0fffffff) + spapr->kernel_addr; 1278 } 1279 1280 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1281 PowerPCCPU *cpu) 1282 { 1283 CPUPPCState *env = &cpu->env; 1284 1285 /* The TCG path should also be holding the BQL at this point */ 1286 g_assert(qemu_mutex_iothread_locked()); 1287 1288 g_assert(!vhyp_cpu_in_nested(cpu)); 1289 1290 if (FIELD_EX64(env->msr, MSR, PR)) { 1291 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1292 env->gpr[3] = H_PRIVILEGE; 1293 } else { 1294 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1295 } 1296 } 1297 1298 struct LPCRSyncState { 1299 target_ulong value; 1300 target_ulong mask; 1301 }; 1302 1303 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1304 { 1305 struct LPCRSyncState *s = arg.host_ptr; 1306 PowerPCCPU *cpu = POWERPC_CPU(cs); 1307 CPUPPCState *env = &cpu->env; 1308 target_ulong lpcr; 1309 1310 cpu_synchronize_state(cs); 1311 lpcr = env->spr[SPR_LPCR]; 1312 lpcr &= ~s->mask; 1313 lpcr |= s->value; 1314 ppc_store_lpcr(cpu, lpcr); 1315 } 1316 1317 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1318 { 1319 CPUState *cs; 1320 struct LPCRSyncState s = { 1321 .value = value, 1322 .mask = mask 1323 }; 1324 CPU_FOREACH(cs) { 1325 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1326 } 1327 } 1328 1329 /* May be used when the machine is not running */ 1330 void spapr_init_all_lpcrs(target_ulong value, target_ulong mask) 1331 { 1332 CPUState *cs; 1333 CPU_FOREACH(cs) { 1334 PowerPCCPU *cpu = POWERPC_CPU(cs); 1335 CPUPPCState *env = &cpu->env; 1336 target_ulong lpcr; 1337 1338 lpcr = env->spr[SPR_LPCR]; 1339 lpcr &= ~(LPCR_HR | LPCR_UPRT); 1340 ppc_store_lpcr(cpu, lpcr); 1341 } 1342 } 1343 1344 1345 static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu, 1346 target_ulong lpid, ppc_v3_pate_t *entry) 1347 { 1348 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1349 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1350 1351 if (!spapr_cpu->in_nested) { 1352 assert(lpid == 0); 1353 1354 /* Copy PATE1:GR into PATE0:HR */ 1355 entry->dw0 = spapr->patb_entry & PATE0_HR; 1356 entry->dw1 = spapr->patb_entry; 1357 1358 } else { 1359 uint64_t patb, pats; 1360 1361 assert(lpid != 0); 1362 1363 patb = spapr->nested_ptcr & PTCR_PATB; 1364 pats = spapr->nested_ptcr & PTCR_PATS; 1365 1366 /* Check if partition table is properly aligned */ 1367 if (patb & MAKE_64BIT_MASK(0, pats + 12)) { 1368 return false; 1369 } 1370 1371 /* Calculate number of entries */ 1372 pats = 1ull << (pats + 12 - 4); 1373 if (pats <= lpid) { 1374 return false; 1375 } 1376 1377 /* Grab entry */ 1378 patb += 16 * lpid; 1379 entry->dw0 = ldq_phys(CPU(cpu)->as, patb); 1380 entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8); 1381 } 1382 1383 return true; 1384 } 1385 1386 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1387 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1388 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1389 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1390 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1391 1392 /* 1393 * Get the fd to access the kernel htab, re-opening it if necessary 1394 */ 1395 static int get_htab_fd(SpaprMachineState *spapr) 1396 { 1397 Error *local_err = NULL; 1398 1399 if (spapr->htab_fd >= 0) { 1400 return spapr->htab_fd; 1401 } 1402 1403 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1404 if (spapr->htab_fd < 0) { 1405 error_report_err(local_err); 1406 } 1407 1408 return spapr->htab_fd; 1409 } 1410 1411 void close_htab_fd(SpaprMachineState *spapr) 1412 { 1413 if (spapr->htab_fd >= 0) { 1414 close(spapr->htab_fd); 1415 } 1416 spapr->htab_fd = -1; 1417 } 1418 1419 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1420 { 1421 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1422 1423 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1424 } 1425 1426 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1427 { 1428 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1429 1430 assert(kvm_enabled()); 1431 1432 if (!spapr->htab) { 1433 return 0; 1434 } 1435 1436 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1437 } 1438 1439 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1440 hwaddr ptex, int n) 1441 { 1442 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1443 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1444 1445 if (!spapr->htab) { 1446 /* 1447 * HTAB is controlled by KVM. Fetch into temporary buffer 1448 */ 1449 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1450 kvmppc_read_hptes(hptes, ptex, n); 1451 return hptes; 1452 } 1453 1454 /* 1455 * HTAB is controlled by QEMU. Just point to the internally 1456 * accessible PTEG. 1457 */ 1458 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1459 } 1460 1461 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1462 const ppc_hash_pte64_t *hptes, 1463 hwaddr ptex, int n) 1464 { 1465 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1466 1467 if (!spapr->htab) { 1468 g_free((void *)hptes); 1469 } 1470 1471 /* Nothing to do for qemu managed HPT */ 1472 } 1473 1474 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1475 uint64_t pte0, uint64_t pte1) 1476 { 1477 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1478 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1479 1480 if (!spapr->htab) { 1481 kvmppc_write_hpte(ptex, pte0, pte1); 1482 } else { 1483 if (pte0 & HPTE64_V_VALID) { 1484 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1485 /* 1486 * When setting valid, we write PTE1 first. This ensures 1487 * proper synchronization with the reading code in 1488 * ppc_hash64_pteg_search() 1489 */ 1490 smp_wmb(); 1491 stq_p(spapr->htab + offset, pte0); 1492 } else { 1493 stq_p(spapr->htab + offset, pte0); 1494 /* 1495 * When clearing it we set PTE0 first. This ensures proper 1496 * synchronization with the reading code in 1497 * ppc_hash64_pteg_search() 1498 */ 1499 smp_wmb(); 1500 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1501 } 1502 } 1503 } 1504 1505 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1506 uint64_t pte1) 1507 { 1508 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_C; 1509 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1510 1511 if (!spapr->htab) { 1512 /* There should always be a hash table when this is called */ 1513 error_report("spapr_hpte_set_c called with no hash table !"); 1514 return; 1515 } 1516 1517 /* The HW performs a non-atomic byte update */ 1518 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1519 } 1520 1521 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1522 uint64_t pte1) 1523 { 1524 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_R; 1525 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1526 1527 if (!spapr->htab) { 1528 /* There should always be a hash table when this is called */ 1529 error_report("spapr_hpte_set_r called with no hash table !"); 1530 return; 1531 } 1532 1533 /* The HW performs a non-atomic byte update */ 1534 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1535 } 1536 1537 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1538 { 1539 int shift; 1540 1541 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1542 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1543 * that's much more than is needed for Linux guests */ 1544 shift = ctz64(pow2ceil(ramsize)) - 7; 1545 shift = MAX(shift, 18); /* Minimum architected size */ 1546 shift = MIN(shift, 46); /* Maximum architected size */ 1547 return shift; 1548 } 1549 1550 void spapr_free_hpt(SpaprMachineState *spapr) 1551 { 1552 qemu_vfree(spapr->htab); 1553 spapr->htab = NULL; 1554 spapr->htab_shift = 0; 1555 close_htab_fd(spapr); 1556 } 1557 1558 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1559 { 1560 ERRP_GUARD(); 1561 long rc; 1562 1563 /* Clean up any HPT info from a previous boot */ 1564 spapr_free_hpt(spapr); 1565 1566 rc = kvmppc_reset_htab(shift); 1567 1568 if (rc == -EOPNOTSUPP) { 1569 error_setg(errp, "HPT not supported in nested guests"); 1570 return -EOPNOTSUPP; 1571 } 1572 1573 if (rc < 0) { 1574 /* kernel-side HPT needed, but couldn't allocate one */ 1575 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1576 shift); 1577 error_append_hint(errp, "Try smaller maxmem?\n"); 1578 return -errno; 1579 } else if (rc > 0) { 1580 /* kernel-side HPT allocated */ 1581 if (rc != shift) { 1582 error_setg(errp, 1583 "Requested order %d HPT, but kernel allocated order %ld", 1584 shift, rc); 1585 error_append_hint(errp, "Try smaller maxmem?\n"); 1586 return -ENOSPC; 1587 } 1588 1589 spapr->htab_shift = shift; 1590 spapr->htab = NULL; 1591 } else { 1592 /* kernel-side HPT not needed, allocate in userspace instead */ 1593 size_t size = 1ULL << shift; 1594 int i; 1595 1596 spapr->htab = qemu_memalign(size, size); 1597 memset(spapr->htab, 0, size); 1598 spapr->htab_shift = shift; 1599 1600 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1601 DIRTY_HPTE(HPTE(spapr->htab, i)); 1602 } 1603 } 1604 /* We're setting up a hash table, so that means we're not radix */ 1605 spapr->patb_entry = 0; 1606 spapr_init_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1607 return 0; 1608 } 1609 1610 void spapr_setup_hpt(SpaprMachineState *spapr) 1611 { 1612 int hpt_shift; 1613 1614 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1615 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1616 } else { 1617 uint64_t current_ram_size; 1618 1619 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1620 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1621 } 1622 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1623 1624 if (kvm_enabled()) { 1625 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1626 1627 /* Check our RMA fits in the possible VRMA */ 1628 if (vrma_limit < spapr->rma_size) { 1629 error_report("Unable to create %" HWADDR_PRIu 1630 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1631 spapr->rma_size / MiB, vrma_limit / MiB); 1632 exit(EXIT_FAILURE); 1633 } 1634 } 1635 } 1636 1637 void spapr_check_mmu_mode(bool guest_radix) 1638 { 1639 if (guest_radix) { 1640 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1641 error_report("Guest requested unavailable MMU mode (radix)."); 1642 exit(EXIT_FAILURE); 1643 } 1644 } else { 1645 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1646 && !kvmppc_has_cap_mmu_hash_v3()) { 1647 error_report("Guest requested unavailable MMU mode (hash)."); 1648 exit(EXIT_FAILURE); 1649 } 1650 } 1651 } 1652 1653 static void spapr_machine_reset(MachineState *machine, ShutdownCause reason) 1654 { 1655 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1656 PowerPCCPU *first_ppc_cpu; 1657 hwaddr fdt_addr; 1658 void *fdt; 1659 int rc; 1660 1661 if (reason != SHUTDOWN_CAUSE_SNAPSHOT_LOAD) { 1662 /* 1663 * Record-replay snapshot load must not consume random, this was 1664 * already replayed from initial machine reset. 1665 */ 1666 qemu_guest_getrandom_nofail(spapr->fdt_rng_seed, 32); 1667 } 1668 1669 pef_kvm_reset(machine->cgs, &error_fatal); 1670 spapr_caps_apply(spapr); 1671 1672 first_ppc_cpu = POWERPC_CPU(first_cpu); 1673 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1674 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1675 spapr->max_compat_pvr)) { 1676 /* 1677 * If using KVM with radix mode available, VCPUs can be started 1678 * without a HPT because KVM will start them in radix mode. 1679 * Set the GR bit in PATE so that we know there is no HPT. 1680 */ 1681 spapr->patb_entry = PATE1_GR; 1682 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1683 } else { 1684 spapr_setup_hpt(spapr); 1685 } 1686 1687 qemu_devices_reset(reason); 1688 1689 spapr_ovec_cleanup(spapr->ov5_cas); 1690 spapr->ov5_cas = spapr_ovec_new(); 1691 1692 ppc_init_compat_all(spapr->max_compat_pvr, &error_fatal); 1693 1694 /* 1695 * This is fixing some of the default configuration of the XIVE 1696 * devices. To be called after the reset of the machine devices. 1697 */ 1698 spapr_irq_reset(spapr, &error_fatal); 1699 1700 /* 1701 * There is no CAS under qtest. Simulate one to please the code that 1702 * depends on spapr->ov5_cas. This is especially needed to test device 1703 * unplug, so we do that before resetting the DRCs. 1704 */ 1705 if (qtest_enabled()) { 1706 spapr_ovec_cleanup(spapr->ov5_cas); 1707 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1708 } 1709 1710 spapr_nvdimm_finish_flushes(); 1711 1712 /* DRC reset may cause a device to be unplugged. This will cause troubles 1713 * if this device is used by another device (eg, a running vhost backend 1714 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1715 * situations, we reset DRCs after all devices have been reset. 1716 */ 1717 spapr_drc_reset_all(spapr); 1718 1719 spapr_clear_pending_events(spapr); 1720 1721 /* 1722 * We place the device tree just below either the top of the RMA, 1723 * or just below 2GB, whichever is lower, so that it can be 1724 * processed with 32-bit real mode code if necessary 1725 */ 1726 fdt_addr = MIN(spapr->rma_size, FDT_MAX_ADDR) - FDT_MAX_SIZE; 1727 1728 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1729 if (spapr->vof) { 1730 spapr_vof_reset(spapr, fdt, &error_fatal); 1731 /* 1732 * Do not pack the FDT as the client may change properties. 1733 * VOF client does not expect the FDT so we do not load it to the VM. 1734 */ 1735 } else { 1736 rc = fdt_pack(fdt); 1737 /* Should only fail if we've built a corrupted tree */ 1738 assert(rc == 0); 1739 1740 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 1741 0, fdt_addr, 0); 1742 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1743 } 1744 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1745 1746 g_free(spapr->fdt_blob); 1747 spapr->fdt_size = fdt_totalsize(fdt); 1748 spapr->fdt_initial_size = spapr->fdt_size; 1749 spapr->fdt_blob = fdt; 1750 1751 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ 1752 machine->fdt = fdt; 1753 1754 /* Set up the entry state */ 1755 first_ppc_cpu->env.gpr[5] = 0; 1756 1757 spapr->fwnmi_system_reset_addr = -1; 1758 spapr->fwnmi_machine_check_addr = -1; 1759 spapr->fwnmi_machine_check_interlock = -1; 1760 1761 /* Signal all vCPUs waiting on this condition */ 1762 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1763 1764 migrate_del_blocker(&spapr->fwnmi_migration_blocker); 1765 } 1766 1767 static void spapr_create_nvram(SpaprMachineState *spapr) 1768 { 1769 DeviceState *dev = qdev_new("spapr-nvram"); 1770 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1771 1772 if (dinfo) { 1773 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1774 &error_fatal); 1775 } 1776 1777 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1778 1779 spapr->nvram = (struct SpaprNvram *)dev; 1780 } 1781 1782 static void spapr_rtc_create(SpaprMachineState *spapr) 1783 { 1784 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1785 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1786 &error_fatal, NULL); 1787 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1788 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1789 "date"); 1790 } 1791 1792 /* Returns whether we want to use VGA or not */ 1793 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1794 { 1795 vga_interface_created = true; 1796 switch (vga_interface_type) { 1797 case VGA_NONE: 1798 return false; 1799 case VGA_DEVICE: 1800 return true; 1801 case VGA_STD: 1802 case VGA_VIRTIO: 1803 case VGA_CIRRUS: 1804 return pci_vga_init(pci_bus) != NULL; 1805 default: 1806 error_setg(errp, 1807 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1808 return false; 1809 } 1810 } 1811 1812 static int spapr_pre_load(void *opaque) 1813 { 1814 int rc; 1815 1816 rc = spapr_caps_pre_load(opaque); 1817 if (rc) { 1818 return rc; 1819 } 1820 1821 return 0; 1822 } 1823 1824 static int spapr_post_load(void *opaque, int version_id) 1825 { 1826 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1827 int err = 0; 1828 1829 err = spapr_caps_post_migration(spapr); 1830 if (err) { 1831 return err; 1832 } 1833 1834 /* 1835 * In earlier versions, there was no separate qdev for the PAPR 1836 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1837 * So when migrating from those versions, poke the incoming offset 1838 * value into the RTC device 1839 */ 1840 if (version_id < 3) { 1841 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1842 if (err) { 1843 return err; 1844 } 1845 } 1846 1847 if (kvm_enabled() && spapr->patb_entry) { 1848 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1849 bool radix = !!(spapr->patb_entry & PATE1_GR); 1850 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1851 1852 /* 1853 * Update LPCR:HR and UPRT as they may not be set properly in 1854 * the stream 1855 */ 1856 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1857 LPCR_HR | LPCR_UPRT); 1858 1859 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1860 if (err) { 1861 error_report("Process table config unsupported by the host"); 1862 return -EINVAL; 1863 } 1864 } 1865 1866 err = spapr_irq_post_load(spapr, version_id); 1867 if (err) { 1868 return err; 1869 } 1870 1871 return err; 1872 } 1873 1874 static int spapr_pre_save(void *opaque) 1875 { 1876 int rc; 1877 1878 rc = spapr_caps_pre_save(opaque); 1879 if (rc) { 1880 return rc; 1881 } 1882 1883 return 0; 1884 } 1885 1886 static bool version_before_3(void *opaque, int version_id) 1887 { 1888 return version_id < 3; 1889 } 1890 1891 static bool spapr_pending_events_needed(void *opaque) 1892 { 1893 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1894 return !QTAILQ_EMPTY(&spapr->pending_events); 1895 } 1896 1897 static const VMStateDescription vmstate_spapr_event_entry = { 1898 .name = "spapr_event_log_entry", 1899 .version_id = 1, 1900 .minimum_version_id = 1, 1901 .fields = (VMStateField[]) { 1902 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1903 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1904 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1905 NULL, extended_length), 1906 VMSTATE_END_OF_LIST() 1907 }, 1908 }; 1909 1910 static const VMStateDescription vmstate_spapr_pending_events = { 1911 .name = "spapr_pending_events", 1912 .version_id = 1, 1913 .minimum_version_id = 1, 1914 .needed = spapr_pending_events_needed, 1915 .fields = (VMStateField[]) { 1916 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1917 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1918 VMSTATE_END_OF_LIST() 1919 }, 1920 }; 1921 1922 static bool spapr_ov5_cas_needed(void *opaque) 1923 { 1924 SpaprMachineState *spapr = opaque; 1925 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1926 bool cas_needed; 1927 1928 /* Prior to the introduction of SpaprOptionVector, we had two option 1929 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1930 * Both of these options encode machine topology into the device-tree 1931 * in such a way that the now-booted OS should still be able to interact 1932 * appropriately with QEMU regardless of what options were actually 1933 * negotiatied on the source side. 1934 * 1935 * As such, we can avoid migrating the CAS-negotiated options if these 1936 * are the only options available on the current machine/platform. 1937 * Since these are the only options available for pseries-2.7 and 1938 * earlier, this allows us to maintain old->new/new->old migration 1939 * compatibility. 1940 * 1941 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1942 * via default pseries-2.8 machines and explicit command-line parameters. 1943 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1944 * of the actual CAS-negotiated values to continue working properly. For 1945 * example, availability of memory unplug depends on knowing whether 1946 * OV5_HP_EVT was negotiated via CAS. 1947 * 1948 * Thus, for any cases where the set of available CAS-negotiatable 1949 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1950 * include the CAS-negotiated options in the migration stream, unless 1951 * if they affect boot time behaviour only. 1952 */ 1953 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1954 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1955 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1956 1957 /* We need extra information if we have any bits outside the mask 1958 * defined above */ 1959 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1960 1961 spapr_ovec_cleanup(ov5_mask); 1962 1963 return cas_needed; 1964 } 1965 1966 static const VMStateDescription vmstate_spapr_ov5_cas = { 1967 .name = "spapr_option_vector_ov5_cas", 1968 .version_id = 1, 1969 .minimum_version_id = 1, 1970 .needed = spapr_ov5_cas_needed, 1971 .fields = (VMStateField[]) { 1972 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1973 vmstate_spapr_ovec, SpaprOptionVector), 1974 VMSTATE_END_OF_LIST() 1975 }, 1976 }; 1977 1978 static bool spapr_patb_entry_needed(void *opaque) 1979 { 1980 SpaprMachineState *spapr = opaque; 1981 1982 return !!spapr->patb_entry; 1983 } 1984 1985 static const VMStateDescription vmstate_spapr_patb_entry = { 1986 .name = "spapr_patb_entry", 1987 .version_id = 1, 1988 .minimum_version_id = 1, 1989 .needed = spapr_patb_entry_needed, 1990 .fields = (VMStateField[]) { 1991 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1992 VMSTATE_END_OF_LIST() 1993 }, 1994 }; 1995 1996 static bool spapr_irq_map_needed(void *opaque) 1997 { 1998 SpaprMachineState *spapr = opaque; 1999 2000 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 2001 } 2002 2003 static const VMStateDescription vmstate_spapr_irq_map = { 2004 .name = "spapr_irq_map", 2005 .version_id = 1, 2006 .minimum_version_id = 1, 2007 .needed = spapr_irq_map_needed, 2008 .fields = (VMStateField[]) { 2009 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 2010 VMSTATE_END_OF_LIST() 2011 }, 2012 }; 2013 2014 static bool spapr_dtb_needed(void *opaque) 2015 { 2016 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 2017 2018 return smc->update_dt_enabled; 2019 } 2020 2021 static int spapr_dtb_pre_load(void *opaque) 2022 { 2023 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2024 2025 g_free(spapr->fdt_blob); 2026 spapr->fdt_blob = NULL; 2027 spapr->fdt_size = 0; 2028 2029 return 0; 2030 } 2031 2032 static const VMStateDescription vmstate_spapr_dtb = { 2033 .name = "spapr_dtb", 2034 .version_id = 1, 2035 .minimum_version_id = 1, 2036 .needed = spapr_dtb_needed, 2037 .pre_load = spapr_dtb_pre_load, 2038 .fields = (VMStateField[]) { 2039 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 2040 VMSTATE_UINT32(fdt_size, SpaprMachineState), 2041 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 2042 fdt_size), 2043 VMSTATE_END_OF_LIST() 2044 }, 2045 }; 2046 2047 static bool spapr_fwnmi_needed(void *opaque) 2048 { 2049 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2050 2051 return spapr->fwnmi_machine_check_addr != -1; 2052 } 2053 2054 static int spapr_fwnmi_pre_save(void *opaque) 2055 { 2056 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2057 2058 /* 2059 * Check if machine check handling is in progress and print a 2060 * warning message. 2061 */ 2062 if (spapr->fwnmi_machine_check_interlock != -1) { 2063 warn_report("A machine check is being handled during migration. The" 2064 "handler may run and log hardware error on the destination"); 2065 } 2066 2067 return 0; 2068 } 2069 2070 static const VMStateDescription vmstate_spapr_fwnmi = { 2071 .name = "spapr_fwnmi", 2072 .version_id = 1, 2073 .minimum_version_id = 1, 2074 .needed = spapr_fwnmi_needed, 2075 .pre_save = spapr_fwnmi_pre_save, 2076 .fields = (VMStateField[]) { 2077 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 2078 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 2079 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 2080 VMSTATE_END_OF_LIST() 2081 }, 2082 }; 2083 2084 static const VMStateDescription vmstate_spapr = { 2085 .name = "spapr", 2086 .version_id = 3, 2087 .minimum_version_id = 1, 2088 .pre_load = spapr_pre_load, 2089 .post_load = spapr_post_load, 2090 .pre_save = spapr_pre_save, 2091 .fields = (VMStateField[]) { 2092 /* used to be @next_irq */ 2093 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2094 2095 /* RTC offset */ 2096 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2097 2098 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2099 VMSTATE_END_OF_LIST() 2100 }, 2101 .subsections = (const VMStateDescription*[]) { 2102 &vmstate_spapr_ov5_cas, 2103 &vmstate_spapr_patb_entry, 2104 &vmstate_spapr_pending_events, 2105 &vmstate_spapr_cap_htm, 2106 &vmstate_spapr_cap_vsx, 2107 &vmstate_spapr_cap_dfp, 2108 &vmstate_spapr_cap_cfpc, 2109 &vmstate_spapr_cap_sbbc, 2110 &vmstate_spapr_cap_ibs, 2111 &vmstate_spapr_cap_hpt_maxpagesize, 2112 &vmstate_spapr_irq_map, 2113 &vmstate_spapr_cap_nested_kvm_hv, 2114 &vmstate_spapr_dtb, 2115 &vmstate_spapr_cap_large_decr, 2116 &vmstate_spapr_cap_ccf_assist, 2117 &vmstate_spapr_cap_fwnmi, 2118 &vmstate_spapr_fwnmi, 2119 &vmstate_spapr_cap_rpt_invalidate, 2120 NULL 2121 } 2122 }; 2123 2124 static int htab_save_setup(QEMUFile *f, void *opaque) 2125 { 2126 SpaprMachineState *spapr = opaque; 2127 2128 /* "Iteration" header */ 2129 if (!spapr->htab_shift) { 2130 qemu_put_be32(f, -1); 2131 } else { 2132 qemu_put_be32(f, spapr->htab_shift); 2133 } 2134 2135 if (spapr->htab) { 2136 spapr->htab_save_index = 0; 2137 spapr->htab_first_pass = true; 2138 } else { 2139 if (spapr->htab_shift) { 2140 assert(kvm_enabled()); 2141 } 2142 } 2143 2144 2145 return 0; 2146 } 2147 2148 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2149 int chunkstart, int n_valid, int n_invalid) 2150 { 2151 qemu_put_be32(f, chunkstart); 2152 qemu_put_be16(f, n_valid); 2153 qemu_put_be16(f, n_invalid); 2154 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2155 HASH_PTE_SIZE_64 * n_valid); 2156 } 2157 2158 static void htab_save_end_marker(QEMUFile *f) 2159 { 2160 qemu_put_be32(f, 0); 2161 qemu_put_be16(f, 0); 2162 qemu_put_be16(f, 0); 2163 } 2164 2165 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2166 int64_t max_ns) 2167 { 2168 bool has_timeout = max_ns != -1; 2169 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2170 int index = spapr->htab_save_index; 2171 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2172 2173 assert(spapr->htab_first_pass); 2174 2175 do { 2176 int chunkstart; 2177 2178 /* Consume invalid HPTEs */ 2179 while ((index < htabslots) 2180 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2181 CLEAN_HPTE(HPTE(spapr->htab, index)); 2182 index++; 2183 } 2184 2185 /* Consume valid HPTEs */ 2186 chunkstart = index; 2187 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2188 && HPTE_VALID(HPTE(spapr->htab, index))) { 2189 CLEAN_HPTE(HPTE(spapr->htab, index)); 2190 index++; 2191 } 2192 2193 if (index > chunkstart) { 2194 int n_valid = index - chunkstart; 2195 2196 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2197 2198 if (has_timeout && 2199 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2200 break; 2201 } 2202 } 2203 } while ((index < htabslots) && !migration_rate_exceeded(f)); 2204 2205 if (index >= htabslots) { 2206 assert(index == htabslots); 2207 index = 0; 2208 spapr->htab_first_pass = false; 2209 } 2210 spapr->htab_save_index = index; 2211 } 2212 2213 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2214 int64_t max_ns) 2215 { 2216 bool final = max_ns < 0; 2217 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2218 int examined = 0, sent = 0; 2219 int index = spapr->htab_save_index; 2220 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2221 2222 assert(!spapr->htab_first_pass); 2223 2224 do { 2225 int chunkstart, invalidstart; 2226 2227 /* Consume non-dirty HPTEs */ 2228 while ((index < htabslots) 2229 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2230 index++; 2231 examined++; 2232 } 2233 2234 chunkstart = index; 2235 /* Consume valid dirty HPTEs */ 2236 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2237 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2238 && HPTE_VALID(HPTE(spapr->htab, index))) { 2239 CLEAN_HPTE(HPTE(spapr->htab, index)); 2240 index++; 2241 examined++; 2242 } 2243 2244 invalidstart = index; 2245 /* Consume invalid dirty HPTEs */ 2246 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2247 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2248 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2249 CLEAN_HPTE(HPTE(spapr->htab, index)); 2250 index++; 2251 examined++; 2252 } 2253 2254 if (index > chunkstart) { 2255 int n_valid = invalidstart - chunkstart; 2256 int n_invalid = index - invalidstart; 2257 2258 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2259 sent += index - chunkstart; 2260 2261 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2262 break; 2263 } 2264 } 2265 2266 if (examined >= htabslots) { 2267 break; 2268 } 2269 2270 if (index >= htabslots) { 2271 assert(index == htabslots); 2272 index = 0; 2273 } 2274 } while ((examined < htabslots) && (!migration_rate_exceeded(f) || final)); 2275 2276 if (index >= htabslots) { 2277 assert(index == htabslots); 2278 index = 0; 2279 } 2280 2281 spapr->htab_save_index = index; 2282 2283 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2284 } 2285 2286 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2287 #define MAX_KVM_BUF_SIZE 2048 2288 2289 static int htab_save_iterate(QEMUFile *f, void *opaque) 2290 { 2291 SpaprMachineState *spapr = opaque; 2292 int fd; 2293 int rc = 0; 2294 2295 /* Iteration header */ 2296 if (!spapr->htab_shift) { 2297 qemu_put_be32(f, -1); 2298 return 1; 2299 } else { 2300 qemu_put_be32(f, 0); 2301 } 2302 2303 if (!spapr->htab) { 2304 assert(kvm_enabled()); 2305 2306 fd = get_htab_fd(spapr); 2307 if (fd < 0) { 2308 return fd; 2309 } 2310 2311 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2312 if (rc < 0) { 2313 return rc; 2314 } 2315 } else if (spapr->htab_first_pass) { 2316 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2317 } else { 2318 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2319 } 2320 2321 htab_save_end_marker(f); 2322 2323 return rc; 2324 } 2325 2326 static int htab_save_complete(QEMUFile *f, void *opaque) 2327 { 2328 SpaprMachineState *spapr = opaque; 2329 int fd; 2330 2331 /* Iteration header */ 2332 if (!spapr->htab_shift) { 2333 qemu_put_be32(f, -1); 2334 return 0; 2335 } else { 2336 qemu_put_be32(f, 0); 2337 } 2338 2339 if (!spapr->htab) { 2340 int rc; 2341 2342 assert(kvm_enabled()); 2343 2344 fd = get_htab_fd(spapr); 2345 if (fd < 0) { 2346 return fd; 2347 } 2348 2349 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2350 if (rc < 0) { 2351 return rc; 2352 } 2353 } else { 2354 if (spapr->htab_first_pass) { 2355 htab_save_first_pass(f, spapr, -1); 2356 } 2357 htab_save_later_pass(f, spapr, -1); 2358 } 2359 2360 /* End marker */ 2361 htab_save_end_marker(f); 2362 2363 return 0; 2364 } 2365 2366 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2367 { 2368 SpaprMachineState *spapr = opaque; 2369 uint32_t section_hdr; 2370 int fd = -1; 2371 Error *local_err = NULL; 2372 2373 if (version_id < 1 || version_id > 1) { 2374 error_report("htab_load() bad version"); 2375 return -EINVAL; 2376 } 2377 2378 section_hdr = qemu_get_be32(f); 2379 2380 if (section_hdr == -1) { 2381 spapr_free_hpt(spapr); 2382 return 0; 2383 } 2384 2385 if (section_hdr) { 2386 int ret; 2387 2388 /* First section gives the htab size */ 2389 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2390 if (ret < 0) { 2391 error_report_err(local_err); 2392 return ret; 2393 } 2394 return 0; 2395 } 2396 2397 if (!spapr->htab) { 2398 assert(kvm_enabled()); 2399 2400 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2401 if (fd < 0) { 2402 error_report_err(local_err); 2403 return fd; 2404 } 2405 } 2406 2407 while (true) { 2408 uint32_t index; 2409 uint16_t n_valid, n_invalid; 2410 2411 index = qemu_get_be32(f); 2412 n_valid = qemu_get_be16(f); 2413 n_invalid = qemu_get_be16(f); 2414 2415 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2416 /* End of Stream */ 2417 break; 2418 } 2419 2420 if ((index + n_valid + n_invalid) > 2421 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2422 /* Bad index in stream */ 2423 error_report( 2424 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2425 index, n_valid, n_invalid, spapr->htab_shift); 2426 return -EINVAL; 2427 } 2428 2429 if (spapr->htab) { 2430 if (n_valid) { 2431 qemu_get_buffer(f, HPTE(spapr->htab, index), 2432 HASH_PTE_SIZE_64 * n_valid); 2433 } 2434 if (n_invalid) { 2435 memset(HPTE(spapr->htab, index + n_valid), 0, 2436 HASH_PTE_SIZE_64 * n_invalid); 2437 } 2438 } else { 2439 int rc; 2440 2441 assert(fd >= 0); 2442 2443 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2444 &local_err); 2445 if (rc < 0) { 2446 error_report_err(local_err); 2447 return rc; 2448 } 2449 } 2450 } 2451 2452 if (!spapr->htab) { 2453 assert(fd >= 0); 2454 close(fd); 2455 } 2456 2457 return 0; 2458 } 2459 2460 static void htab_save_cleanup(void *opaque) 2461 { 2462 SpaprMachineState *spapr = opaque; 2463 2464 close_htab_fd(spapr); 2465 } 2466 2467 static SaveVMHandlers savevm_htab_handlers = { 2468 .save_setup = htab_save_setup, 2469 .save_live_iterate = htab_save_iterate, 2470 .save_live_complete_precopy = htab_save_complete, 2471 .save_cleanup = htab_save_cleanup, 2472 .load_state = htab_load, 2473 }; 2474 2475 static void spapr_boot_set(void *opaque, const char *boot_device, 2476 Error **errp) 2477 { 2478 SpaprMachineState *spapr = SPAPR_MACHINE(opaque); 2479 2480 g_free(spapr->boot_device); 2481 spapr->boot_device = g_strdup(boot_device); 2482 } 2483 2484 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2485 { 2486 MachineState *machine = MACHINE(spapr); 2487 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2488 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2489 int i; 2490 2491 g_assert(!nr_lmbs || machine->device_memory); 2492 for (i = 0; i < nr_lmbs; i++) { 2493 uint64_t addr; 2494 2495 addr = i * lmb_size + machine->device_memory->base; 2496 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2497 addr / lmb_size); 2498 } 2499 } 2500 2501 /* 2502 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2503 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2504 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2505 */ 2506 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2507 { 2508 int i; 2509 2510 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2511 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2512 " is not aligned to %" PRIu64 " MiB", 2513 machine->ram_size, 2514 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2515 return; 2516 } 2517 2518 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2519 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2520 " is not aligned to %" PRIu64 " MiB", 2521 machine->ram_size, 2522 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2523 return; 2524 } 2525 2526 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2527 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2528 error_setg(errp, 2529 "Node %d memory size 0x%" PRIx64 2530 " is not aligned to %" PRIu64 " MiB", 2531 i, machine->numa_state->nodes[i].node_mem, 2532 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2533 return; 2534 } 2535 } 2536 } 2537 2538 /* find cpu slot in machine->possible_cpus by core_id */ 2539 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2540 { 2541 int index = id / ms->smp.threads; 2542 2543 if (index >= ms->possible_cpus->len) { 2544 return NULL; 2545 } 2546 if (idx) { 2547 *idx = index; 2548 } 2549 return &ms->possible_cpus->cpus[index]; 2550 } 2551 2552 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2553 { 2554 MachineState *ms = MACHINE(spapr); 2555 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2556 Error *local_err = NULL; 2557 bool vsmt_user = !!spapr->vsmt; 2558 int kvm_smt = kvmppc_smt_threads(); 2559 int ret; 2560 unsigned int smp_threads = ms->smp.threads; 2561 2562 if (tcg_enabled()) { 2563 if (smp_threads > 1 && 2564 !ppc_type_check_compat(ms->cpu_type, CPU_POWERPC_LOGICAL_2_07, 0, 2565 spapr->max_compat_pvr)) { 2566 error_setg(errp, "TCG only supports SMT on POWER8 or newer CPUs"); 2567 return; 2568 } 2569 2570 if (smp_threads > 8) { 2571 error_setg(errp, "TCG cannot support more than 8 threads/core " 2572 "on a pseries machine"); 2573 return; 2574 } 2575 } 2576 if (!is_power_of_2(smp_threads)) { 2577 error_setg(errp, "Cannot support %d threads/core on a pseries " 2578 "machine because it must be a power of 2", smp_threads); 2579 return; 2580 } 2581 2582 /* Determine the VSMT mode to use: */ 2583 if (vsmt_user) { 2584 if (spapr->vsmt < smp_threads) { 2585 error_setg(errp, "Cannot support VSMT mode %d" 2586 " because it must be >= threads/core (%d)", 2587 spapr->vsmt, smp_threads); 2588 return; 2589 } 2590 /* In this case, spapr->vsmt has been set by the command line */ 2591 } else if (!smc->smp_threads_vsmt) { 2592 /* 2593 * Default VSMT value is tricky, because we need it to be as 2594 * consistent as possible (for migration), but this requires 2595 * changing it for at least some existing cases. We pick 8 as 2596 * the value that we'd get with KVM on POWER8, the 2597 * overwhelmingly common case in production systems. 2598 */ 2599 spapr->vsmt = MAX(8, smp_threads); 2600 } else { 2601 spapr->vsmt = smp_threads; 2602 } 2603 2604 /* KVM: If necessary, set the SMT mode: */ 2605 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2606 ret = kvmppc_set_smt_threads(spapr->vsmt); 2607 if (ret) { 2608 /* Looks like KVM isn't able to change VSMT mode */ 2609 error_setg(&local_err, 2610 "Failed to set KVM's VSMT mode to %d (errno %d)", 2611 spapr->vsmt, ret); 2612 /* We can live with that if the default one is big enough 2613 * for the number of threads, and a submultiple of the one 2614 * we want. In this case we'll waste some vcpu ids, but 2615 * behaviour will be correct */ 2616 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2617 warn_report_err(local_err); 2618 } else { 2619 if (!vsmt_user) { 2620 error_append_hint(&local_err, 2621 "On PPC, a VM with %d threads/core" 2622 " on a host with %d threads/core" 2623 " requires the use of VSMT mode %d.\n", 2624 smp_threads, kvm_smt, spapr->vsmt); 2625 } 2626 kvmppc_error_append_smt_possible_hint(&local_err); 2627 error_propagate(errp, local_err); 2628 } 2629 } 2630 } 2631 /* else TCG: nothing to do currently */ 2632 } 2633 2634 static void spapr_init_cpus(SpaprMachineState *spapr) 2635 { 2636 MachineState *machine = MACHINE(spapr); 2637 MachineClass *mc = MACHINE_GET_CLASS(machine); 2638 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2639 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2640 const CPUArchIdList *possible_cpus; 2641 unsigned int smp_cpus = machine->smp.cpus; 2642 unsigned int smp_threads = machine->smp.threads; 2643 unsigned int max_cpus = machine->smp.max_cpus; 2644 int boot_cores_nr = smp_cpus / smp_threads; 2645 int i; 2646 2647 possible_cpus = mc->possible_cpu_arch_ids(machine); 2648 if (mc->has_hotpluggable_cpus) { 2649 if (smp_cpus % smp_threads) { 2650 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2651 smp_cpus, smp_threads); 2652 exit(1); 2653 } 2654 if (max_cpus % smp_threads) { 2655 error_report("max_cpus (%u) must be multiple of threads (%u)", 2656 max_cpus, smp_threads); 2657 exit(1); 2658 } 2659 } else { 2660 if (max_cpus != smp_cpus) { 2661 error_report("This machine version does not support CPU hotplug"); 2662 exit(1); 2663 } 2664 boot_cores_nr = possible_cpus->len; 2665 } 2666 2667 if (smc->pre_2_10_has_unused_icps) { 2668 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2669 /* Dummy entries get deregistered when real ICPState objects 2670 * are registered during CPU core hotplug. 2671 */ 2672 pre_2_10_vmstate_register_dummy_icp(i); 2673 } 2674 } 2675 2676 for (i = 0; i < possible_cpus->len; i++) { 2677 int core_id = i * smp_threads; 2678 2679 if (mc->has_hotpluggable_cpus) { 2680 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2681 spapr_vcpu_id(spapr, core_id)); 2682 } 2683 2684 if (i < boot_cores_nr) { 2685 Object *core = object_new(type); 2686 int nr_threads = smp_threads; 2687 2688 /* Handle the partially filled core for older machine types */ 2689 if ((i + 1) * smp_threads >= smp_cpus) { 2690 nr_threads = smp_cpus - i * smp_threads; 2691 } 2692 2693 object_property_set_int(core, "nr-threads", nr_threads, 2694 &error_fatal); 2695 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2696 &error_fatal); 2697 qdev_realize(DEVICE(core), NULL, &error_fatal); 2698 2699 object_unref(core); 2700 } 2701 } 2702 } 2703 2704 static PCIHostState *spapr_create_default_phb(void) 2705 { 2706 DeviceState *dev; 2707 2708 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2709 qdev_prop_set_uint32(dev, "index", 0); 2710 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2711 2712 return PCI_HOST_BRIDGE(dev); 2713 } 2714 2715 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2716 { 2717 MachineState *machine = MACHINE(spapr); 2718 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2719 hwaddr rma_size = machine->ram_size; 2720 hwaddr node0_size = spapr_node0_size(machine); 2721 2722 /* RMA has to fit in the first NUMA node */ 2723 rma_size = MIN(rma_size, node0_size); 2724 2725 /* 2726 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2727 * never exceed that 2728 */ 2729 rma_size = MIN(rma_size, 1 * TiB); 2730 2731 /* 2732 * Clamp the RMA size based on machine type. This is for 2733 * migration compatibility with older qemu versions, which limited 2734 * the RMA size for complicated and mostly bad reasons. 2735 */ 2736 if (smc->rma_limit) { 2737 rma_size = MIN(rma_size, smc->rma_limit); 2738 } 2739 2740 if (rma_size < MIN_RMA_SLOF) { 2741 error_setg(errp, 2742 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2743 "ldMiB guest RMA (Real Mode Area memory)", 2744 MIN_RMA_SLOF / MiB); 2745 return 0; 2746 } 2747 2748 return rma_size; 2749 } 2750 2751 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2752 { 2753 MachineState *machine = MACHINE(spapr); 2754 int i; 2755 2756 for (i = 0; i < machine->ram_slots; i++) { 2757 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2758 } 2759 } 2760 2761 /* pSeries LPAR / sPAPR hardware init */ 2762 static void spapr_machine_init(MachineState *machine) 2763 { 2764 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2765 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2766 MachineClass *mc = MACHINE_GET_CLASS(machine); 2767 const char *bios_default = spapr->vof ? FW_FILE_NAME_VOF : FW_FILE_NAME; 2768 const char *bios_name = machine->firmware ?: bios_default; 2769 g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2770 const char *kernel_filename = machine->kernel_filename; 2771 const char *initrd_filename = machine->initrd_filename; 2772 PCIHostState *phb; 2773 bool has_vga; 2774 int i; 2775 MemoryRegion *sysmem = get_system_memory(); 2776 long load_limit, fw_size; 2777 Error *resize_hpt_err = NULL; 2778 2779 if (!filename) { 2780 error_report("Could not find LPAR firmware '%s'", bios_name); 2781 exit(1); 2782 } 2783 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2784 if (fw_size <= 0) { 2785 error_report("Could not load LPAR firmware '%s'", filename); 2786 exit(1); 2787 } 2788 2789 /* 2790 * if Secure VM (PEF) support is configured, then initialize it 2791 */ 2792 pef_kvm_init(machine->cgs, &error_fatal); 2793 2794 msi_nonbroken = true; 2795 2796 QLIST_INIT(&spapr->phbs); 2797 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2798 2799 /* Determine capabilities to run with */ 2800 spapr_caps_init(spapr); 2801 2802 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2803 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2804 /* 2805 * If the user explicitly requested a mode we should either 2806 * supply it, or fail completely (which we do below). But if 2807 * it's not set explicitly, we reset our mode to something 2808 * that works 2809 */ 2810 if (resize_hpt_err) { 2811 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2812 error_free(resize_hpt_err); 2813 resize_hpt_err = NULL; 2814 } else { 2815 spapr->resize_hpt = smc->resize_hpt_default; 2816 } 2817 } 2818 2819 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2820 2821 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2822 /* 2823 * User requested HPT resize, but this host can't supply it. Bail out 2824 */ 2825 error_report_err(resize_hpt_err); 2826 exit(1); 2827 } 2828 error_free(resize_hpt_err); 2829 2830 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2831 2832 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2833 load_limit = MIN(spapr->rma_size, FDT_MAX_ADDR) - FW_OVERHEAD; 2834 2835 /* 2836 * VSMT must be set in order to be able to compute VCPU ids, ie to 2837 * call spapr_max_server_number() or spapr_vcpu_id(). 2838 */ 2839 spapr_set_vsmt_mode(spapr, &error_fatal); 2840 2841 /* Set up Interrupt Controller before we create the VCPUs */ 2842 spapr_irq_init(spapr, &error_fatal); 2843 2844 /* Set up containers for ibm,client-architecture-support negotiated options 2845 */ 2846 spapr->ov5 = spapr_ovec_new(); 2847 spapr->ov5_cas = spapr_ovec_new(); 2848 2849 if (smc->dr_lmb_enabled) { 2850 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2851 spapr_validate_node_memory(machine, &error_fatal); 2852 } 2853 2854 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2855 2856 /* Do not advertise FORM2 NUMA support for pseries-6.1 and older */ 2857 if (!smc->pre_6_2_numa_affinity) { 2858 spapr_ovec_set(spapr->ov5, OV5_FORM2_AFFINITY); 2859 } 2860 2861 /* advertise support for dedicated HP event source to guests */ 2862 if (spapr->use_hotplug_event_source) { 2863 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2864 } 2865 2866 /* advertise support for HPT resizing */ 2867 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2868 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2869 } 2870 2871 /* advertise support for ibm,dyamic-memory-v2 */ 2872 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2873 2874 /* advertise XIVE on POWER9 machines */ 2875 if (spapr->irq->xive) { 2876 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2877 } 2878 2879 /* init CPUs */ 2880 spapr_init_cpus(spapr); 2881 2882 /* Init numa_assoc_array */ 2883 spapr_numa_associativity_init(spapr, machine); 2884 2885 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2886 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2887 spapr->max_compat_pvr)) { 2888 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2889 /* KVM and TCG always allow GTSE with radix... */ 2890 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2891 } 2892 /* ... but not with hash (currently). */ 2893 2894 if (kvm_enabled()) { 2895 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2896 kvmppc_enable_logical_ci_hcalls(); 2897 kvmppc_enable_set_mode_hcall(); 2898 2899 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2900 kvmppc_enable_clear_ref_mod_hcalls(); 2901 2902 /* Enable H_PAGE_INIT */ 2903 kvmppc_enable_h_page_init(); 2904 } 2905 2906 /* map RAM */ 2907 memory_region_add_subregion(sysmem, 0, machine->ram); 2908 2909 /* initialize hotplug memory address space */ 2910 if (machine->ram_size < machine->maxram_size) { 2911 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2912 hwaddr device_mem_base; 2913 2914 /* 2915 * Limit the number of hotpluggable memory slots to half the number 2916 * slots that KVM supports, leaving the other half for PCI and other 2917 * devices. However ensure that number of slots doesn't drop below 32. 2918 */ 2919 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2920 SPAPR_MAX_RAM_SLOTS; 2921 2922 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2923 max_memslots = SPAPR_MAX_RAM_SLOTS; 2924 } 2925 if (machine->ram_slots > max_memslots) { 2926 error_report("Specified number of memory slots %" 2927 PRIu64" exceeds max supported %d", 2928 machine->ram_slots, max_memslots); 2929 exit(1); 2930 } 2931 2932 device_mem_base = ROUND_UP(machine->ram_size, SPAPR_DEVICE_MEM_ALIGN); 2933 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 2934 } 2935 2936 if (smc->dr_lmb_enabled) { 2937 spapr_create_lmb_dr_connectors(spapr); 2938 } 2939 2940 if (mc->nvdimm_supported) { 2941 spapr_create_nvdimm_dr_connectors(spapr); 2942 } 2943 2944 /* Set up RTAS event infrastructure */ 2945 spapr_events_init(spapr); 2946 2947 /* Set up the RTC RTAS interfaces */ 2948 spapr_rtc_create(spapr); 2949 2950 /* Set up VIO bus */ 2951 spapr->vio_bus = spapr_vio_bus_init(); 2952 2953 for (i = 0; serial_hd(i); i++) { 2954 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2955 } 2956 2957 /* We always have at least the nvram device on VIO */ 2958 spapr_create_nvram(spapr); 2959 2960 /* 2961 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2962 * connectors (described in root DT node's "ibm,drc-types" property) 2963 * are pre-initialized here. additional child connectors (such as 2964 * connectors for a PHBs PCI slots) are added as needed during their 2965 * parent's realization. 2966 */ 2967 if (smc->dr_phb_enabled) { 2968 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2969 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2970 } 2971 } 2972 2973 /* Set up PCI */ 2974 spapr_pci_rtas_init(); 2975 2976 phb = spapr_create_default_phb(); 2977 2978 for (i = 0; i < nb_nics; i++) { 2979 NICInfo *nd = &nd_table[i]; 2980 2981 if (!nd->model) { 2982 nd->model = g_strdup("spapr-vlan"); 2983 } 2984 2985 if (g_str_equal(nd->model, "spapr-vlan") || 2986 g_str_equal(nd->model, "ibmveth")) { 2987 spapr_vlan_create(spapr->vio_bus, nd); 2988 } else { 2989 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2990 } 2991 } 2992 2993 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2994 spapr_vscsi_create(spapr->vio_bus); 2995 } 2996 2997 /* Graphics */ 2998 has_vga = spapr_vga_init(phb->bus, &error_fatal); 2999 if (has_vga) { 3000 spapr->want_stdout_path = !machine->enable_graphics; 3001 machine->usb |= defaults_enabled() && !machine->usb_disabled; 3002 } else { 3003 spapr->want_stdout_path = true; 3004 } 3005 3006 if (machine->usb) { 3007 if (smc->use_ohci_by_default) { 3008 pci_create_simple(phb->bus, -1, "pci-ohci"); 3009 } else { 3010 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 3011 } 3012 3013 if (has_vga) { 3014 USBBus *usb_bus = usb_bus_find(-1); 3015 3016 usb_create_simple(usb_bus, "usb-kbd"); 3017 usb_create_simple(usb_bus, "usb-mouse"); 3018 } 3019 } 3020 3021 if (kernel_filename) { 3022 uint64_t loaded_addr = 0; 3023 3024 spapr->kernel_size = load_elf(kernel_filename, NULL, 3025 translate_kernel_address, spapr, 3026 NULL, &loaded_addr, NULL, NULL, 1, 3027 PPC_ELF_MACHINE, 0, 0); 3028 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 3029 spapr->kernel_size = load_elf(kernel_filename, NULL, 3030 translate_kernel_address, spapr, 3031 NULL, &loaded_addr, NULL, NULL, 0, 3032 PPC_ELF_MACHINE, 0, 0); 3033 spapr->kernel_le = spapr->kernel_size > 0; 3034 } 3035 if (spapr->kernel_size < 0) { 3036 error_report("error loading %s: %s", kernel_filename, 3037 load_elf_strerror(spapr->kernel_size)); 3038 exit(1); 3039 } 3040 3041 if (spapr->kernel_addr != loaded_addr) { 3042 warn_report("spapr: kernel_addr changed from 0x%"PRIx64 3043 " to 0x%"PRIx64, 3044 spapr->kernel_addr, loaded_addr); 3045 spapr->kernel_addr = loaded_addr; 3046 } 3047 3048 /* load initrd */ 3049 if (initrd_filename) { 3050 /* Try to locate the initrd in the gap between the kernel 3051 * and the firmware. Add a bit of space just in case 3052 */ 3053 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 3054 + 0x1ffff) & ~0xffff; 3055 spapr->initrd_size = load_image_targphys(initrd_filename, 3056 spapr->initrd_base, 3057 load_limit 3058 - spapr->initrd_base); 3059 if (spapr->initrd_size < 0) { 3060 error_report("could not load initial ram disk '%s'", 3061 initrd_filename); 3062 exit(1); 3063 } 3064 } 3065 } 3066 3067 /* FIXME: Should register things through the MachineState's qdev 3068 * interface, this is a legacy from the sPAPREnvironment structure 3069 * which predated MachineState but had a similar function */ 3070 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3071 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3072 &savevm_htab_handlers, spapr); 3073 3074 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 3075 3076 qemu_register_boot_set(spapr_boot_set, spapr); 3077 3078 /* 3079 * Nothing needs to be done to resume a suspended guest because 3080 * suspending does not change the machine state, so no need for 3081 * a ->wakeup method. 3082 */ 3083 qemu_register_wakeup_support(); 3084 3085 if (kvm_enabled()) { 3086 /* to stop and start vmclock */ 3087 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3088 &spapr->tb); 3089 3090 kvmppc_spapr_enable_inkernel_multitce(); 3091 } 3092 3093 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3094 if (spapr->vof) { 3095 spapr->vof->fw_size = fw_size; /* for claim() on itself */ 3096 spapr_register_hypercall(KVMPPC_H_VOF_CLIENT, spapr_h_vof_client); 3097 } 3098 3099 spapr_watchdog_init(spapr); 3100 } 3101 3102 #define DEFAULT_KVM_TYPE "auto" 3103 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3104 { 3105 /* 3106 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3107 * accommodate the 'HV' and 'PV' formats that exists in the 3108 * wild. The 'auto' mode is being introduced already as 3109 * lower-case, thus we don't need to bother checking for 3110 * "AUTO". 3111 */ 3112 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3113 return 0; 3114 } 3115 3116 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3117 return 1; 3118 } 3119 3120 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3121 return 2; 3122 } 3123 3124 error_report("Unknown kvm-type specified '%s'", vm_type); 3125 return -1; 3126 } 3127 3128 /* 3129 * Implementation of an interface to adjust firmware path 3130 * for the bootindex property handling. 3131 */ 3132 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3133 DeviceState *dev) 3134 { 3135 #define CAST(type, obj, name) \ 3136 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3137 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3138 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3139 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3140 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3141 3142 if (d && bus) { 3143 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3144 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3145 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3146 3147 if (spapr) { 3148 /* 3149 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3150 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3151 * 0x8000 | (target << 8) | (bus << 5) | lun 3152 * (see the "Logical unit addressing format" table in SAM5) 3153 */ 3154 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3155 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3156 (uint64_t)id << 48); 3157 } else if (virtio) { 3158 /* 3159 * We use SRP luns of the form 01000000 | (target << 8) | lun 3160 * in the top 32 bits of the 64-bit LUN 3161 * Note: the quote above is from SLOF and it is wrong, 3162 * the actual binding is: 3163 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3164 */ 3165 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3166 if (d->lun >= 256) { 3167 /* Use the LUN "flat space addressing method" */ 3168 id |= 0x4000; 3169 } 3170 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3171 (uint64_t)id << 32); 3172 } else if (usb) { 3173 /* 3174 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3175 * in the top 32 bits of the 64-bit LUN 3176 */ 3177 unsigned usb_port = atoi(usb->port->path); 3178 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3179 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3180 (uint64_t)id << 32); 3181 } 3182 } 3183 3184 /* 3185 * SLOF probes the USB devices, and if it recognizes that the device is a 3186 * storage device, it changes its name to "storage" instead of "usb-host", 3187 * and additionally adds a child node for the SCSI LUN, so the correct 3188 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3189 */ 3190 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3191 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3192 if (usb_device_is_scsi_storage(usbdev)) { 3193 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3194 } 3195 } 3196 3197 if (phb) { 3198 /* Replace "pci" with "pci@800000020000000" */ 3199 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3200 } 3201 3202 if (vsc) { 3203 /* Same logic as virtio above */ 3204 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3205 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3206 } 3207 3208 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3209 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3210 PCIDevice *pdev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3211 return g_strdup_printf("pci@%x", PCI_SLOT(pdev->devfn)); 3212 } 3213 3214 if (pcidev) { 3215 return spapr_pci_fw_dev_name(pcidev); 3216 } 3217 3218 return NULL; 3219 } 3220 3221 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3222 { 3223 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3224 3225 return g_strdup(spapr->kvm_type); 3226 } 3227 3228 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3229 { 3230 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3231 3232 g_free(spapr->kvm_type); 3233 spapr->kvm_type = g_strdup(value); 3234 } 3235 3236 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3237 { 3238 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3239 3240 return spapr->use_hotplug_event_source; 3241 } 3242 3243 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3244 Error **errp) 3245 { 3246 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3247 3248 spapr->use_hotplug_event_source = value; 3249 } 3250 3251 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3252 { 3253 return true; 3254 } 3255 3256 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3257 { 3258 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3259 3260 switch (spapr->resize_hpt) { 3261 case SPAPR_RESIZE_HPT_DEFAULT: 3262 return g_strdup("default"); 3263 case SPAPR_RESIZE_HPT_DISABLED: 3264 return g_strdup("disabled"); 3265 case SPAPR_RESIZE_HPT_ENABLED: 3266 return g_strdup("enabled"); 3267 case SPAPR_RESIZE_HPT_REQUIRED: 3268 return g_strdup("required"); 3269 } 3270 g_assert_not_reached(); 3271 } 3272 3273 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3274 { 3275 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3276 3277 if (strcmp(value, "default") == 0) { 3278 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3279 } else if (strcmp(value, "disabled") == 0) { 3280 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3281 } else if (strcmp(value, "enabled") == 0) { 3282 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3283 } else if (strcmp(value, "required") == 0) { 3284 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3285 } else { 3286 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3287 } 3288 } 3289 3290 static bool spapr_get_vof(Object *obj, Error **errp) 3291 { 3292 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3293 3294 return spapr->vof != NULL; 3295 } 3296 3297 static void spapr_set_vof(Object *obj, bool value, Error **errp) 3298 { 3299 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3300 3301 if (spapr->vof) { 3302 vof_cleanup(spapr->vof); 3303 g_free(spapr->vof); 3304 spapr->vof = NULL; 3305 } 3306 if (!value) { 3307 return; 3308 } 3309 spapr->vof = g_malloc0(sizeof(*spapr->vof)); 3310 } 3311 3312 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3313 { 3314 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3315 3316 if (spapr->irq == &spapr_irq_xics_legacy) { 3317 return g_strdup("legacy"); 3318 } else if (spapr->irq == &spapr_irq_xics) { 3319 return g_strdup("xics"); 3320 } else if (spapr->irq == &spapr_irq_xive) { 3321 return g_strdup("xive"); 3322 } else if (spapr->irq == &spapr_irq_dual) { 3323 return g_strdup("dual"); 3324 } 3325 g_assert_not_reached(); 3326 } 3327 3328 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3329 { 3330 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3331 3332 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3333 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3334 return; 3335 } 3336 3337 /* The legacy IRQ backend can not be set */ 3338 if (strcmp(value, "xics") == 0) { 3339 spapr->irq = &spapr_irq_xics; 3340 } else if (strcmp(value, "xive") == 0) { 3341 spapr->irq = &spapr_irq_xive; 3342 } else if (strcmp(value, "dual") == 0) { 3343 spapr->irq = &spapr_irq_dual; 3344 } else { 3345 error_setg(errp, "Bad value for \"ic-mode\" property"); 3346 } 3347 } 3348 3349 static char *spapr_get_host_model(Object *obj, Error **errp) 3350 { 3351 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3352 3353 return g_strdup(spapr->host_model); 3354 } 3355 3356 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3357 { 3358 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3359 3360 g_free(spapr->host_model); 3361 spapr->host_model = g_strdup(value); 3362 } 3363 3364 static char *spapr_get_host_serial(Object *obj, Error **errp) 3365 { 3366 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3367 3368 return g_strdup(spapr->host_serial); 3369 } 3370 3371 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3372 { 3373 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3374 3375 g_free(spapr->host_serial); 3376 spapr->host_serial = g_strdup(value); 3377 } 3378 3379 static void spapr_instance_init(Object *obj) 3380 { 3381 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3382 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3383 MachineState *ms = MACHINE(spapr); 3384 MachineClass *mc = MACHINE_GET_CLASS(ms); 3385 3386 /* 3387 * NVDIMM support went live in 5.1 without considering that, in 3388 * other archs, the user needs to enable NVDIMM support with the 3389 * 'nvdimm' machine option and the default behavior is NVDIMM 3390 * support disabled. It is too late to roll back to the standard 3391 * behavior without breaking 5.1 guests. 3392 */ 3393 if (mc->nvdimm_supported) { 3394 ms->nvdimms_state->is_enabled = true; 3395 } 3396 3397 spapr->htab_fd = -1; 3398 spapr->use_hotplug_event_source = true; 3399 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3400 object_property_add_str(obj, "kvm-type", 3401 spapr_get_kvm_type, spapr_set_kvm_type); 3402 object_property_set_description(obj, "kvm-type", 3403 "Specifies the KVM virtualization mode (auto," 3404 " hv, pr). Defaults to 'auto'. This mode will use" 3405 " any available KVM module loaded in the host," 3406 " where kvm_hv takes precedence if both kvm_hv and" 3407 " kvm_pr are loaded."); 3408 object_property_add_bool(obj, "modern-hotplug-events", 3409 spapr_get_modern_hotplug_events, 3410 spapr_set_modern_hotplug_events); 3411 object_property_set_description(obj, "modern-hotplug-events", 3412 "Use dedicated hotplug event mechanism in" 3413 " place of standard EPOW events when possible" 3414 " (required for memory hot-unplug support)"); 3415 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3416 "Maximum permitted CPU compatibility mode"); 3417 3418 object_property_add_str(obj, "resize-hpt", 3419 spapr_get_resize_hpt, spapr_set_resize_hpt); 3420 object_property_set_description(obj, "resize-hpt", 3421 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3422 object_property_add_uint32_ptr(obj, "vsmt", 3423 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3424 object_property_set_description(obj, "vsmt", 3425 "Virtual SMT: KVM behaves as if this were" 3426 " the host's SMT mode"); 3427 3428 object_property_add_bool(obj, "vfio-no-msix-emulation", 3429 spapr_get_msix_emulation, NULL); 3430 3431 object_property_add_uint64_ptr(obj, "kernel-addr", 3432 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3433 object_property_set_description(obj, "kernel-addr", 3434 stringify(KERNEL_LOAD_ADDR) 3435 " for -kernel is the default"); 3436 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3437 3438 object_property_add_bool(obj, "x-vof", spapr_get_vof, spapr_set_vof); 3439 object_property_set_description(obj, "x-vof", 3440 "Enable Virtual Open Firmware (experimental)"); 3441 3442 /* The machine class defines the default interrupt controller mode */ 3443 spapr->irq = smc->irq; 3444 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3445 spapr_set_ic_mode); 3446 object_property_set_description(obj, "ic-mode", 3447 "Specifies the interrupt controller mode (xics, xive, dual)"); 3448 3449 object_property_add_str(obj, "host-model", 3450 spapr_get_host_model, spapr_set_host_model); 3451 object_property_set_description(obj, "host-model", 3452 "Host model to advertise in guest device tree"); 3453 object_property_add_str(obj, "host-serial", 3454 spapr_get_host_serial, spapr_set_host_serial); 3455 object_property_set_description(obj, "host-serial", 3456 "Host serial number to advertise in guest device tree"); 3457 } 3458 3459 static void spapr_machine_finalizefn(Object *obj) 3460 { 3461 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3462 3463 g_free(spapr->kvm_type); 3464 } 3465 3466 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3467 { 3468 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3469 PowerPCCPU *cpu = POWERPC_CPU(cs); 3470 CPUPPCState *env = &cpu->env; 3471 3472 cpu_synchronize_state(cs); 3473 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3474 if (spapr->fwnmi_system_reset_addr != -1) { 3475 uint64_t rtas_addr, addr; 3476 3477 /* get rtas addr from fdt */ 3478 rtas_addr = spapr_get_rtas_addr(); 3479 if (!rtas_addr) { 3480 qemu_system_guest_panicked(NULL); 3481 return; 3482 } 3483 3484 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3485 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3486 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3487 env->gpr[3] = addr; 3488 } 3489 ppc_cpu_do_system_reset(cs); 3490 if (spapr->fwnmi_system_reset_addr != -1) { 3491 env->nip = spapr->fwnmi_system_reset_addr; 3492 } 3493 } 3494 3495 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3496 { 3497 CPUState *cs; 3498 3499 CPU_FOREACH(cs) { 3500 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3501 } 3502 } 3503 3504 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3505 void *fdt, int *fdt_start_offset, Error **errp) 3506 { 3507 uint64_t addr; 3508 uint32_t node; 3509 3510 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3511 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3512 &error_abort); 3513 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3514 SPAPR_MEMORY_BLOCK_SIZE); 3515 return 0; 3516 } 3517 3518 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3519 bool dedicated_hp_event_source) 3520 { 3521 SpaprDrc *drc; 3522 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3523 int i; 3524 uint64_t addr = addr_start; 3525 bool hotplugged = spapr_drc_hotplugged(dev); 3526 3527 for (i = 0; i < nr_lmbs; i++) { 3528 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3529 addr / SPAPR_MEMORY_BLOCK_SIZE); 3530 g_assert(drc); 3531 3532 /* 3533 * memory_device_get_free_addr() provided a range of free addresses 3534 * that doesn't overlap with any existing mapping at pre-plug. The 3535 * corresponding LMB DRCs are thus assumed to be all attachable. 3536 */ 3537 spapr_drc_attach(drc, dev); 3538 if (!hotplugged) { 3539 spapr_drc_reset(drc); 3540 } 3541 addr += SPAPR_MEMORY_BLOCK_SIZE; 3542 } 3543 /* send hotplug notification to the 3544 * guest only in case of hotplugged memory 3545 */ 3546 if (hotplugged) { 3547 if (dedicated_hp_event_source) { 3548 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3549 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3550 g_assert(drc); 3551 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3552 nr_lmbs, 3553 spapr_drc_index(drc)); 3554 } else { 3555 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3556 nr_lmbs); 3557 } 3558 } 3559 } 3560 3561 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3562 { 3563 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3564 PCDIMMDevice *dimm = PC_DIMM(dev); 3565 uint64_t size, addr; 3566 int64_t slot; 3567 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3568 3569 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3570 3571 pc_dimm_plug(dimm, MACHINE(ms)); 3572 3573 if (!is_nvdimm) { 3574 addr = object_property_get_uint(OBJECT(dimm), 3575 PC_DIMM_ADDR_PROP, &error_abort); 3576 spapr_add_lmbs(dev, addr, size, 3577 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3578 } else { 3579 slot = object_property_get_int(OBJECT(dimm), 3580 PC_DIMM_SLOT_PROP, &error_abort); 3581 /* We should have valid slot number at this point */ 3582 g_assert(slot >= 0); 3583 spapr_add_nvdimm(dev, slot); 3584 } 3585 } 3586 3587 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3588 Error **errp) 3589 { 3590 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3591 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3592 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3593 PCDIMMDevice *dimm = PC_DIMM(dev); 3594 Error *local_err = NULL; 3595 uint64_t size; 3596 Object *memdev; 3597 hwaddr pagesize; 3598 3599 if (!smc->dr_lmb_enabled) { 3600 error_setg(errp, "Memory hotplug not supported for this machine"); 3601 return; 3602 } 3603 3604 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3605 if (local_err) { 3606 error_propagate(errp, local_err); 3607 return; 3608 } 3609 3610 if (is_nvdimm) { 3611 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3612 return; 3613 } 3614 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3615 error_setg(errp, "Hotplugged memory size must be a multiple of " 3616 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3617 return; 3618 } 3619 3620 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3621 &error_abort); 3622 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3623 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3624 return; 3625 } 3626 3627 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3628 } 3629 3630 struct SpaprDimmState { 3631 PCDIMMDevice *dimm; 3632 uint32_t nr_lmbs; 3633 QTAILQ_ENTRY(SpaprDimmState) next; 3634 }; 3635 3636 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3637 PCDIMMDevice *dimm) 3638 { 3639 SpaprDimmState *dimm_state = NULL; 3640 3641 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3642 if (dimm_state->dimm == dimm) { 3643 break; 3644 } 3645 } 3646 return dimm_state; 3647 } 3648 3649 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3650 uint32_t nr_lmbs, 3651 PCDIMMDevice *dimm) 3652 { 3653 SpaprDimmState *ds = NULL; 3654 3655 /* 3656 * If this request is for a DIMM whose removal had failed earlier 3657 * (due to guest's refusal to remove the LMBs), we would have this 3658 * dimm already in the pending_dimm_unplugs list. In that 3659 * case don't add again. 3660 */ 3661 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3662 if (!ds) { 3663 ds = g_new0(SpaprDimmState, 1); 3664 ds->nr_lmbs = nr_lmbs; 3665 ds->dimm = dimm; 3666 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3667 } 3668 return ds; 3669 } 3670 3671 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3672 SpaprDimmState *dimm_state) 3673 { 3674 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3675 g_free(dimm_state); 3676 } 3677 3678 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3679 PCDIMMDevice *dimm) 3680 { 3681 SpaprDrc *drc; 3682 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3683 &error_abort); 3684 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3685 uint32_t avail_lmbs = 0; 3686 uint64_t addr_start, addr; 3687 int i; 3688 3689 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3690 &error_abort); 3691 3692 addr = addr_start; 3693 for (i = 0; i < nr_lmbs; i++) { 3694 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3695 addr / SPAPR_MEMORY_BLOCK_SIZE); 3696 g_assert(drc); 3697 if (drc->dev) { 3698 avail_lmbs++; 3699 } 3700 addr += SPAPR_MEMORY_BLOCK_SIZE; 3701 } 3702 3703 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3704 } 3705 3706 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev) 3707 { 3708 SpaprDimmState *ds; 3709 PCDIMMDevice *dimm; 3710 SpaprDrc *drc; 3711 uint32_t nr_lmbs; 3712 uint64_t size, addr_start, addr; 3713 g_autofree char *qapi_error = NULL; 3714 int i; 3715 3716 if (!dev) { 3717 return; 3718 } 3719 3720 dimm = PC_DIMM(dev); 3721 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3722 3723 /* 3724 * 'ds == NULL' would mean that the DIMM doesn't have a pending 3725 * unplug state, but one of its DRC is marked as unplug_requested. 3726 * This is bad and weird enough to g_assert() out. 3727 */ 3728 g_assert(ds); 3729 3730 spapr_pending_dimm_unplugs_remove(spapr, ds); 3731 3732 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3733 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3734 3735 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3736 &error_abort); 3737 3738 addr = addr_start; 3739 for (i = 0; i < nr_lmbs; i++) { 3740 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3741 addr / SPAPR_MEMORY_BLOCK_SIZE); 3742 g_assert(drc); 3743 3744 drc->unplug_requested = false; 3745 addr += SPAPR_MEMORY_BLOCK_SIZE; 3746 } 3747 3748 /* 3749 * Tell QAPI that something happened and the memory 3750 * hotunplug wasn't successful. Keep sending 3751 * MEM_UNPLUG_ERROR even while sending 3752 * DEVICE_UNPLUG_GUEST_ERROR until the deprecation of 3753 * MEM_UNPLUG_ERROR is due. 3754 */ 3755 qapi_error = g_strdup_printf("Memory hotunplug rejected by the guest " 3756 "for device %s", dev->id); 3757 3758 qapi_event_send_mem_unplug_error(dev->id ? : "", qapi_error); 3759 3760 qapi_event_send_device_unplug_guest_error(dev->id, 3761 dev->canonical_path); 3762 } 3763 3764 /* Callback to be called during DRC release. */ 3765 void spapr_lmb_release(DeviceState *dev) 3766 { 3767 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3768 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3769 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3770 3771 /* This information will get lost if a migration occurs 3772 * during the unplug process. In this case recover it. */ 3773 if (ds == NULL) { 3774 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3775 g_assert(ds); 3776 /* The DRC being examined by the caller at least must be counted */ 3777 g_assert(ds->nr_lmbs); 3778 } 3779 3780 if (--ds->nr_lmbs) { 3781 return; 3782 } 3783 3784 /* 3785 * Now that all the LMBs have been removed by the guest, call the 3786 * unplug handler chain. This can never fail. 3787 */ 3788 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3789 object_unparent(OBJECT(dev)); 3790 } 3791 3792 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3793 { 3794 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3795 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3796 3797 /* We really shouldn't get this far without anything to unplug */ 3798 g_assert(ds); 3799 3800 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3801 qdev_unrealize(dev); 3802 spapr_pending_dimm_unplugs_remove(spapr, ds); 3803 } 3804 3805 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3806 DeviceState *dev, Error **errp) 3807 { 3808 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3809 PCDIMMDevice *dimm = PC_DIMM(dev); 3810 uint32_t nr_lmbs; 3811 uint64_t size, addr_start, addr; 3812 int i; 3813 SpaprDrc *drc; 3814 3815 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3816 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3817 return; 3818 } 3819 3820 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3821 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3822 3823 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3824 &error_abort); 3825 3826 /* 3827 * An existing pending dimm state for this DIMM means that there is an 3828 * unplug operation in progress, waiting for the spapr_lmb_release 3829 * callback to complete the job (BQL can't cover that far). In this case, 3830 * bail out to avoid detaching DRCs that were already released. 3831 */ 3832 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3833 error_setg(errp, "Memory unplug already in progress for device %s", 3834 dev->id); 3835 return; 3836 } 3837 3838 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3839 3840 addr = addr_start; 3841 for (i = 0; i < nr_lmbs; i++) { 3842 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3843 addr / SPAPR_MEMORY_BLOCK_SIZE); 3844 g_assert(drc); 3845 3846 spapr_drc_unplug_request(drc); 3847 addr += SPAPR_MEMORY_BLOCK_SIZE; 3848 } 3849 3850 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3851 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3852 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3853 nr_lmbs, spapr_drc_index(drc)); 3854 } 3855 3856 /* Callback to be called during DRC release. */ 3857 void spapr_core_release(DeviceState *dev) 3858 { 3859 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3860 3861 /* Call the unplug handler chain. This can never fail. */ 3862 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3863 object_unparent(OBJECT(dev)); 3864 } 3865 3866 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3867 { 3868 MachineState *ms = MACHINE(hotplug_dev); 3869 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3870 CPUCore *cc = CPU_CORE(dev); 3871 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3872 3873 if (smc->pre_2_10_has_unused_icps) { 3874 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3875 int i; 3876 3877 for (i = 0; i < cc->nr_threads; i++) { 3878 CPUState *cs = CPU(sc->threads[i]); 3879 3880 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3881 } 3882 } 3883 3884 assert(core_slot); 3885 core_slot->cpu = NULL; 3886 qdev_unrealize(dev); 3887 } 3888 3889 static 3890 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3891 Error **errp) 3892 { 3893 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3894 int index; 3895 SpaprDrc *drc; 3896 CPUCore *cc = CPU_CORE(dev); 3897 3898 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3899 error_setg(errp, "Unable to find CPU core with core-id: %d", 3900 cc->core_id); 3901 return; 3902 } 3903 if (index == 0) { 3904 error_setg(errp, "Boot CPU core may not be unplugged"); 3905 return; 3906 } 3907 3908 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3909 spapr_vcpu_id(spapr, cc->core_id)); 3910 g_assert(drc); 3911 3912 if (!spapr_drc_unplug_requested(drc)) { 3913 spapr_drc_unplug_request(drc); 3914 } 3915 3916 /* 3917 * spapr_hotplug_req_remove_by_index is left unguarded, out of the 3918 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ 3919 * pulses removing the same CPU. Otherwise, in an failed hotunplug 3920 * attempt (e.g. the kernel will refuse to remove the last online 3921 * CPU), we will never attempt it again because unplug_requested 3922 * will still be 'true' in that case. 3923 */ 3924 spapr_hotplug_req_remove_by_index(drc); 3925 } 3926 3927 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3928 void *fdt, int *fdt_start_offset, Error **errp) 3929 { 3930 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3931 CPUState *cs = CPU(core->threads[0]); 3932 PowerPCCPU *cpu = POWERPC_CPU(cs); 3933 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3934 int id = spapr_get_vcpu_id(cpu); 3935 g_autofree char *nodename = NULL; 3936 int offset; 3937 3938 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3939 offset = fdt_add_subnode(fdt, 0, nodename); 3940 3941 spapr_dt_cpu(cs, fdt, offset, spapr); 3942 3943 /* 3944 * spapr_dt_cpu() does not fill the 'name' property in the 3945 * CPU node. The function is called during boot process, before 3946 * and after CAS, and overwriting the 'name' property written 3947 * by SLOF is not allowed. 3948 * 3949 * Write it manually after spapr_dt_cpu(). This makes the hotplug 3950 * CPUs more compatible with the coldplugged ones, which have 3951 * the 'name' property. Linux Kernel also relies on this 3952 * property to identify CPU nodes. 3953 */ 3954 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 3955 3956 *fdt_start_offset = offset; 3957 return 0; 3958 } 3959 3960 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3961 { 3962 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3963 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3964 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3965 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3966 CPUCore *cc = CPU_CORE(dev); 3967 CPUState *cs; 3968 SpaprDrc *drc; 3969 CPUArchId *core_slot; 3970 int index; 3971 bool hotplugged = spapr_drc_hotplugged(dev); 3972 int i; 3973 3974 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3975 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 3976 3977 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3978 spapr_vcpu_id(spapr, cc->core_id)); 3979 3980 g_assert(drc || !mc->has_hotpluggable_cpus); 3981 3982 if (drc) { 3983 /* 3984 * spapr_core_pre_plug() already buys us this is a brand new 3985 * core being plugged into a free slot. Nothing should already 3986 * be attached to the corresponding DRC. 3987 */ 3988 spapr_drc_attach(drc, dev); 3989 3990 if (hotplugged) { 3991 /* 3992 * Send hotplug notification interrupt to the guest only 3993 * in case of hotplugged CPUs. 3994 */ 3995 spapr_hotplug_req_add_by_index(drc); 3996 } else { 3997 spapr_drc_reset(drc); 3998 } 3999 } 4000 4001 core_slot->cpu = OBJECT(dev); 4002 4003 /* 4004 * Set compatibility mode to match the boot CPU, which was either set 4005 * by the machine reset code or by CAS. This really shouldn't fail at 4006 * this point. 4007 */ 4008 if (hotplugged) { 4009 for (i = 0; i < cc->nr_threads; i++) { 4010 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 4011 &error_abort); 4012 } 4013 } 4014 4015 if (smc->pre_2_10_has_unused_icps) { 4016 for (i = 0; i < cc->nr_threads; i++) { 4017 cs = CPU(core->threads[i]); 4018 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 4019 } 4020 } 4021 } 4022 4023 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4024 Error **errp) 4025 { 4026 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 4027 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 4028 CPUCore *cc = CPU_CORE(dev); 4029 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 4030 const char *type = object_get_typename(OBJECT(dev)); 4031 CPUArchId *core_slot; 4032 int index; 4033 unsigned int smp_threads = machine->smp.threads; 4034 4035 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 4036 error_setg(errp, "CPU hotplug not supported for this machine"); 4037 return; 4038 } 4039 4040 if (strcmp(base_core_type, type)) { 4041 error_setg(errp, "CPU core type should be %s", base_core_type); 4042 return; 4043 } 4044 4045 if (cc->core_id % smp_threads) { 4046 error_setg(errp, "invalid core id %d", cc->core_id); 4047 return; 4048 } 4049 4050 /* 4051 * In general we should have homogeneous threads-per-core, but old 4052 * (pre hotplug support) machine types allow the last core to have 4053 * reduced threads as a compatibility hack for when we allowed 4054 * total vcpus not a multiple of threads-per-core. 4055 */ 4056 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 4057 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 4058 smp_threads); 4059 return; 4060 } 4061 4062 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 4063 if (!core_slot) { 4064 error_setg(errp, "core id %d out of range", cc->core_id); 4065 return; 4066 } 4067 4068 if (core_slot->cpu) { 4069 error_setg(errp, "core %d already populated", cc->core_id); 4070 return; 4071 } 4072 4073 numa_cpu_pre_plug(core_slot, dev, errp); 4074 } 4075 4076 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 4077 void *fdt, int *fdt_start_offset, Error **errp) 4078 { 4079 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 4080 int intc_phandle; 4081 4082 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 4083 if (intc_phandle <= 0) { 4084 return -1; 4085 } 4086 4087 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 4088 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 4089 return -1; 4090 } 4091 4092 /* generally SLOF creates these, for hotplug it's up to QEMU */ 4093 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 4094 4095 return 0; 4096 } 4097 4098 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4099 Error **errp) 4100 { 4101 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4102 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4103 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4104 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 4105 SpaprDrc *drc; 4106 4107 if (dev->hotplugged && !smc->dr_phb_enabled) { 4108 error_setg(errp, "PHB hotplug not supported for this machine"); 4109 return false; 4110 } 4111 4112 if (sphb->index == (uint32_t)-1) { 4113 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 4114 return false; 4115 } 4116 4117 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4118 if (drc && drc->dev) { 4119 error_setg(errp, "PHB %d already attached", sphb->index); 4120 return false; 4121 } 4122 4123 /* 4124 * This will check that sphb->index doesn't exceed the maximum number of 4125 * PHBs for the current machine type. 4126 */ 4127 return 4128 smc->phb_placement(spapr, sphb->index, 4129 &sphb->buid, &sphb->io_win_addr, 4130 &sphb->mem_win_addr, &sphb->mem64_win_addr, 4131 windows_supported, sphb->dma_liobn, 4132 errp); 4133 } 4134 4135 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4136 { 4137 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4138 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4139 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4140 SpaprDrc *drc; 4141 bool hotplugged = spapr_drc_hotplugged(dev); 4142 4143 if (!smc->dr_phb_enabled) { 4144 return; 4145 } 4146 4147 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4148 /* hotplug hooks should check it's enabled before getting this far */ 4149 assert(drc); 4150 4151 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 4152 spapr_drc_attach(drc, dev); 4153 4154 if (hotplugged) { 4155 spapr_hotplug_req_add_by_index(drc); 4156 } else { 4157 spapr_drc_reset(drc); 4158 } 4159 } 4160 4161 void spapr_phb_release(DeviceState *dev) 4162 { 4163 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4164 4165 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4166 object_unparent(OBJECT(dev)); 4167 } 4168 4169 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4170 { 4171 qdev_unrealize(dev); 4172 } 4173 4174 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4175 DeviceState *dev, Error **errp) 4176 { 4177 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4178 SpaprDrc *drc; 4179 4180 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4181 assert(drc); 4182 4183 if (!spapr_drc_unplug_requested(drc)) { 4184 spapr_drc_unplug_request(drc); 4185 spapr_hotplug_req_remove_by_index(drc); 4186 } else { 4187 error_setg(errp, 4188 "PCI Host Bridge unplug already in progress for device %s", 4189 dev->id); 4190 } 4191 } 4192 4193 static 4194 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4195 Error **errp) 4196 { 4197 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4198 4199 if (spapr->tpm_proxy != NULL) { 4200 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4201 return false; 4202 } 4203 4204 return true; 4205 } 4206 4207 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4208 { 4209 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4210 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4211 4212 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4213 g_assert(spapr->tpm_proxy == NULL); 4214 4215 spapr->tpm_proxy = tpm_proxy; 4216 } 4217 4218 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4219 { 4220 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4221 4222 qdev_unrealize(dev); 4223 object_unparent(OBJECT(dev)); 4224 spapr->tpm_proxy = NULL; 4225 } 4226 4227 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4228 DeviceState *dev, Error **errp) 4229 { 4230 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4231 spapr_memory_plug(hotplug_dev, dev); 4232 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4233 spapr_core_plug(hotplug_dev, dev); 4234 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4235 spapr_phb_plug(hotplug_dev, dev); 4236 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4237 spapr_tpm_proxy_plug(hotplug_dev, dev); 4238 } 4239 } 4240 4241 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4242 DeviceState *dev, Error **errp) 4243 { 4244 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4245 spapr_memory_unplug(hotplug_dev, dev); 4246 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4247 spapr_core_unplug(hotplug_dev, dev); 4248 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4249 spapr_phb_unplug(hotplug_dev, dev); 4250 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4251 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4252 } 4253 } 4254 4255 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4256 { 4257 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4258 /* 4259 * CAS will process all pending unplug requests. 4260 * 4261 * HACK: a guest could theoretically have cleared all bits in OV5, 4262 * but none of the guests we care for do. 4263 */ 4264 spapr_ovec_empty(spapr->ov5_cas); 4265 } 4266 4267 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4268 DeviceState *dev, Error **errp) 4269 { 4270 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4271 MachineClass *mc = MACHINE_GET_CLASS(sms); 4272 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4273 4274 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4275 if (spapr_memory_hot_unplug_supported(sms)) { 4276 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4277 } else { 4278 error_setg(errp, "Memory hot unplug not supported for this guest"); 4279 } 4280 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4281 if (!mc->has_hotpluggable_cpus) { 4282 error_setg(errp, "CPU hot unplug not supported on this machine"); 4283 return; 4284 } 4285 spapr_core_unplug_request(hotplug_dev, dev, errp); 4286 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4287 if (!smc->dr_phb_enabled) { 4288 error_setg(errp, "PHB hot unplug not supported on this machine"); 4289 return; 4290 } 4291 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4292 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4293 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4294 } 4295 } 4296 4297 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4298 DeviceState *dev, Error **errp) 4299 { 4300 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4301 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4302 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4303 spapr_core_pre_plug(hotplug_dev, dev, errp); 4304 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4305 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4306 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4307 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4308 } 4309 } 4310 4311 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4312 DeviceState *dev) 4313 { 4314 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4315 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4316 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4317 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4318 return HOTPLUG_HANDLER(machine); 4319 } 4320 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4321 PCIDevice *pcidev = PCI_DEVICE(dev); 4322 PCIBus *root = pci_device_root_bus(pcidev); 4323 SpaprPhbState *phb = 4324 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4325 TYPE_SPAPR_PCI_HOST_BRIDGE); 4326 4327 if (phb) { 4328 return HOTPLUG_HANDLER(phb); 4329 } 4330 } 4331 return NULL; 4332 } 4333 4334 static CpuInstanceProperties 4335 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4336 { 4337 CPUArchId *core_slot; 4338 MachineClass *mc = MACHINE_GET_CLASS(machine); 4339 4340 /* make sure possible_cpu are initialized */ 4341 mc->possible_cpu_arch_ids(machine); 4342 /* get CPU core slot containing thread that matches cpu_index */ 4343 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4344 assert(core_slot); 4345 return core_slot->props; 4346 } 4347 4348 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4349 { 4350 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4351 } 4352 4353 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4354 { 4355 int i; 4356 unsigned int smp_threads = machine->smp.threads; 4357 unsigned int smp_cpus = machine->smp.cpus; 4358 const char *core_type; 4359 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4360 MachineClass *mc = MACHINE_GET_CLASS(machine); 4361 4362 if (!mc->has_hotpluggable_cpus) { 4363 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4364 } 4365 if (machine->possible_cpus) { 4366 assert(machine->possible_cpus->len == spapr_max_cores); 4367 return machine->possible_cpus; 4368 } 4369 4370 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4371 if (!core_type) { 4372 error_report("Unable to find sPAPR CPU Core definition"); 4373 exit(1); 4374 } 4375 4376 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4377 sizeof(CPUArchId) * spapr_max_cores); 4378 machine->possible_cpus->len = spapr_max_cores; 4379 for (i = 0; i < machine->possible_cpus->len; i++) { 4380 int core_id = i * smp_threads; 4381 4382 machine->possible_cpus->cpus[i].type = core_type; 4383 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4384 machine->possible_cpus->cpus[i].arch_id = core_id; 4385 machine->possible_cpus->cpus[i].props.has_core_id = true; 4386 machine->possible_cpus->cpus[i].props.core_id = core_id; 4387 } 4388 return machine->possible_cpus; 4389 } 4390 4391 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4392 uint64_t *buid, hwaddr *pio, 4393 hwaddr *mmio32, hwaddr *mmio64, 4394 unsigned n_dma, uint32_t *liobns, Error **errp) 4395 { 4396 /* 4397 * New-style PHB window placement. 4398 * 4399 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4400 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4401 * windows. 4402 * 4403 * Some guest kernels can't work with MMIO windows above 1<<46 4404 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4405 * 4406 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4407 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4408 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4409 * 1TiB 64-bit MMIO windows for each PHB. 4410 */ 4411 const uint64_t base_buid = 0x800000020000000ULL; 4412 int i; 4413 4414 /* Sanity check natural alignments */ 4415 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4416 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4417 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4418 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4419 /* Sanity check bounds */ 4420 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4421 SPAPR_PCI_MEM32_WIN_SIZE); 4422 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4423 SPAPR_PCI_MEM64_WIN_SIZE); 4424 4425 if (index >= SPAPR_MAX_PHBS) { 4426 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4427 SPAPR_MAX_PHBS - 1); 4428 return false; 4429 } 4430 4431 *buid = base_buid + index; 4432 for (i = 0; i < n_dma; ++i) { 4433 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4434 } 4435 4436 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4437 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4438 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4439 return true; 4440 } 4441 4442 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4443 { 4444 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4445 4446 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4447 } 4448 4449 static void spapr_ics_resend(XICSFabric *dev) 4450 { 4451 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4452 4453 ics_resend(spapr->ics); 4454 } 4455 4456 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4457 { 4458 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4459 4460 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4461 } 4462 4463 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4464 Monitor *mon) 4465 { 4466 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4467 4468 spapr_irq_print_info(spapr, mon); 4469 monitor_printf(mon, "irqchip: %s\n", 4470 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4471 } 4472 4473 /* 4474 * This is a XIVE only operation 4475 */ 4476 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4477 uint8_t nvt_blk, uint32_t nvt_idx, 4478 bool cam_ignore, uint8_t priority, 4479 uint32_t logic_serv, XiveTCTXMatch *match) 4480 { 4481 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4482 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4483 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4484 int count; 4485 4486 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4487 priority, logic_serv, match); 4488 if (count < 0) { 4489 return count; 4490 } 4491 4492 /* 4493 * When we implement the save and restore of the thread interrupt 4494 * contexts in the enter/exit CPU handlers of the machine and the 4495 * escalations in QEMU, we should be able to handle non dispatched 4496 * vCPUs. 4497 * 4498 * Until this is done, the sPAPR machine should find at least one 4499 * matching context always. 4500 */ 4501 if (count == 0) { 4502 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4503 nvt_blk, nvt_idx); 4504 } 4505 4506 return count; 4507 } 4508 4509 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4510 { 4511 return cpu->vcpu_id; 4512 } 4513 4514 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4515 { 4516 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4517 MachineState *ms = MACHINE(spapr); 4518 int vcpu_id; 4519 4520 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4521 4522 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4523 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4524 error_append_hint(errp, "Adjust the number of cpus to %d " 4525 "or try to raise the number of threads per core\n", 4526 vcpu_id * ms->smp.threads / spapr->vsmt); 4527 return false; 4528 } 4529 4530 cpu->vcpu_id = vcpu_id; 4531 return true; 4532 } 4533 4534 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4535 { 4536 CPUState *cs; 4537 4538 CPU_FOREACH(cs) { 4539 PowerPCCPU *cpu = POWERPC_CPU(cs); 4540 4541 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4542 return cpu; 4543 } 4544 } 4545 4546 return NULL; 4547 } 4548 4549 static bool spapr_cpu_in_nested(PowerPCCPU *cpu) 4550 { 4551 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4552 4553 return spapr_cpu->in_nested; 4554 } 4555 4556 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4557 { 4558 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4559 4560 /* These are only called by TCG, KVM maintains dispatch state */ 4561 4562 spapr_cpu->prod = false; 4563 if (spapr_cpu->vpa_addr) { 4564 CPUState *cs = CPU(cpu); 4565 uint32_t dispatch; 4566 4567 dispatch = ldl_be_phys(cs->as, 4568 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4569 dispatch++; 4570 if ((dispatch & 1) != 0) { 4571 qemu_log_mask(LOG_GUEST_ERROR, 4572 "VPA: incorrect dispatch counter value for " 4573 "dispatched partition %u, correcting.\n", dispatch); 4574 dispatch++; 4575 } 4576 stl_be_phys(cs->as, 4577 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4578 } 4579 } 4580 4581 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4582 { 4583 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4584 4585 if (spapr_cpu->vpa_addr) { 4586 CPUState *cs = CPU(cpu); 4587 uint32_t dispatch; 4588 4589 dispatch = ldl_be_phys(cs->as, 4590 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4591 dispatch++; 4592 if ((dispatch & 1) != 1) { 4593 qemu_log_mask(LOG_GUEST_ERROR, 4594 "VPA: incorrect dispatch counter value for " 4595 "preempted partition %u, correcting.\n", dispatch); 4596 dispatch++; 4597 } 4598 stl_be_phys(cs->as, 4599 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4600 } 4601 } 4602 4603 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4604 { 4605 MachineClass *mc = MACHINE_CLASS(oc); 4606 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4607 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4608 NMIClass *nc = NMI_CLASS(oc); 4609 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4610 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4611 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4612 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4613 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4614 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); 4615 4616 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4617 mc->ignore_boot_device_suffixes = true; 4618 4619 /* 4620 * We set up the default / latest behaviour here. The class_init 4621 * functions for the specific versioned machine types can override 4622 * these details for backwards compatibility 4623 */ 4624 mc->init = spapr_machine_init; 4625 mc->reset = spapr_machine_reset; 4626 mc->block_default_type = IF_SCSI; 4627 4628 /* 4629 * Setting max_cpus to INT32_MAX. Both KVM and TCG max_cpus values 4630 * should be limited by the host capability instead of hardcoded. 4631 * max_cpus for KVM guests will be checked in kvm_init(), and TCG 4632 * guests are welcome to have as many CPUs as the host are capable 4633 * of emulate. 4634 */ 4635 mc->max_cpus = INT32_MAX; 4636 4637 mc->no_parallel = 1; 4638 mc->default_boot_order = ""; 4639 mc->default_ram_size = 512 * MiB; 4640 mc->default_ram_id = "ppc_spapr.ram"; 4641 mc->default_display = "std"; 4642 mc->kvm_type = spapr_kvm_type; 4643 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4644 mc->pci_allow_0_address = true; 4645 assert(!mc->get_hotplug_handler); 4646 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4647 hc->pre_plug = spapr_machine_device_pre_plug; 4648 hc->plug = spapr_machine_device_plug; 4649 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4650 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4651 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4652 hc->unplug_request = spapr_machine_device_unplug_request; 4653 hc->unplug = spapr_machine_device_unplug; 4654 4655 smc->dr_lmb_enabled = true; 4656 smc->update_dt_enabled = true; 4657 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 4658 mc->has_hotpluggable_cpus = true; 4659 mc->nvdimm_supported = true; 4660 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4661 fwc->get_dev_path = spapr_get_fw_dev_path; 4662 nc->nmi_monitor_handler = spapr_nmi; 4663 smc->phb_placement = spapr_phb_placement; 4664 vhc->cpu_in_nested = spapr_cpu_in_nested; 4665 vhc->deliver_hv_excp = spapr_exit_nested; 4666 vhc->hypercall = emulate_spapr_hypercall; 4667 vhc->hpt_mask = spapr_hpt_mask; 4668 vhc->map_hptes = spapr_map_hptes; 4669 vhc->unmap_hptes = spapr_unmap_hptes; 4670 vhc->hpte_set_c = spapr_hpte_set_c; 4671 vhc->hpte_set_r = spapr_hpte_set_r; 4672 vhc->get_pate = spapr_get_pate; 4673 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4674 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4675 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4676 xic->ics_get = spapr_ics_get; 4677 xic->ics_resend = spapr_ics_resend; 4678 xic->icp_get = spapr_icp_get; 4679 ispc->print_info = spapr_pic_print_info; 4680 /* Force NUMA node memory size to be a multiple of 4681 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4682 * in which LMBs are represented and hot-added 4683 */ 4684 mc->numa_mem_align_shift = 28; 4685 mc->auto_enable_numa = true; 4686 4687 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4688 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4689 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4690 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4691 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4692 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4693 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4694 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4695 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4696 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4697 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4698 smc->default_caps.caps[SPAPR_CAP_RPT_INVALIDATE] = SPAPR_CAP_OFF; 4699 4700 /* 4701 * This cap specifies whether the AIL 3 mode for 4702 * H_SET_RESOURCE is supported. The default is modified 4703 * by default_caps_with_cpu(). 4704 */ 4705 smc->default_caps.caps[SPAPR_CAP_AIL_MODE_3] = SPAPR_CAP_ON; 4706 spapr_caps_add_properties(smc); 4707 smc->irq = &spapr_irq_dual; 4708 smc->dr_phb_enabled = true; 4709 smc->linux_pci_probe = true; 4710 smc->smp_threads_vsmt = true; 4711 smc->nr_xirqs = SPAPR_NR_XIRQS; 4712 xfc->match_nvt = spapr_match_nvt; 4713 vmc->client_architecture_support = spapr_vof_client_architecture_support; 4714 vmc->quiesce = spapr_vof_quiesce; 4715 vmc->setprop = spapr_vof_setprop; 4716 } 4717 4718 static const TypeInfo spapr_machine_info = { 4719 .name = TYPE_SPAPR_MACHINE, 4720 .parent = TYPE_MACHINE, 4721 .abstract = true, 4722 .instance_size = sizeof(SpaprMachineState), 4723 .instance_init = spapr_instance_init, 4724 .instance_finalize = spapr_machine_finalizefn, 4725 .class_size = sizeof(SpaprMachineClass), 4726 .class_init = spapr_machine_class_init, 4727 .interfaces = (InterfaceInfo[]) { 4728 { TYPE_FW_PATH_PROVIDER }, 4729 { TYPE_NMI }, 4730 { TYPE_HOTPLUG_HANDLER }, 4731 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4732 { TYPE_XICS_FABRIC }, 4733 { TYPE_INTERRUPT_STATS_PROVIDER }, 4734 { TYPE_XIVE_FABRIC }, 4735 { TYPE_VOF_MACHINE_IF }, 4736 { } 4737 }, 4738 }; 4739 4740 static void spapr_machine_latest_class_options(MachineClass *mc) 4741 { 4742 mc->alias = "pseries"; 4743 mc->is_default = true; 4744 } 4745 4746 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4747 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4748 void *data) \ 4749 { \ 4750 MachineClass *mc = MACHINE_CLASS(oc); \ 4751 spapr_machine_##suffix##_class_options(mc); \ 4752 if (latest) { \ 4753 spapr_machine_latest_class_options(mc); \ 4754 } \ 4755 } \ 4756 static const TypeInfo spapr_machine_##suffix##_info = { \ 4757 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4758 .parent = TYPE_SPAPR_MACHINE, \ 4759 .class_init = spapr_machine_##suffix##_class_init, \ 4760 }; \ 4761 static void spapr_machine_register_##suffix(void) \ 4762 { \ 4763 type_register(&spapr_machine_##suffix##_info); \ 4764 } \ 4765 type_init(spapr_machine_register_##suffix) 4766 4767 /* 4768 * pseries-8.2 4769 */ 4770 static void spapr_machine_8_2_class_options(MachineClass *mc) 4771 { 4772 /* Defaults for the latest behaviour inherited from the base class */ 4773 } 4774 4775 DEFINE_SPAPR_MACHINE(8_2, "8.2", true); 4776 4777 /* 4778 * pseries-8.1 4779 */ 4780 static void spapr_machine_8_1_class_options(MachineClass *mc) 4781 { 4782 spapr_machine_8_2_class_options(mc); 4783 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len); 4784 } 4785 4786 DEFINE_SPAPR_MACHINE(8_1, "8.1", false); 4787 4788 /* 4789 * pseries-8.0 4790 */ 4791 static void spapr_machine_8_0_class_options(MachineClass *mc) 4792 { 4793 spapr_machine_8_1_class_options(mc); 4794 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 4795 } 4796 4797 DEFINE_SPAPR_MACHINE(8_0, "8.0", false); 4798 4799 /* 4800 * pseries-7.2 4801 */ 4802 static void spapr_machine_7_2_class_options(MachineClass *mc) 4803 { 4804 spapr_machine_8_0_class_options(mc); 4805 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 4806 } 4807 4808 DEFINE_SPAPR_MACHINE(7_2, "7.2", false); 4809 4810 /* 4811 * pseries-7.1 4812 */ 4813 static void spapr_machine_7_1_class_options(MachineClass *mc) 4814 { 4815 spapr_machine_7_2_class_options(mc); 4816 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 4817 } 4818 4819 DEFINE_SPAPR_MACHINE(7_1, "7.1", false); 4820 4821 /* 4822 * pseries-7.0 4823 */ 4824 static void spapr_machine_7_0_class_options(MachineClass *mc) 4825 { 4826 spapr_machine_7_1_class_options(mc); 4827 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 4828 } 4829 4830 DEFINE_SPAPR_MACHINE(7_0, "7.0", false); 4831 4832 /* 4833 * pseries-6.2 4834 */ 4835 static void spapr_machine_6_2_class_options(MachineClass *mc) 4836 { 4837 spapr_machine_7_0_class_options(mc); 4838 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 4839 } 4840 4841 DEFINE_SPAPR_MACHINE(6_2, "6.2", false); 4842 4843 /* 4844 * pseries-6.1 4845 */ 4846 static void spapr_machine_6_1_class_options(MachineClass *mc) 4847 { 4848 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4849 4850 spapr_machine_6_2_class_options(mc); 4851 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 4852 smc->pre_6_2_numa_affinity = true; 4853 mc->smp_props.prefer_sockets = true; 4854 } 4855 4856 DEFINE_SPAPR_MACHINE(6_1, "6.1", false); 4857 4858 /* 4859 * pseries-6.0 4860 */ 4861 static void spapr_machine_6_0_class_options(MachineClass *mc) 4862 { 4863 spapr_machine_6_1_class_options(mc); 4864 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 4865 } 4866 4867 DEFINE_SPAPR_MACHINE(6_0, "6.0", false); 4868 4869 /* 4870 * pseries-5.2 4871 */ 4872 static void spapr_machine_5_2_class_options(MachineClass *mc) 4873 { 4874 spapr_machine_6_0_class_options(mc); 4875 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4876 } 4877 4878 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4879 4880 /* 4881 * pseries-5.1 4882 */ 4883 static void spapr_machine_5_1_class_options(MachineClass *mc) 4884 { 4885 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4886 4887 spapr_machine_5_2_class_options(mc); 4888 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4889 smc->pre_5_2_numa_associativity = true; 4890 } 4891 4892 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4893 4894 /* 4895 * pseries-5.0 4896 */ 4897 static void spapr_machine_5_0_class_options(MachineClass *mc) 4898 { 4899 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4900 static GlobalProperty compat[] = { 4901 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4902 }; 4903 4904 spapr_machine_5_1_class_options(mc); 4905 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4906 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4907 mc->numa_mem_supported = true; 4908 smc->pre_5_1_assoc_refpoints = true; 4909 } 4910 4911 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4912 4913 /* 4914 * pseries-4.2 4915 */ 4916 static void spapr_machine_4_2_class_options(MachineClass *mc) 4917 { 4918 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4919 4920 spapr_machine_5_0_class_options(mc); 4921 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4922 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4923 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4924 smc->rma_limit = 16 * GiB; 4925 mc->nvdimm_supported = false; 4926 } 4927 4928 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4929 4930 /* 4931 * pseries-4.1 4932 */ 4933 static void spapr_machine_4_1_class_options(MachineClass *mc) 4934 { 4935 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4936 static GlobalProperty compat[] = { 4937 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4938 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4939 }; 4940 4941 spapr_machine_4_2_class_options(mc); 4942 smc->linux_pci_probe = false; 4943 smc->smp_threads_vsmt = false; 4944 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4945 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4946 } 4947 4948 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4949 4950 /* 4951 * pseries-4.0 4952 */ 4953 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4954 uint64_t *buid, hwaddr *pio, 4955 hwaddr *mmio32, hwaddr *mmio64, 4956 unsigned n_dma, uint32_t *liobns, Error **errp) 4957 { 4958 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 4959 liobns, errp)) { 4960 return false; 4961 } 4962 return true; 4963 } 4964 static void spapr_machine_4_0_class_options(MachineClass *mc) 4965 { 4966 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4967 4968 spapr_machine_4_1_class_options(mc); 4969 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4970 smc->phb_placement = phb_placement_4_0; 4971 smc->irq = &spapr_irq_xics; 4972 smc->pre_4_1_migration = true; 4973 } 4974 4975 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4976 4977 /* 4978 * pseries-3.1 4979 */ 4980 static void spapr_machine_3_1_class_options(MachineClass *mc) 4981 { 4982 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4983 4984 spapr_machine_4_0_class_options(mc); 4985 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4986 4987 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4988 smc->update_dt_enabled = false; 4989 smc->dr_phb_enabled = false; 4990 smc->broken_host_serial_model = true; 4991 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4992 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4993 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4994 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4995 } 4996 4997 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4998 4999 /* 5000 * pseries-3.0 5001 */ 5002 5003 static void spapr_machine_3_0_class_options(MachineClass *mc) 5004 { 5005 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5006 5007 spapr_machine_3_1_class_options(mc); 5008 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 5009 5010 smc->legacy_irq_allocation = true; 5011 smc->nr_xirqs = 0x400; 5012 smc->irq = &spapr_irq_xics_legacy; 5013 } 5014 5015 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 5016 5017 /* 5018 * pseries-2.12 5019 */ 5020 static void spapr_machine_2_12_class_options(MachineClass *mc) 5021 { 5022 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5023 static GlobalProperty compat[] = { 5024 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 5025 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 5026 }; 5027 5028 spapr_machine_3_0_class_options(mc); 5029 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 5030 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5031 5032 /* We depend on kvm_enabled() to choose a default value for the 5033 * hpt-max-page-size capability. Of course we can't do it here 5034 * because this is too early and the HW accelerator isn't initialized 5035 * yet. Postpone this to machine init (see default_caps_with_cpu()). 5036 */ 5037 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 5038 } 5039 5040 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 5041 5042 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 5043 { 5044 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5045 5046 spapr_machine_2_12_class_options(mc); 5047 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 5048 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 5049 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 5050 } 5051 5052 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 5053 5054 /* 5055 * pseries-2.11 5056 */ 5057 5058 static void spapr_machine_2_11_class_options(MachineClass *mc) 5059 { 5060 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5061 5062 spapr_machine_2_12_class_options(mc); 5063 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 5064 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 5065 } 5066 5067 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 5068 5069 /* 5070 * pseries-2.10 5071 */ 5072 5073 static void spapr_machine_2_10_class_options(MachineClass *mc) 5074 { 5075 spapr_machine_2_11_class_options(mc); 5076 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 5077 } 5078 5079 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 5080 5081 /* 5082 * pseries-2.9 5083 */ 5084 5085 static void spapr_machine_2_9_class_options(MachineClass *mc) 5086 { 5087 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5088 static GlobalProperty compat[] = { 5089 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 5090 }; 5091 5092 spapr_machine_2_10_class_options(mc); 5093 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 5094 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5095 smc->pre_2_10_has_unused_icps = true; 5096 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 5097 } 5098 5099 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 5100 5101 /* 5102 * pseries-2.8 5103 */ 5104 5105 static void spapr_machine_2_8_class_options(MachineClass *mc) 5106 { 5107 static GlobalProperty compat[] = { 5108 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 5109 }; 5110 5111 spapr_machine_2_9_class_options(mc); 5112 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 5113 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5114 mc->numa_mem_align_shift = 23; 5115 } 5116 5117 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 5118 5119 /* 5120 * pseries-2.7 5121 */ 5122 5123 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 5124 uint64_t *buid, hwaddr *pio, 5125 hwaddr *mmio32, hwaddr *mmio64, 5126 unsigned n_dma, uint32_t *liobns, Error **errp) 5127 { 5128 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 5129 const uint64_t base_buid = 0x800000020000000ULL; 5130 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 5131 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 5132 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 5133 const uint32_t max_index = 255; 5134 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 5135 5136 uint64_t ram_top = MACHINE(spapr)->ram_size; 5137 hwaddr phb0_base, phb_base; 5138 int i; 5139 5140 /* Do we have device memory? */ 5141 if (MACHINE(spapr)->device_memory) { 5142 /* Can't just use maxram_size, because there may be an 5143 * alignment gap between normal and device memory regions 5144 */ 5145 ram_top = MACHINE(spapr)->device_memory->base + 5146 memory_region_size(&MACHINE(spapr)->device_memory->mr); 5147 } 5148 5149 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 5150 5151 if (index > max_index) { 5152 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 5153 max_index); 5154 return false; 5155 } 5156 5157 *buid = base_buid + index; 5158 for (i = 0; i < n_dma; ++i) { 5159 liobns[i] = SPAPR_PCI_LIOBN(index, i); 5160 } 5161 5162 phb_base = phb0_base + index * phb_spacing; 5163 *pio = phb_base + pio_offset; 5164 *mmio32 = phb_base + mmio_offset; 5165 /* 5166 * We don't set the 64-bit MMIO window, relying on the PHB's 5167 * fallback behaviour of automatically splitting a large "32-bit" 5168 * window into contiguous 32-bit and 64-bit windows 5169 */ 5170 5171 return true; 5172 } 5173 5174 static void spapr_machine_2_7_class_options(MachineClass *mc) 5175 { 5176 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5177 static GlobalProperty compat[] = { 5178 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 5179 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 5180 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 5181 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 5182 }; 5183 5184 spapr_machine_2_8_class_options(mc); 5185 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 5186 mc->default_machine_opts = "modern-hotplug-events=off"; 5187 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 5188 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5189 smc->phb_placement = phb_placement_2_7; 5190 } 5191 5192 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 5193 5194 /* 5195 * pseries-2.6 5196 */ 5197 5198 static void spapr_machine_2_6_class_options(MachineClass *mc) 5199 { 5200 static GlobalProperty compat[] = { 5201 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 5202 }; 5203 5204 spapr_machine_2_7_class_options(mc); 5205 mc->has_hotpluggable_cpus = false; 5206 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 5207 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5208 } 5209 5210 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 5211 5212 /* 5213 * pseries-2.5 5214 */ 5215 5216 static void spapr_machine_2_5_class_options(MachineClass *mc) 5217 { 5218 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5219 static GlobalProperty compat[] = { 5220 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 5221 }; 5222 5223 spapr_machine_2_6_class_options(mc); 5224 smc->use_ohci_by_default = true; 5225 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 5226 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5227 } 5228 5229 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 5230 5231 /* 5232 * pseries-2.4 5233 */ 5234 5235 static void spapr_machine_2_4_class_options(MachineClass *mc) 5236 { 5237 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5238 5239 spapr_machine_2_5_class_options(mc); 5240 smc->dr_lmb_enabled = false; 5241 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 5242 } 5243 5244 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 5245 5246 /* 5247 * pseries-2.3 5248 */ 5249 5250 static void spapr_machine_2_3_class_options(MachineClass *mc) 5251 { 5252 static GlobalProperty compat[] = { 5253 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 5254 }; 5255 spapr_machine_2_4_class_options(mc); 5256 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 5257 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5258 } 5259 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 5260 5261 /* 5262 * pseries-2.2 5263 */ 5264 5265 static void spapr_machine_2_2_class_options(MachineClass *mc) 5266 { 5267 static GlobalProperty compat[] = { 5268 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 5269 }; 5270 5271 spapr_machine_2_3_class_options(mc); 5272 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 5273 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5274 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 5275 } 5276 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 5277 5278 /* 5279 * pseries-2.1 5280 */ 5281 5282 static void spapr_machine_2_1_class_options(MachineClass *mc) 5283 { 5284 spapr_machine_2_2_class_options(mc); 5285 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 5286 } 5287 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 5288 5289 static void spapr_machine_register_types(void) 5290 { 5291 type_register_static(&spapr_machine_info); 5292 } 5293 5294 type_init(spapr_machine_register_types) 5295