1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/numa.h" 32 #include "hw/hw.h" 33 #include "qemu/log.h" 34 #include "hw/fw-path-provider.h" 35 #include "elf.h" 36 #include "net/net.h" 37 #include "sysemu/device_tree.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/misc.h" 42 #include "migration/global_state.h" 43 #include "migration/register.h" 44 #include "mmu-hash64.h" 45 #include "mmu-book3s-v3.h" 46 #include "cpu-models.h" 47 #include "qom/cpu.h" 48 49 #include "hw/boards.h" 50 #include "hw/ppc/ppc.h" 51 #include "hw/loader.h" 52 53 #include "hw/ppc/fdt.h" 54 #include "hw/ppc/spapr.h" 55 #include "hw/ppc/spapr_vio.h" 56 #include "hw/pci-host/spapr.h" 57 #include "hw/ppc/xics.h" 58 #include "hw/pci/msi.h" 59 60 #include "hw/pci/pci.h" 61 #include "hw/scsi/scsi.h" 62 #include "hw/virtio/virtio-scsi.h" 63 #include "hw/virtio/vhost-scsi-common.h" 64 65 #include "exec/address-spaces.h" 66 #include "hw/usb.h" 67 #include "qemu/config-file.h" 68 #include "qemu/error-report.h" 69 #include "trace.h" 70 #include "hw/nmi.h" 71 #include "hw/intc/intc.h" 72 73 #include "hw/compat.h" 74 #include "qemu/cutils.h" 75 #include "hw/ppc/spapr_cpu_core.h" 76 #include "hw/mem/memory-device.h" 77 78 #include <libfdt.h> 79 80 /* SLOF memory layout: 81 * 82 * SLOF raw image loaded at 0, copies its romfs right below the flat 83 * device-tree, then position SLOF itself 31M below that 84 * 85 * So we set FW_OVERHEAD to 40MB which should account for all of that 86 * and more 87 * 88 * We load our kernel at 4M, leaving space for SLOF initial image 89 */ 90 #define FDT_MAX_SIZE 0x100000 91 #define RTAS_MAX_SIZE 0x10000 92 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 93 #define FW_MAX_SIZE 0x400000 94 #define FW_FILE_NAME "slof.bin" 95 #define FW_OVERHEAD 0x2800000 96 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 97 98 #define MIN_RMA_SLOF 128UL 99 100 #define PHANDLE_XICP 0x00001111 101 102 /* These two functions implement the VCPU id numbering: one to compute them 103 * all and one to identify thread 0 of a VCORE. Any change to the first one 104 * is likely to have an impact on the second one, so let's keep them close. 105 */ 106 static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index) 107 { 108 assert(spapr->vsmt); 109 return 110 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 111 } 112 static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr, 113 PowerPCCPU *cpu) 114 { 115 assert(spapr->vsmt); 116 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 117 } 118 119 static ICSState *spapr_ics_create(sPAPRMachineState *spapr, 120 const char *type_ics, 121 int nr_irqs, Error **errp) 122 { 123 Error *local_err = NULL; 124 Object *obj; 125 126 obj = object_new(type_ics); 127 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); 128 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), 129 &error_abort); 130 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); 131 if (local_err) { 132 goto error; 133 } 134 object_property_set_bool(obj, true, "realized", &local_err); 135 if (local_err) { 136 goto error; 137 } 138 139 return ICS_SIMPLE(obj); 140 141 error: 142 error_propagate(errp, local_err); 143 return NULL; 144 } 145 146 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 147 { 148 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 149 * and newer QEMUs don't even have them. In both cases, we don't want 150 * to send anything on the wire. 151 */ 152 return false; 153 } 154 155 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 156 .name = "icp/server", 157 .version_id = 1, 158 .minimum_version_id = 1, 159 .needed = pre_2_10_vmstate_dummy_icp_needed, 160 .fields = (VMStateField[]) { 161 VMSTATE_UNUSED(4), /* uint32_t xirr */ 162 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 163 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 164 VMSTATE_END_OF_LIST() 165 }, 166 }; 167 168 static void pre_2_10_vmstate_register_dummy_icp(int i) 169 { 170 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 171 (void *)(uintptr_t) i); 172 } 173 174 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 175 { 176 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 177 (void *)(uintptr_t) i); 178 } 179 180 static int xics_max_server_number(sPAPRMachineState *spapr) 181 { 182 assert(spapr->vsmt); 183 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads); 184 } 185 186 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) 187 { 188 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 189 190 if (kvm_enabled()) { 191 if (machine_kernel_irqchip_allowed(machine) && 192 !xics_kvm_init(spapr, errp)) { 193 spapr->icp_type = TYPE_KVM_ICP; 194 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp); 195 } 196 if (machine_kernel_irqchip_required(machine) && !spapr->ics) { 197 error_prepend(errp, "kernel_irqchip requested but unavailable: "); 198 return; 199 } 200 } 201 202 if (!spapr->ics) { 203 xics_spapr_init(spapr); 204 spapr->icp_type = TYPE_ICP; 205 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp); 206 if (!spapr->ics) { 207 return; 208 } 209 } 210 } 211 212 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 213 int smt_threads) 214 { 215 int i, ret = 0; 216 uint32_t servers_prop[smt_threads]; 217 uint32_t gservers_prop[smt_threads * 2]; 218 int index = spapr_get_vcpu_id(cpu); 219 220 if (cpu->compat_pvr) { 221 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 222 if (ret < 0) { 223 return ret; 224 } 225 } 226 227 /* Build interrupt servers and gservers properties */ 228 for (i = 0; i < smt_threads; i++) { 229 servers_prop[i] = cpu_to_be32(index + i); 230 /* Hack, direct the group queues back to cpu 0 */ 231 gservers_prop[i*2] = cpu_to_be32(index + i); 232 gservers_prop[i*2 + 1] = 0; 233 } 234 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 235 servers_prop, sizeof(servers_prop)); 236 if (ret < 0) { 237 return ret; 238 } 239 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 240 gservers_prop, sizeof(gservers_prop)); 241 242 return ret; 243 } 244 245 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 246 { 247 int index = spapr_get_vcpu_id(cpu); 248 uint32_t associativity[] = {cpu_to_be32(0x5), 249 cpu_to_be32(0x0), 250 cpu_to_be32(0x0), 251 cpu_to_be32(0x0), 252 cpu_to_be32(cpu->node_id), 253 cpu_to_be32(index)}; 254 255 /* Advertise NUMA via ibm,associativity */ 256 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 257 sizeof(associativity)); 258 } 259 260 /* Populate the "ibm,pa-features" property */ 261 static void spapr_populate_pa_features(sPAPRMachineState *spapr, 262 PowerPCCPU *cpu, 263 void *fdt, int offset, 264 bool legacy_guest) 265 { 266 uint8_t pa_features_206[] = { 6, 0, 267 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 268 uint8_t pa_features_207[] = { 24, 0, 269 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 270 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 271 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 272 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 273 uint8_t pa_features_300[] = { 66, 0, 274 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 275 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 276 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 277 /* 6: DS207 */ 278 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 279 /* 16: Vector */ 280 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 281 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 282 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 283 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 284 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 285 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 286 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 287 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 288 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 289 /* 42: PM, 44: PC RA, 46: SC vec'd */ 290 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 291 /* 48: SIMD, 50: QP BFP, 52: String */ 292 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 293 /* 54: DecFP, 56: DecI, 58: SHA */ 294 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 295 /* 60: NM atomic, 62: RNG */ 296 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 297 }; 298 uint8_t *pa_features = NULL; 299 size_t pa_size; 300 301 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 302 pa_features = pa_features_206; 303 pa_size = sizeof(pa_features_206); 304 } 305 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 306 pa_features = pa_features_207; 307 pa_size = sizeof(pa_features_207); 308 } 309 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 310 pa_features = pa_features_300; 311 pa_size = sizeof(pa_features_300); 312 } 313 if (!pa_features) { 314 return; 315 } 316 317 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 318 /* 319 * Note: we keep CI large pages off by default because a 64K capable 320 * guest provisioned with large pages might otherwise try to map a qemu 321 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 322 * even if that qemu runs on a 4k host. 323 * We dd this bit back here if we are confident this is not an issue 324 */ 325 pa_features[3] |= 0x20; 326 } 327 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 328 pa_features[24] |= 0x80; /* Transactional memory support */ 329 } 330 if (legacy_guest && pa_size > 40) { 331 /* Workaround for broken kernels that attempt (guest) radix 332 * mode when they can't handle it, if they see the radix bit set 333 * in pa-features. So hide it from them. */ 334 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 335 } 336 337 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 338 } 339 340 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 341 { 342 int ret = 0, offset, cpus_offset; 343 CPUState *cs; 344 char cpu_model[32]; 345 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 346 347 CPU_FOREACH(cs) { 348 PowerPCCPU *cpu = POWERPC_CPU(cs); 349 DeviceClass *dc = DEVICE_GET_CLASS(cs); 350 int index = spapr_get_vcpu_id(cpu); 351 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 352 353 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 354 continue; 355 } 356 357 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 358 359 cpus_offset = fdt_path_offset(fdt, "/cpus"); 360 if (cpus_offset < 0) { 361 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 362 if (cpus_offset < 0) { 363 return cpus_offset; 364 } 365 } 366 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 367 if (offset < 0) { 368 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 369 if (offset < 0) { 370 return offset; 371 } 372 } 373 374 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 375 pft_size_prop, sizeof(pft_size_prop)); 376 if (ret < 0) { 377 return ret; 378 } 379 380 if (nb_numa_nodes > 1) { 381 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 382 if (ret < 0) { 383 return ret; 384 } 385 } 386 387 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 388 if (ret < 0) { 389 return ret; 390 } 391 392 spapr_populate_pa_features(spapr, cpu, fdt, offset, 393 spapr->cas_legacy_guest_workaround); 394 } 395 return ret; 396 } 397 398 static hwaddr spapr_node0_size(MachineState *machine) 399 { 400 if (nb_numa_nodes) { 401 int i; 402 for (i = 0; i < nb_numa_nodes; ++i) { 403 if (numa_info[i].node_mem) { 404 return MIN(pow2floor(numa_info[i].node_mem), 405 machine->ram_size); 406 } 407 } 408 } 409 return machine->ram_size; 410 } 411 412 static void add_str(GString *s, const gchar *s1) 413 { 414 g_string_append_len(s, s1, strlen(s1) + 1); 415 } 416 417 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 418 hwaddr size) 419 { 420 uint32_t associativity[] = { 421 cpu_to_be32(0x4), /* length */ 422 cpu_to_be32(0x0), cpu_to_be32(0x0), 423 cpu_to_be32(0x0), cpu_to_be32(nodeid) 424 }; 425 char mem_name[32]; 426 uint64_t mem_reg_property[2]; 427 int off; 428 429 mem_reg_property[0] = cpu_to_be64(start); 430 mem_reg_property[1] = cpu_to_be64(size); 431 432 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 433 off = fdt_add_subnode(fdt, 0, mem_name); 434 _FDT(off); 435 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 436 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 437 sizeof(mem_reg_property)))); 438 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 439 sizeof(associativity)))); 440 return off; 441 } 442 443 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 444 { 445 MachineState *machine = MACHINE(spapr); 446 hwaddr mem_start, node_size; 447 int i, nb_nodes = nb_numa_nodes; 448 NodeInfo *nodes = numa_info; 449 NodeInfo ramnode; 450 451 /* No NUMA nodes, assume there is just one node with whole RAM */ 452 if (!nb_numa_nodes) { 453 nb_nodes = 1; 454 ramnode.node_mem = machine->ram_size; 455 nodes = &ramnode; 456 } 457 458 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 459 if (!nodes[i].node_mem) { 460 continue; 461 } 462 if (mem_start >= machine->ram_size) { 463 node_size = 0; 464 } else { 465 node_size = nodes[i].node_mem; 466 if (node_size > machine->ram_size - mem_start) { 467 node_size = machine->ram_size - mem_start; 468 } 469 } 470 if (!mem_start) { 471 /* spapr_machine_init() checks for rma_size <= node0_size 472 * already */ 473 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 474 mem_start += spapr->rma_size; 475 node_size -= spapr->rma_size; 476 } 477 for ( ; node_size; ) { 478 hwaddr sizetmp = pow2floor(node_size); 479 480 /* mem_start != 0 here */ 481 if (ctzl(mem_start) < ctzl(sizetmp)) { 482 sizetmp = 1ULL << ctzl(mem_start); 483 } 484 485 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 486 node_size -= sizetmp; 487 mem_start += sizetmp; 488 } 489 } 490 491 return 0; 492 } 493 494 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 495 sPAPRMachineState *spapr) 496 { 497 PowerPCCPU *cpu = POWERPC_CPU(cs); 498 CPUPPCState *env = &cpu->env; 499 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 500 int index = spapr_get_vcpu_id(cpu); 501 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 502 0xffffffff, 0xffffffff}; 503 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 504 : SPAPR_TIMEBASE_FREQ; 505 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 506 uint32_t page_sizes_prop[64]; 507 size_t page_sizes_prop_size; 508 uint32_t vcpus_per_socket = smp_threads * smp_cores; 509 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 510 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 511 sPAPRDRConnector *drc; 512 int drc_index; 513 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 514 int i; 515 516 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 517 if (drc) { 518 drc_index = spapr_drc_index(drc); 519 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 520 } 521 522 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 523 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 524 525 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 526 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 527 env->dcache_line_size))); 528 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 529 env->dcache_line_size))); 530 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 531 env->icache_line_size))); 532 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 533 env->icache_line_size))); 534 535 if (pcc->l1_dcache_size) { 536 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 537 pcc->l1_dcache_size))); 538 } else { 539 warn_report("Unknown L1 dcache size for cpu"); 540 } 541 if (pcc->l1_icache_size) { 542 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 543 pcc->l1_icache_size))); 544 } else { 545 warn_report("Unknown L1 icache size for cpu"); 546 } 547 548 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 549 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 550 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 551 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 552 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 553 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 554 555 if (env->spr_cb[SPR_PURR].oea_read) { 556 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 557 } 558 559 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 560 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 561 segs, sizeof(segs)))); 562 } 563 564 /* Advertise VSX (vector extensions) if available 565 * 1 == VMX / Altivec available 566 * 2 == VSX available 567 * 568 * Only CPUs for which we create core types in spapr_cpu_core.c 569 * are possible, and all of those have VMX */ 570 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 571 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 572 } else { 573 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 574 } 575 576 /* Advertise DFP (Decimal Floating Point) if available 577 * 0 / no property == no DFP 578 * 1 == DFP available */ 579 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 580 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 581 } 582 583 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 584 sizeof(page_sizes_prop)); 585 if (page_sizes_prop_size) { 586 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 587 page_sizes_prop, page_sizes_prop_size))); 588 } 589 590 spapr_populate_pa_features(spapr, cpu, fdt, offset, false); 591 592 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 593 cs->cpu_index / vcpus_per_socket))); 594 595 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 596 pft_size_prop, sizeof(pft_size_prop)))); 597 598 if (nb_numa_nodes > 1) { 599 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 600 } 601 602 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 603 604 if (pcc->radix_page_info) { 605 for (i = 0; i < pcc->radix_page_info->count; i++) { 606 radix_AP_encodings[i] = 607 cpu_to_be32(pcc->radix_page_info->entries[i]); 608 } 609 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 610 radix_AP_encodings, 611 pcc->radix_page_info->count * 612 sizeof(radix_AP_encodings[0])))); 613 } 614 } 615 616 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 617 { 618 CPUState *cs; 619 int cpus_offset; 620 char *nodename; 621 622 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 623 _FDT(cpus_offset); 624 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 625 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 626 627 /* 628 * We walk the CPUs in reverse order to ensure that CPU DT nodes 629 * created by fdt_add_subnode() end up in the right order in FDT 630 * for the guest kernel the enumerate the CPUs correctly. 631 */ 632 CPU_FOREACH_REVERSE(cs) { 633 PowerPCCPU *cpu = POWERPC_CPU(cs); 634 int index = spapr_get_vcpu_id(cpu); 635 DeviceClass *dc = DEVICE_GET_CLASS(cs); 636 int offset; 637 638 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 639 continue; 640 } 641 642 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 643 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 644 g_free(nodename); 645 _FDT(offset); 646 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 647 } 648 649 } 650 651 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 652 { 653 MemoryDeviceInfoList *info; 654 655 for (info = list; info; info = info->next) { 656 MemoryDeviceInfo *value = info->value; 657 658 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 659 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 660 661 if (pcdimm_info->addr >= addr && 662 addr < (pcdimm_info->addr + pcdimm_info->size)) { 663 return pcdimm_info->node; 664 } 665 } 666 } 667 668 return -1; 669 } 670 671 struct sPAPRDrconfCellV2 { 672 uint32_t seq_lmbs; 673 uint64_t base_addr; 674 uint32_t drc_index; 675 uint32_t aa_index; 676 uint32_t flags; 677 } QEMU_PACKED; 678 679 typedef struct DrconfCellQueue { 680 struct sPAPRDrconfCellV2 cell; 681 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 682 } DrconfCellQueue; 683 684 static DrconfCellQueue * 685 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 686 uint32_t drc_index, uint32_t aa_index, 687 uint32_t flags) 688 { 689 DrconfCellQueue *elem; 690 691 elem = g_malloc0(sizeof(*elem)); 692 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 693 elem->cell.base_addr = cpu_to_be64(base_addr); 694 elem->cell.drc_index = cpu_to_be32(drc_index); 695 elem->cell.aa_index = cpu_to_be32(aa_index); 696 elem->cell.flags = cpu_to_be32(flags); 697 698 return elem; 699 } 700 701 /* ibm,dynamic-memory-v2 */ 702 static int spapr_populate_drmem_v2(sPAPRMachineState *spapr, void *fdt, 703 int offset, MemoryDeviceInfoList *dimms) 704 { 705 MachineState *machine = MACHINE(spapr); 706 uint8_t *int_buf, *cur_index, buf_len; 707 int ret; 708 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 709 uint64_t addr, cur_addr, size; 710 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 711 uint64_t mem_end = machine->device_memory->base + 712 memory_region_size(&machine->device_memory->mr); 713 uint32_t node, nr_entries = 0; 714 sPAPRDRConnector *drc; 715 DrconfCellQueue *elem, *next; 716 MemoryDeviceInfoList *info; 717 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 718 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 719 720 /* Entry to cover RAM and the gap area */ 721 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 722 SPAPR_LMB_FLAGS_RESERVED | 723 SPAPR_LMB_FLAGS_DRC_INVALID); 724 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 725 nr_entries++; 726 727 cur_addr = machine->device_memory->base; 728 for (info = dimms; info; info = info->next) { 729 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 730 731 addr = di->addr; 732 size = di->size; 733 node = di->node; 734 735 /* Entry for hot-pluggable area */ 736 if (cur_addr < addr) { 737 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 738 g_assert(drc); 739 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 740 cur_addr, spapr_drc_index(drc), -1, 0); 741 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 742 nr_entries++; 743 } 744 745 /* Entry for DIMM */ 746 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 747 g_assert(drc); 748 elem = spapr_get_drconf_cell(size / lmb_size, addr, 749 spapr_drc_index(drc), node, 750 SPAPR_LMB_FLAGS_ASSIGNED); 751 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 752 nr_entries++; 753 cur_addr = addr + size; 754 } 755 756 /* Entry for remaining hotpluggable area */ 757 if (cur_addr < mem_end) { 758 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 759 g_assert(drc); 760 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 761 cur_addr, spapr_drc_index(drc), -1, 0); 762 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 763 nr_entries++; 764 } 765 766 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 767 int_buf = cur_index = g_malloc0(buf_len); 768 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 769 cur_index += sizeof(nr_entries); 770 771 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 772 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 773 cur_index += sizeof(elem->cell); 774 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 775 g_free(elem); 776 } 777 778 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 779 g_free(int_buf); 780 if (ret < 0) { 781 return -1; 782 } 783 return 0; 784 } 785 786 /* ibm,dynamic-memory */ 787 static int spapr_populate_drmem_v1(sPAPRMachineState *spapr, void *fdt, 788 int offset, MemoryDeviceInfoList *dimms) 789 { 790 MachineState *machine = MACHINE(spapr); 791 int i, ret; 792 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 793 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 794 uint32_t nr_lmbs = (machine->device_memory->base + 795 memory_region_size(&machine->device_memory->mr)) / 796 lmb_size; 797 uint32_t *int_buf, *cur_index, buf_len; 798 799 /* 800 * Allocate enough buffer size to fit in ibm,dynamic-memory 801 */ 802 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 803 cur_index = int_buf = g_malloc0(buf_len); 804 int_buf[0] = cpu_to_be32(nr_lmbs); 805 cur_index++; 806 for (i = 0; i < nr_lmbs; i++) { 807 uint64_t addr = i * lmb_size; 808 uint32_t *dynamic_memory = cur_index; 809 810 if (i >= device_lmb_start) { 811 sPAPRDRConnector *drc; 812 813 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 814 g_assert(drc); 815 816 dynamic_memory[0] = cpu_to_be32(addr >> 32); 817 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 818 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 819 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 820 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 821 if (memory_region_present(get_system_memory(), addr)) { 822 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 823 } else { 824 dynamic_memory[5] = cpu_to_be32(0); 825 } 826 } else { 827 /* 828 * LMB information for RMA, boot time RAM and gap b/n RAM and 829 * device memory region -- all these are marked as reserved 830 * and as having no valid DRC. 831 */ 832 dynamic_memory[0] = cpu_to_be32(addr >> 32); 833 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 834 dynamic_memory[2] = cpu_to_be32(0); 835 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 836 dynamic_memory[4] = cpu_to_be32(-1); 837 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 838 SPAPR_LMB_FLAGS_DRC_INVALID); 839 } 840 841 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 842 } 843 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 844 g_free(int_buf); 845 if (ret < 0) { 846 return -1; 847 } 848 return 0; 849 } 850 851 /* 852 * Adds ibm,dynamic-reconfiguration-memory node. 853 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 854 * of this device tree node. 855 */ 856 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 857 { 858 MachineState *machine = MACHINE(spapr); 859 int ret, i, offset; 860 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 861 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 862 uint32_t *int_buf, *cur_index, buf_len; 863 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 864 MemoryDeviceInfoList *dimms = NULL; 865 866 /* 867 * Don't create the node if there is no device memory 868 */ 869 if (machine->ram_size == machine->maxram_size) { 870 return 0; 871 } 872 873 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 874 875 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 876 sizeof(prop_lmb_size)); 877 if (ret < 0) { 878 return ret; 879 } 880 881 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 882 if (ret < 0) { 883 return ret; 884 } 885 886 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 887 if (ret < 0) { 888 return ret; 889 } 890 891 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 892 dimms = qmp_memory_device_list(); 893 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 894 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 895 } else { 896 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 897 } 898 qapi_free_MemoryDeviceInfoList(dimms); 899 900 if (ret < 0) { 901 return ret; 902 } 903 904 /* ibm,associativity-lookup-arrays */ 905 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 906 cur_index = int_buf = g_malloc0(buf_len); 907 908 cur_index = int_buf; 909 int_buf[0] = cpu_to_be32(nr_nodes); 910 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 911 cur_index += 2; 912 for (i = 0; i < nr_nodes; i++) { 913 uint32_t associativity[] = { 914 cpu_to_be32(0x0), 915 cpu_to_be32(0x0), 916 cpu_to_be32(0x0), 917 cpu_to_be32(i) 918 }; 919 memcpy(cur_index, associativity, sizeof(associativity)); 920 cur_index += 4; 921 } 922 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 923 (cur_index - int_buf) * sizeof(uint32_t)); 924 g_free(int_buf); 925 926 return ret; 927 } 928 929 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 930 sPAPROptionVector *ov5_updates) 931 { 932 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 933 int ret = 0, offset; 934 935 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 936 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 937 g_assert(smc->dr_lmb_enabled); 938 ret = spapr_populate_drconf_memory(spapr, fdt); 939 if (ret) { 940 goto out; 941 } 942 } 943 944 offset = fdt_path_offset(fdt, "/chosen"); 945 if (offset < 0) { 946 offset = fdt_add_subnode(fdt, 0, "chosen"); 947 if (offset < 0) { 948 return offset; 949 } 950 } 951 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 952 "ibm,architecture-vec-5"); 953 954 out: 955 return ret; 956 } 957 958 static bool spapr_hotplugged_dev_before_cas(void) 959 { 960 Object *drc_container, *obj; 961 ObjectProperty *prop; 962 ObjectPropertyIterator iter; 963 964 drc_container = container_get(object_get_root(), "/dr-connector"); 965 object_property_iter_init(&iter, drc_container); 966 while ((prop = object_property_iter_next(&iter))) { 967 if (!strstart(prop->type, "link<", NULL)) { 968 continue; 969 } 970 obj = object_property_get_link(drc_container, prop->name, NULL); 971 if (spapr_drc_needed(obj)) { 972 return true; 973 } 974 } 975 return false; 976 } 977 978 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 979 target_ulong addr, target_ulong size, 980 sPAPROptionVector *ov5_updates) 981 { 982 void *fdt, *fdt_skel; 983 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 984 985 if (spapr_hotplugged_dev_before_cas()) { 986 return 1; 987 } 988 989 if (size < sizeof(hdr) || size > FW_MAX_SIZE) { 990 error_report("SLOF provided an unexpected CAS buffer size " 991 TARGET_FMT_lu " (min: %zu, max: %u)", 992 size, sizeof(hdr), FW_MAX_SIZE); 993 exit(EXIT_FAILURE); 994 } 995 996 size -= sizeof(hdr); 997 998 /* Create skeleton */ 999 fdt_skel = g_malloc0(size); 1000 _FDT((fdt_create(fdt_skel, size))); 1001 _FDT((fdt_finish_reservemap(fdt_skel))); 1002 _FDT((fdt_begin_node(fdt_skel, ""))); 1003 _FDT((fdt_end_node(fdt_skel))); 1004 _FDT((fdt_finish(fdt_skel))); 1005 fdt = g_malloc0(size); 1006 _FDT((fdt_open_into(fdt_skel, fdt, size))); 1007 g_free(fdt_skel); 1008 1009 /* Fixup cpu nodes */ 1010 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 1011 1012 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 1013 return -1; 1014 } 1015 1016 /* Pack resulting tree */ 1017 _FDT((fdt_pack(fdt))); 1018 1019 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 1020 trace_spapr_cas_failed(size); 1021 return -1; 1022 } 1023 1024 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 1025 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 1026 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 1027 g_free(fdt); 1028 1029 return 0; 1030 } 1031 1032 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 1033 { 1034 int rtas; 1035 GString *hypertas = g_string_sized_new(256); 1036 GString *qemu_hypertas = g_string_sized_new(256); 1037 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 1038 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 1039 memory_region_size(&MACHINE(spapr)->device_memory->mr); 1040 uint32_t lrdr_capacity[] = { 1041 cpu_to_be32(max_device_addr >> 32), 1042 cpu_to_be32(max_device_addr & 0xffffffff), 1043 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 1044 cpu_to_be32(max_cpus / smp_threads), 1045 }; 1046 uint32_t maxdomains[] = { 1047 cpu_to_be32(4), 1048 cpu_to_be32(0), 1049 cpu_to_be32(0), 1050 cpu_to_be32(0), 1051 cpu_to_be32(nb_numa_nodes ? nb_numa_nodes - 1 : 0), 1052 }; 1053 1054 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 1055 1056 /* hypertas */ 1057 add_str(hypertas, "hcall-pft"); 1058 add_str(hypertas, "hcall-term"); 1059 add_str(hypertas, "hcall-dabr"); 1060 add_str(hypertas, "hcall-interrupt"); 1061 add_str(hypertas, "hcall-tce"); 1062 add_str(hypertas, "hcall-vio"); 1063 add_str(hypertas, "hcall-splpar"); 1064 add_str(hypertas, "hcall-bulk"); 1065 add_str(hypertas, "hcall-set-mode"); 1066 add_str(hypertas, "hcall-sprg0"); 1067 add_str(hypertas, "hcall-copy"); 1068 add_str(hypertas, "hcall-debug"); 1069 add_str(qemu_hypertas, "hcall-memop1"); 1070 1071 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 1072 add_str(hypertas, "hcall-multi-tce"); 1073 } 1074 1075 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 1076 add_str(hypertas, "hcall-hpt-resize"); 1077 } 1078 1079 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 1080 hypertas->str, hypertas->len)); 1081 g_string_free(hypertas, TRUE); 1082 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 1083 qemu_hypertas->str, qemu_hypertas->len)); 1084 g_string_free(qemu_hypertas, TRUE); 1085 1086 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 1087 refpoints, sizeof(refpoints))); 1088 1089 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 1090 maxdomains, sizeof(maxdomains))); 1091 1092 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 1093 RTAS_ERROR_LOG_MAX)); 1094 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 1095 RTAS_EVENT_SCAN_RATE)); 1096 1097 g_assert(msi_nonbroken); 1098 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 1099 1100 /* 1101 * According to PAPR, rtas ibm,os-term does not guarantee a return 1102 * back to the guest cpu. 1103 * 1104 * While an additional ibm,extended-os-term property indicates 1105 * that rtas call return will always occur. Set this property. 1106 */ 1107 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1108 1109 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1110 lrdr_capacity, sizeof(lrdr_capacity))); 1111 1112 spapr_dt_rtas_tokens(fdt, rtas); 1113 } 1114 1115 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features 1116 * that the guest may request and thus the valid values for bytes 24..26 of 1117 * option vector 5: */ 1118 static void spapr_dt_ov5_platform_support(void *fdt, int chosen) 1119 { 1120 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1121 1122 char val[2 * 4] = { 1123 23, 0x00, /* Xive mode, filled in below. */ 1124 24, 0x00, /* Hash/Radix, filled in below. */ 1125 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1126 26, 0x40, /* Radix options: GTSE == yes. */ 1127 }; 1128 1129 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1130 first_ppc_cpu->compat_pvr)) { 1131 /* If we're in a pre POWER9 compat mode then the guest should do hash */ 1132 val[3] = 0x00; /* Hash */ 1133 } else if (kvm_enabled()) { 1134 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1135 val[3] = 0x80; /* OV5_MMU_BOTH */ 1136 } else if (kvmppc_has_cap_mmu_radix()) { 1137 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1138 } else { 1139 val[3] = 0x00; /* Hash */ 1140 } 1141 } else { 1142 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1143 val[3] = 0xC0; 1144 } 1145 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1146 val, sizeof(val))); 1147 } 1148 1149 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 1150 { 1151 MachineState *machine = MACHINE(spapr); 1152 int chosen; 1153 const char *boot_device = machine->boot_order; 1154 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1155 size_t cb = 0; 1156 char *bootlist = get_boot_devices_list(&cb, true); 1157 1158 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1159 1160 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 1161 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1162 spapr->initrd_base)); 1163 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1164 spapr->initrd_base + spapr->initrd_size)); 1165 1166 if (spapr->kernel_size) { 1167 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1168 cpu_to_be64(spapr->kernel_size) }; 1169 1170 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1171 &kprop, sizeof(kprop))); 1172 if (spapr->kernel_le) { 1173 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1174 } 1175 } 1176 if (boot_menu) { 1177 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1178 } 1179 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1180 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1181 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1182 1183 if (cb && bootlist) { 1184 int i; 1185 1186 for (i = 0; i < cb; i++) { 1187 if (bootlist[i] == '\n') { 1188 bootlist[i] = ' '; 1189 } 1190 } 1191 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1192 } 1193 1194 if (boot_device && strlen(boot_device)) { 1195 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1196 } 1197 1198 if (!spapr->has_graphics && stdout_path) { 1199 /* 1200 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1201 * kernel. New platforms should only use the "stdout-path" property. Set 1202 * the new property and continue using older property to remain 1203 * compatible with the existing firmware. 1204 */ 1205 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1206 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1207 } 1208 1209 spapr_dt_ov5_platform_support(fdt, chosen); 1210 1211 g_free(stdout_path); 1212 g_free(bootlist); 1213 } 1214 1215 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 1216 { 1217 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1218 * KVM to work under pHyp with some guest co-operation */ 1219 int hypervisor; 1220 uint8_t hypercall[16]; 1221 1222 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1223 /* indicate KVM hypercall interface */ 1224 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1225 if (kvmppc_has_cap_fixup_hcalls()) { 1226 /* 1227 * Older KVM versions with older guest kernels were broken 1228 * with the magic page, don't allow the guest to map it. 1229 */ 1230 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1231 sizeof(hypercall))) { 1232 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1233 hypercall, sizeof(hypercall))); 1234 } 1235 } 1236 } 1237 1238 static void *spapr_build_fdt(sPAPRMachineState *spapr, 1239 hwaddr rtas_addr, 1240 hwaddr rtas_size) 1241 { 1242 MachineState *machine = MACHINE(spapr); 1243 MachineClass *mc = MACHINE_GET_CLASS(machine); 1244 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1245 int ret; 1246 void *fdt; 1247 sPAPRPHBState *phb; 1248 char *buf; 1249 1250 fdt = g_malloc0(FDT_MAX_SIZE); 1251 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1252 1253 /* Root node */ 1254 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1255 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1256 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1257 1258 /* 1259 * Add info to guest to indentify which host is it being run on 1260 * and what is the uuid of the guest 1261 */ 1262 if (kvmppc_get_host_model(&buf)) { 1263 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1264 g_free(buf); 1265 } 1266 if (kvmppc_get_host_serial(&buf)) { 1267 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1268 g_free(buf); 1269 } 1270 1271 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1272 1273 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1274 if (qemu_uuid_set) { 1275 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1276 } 1277 g_free(buf); 1278 1279 if (qemu_get_vm_name()) { 1280 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1281 qemu_get_vm_name())); 1282 } 1283 1284 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1285 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1286 1287 /* /interrupt controller */ 1288 spapr_dt_xics(xics_max_server_number(spapr), fdt, PHANDLE_XICP); 1289 1290 ret = spapr_populate_memory(spapr, fdt); 1291 if (ret < 0) { 1292 error_report("couldn't setup memory nodes in fdt"); 1293 exit(1); 1294 } 1295 1296 /* /vdevice */ 1297 spapr_dt_vdevice(spapr->vio_bus, fdt); 1298 1299 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1300 ret = spapr_rng_populate_dt(fdt); 1301 if (ret < 0) { 1302 error_report("could not set up rng device in the fdt"); 1303 exit(1); 1304 } 1305 } 1306 1307 QLIST_FOREACH(phb, &spapr->phbs, list) { 1308 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 1309 if (ret < 0) { 1310 error_report("couldn't setup PCI devices in fdt"); 1311 exit(1); 1312 } 1313 } 1314 1315 /* cpus */ 1316 spapr_populate_cpus_dt_node(fdt, spapr); 1317 1318 if (smc->dr_lmb_enabled) { 1319 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1320 } 1321 1322 if (mc->has_hotpluggable_cpus) { 1323 int offset = fdt_path_offset(fdt, "/cpus"); 1324 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1325 SPAPR_DR_CONNECTOR_TYPE_CPU); 1326 if (ret < 0) { 1327 error_report("Couldn't set up CPU DR device tree properties"); 1328 exit(1); 1329 } 1330 } 1331 1332 /* /event-sources */ 1333 spapr_dt_events(spapr, fdt); 1334 1335 /* /rtas */ 1336 spapr_dt_rtas(spapr, fdt); 1337 1338 /* /chosen */ 1339 spapr_dt_chosen(spapr, fdt); 1340 1341 /* /hypervisor */ 1342 if (kvm_enabled()) { 1343 spapr_dt_hypervisor(spapr, fdt); 1344 } 1345 1346 /* Build memory reserve map */ 1347 if (spapr->kernel_size) { 1348 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1349 } 1350 if (spapr->initrd_size) { 1351 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1352 } 1353 1354 /* ibm,client-architecture-support updates */ 1355 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1356 if (ret < 0) { 1357 error_report("couldn't setup CAS properties fdt"); 1358 exit(1); 1359 } 1360 1361 return fdt; 1362 } 1363 1364 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1365 { 1366 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1367 } 1368 1369 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1370 PowerPCCPU *cpu) 1371 { 1372 CPUPPCState *env = &cpu->env; 1373 1374 /* The TCG path should also be holding the BQL at this point */ 1375 g_assert(qemu_mutex_iothread_locked()); 1376 1377 if (msr_pr) { 1378 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1379 env->gpr[3] = H_PRIVILEGE; 1380 } else { 1381 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1382 } 1383 } 1384 1385 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1386 { 1387 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1388 1389 return spapr->patb_entry; 1390 } 1391 1392 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1393 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1394 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1395 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1396 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1397 1398 /* 1399 * Get the fd to access the kernel htab, re-opening it if necessary 1400 */ 1401 static int get_htab_fd(sPAPRMachineState *spapr) 1402 { 1403 Error *local_err = NULL; 1404 1405 if (spapr->htab_fd >= 0) { 1406 return spapr->htab_fd; 1407 } 1408 1409 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1410 if (spapr->htab_fd < 0) { 1411 error_report_err(local_err); 1412 } 1413 1414 return spapr->htab_fd; 1415 } 1416 1417 void close_htab_fd(sPAPRMachineState *spapr) 1418 { 1419 if (spapr->htab_fd >= 0) { 1420 close(spapr->htab_fd); 1421 } 1422 spapr->htab_fd = -1; 1423 } 1424 1425 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1426 { 1427 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1428 1429 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1430 } 1431 1432 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1433 { 1434 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1435 1436 assert(kvm_enabled()); 1437 1438 if (!spapr->htab) { 1439 return 0; 1440 } 1441 1442 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1443 } 1444 1445 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1446 hwaddr ptex, int n) 1447 { 1448 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1449 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1450 1451 if (!spapr->htab) { 1452 /* 1453 * HTAB is controlled by KVM. Fetch into temporary buffer 1454 */ 1455 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1456 kvmppc_read_hptes(hptes, ptex, n); 1457 return hptes; 1458 } 1459 1460 /* 1461 * HTAB is controlled by QEMU. Just point to the internally 1462 * accessible PTEG. 1463 */ 1464 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1465 } 1466 1467 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1468 const ppc_hash_pte64_t *hptes, 1469 hwaddr ptex, int n) 1470 { 1471 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1472 1473 if (!spapr->htab) { 1474 g_free((void *)hptes); 1475 } 1476 1477 /* Nothing to do for qemu managed HPT */ 1478 } 1479 1480 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1481 uint64_t pte0, uint64_t pte1) 1482 { 1483 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1484 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1485 1486 if (!spapr->htab) { 1487 kvmppc_write_hpte(ptex, pte0, pte1); 1488 } else { 1489 stq_p(spapr->htab + offset, pte0); 1490 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1491 } 1492 } 1493 1494 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1495 { 1496 int shift; 1497 1498 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1499 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1500 * that's much more than is needed for Linux guests */ 1501 shift = ctz64(pow2ceil(ramsize)) - 7; 1502 shift = MAX(shift, 18); /* Minimum architected size */ 1503 shift = MIN(shift, 46); /* Maximum architected size */ 1504 return shift; 1505 } 1506 1507 void spapr_free_hpt(sPAPRMachineState *spapr) 1508 { 1509 g_free(spapr->htab); 1510 spapr->htab = NULL; 1511 spapr->htab_shift = 0; 1512 close_htab_fd(spapr); 1513 } 1514 1515 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1516 Error **errp) 1517 { 1518 long rc; 1519 1520 /* Clean up any HPT info from a previous boot */ 1521 spapr_free_hpt(spapr); 1522 1523 rc = kvmppc_reset_htab(shift); 1524 if (rc < 0) { 1525 /* kernel-side HPT needed, but couldn't allocate one */ 1526 error_setg_errno(errp, errno, 1527 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1528 shift); 1529 /* This is almost certainly fatal, but if the caller really 1530 * wants to carry on with shift == 0, it's welcome to try */ 1531 } else if (rc > 0) { 1532 /* kernel-side HPT allocated */ 1533 if (rc != shift) { 1534 error_setg(errp, 1535 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1536 shift, rc); 1537 } 1538 1539 spapr->htab_shift = shift; 1540 spapr->htab = NULL; 1541 } else { 1542 /* kernel-side HPT not needed, allocate in userspace instead */ 1543 size_t size = 1ULL << shift; 1544 int i; 1545 1546 spapr->htab = qemu_memalign(size, size); 1547 if (!spapr->htab) { 1548 error_setg_errno(errp, errno, 1549 "Could not allocate HPT of order %d", shift); 1550 return; 1551 } 1552 1553 memset(spapr->htab, 0, size); 1554 spapr->htab_shift = shift; 1555 1556 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1557 DIRTY_HPTE(HPTE(spapr->htab, i)); 1558 } 1559 } 1560 /* We're setting up a hash table, so that means we're not radix */ 1561 spapr->patb_entry = 0; 1562 } 1563 1564 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1565 { 1566 int hpt_shift; 1567 1568 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1569 || (spapr->cas_reboot 1570 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1571 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1572 } else { 1573 uint64_t current_ram_size; 1574 1575 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1576 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1577 } 1578 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1579 1580 if (spapr->vrma_adjust) { 1581 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1582 spapr->htab_shift); 1583 } 1584 } 1585 1586 static int spapr_reset_drcs(Object *child, void *opaque) 1587 { 1588 sPAPRDRConnector *drc = 1589 (sPAPRDRConnector *) object_dynamic_cast(child, 1590 TYPE_SPAPR_DR_CONNECTOR); 1591 1592 if (drc) { 1593 spapr_drc_reset(drc); 1594 } 1595 1596 return 0; 1597 } 1598 1599 static void spapr_machine_reset(void) 1600 { 1601 MachineState *machine = MACHINE(qdev_get_machine()); 1602 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1603 PowerPCCPU *first_ppc_cpu; 1604 uint32_t rtas_limit; 1605 hwaddr rtas_addr, fdt_addr; 1606 void *fdt; 1607 int rc; 1608 1609 spapr_caps_reset(spapr); 1610 1611 first_ppc_cpu = POWERPC_CPU(first_cpu); 1612 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1613 ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1614 spapr->max_compat_pvr)) { 1615 /* If using KVM with radix mode available, VCPUs can be started 1616 * without a HPT because KVM will start them in radix mode. 1617 * Set the GR bit in PATB so that we know there is no HPT. */ 1618 spapr->patb_entry = PATBE1_GR; 1619 } else { 1620 spapr_setup_hpt_and_vrma(spapr); 1621 } 1622 1623 /* if this reset wasn't generated by CAS, we should reset our 1624 * negotiated options and start from scratch */ 1625 if (!spapr->cas_reboot) { 1626 spapr_ovec_cleanup(spapr->ov5_cas); 1627 spapr->ov5_cas = spapr_ovec_new(); 1628 1629 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); 1630 } 1631 1632 qemu_devices_reset(); 1633 1634 /* DRC reset may cause a device to be unplugged. This will cause troubles 1635 * if this device is used by another device (eg, a running vhost backend 1636 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1637 * situations, we reset DRCs after all devices have been reset. 1638 */ 1639 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1640 1641 spapr_clear_pending_events(spapr); 1642 1643 /* 1644 * We place the device tree and RTAS just below either the top of the RMA, 1645 * or just below 2GB, whichever is lowere, so that it can be 1646 * processed with 32-bit real mode code if necessary 1647 */ 1648 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1649 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1650 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1651 1652 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1653 1654 spapr_load_rtas(spapr, fdt, rtas_addr); 1655 1656 rc = fdt_pack(fdt); 1657 1658 /* Should only fail if we've built a corrupted tree */ 1659 assert(rc == 0); 1660 1661 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1662 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1663 fdt_totalsize(fdt), FDT_MAX_SIZE); 1664 exit(1); 1665 } 1666 1667 /* Load the fdt */ 1668 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1669 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1670 g_free(fdt); 1671 1672 /* Set up the entry state */ 1673 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); 1674 first_ppc_cpu->env.gpr[5] = 0; 1675 1676 spapr->cas_reboot = false; 1677 } 1678 1679 static void spapr_create_nvram(sPAPRMachineState *spapr) 1680 { 1681 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1682 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1683 1684 if (dinfo) { 1685 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1686 &error_fatal); 1687 } 1688 1689 qdev_init_nofail(dev); 1690 1691 spapr->nvram = (struct sPAPRNVRAM *)dev; 1692 } 1693 1694 static void spapr_rtc_create(sPAPRMachineState *spapr) 1695 { 1696 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1697 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1698 &error_fatal); 1699 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1700 &error_fatal); 1701 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1702 "date", &error_fatal); 1703 } 1704 1705 /* Returns whether we want to use VGA or not */ 1706 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1707 { 1708 switch (vga_interface_type) { 1709 case VGA_NONE: 1710 return false; 1711 case VGA_DEVICE: 1712 return true; 1713 case VGA_STD: 1714 case VGA_VIRTIO: 1715 return pci_vga_init(pci_bus) != NULL; 1716 default: 1717 error_setg(errp, 1718 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1719 return false; 1720 } 1721 } 1722 1723 static int spapr_pre_load(void *opaque) 1724 { 1725 int rc; 1726 1727 rc = spapr_caps_pre_load(opaque); 1728 if (rc) { 1729 return rc; 1730 } 1731 1732 return 0; 1733 } 1734 1735 static int spapr_post_load(void *opaque, int version_id) 1736 { 1737 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1738 int err = 0; 1739 1740 err = spapr_caps_post_migration(spapr); 1741 if (err) { 1742 return err; 1743 } 1744 1745 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1746 CPUState *cs; 1747 CPU_FOREACH(cs) { 1748 PowerPCCPU *cpu = POWERPC_CPU(cs); 1749 icp_resend(ICP(cpu->intc)); 1750 } 1751 } 1752 1753 /* In earlier versions, there was no separate qdev for the PAPR 1754 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1755 * So when migrating from those versions, poke the incoming offset 1756 * value into the RTC device */ 1757 if (version_id < 3) { 1758 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1759 } 1760 1761 if (kvm_enabled() && spapr->patb_entry) { 1762 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1763 bool radix = !!(spapr->patb_entry & PATBE1_GR); 1764 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1765 1766 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1767 if (err) { 1768 error_report("Process table config unsupported by the host"); 1769 return -EINVAL; 1770 } 1771 } 1772 1773 return err; 1774 } 1775 1776 static int spapr_pre_save(void *opaque) 1777 { 1778 int rc; 1779 1780 rc = spapr_caps_pre_save(opaque); 1781 if (rc) { 1782 return rc; 1783 } 1784 1785 return 0; 1786 } 1787 1788 static bool version_before_3(void *opaque, int version_id) 1789 { 1790 return version_id < 3; 1791 } 1792 1793 static bool spapr_pending_events_needed(void *opaque) 1794 { 1795 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1796 return !QTAILQ_EMPTY(&spapr->pending_events); 1797 } 1798 1799 static const VMStateDescription vmstate_spapr_event_entry = { 1800 .name = "spapr_event_log_entry", 1801 .version_id = 1, 1802 .minimum_version_id = 1, 1803 .fields = (VMStateField[]) { 1804 VMSTATE_UINT32(summary, sPAPREventLogEntry), 1805 VMSTATE_UINT32(extended_length, sPAPREventLogEntry), 1806 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, 1807 NULL, extended_length), 1808 VMSTATE_END_OF_LIST() 1809 }, 1810 }; 1811 1812 static const VMStateDescription vmstate_spapr_pending_events = { 1813 .name = "spapr_pending_events", 1814 .version_id = 1, 1815 .minimum_version_id = 1, 1816 .needed = spapr_pending_events_needed, 1817 .fields = (VMStateField[]) { 1818 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, 1819 vmstate_spapr_event_entry, sPAPREventLogEntry, next), 1820 VMSTATE_END_OF_LIST() 1821 }, 1822 }; 1823 1824 static bool spapr_ov5_cas_needed(void *opaque) 1825 { 1826 sPAPRMachineState *spapr = opaque; 1827 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1828 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1829 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1830 bool cas_needed; 1831 1832 /* Prior to the introduction of sPAPROptionVector, we had two option 1833 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1834 * Both of these options encode machine topology into the device-tree 1835 * in such a way that the now-booted OS should still be able to interact 1836 * appropriately with QEMU regardless of what options were actually 1837 * negotiatied on the source side. 1838 * 1839 * As such, we can avoid migrating the CAS-negotiated options if these 1840 * are the only options available on the current machine/platform. 1841 * Since these are the only options available for pseries-2.7 and 1842 * earlier, this allows us to maintain old->new/new->old migration 1843 * compatibility. 1844 * 1845 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1846 * via default pseries-2.8 machines and explicit command-line parameters. 1847 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1848 * of the actual CAS-negotiated values to continue working properly. For 1849 * example, availability of memory unplug depends on knowing whether 1850 * OV5_HP_EVT was negotiated via CAS. 1851 * 1852 * Thus, for any cases where the set of available CAS-negotiatable 1853 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1854 * include the CAS-negotiated options in the migration stream, unless 1855 * if they affect boot time behaviour only. 1856 */ 1857 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1858 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1859 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1860 1861 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1862 * the mask itself since in the future it's possible "legacy" bits may be 1863 * removed via machine options, which could generate a false positive 1864 * that breaks migration. 1865 */ 1866 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1867 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1868 1869 spapr_ovec_cleanup(ov5_mask); 1870 spapr_ovec_cleanup(ov5_legacy); 1871 spapr_ovec_cleanup(ov5_removed); 1872 1873 return cas_needed; 1874 } 1875 1876 static const VMStateDescription vmstate_spapr_ov5_cas = { 1877 .name = "spapr_option_vector_ov5_cas", 1878 .version_id = 1, 1879 .minimum_version_id = 1, 1880 .needed = spapr_ov5_cas_needed, 1881 .fields = (VMStateField[]) { 1882 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1883 vmstate_spapr_ovec, sPAPROptionVector), 1884 VMSTATE_END_OF_LIST() 1885 }, 1886 }; 1887 1888 static bool spapr_patb_entry_needed(void *opaque) 1889 { 1890 sPAPRMachineState *spapr = opaque; 1891 1892 return !!spapr->patb_entry; 1893 } 1894 1895 static const VMStateDescription vmstate_spapr_patb_entry = { 1896 .name = "spapr_patb_entry", 1897 .version_id = 1, 1898 .minimum_version_id = 1, 1899 .needed = spapr_patb_entry_needed, 1900 .fields = (VMStateField[]) { 1901 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1902 VMSTATE_END_OF_LIST() 1903 }, 1904 }; 1905 1906 static const VMStateDescription vmstate_spapr = { 1907 .name = "spapr", 1908 .version_id = 3, 1909 .minimum_version_id = 1, 1910 .pre_load = spapr_pre_load, 1911 .post_load = spapr_post_load, 1912 .pre_save = spapr_pre_save, 1913 .fields = (VMStateField[]) { 1914 /* used to be @next_irq */ 1915 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1916 1917 /* RTC offset */ 1918 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1919 1920 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1921 VMSTATE_END_OF_LIST() 1922 }, 1923 .subsections = (const VMStateDescription*[]) { 1924 &vmstate_spapr_ov5_cas, 1925 &vmstate_spapr_patb_entry, 1926 &vmstate_spapr_pending_events, 1927 &vmstate_spapr_cap_htm, 1928 &vmstate_spapr_cap_vsx, 1929 &vmstate_spapr_cap_dfp, 1930 &vmstate_spapr_cap_cfpc, 1931 &vmstate_spapr_cap_sbbc, 1932 &vmstate_spapr_cap_ibs, 1933 NULL 1934 } 1935 }; 1936 1937 static int htab_save_setup(QEMUFile *f, void *opaque) 1938 { 1939 sPAPRMachineState *spapr = opaque; 1940 1941 /* "Iteration" header */ 1942 if (!spapr->htab_shift) { 1943 qemu_put_be32(f, -1); 1944 } else { 1945 qemu_put_be32(f, spapr->htab_shift); 1946 } 1947 1948 if (spapr->htab) { 1949 spapr->htab_save_index = 0; 1950 spapr->htab_first_pass = true; 1951 } else { 1952 if (spapr->htab_shift) { 1953 assert(kvm_enabled()); 1954 } 1955 } 1956 1957 1958 return 0; 1959 } 1960 1961 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr, 1962 int chunkstart, int n_valid, int n_invalid) 1963 { 1964 qemu_put_be32(f, chunkstart); 1965 qemu_put_be16(f, n_valid); 1966 qemu_put_be16(f, n_invalid); 1967 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1968 HASH_PTE_SIZE_64 * n_valid); 1969 } 1970 1971 static void htab_save_end_marker(QEMUFile *f) 1972 { 1973 qemu_put_be32(f, 0); 1974 qemu_put_be16(f, 0); 1975 qemu_put_be16(f, 0); 1976 } 1977 1978 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1979 int64_t max_ns) 1980 { 1981 bool has_timeout = max_ns != -1; 1982 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1983 int index = spapr->htab_save_index; 1984 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1985 1986 assert(spapr->htab_first_pass); 1987 1988 do { 1989 int chunkstart; 1990 1991 /* Consume invalid HPTEs */ 1992 while ((index < htabslots) 1993 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1994 CLEAN_HPTE(HPTE(spapr->htab, index)); 1995 index++; 1996 } 1997 1998 /* Consume valid HPTEs */ 1999 chunkstart = index; 2000 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2001 && HPTE_VALID(HPTE(spapr->htab, index))) { 2002 CLEAN_HPTE(HPTE(spapr->htab, index)); 2003 index++; 2004 } 2005 2006 if (index > chunkstart) { 2007 int n_valid = index - chunkstart; 2008 2009 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2010 2011 if (has_timeout && 2012 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2013 break; 2014 } 2015 } 2016 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2017 2018 if (index >= htabslots) { 2019 assert(index == htabslots); 2020 index = 0; 2021 spapr->htab_first_pass = false; 2022 } 2023 spapr->htab_save_index = index; 2024 } 2025 2026 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 2027 int64_t max_ns) 2028 { 2029 bool final = max_ns < 0; 2030 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2031 int examined = 0, sent = 0; 2032 int index = spapr->htab_save_index; 2033 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2034 2035 assert(!spapr->htab_first_pass); 2036 2037 do { 2038 int chunkstart, invalidstart; 2039 2040 /* Consume non-dirty HPTEs */ 2041 while ((index < htabslots) 2042 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2043 index++; 2044 examined++; 2045 } 2046 2047 chunkstart = index; 2048 /* Consume valid dirty HPTEs */ 2049 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2050 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2051 && HPTE_VALID(HPTE(spapr->htab, index))) { 2052 CLEAN_HPTE(HPTE(spapr->htab, index)); 2053 index++; 2054 examined++; 2055 } 2056 2057 invalidstart = index; 2058 /* Consume invalid dirty HPTEs */ 2059 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2060 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2061 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2062 CLEAN_HPTE(HPTE(spapr->htab, index)); 2063 index++; 2064 examined++; 2065 } 2066 2067 if (index > chunkstart) { 2068 int n_valid = invalidstart - chunkstart; 2069 int n_invalid = index - invalidstart; 2070 2071 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2072 sent += index - chunkstart; 2073 2074 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2075 break; 2076 } 2077 } 2078 2079 if (examined >= htabslots) { 2080 break; 2081 } 2082 2083 if (index >= htabslots) { 2084 assert(index == htabslots); 2085 index = 0; 2086 } 2087 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2088 2089 if (index >= htabslots) { 2090 assert(index == htabslots); 2091 index = 0; 2092 } 2093 2094 spapr->htab_save_index = index; 2095 2096 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2097 } 2098 2099 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2100 #define MAX_KVM_BUF_SIZE 2048 2101 2102 static int htab_save_iterate(QEMUFile *f, void *opaque) 2103 { 2104 sPAPRMachineState *spapr = opaque; 2105 int fd; 2106 int rc = 0; 2107 2108 /* Iteration header */ 2109 if (!spapr->htab_shift) { 2110 qemu_put_be32(f, -1); 2111 return 1; 2112 } else { 2113 qemu_put_be32(f, 0); 2114 } 2115 2116 if (!spapr->htab) { 2117 assert(kvm_enabled()); 2118 2119 fd = get_htab_fd(spapr); 2120 if (fd < 0) { 2121 return fd; 2122 } 2123 2124 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2125 if (rc < 0) { 2126 return rc; 2127 } 2128 } else if (spapr->htab_first_pass) { 2129 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2130 } else { 2131 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2132 } 2133 2134 htab_save_end_marker(f); 2135 2136 return rc; 2137 } 2138 2139 static int htab_save_complete(QEMUFile *f, void *opaque) 2140 { 2141 sPAPRMachineState *spapr = opaque; 2142 int fd; 2143 2144 /* Iteration header */ 2145 if (!spapr->htab_shift) { 2146 qemu_put_be32(f, -1); 2147 return 0; 2148 } else { 2149 qemu_put_be32(f, 0); 2150 } 2151 2152 if (!spapr->htab) { 2153 int rc; 2154 2155 assert(kvm_enabled()); 2156 2157 fd = get_htab_fd(spapr); 2158 if (fd < 0) { 2159 return fd; 2160 } 2161 2162 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2163 if (rc < 0) { 2164 return rc; 2165 } 2166 } else { 2167 if (spapr->htab_first_pass) { 2168 htab_save_first_pass(f, spapr, -1); 2169 } 2170 htab_save_later_pass(f, spapr, -1); 2171 } 2172 2173 /* End marker */ 2174 htab_save_end_marker(f); 2175 2176 return 0; 2177 } 2178 2179 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2180 { 2181 sPAPRMachineState *spapr = opaque; 2182 uint32_t section_hdr; 2183 int fd = -1; 2184 Error *local_err = NULL; 2185 2186 if (version_id < 1 || version_id > 1) { 2187 error_report("htab_load() bad version"); 2188 return -EINVAL; 2189 } 2190 2191 section_hdr = qemu_get_be32(f); 2192 2193 if (section_hdr == -1) { 2194 spapr_free_hpt(spapr); 2195 return 0; 2196 } 2197 2198 if (section_hdr) { 2199 /* First section gives the htab size */ 2200 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2201 if (local_err) { 2202 error_report_err(local_err); 2203 return -EINVAL; 2204 } 2205 return 0; 2206 } 2207 2208 if (!spapr->htab) { 2209 assert(kvm_enabled()); 2210 2211 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2212 if (fd < 0) { 2213 error_report_err(local_err); 2214 return fd; 2215 } 2216 } 2217 2218 while (true) { 2219 uint32_t index; 2220 uint16_t n_valid, n_invalid; 2221 2222 index = qemu_get_be32(f); 2223 n_valid = qemu_get_be16(f); 2224 n_invalid = qemu_get_be16(f); 2225 2226 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2227 /* End of Stream */ 2228 break; 2229 } 2230 2231 if ((index + n_valid + n_invalid) > 2232 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2233 /* Bad index in stream */ 2234 error_report( 2235 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2236 index, n_valid, n_invalid, spapr->htab_shift); 2237 return -EINVAL; 2238 } 2239 2240 if (spapr->htab) { 2241 if (n_valid) { 2242 qemu_get_buffer(f, HPTE(spapr->htab, index), 2243 HASH_PTE_SIZE_64 * n_valid); 2244 } 2245 if (n_invalid) { 2246 memset(HPTE(spapr->htab, index + n_valid), 0, 2247 HASH_PTE_SIZE_64 * n_invalid); 2248 } 2249 } else { 2250 int rc; 2251 2252 assert(fd >= 0); 2253 2254 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2255 if (rc < 0) { 2256 return rc; 2257 } 2258 } 2259 } 2260 2261 if (!spapr->htab) { 2262 assert(fd >= 0); 2263 close(fd); 2264 } 2265 2266 return 0; 2267 } 2268 2269 static void htab_save_cleanup(void *opaque) 2270 { 2271 sPAPRMachineState *spapr = opaque; 2272 2273 close_htab_fd(spapr); 2274 } 2275 2276 static SaveVMHandlers savevm_htab_handlers = { 2277 .save_setup = htab_save_setup, 2278 .save_live_iterate = htab_save_iterate, 2279 .save_live_complete_precopy = htab_save_complete, 2280 .save_cleanup = htab_save_cleanup, 2281 .load_state = htab_load, 2282 }; 2283 2284 static void spapr_boot_set(void *opaque, const char *boot_device, 2285 Error **errp) 2286 { 2287 MachineState *machine = MACHINE(opaque); 2288 machine->boot_order = g_strdup(boot_device); 2289 } 2290 2291 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 2292 { 2293 MachineState *machine = MACHINE(spapr); 2294 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2295 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2296 int i; 2297 2298 for (i = 0; i < nr_lmbs; i++) { 2299 uint64_t addr; 2300 2301 addr = i * lmb_size + machine->device_memory->base; 2302 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2303 addr / lmb_size); 2304 } 2305 } 2306 2307 /* 2308 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2309 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2310 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2311 */ 2312 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2313 { 2314 int i; 2315 2316 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2317 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2318 " is not aligned to %llu MiB", 2319 machine->ram_size, 2320 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2321 return; 2322 } 2323 2324 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2325 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2326 " is not aligned to %llu MiB", 2327 machine->ram_size, 2328 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2329 return; 2330 } 2331 2332 for (i = 0; i < nb_numa_nodes; i++) { 2333 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2334 error_setg(errp, 2335 "Node %d memory size 0x%" PRIx64 2336 " is not aligned to %llu MiB", 2337 i, numa_info[i].node_mem, 2338 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2339 return; 2340 } 2341 } 2342 } 2343 2344 /* find cpu slot in machine->possible_cpus by core_id */ 2345 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2346 { 2347 int index = id / smp_threads; 2348 2349 if (index >= ms->possible_cpus->len) { 2350 return NULL; 2351 } 2352 if (idx) { 2353 *idx = index; 2354 } 2355 return &ms->possible_cpus->cpus[index]; 2356 } 2357 2358 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) 2359 { 2360 Error *local_err = NULL; 2361 bool vsmt_user = !!spapr->vsmt; 2362 int kvm_smt = kvmppc_smt_threads(); 2363 int ret; 2364 2365 if (!kvm_enabled() && (smp_threads > 1)) { 2366 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2367 "on a pseries machine"); 2368 goto out; 2369 } 2370 if (!is_power_of_2(smp_threads)) { 2371 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2372 "machine because it must be a power of 2", smp_threads); 2373 goto out; 2374 } 2375 2376 /* Detemine the VSMT mode to use: */ 2377 if (vsmt_user) { 2378 if (spapr->vsmt < smp_threads) { 2379 error_setg(&local_err, "Cannot support VSMT mode %d" 2380 " because it must be >= threads/core (%d)", 2381 spapr->vsmt, smp_threads); 2382 goto out; 2383 } 2384 /* In this case, spapr->vsmt has been set by the command line */ 2385 } else { 2386 /* 2387 * Default VSMT value is tricky, because we need it to be as 2388 * consistent as possible (for migration), but this requires 2389 * changing it for at least some existing cases. We pick 8 as 2390 * the value that we'd get with KVM on POWER8, the 2391 * overwhelmingly common case in production systems. 2392 */ 2393 spapr->vsmt = MAX(8, smp_threads); 2394 } 2395 2396 /* KVM: If necessary, set the SMT mode: */ 2397 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2398 ret = kvmppc_set_smt_threads(spapr->vsmt); 2399 if (ret) { 2400 /* Looks like KVM isn't able to change VSMT mode */ 2401 error_setg(&local_err, 2402 "Failed to set KVM's VSMT mode to %d (errno %d)", 2403 spapr->vsmt, ret); 2404 /* We can live with that if the default one is big enough 2405 * for the number of threads, and a submultiple of the one 2406 * we want. In this case we'll waste some vcpu ids, but 2407 * behaviour will be correct */ 2408 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2409 warn_report_err(local_err); 2410 local_err = NULL; 2411 goto out; 2412 } else { 2413 if (!vsmt_user) { 2414 error_append_hint(&local_err, 2415 "On PPC, a VM with %d threads/core" 2416 " on a host with %d threads/core" 2417 " requires the use of VSMT mode %d.\n", 2418 smp_threads, kvm_smt, spapr->vsmt); 2419 } 2420 kvmppc_hint_smt_possible(&local_err); 2421 goto out; 2422 } 2423 } 2424 } 2425 /* else TCG: nothing to do currently */ 2426 out: 2427 error_propagate(errp, local_err); 2428 } 2429 2430 static void spapr_init_cpus(sPAPRMachineState *spapr) 2431 { 2432 MachineState *machine = MACHINE(spapr); 2433 MachineClass *mc = MACHINE_GET_CLASS(machine); 2434 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2435 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2436 const CPUArchIdList *possible_cpus; 2437 int boot_cores_nr = smp_cpus / smp_threads; 2438 int i; 2439 2440 possible_cpus = mc->possible_cpu_arch_ids(machine); 2441 if (mc->has_hotpluggable_cpus) { 2442 if (smp_cpus % smp_threads) { 2443 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2444 smp_cpus, smp_threads); 2445 exit(1); 2446 } 2447 if (max_cpus % smp_threads) { 2448 error_report("max_cpus (%u) must be multiple of threads (%u)", 2449 max_cpus, smp_threads); 2450 exit(1); 2451 } 2452 } else { 2453 if (max_cpus != smp_cpus) { 2454 error_report("This machine version does not support CPU hotplug"); 2455 exit(1); 2456 } 2457 boot_cores_nr = possible_cpus->len; 2458 } 2459 2460 /* VSMT must be set in order to be able to compute VCPU ids, ie to 2461 * call xics_max_server_number() or spapr_vcpu_id(). 2462 */ 2463 spapr_set_vsmt_mode(spapr, &error_fatal); 2464 2465 if (smc->pre_2_10_has_unused_icps) { 2466 int i; 2467 2468 for (i = 0; i < xics_max_server_number(spapr); i++) { 2469 /* Dummy entries get deregistered when real ICPState objects 2470 * are registered during CPU core hotplug. 2471 */ 2472 pre_2_10_vmstate_register_dummy_icp(i); 2473 } 2474 } 2475 2476 for (i = 0; i < possible_cpus->len; i++) { 2477 int core_id = i * smp_threads; 2478 2479 if (mc->has_hotpluggable_cpus) { 2480 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2481 spapr_vcpu_id(spapr, core_id)); 2482 } 2483 2484 if (i < boot_cores_nr) { 2485 Object *core = object_new(type); 2486 int nr_threads = smp_threads; 2487 2488 /* Handle the partially filled core for older machine types */ 2489 if ((i + 1) * smp_threads >= smp_cpus) { 2490 nr_threads = smp_cpus - i * smp_threads; 2491 } 2492 2493 object_property_set_int(core, nr_threads, "nr-threads", 2494 &error_fatal); 2495 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2496 &error_fatal); 2497 object_property_set_bool(core, true, "realized", &error_fatal); 2498 } 2499 } 2500 } 2501 2502 /* pSeries LPAR / sPAPR hardware init */ 2503 static void spapr_machine_init(MachineState *machine) 2504 { 2505 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2506 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2507 const char *kernel_filename = machine->kernel_filename; 2508 const char *initrd_filename = machine->initrd_filename; 2509 PCIHostState *phb; 2510 int i; 2511 MemoryRegion *sysmem = get_system_memory(); 2512 MemoryRegion *ram = g_new(MemoryRegion, 1); 2513 hwaddr node0_size = spapr_node0_size(machine); 2514 long load_limit, fw_size; 2515 char *filename; 2516 Error *resize_hpt_err = NULL; 2517 PowerPCCPU *first_ppc_cpu; 2518 2519 msi_nonbroken = true; 2520 2521 QLIST_INIT(&spapr->phbs); 2522 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2523 2524 /* Check HPT resizing availability */ 2525 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2526 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2527 /* 2528 * If the user explicitly requested a mode we should either 2529 * supply it, or fail completely (which we do below). But if 2530 * it's not set explicitly, we reset our mode to something 2531 * that works 2532 */ 2533 if (resize_hpt_err) { 2534 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2535 error_free(resize_hpt_err); 2536 resize_hpt_err = NULL; 2537 } else { 2538 spapr->resize_hpt = smc->resize_hpt_default; 2539 } 2540 } 2541 2542 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2543 2544 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2545 /* 2546 * User requested HPT resize, but this host can't supply it. Bail out 2547 */ 2548 error_report_err(resize_hpt_err); 2549 exit(1); 2550 } 2551 2552 spapr->rma_size = node0_size; 2553 2554 /* With KVM, we don't actually know whether KVM supports an 2555 * unbounded RMA (PR KVM) or is limited by the hash table size 2556 * (HV KVM using VRMA), so we always assume the latter 2557 * 2558 * In that case, we also limit the initial allocations for RTAS 2559 * etc... to 256M since we have no way to know what the VRMA size 2560 * is going to be as it depends on the size of the hash table 2561 * which isn't determined yet. 2562 */ 2563 if (kvm_enabled()) { 2564 spapr->vrma_adjust = 1; 2565 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2566 } 2567 2568 /* Actually we don't support unbounded RMA anymore since we added 2569 * proper emulation of HV mode. The max we can get is 16G which 2570 * also happens to be what we configure for PAPR mode so make sure 2571 * we don't do anything bigger than that 2572 */ 2573 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2574 2575 if (spapr->rma_size > node0_size) { 2576 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2577 spapr->rma_size); 2578 exit(1); 2579 } 2580 2581 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2582 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2583 2584 /* Set up Interrupt Controller before we create the VCPUs */ 2585 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); 2586 2587 /* Set up containers for ibm,client-architecture-support negotiated options 2588 */ 2589 spapr->ov5 = spapr_ovec_new(); 2590 spapr->ov5_cas = spapr_ovec_new(); 2591 2592 if (smc->dr_lmb_enabled) { 2593 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2594 spapr_validate_node_memory(machine, &error_fatal); 2595 } 2596 2597 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2598 2599 /* advertise support for dedicated HP event source to guests */ 2600 if (spapr->use_hotplug_event_source) { 2601 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2602 } 2603 2604 /* advertise support for HPT resizing */ 2605 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2606 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2607 } 2608 2609 /* advertise support for ibm,dyamic-memory-v2 */ 2610 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2611 2612 /* init CPUs */ 2613 spapr_init_cpus(spapr); 2614 2615 first_ppc_cpu = POWERPC_CPU(first_cpu); 2616 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2617 ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 2618 spapr->max_compat_pvr)) { 2619 /* KVM and TCG always allow GTSE with radix... */ 2620 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2621 } 2622 /* ... but not with hash (currently). */ 2623 2624 if (kvm_enabled()) { 2625 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2626 kvmppc_enable_logical_ci_hcalls(); 2627 kvmppc_enable_set_mode_hcall(); 2628 2629 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2630 kvmppc_enable_clear_ref_mod_hcalls(); 2631 } 2632 2633 /* allocate RAM */ 2634 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2635 machine->ram_size); 2636 memory_region_add_subregion(sysmem, 0, ram); 2637 2638 /* always allocate the device memory information */ 2639 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2640 2641 /* initialize hotplug memory address space */ 2642 if (machine->ram_size < machine->maxram_size) { 2643 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2644 /* 2645 * Limit the number of hotpluggable memory slots to half the number 2646 * slots that KVM supports, leaving the other half for PCI and other 2647 * devices. However ensure that number of slots doesn't drop below 32. 2648 */ 2649 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2650 SPAPR_MAX_RAM_SLOTS; 2651 2652 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2653 max_memslots = SPAPR_MAX_RAM_SLOTS; 2654 } 2655 if (machine->ram_slots > max_memslots) { 2656 error_report("Specified number of memory slots %" 2657 PRIu64" exceeds max supported %d", 2658 machine->ram_slots, max_memslots); 2659 exit(1); 2660 } 2661 2662 machine->device_memory->base = ROUND_UP(machine->ram_size, 2663 SPAPR_DEVICE_MEM_ALIGN); 2664 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2665 "device-memory", device_mem_size); 2666 memory_region_add_subregion(sysmem, machine->device_memory->base, 2667 &machine->device_memory->mr); 2668 } 2669 2670 if (smc->dr_lmb_enabled) { 2671 spapr_create_lmb_dr_connectors(spapr); 2672 } 2673 2674 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2675 if (!filename) { 2676 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2677 exit(1); 2678 } 2679 spapr->rtas_size = get_image_size(filename); 2680 if (spapr->rtas_size < 0) { 2681 error_report("Could not get size of LPAR rtas '%s'", filename); 2682 exit(1); 2683 } 2684 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2685 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2686 error_report("Could not load LPAR rtas '%s'", filename); 2687 exit(1); 2688 } 2689 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2690 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2691 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2692 exit(1); 2693 } 2694 g_free(filename); 2695 2696 /* Set up RTAS event infrastructure */ 2697 spapr_events_init(spapr); 2698 2699 /* Set up the RTC RTAS interfaces */ 2700 spapr_rtc_create(spapr); 2701 2702 /* Set up VIO bus */ 2703 spapr->vio_bus = spapr_vio_bus_init(); 2704 2705 for (i = 0; i < serial_max_hds(); i++) { 2706 if (serial_hd(i)) { 2707 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2708 } 2709 } 2710 2711 /* We always have at least the nvram device on VIO */ 2712 spapr_create_nvram(spapr); 2713 2714 /* Set up PCI */ 2715 spapr_pci_rtas_init(); 2716 2717 phb = spapr_create_phb(spapr, 0); 2718 2719 for (i = 0; i < nb_nics; i++) { 2720 NICInfo *nd = &nd_table[i]; 2721 2722 if (!nd->model) { 2723 nd->model = g_strdup("spapr-vlan"); 2724 } 2725 2726 if (g_str_equal(nd->model, "spapr-vlan") || 2727 g_str_equal(nd->model, "ibmveth")) { 2728 spapr_vlan_create(spapr->vio_bus, nd); 2729 } else { 2730 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2731 } 2732 } 2733 2734 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2735 spapr_vscsi_create(spapr->vio_bus); 2736 } 2737 2738 /* Graphics */ 2739 if (spapr_vga_init(phb->bus, &error_fatal)) { 2740 spapr->has_graphics = true; 2741 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2742 } 2743 2744 if (machine->usb) { 2745 if (smc->use_ohci_by_default) { 2746 pci_create_simple(phb->bus, -1, "pci-ohci"); 2747 } else { 2748 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2749 } 2750 2751 if (spapr->has_graphics) { 2752 USBBus *usb_bus = usb_bus_find(-1); 2753 2754 usb_create_simple(usb_bus, "usb-kbd"); 2755 usb_create_simple(usb_bus, "usb-mouse"); 2756 } 2757 } 2758 2759 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2760 error_report( 2761 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2762 MIN_RMA_SLOF); 2763 exit(1); 2764 } 2765 2766 if (kernel_filename) { 2767 uint64_t lowaddr = 0; 2768 2769 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2770 NULL, NULL, &lowaddr, NULL, 1, 2771 PPC_ELF_MACHINE, 0, 0); 2772 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2773 spapr->kernel_size = load_elf(kernel_filename, 2774 translate_kernel_address, NULL, NULL, 2775 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2776 0, 0); 2777 spapr->kernel_le = spapr->kernel_size > 0; 2778 } 2779 if (spapr->kernel_size < 0) { 2780 error_report("error loading %s: %s", kernel_filename, 2781 load_elf_strerror(spapr->kernel_size)); 2782 exit(1); 2783 } 2784 2785 /* load initrd */ 2786 if (initrd_filename) { 2787 /* Try to locate the initrd in the gap between the kernel 2788 * and the firmware. Add a bit of space just in case 2789 */ 2790 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2791 + 0x1ffff) & ~0xffff; 2792 spapr->initrd_size = load_image_targphys(initrd_filename, 2793 spapr->initrd_base, 2794 load_limit 2795 - spapr->initrd_base); 2796 if (spapr->initrd_size < 0) { 2797 error_report("could not load initial ram disk '%s'", 2798 initrd_filename); 2799 exit(1); 2800 } 2801 } 2802 } 2803 2804 if (bios_name == NULL) { 2805 bios_name = FW_FILE_NAME; 2806 } 2807 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2808 if (!filename) { 2809 error_report("Could not find LPAR firmware '%s'", bios_name); 2810 exit(1); 2811 } 2812 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2813 if (fw_size <= 0) { 2814 error_report("Could not load LPAR firmware '%s'", filename); 2815 exit(1); 2816 } 2817 g_free(filename); 2818 2819 /* FIXME: Should register things through the MachineState's qdev 2820 * interface, this is a legacy from the sPAPREnvironment structure 2821 * which predated MachineState but had a similar function */ 2822 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2823 register_savevm_live(NULL, "spapr/htab", -1, 1, 2824 &savevm_htab_handlers, spapr); 2825 2826 qemu_register_boot_set(spapr_boot_set, spapr); 2827 2828 if (kvm_enabled()) { 2829 /* to stop and start vmclock */ 2830 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2831 &spapr->tb); 2832 2833 kvmppc_spapr_enable_inkernel_multitce(); 2834 } 2835 } 2836 2837 static int spapr_kvm_type(const char *vm_type) 2838 { 2839 if (!vm_type) { 2840 return 0; 2841 } 2842 2843 if (!strcmp(vm_type, "HV")) { 2844 return 1; 2845 } 2846 2847 if (!strcmp(vm_type, "PR")) { 2848 return 2; 2849 } 2850 2851 error_report("Unknown kvm-type specified '%s'", vm_type); 2852 exit(1); 2853 } 2854 2855 /* 2856 * Implementation of an interface to adjust firmware path 2857 * for the bootindex property handling. 2858 */ 2859 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2860 DeviceState *dev) 2861 { 2862 #define CAST(type, obj, name) \ 2863 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2864 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2865 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2866 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 2867 2868 if (d) { 2869 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2870 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2871 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2872 2873 if (spapr) { 2874 /* 2875 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2876 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2877 * in the top 16 bits of the 64-bit LUN 2878 */ 2879 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2880 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2881 (uint64_t)id << 48); 2882 } else if (virtio) { 2883 /* 2884 * We use SRP luns of the form 01000000 | (target << 8) | lun 2885 * in the top 32 bits of the 64-bit LUN 2886 * Note: the quote above is from SLOF and it is wrong, 2887 * the actual binding is: 2888 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2889 */ 2890 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2891 if (d->lun >= 256) { 2892 /* Use the LUN "flat space addressing method" */ 2893 id |= 0x4000; 2894 } 2895 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2896 (uint64_t)id << 32); 2897 } else if (usb) { 2898 /* 2899 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2900 * in the top 32 bits of the 64-bit LUN 2901 */ 2902 unsigned usb_port = atoi(usb->port->path); 2903 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2904 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2905 (uint64_t)id << 32); 2906 } 2907 } 2908 2909 /* 2910 * SLOF probes the USB devices, and if it recognizes that the device is a 2911 * storage device, it changes its name to "storage" instead of "usb-host", 2912 * and additionally adds a child node for the SCSI LUN, so the correct 2913 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2914 */ 2915 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2916 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2917 if (usb_host_dev_is_scsi_storage(usbdev)) { 2918 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2919 } 2920 } 2921 2922 if (phb) { 2923 /* Replace "pci" with "pci@800000020000000" */ 2924 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2925 } 2926 2927 if (vsc) { 2928 /* Same logic as virtio above */ 2929 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 2930 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 2931 } 2932 2933 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 2934 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 2935 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 2936 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 2937 } 2938 2939 return NULL; 2940 } 2941 2942 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2943 { 2944 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2945 2946 return g_strdup(spapr->kvm_type); 2947 } 2948 2949 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2950 { 2951 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2952 2953 g_free(spapr->kvm_type); 2954 spapr->kvm_type = g_strdup(value); 2955 } 2956 2957 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2958 { 2959 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2960 2961 return spapr->use_hotplug_event_source; 2962 } 2963 2964 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2965 Error **errp) 2966 { 2967 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2968 2969 spapr->use_hotplug_event_source = value; 2970 } 2971 2972 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 2973 { 2974 return true; 2975 } 2976 2977 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 2978 { 2979 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2980 2981 switch (spapr->resize_hpt) { 2982 case SPAPR_RESIZE_HPT_DEFAULT: 2983 return g_strdup("default"); 2984 case SPAPR_RESIZE_HPT_DISABLED: 2985 return g_strdup("disabled"); 2986 case SPAPR_RESIZE_HPT_ENABLED: 2987 return g_strdup("enabled"); 2988 case SPAPR_RESIZE_HPT_REQUIRED: 2989 return g_strdup("required"); 2990 } 2991 g_assert_not_reached(); 2992 } 2993 2994 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 2995 { 2996 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2997 2998 if (strcmp(value, "default") == 0) { 2999 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3000 } else if (strcmp(value, "disabled") == 0) { 3001 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3002 } else if (strcmp(value, "enabled") == 0) { 3003 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3004 } else if (strcmp(value, "required") == 0) { 3005 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3006 } else { 3007 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3008 } 3009 } 3010 3011 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3012 void *opaque, Error **errp) 3013 { 3014 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3015 } 3016 3017 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3018 void *opaque, Error **errp) 3019 { 3020 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3021 } 3022 3023 static void spapr_instance_init(Object *obj) 3024 { 3025 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3026 3027 spapr->htab_fd = -1; 3028 spapr->use_hotplug_event_source = true; 3029 object_property_add_str(obj, "kvm-type", 3030 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3031 object_property_set_description(obj, "kvm-type", 3032 "Specifies the KVM virtualization mode (HV, PR)", 3033 NULL); 3034 object_property_add_bool(obj, "modern-hotplug-events", 3035 spapr_get_modern_hotplug_events, 3036 spapr_set_modern_hotplug_events, 3037 NULL); 3038 object_property_set_description(obj, "modern-hotplug-events", 3039 "Use dedicated hotplug event mechanism in" 3040 " place of standard EPOW events when possible" 3041 " (required for memory hot-unplug support)", 3042 NULL); 3043 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3044 "Maximum permitted CPU compatibility mode", 3045 &error_fatal); 3046 3047 object_property_add_str(obj, "resize-hpt", 3048 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3049 object_property_set_description(obj, "resize-hpt", 3050 "Resizing of the Hash Page Table (enabled, disabled, required)", 3051 NULL); 3052 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3053 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3054 object_property_set_description(obj, "vsmt", 3055 "Virtual SMT: KVM behaves as if this were" 3056 " the host's SMT mode", &error_abort); 3057 object_property_add_bool(obj, "vfio-no-msix-emulation", 3058 spapr_get_msix_emulation, NULL, NULL); 3059 } 3060 3061 static void spapr_machine_finalizefn(Object *obj) 3062 { 3063 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3064 3065 g_free(spapr->kvm_type); 3066 } 3067 3068 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3069 { 3070 cpu_synchronize_state(cs); 3071 ppc_cpu_do_system_reset(cs); 3072 } 3073 3074 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3075 { 3076 CPUState *cs; 3077 3078 CPU_FOREACH(cs) { 3079 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3080 } 3081 } 3082 3083 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3084 uint32_t node, bool dedicated_hp_event_source, 3085 Error **errp) 3086 { 3087 sPAPRDRConnector *drc; 3088 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3089 int i, fdt_offset, fdt_size; 3090 void *fdt; 3091 uint64_t addr = addr_start; 3092 bool hotplugged = spapr_drc_hotplugged(dev); 3093 Error *local_err = NULL; 3094 3095 for (i = 0; i < nr_lmbs; i++) { 3096 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3097 addr / SPAPR_MEMORY_BLOCK_SIZE); 3098 g_assert(drc); 3099 3100 fdt = create_device_tree(&fdt_size); 3101 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 3102 SPAPR_MEMORY_BLOCK_SIZE); 3103 3104 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3105 if (local_err) { 3106 while (addr > addr_start) { 3107 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3108 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3109 addr / SPAPR_MEMORY_BLOCK_SIZE); 3110 spapr_drc_detach(drc); 3111 } 3112 g_free(fdt); 3113 error_propagate(errp, local_err); 3114 return; 3115 } 3116 if (!hotplugged) { 3117 spapr_drc_reset(drc); 3118 } 3119 addr += SPAPR_MEMORY_BLOCK_SIZE; 3120 } 3121 /* send hotplug notification to the 3122 * guest only in case of hotplugged memory 3123 */ 3124 if (hotplugged) { 3125 if (dedicated_hp_event_source) { 3126 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3127 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3128 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3129 nr_lmbs, 3130 spapr_drc_index(drc)); 3131 } else { 3132 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3133 nr_lmbs); 3134 } 3135 } 3136 } 3137 3138 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3139 Error **errp) 3140 { 3141 Error *local_err = NULL; 3142 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3143 PCDIMMDevice *dimm = PC_DIMM(dev); 3144 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3145 MemoryRegion *mr; 3146 uint64_t align, size, addr; 3147 uint32_t node; 3148 3149 mr = ddc->get_memory_region(dimm, &local_err); 3150 if (local_err) { 3151 goto out; 3152 } 3153 align = memory_region_get_alignment(mr); 3154 size = memory_region_size(mr); 3155 3156 pc_dimm_memory_plug(dev, MACHINE(ms), align, &local_err); 3157 if (local_err) { 3158 goto out; 3159 } 3160 3161 addr = object_property_get_uint(OBJECT(dimm), 3162 PC_DIMM_ADDR_PROP, &local_err); 3163 if (local_err) { 3164 goto out_unplug; 3165 } 3166 3167 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, 3168 &error_abort); 3169 spapr_add_lmbs(dev, addr, size, node, 3170 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3171 &local_err); 3172 if (local_err) { 3173 goto out_unplug; 3174 } 3175 3176 return; 3177 3178 out_unplug: 3179 pc_dimm_memory_unplug(dev, MACHINE(ms)); 3180 out: 3181 error_propagate(errp, local_err); 3182 } 3183 3184 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3185 Error **errp) 3186 { 3187 const sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3188 PCDIMMDevice *dimm = PC_DIMM(dev); 3189 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3190 MemoryRegion *mr; 3191 uint64_t size; 3192 char *mem_dev; 3193 3194 if (!smc->dr_lmb_enabled) { 3195 error_setg(errp, "Memory hotplug not supported for this machine"); 3196 return; 3197 } 3198 3199 mr = ddc->get_memory_region(dimm, errp); 3200 if (!mr) { 3201 return; 3202 } 3203 size = memory_region_size(mr); 3204 3205 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3206 error_setg(errp, "Hotplugged memory size must be a multiple of " 3207 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 3208 return; 3209 } 3210 3211 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 3212 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 3213 error_setg(errp, "Memory backend has bad page size. " 3214 "Use 'memory-backend-file' with correct mem-path."); 3215 goto out; 3216 } 3217 3218 out: 3219 g_free(mem_dev); 3220 } 3221 3222 struct sPAPRDIMMState { 3223 PCDIMMDevice *dimm; 3224 uint32_t nr_lmbs; 3225 QTAILQ_ENTRY(sPAPRDIMMState) next; 3226 }; 3227 3228 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 3229 PCDIMMDevice *dimm) 3230 { 3231 sPAPRDIMMState *dimm_state = NULL; 3232 3233 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3234 if (dimm_state->dimm == dimm) { 3235 break; 3236 } 3237 } 3238 return dimm_state; 3239 } 3240 3241 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 3242 uint32_t nr_lmbs, 3243 PCDIMMDevice *dimm) 3244 { 3245 sPAPRDIMMState *ds = NULL; 3246 3247 /* 3248 * If this request is for a DIMM whose removal had failed earlier 3249 * (due to guest's refusal to remove the LMBs), we would have this 3250 * dimm already in the pending_dimm_unplugs list. In that 3251 * case don't add again. 3252 */ 3253 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3254 if (!ds) { 3255 ds = g_malloc0(sizeof(sPAPRDIMMState)); 3256 ds->nr_lmbs = nr_lmbs; 3257 ds->dimm = dimm; 3258 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3259 } 3260 return ds; 3261 } 3262 3263 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 3264 sPAPRDIMMState *dimm_state) 3265 { 3266 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3267 g_free(dimm_state); 3268 } 3269 3270 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 3271 PCDIMMDevice *dimm) 3272 { 3273 sPAPRDRConnector *drc; 3274 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3275 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3276 uint64_t size = memory_region_size(mr); 3277 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3278 uint32_t avail_lmbs = 0; 3279 uint64_t addr_start, addr; 3280 int i; 3281 3282 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3283 &error_abort); 3284 3285 addr = addr_start; 3286 for (i = 0; i < nr_lmbs; i++) { 3287 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3288 addr / SPAPR_MEMORY_BLOCK_SIZE); 3289 g_assert(drc); 3290 if (drc->dev) { 3291 avail_lmbs++; 3292 } 3293 addr += SPAPR_MEMORY_BLOCK_SIZE; 3294 } 3295 3296 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3297 } 3298 3299 /* Callback to be called during DRC release. */ 3300 void spapr_lmb_release(DeviceState *dev) 3301 { 3302 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3303 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3304 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3305 3306 /* This information will get lost if a migration occurs 3307 * during the unplug process. In this case recover it. */ 3308 if (ds == NULL) { 3309 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3310 g_assert(ds); 3311 /* The DRC being examined by the caller at least must be counted */ 3312 g_assert(ds->nr_lmbs); 3313 } 3314 3315 if (--ds->nr_lmbs) { 3316 return; 3317 } 3318 3319 /* 3320 * Now that all the LMBs have been removed by the guest, call the 3321 * unplug handler chain. This can never fail. 3322 */ 3323 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3324 } 3325 3326 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3327 { 3328 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3329 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3330 3331 pc_dimm_memory_unplug(dev, MACHINE(hotplug_dev)); 3332 object_unparent(OBJECT(dev)); 3333 spapr_pending_dimm_unplugs_remove(spapr, ds); 3334 } 3335 3336 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3337 DeviceState *dev, Error **errp) 3338 { 3339 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3340 Error *local_err = NULL; 3341 PCDIMMDevice *dimm = PC_DIMM(dev); 3342 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3343 MemoryRegion *mr; 3344 uint32_t nr_lmbs; 3345 uint64_t size, addr_start, addr; 3346 int i; 3347 sPAPRDRConnector *drc; 3348 3349 mr = ddc->get_memory_region(dimm, &local_err); 3350 if (local_err) { 3351 goto out; 3352 } 3353 size = memory_region_size(mr); 3354 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3355 3356 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3357 &local_err); 3358 if (local_err) { 3359 goto out; 3360 } 3361 3362 /* 3363 * An existing pending dimm state for this DIMM means that there is an 3364 * unplug operation in progress, waiting for the spapr_lmb_release 3365 * callback to complete the job (BQL can't cover that far). In this case, 3366 * bail out to avoid detaching DRCs that were already released. 3367 */ 3368 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3369 error_setg(&local_err, 3370 "Memory unplug already in progress for device %s", 3371 dev->id); 3372 goto out; 3373 } 3374 3375 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3376 3377 addr = addr_start; 3378 for (i = 0; i < nr_lmbs; i++) { 3379 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3380 addr / SPAPR_MEMORY_BLOCK_SIZE); 3381 g_assert(drc); 3382 3383 spapr_drc_detach(drc); 3384 addr += SPAPR_MEMORY_BLOCK_SIZE; 3385 } 3386 3387 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3388 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3389 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3390 nr_lmbs, spapr_drc_index(drc)); 3391 out: 3392 error_propagate(errp, local_err); 3393 } 3394 3395 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 3396 sPAPRMachineState *spapr) 3397 { 3398 PowerPCCPU *cpu = POWERPC_CPU(cs); 3399 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3400 int id = spapr_get_vcpu_id(cpu); 3401 void *fdt; 3402 int offset, fdt_size; 3403 char *nodename; 3404 3405 fdt = create_device_tree(&fdt_size); 3406 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3407 offset = fdt_add_subnode(fdt, 0, nodename); 3408 3409 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3410 g_free(nodename); 3411 3412 *fdt_offset = offset; 3413 return fdt; 3414 } 3415 3416 /* Callback to be called during DRC release. */ 3417 void spapr_core_release(DeviceState *dev) 3418 { 3419 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3420 3421 /* Call the unplug handler chain. This can never fail. */ 3422 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3423 } 3424 3425 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3426 { 3427 MachineState *ms = MACHINE(hotplug_dev); 3428 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3429 CPUCore *cc = CPU_CORE(dev); 3430 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3431 3432 if (smc->pre_2_10_has_unused_icps) { 3433 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3434 int i; 3435 3436 for (i = 0; i < cc->nr_threads; i++) { 3437 CPUState *cs = CPU(sc->threads[i]); 3438 3439 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3440 } 3441 } 3442 3443 assert(core_slot); 3444 core_slot->cpu = NULL; 3445 object_unparent(OBJECT(dev)); 3446 } 3447 3448 static 3449 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3450 Error **errp) 3451 { 3452 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3453 int index; 3454 sPAPRDRConnector *drc; 3455 CPUCore *cc = CPU_CORE(dev); 3456 3457 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3458 error_setg(errp, "Unable to find CPU core with core-id: %d", 3459 cc->core_id); 3460 return; 3461 } 3462 if (index == 0) { 3463 error_setg(errp, "Boot CPU core may not be unplugged"); 3464 return; 3465 } 3466 3467 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3468 spapr_vcpu_id(spapr, cc->core_id)); 3469 g_assert(drc); 3470 3471 spapr_drc_detach(drc); 3472 3473 spapr_hotplug_req_remove_by_index(drc); 3474 } 3475 3476 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3477 Error **errp) 3478 { 3479 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3480 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3481 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3482 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3483 CPUCore *cc = CPU_CORE(dev); 3484 CPUState *cs = CPU(core->threads[0]); 3485 sPAPRDRConnector *drc; 3486 Error *local_err = NULL; 3487 CPUArchId *core_slot; 3488 int index; 3489 bool hotplugged = spapr_drc_hotplugged(dev); 3490 3491 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3492 if (!core_slot) { 3493 error_setg(errp, "Unable to find CPU core with core-id: %d", 3494 cc->core_id); 3495 return; 3496 } 3497 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3498 spapr_vcpu_id(spapr, cc->core_id)); 3499 3500 g_assert(drc || !mc->has_hotpluggable_cpus); 3501 3502 if (drc) { 3503 void *fdt; 3504 int fdt_offset; 3505 3506 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 3507 3508 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3509 if (local_err) { 3510 g_free(fdt); 3511 error_propagate(errp, local_err); 3512 return; 3513 } 3514 3515 if (hotplugged) { 3516 /* 3517 * Send hotplug notification interrupt to the guest only 3518 * in case of hotplugged CPUs. 3519 */ 3520 spapr_hotplug_req_add_by_index(drc); 3521 } else { 3522 spapr_drc_reset(drc); 3523 } 3524 } 3525 3526 core_slot->cpu = OBJECT(dev); 3527 3528 if (smc->pre_2_10_has_unused_icps) { 3529 int i; 3530 3531 for (i = 0; i < cc->nr_threads; i++) { 3532 cs = CPU(core->threads[i]); 3533 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3534 } 3535 } 3536 } 3537 3538 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3539 Error **errp) 3540 { 3541 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3542 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3543 Error *local_err = NULL; 3544 CPUCore *cc = CPU_CORE(dev); 3545 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3546 const char *type = object_get_typename(OBJECT(dev)); 3547 CPUArchId *core_slot; 3548 int index; 3549 3550 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3551 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3552 goto out; 3553 } 3554 3555 if (strcmp(base_core_type, type)) { 3556 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3557 goto out; 3558 } 3559 3560 if (cc->core_id % smp_threads) { 3561 error_setg(&local_err, "invalid core id %d", cc->core_id); 3562 goto out; 3563 } 3564 3565 /* 3566 * In general we should have homogeneous threads-per-core, but old 3567 * (pre hotplug support) machine types allow the last core to have 3568 * reduced threads as a compatibility hack for when we allowed 3569 * total vcpus not a multiple of threads-per-core. 3570 */ 3571 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3572 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3573 cc->nr_threads, smp_threads); 3574 goto out; 3575 } 3576 3577 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3578 if (!core_slot) { 3579 error_setg(&local_err, "core id %d out of range", cc->core_id); 3580 goto out; 3581 } 3582 3583 if (core_slot->cpu) { 3584 error_setg(&local_err, "core %d already populated", cc->core_id); 3585 goto out; 3586 } 3587 3588 numa_cpu_pre_plug(core_slot, dev, &local_err); 3589 3590 out: 3591 error_propagate(errp, local_err); 3592 } 3593 3594 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3595 DeviceState *dev, Error **errp) 3596 { 3597 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3598 spapr_memory_plug(hotplug_dev, dev, errp); 3599 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3600 spapr_core_plug(hotplug_dev, dev, errp); 3601 } 3602 } 3603 3604 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 3605 DeviceState *dev, Error **errp) 3606 { 3607 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3608 spapr_memory_unplug(hotplug_dev, dev); 3609 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3610 spapr_core_unplug(hotplug_dev, dev); 3611 } 3612 } 3613 3614 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3615 DeviceState *dev, Error **errp) 3616 { 3617 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3618 MachineClass *mc = MACHINE_GET_CLASS(sms); 3619 3620 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3621 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3622 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3623 } else { 3624 /* NOTE: this means there is a window after guest reset, prior to 3625 * CAS negotiation, where unplug requests will fail due to the 3626 * capability not being detected yet. This is a bit different than 3627 * the case with PCI unplug, where the events will be queued and 3628 * eventually handled by the guest after boot 3629 */ 3630 error_setg(errp, "Memory hot unplug not supported for this guest"); 3631 } 3632 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3633 if (!mc->has_hotpluggable_cpus) { 3634 error_setg(errp, "CPU hot unplug not supported on this machine"); 3635 return; 3636 } 3637 spapr_core_unplug_request(hotplug_dev, dev, errp); 3638 } 3639 } 3640 3641 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3642 DeviceState *dev, Error **errp) 3643 { 3644 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3645 spapr_memory_pre_plug(hotplug_dev, dev, errp); 3646 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3647 spapr_core_pre_plug(hotplug_dev, dev, errp); 3648 } 3649 } 3650 3651 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3652 DeviceState *dev) 3653 { 3654 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3655 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3656 return HOTPLUG_HANDLER(machine); 3657 } 3658 return NULL; 3659 } 3660 3661 static CpuInstanceProperties 3662 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3663 { 3664 CPUArchId *core_slot; 3665 MachineClass *mc = MACHINE_GET_CLASS(machine); 3666 3667 /* make sure possible_cpu are intialized */ 3668 mc->possible_cpu_arch_ids(machine); 3669 /* get CPU core slot containing thread that matches cpu_index */ 3670 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3671 assert(core_slot); 3672 return core_slot->props; 3673 } 3674 3675 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 3676 { 3677 return idx / smp_cores % nb_numa_nodes; 3678 } 3679 3680 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3681 { 3682 int i; 3683 const char *core_type; 3684 int spapr_max_cores = max_cpus / smp_threads; 3685 MachineClass *mc = MACHINE_GET_CLASS(machine); 3686 3687 if (!mc->has_hotpluggable_cpus) { 3688 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3689 } 3690 if (machine->possible_cpus) { 3691 assert(machine->possible_cpus->len == spapr_max_cores); 3692 return machine->possible_cpus; 3693 } 3694 3695 core_type = spapr_get_cpu_core_type(machine->cpu_type); 3696 if (!core_type) { 3697 error_report("Unable to find sPAPR CPU Core definition"); 3698 exit(1); 3699 } 3700 3701 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3702 sizeof(CPUArchId) * spapr_max_cores); 3703 machine->possible_cpus->len = spapr_max_cores; 3704 for (i = 0; i < machine->possible_cpus->len; i++) { 3705 int core_id = i * smp_threads; 3706 3707 machine->possible_cpus->cpus[i].type = core_type; 3708 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3709 machine->possible_cpus->cpus[i].arch_id = core_id; 3710 machine->possible_cpus->cpus[i].props.has_core_id = true; 3711 machine->possible_cpus->cpus[i].props.core_id = core_id; 3712 } 3713 return machine->possible_cpus; 3714 } 3715 3716 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3717 uint64_t *buid, hwaddr *pio, 3718 hwaddr *mmio32, hwaddr *mmio64, 3719 unsigned n_dma, uint32_t *liobns, Error **errp) 3720 { 3721 /* 3722 * New-style PHB window placement. 3723 * 3724 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3725 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3726 * windows. 3727 * 3728 * Some guest kernels can't work with MMIO windows above 1<<46 3729 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3730 * 3731 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3732 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3733 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3734 * 1TiB 64-bit MMIO windows for each PHB. 3735 */ 3736 const uint64_t base_buid = 0x800000020000000ULL; 3737 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3738 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3739 int i; 3740 3741 /* Sanity check natural alignments */ 3742 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3743 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3744 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3745 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3746 /* Sanity check bounds */ 3747 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3748 SPAPR_PCI_MEM32_WIN_SIZE); 3749 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3750 SPAPR_PCI_MEM64_WIN_SIZE); 3751 3752 if (index >= SPAPR_MAX_PHBS) { 3753 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3754 SPAPR_MAX_PHBS - 1); 3755 return; 3756 } 3757 3758 *buid = base_buid + index; 3759 for (i = 0; i < n_dma; ++i) { 3760 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3761 } 3762 3763 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3764 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3765 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3766 } 3767 3768 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3769 { 3770 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3771 3772 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3773 } 3774 3775 static void spapr_ics_resend(XICSFabric *dev) 3776 { 3777 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3778 3779 ics_resend(spapr->ics); 3780 } 3781 3782 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 3783 { 3784 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 3785 3786 return cpu ? ICP(cpu->intc) : NULL; 3787 } 3788 3789 #define ICS_IRQ_FREE(ics, srcno) \ 3790 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) 3791 3792 static int ics_find_free_block(ICSState *ics, int num, int alignnum) 3793 { 3794 int first, i; 3795 3796 for (first = 0; first < ics->nr_irqs; first += alignnum) { 3797 if (num > (ics->nr_irqs - first)) { 3798 return -1; 3799 } 3800 for (i = first; i < first + num; ++i) { 3801 if (!ICS_IRQ_FREE(ics, i)) { 3802 break; 3803 } 3804 } 3805 if (i == (first + num)) { 3806 return first; 3807 } 3808 } 3809 3810 return -1; 3811 } 3812 3813 /* 3814 * Allocate the IRQ number and set the IRQ type, LSI or MSI 3815 */ 3816 static void spapr_irq_set_lsi(sPAPRMachineState *spapr, int irq, bool lsi) 3817 { 3818 ics_set_irq_type(spapr->ics, irq - spapr->ics->offset, lsi); 3819 } 3820 3821 int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi, 3822 Error **errp) 3823 { 3824 ICSState *ics = spapr->ics; 3825 int irq; 3826 3827 assert(ics); 3828 3829 if (irq_hint) { 3830 if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) { 3831 error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint); 3832 return -1; 3833 } 3834 irq = irq_hint; 3835 } else { 3836 irq = ics_find_free_block(ics, 1, 1); 3837 if (irq < 0) { 3838 error_setg(errp, "can't allocate IRQ: no IRQ left"); 3839 return -1; 3840 } 3841 irq += ics->offset; 3842 } 3843 3844 spapr_irq_set_lsi(spapr, irq, lsi); 3845 trace_spapr_irq_alloc(irq); 3846 3847 return irq; 3848 } 3849 3850 /* 3851 * Allocate block of consecutive IRQs, and return the number of the first IRQ in 3852 * the block. If align==true, aligns the first IRQ number to num. 3853 */ 3854 int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi, 3855 bool align, Error **errp) 3856 { 3857 ICSState *ics = spapr->ics; 3858 int i, first = -1; 3859 3860 assert(ics); 3861 3862 /* 3863 * MSIMesage::data is used for storing VIRQ so 3864 * it has to be aligned to num to support multiple 3865 * MSI vectors. MSI-X is not affected by this. 3866 * The hint is used for the first IRQ, the rest should 3867 * be allocated continuously. 3868 */ 3869 if (align) { 3870 assert((num == 1) || (num == 2) || (num == 4) || 3871 (num == 8) || (num == 16) || (num == 32)); 3872 first = ics_find_free_block(ics, num, num); 3873 } else { 3874 first = ics_find_free_block(ics, num, 1); 3875 } 3876 if (first < 0) { 3877 error_setg(errp, "can't find a free %d-IRQ block", num); 3878 return -1; 3879 } 3880 3881 first += ics->offset; 3882 for (i = first; i < first + num; ++i) { 3883 spapr_irq_set_lsi(spapr, i, lsi); 3884 } 3885 3886 trace_spapr_irq_alloc_block(first, num, lsi, align); 3887 3888 return first; 3889 } 3890 3891 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num) 3892 { 3893 ICSState *ics = spapr->ics; 3894 int srcno = irq - ics->offset; 3895 int i; 3896 3897 if (ics_valid_irq(ics, irq)) { 3898 trace_spapr_irq_free(0, irq, num); 3899 for (i = srcno; i < srcno + num; ++i) { 3900 if (ICS_IRQ_FREE(ics, i)) { 3901 trace_spapr_irq_free_warn(0, i + ics->offset); 3902 } 3903 memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); 3904 } 3905 } 3906 } 3907 3908 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq) 3909 { 3910 ICSState *ics = spapr->ics; 3911 3912 if (ics_valid_irq(ics, irq)) { 3913 return ics->qirqs[irq - ics->offset]; 3914 } 3915 3916 return NULL; 3917 } 3918 3919 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3920 Monitor *mon) 3921 { 3922 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3923 CPUState *cs; 3924 3925 CPU_FOREACH(cs) { 3926 PowerPCCPU *cpu = POWERPC_CPU(cs); 3927 3928 icp_pic_print_info(ICP(cpu->intc), mon); 3929 } 3930 3931 ics_pic_print_info(spapr->ics, mon); 3932 } 3933 3934 int spapr_get_vcpu_id(PowerPCCPU *cpu) 3935 { 3936 return cpu->vcpu_id; 3937 } 3938 3939 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 3940 { 3941 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3942 int vcpu_id; 3943 3944 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 3945 3946 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 3947 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 3948 error_append_hint(errp, "Adjust the number of cpus to %d " 3949 "or try to raise the number of threads per core\n", 3950 vcpu_id * smp_threads / spapr->vsmt); 3951 return; 3952 } 3953 3954 cpu->vcpu_id = vcpu_id; 3955 } 3956 3957 PowerPCCPU *spapr_find_cpu(int vcpu_id) 3958 { 3959 CPUState *cs; 3960 3961 CPU_FOREACH(cs) { 3962 PowerPCCPU *cpu = POWERPC_CPU(cs); 3963 3964 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 3965 return cpu; 3966 } 3967 } 3968 3969 return NULL; 3970 } 3971 3972 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3973 { 3974 MachineClass *mc = MACHINE_CLASS(oc); 3975 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3976 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3977 NMIClass *nc = NMI_CLASS(oc); 3978 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3979 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3980 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3981 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3982 3983 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3984 3985 /* 3986 * We set up the default / latest behaviour here. The class_init 3987 * functions for the specific versioned machine types can override 3988 * these details for backwards compatibility 3989 */ 3990 mc->init = spapr_machine_init; 3991 mc->reset = spapr_machine_reset; 3992 mc->block_default_type = IF_SCSI; 3993 mc->max_cpus = 1024; 3994 mc->no_parallel = 1; 3995 mc->default_boot_order = ""; 3996 mc->default_ram_size = 512 * M_BYTE; 3997 mc->kvm_type = spapr_kvm_type; 3998 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 3999 mc->pci_allow_0_address = true; 4000 assert(!mc->get_hotplug_handler); 4001 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4002 hc->pre_plug = spapr_machine_device_pre_plug; 4003 hc->plug = spapr_machine_device_plug; 4004 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4005 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4006 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4007 hc->unplug_request = spapr_machine_device_unplug_request; 4008 hc->unplug = spapr_machine_device_unplug; 4009 4010 smc->dr_lmb_enabled = true; 4011 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4012 mc->has_hotpluggable_cpus = true; 4013 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4014 fwc->get_dev_path = spapr_get_fw_dev_path; 4015 nc->nmi_monitor_handler = spapr_nmi; 4016 smc->phb_placement = spapr_phb_placement; 4017 vhc->hypercall = emulate_spapr_hypercall; 4018 vhc->hpt_mask = spapr_hpt_mask; 4019 vhc->map_hptes = spapr_map_hptes; 4020 vhc->unmap_hptes = spapr_unmap_hptes; 4021 vhc->store_hpte = spapr_store_hpte; 4022 vhc->get_patbe = spapr_get_patbe; 4023 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4024 xic->ics_get = spapr_ics_get; 4025 xic->ics_resend = spapr_ics_resend; 4026 xic->icp_get = spapr_icp_get; 4027 ispc->print_info = spapr_pic_print_info; 4028 /* Force NUMA node memory size to be a multiple of 4029 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4030 * in which LMBs are represented and hot-added 4031 */ 4032 mc->numa_mem_align_shift = 28; 4033 4034 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4035 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4036 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4037 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4038 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4039 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4040 spapr_caps_add_properties(smc, &error_abort); 4041 } 4042 4043 static const TypeInfo spapr_machine_info = { 4044 .name = TYPE_SPAPR_MACHINE, 4045 .parent = TYPE_MACHINE, 4046 .abstract = true, 4047 .instance_size = sizeof(sPAPRMachineState), 4048 .instance_init = spapr_instance_init, 4049 .instance_finalize = spapr_machine_finalizefn, 4050 .class_size = sizeof(sPAPRMachineClass), 4051 .class_init = spapr_machine_class_init, 4052 .interfaces = (InterfaceInfo[]) { 4053 { TYPE_FW_PATH_PROVIDER }, 4054 { TYPE_NMI }, 4055 { TYPE_HOTPLUG_HANDLER }, 4056 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4057 { TYPE_XICS_FABRIC }, 4058 { TYPE_INTERRUPT_STATS_PROVIDER }, 4059 { } 4060 }, 4061 }; 4062 4063 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4064 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4065 void *data) \ 4066 { \ 4067 MachineClass *mc = MACHINE_CLASS(oc); \ 4068 spapr_machine_##suffix##_class_options(mc); \ 4069 if (latest) { \ 4070 mc->alias = "pseries"; \ 4071 mc->is_default = 1; \ 4072 } \ 4073 } \ 4074 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 4075 { \ 4076 MachineState *machine = MACHINE(obj); \ 4077 spapr_machine_##suffix##_instance_options(machine); \ 4078 } \ 4079 static const TypeInfo spapr_machine_##suffix##_info = { \ 4080 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4081 .parent = TYPE_SPAPR_MACHINE, \ 4082 .class_init = spapr_machine_##suffix##_class_init, \ 4083 .instance_init = spapr_machine_##suffix##_instance_init, \ 4084 }; \ 4085 static void spapr_machine_register_##suffix(void) \ 4086 { \ 4087 type_register(&spapr_machine_##suffix##_info); \ 4088 } \ 4089 type_init(spapr_machine_register_##suffix) 4090 4091 /* 4092 * pseries-3.0 4093 */ 4094 static void spapr_machine_3_0_instance_options(MachineState *machine) 4095 { 4096 } 4097 4098 static void spapr_machine_3_0_class_options(MachineClass *mc) 4099 { 4100 /* Defaults for the latest behaviour inherited from the base class */ 4101 } 4102 4103 DEFINE_SPAPR_MACHINE(3_0, "3.0", true); 4104 4105 /* 4106 * pseries-2.12 4107 */ 4108 #define SPAPR_COMPAT_2_12 \ 4109 HW_COMPAT_2_12 \ 4110 { \ 4111 .driver = TYPE_POWERPC_CPU, \ 4112 .property = "pre-3.0-migration", \ 4113 .value = "on", \ 4114 }, 4115 4116 static void spapr_machine_2_12_instance_options(MachineState *machine) 4117 { 4118 spapr_machine_3_0_instance_options(machine); 4119 } 4120 4121 static void spapr_machine_2_12_class_options(MachineClass *mc) 4122 { 4123 spapr_machine_3_0_class_options(mc); 4124 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_12); 4125 } 4126 4127 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4128 4129 static void spapr_machine_2_12_sxxm_instance_options(MachineState *machine) 4130 { 4131 spapr_machine_2_12_instance_options(machine); 4132 } 4133 4134 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4135 { 4136 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4137 4138 spapr_machine_2_12_class_options(mc); 4139 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4140 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4141 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4142 } 4143 4144 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4145 4146 /* 4147 * pseries-2.11 4148 */ 4149 #define SPAPR_COMPAT_2_11 \ 4150 HW_COMPAT_2_11 4151 4152 static void spapr_machine_2_11_instance_options(MachineState *machine) 4153 { 4154 spapr_machine_2_12_instance_options(machine); 4155 } 4156 4157 static void spapr_machine_2_11_class_options(MachineClass *mc) 4158 { 4159 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4160 4161 spapr_machine_2_12_class_options(mc); 4162 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4163 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11); 4164 } 4165 4166 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4167 4168 /* 4169 * pseries-2.10 4170 */ 4171 #define SPAPR_COMPAT_2_10 \ 4172 HW_COMPAT_2_10 4173 4174 static void spapr_machine_2_10_instance_options(MachineState *machine) 4175 { 4176 spapr_machine_2_11_instance_options(machine); 4177 } 4178 4179 static void spapr_machine_2_10_class_options(MachineClass *mc) 4180 { 4181 spapr_machine_2_11_class_options(mc); 4182 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10); 4183 } 4184 4185 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4186 4187 /* 4188 * pseries-2.9 4189 */ 4190 #define SPAPR_COMPAT_2_9 \ 4191 HW_COMPAT_2_9 \ 4192 { \ 4193 .driver = TYPE_POWERPC_CPU, \ 4194 .property = "pre-2.10-migration", \ 4195 .value = "on", \ 4196 }, \ 4197 4198 static void spapr_machine_2_9_instance_options(MachineState *machine) 4199 { 4200 spapr_machine_2_10_instance_options(machine); 4201 } 4202 4203 static void spapr_machine_2_9_class_options(MachineClass *mc) 4204 { 4205 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4206 4207 spapr_machine_2_10_class_options(mc); 4208 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); 4209 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4210 smc->pre_2_10_has_unused_icps = true; 4211 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4212 } 4213 4214 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4215 4216 /* 4217 * pseries-2.8 4218 */ 4219 #define SPAPR_COMPAT_2_8 \ 4220 HW_COMPAT_2_8 \ 4221 { \ 4222 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4223 .property = "pcie-extended-configuration-space", \ 4224 .value = "off", \ 4225 }, 4226 4227 static void spapr_machine_2_8_instance_options(MachineState *machine) 4228 { 4229 spapr_machine_2_9_instance_options(machine); 4230 } 4231 4232 static void spapr_machine_2_8_class_options(MachineClass *mc) 4233 { 4234 spapr_machine_2_9_class_options(mc); 4235 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 4236 mc->numa_mem_align_shift = 23; 4237 } 4238 4239 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4240 4241 /* 4242 * pseries-2.7 4243 */ 4244 #define SPAPR_COMPAT_2_7 \ 4245 HW_COMPAT_2_7 \ 4246 { \ 4247 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4248 .property = "mem_win_size", \ 4249 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 4250 }, \ 4251 { \ 4252 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4253 .property = "mem64_win_size", \ 4254 .value = "0", \ 4255 }, \ 4256 { \ 4257 .driver = TYPE_POWERPC_CPU, \ 4258 .property = "pre-2.8-migration", \ 4259 .value = "on", \ 4260 }, \ 4261 { \ 4262 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4263 .property = "pre-2.8-migration", \ 4264 .value = "on", \ 4265 }, 4266 4267 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 4268 uint64_t *buid, hwaddr *pio, 4269 hwaddr *mmio32, hwaddr *mmio64, 4270 unsigned n_dma, uint32_t *liobns, Error **errp) 4271 { 4272 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4273 const uint64_t base_buid = 0x800000020000000ULL; 4274 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4275 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4276 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4277 const uint32_t max_index = 255; 4278 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4279 4280 uint64_t ram_top = MACHINE(spapr)->ram_size; 4281 hwaddr phb0_base, phb_base; 4282 int i; 4283 4284 /* Do we have device memory? */ 4285 if (MACHINE(spapr)->maxram_size > ram_top) { 4286 /* Can't just use maxram_size, because there may be an 4287 * alignment gap between normal and device memory regions 4288 */ 4289 ram_top = MACHINE(spapr)->device_memory->base + 4290 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4291 } 4292 4293 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4294 4295 if (index > max_index) { 4296 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4297 max_index); 4298 return; 4299 } 4300 4301 *buid = base_buid + index; 4302 for (i = 0; i < n_dma; ++i) { 4303 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4304 } 4305 4306 phb_base = phb0_base + index * phb_spacing; 4307 *pio = phb_base + pio_offset; 4308 *mmio32 = phb_base + mmio_offset; 4309 /* 4310 * We don't set the 64-bit MMIO window, relying on the PHB's 4311 * fallback behaviour of automatically splitting a large "32-bit" 4312 * window into contiguous 32-bit and 64-bit windows 4313 */ 4314 } 4315 4316 static void spapr_machine_2_7_instance_options(MachineState *machine) 4317 { 4318 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 4319 4320 spapr_machine_2_8_instance_options(machine); 4321 spapr->use_hotplug_event_source = false; 4322 } 4323 4324 static void spapr_machine_2_7_class_options(MachineClass *mc) 4325 { 4326 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4327 4328 spapr_machine_2_8_class_options(mc); 4329 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4330 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 4331 smc->phb_placement = phb_placement_2_7; 4332 } 4333 4334 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4335 4336 /* 4337 * pseries-2.6 4338 */ 4339 #define SPAPR_COMPAT_2_6 \ 4340 HW_COMPAT_2_6 \ 4341 { \ 4342 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 4343 .property = "ddw",\ 4344 .value = stringify(off),\ 4345 }, 4346 4347 static void spapr_machine_2_6_instance_options(MachineState *machine) 4348 { 4349 spapr_machine_2_7_instance_options(machine); 4350 } 4351 4352 static void spapr_machine_2_6_class_options(MachineClass *mc) 4353 { 4354 spapr_machine_2_7_class_options(mc); 4355 mc->has_hotpluggable_cpus = false; 4356 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 4357 } 4358 4359 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4360 4361 /* 4362 * pseries-2.5 4363 */ 4364 #define SPAPR_COMPAT_2_5 \ 4365 HW_COMPAT_2_5 \ 4366 { \ 4367 .driver = "spapr-vlan", \ 4368 .property = "use-rx-buffer-pools", \ 4369 .value = "off", \ 4370 }, 4371 4372 static void spapr_machine_2_5_instance_options(MachineState *machine) 4373 { 4374 spapr_machine_2_6_instance_options(machine); 4375 } 4376 4377 static void spapr_machine_2_5_class_options(MachineClass *mc) 4378 { 4379 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4380 4381 spapr_machine_2_6_class_options(mc); 4382 smc->use_ohci_by_default = true; 4383 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 4384 } 4385 4386 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4387 4388 /* 4389 * pseries-2.4 4390 */ 4391 #define SPAPR_COMPAT_2_4 \ 4392 HW_COMPAT_2_4 4393 4394 static void spapr_machine_2_4_instance_options(MachineState *machine) 4395 { 4396 spapr_machine_2_5_instance_options(machine); 4397 } 4398 4399 static void spapr_machine_2_4_class_options(MachineClass *mc) 4400 { 4401 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4402 4403 spapr_machine_2_5_class_options(mc); 4404 smc->dr_lmb_enabled = false; 4405 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 4406 } 4407 4408 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4409 4410 /* 4411 * pseries-2.3 4412 */ 4413 #define SPAPR_COMPAT_2_3 \ 4414 HW_COMPAT_2_3 \ 4415 {\ 4416 .driver = "spapr-pci-host-bridge",\ 4417 .property = "dynamic-reconfiguration",\ 4418 .value = "off",\ 4419 }, 4420 4421 static void spapr_machine_2_3_instance_options(MachineState *machine) 4422 { 4423 spapr_machine_2_4_instance_options(machine); 4424 } 4425 4426 static void spapr_machine_2_3_class_options(MachineClass *mc) 4427 { 4428 spapr_machine_2_4_class_options(mc); 4429 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 4430 } 4431 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4432 4433 /* 4434 * pseries-2.2 4435 */ 4436 4437 #define SPAPR_COMPAT_2_2 \ 4438 HW_COMPAT_2_2 \ 4439 {\ 4440 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 4441 .property = "mem_win_size",\ 4442 .value = "0x20000000",\ 4443 }, 4444 4445 static void spapr_machine_2_2_instance_options(MachineState *machine) 4446 { 4447 spapr_machine_2_3_instance_options(machine); 4448 machine->suppress_vmdesc = true; 4449 } 4450 4451 static void spapr_machine_2_2_class_options(MachineClass *mc) 4452 { 4453 spapr_machine_2_3_class_options(mc); 4454 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 4455 } 4456 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4457 4458 /* 4459 * pseries-2.1 4460 */ 4461 #define SPAPR_COMPAT_2_1 \ 4462 HW_COMPAT_2_1 4463 4464 static void spapr_machine_2_1_instance_options(MachineState *machine) 4465 { 4466 spapr_machine_2_2_instance_options(machine); 4467 } 4468 4469 static void spapr_machine_2_1_class_options(MachineClass *mc) 4470 { 4471 spapr_machine_2_2_class_options(mc); 4472 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 4473 } 4474 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4475 4476 static void spapr_machine_register_types(void) 4477 { 4478 type_register_static(&spapr_machine_info); 4479 } 4480 4481 type_init(spapr_machine_register_types) 4482