1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/datadir.h" 30 #include "qapi/error.h" 31 #include "qapi/qapi-events-machine.h" 32 #include "qapi/visitor.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/hostmem.h" 35 #include "sysemu/numa.h" 36 #include "sysemu/qtest.h" 37 #include "sysemu/reset.h" 38 #include "sysemu/runstate.h" 39 #include "qemu/log.h" 40 #include "hw/fw-path-provider.h" 41 #include "elf.h" 42 #include "net/net.h" 43 #include "sysemu/device_tree.h" 44 #include "sysemu/cpus.h" 45 #include "sysemu/hw_accel.h" 46 #include "kvm_ppc.h" 47 #include "migration/misc.h" 48 #include "migration/qemu-file-types.h" 49 #include "migration/global_state.h" 50 #include "migration/register.h" 51 #include "migration/blocker.h" 52 #include "mmu-hash64.h" 53 #include "mmu-book3s-v3.h" 54 #include "cpu-models.h" 55 #include "hw/core/cpu.h" 56 57 #include "hw/ppc/ppc.h" 58 #include "hw/loader.h" 59 60 #include "hw/ppc/fdt.h" 61 #include "hw/ppc/spapr.h" 62 #include "hw/ppc/spapr_vio.h" 63 #include "hw/qdev-properties.h" 64 #include "hw/pci-host/spapr.h" 65 #include "hw/pci/msi.h" 66 67 #include "hw/pci/pci.h" 68 #include "hw/scsi/scsi.h" 69 #include "hw/virtio/virtio-scsi.h" 70 #include "hw/virtio/vhost-scsi-common.h" 71 72 #include "exec/ram_addr.h" 73 #include "hw/usb.h" 74 #include "qemu/config-file.h" 75 #include "qemu/error-report.h" 76 #include "trace.h" 77 #include "hw/nmi.h" 78 #include "hw/intc/intc.h" 79 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 #include "hw/ppc/spapr_nvdimm.h" 84 #include "hw/ppc/spapr_numa.h" 85 #include "hw/ppc/pef.h" 86 87 #include "monitor/monitor.h" 88 89 #include <libfdt.h> 90 91 /* SLOF memory layout: 92 * 93 * SLOF raw image loaded at 0, copies its romfs right below the flat 94 * device-tree, then position SLOF itself 31M below that 95 * 96 * So we set FW_OVERHEAD to 40MB which should account for all of that 97 * and more 98 * 99 * We load our kernel at 4M, leaving space for SLOF initial image 100 */ 101 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */ 102 #define FW_MAX_SIZE 0x400000 103 #define FW_FILE_NAME "slof.bin" 104 #define FW_OVERHEAD 0x2800000 105 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 106 107 #define MIN_RMA_SLOF (128 * MiB) 108 109 #define PHANDLE_INTC 0x00001111 110 111 /* These two functions implement the VCPU id numbering: one to compute them 112 * all and one to identify thread 0 of a VCORE. Any change to the first one 113 * is likely to have an impact on the second one, so let's keep them close. 114 */ 115 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 116 { 117 MachineState *ms = MACHINE(spapr); 118 unsigned int smp_threads = ms->smp.threads; 119 120 assert(spapr->vsmt); 121 return 122 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 123 } 124 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 125 PowerPCCPU *cpu) 126 { 127 assert(spapr->vsmt); 128 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 129 } 130 131 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 132 { 133 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 134 * and newer QEMUs don't even have them. In both cases, we don't want 135 * to send anything on the wire. 136 */ 137 return false; 138 } 139 140 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 141 .name = "icp/server", 142 .version_id = 1, 143 .minimum_version_id = 1, 144 .needed = pre_2_10_vmstate_dummy_icp_needed, 145 .fields = (VMStateField[]) { 146 VMSTATE_UNUSED(4), /* uint32_t xirr */ 147 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 148 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 149 VMSTATE_END_OF_LIST() 150 }, 151 }; 152 153 static void pre_2_10_vmstate_register_dummy_icp(int i) 154 { 155 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 156 (void *)(uintptr_t) i); 157 } 158 159 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 160 { 161 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 162 (void *)(uintptr_t) i); 163 } 164 165 int spapr_max_server_number(SpaprMachineState *spapr) 166 { 167 MachineState *ms = MACHINE(spapr); 168 169 assert(spapr->vsmt); 170 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 171 } 172 173 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 174 int smt_threads) 175 { 176 int i, ret = 0; 177 uint32_t servers_prop[smt_threads]; 178 uint32_t gservers_prop[smt_threads * 2]; 179 int index = spapr_get_vcpu_id(cpu); 180 181 if (cpu->compat_pvr) { 182 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 183 if (ret < 0) { 184 return ret; 185 } 186 } 187 188 /* Build interrupt servers and gservers properties */ 189 for (i = 0; i < smt_threads; i++) { 190 servers_prop[i] = cpu_to_be32(index + i); 191 /* Hack, direct the group queues back to cpu 0 */ 192 gservers_prop[i*2] = cpu_to_be32(index + i); 193 gservers_prop[i*2 + 1] = 0; 194 } 195 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 196 servers_prop, sizeof(servers_prop)); 197 if (ret < 0) { 198 return ret; 199 } 200 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 201 gservers_prop, sizeof(gservers_prop)); 202 203 return ret; 204 } 205 206 static void spapr_dt_pa_features(SpaprMachineState *spapr, 207 PowerPCCPU *cpu, 208 void *fdt, int offset) 209 { 210 uint8_t pa_features_206[] = { 6, 0, 211 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 212 uint8_t pa_features_207[] = { 24, 0, 213 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 214 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 215 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 216 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 217 uint8_t pa_features_300[] = { 66, 0, 218 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 219 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 220 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 221 /* 6: DS207 */ 222 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 223 /* 16: Vector */ 224 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 225 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 226 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 227 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 228 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 229 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 230 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 231 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 232 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 233 /* 42: PM, 44: PC RA, 46: SC vec'd */ 234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 235 /* 48: SIMD, 50: QP BFP, 52: String */ 236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 237 /* 54: DecFP, 56: DecI, 58: SHA */ 238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 239 /* 60: NM atomic, 62: RNG */ 240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 241 }; 242 uint8_t *pa_features = NULL; 243 size_t pa_size; 244 245 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 246 pa_features = pa_features_206; 247 pa_size = sizeof(pa_features_206); 248 } 249 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 250 pa_features = pa_features_207; 251 pa_size = sizeof(pa_features_207); 252 } 253 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 254 pa_features = pa_features_300; 255 pa_size = sizeof(pa_features_300); 256 } 257 if (!pa_features) { 258 return; 259 } 260 261 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 262 /* 263 * Note: we keep CI large pages off by default because a 64K capable 264 * guest provisioned with large pages might otherwise try to map a qemu 265 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 266 * even if that qemu runs on a 4k host. 267 * We dd this bit back here if we are confident this is not an issue 268 */ 269 pa_features[3] |= 0x20; 270 } 271 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 272 pa_features[24] |= 0x80; /* Transactional memory support */ 273 } 274 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 275 /* Workaround for broken kernels that attempt (guest) radix 276 * mode when they can't handle it, if they see the radix bit set 277 * in pa-features. So hide it from them. */ 278 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 279 } 280 281 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 282 } 283 284 static hwaddr spapr_node0_size(MachineState *machine) 285 { 286 if (machine->numa_state->num_nodes) { 287 int i; 288 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 289 if (machine->numa_state->nodes[i].node_mem) { 290 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 291 machine->ram_size); 292 } 293 } 294 } 295 return machine->ram_size; 296 } 297 298 static void add_str(GString *s, const gchar *s1) 299 { 300 g_string_append_len(s, s1, strlen(s1) + 1); 301 } 302 303 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 304 hwaddr start, hwaddr size) 305 { 306 char mem_name[32]; 307 uint64_t mem_reg_property[2]; 308 int off; 309 310 mem_reg_property[0] = cpu_to_be64(start); 311 mem_reg_property[1] = cpu_to_be64(size); 312 313 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 314 off = fdt_add_subnode(fdt, 0, mem_name); 315 _FDT(off); 316 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 317 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 318 sizeof(mem_reg_property)))); 319 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 320 return off; 321 } 322 323 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 324 { 325 MemoryDeviceInfoList *info; 326 327 for (info = list; info; info = info->next) { 328 MemoryDeviceInfo *value = info->value; 329 330 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 331 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 332 333 if (addr >= pcdimm_info->addr && 334 addr < (pcdimm_info->addr + pcdimm_info->size)) { 335 return pcdimm_info->node; 336 } 337 } 338 } 339 340 return -1; 341 } 342 343 struct sPAPRDrconfCellV2 { 344 uint32_t seq_lmbs; 345 uint64_t base_addr; 346 uint32_t drc_index; 347 uint32_t aa_index; 348 uint32_t flags; 349 } QEMU_PACKED; 350 351 typedef struct DrconfCellQueue { 352 struct sPAPRDrconfCellV2 cell; 353 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 354 } DrconfCellQueue; 355 356 static DrconfCellQueue * 357 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 358 uint32_t drc_index, uint32_t aa_index, 359 uint32_t flags) 360 { 361 DrconfCellQueue *elem; 362 363 elem = g_malloc0(sizeof(*elem)); 364 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 365 elem->cell.base_addr = cpu_to_be64(base_addr); 366 elem->cell.drc_index = cpu_to_be32(drc_index); 367 elem->cell.aa_index = cpu_to_be32(aa_index); 368 elem->cell.flags = cpu_to_be32(flags); 369 370 return elem; 371 } 372 373 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 374 int offset, MemoryDeviceInfoList *dimms) 375 { 376 MachineState *machine = MACHINE(spapr); 377 uint8_t *int_buf, *cur_index; 378 int ret; 379 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 380 uint64_t addr, cur_addr, size; 381 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 382 uint64_t mem_end = machine->device_memory->base + 383 memory_region_size(&machine->device_memory->mr); 384 uint32_t node, buf_len, nr_entries = 0; 385 SpaprDrc *drc; 386 DrconfCellQueue *elem, *next; 387 MemoryDeviceInfoList *info; 388 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 389 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 390 391 /* Entry to cover RAM and the gap area */ 392 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 393 SPAPR_LMB_FLAGS_RESERVED | 394 SPAPR_LMB_FLAGS_DRC_INVALID); 395 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 396 nr_entries++; 397 398 cur_addr = machine->device_memory->base; 399 for (info = dimms; info; info = info->next) { 400 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 401 402 addr = di->addr; 403 size = di->size; 404 node = di->node; 405 406 /* 407 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 408 * area is marked hotpluggable in the next iteration for the bigger 409 * chunk including the NVDIMM occupied area. 410 */ 411 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 412 continue; 413 414 /* Entry for hot-pluggable area */ 415 if (cur_addr < addr) { 416 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 417 g_assert(drc); 418 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 419 cur_addr, spapr_drc_index(drc), -1, 0); 420 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 421 nr_entries++; 422 } 423 424 /* Entry for DIMM */ 425 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 426 g_assert(drc); 427 elem = spapr_get_drconf_cell(size / lmb_size, addr, 428 spapr_drc_index(drc), node, 429 (SPAPR_LMB_FLAGS_ASSIGNED | 430 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 431 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 432 nr_entries++; 433 cur_addr = addr + size; 434 } 435 436 /* Entry for remaining hotpluggable area */ 437 if (cur_addr < mem_end) { 438 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 439 g_assert(drc); 440 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 441 cur_addr, spapr_drc_index(drc), -1, 0); 442 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 443 nr_entries++; 444 } 445 446 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 447 int_buf = cur_index = g_malloc0(buf_len); 448 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 449 cur_index += sizeof(nr_entries); 450 451 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 452 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 453 cur_index += sizeof(elem->cell); 454 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 455 g_free(elem); 456 } 457 458 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 459 g_free(int_buf); 460 if (ret < 0) { 461 return -1; 462 } 463 return 0; 464 } 465 466 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 467 int offset, MemoryDeviceInfoList *dimms) 468 { 469 MachineState *machine = MACHINE(spapr); 470 int i, ret; 471 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 472 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 473 uint32_t nr_lmbs = (machine->device_memory->base + 474 memory_region_size(&machine->device_memory->mr)) / 475 lmb_size; 476 uint32_t *int_buf, *cur_index, buf_len; 477 478 /* 479 * Allocate enough buffer size to fit in ibm,dynamic-memory 480 */ 481 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 482 cur_index = int_buf = g_malloc0(buf_len); 483 int_buf[0] = cpu_to_be32(nr_lmbs); 484 cur_index++; 485 for (i = 0; i < nr_lmbs; i++) { 486 uint64_t addr = i * lmb_size; 487 uint32_t *dynamic_memory = cur_index; 488 489 if (i >= device_lmb_start) { 490 SpaprDrc *drc; 491 492 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 493 g_assert(drc); 494 495 dynamic_memory[0] = cpu_to_be32(addr >> 32); 496 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 497 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 498 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 499 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 500 if (memory_region_present(get_system_memory(), addr)) { 501 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 502 } else { 503 dynamic_memory[5] = cpu_to_be32(0); 504 } 505 } else { 506 /* 507 * LMB information for RMA, boot time RAM and gap b/n RAM and 508 * device memory region -- all these are marked as reserved 509 * and as having no valid DRC. 510 */ 511 dynamic_memory[0] = cpu_to_be32(addr >> 32); 512 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 513 dynamic_memory[2] = cpu_to_be32(0); 514 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 515 dynamic_memory[4] = cpu_to_be32(-1); 516 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 517 SPAPR_LMB_FLAGS_DRC_INVALID); 518 } 519 520 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 521 } 522 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 523 g_free(int_buf); 524 if (ret < 0) { 525 return -1; 526 } 527 return 0; 528 } 529 530 /* 531 * Adds ibm,dynamic-reconfiguration-memory node. 532 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 533 * of this device tree node. 534 */ 535 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 536 void *fdt) 537 { 538 MachineState *machine = MACHINE(spapr); 539 int ret, offset; 540 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 541 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 542 cpu_to_be32(lmb_size & 0xffffffff)}; 543 MemoryDeviceInfoList *dimms = NULL; 544 545 /* 546 * Don't create the node if there is no device memory 547 */ 548 if (machine->ram_size == machine->maxram_size) { 549 return 0; 550 } 551 552 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 553 554 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 555 sizeof(prop_lmb_size)); 556 if (ret < 0) { 557 return ret; 558 } 559 560 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 561 if (ret < 0) { 562 return ret; 563 } 564 565 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 566 if (ret < 0) { 567 return ret; 568 } 569 570 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 571 dimms = qmp_memory_device_list(); 572 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 573 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 574 } else { 575 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 576 } 577 qapi_free_MemoryDeviceInfoList(dimms); 578 579 if (ret < 0) { 580 return ret; 581 } 582 583 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 584 585 return ret; 586 } 587 588 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 589 { 590 MachineState *machine = MACHINE(spapr); 591 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 592 hwaddr mem_start, node_size; 593 int i, nb_nodes = machine->numa_state->num_nodes; 594 NodeInfo *nodes = machine->numa_state->nodes; 595 596 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 597 if (!nodes[i].node_mem) { 598 continue; 599 } 600 if (mem_start >= machine->ram_size) { 601 node_size = 0; 602 } else { 603 node_size = nodes[i].node_mem; 604 if (node_size > machine->ram_size - mem_start) { 605 node_size = machine->ram_size - mem_start; 606 } 607 } 608 if (!mem_start) { 609 /* spapr_machine_init() checks for rma_size <= node0_size 610 * already */ 611 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 612 mem_start += spapr->rma_size; 613 node_size -= spapr->rma_size; 614 } 615 for ( ; node_size; ) { 616 hwaddr sizetmp = pow2floor(node_size); 617 618 /* mem_start != 0 here */ 619 if (ctzl(mem_start) < ctzl(sizetmp)) { 620 sizetmp = 1ULL << ctzl(mem_start); 621 } 622 623 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 624 node_size -= sizetmp; 625 mem_start += sizetmp; 626 } 627 } 628 629 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 630 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 631 int ret; 632 633 g_assert(smc->dr_lmb_enabled); 634 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 635 if (ret) { 636 return ret; 637 } 638 } 639 640 return 0; 641 } 642 643 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 644 SpaprMachineState *spapr) 645 { 646 MachineState *ms = MACHINE(spapr); 647 PowerPCCPU *cpu = POWERPC_CPU(cs); 648 CPUPPCState *env = &cpu->env; 649 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 650 int index = spapr_get_vcpu_id(cpu); 651 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 652 0xffffffff, 0xffffffff}; 653 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 654 : SPAPR_TIMEBASE_FREQ; 655 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 656 uint32_t page_sizes_prop[64]; 657 size_t page_sizes_prop_size; 658 unsigned int smp_threads = ms->smp.threads; 659 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 660 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 661 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 662 SpaprDrc *drc; 663 int drc_index; 664 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 665 int i; 666 667 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 668 if (drc) { 669 drc_index = spapr_drc_index(drc); 670 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 671 } 672 673 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 674 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 675 676 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 677 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 678 env->dcache_line_size))); 679 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 680 env->dcache_line_size))); 681 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 682 env->icache_line_size))); 683 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 684 env->icache_line_size))); 685 686 if (pcc->l1_dcache_size) { 687 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 688 pcc->l1_dcache_size))); 689 } else { 690 warn_report("Unknown L1 dcache size for cpu"); 691 } 692 if (pcc->l1_icache_size) { 693 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 694 pcc->l1_icache_size))); 695 } else { 696 warn_report("Unknown L1 icache size for cpu"); 697 } 698 699 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 700 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 701 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 702 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 703 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 704 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 705 706 if (ppc_has_spr(cpu, SPR_PURR)) { 707 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 708 } 709 if (ppc_has_spr(cpu, SPR_PURR)) { 710 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 711 } 712 713 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 714 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 715 segs, sizeof(segs)))); 716 } 717 718 /* Advertise VSX (vector extensions) if available 719 * 1 == VMX / Altivec available 720 * 2 == VSX available 721 * 722 * Only CPUs for which we create core types in spapr_cpu_core.c 723 * are possible, and all of those have VMX */ 724 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 725 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 726 } else { 727 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 728 } 729 730 /* Advertise DFP (Decimal Floating Point) if available 731 * 0 / no property == no DFP 732 * 1 == DFP available */ 733 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 734 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 735 } 736 737 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 738 sizeof(page_sizes_prop)); 739 if (page_sizes_prop_size) { 740 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 741 page_sizes_prop, page_sizes_prop_size))); 742 } 743 744 spapr_dt_pa_features(spapr, cpu, fdt, offset); 745 746 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 747 cs->cpu_index / vcpus_per_socket))); 748 749 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 750 pft_size_prop, sizeof(pft_size_prop)))); 751 752 if (ms->numa_state->num_nodes > 1) { 753 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 754 } 755 756 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 757 758 if (pcc->radix_page_info) { 759 for (i = 0; i < pcc->radix_page_info->count; i++) { 760 radix_AP_encodings[i] = 761 cpu_to_be32(pcc->radix_page_info->entries[i]); 762 } 763 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 764 radix_AP_encodings, 765 pcc->radix_page_info->count * 766 sizeof(radix_AP_encodings[0])))); 767 } 768 769 /* 770 * We set this property to let the guest know that it can use the large 771 * decrementer and its width in bits. 772 */ 773 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 774 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 775 pcc->lrg_decr_bits))); 776 } 777 778 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 779 { 780 CPUState **rev; 781 CPUState *cs; 782 int n_cpus; 783 int cpus_offset; 784 int i; 785 786 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 787 _FDT(cpus_offset); 788 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 789 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 790 791 /* 792 * We walk the CPUs in reverse order to ensure that CPU DT nodes 793 * created by fdt_add_subnode() end up in the right order in FDT 794 * for the guest kernel the enumerate the CPUs correctly. 795 * 796 * The CPU list cannot be traversed in reverse order, so we need 797 * to do extra work. 798 */ 799 n_cpus = 0; 800 rev = NULL; 801 CPU_FOREACH(cs) { 802 rev = g_renew(CPUState *, rev, n_cpus + 1); 803 rev[n_cpus++] = cs; 804 } 805 806 for (i = n_cpus - 1; i >= 0; i--) { 807 CPUState *cs = rev[i]; 808 PowerPCCPU *cpu = POWERPC_CPU(cs); 809 int index = spapr_get_vcpu_id(cpu); 810 DeviceClass *dc = DEVICE_GET_CLASS(cs); 811 g_autofree char *nodename = NULL; 812 int offset; 813 814 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 815 continue; 816 } 817 818 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 819 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 820 _FDT(offset); 821 spapr_dt_cpu(cs, fdt, offset, spapr); 822 } 823 824 g_free(rev); 825 } 826 827 static int spapr_dt_rng(void *fdt) 828 { 829 int node; 830 int ret; 831 832 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 833 if (node <= 0) { 834 return -1; 835 } 836 ret = fdt_setprop_string(fdt, node, "device_type", 837 "ibm,platform-facilities"); 838 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 839 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 840 841 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 842 if (node <= 0) { 843 return -1; 844 } 845 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 846 847 return ret ? -1 : 0; 848 } 849 850 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 851 { 852 MachineState *ms = MACHINE(spapr); 853 int rtas; 854 GString *hypertas = g_string_sized_new(256); 855 GString *qemu_hypertas = g_string_sized_new(256); 856 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 857 memory_region_size(&MACHINE(spapr)->device_memory->mr); 858 uint32_t lrdr_capacity[] = { 859 cpu_to_be32(max_device_addr >> 32), 860 cpu_to_be32(max_device_addr & 0xffffffff), 861 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 862 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 863 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 864 }; 865 866 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 867 868 /* hypertas */ 869 add_str(hypertas, "hcall-pft"); 870 add_str(hypertas, "hcall-term"); 871 add_str(hypertas, "hcall-dabr"); 872 add_str(hypertas, "hcall-interrupt"); 873 add_str(hypertas, "hcall-tce"); 874 add_str(hypertas, "hcall-vio"); 875 add_str(hypertas, "hcall-splpar"); 876 add_str(hypertas, "hcall-join"); 877 add_str(hypertas, "hcall-bulk"); 878 add_str(hypertas, "hcall-set-mode"); 879 add_str(hypertas, "hcall-sprg0"); 880 add_str(hypertas, "hcall-copy"); 881 add_str(hypertas, "hcall-debug"); 882 add_str(hypertas, "hcall-vphn"); 883 add_str(qemu_hypertas, "hcall-memop1"); 884 885 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 886 add_str(hypertas, "hcall-multi-tce"); 887 } 888 889 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 890 add_str(hypertas, "hcall-hpt-resize"); 891 } 892 893 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 894 hypertas->str, hypertas->len)); 895 g_string_free(hypertas, TRUE); 896 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 897 qemu_hypertas->str, qemu_hypertas->len)); 898 g_string_free(qemu_hypertas, TRUE); 899 900 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 901 902 /* 903 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 904 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 905 * 906 * The system reset requirements are driven by existing Linux and PowerVM 907 * implementation which (contrary to PAPR) saves r3 in the error log 908 * structure like machine check, so Linux expects to find the saved r3 909 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 910 * does not look at the error value). 911 * 912 * System reset interrupts are not subject to interlock like machine 913 * check, so this memory area could be corrupted if the sreset is 914 * interrupted by a machine check (or vice versa) if it was shared. To 915 * prevent this, system reset uses per-CPU areas for the sreset save 916 * area. A system reset that interrupts a system reset handler could 917 * still overwrite this area, but Linux doesn't try to recover in that 918 * case anyway. 919 * 920 * The extra 8 bytes is required because Linux's FWNMI error log check 921 * is off-by-one. 922 */ 923 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX + 924 ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t))); 925 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 926 RTAS_ERROR_LOG_MAX)); 927 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 928 RTAS_EVENT_SCAN_RATE)); 929 930 g_assert(msi_nonbroken); 931 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 932 933 /* 934 * According to PAPR, rtas ibm,os-term does not guarantee a return 935 * back to the guest cpu. 936 * 937 * While an additional ibm,extended-os-term property indicates 938 * that rtas call return will always occur. Set this property. 939 */ 940 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 941 942 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 943 lrdr_capacity, sizeof(lrdr_capacity))); 944 945 spapr_dt_rtas_tokens(fdt, rtas); 946 } 947 948 /* 949 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 950 * and the XIVE features that the guest may request and thus the valid 951 * values for bytes 23..26 of option vector 5: 952 */ 953 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 954 int chosen) 955 { 956 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 957 958 char val[2 * 4] = { 959 23, 0x00, /* XICS / XIVE mode */ 960 24, 0x00, /* Hash/Radix, filled in below. */ 961 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 962 26, 0x40, /* Radix options: GTSE == yes. */ 963 }; 964 965 if (spapr->irq->xics && spapr->irq->xive) { 966 val[1] = SPAPR_OV5_XIVE_BOTH; 967 } else if (spapr->irq->xive) { 968 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 969 } else { 970 assert(spapr->irq->xics); 971 val[1] = SPAPR_OV5_XIVE_LEGACY; 972 } 973 974 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 975 first_ppc_cpu->compat_pvr)) { 976 /* 977 * If we're in a pre POWER9 compat mode then the guest should 978 * do hash and use the legacy interrupt mode 979 */ 980 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 981 val[3] = 0x00; /* Hash */ 982 spapr_check_mmu_mode(false); 983 } else if (kvm_enabled()) { 984 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 985 val[3] = 0x80; /* OV5_MMU_BOTH */ 986 } else if (kvmppc_has_cap_mmu_radix()) { 987 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 988 } else { 989 val[3] = 0x00; /* Hash */ 990 } 991 } else { 992 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 993 val[3] = 0xC0; 994 } 995 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 996 val, sizeof(val))); 997 } 998 999 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1000 { 1001 MachineState *machine = MACHINE(spapr); 1002 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1003 int chosen; 1004 1005 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1006 1007 if (reset) { 1008 const char *boot_device = spapr->boot_device; 1009 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1010 size_t cb = 0; 1011 char *bootlist = get_boot_devices_list(&cb); 1012 1013 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1014 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1015 machine->kernel_cmdline)); 1016 } 1017 1018 if (spapr->initrd_size) { 1019 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1020 spapr->initrd_base)); 1021 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1022 spapr->initrd_base + spapr->initrd_size)); 1023 } 1024 1025 if (spapr->kernel_size) { 1026 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1027 cpu_to_be64(spapr->kernel_size) }; 1028 1029 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1030 &kprop, sizeof(kprop))); 1031 if (spapr->kernel_le) { 1032 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1033 } 1034 } 1035 if (boot_menu) { 1036 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1037 } 1038 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1039 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1040 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1041 1042 if (cb && bootlist) { 1043 int i; 1044 1045 for (i = 0; i < cb; i++) { 1046 if (bootlist[i] == '\n') { 1047 bootlist[i] = ' '; 1048 } 1049 } 1050 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1051 } 1052 1053 if (boot_device && strlen(boot_device)) { 1054 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1055 } 1056 1057 if (!spapr->has_graphics && stdout_path) { 1058 /* 1059 * "linux,stdout-path" and "stdout" properties are 1060 * deprecated by linux kernel. New platforms should only 1061 * use the "stdout-path" property. Set the new property 1062 * and continue using older property to remain compatible 1063 * with the existing firmware. 1064 */ 1065 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1066 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1067 } 1068 1069 /* 1070 * We can deal with BAR reallocation just fine, advertise it 1071 * to the guest 1072 */ 1073 if (smc->linux_pci_probe) { 1074 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1075 } 1076 1077 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1078 1079 g_free(stdout_path); 1080 g_free(bootlist); 1081 } 1082 1083 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1084 } 1085 1086 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1087 { 1088 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1089 * KVM to work under pHyp with some guest co-operation */ 1090 int hypervisor; 1091 uint8_t hypercall[16]; 1092 1093 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1094 /* indicate KVM hypercall interface */ 1095 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1096 if (kvmppc_has_cap_fixup_hcalls()) { 1097 /* 1098 * Older KVM versions with older guest kernels were broken 1099 * with the magic page, don't allow the guest to map it. 1100 */ 1101 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1102 sizeof(hypercall))) { 1103 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1104 hypercall, sizeof(hypercall))); 1105 } 1106 } 1107 } 1108 1109 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1110 { 1111 MachineState *machine = MACHINE(spapr); 1112 MachineClass *mc = MACHINE_GET_CLASS(machine); 1113 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1114 uint32_t root_drc_type_mask = 0; 1115 int ret; 1116 void *fdt; 1117 SpaprPhbState *phb; 1118 char *buf; 1119 1120 fdt = g_malloc0(space); 1121 _FDT((fdt_create_empty_tree(fdt, space))); 1122 1123 /* Root node */ 1124 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1125 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1126 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1127 1128 /* Guest UUID & Name*/ 1129 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1130 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1131 if (qemu_uuid_set) { 1132 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1133 } 1134 g_free(buf); 1135 1136 if (qemu_get_vm_name()) { 1137 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1138 qemu_get_vm_name())); 1139 } 1140 1141 /* Host Model & Serial Number */ 1142 if (spapr->host_model) { 1143 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1144 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1145 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1146 g_free(buf); 1147 } 1148 1149 if (spapr->host_serial) { 1150 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1151 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1152 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1153 g_free(buf); 1154 } 1155 1156 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1157 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1158 1159 /* /interrupt controller */ 1160 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1161 1162 ret = spapr_dt_memory(spapr, fdt); 1163 if (ret < 0) { 1164 error_report("couldn't setup memory nodes in fdt"); 1165 exit(1); 1166 } 1167 1168 /* /vdevice */ 1169 spapr_dt_vdevice(spapr->vio_bus, fdt); 1170 1171 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1172 ret = spapr_dt_rng(fdt); 1173 if (ret < 0) { 1174 error_report("could not set up rng device in the fdt"); 1175 exit(1); 1176 } 1177 } 1178 1179 QLIST_FOREACH(phb, &spapr->phbs, list) { 1180 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1181 if (ret < 0) { 1182 error_report("couldn't setup PCI devices in fdt"); 1183 exit(1); 1184 } 1185 } 1186 1187 spapr_dt_cpus(fdt, spapr); 1188 1189 /* ibm,drc-indexes and friends */ 1190 if (smc->dr_lmb_enabled) { 1191 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1192 } 1193 if (smc->dr_phb_enabled) { 1194 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1195 } 1196 if (mc->nvdimm_supported) { 1197 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1198 } 1199 if (root_drc_type_mask) { 1200 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1201 } 1202 1203 if (mc->has_hotpluggable_cpus) { 1204 int offset = fdt_path_offset(fdt, "/cpus"); 1205 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1206 if (ret < 0) { 1207 error_report("Couldn't set up CPU DR device tree properties"); 1208 exit(1); 1209 } 1210 } 1211 1212 /* /event-sources */ 1213 spapr_dt_events(spapr, fdt); 1214 1215 /* /rtas */ 1216 spapr_dt_rtas(spapr, fdt); 1217 1218 /* /chosen */ 1219 spapr_dt_chosen(spapr, fdt, reset); 1220 1221 /* /hypervisor */ 1222 if (kvm_enabled()) { 1223 spapr_dt_hypervisor(spapr, fdt); 1224 } 1225 1226 /* Build memory reserve map */ 1227 if (reset) { 1228 if (spapr->kernel_size) { 1229 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1230 spapr->kernel_size))); 1231 } 1232 if (spapr->initrd_size) { 1233 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1234 spapr->initrd_size))); 1235 } 1236 } 1237 1238 /* NVDIMM devices */ 1239 if (mc->nvdimm_supported) { 1240 spapr_dt_persistent_memory(spapr, fdt); 1241 } 1242 1243 return fdt; 1244 } 1245 1246 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1247 { 1248 SpaprMachineState *spapr = opaque; 1249 1250 return (addr & 0x0fffffff) + spapr->kernel_addr; 1251 } 1252 1253 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1254 PowerPCCPU *cpu) 1255 { 1256 CPUPPCState *env = &cpu->env; 1257 1258 /* The TCG path should also be holding the BQL at this point */ 1259 g_assert(qemu_mutex_iothread_locked()); 1260 1261 if (msr_pr) { 1262 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1263 env->gpr[3] = H_PRIVILEGE; 1264 } else { 1265 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1266 } 1267 } 1268 1269 struct LPCRSyncState { 1270 target_ulong value; 1271 target_ulong mask; 1272 }; 1273 1274 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1275 { 1276 struct LPCRSyncState *s = arg.host_ptr; 1277 PowerPCCPU *cpu = POWERPC_CPU(cs); 1278 CPUPPCState *env = &cpu->env; 1279 target_ulong lpcr; 1280 1281 cpu_synchronize_state(cs); 1282 lpcr = env->spr[SPR_LPCR]; 1283 lpcr &= ~s->mask; 1284 lpcr |= s->value; 1285 ppc_store_lpcr(cpu, lpcr); 1286 } 1287 1288 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1289 { 1290 CPUState *cs; 1291 struct LPCRSyncState s = { 1292 .value = value, 1293 .mask = mask 1294 }; 1295 CPU_FOREACH(cs) { 1296 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1297 } 1298 } 1299 1300 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1301 { 1302 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1303 1304 /* Copy PATE1:GR into PATE0:HR */ 1305 entry->dw0 = spapr->patb_entry & PATE0_HR; 1306 entry->dw1 = spapr->patb_entry; 1307 } 1308 1309 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1310 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1311 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1312 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1313 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1314 1315 /* 1316 * Get the fd to access the kernel htab, re-opening it if necessary 1317 */ 1318 static int get_htab_fd(SpaprMachineState *spapr) 1319 { 1320 Error *local_err = NULL; 1321 1322 if (spapr->htab_fd >= 0) { 1323 return spapr->htab_fd; 1324 } 1325 1326 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1327 if (spapr->htab_fd < 0) { 1328 error_report_err(local_err); 1329 } 1330 1331 return spapr->htab_fd; 1332 } 1333 1334 void close_htab_fd(SpaprMachineState *spapr) 1335 { 1336 if (spapr->htab_fd >= 0) { 1337 close(spapr->htab_fd); 1338 } 1339 spapr->htab_fd = -1; 1340 } 1341 1342 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1343 { 1344 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1345 1346 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1347 } 1348 1349 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1350 { 1351 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1352 1353 assert(kvm_enabled()); 1354 1355 if (!spapr->htab) { 1356 return 0; 1357 } 1358 1359 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1360 } 1361 1362 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1363 hwaddr ptex, int n) 1364 { 1365 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1366 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1367 1368 if (!spapr->htab) { 1369 /* 1370 * HTAB is controlled by KVM. Fetch into temporary buffer 1371 */ 1372 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1373 kvmppc_read_hptes(hptes, ptex, n); 1374 return hptes; 1375 } 1376 1377 /* 1378 * HTAB is controlled by QEMU. Just point to the internally 1379 * accessible PTEG. 1380 */ 1381 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1382 } 1383 1384 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1385 const ppc_hash_pte64_t *hptes, 1386 hwaddr ptex, int n) 1387 { 1388 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1389 1390 if (!spapr->htab) { 1391 g_free((void *)hptes); 1392 } 1393 1394 /* Nothing to do for qemu managed HPT */ 1395 } 1396 1397 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1398 uint64_t pte0, uint64_t pte1) 1399 { 1400 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1401 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1402 1403 if (!spapr->htab) { 1404 kvmppc_write_hpte(ptex, pte0, pte1); 1405 } else { 1406 if (pte0 & HPTE64_V_VALID) { 1407 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1408 /* 1409 * When setting valid, we write PTE1 first. This ensures 1410 * proper synchronization with the reading code in 1411 * ppc_hash64_pteg_search() 1412 */ 1413 smp_wmb(); 1414 stq_p(spapr->htab + offset, pte0); 1415 } else { 1416 stq_p(spapr->htab + offset, pte0); 1417 /* 1418 * When clearing it we set PTE0 first. This ensures proper 1419 * synchronization with the reading code in 1420 * ppc_hash64_pteg_search() 1421 */ 1422 smp_wmb(); 1423 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1424 } 1425 } 1426 } 1427 1428 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1429 uint64_t pte1) 1430 { 1431 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1432 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1433 1434 if (!spapr->htab) { 1435 /* There should always be a hash table when this is called */ 1436 error_report("spapr_hpte_set_c called with no hash table !"); 1437 return; 1438 } 1439 1440 /* The HW performs a non-atomic byte update */ 1441 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1442 } 1443 1444 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1445 uint64_t pte1) 1446 { 1447 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1448 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1449 1450 if (!spapr->htab) { 1451 /* There should always be a hash table when this is called */ 1452 error_report("spapr_hpte_set_r called with no hash table !"); 1453 return; 1454 } 1455 1456 /* The HW performs a non-atomic byte update */ 1457 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1458 } 1459 1460 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1461 { 1462 int shift; 1463 1464 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1465 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1466 * that's much more than is needed for Linux guests */ 1467 shift = ctz64(pow2ceil(ramsize)) - 7; 1468 shift = MAX(shift, 18); /* Minimum architected size */ 1469 shift = MIN(shift, 46); /* Maximum architected size */ 1470 return shift; 1471 } 1472 1473 void spapr_free_hpt(SpaprMachineState *spapr) 1474 { 1475 g_free(spapr->htab); 1476 spapr->htab = NULL; 1477 spapr->htab_shift = 0; 1478 close_htab_fd(spapr); 1479 } 1480 1481 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1482 { 1483 ERRP_GUARD(); 1484 long rc; 1485 1486 /* Clean up any HPT info from a previous boot */ 1487 spapr_free_hpt(spapr); 1488 1489 rc = kvmppc_reset_htab(shift); 1490 1491 if (rc == -EOPNOTSUPP) { 1492 error_setg(errp, "HPT not supported in nested guests"); 1493 return -EOPNOTSUPP; 1494 } 1495 1496 if (rc < 0) { 1497 /* kernel-side HPT needed, but couldn't allocate one */ 1498 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1499 shift); 1500 error_append_hint(errp, "Try smaller maxmem?\n"); 1501 return -errno; 1502 } else if (rc > 0) { 1503 /* kernel-side HPT allocated */ 1504 if (rc != shift) { 1505 error_setg(errp, 1506 "Requested order %d HPT, but kernel allocated order %ld", 1507 shift, rc); 1508 error_append_hint(errp, "Try smaller maxmem?\n"); 1509 return -ENOSPC; 1510 } 1511 1512 spapr->htab_shift = shift; 1513 spapr->htab = NULL; 1514 } else { 1515 /* kernel-side HPT not needed, allocate in userspace instead */ 1516 size_t size = 1ULL << shift; 1517 int i; 1518 1519 spapr->htab = qemu_memalign(size, size); 1520 memset(spapr->htab, 0, size); 1521 spapr->htab_shift = shift; 1522 1523 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1524 DIRTY_HPTE(HPTE(spapr->htab, i)); 1525 } 1526 } 1527 /* We're setting up a hash table, so that means we're not radix */ 1528 spapr->patb_entry = 0; 1529 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1530 return 0; 1531 } 1532 1533 void spapr_setup_hpt(SpaprMachineState *spapr) 1534 { 1535 int hpt_shift; 1536 1537 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1538 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1539 } else { 1540 uint64_t current_ram_size; 1541 1542 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1543 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1544 } 1545 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1546 1547 if (kvm_enabled()) { 1548 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1549 1550 /* Check our RMA fits in the possible VRMA */ 1551 if (vrma_limit < spapr->rma_size) { 1552 error_report("Unable to create %" HWADDR_PRIu 1553 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1554 spapr->rma_size / MiB, vrma_limit / MiB); 1555 exit(EXIT_FAILURE); 1556 } 1557 } 1558 } 1559 1560 void spapr_check_mmu_mode(bool guest_radix) 1561 { 1562 if (guest_radix) { 1563 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1564 error_report("Guest requested unavailable MMU mode (radix)."); 1565 exit(EXIT_FAILURE); 1566 } 1567 } else { 1568 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1569 && !kvmppc_has_cap_mmu_hash_v3()) { 1570 error_report("Guest requested unavailable MMU mode (hash)."); 1571 exit(EXIT_FAILURE); 1572 } 1573 } 1574 } 1575 1576 static void spapr_machine_reset(MachineState *machine) 1577 { 1578 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1579 PowerPCCPU *first_ppc_cpu; 1580 hwaddr fdt_addr; 1581 void *fdt; 1582 int rc; 1583 1584 pef_kvm_reset(machine->cgs, &error_fatal); 1585 spapr_caps_apply(spapr); 1586 1587 first_ppc_cpu = POWERPC_CPU(first_cpu); 1588 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1589 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1590 spapr->max_compat_pvr)) { 1591 /* 1592 * If using KVM with radix mode available, VCPUs can be started 1593 * without a HPT because KVM will start them in radix mode. 1594 * Set the GR bit in PATE so that we know there is no HPT. 1595 */ 1596 spapr->patb_entry = PATE1_GR; 1597 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1598 } else { 1599 spapr_setup_hpt(spapr); 1600 } 1601 1602 qemu_devices_reset(); 1603 1604 spapr_ovec_cleanup(spapr->ov5_cas); 1605 spapr->ov5_cas = spapr_ovec_new(); 1606 1607 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1608 1609 /* 1610 * This is fixing some of the default configuration of the XIVE 1611 * devices. To be called after the reset of the machine devices. 1612 */ 1613 spapr_irq_reset(spapr, &error_fatal); 1614 1615 /* 1616 * There is no CAS under qtest. Simulate one to please the code that 1617 * depends on spapr->ov5_cas. This is especially needed to test device 1618 * unplug, so we do that before resetting the DRCs. 1619 */ 1620 if (qtest_enabled()) { 1621 spapr_ovec_cleanup(spapr->ov5_cas); 1622 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1623 } 1624 1625 /* DRC reset may cause a device to be unplugged. This will cause troubles 1626 * if this device is used by another device (eg, a running vhost backend 1627 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1628 * situations, we reset DRCs after all devices have been reset. 1629 */ 1630 spapr_drc_reset_all(spapr); 1631 1632 spapr_clear_pending_events(spapr); 1633 1634 /* 1635 * We place the device tree just below either the top of the RMA, 1636 * or just below 2GB, whichever is lower, so that it can be 1637 * processed with 32-bit real mode code if necessary 1638 */ 1639 fdt_addr = MIN(spapr->rma_size, FDT_MAX_ADDR) - FDT_MAX_SIZE; 1640 1641 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1642 1643 rc = fdt_pack(fdt); 1644 1645 /* Should only fail if we've built a corrupted tree */ 1646 assert(rc == 0); 1647 1648 /* Load the fdt */ 1649 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1650 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1651 g_free(spapr->fdt_blob); 1652 spapr->fdt_size = fdt_totalsize(fdt); 1653 spapr->fdt_initial_size = spapr->fdt_size; 1654 spapr->fdt_blob = fdt; 1655 1656 /* Set up the entry state */ 1657 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); 1658 first_ppc_cpu->env.gpr[5] = 0; 1659 1660 spapr->fwnmi_system_reset_addr = -1; 1661 spapr->fwnmi_machine_check_addr = -1; 1662 spapr->fwnmi_machine_check_interlock = -1; 1663 1664 /* Signal all vCPUs waiting on this condition */ 1665 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1666 1667 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1668 } 1669 1670 static void spapr_create_nvram(SpaprMachineState *spapr) 1671 { 1672 DeviceState *dev = qdev_new("spapr-nvram"); 1673 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1674 1675 if (dinfo) { 1676 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1677 &error_fatal); 1678 } 1679 1680 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1681 1682 spapr->nvram = (struct SpaprNvram *)dev; 1683 } 1684 1685 static void spapr_rtc_create(SpaprMachineState *spapr) 1686 { 1687 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1688 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1689 &error_fatal, NULL); 1690 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1691 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1692 "date"); 1693 } 1694 1695 /* Returns whether we want to use VGA or not */ 1696 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1697 { 1698 switch (vga_interface_type) { 1699 case VGA_NONE: 1700 return false; 1701 case VGA_DEVICE: 1702 return true; 1703 case VGA_STD: 1704 case VGA_VIRTIO: 1705 case VGA_CIRRUS: 1706 return pci_vga_init(pci_bus) != NULL; 1707 default: 1708 error_setg(errp, 1709 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1710 return false; 1711 } 1712 } 1713 1714 static int spapr_pre_load(void *opaque) 1715 { 1716 int rc; 1717 1718 rc = spapr_caps_pre_load(opaque); 1719 if (rc) { 1720 return rc; 1721 } 1722 1723 return 0; 1724 } 1725 1726 static int spapr_post_load(void *opaque, int version_id) 1727 { 1728 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1729 int err = 0; 1730 1731 err = spapr_caps_post_migration(spapr); 1732 if (err) { 1733 return err; 1734 } 1735 1736 /* 1737 * In earlier versions, there was no separate qdev for the PAPR 1738 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1739 * So when migrating from those versions, poke the incoming offset 1740 * value into the RTC device 1741 */ 1742 if (version_id < 3) { 1743 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1744 if (err) { 1745 return err; 1746 } 1747 } 1748 1749 if (kvm_enabled() && spapr->patb_entry) { 1750 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1751 bool radix = !!(spapr->patb_entry & PATE1_GR); 1752 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1753 1754 /* 1755 * Update LPCR:HR and UPRT as they may not be set properly in 1756 * the stream 1757 */ 1758 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1759 LPCR_HR | LPCR_UPRT); 1760 1761 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1762 if (err) { 1763 error_report("Process table config unsupported by the host"); 1764 return -EINVAL; 1765 } 1766 } 1767 1768 err = spapr_irq_post_load(spapr, version_id); 1769 if (err) { 1770 return err; 1771 } 1772 1773 return err; 1774 } 1775 1776 static int spapr_pre_save(void *opaque) 1777 { 1778 int rc; 1779 1780 rc = spapr_caps_pre_save(opaque); 1781 if (rc) { 1782 return rc; 1783 } 1784 1785 return 0; 1786 } 1787 1788 static bool version_before_3(void *opaque, int version_id) 1789 { 1790 return version_id < 3; 1791 } 1792 1793 static bool spapr_pending_events_needed(void *opaque) 1794 { 1795 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1796 return !QTAILQ_EMPTY(&spapr->pending_events); 1797 } 1798 1799 static const VMStateDescription vmstate_spapr_event_entry = { 1800 .name = "spapr_event_log_entry", 1801 .version_id = 1, 1802 .minimum_version_id = 1, 1803 .fields = (VMStateField[]) { 1804 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1805 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1806 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1807 NULL, extended_length), 1808 VMSTATE_END_OF_LIST() 1809 }, 1810 }; 1811 1812 static const VMStateDescription vmstate_spapr_pending_events = { 1813 .name = "spapr_pending_events", 1814 .version_id = 1, 1815 .minimum_version_id = 1, 1816 .needed = spapr_pending_events_needed, 1817 .fields = (VMStateField[]) { 1818 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1819 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1820 VMSTATE_END_OF_LIST() 1821 }, 1822 }; 1823 1824 static bool spapr_ov5_cas_needed(void *opaque) 1825 { 1826 SpaprMachineState *spapr = opaque; 1827 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1828 bool cas_needed; 1829 1830 /* Prior to the introduction of SpaprOptionVector, we had two option 1831 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1832 * Both of these options encode machine topology into the device-tree 1833 * in such a way that the now-booted OS should still be able to interact 1834 * appropriately with QEMU regardless of what options were actually 1835 * negotiatied on the source side. 1836 * 1837 * As such, we can avoid migrating the CAS-negotiated options if these 1838 * are the only options available on the current machine/platform. 1839 * Since these are the only options available for pseries-2.7 and 1840 * earlier, this allows us to maintain old->new/new->old migration 1841 * compatibility. 1842 * 1843 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1844 * via default pseries-2.8 machines and explicit command-line parameters. 1845 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1846 * of the actual CAS-negotiated values to continue working properly. For 1847 * example, availability of memory unplug depends on knowing whether 1848 * OV5_HP_EVT was negotiated via CAS. 1849 * 1850 * Thus, for any cases where the set of available CAS-negotiatable 1851 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1852 * include the CAS-negotiated options in the migration stream, unless 1853 * if they affect boot time behaviour only. 1854 */ 1855 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1856 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1857 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1858 1859 /* We need extra information if we have any bits outside the mask 1860 * defined above */ 1861 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1862 1863 spapr_ovec_cleanup(ov5_mask); 1864 1865 return cas_needed; 1866 } 1867 1868 static const VMStateDescription vmstate_spapr_ov5_cas = { 1869 .name = "spapr_option_vector_ov5_cas", 1870 .version_id = 1, 1871 .minimum_version_id = 1, 1872 .needed = spapr_ov5_cas_needed, 1873 .fields = (VMStateField[]) { 1874 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1875 vmstate_spapr_ovec, SpaprOptionVector), 1876 VMSTATE_END_OF_LIST() 1877 }, 1878 }; 1879 1880 static bool spapr_patb_entry_needed(void *opaque) 1881 { 1882 SpaprMachineState *spapr = opaque; 1883 1884 return !!spapr->patb_entry; 1885 } 1886 1887 static const VMStateDescription vmstate_spapr_patb_entry = { 1888 .name = "spapr_patb_entry", 1889 .version_id = 1, 1890 .minimum_version_id = 1, 1891 .needed = spapr_patb_entry_needed, 1892 .fields = (VMStateField[]) { 1893 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1894 VMSTATE_END_OF_LIST() 1895 }, 1896 }; 1897 1898 static bool spapr_irq_map_needed(void *opaque) 1899 { 1900 SpaprMachineState *spapr = opaque; 1901 1902 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1903 } 1904 1905 static const VMStateDescription vmstate_spapr_irq_map = { 1906 .name = "spapr_irq_map", 1907 .version_id = 1, 1908 .minimum_version_id = 1, 1909 .needed = spapr_irq_map_needed, 1910 .fields = (VMStateField[]) { 1911 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1912 VMSTATE_END_OF_LIST() 1913 }, 1914 }; 1915 1916 static bool spapr_dtb_needed(void *opaque) 1917 { 1918 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1919 1920 return smc->update_dt_enabled; 1921 } 1922 1923 static int spapr_dtb_pre_load(void *opaque) 1924 { 1925 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1926 1927 g_free(spapr->fdt_blob); 1928 spapr->fdt_blob = NULL; 1929 spapr->fdt_size = 0; 1930 1931 return 0; 1932 } 1933 1934 static const VMStateDescription vmstate_spapr_dtb = { 1935 .name = "spapr_dtb", 1936 .version_id = 1, 1937 .minimum_version_id = 1, 1938 .needed = spapr_dtb_needed, 1939 .pre_load = spapr_dtb_pre_load, 1940 .fields = (VMStateField[]) { 1941 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1942 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1943 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1944 fdt_size), 1945 VMSTATE_END_OF_LIST() 1946 }, 1947 }; 1948 1949 static bool spapr_fwnmi_needed(void *opaque) 1950 { 1951 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1952 1953 return spapr->fwnmi_machine_check_addr != -1; 1954 } 1955 1956 static int spapr_fwnmi_pre_save(void *opaque) 1957 { 1958 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1959 1960 /* 1961 * Check if machine check handling is in progress and print a 1962 * warning message. 1963 */ 1964 if (spapr->fwnmi_machine_check_interlock != -1) { 1965 warn_report("A machine check is being handled during migration. The" 1966 "handler may run and log hardware error on the destination"); 1967 } 1968 1969 return 0; 1970 } 1971 1972 static const VMStateDescription vmstate_spapr_fwnmi = { 1973 .name = "spapr_fwnmi", 1974 .version_id = 1, 1975 .minimum_version_id = 1, 1976 .needed = spapr_fwnmi_needed, 1977 .pre_save = spapr_fwnmi_pre_save, 1978 .fields = (VMStateField[]) { 1979 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 1980 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 1981 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 1982 VMSTATE_END_OF_LIST() 1983 }, 1984 }; 1985 1986 static const VMStateDescription vmstate_spapr = { 1987 .name = "spapr", 1988 .version_id = 3, 1989 .minimum_version_id = 1, 1990 .pre_load = spapr_pre_load, 1991 .post_load = spapr_post_load, 1992 .pre_save = spapr_pre_save, 1993 .fields = (VMStateField[]) { 1994 /* used to be @next_irq */ 1995 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1996 1997 /* RTC offset */ 1998 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 1999 2000 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2001 VMSTATE_END_OF_LIST() 2002 }, 2003 .subsections = (const VMStateDescription*[]) { 2004 &vmstate_spapr_ov5_cas, 2005 &vmstate_spapr_patb_entry, 2006 &vmstate_spapr_pending_events, 2007 &vmstate_spapr_cap_htm, 2008 &vmstate_spapr_cap_vsx, 2009 &vmstate_spapr_cap_dfp, 2010 &vmstate_spapr_cap_cfpc, 2011 &vmstate_spapr_cap_sbbc, 2012 &vmstate_spapr_cap_ibs, 2013 &vmstate_spapr_cap_hpt_maxpagesize, 2014 &vmstate_spapr_irq_map, 2015 &vmstate_spapr_cap_nested_kvm_hv, 2016 &vmstate_spapr_dtb, 2017 &vmstate_spapr_cap_large_decr, 2018 &vmstate_spapr_cap_ccf_assist, 2019 &vmstate_spapr_cap_fwnmi, 2020 &vmstate_spapr_fwnmi, 2021 NULL 2022 } 2023 }; 2024 2025 static int htab_save_setup(QEMUFile *f, void *opaque) 2026 { 2027 SpaprMachineState *spapr = opaque; 2028 2029 /* "Iteration" header */ 2030 if (!spapr->htab_shift) { 2031 qemu_put_be32(f, -1); 2032 } else { 2033 qemu_put_be32(f, spapr->htab_shift); 2034 } 2035 2036 if (spapr->htab) { 2037 spapr->htab_save_index = 0; 2038 spapr->htab_first_pass = true; 2039 } else { 2040 if (spapr->htab_shift) { 2041 assert(kvm_enabled()); 2042 } 2043 } 2044 2045 2046 return 0; 2047 } 2048 2049 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2050 int chunkstart, int n_valid, int n_invalid) 2051 { 2052 qemu_put_be32(f, chunkstart); 2053 qemu_put_be16(f, n_valid); 2054 qemu_put_be16(f, n_invalid); 2055 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2056 HASH_PTE_SIZE_64 * n_valid); 2057 } 2058 2059 static void htab_save_end_marker(QEMUFile *f) 2060 { 2061 qemu_put_be32(f, 0); 2062 qemu_put_be16(f, 0); 2063 qemu_put_be16(f, 0); 2064 } 2065 2066 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2067 int64_t max_ns) 2068 { 2069 bool has_timeout = max_ns != -1; 2070 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2071 int index = spapr->htab_save_index; 2072 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2073 2074 assert(spapr->htab_first_pass); 2075 2076 do { 2077 int chunkstart; 2078 2079 /* Consume invalid HPTEs */ 2080 while ((index < htabslots) 2081 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2082 CLEAN_HPTE(HPTE(spapr->htab, index)); 2083 index++; 2084 } 2085 2086 /* Consume valid HPTEs */ 2087 chunkstart = index; 2088 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2089 && HPTE_VALID(HPTE(spapr->htab, index))) { 2090 CLEAN_HPTE(HPTE(spapr->htab, index)); 2091 index++; 2092 } 2093 2094 if (index > chunkstart) { 2095 int n_valid = index - chunkstart; 2096 2097 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2098 2099 if (has_timeout && 2100 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2101 break; 2102 } 2103 } 2104 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2105 2106 if (index >= htabslots) { 2107 assert(index == htabslots); 2108 index = 0; 2109 spapr->htab_first_pass = false; 2110 } 2111 spapr->htab_save_index = index; 2112 } 2113 2114 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2115 int64_t max_ns) 2116 { 2117 bool final = max_ns < 0; 2118 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2119 int examined = 0, sent = 0; 2120 int index = spapr->htab_save_index; 2121 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2122 2123 assert(!spapr->htab_first_pass); 2124 2125 do { 2126 int chunkstart, invalidstart; 2127 2128 /* Consume non-dirty HPTEs */ 2129 while ((index < htabslots) 2130 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2131 index++; 2132 examined++; 2133 } 2134 2135 chunkstart = index; 2136 /* Consume valid dirty HPTEs */ 2137 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2138 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2139 && HPTE_VALID(HPTE(spapr->htab, index))) { 2140 CLEAN_HPTE(HPTE(spapr->htab, index)); 2141 index++; 2142 examined++; 2143 } 2144 2145 invalidstart = index; 2146 /* Consume invalid dirty HPTEs */ 2147 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2148 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2149 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2150 CLEAN_HPTE(HPTE(spapr->htab, index)); 2151 index++; 2152 examined++; 2153 } 2154 2155 if (index > chunkstart) { 2156 int n_valid = invalidstart - chunkstart; 2157 int n_invalid = index - invalidstart; 2158 2159 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2160 sent += index - chunkstart; 2161 2162 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2163 break; 2164 } 2165 } 2166 2167 if (examined >= htabslots) { 2168 break; 2169 } 2170 2171 if (index >= htabslots) { 2172 assert(index == htabslots); 2173 index = 0; 2174 } 2175 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2176 2177 if (index >= htabslots) { 2178 assert(index == htabslots); 2179 index = 0; 2180 } 2181 2182 spapr->htab_save_index = index; 2183 2184 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2185 } 2186 2187 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2188 #define MAX_KVM_BUF_SIZE 2048 2189 2190 static int htab_save_iterate(QEMUFile *f, void *opaque) 2191 { 2192 SpaprMachineState *spapr = opaque; 2193 int fd; 2194 int rc = 0; 2195 2196 /* Iteration header */ 2197 if (!spapr->htab_shift) { 2198 qemu_put_be32(f, -1); 2199 return 1; 2200 } else { 2201 qemu_put_be32(f, 0); 2202 } 2203 2204 if (!spapr->htab) { 2205 assert(kvm_enabled()); 2206 2207 fd = get_htab_fd(spapr); 2208 if (fd < 0) { 2209 return fd; 2210 } 2211 2212 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2213 if (rc < 0) { 2214 return rc; 2215 } 2216 } else if (spapr->htab_first_pass) { 2217 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2218 } else { 2219 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2220 } 2221 2222 htab_save_end_marker(f); 2223 2224 return rc; 2225 } 2226 2227 static int htab_save_complete(QEMUFile *f, void *opaque) 2228 { 2229 SpaprMachineState *spapr = opaque; 2230 int fd; 2231 2232 /* Iteration header */ 2233 if (!spapr->htab_shift) { 2234 qemu_put_be32(f, -1); 2235 return 0; 2236 } else { 2237 qemu_put_be32(f, 0); 2238 } 2239 2240 if (!spapr->htab) { 2241 int rc; 2242 2243 assert(kvm_enabled()); 2244 2245 fd = get_htab_fd(spapr); 2246 if (fd < 0) { 2247 return fd; 2248 } 2249 2250 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2251 if (rc < 0) { 2252 return rc; 2253 } 2254 } else { 2255 if (spapr->htab_first_pass) { 2256 htab_save_first_pass(f, spapr, -1); 2257 } 2258 htab_save_later_pass(f, spapr, -1); 2259 } 2260 2261 /* End marker */ 2262 htab_save_end_marker(f); 2263 2264 return 0; 2265 } 2266 2267 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2268 { 2269 SpaprMachineState *spapr = opaque; 2270 uint32_t section_hdr; 2271 int fd = -1; 2272 Error *local_err = NULL; 2273 2274 if (version_id < 1 || version_id > 1) { 2275 error_report("htab_load() bad version"); 2276 return -EINVAL; 2277 } 2278 2279 section_hdr = qemu_get_be32(f); 2280 2281 if (section_hdr == -1) { 2282 spapr_free_hpt(spapr); 2283 return 0; 2284 } 2285 2286 if (section_hdr) { 2287 int ret; 2288 2289 /* First section gives the htab size */ 2290 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2291 if (ret < 0) { 2292 error_report_err(local_err); 2293 return ret; 2294 } 2295 return 0; 2296 } 2297 2298 if (!spapr->htab) { 2299 assert(kvm_enabled()); 2300 2301 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2302 if (fd < 0) { 2303 error_report_err(local_err); 2304 return fd; 2305 } 2306 } 2307 2308 while (true) { 2309 uint32_t index; 2310 uint16_t n_valid, n_invalid; 2311 2312 index = qemu_get_be32(f); 2313 n_valid = qemu_get_be16(f); 2314 n_invalid = qemu_get_be16(f); 2315 2316 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2317 /* End of Stream */ 2318 break; 2319 } 2320 2321 if ((index + n_valid + n_invalid) > 2322 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2323 /* Bad index in stream */ 2324 error_report( 2325 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2326 index, n_valid, n_invalid, spapr->htab_shift); 2327 return -EINVAL; 2328 } 2329 2330 if (spapr->htab) { 2331 if (n_valid) { 2332 qemu_get_buffer(f, HPTE(spapr->htab, index), 2333 HASH_PTE_SIZE_64 * n_valid); 2334 } 2335 if (n_invalid) { 2336 memset(HPTE(spapr->htab, index + n_valid), 0, 2337 HASH_PTE_SIZE_64 * n_invalid); 2338 } 2339 } else { 2340 int rc; 2341 2342 assert(fd >= 0); 2343 2344 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2345 &local_err); 2346 if (rc < 0) { 2347 error_report_err(local_err); 2348 return rc; 2349 } 2350 } 2351 } 2352 2353 if (!spapr->htab) { 2354 assert(fd >= 0); 2355 close(fd); 2356 } 2357 2358 return 0; 2359 } 2360 2361 static void htab_save_cleanup(void *opaque) 2362 { 2363 SpaprMachineState *spapr = opaque; 2364 2365 close_htab_fd(spapr); 2366 } 2367 2368 static SaveVMHandlers savevm_htab_handlers = { 2369 .save_setup = htab_save_setup, 2370 .save_live_iterate = htab_save_iterate, 2371 .save_live_complete_precopy = htab_save_complete, 2372 .save_cleanup = htab_save_cleanup, 2373 .load_state = htab_load, 2374 }; 2375 2376 static void spapr_boot_set(void *opaque, const char *boot_device, 2377 Error **errp) 2378 { 2379 SpaprMachineState *spapr = SPAPR_MACHINE(opaque); 2380 2381 g_free(spapr->boot_device); 2382 spapr->boot_device = g_strdup(boot_device); 2383 } 2384 2385 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2386 { 2387 MachineState *machine = MACHINE(spapr); 2388 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2389 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2390 int i; 2391 2392 for (i = 0; i < nr_lmbs; i++) { 2393 uint64_t addr; 2394 2395 addr = i * lmb_size + machine->device_memory->base; 2396 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2397 addr / lmb_size); 2398 } 2399 } 2400 2401 /* 2402 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2403 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2404 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2405 */ 2406 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2407 { 2408 int i; 2409 2410 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2411 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2412 " is not aligned to %" PRIu64 " MiB", 2413 machine->ram_size, 2414 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2415 return; 2416 } 2417 2418 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2419 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2420 " is not aligned to %" PRIu64 " MiB", 2421 machine->ram_size, 2422 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2423 return; 2424 } 2425 2426 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2427 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2428 error_setg(errp, 2429 "Node %d memory size 0x%" PRIx64 2430 " is not aligned to %" PRIu64 " MiB", 2431 i, machine->numa_state->nodes[i].node_mem, 2432 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2433 return; 2434 } 2435 } 2436 } 2437 2438 /* find cpu slot in machine->possible_cpus by core_id */ 2439 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2440 { 2441 int index = id / ms->smp.threads; 2442 2443 if (index >= ms->possible_cpus->len) { 2444 return NULL; 2445 } 2446 if (idx) { 2447 *idx = index; 2448 } 2449 return &ms->possible_cpus->cpus[index]; 2450 } 2451 2452 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2453 { 2454 MachineState *ms = MACHINE(spapr); 2455 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2456 Error *local_err = NULL; 2457 bool vsmt_user = !!spapr->vsmt; 2458 int kvm_smt = kvmppc_smt_threads(); 2459 int ret; 2460 unsigned int smp_threads = ms->smp.threads; 2461 2462 if (!kvm_enabled() && (smp_threads > 1)) { 2463 error_setg(errp, "TCG cannot support more than 1 thread/core " 2464 "on a pseries machine"); 2465 return; 2466 } 2467 if (!is_power_of_2(smp_threads)) { 2468 error_setg(errp, "Cannot support %d threads/core on a pseries " 2469 "machine because it must be a power of 2", smp_threads); 2470 return; 2471 } 2472 2473 /* Detemine the VSMT mode to use: */ 2474 if (vsmt_user) { 2475 if (spapr->vsmt < smp_threads) { 2476 error_setg(errp, "Cannot support VSMT mode %d" 2477 " because it must be >= threads/core (%d)", 2478 spapr->vsmt, smp_threads); 2479 return; 2480 } 2481 /* In this case, spapr->vsmt has been set by the command line */ 2482 } else if (!smc->smp_threads_vsmt) { 2483 /* 2484 * Default VSMT value is tricky, because we need it to be as 2485 * consistent as possible (for migration), but this requires 2486 * changing it for at least some existing cases. We pick 8 as 2487 * the value that we'd get with KVM on POWER8, the 2488 * overwhelmingly common case in production systems. 2489 */ 2490 spapr->vsmt = MAX(8, smp_threads); 2491 } else { 2492 spapr->vsmt = smp_threads; 2493 } 2494 2495 /* KVM: If necessary, set the SMT mode: */ 2496 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2497 ret = kvmppc_set_smt_threads(spapr->vsmt); 2498 if (ret) { 2499 /* Looks like KVM isn't able to change VSMT mode */ 2500 error_setg(&local_err, 2501 "Failed to set KVM's VSMT mode to %d (errno %d)", 2502 spapr->vsmt, ret); 2503 /* We can live with that if the default one is big enough 2504 * for the number of threads, and a submultiple of the one 2505 * we want. In this case we'll waste some vcpu ids, but 2506 * behaviour will be correct */ 2507 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2508 warn_report_err(local_err); 2509 } else { 2510 if (!vsmt_user) { 2511 error_append_hint(&local_err, 2512 "On PPC, a VM with %d threads/core" 2513 " on a host with %d threads/core" 2514 " requires the use of VSMT mode %d.\n", 2515 smp_threads, kvm_smt, spapr->vsmt); 2516 } 2517 kvmppc_error_append_smt_possible_hint(&local_err); 2518 error_propagate(errp, local_err); 2519 } 2520 } 2521 } 2522 /* else TCG: nothing to do currently */ 2523 } 2524 2525 static void spapr_init_cpus(SpaprMachineState *spapr) 2526 { 2527 MachineState *machine = MACHINE(spapr); 2528 MachineClass *mc = MACHINE_GET_CLASS(machine); 2529 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2530 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2531 const CPUArchIdList *possible_cpus; 2532 unsigned int smp_cpus = machine->smp.cpus; 2533 unsigned int smp_threads = machine->smp.threads; 2534 unsigned int max_cpus = machine->smp.max_cpus; 2535 int boot_cores_nr = smp_cpus / smp_threads; 2536 int i; 2537 2538 possible_cpus = mc->possible_cpu_arch_ids(machine); 2539 if (mc->has_hotpluggable_cpus) { 2540 if (smp_cpus % smp_threads) { 2541 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2542 smp_cpus, smp_threads); 2543 exit(1); 2544 } 2545 if (max_cpus % smp_threads) { 2546 error_report("max_cpus (%u) must be multiple of threads (%u)", 2547 max_cpus, smp_threads); 2548 exit(1); 2549 } 2550 } else { 2551 if (max_cpus != smp_cpus) { 2552 error_report("This machine version does not support CPU hotplug"); 2553 exit(1); 2554 } 2555 boot_cores_nr = possible_cpus->len; 2556 } 2557 2558 if (smc->pre_2_10_has_unused_icps) { 2559 int i; 2560 2561 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2562 /* Dummy entries get deregistered when real ICPState objects 2563 * are registered during CPU core hotplug. 2564 */ 2565 pre_2_10_vmstate_register_dummy_icp(i); 2566 } 2567 } 2568 2569 for (i = 0; i < possible_cpus->len; i++) { 2570 int core_id = i * smp_threads; 2571 2572 if (mc->has_hotpluggable_cpus) { 2573 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2574 spapr_vcpu_id(spapr, core_id)); 2575 } 2576 2577 if (i < boot_cores_nr) { 2578 Object *core = object_new(type); 2579 int nr_threads = smp_threads; 2580 2581 /* Handle the partially filled core for older machine types */ 2582 if ((i + 1) * smp_threads >= smp_cpus) { 2583 nr_threads = smp_cpus - i * smp_threads; 2584 } 2585 2586 object_property_set_int(core, "nr-threads", nr_threads, 2587 &error_fatal); 2588 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2589 &error_fatal); 2590 qdev_realize(DEVICE(core), NULL, &error_fatal); 2591 2592 object_unref(core); 2593 } 2594 } 2595 } 2596 2597 static PCIHostState *spapr_create_default_phb(void) 2598 { 2599 DeviceState *dev; 2600 2601 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2602 qdev_prop_set_uint32(dev, "index", 0); 2603 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2604 2605 return PCI_HOST_BRIDGE(dev); 2606 } 2607 2608 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2609 { 2610 MachineState *machine = MACHINE(spapr); 2611 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2612 hwaddr rma_size = machine->ram_size; 2613 hwaddr node0_size = spapr_node0_size(machine); 2614 2615 /* RMA has to fit in the first NUMA node */ 2616 rma_size = MIN(rma_size, node0_size); 2617 2618 /* 2619 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2620 * never exceed that 2621 */ 2622 rma_size = MIN(rma_size, 1 * TiB); 2623 2624 /* 2625 * Clamp the RMA size based on machine type. This is for 2626 * migration compatibility with older qemu versions, which limited 2627 * the RMA size for complicated and mostly bad reasons. 2628 */ 2629 if (smc->rma_limit) { 2630 rma_size = MIN(rma_size, smc->rma_limit); 2631 } 2632 2633 if (rma_size < MIN_RMA_SLOF) { 2634 error_setg(errp, 2635 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2636 "ldMiB guest RMA (Real Mode Area memory)", 2637 MIN_RMA_SLOF / MiB); 2638 return 0; 2639 } 2640 2641 return rma_size; 2642 } 2643 2644 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2645 { 2646 MachineState *machine = MACHINE(spapr); 2647 int i; 2648 2649 for (i = 0; i < machine->ram_slots; i++) { 2650 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2651 } 2652 } 2653 2654 /* pSeries LPAR / sPAPR hardware init */ 2655 static void spapr_machine_init(MachineState *machine) 2656 { 2657 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2658 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2659 MachineClass *mc = MACHINE_GET_CLASS(machine); 2660 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 2661 const char *kernel_filename = machine->kernel_filename; 2662 const char *initrd_filename = machine->initrd_filename; 2663 PCIHostState *phb; 2664 int i; 2665 MemoryRegion *sysmem = get_system_memory(); 2666 long load_limit, fw_size; 2667 char *filename; 2668 Error *resize_hpt_err = NULL; 2669 2670 /* 2671 * if Secure VM (PEF) support is configured, then initialize it 2672 */ 2673 pef_kvm_init(machine->cgs, &error_fatal); 2674 2675 msi_nonbroken = true; 2676 2677 QLIST_INIT(&spapr->phbs); 2678 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2679 2680 /* Determine capabilities to run with */ 2681 spapr_caps_init(spapr); 2682 2683 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2684 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2685 /* 2686 * If the user explicitly requested a mode we should either 2687 * supply it, or fail completely (which we do below). But if 2688 * it's not set explicitly, we reset our mode to something 2689 * that works 2690 */ 2691 if (resize_hpt_err) { 2692 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2693 error_free(resize_hpt_err); 2694 resize_hpt_err = NULL; 2695 } else { 2696 spapr->resize_hpt = smc->resize_hpt_default; 2697 } 2698 } 2699 2700 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2701 2702 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2703 /* 2704 * User requested HPT resize, but this host can't supply it. Bail out 2705 */ 2706 error_report_err(resize_hpt_err); 2707 exit(1); 2708 } 2709 error_free(resize_hpt_err); 2710 2711 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2712 2713 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2714 load_limit = MIN(spapr->rma_size, FDT_MAX_ADDR) - FW_OVERHEAD; 2715 2716 /* 2717 * VSMT must be set in order to be able to compute VCPU ids, ie to 2718 * call spapr_max_server_number() or spapr_vcpu_id(). 2719 */ 2720 spapr_set_vsmt_mode(spapr, &error_fatal); 2721 2722 /* Set up Interrupt Controller before we create the VCPUs */ 2723 spapr_irq_init(spapr, &error_fatal); 2724 2725 /* Set up containers for ibm,client-architecture-support negotiated options 2726 */ 2727 spapr->ov5 = spapr_ovec_new(); 2728 spapr->ov5_cas = spapr_ovec_new(); 2729 2730 if (smc->dr_lmb_enabled) { 2731 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2732 spapr_validate_node_memory(machine, &error_fatal); 2733 } 2734 2735 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2736 2737 /* advertise support for dedicated HP event source to guests */ 2738 if (spapr->use_hotplug_event_source) { 2739 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2740 } 2741 2742 /* advertise support for HPT resizing */ 2743 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2744 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2745 } 2746 2747 /* advertise support for ibm,dyamic-memory-v2 */ 2748 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2749 2750 /* advertise XIVE on POWER9 machines */ 2751 if (spapr->irq->xive) { 2752 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2753 } 2754 2755 /* init CPUs */ 2756 spapr_init_cpus(spapr); 2757 2758 /* 2759 * check we don't have a memory-less/cpu-less NUMA node 2760 * Firmware relies on the existing memory/cpu topology to provide the 2761 * NUMA topology to the kernel. 2762 * And the linux kernel needs to know the NUMA topology at start 2763 * to be able to hotplug CPUs later. 2764 */ 2765 if (machine->numa_state->num_nodes) { 2766 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2767 /* check for memory-less node */ 2768 if (machine->numa_state->nodes[i].node_mem == 0) { 2769 CPUState *cs; 2770 int found = 0; 2771 /* check for cpu-less node */ 2772 CPU_FOREACH(cs) { 2773 PowerPCCPU *cpu = POWERPC_CPU(cs); 2774 if (cpu->node_id == i) { 2775 found = 1; 2776 break; 2777 } 2778 } 2779 /* memory-less and cpu-less node */ 2780 if (!found) { 2781 error_report( 2782 "Memory-less/cpu-less nodes are not supported (node %d)", 2783 i); 2784 exit(1); 2785 } 2786 } 2787 } 2788 2789 } 2790 2791 spapr->gpu_numa_id = spapr_numa_initial_nvgpu_numa_id(machine); 2792 2793 /* Init numa_assoc_array */ 2794 spapr_numa_associativity_init(spapr, machine); 2795 2796 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2797 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2798 spapr->max_compat_pvr)) { 2799 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2800 /* KVM and TCG always allow GTSE with radix... */ 2801 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2802 } 2803 /* ... but not with hash (currently). */ 2804 2805 if (kvm_enabled()) { 2806 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2807 kvmppc_enable_logical_ci_hcalls(); 2808 kvmppc_enable_set_mode_hcall(); 2809 2810 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2811 kvmppc_enable_clear_ref_mod_hcalls(); 2812 2813 /* Enable H_PAGE_INIT */ 2814 kvmppc_enable_h_page_init(); 2815 } 2816 2817 /* map RAM */ 2818 memory_region_add_subregion(sysmem, 0, machine->ram); 2819 2820 /* always allocate the device memory information */ 2821 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2822 2823 /* initialize hotplug memory address space */ 2824 if (machine->ram_size < machine->maxram_size) { 2825 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2826 /* 2827 * Limit the number of hotpluggable memory slots to half the number 2828 * slots that KVM supports, leaving the other half for PCI and other 2829 * devices. However ensure that number of slots doesn't drop below 32. 2830 */ 2831 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2832 SPAPR_MAX_RAM_SLOTS; 2833 2834 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2835 max_memslots = SPAPR_MAX_RAM_SLOTS; 2836 } 2837 if (machine->ram_slots > max_memslots) { 2838 error_report("Specified number of memory slots %" 2839 PRIu64" exceeds max supported %d", 2840 machine->ram_slots, max_memslots); 2841 exit(1); 2842 } 2843 2844 machine->device_memory->base = ROUND_UP(machine->ram_size, 2845 SPAPR_DEVICE_MEM_ALIGN); 2846 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2847 "device-memory", device_mem_size); 2848 memory_region_add_subregion(sysmem, machine->device_memory->base, 2849 &machine->device_memory->mr); 2850 } 2851 2852 if (smc->dr_lmb_enabled) { 2853 spapr_create_lmb_dr_connectors(spapr); 2854 } 2855 2856 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2857 /* Create the error string for live migration blocker */ 2858 error_setg(&spapr->fwnmi_migration_blocker, 2859 "A machine check is being handled during migration. The handler" 2860 "may run and log hardware error on the destination"); 2861 } 2862 2863 if (mc->nvdimm_supported) { 2864 spapr_create_nvdimm_dr_connectors(spapr); 2865 } 2866 2867 /* Set up RTAS event infrastructure */ 2868 spapr_events_init(spapr); 2869 2870 /* Set up the RTC RTAS interfaces */ 2871 spapr_rtc_create(spapr); 2872 2873 /* Set up VIO bus */ 2874 spapr->vio_bus = spapr_vio_bus_init(); 2875 2876 for (i = 0; serial_hd(i); i++) { 2877 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2878 } 2879 2880 /* We always have at least the nvram device on VIO */ 2881 spapr_create_nvram(spapr); 2882 2883 /* 2884 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2885 * connectors (described in root DT node's "ibm,drc-types" property) 2886 * are pre-initialized here. additional child connectors (such as 2887 * connectors for a PHBs PCI slots) are added as needed during their 2888 * parent's realization. 2889 */ 2890 if (smc->dr_phb_enabled) { 2891 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2892 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2893 } 2894 } 2895 2896 /* Set up PCI */ 2897 spapr_pci_rtas_init(); 2898 2899 phb = spapr_create_default_phb(); 2900 2901 for (i = 0; i < nb_nics; i++) { 2902 NICInfo *nd = &nd_table[i]; 2903 2904 if (!nd->model) { 2905 nd->model = g_strdup("spapr-vlan"); 2906 } 2907 2908 if (g_str_equal(nd->model, "spapr-vlan") || 2909 g_str_equal(nd->model, "ibmveth")) { 2910 spapr_vlan_create(spapr->vio_bus, nd); 2911 } else { 2912 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2913 } 2914 } 2915 2916 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2917 spapr_vscsi_create(spapr->vio_bus); 2918 } 2919 2920 /* Graphics */ 2921 if (spapr_vga_init(phb->bus, &error_fatal)) { 2922 spapr->has_graphics = true; 2923 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2924 } 2925 2926 if (machine->usb) { 2927 if (smc->use_ohci_by_default) { 2928 pci_create_simple(phb->bus, -1, "pci-ohci"); 2929 } else { 2930 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2931 } 2932 2933 if (spapr->has_graphics) { 2934 USBBus *usb_bus = usb_bus_find(-1); 2935 2936 usb_create_simple(usb_bus, "usb-kbd"); 2937 usb_create_simple(usb_bus, "usb-mouse"); 2938 } 2939 } 2940 2941 if (kernel_filename) { 2942 spapr->kernel_size = load_elf(kernel_filename, NULL, 2943 translate_kernel_address, spapr, 2944 NULL, NULL, NULL, NULL, 1, 2945 PPC_ELF_MACHINE, 0, 0); 2946 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2947 spapr->kernel_size = load_elf(kernel_filename, NULL, 2948 translate_kernel_address, spapr, 2949 NULL, NULL, NULL, NULL, 0, 2950 PPC_ELF_MACHINE, 0, 0); 2951 spapr->kernel_le = spapr->kernel_size > 0; 2952 } 2953 if (spapr->kernel_size < 0) { 2954 error_report("error loading %s: %s", kernel_filename, 2955 load_elf_strerror(spapr->kernel_size)); 2956 exit(1); 2957 } 2958 2959 /* load initrd */ 2960 if (initrd_filename) { 2961 /* Try to locate the initrd in the gap between the kernel 2962 * and the firmware. Add a bit of space just in case 2963 */ 2964 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2965 + 0x1ffff) & ~0xffff; 2966 spapr->initrd_size = load_image_targphys(initrd_filename, 2967 spapr->initrd_base, 2968 load_limit 2969 - spapr->initrd_base); 2970 if (spapr->initrd_size < 0) { 2971 error_report("could not load initial ram disk '%s'", 2972 initrd_filename); 2973 exit(1); 2974 } 2975 } 2976 } 2977 2978 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2979 if (!filename) { 2980 error_report("Could not find LPAR firmware '%s'", bios_name); 2981 exit(1); 2982 } 2983 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2984 if (fw_size <= 0) { 2985 error_report("Could not load LPAR firmware '%s'", filename); 2986 exit(1); 2987 } 2988 g_free(filename); 2989 2990 /* FIXME: Should register things through the MachineState's qdev 2991 * interface, this is a legacy from the sPAPREnvironment structure 2992 * which predated MachineState but had a similar function */ 2993 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2994 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 2995 &savevm_htab_handlers, spapr); 2996 2997 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 2998 2999 qemu_register_boot_set(spapr_boot_set, spapr); 3000 3001 /* 3002 * Nothing needs to be done to resume a suspended guest because 3003 * suspending does not change the machine state, so no need for 3004 * a ->wakeup method. 3005 */ 3006 qemu_register_wakeup_support(); 3007 3008 if (kvm_enabled()) { 3009 /* to stop and start vmclock */ 3010 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3011 &spapr->tb); 3012 3013 kvmppc_spapr_enable_inkernel_multitce(); 3014 } 3015 3016 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3017 } 3018 3019 #define DEFAULT_KVM_TYPE "auto" 3020 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3021 { 3022 /* 3023 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3024 * accomodate the 'HV' and 'PV' formats that exists in the 3025 * wild. The 'auto' mode is being introduced already as 3026 * lower-case, thus we don't need to bother checking for 3027 * "AUTO". 3028 */ 3029 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3030 return 0; 3031 } 3032 3033 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3034 return 1; 3035 } 3036 3037 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3038 return 2; 3039 } 3040 3041 error_report("Unknown kvm-type specified '%s'", vm_type); 3042 exit(1); 3043 } 3044 3045 /* 3046 * Implementation of an interface to adjust firmware path 3047 * for the bootindex property handling. 3048 */ 3049 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3050 DeviceState *dev) 3051 { 3052 #define CAST(type, obj, name) \ 3053 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3054 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3055 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3056 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3057 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3058 3059 if (d) { 3060 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3061 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3062 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3063 3064 if (spapr) { 3065 /* 3066 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3067 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3068 * 0x8000 | (target << 8) | (bus << 5) | lun 3069 * (see the "Logical unit addressing format" table in SAM5) 3070 */ 3071 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3072 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3073 (uint64_t)id << 48); 3074 } else if (virtio) { 3075 /* 3076 * We use SRP luns of the form 01000000 | (target << 8) | lun 3077 * in the top 32 bits of the 64-bit LUN 3078 * Note: the quote above is from SLOF and it is wrong, 3079 * the actual binding is: 3080 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3081 */ 3082 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3083 if (d->lun >= 256) { 3084 /* Use the LUN "flat space addressing method" */ 3085 id |= 0x4000; 3086 } 3087 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3088 (uint64_t)id << 32); 3089 } else if (usb) { 3090 /* 3091 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3092 * in the top 32 bits of the 64-bit LUN 3093 */ 3094 unsigned usb_port = atoi(usb->port->path); 3095 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3096 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3097 (uint64_t)id << 32); 3098 } 3099 } 3100 3101 /* 3102 * SLOF probes the USB devices, and if it recognizes that the device is a 3103 * storage device, it changes its name to "storage" instead of "usb-host", 3104 * and additionally adds a child node for the SCSI LUN, so the correct 3105 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3106 */ 3107 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3108 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3109 if (usb_host_dev_is_scsi_storage(usbdev)) { 3110 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3111 } 3112 } 3113 3114 if (phb) { 3115 /* Replace "pci" with "pci@800000020000000" */ 3116 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3117 } 3118 3119 if (vsc) { 3120 /* Same logic as virtio above */ 3121 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3122 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3123 } 3124 3125 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3126 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3127 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3128 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3129 } 3130 3131 if (pcidev) { 3132 return spapr_pci_fw_dev_name(pcidev); 3133 } 3134 3135 return NULL; 3136 } 3137 3138 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3139 { 3140 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3141 3142 return g_strdup(spapr->kvm_type); 3143 } 3144 3145 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3146 { 3147 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3148 3149 g_free(spapr->kvm_type); 3150 spapr->kvm_type = g_strdup(value); 3151 } 3152 3153 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3154 { 3155 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3156 3157 return spapr->use_hotplug_event_source; 3158 } 3159 3160 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3161 Error **errp) 3162 { 3163 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3164 3165 spapr->use_hotplug_event_source = value; 3166 } 3167 3168 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3169 { 3170 return true; 3171 } 3172 3173 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3174 { 3175 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3176 3177 switch (spapr->resize_hpt) { 3178 case SPAPR_RESIZE_HPT_DEFAULT: 3179 return g_strdup("default"); 3180 case SPAPR_RESIZE_HPT_DISABLED: 3181 return g_strdup("disabled"); 3182 case SPAPR_RESIZE_HPT_ENABLED: 3183 return g_strdup("enabled"); 3184 case SPAPR_RESIZE_HPT_REQUIRED: 3185 return g_strdup("required"); 3186 } 3187 g_assert_not_reached(); 3188 } 3189 3190 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3191 { 3192 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3193 3194 if (strcmp(value, "default") == 0) { 3195 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3196 } else if (strcmp(value, "disabled") == 0) { 3197 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3198 } else if (strcmp(value, "enabled") == 0) { 3199 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3200 } else if (strcmp(value, "required") == 0) { 3201 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3202 } else { 3203 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3204 } 3205 } 3206 3207 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3208 { 3209 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3210 3211 if (spapr->irq == &spapr_irq_xics_legacy) { 3212 return g_strdup("legacy"); 3213 } else if (spapr->irq == &spapr_irq_xics) { 3214 return g_strdup("xics"); 3215 } else if (spapr->irq == &spapr_irq_xive) { 3216 return g_strdup("xive"); 3217 } else if (spapr->irq == &spapr_irq_dual) { 3218 return g_strdup("dual"); 3219 } 3220 g_assert_not_reached(); 3221 } 3222 3223 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3224 { 3225 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3226 3227 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3228 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3229 return; 3230 } 3231 3232 /* The legacy IRQ backend can not be set */ 3233 if (strcmp(value, "xics") == 0) { 3234 spapr->irq = &spapr_irq_xics; 3235 } else if (strcmp(value, "xive") == 0) { 3236 spapr->irq = &spapr_irq_xive; 3237 } else if (strcmp(value, "dual") == 0) { 3238 spapr->irq = &spapr_irq_dual; 3239 } else { 3240 error_setg(errp, "Bad value for \"ic-mode\" property"); 3241 } 3242 } 3243 3244 static char *spapr_get_host_model(Object *obj, Error **errp) 3245 { 3246 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3247 3248 return g_strdup(spapr->host_model); 3249 } 3250 3251 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3252 { 3253 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3254 3255 g_free(spapr->host_model); 3256 spapr->host_model = g_strdup(value); 3257 } 3258 3259 static char *spapr_get_host_serial(Object *obj, Error **errp) 3260 { 3261 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3262 3263 return g_strdup(spapr->host_serial); 3264 } 3265 3266 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3267 { 3268 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3269 3270 g_free(spapr->host_serial); 3271 spapr->host_serial = g_strdup(value); 3272 } 3273 3274 static void spapr_instance_init(Object *obj) 3275 { 3276 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3277 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3278 MachineState *ms = MACHINE(spapr); 3279 MachineClass *mc = MACHINE_GET_CLASS(ms); 3280 3281 /* 3282 * NVDIMM support went live in 5.1 without considering that, in 3283 * other archs, the user needs to enable NVDIMM support with the 3284 * 'nvdimm' machine option and the default behavior is NVDIMM 3285 * support disabled. It is too late to roll back to the standard 3286 * behavior without breaking 5.1 guests. 3287 */ 3288 if (mc->nvdimm_supported) { 3289 ms->nvdimms_state->is_enabled = true; 3290 } 3291 3292 spapr->htab_fd = -1; 3293 spapr->use_hotplug_event_source = true; 3294 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3295 object_property_add_str(obj, "kvm-type", 3296 spapr_get_kvm_type, spapr_set_kvm_type); 3297 object_property_set_description(obj, "kvm-type", 3298 "Specifies the KVM virtualization mode (auto," 3299 " hv, pr). Defaults to 'auto'. This mode will use" 3300 " any available KVM module loaded in the host," 3301 " where kvm_hv takes precedence if both kvm_hv and" 3302 " kvm_pr are loaded."); 3303 object_property_add_bool(obj, "modern-hotplug-events", 3304 spapr_get_modern_hotplug_events, 3305 spapr_set_modern_hotplug_events); 3306 object_property_set_description(obj, "modern-hotplug-events", 3307 "Use dedicated hotplug event mechanism in" 3308 " place of standard EPOW events when possible" 3309 " (required for memory hot-unplug support)"); 3310 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3311 "Maximum permitted CPU compatibility mode"); 3312 3313 object_property_add_str(obj, "resize-hpt", 3314 spapr_get_resize_hpt, spapr_set_resize_hpt); 3315 object_property_set_description(obj, "resize-hpt", 3316 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3317 object_property_add_uint32_ptr(obj, "vsmt", 3318 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3319 object_property_set_description(obj, "vsmt", 3320 "Virtual SMT: KVM behaves as if this were" 3321 " the host's SMT mode"); 3322 3323 object_property_add_bool(obj, "vfio-no-msix-emulation", 3324 spapr_get_msix_emulation, NULL); 3325 3326 object_property_add_uint64_ptr(obj, "kernel-addr", 3327 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3328 object_property_set_description(obj, "kernel-addr", 3329 stringify(KERNEL_LOAD_ADDR) 3330 " for -kernel is the default"); 3331 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3332 /* The machine class defines the default interrupt controller mode */ 3333 spapr->irq = smc->irq; 3334 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3335 spapr_set_ic_mode); 3336 object_property_set_description(obj, "ic-mode", 3337 "Specifies the interrupt controller mode (xics, xive, dual)"); 3338 3339 object_property_add_str(obj, "host-model", 3340 spapr_get_host_model, spapr_set_host_model); 3341 object_property_set_description(obj, "host-model", 3342 "Host model to advertise in guest device tree"); 3343 object_property_add_str(obj, "host-serial", 3344 spapr_get_host_serial, spapr_set_host_serial); 3345 object_property_set_description(obj, "host-serial", 3346 "Host serial number to advertise in guest device tree"); 3347 } 3348 3349 static void spapr_machine_finalizefn(Object *obj) 3350 { 3351 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3352 3353 g_free(spapr->kvm_type); 3354 } 3355 3356 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3357 { 3358 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3359 PowerPCCPU *cpu = POWERPC_CPU(cs); 3360 CPUPPCState *env = &cpu->env; 3361 3362 cpu_synchronize_state(cs); 3363 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3364 if (spapr->fwnmi_system_reset_addr != -1) { 3365 uint64_t rtas_addr, addr; 3366 3367 /* get rtas addr from fdt */ 3368 rtas_addr = spapr_get_rtas_addr(); 3369 if (!rtas_addr) { 3370 qemu_system_guest_panicked(NULL); 3371 return; 3372 } 3373 3374 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3375 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3376 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3377 env->gpr[3] = addr; 3378 } 3379 ppc_cpu_do_system_reset(cs); 3380 if (spapr->fwnmi_system_reset_addr != -1) { 3381 env->nip = spapr->fwnmi_system_reset_addr; 3382 } 3383 } 3384 3385 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3386 { 3387 CPUState *cs; 3388 3389 CPU_FOREACH(cs) { 3390 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3391 } 3392 } 3393 3394 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3395 void *fdt, int *fdt_start_offset, Error **errp) 3396 { 3397 uint64_t addr; 3398 uint32_t node; 3399 3400 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3401 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3402 &error_abort); 3403 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3404 SPAPR_MEMORY_BLOCK_SIZE); 3405 return 0; 3406 } 3407 3408 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3409 bool dedicated_hp_event_source) 3410 { 3411 SpaprDrc *drc; 3412 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3413 int i; 3414 uint64_t addr = addr_start; 3415 bool hotplugged = spapr_drc_hotplugged(dev); 3416 3417 for (i = 0; i < nr_lmbs; i++) { 3418 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3419 addr / SPAPR_MEMORY_BLOCK_SIZE); 3420 g_assert(drc); 3421 3422 /* 3423 * memory_device_get_free_addr() provided a range of free addresses 3424 * that doesn't overlap with any existing mapping at pre-plug. The 3425 * corresponding LMB DRCs are thus assumed to be all attachable. 3426 */ 3427 spapr_drc_attach(drc, dev); 3428 if (!hotplugged) { 3429 spapr_drc_reset(drc); 3430 } 3431 addr += SPAPR_MEMORY_BLOCK_SIZE; 3432 } 3433 /* send hotplug notification to the 3434 * guest only in case of hotplugged memory 3435 */ 3436 if (hotplugged) { 3437 if (dedicated_hp_event_source) { 3438 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3439 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3440 g_assert(drc); 3441 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3442 nr_lmbs, 3443 spapr_drc_index(drc)); 3444 } else { 3445 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3446 nr_lmbs); 3447 } 3448 } 3449 } 3450 3451 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3452 { 3453 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3454 PCDIMMDevice *dimm = PC_DIMM(dev); 3455 uint64_t size, addr; 3456 int64_t slot; 3457 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3458 3459 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3460 3461 pc_dimm_plug(dimm, MACHINE(ms)); 3462 3463 if (!is_nvdimm) { 3464 addr = object_property_get_uint(OBJECT(dimm), 3465 PC_DIMM_ADDR_PROP, &error_abort); 3466 spapr_add_lmbs(dev, addr, size, 3467 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3468 } else { 3469 slot = object_property_get_int(OBJECT(dimm), 3470 PC_DIMM_SLOT_PROP, &error_abort); 3471 /* We should have valid slot number at this point */ 3472 g_assert(slot >= 0); 3473 spapr_add_nvdimm(dev, slot); 3474 } 3475 } 3476 3477 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3478 Error **errp) 3479 { 3480 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3481 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3482 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3483 PCDIMMDevice *dimm = PC_DIMM(dev); 3484 Error *local_err = NULL; 3485 uint64_t size; 3486 Object *memdev; 3487 hwaddr pagesize; 3488 3489 if (!smc->dr_lmb_enabled) { 3490 error_setg(errp, "Memory hotplug not supported for this machine"); 3491 return; 3492 } 3493 3494 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3495 if (local_err) { 3496 error_propagate(errp, local_err); 3497 return; 3498 } 3499 3500 if (is_nvdimm) { 3501 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3502 return; 3503 } 3504 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3505 error_setg(errp, "Hotplugged memory size must be a multiple of " 3506 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3507 return; 3508 } 3509 3510 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3511 &error_abort); 3512 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3513 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3514 return; 3515 } 3516 3517 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3518 } 3519 3520 struct SpaprDimmState { 3521 PCDIMMDevice *dimm; 3522 uint32_t nr_lmbs; 3523 QTAILQ_ENTRY(SpaprDimmState) next; 3524 }; 3525 3526 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3527 PCDIMMDevice *dimm) 3528 { 3529 SpaprDimmState *dimm_state = NULL; 3530 3531 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3532 if (dimm_state->dimm == dimm) { 3533 break; 3534 } 3535 } 3536 return dimm_state; 3537 } 3538 3539 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3540 uint32_t nr_lmbs, 3541 PCDIMMDevice *dimm) 3542 { 3543 SpaprDimmState *ds = NULL; 3544 3545 /* 3546 * If this request is for a DIMM whose removal had failed earlier 3547 * (due to guest's refusal to remove the LMBs), we would have this 3548 * dimm already in the pending_dimm_unplugs list. In that 3549 * case don't add again. 3550 */ 3551 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3552 if (!ds) { 3553 ds = g_malloc0(sizeof(SpaprDimmState)); 3554 ds->nr_lmbs = nr_lmbs; 3555 ds->dimm = dimm; 3556 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3557 } 3558 return ds; 3559 } 3560 3561 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3562 SpaprDimmState *dimm_state) 3563 { 3564 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3565 g_free(dimm_state); 3566 } 3567 3568 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3569 PCDIMMDevice *dimm) 3570 { 3571 SpaprDrc *drc; 3572 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3573 &error_abort); 3574 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3575 uint32_t avail_lmbs = 0; 3576 uint64_t addr_start, addr; 3577 int i; 3578 3579 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3580 &error_abort); 3581 3582 addr = addr_start; 3583 for (i = 0; i < nr_lmbs; i++) { 3584 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3585 addr / SPAPR_MEMORY_BLOCK_SIZE); 3586 g_assert(drc); 3587 if (drc->dev) { 3588 avail_lmbs++; 3589 } 3590 addr += SPAPR_MEMORY_BLOCK_SIZE; 3591 } 3592 3593 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3594 } 3595 3596 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev) 3597 { 3598 SpaprDimmState *ds; 3599 PCDIMMDevice *dimm; 3600 SpaprDrc *drc; 3601 uint32_t nr_lmbs; 3602 uint64_t size, addr_start, addr; 3603 g_autofree char *qapi_error = NULL; 3604 int i; 3605 3606 if (!dev) { 3607 return; 3608 } 3609 3610 dimm = PC_DIMM(dev); 3611 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3612 3613 /* 3614 * 'ds == NULL' would mean that the DIMM doesn't have a pending 3615 * unplug state, but one of its DRC is marked as unplug_requested. 3616 * This is bad and weird enough to g_assert() out. 3617 */ 3618 g_assert(ds); 3619 3620 spapr_pending_dimm_unplugs_remove(spapr, ds); 3621 3622 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3623 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3624 3625 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3626 &error_abort); 3627 3628 addr = addr_start; 3629 for (i = 0; i < nr_lmbs; i++) { 3630 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3631 addr / SPAPR_MEMORY_BLOCK_SIZE); 3632 g_assert(drc); 3633 3634 drc->unplug_requested = false; 3635 addr += SPAPR_MEMORY_BLOCK_SIZE; 3636 } 3637 3638 /* 3639 * Tell QAPI that something happened and the memory 3640 * hotunplug wasn't successful. 3641 */ 3642 qapi_error = g_strdup_printf("Memory hotunplug rejected by the guest " 3643 "for device %s", dev->id); 3644 qapi_event_send_mem_unplug_error(dev->id, qapi_error); 3645 } 3646 3647 /* Callback to be called during DRC release. */ 3648 void spapr_lmb_release(DeviceState *dev) 3649 { 3650 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3651 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3652 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3653 3654 /* This information will get lost if a migration occurs 3655 * during the unplug process. In this case recover it. */ 3656 if (ds == NULL) { 3657 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3658 g_assert(ds); 3659 /* The DRC being examined by the caller at least must be counted */ 3660 g_assert(ds->nr_lmbs); 3661 } 3662 3663 if (--ds->nr_lmbs) { 3664 return; 3665 } 3666 3667 /* 3668 * Now that all the LMBs have been removed by the guest, call the 3669 * unplug handler chain. This can never fail. 3670 */ 3671 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3672 object_unparent(OBJECT(dev)); 3673 } 3674 3675 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3676 { 3677 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3678 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3679 3680 /* We really shouldn't get this far without anything to unplug */ 3681 g_assert(ds); 3682 3683 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3684 qdev_unrealize(dev); 3685 spapr_pending_dimm_unplugs_remove(spapr, ds); 3686 } 3687 3688 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3689 DeviceState *dev, Error **errp) 3690 { 3691 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3692 PCDIMMDevice *dimm = PC_DIMM(dev); 3693 uint32_t nr_lmbs; 3694 uint64_t size, addr_start, addr; 3695 int i; 3696 SpaprDrc *drc; 3697 3698 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3699 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3700 return; 3701 } 3702 3703 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3704 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3705 3706 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3707 &error_abort); 3708 3709 /* 3710 * An existing pending dimm state for this DIMM means that there is an 3711 * unplug operation in progress, waiting for the spapr_lmb_release 3712 * callback to complete the job (BQL can't cover that far). In this case, 3713 * bail out to avoid detaching DRCs that were already released. 3714 */ 3715 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3716 error_setg(errp, "Memory unplug already in progress for device %s", 3717 dev->id); 3718 return; 3719 } 3720 3721 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3722 3723 addr = addr_start; 3724 for (i = 0; i < nr_lmbs; i++) { 3725 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3726 addr / SPAPR_MEMORY_BLOCK_SIZE); 3727 g_assert(drc); 3728 3729 spapr_drc_unplug_request(drc); 3730 addr += SPAPR_MEMORY_BLOCK_SIZE; 3731 } 3732 3733 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3734 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3735 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3736 nr_lmbs, spapr_drc_index(drc)); 3737 } 3738 3739 /* Callback to be called during DRC release. */ 3740 void spapr_core_release(DeviceState *dev) 3741 { 3742 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3743 3744 /* Call the unplug handler chain. This can never fail. */ 3745 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3746 object_unparent(OBJECT(dev)); 3747 } 3748 3749 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3750 { 3751 MachineState *ms = MACHINE(hotplug_dev); 3752 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3753 CPUCore *cc = CPU_CORE(dev); 3754 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3755 3756 if (smc->pre_2_10_has_unused_icps) { 3757 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3758 int i; 3759 3760 for (i = 0; i < cc->nr_threads; i++) { 3761 CPUState *cs = CPU(sc->threads[i]); 3762 3763 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3764 } 3765 } 3766 3767 assert(core_slot); 3768 core_slot->cpu = NULL; 3769 qdev_unrealize(dev); 3770 } 3771 3772 static 3773 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3774 Error **errp) 3775 { 3776 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3777 int index; 3778 SpaprDrc *drc; 3779 CPUCore *cc = CPU_CORE(dev); 3780 3781 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3782 error_setg(errp, "Unable to find CPU core with core-id: %d", 3783 cc->core_id); 3784 return; 3785 } 3786 if (index == 0) { 3787 error_setg(errp, "Boot CPU core may not be unplugged"); 3788 return; 3789 } 3790 3791 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3792 spapr_vcpu_id(spapr, cc->core_id)); 3793 g_assert(drc); 3794 3795 if (!spapr_drc_unplug_requested(drc)) { 3796 spapr_drc_unplug_request(drc); 3797 } 3798 3799 /* 3800 * spapr_hotplug_req_remove_by_index is left unguarded, out of the 3801 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ 3802 * pulses removing the same CPU. Otherwise, in an failed hotunplug 3803 * attempt (e.g. the kernel will refuse to remove the last online 3804 * CPU), we will never attempt it again because unplug_requested 3805 * will still be 'true' in that case. 3806 */ 3807 spapr_hotplug_req_remove_by_index(drc); 3808 } 3809 3810 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3811 void *fdt, int *fdt_start_offset, Error **errp) 3812 { 3813 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3814 CPUState *cs = CPU(core->threads[0]); 3815 PowerPCCPU *cpu = POWERPC_CPU(cs); 3816 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3817 int id = spapr_get_vcpu_id(cpu); 3818 g_autofree char *nodename = NULL; 3819 int offset; 3820 3821 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3822 offset = fdt_add_subnode(fdt, 0, nodename); 3823 3824 spapr_dt_cpu(cs, fdt, offset, spapr); 3825 3826 /* 3827 * spapr_dt_cpu() does not fill the 'name' property in the 3828 * CPU node. The function is called during boot process, before 3829 * and after CAS, and overwriting the 'name' property written 3830 * by SLOF is not allowed. 3831 * 3832 * Write it manually after spapr_dt_cpu(). This makes the hotplug 3833 * CPUs more compatible with the coldplugged ones, which have 3834 * the 'name' property. Linux Kernel also relies on this 3835 * property to identify CPU nodes. 3836 */ 3837 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 3838 3839 *fdt_start_offset = offset; 3840 return 0; 3841 } 3842 3843 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3844 { 3845 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3846 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3847 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3848 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3849 CPUCore *cc = CPU_CORE(dev); 3850 CPUState *cs; 3851 SpaprDrc *drc; 3852 CPUArchId *core_slot; 3853 int index; 3854 bool hotplugged = spapr_drc_hotplugged(dev); 3855 int i; 3856 3857 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3858 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 3859 3860 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3861 spapr_vcpu_id(spapr, cc->core_id)); 3862 3863 g_assert(drc || !mc->has_hotpluggable_cpus); 3864 3865 if (drc) { 3866 /* 3867 * spapr_core_pre_plug() already buys us this is a brand new 3868 * core being plugged into a free slot. Nothing should already 3869 * be attached to the corresponding DRC. 3870 */ 3871 spapr_drc_attach(drc, dev); 3872 3873 if (hotplugged) { 3874 /* 3875 * Send hotplug notification interrupt to the guest only 3876 * in case of hotplugged CPUs. 3877 */ 3878 spapr_hotplug_req_add_by_index(drc); 3879 } else { 3880 spapr_drc_reset(drc); 3881 } 3882 } 3883 3884 core_slot->cpu = OBJECT(dev); 3885 3886 /* 3887 * Set compatibility mode to match the boot CPU, which was either set 3888 * by the machine reset code or by CAS. This really shouldn't fail at 3889 * this point. 3890 */ 3891 if (hotplugged) { 3892 for (i = 0; i < cc->nr_threads; i++) { 3893 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3894 &error_abort); 3895 } 3896 } 3897 3898 if (smc->pre_2_10_has_unused_icps) { 3899 for (i = 0; i < cc->nr_threads; i++) { 3900 cs = CPU(core->threads[i]); 3901 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3902 } 3903 } 3904 } 3905 3906 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3907 Error **errp) 3908 { 3909 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3910 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3911 CPUCore *cc = CPU_CORE(dev); 3912 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3913 const char *type = object_get_typename(OBJECT(dev)); 3914 CPUArchId *core_slot; 3915 int index; 3916 unsigned int smp_threads = machine->smp.threads; 3917 3918 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3919 error_setg(errp, "CPU hotplug not supported for this machine"); 3920 return; 3921 } 3922 3923 if (strcmp(base_core_type, type)) { 3924 error_setg(errp, "CPU core type should be %s", base_core_type); 3925 return; 3926 } 3927 3928 if (cc->core_id % smp_threads) { 3929 error_setg(errp, "invalid core id %d", cc->core_id); 3930 return; 3931 } 3932 3933 /* 3934 * In general we should have homogeneous threads-per-core, but old 3935 * (pre hotplug support) machine types allow the last core to have 3936 * reduced threads as a compatibility hack for when we allowed 3937 * total vcpus not a multiple of threads-per-core. 3938 */ 3939 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3940 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 3941 smp_threads); 3942 return; 3943 } 3944 3945 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3946 if (!core_slot) { 3947 error_setg(errp, "core id %d out of range", cc->core_id); 3948 return; 3949 } 3950 3951 if (core_slot->cpu) { 3952 error_setg(errp, "core %d already populated", cc->core_id); 3953 return; 3954 } 3955 3956 numa_cpu_pre_plug(core_slot, dev, errp); 3957 } 3958 3959 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3960 void *fdt, int *fdt_start_offset, Error **errp) 3961 { 3962 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3963 int intc_phandle; 3964 3965 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3966 if (intc_phandle <= 0) { 3967 return -1; 3968 } 3969 3970 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3971 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3972 return -1; 3973 } 3974 3975 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3976 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3977 3978 return 0; 3979 } 3980 3981 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3982 Error **errp) 3983 { 3984 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3985 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3986 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3987 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3988 SpaprDrc *drc; 3989 3990 if (dev->hotplugged && !smc->dr_phb_enabled) { 3991 error_setg(errp, "PHB hotplug not supported for this machine"); 3992 return false; 3993 } 3994 3995 if (sphb->index == (uint32_t)-1) { 3996 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3997 return false; 3998 } 3999 4000 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4001 if (drc && drc->dev) { 4002 error_setg(errp, "PHB %d already attached", sphb->index); 4003 return false; 4004 } 4005 4006 /* 4007 * This will check that sphb->index doesn't exceed the maximum number of 4008 * PHBs for the current machine type. 4009 */ 4010 return 4011 smc->phb_placement(spapr, sphb->index, 4012 &sphb->buid, &sphb->io_win_addr, 4013 &sphb->mem_win_addr, &sphb->mem64_win_addr, 4014 windows_supported, sphb->dma_liobn, 4015 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 4016 errp); 4017 } 4018 4019 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4020 { 4021 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4022 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4023 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4024 SpaprDrc *drc; 4025 bool hotplugged = spapr_drc_hotplugged(dev); 4026 4027 if (!smc->dr_phb_enabled) { 4028 return; 4029 } 4030 4031 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4032 /* hotplug hooks should check it's enabled before getting this far */ 4033 assert(drc); 4034 4035 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 4036 spapr_drc_attach(drc, dev); 4037 4038 if (hotplugged) { 4039 spapr_hotplug_req_add_by_index(drc); 4040 } else { 4041 spapr_drc_reset(drc); 4042 } 4043 } 4044 4045 void spapr_phb_release(DeviceState *dev) 4046 { 4047 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4048 4049 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4050 object_unparent(OBJECT(dev)); 4051 } 4052 4053 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4054 { 4055 qdev_unrealize(dev); 4056 } 4057 4058 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4059 DeviceState *dev, Error **errp) 4060 { 4061 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4062 SpaprDrc *drc; 4063 4064 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4065 assert(drc); 4066 4067 if (!spapr_drc_unplug_requested(drc)) { 4068 spapr_drc_unplug_request(drc); 4069 spapr_hotplug_req_remove_by_index(drc); 4070 } else { 4071 error_setg(errp, 4072 "PCI Host Bridge unplug already in progress for device %s", 4073 dev->id); 4074 } 4075 } 4076 4077 static 4078 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4079 Error **errp) 4080 { 4081 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4082 4083 if (spapr->tpm_proxy != NULL) { 4084 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4085 return false; 4086 } 4087 4088 return true; 4089 } 4090 4091 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4092 { 4093 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4094 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4095 4096 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4097 g_assert(spapr->tpm_proxy == NULL); 4098 4099 spapr->tpm_proxy = tpm_proxy; 4100 } 4101 4102 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4103 { 4104 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4105 4106 qdev_unrealize(dev); 4107 object_unparent(OBJECT(dev)); 4108 spapr->tpm_proxy = NULL; 4109 } 4110 4111 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4112 DeviceState *dev, Error **errp) 4113 { 4114 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4115 spapr_memory_plug(hotplug_dev, dev); 4116 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4117 spapr_core_plug(hotplug_dev, dev); 4118 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4119 spapr_phb_plug(hotplug_dev, dev); 4120 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4121 spapr_tpm_proxy_plug(hotplug_dev, dev); 4122 } 4123 } 4124 4125 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4126 DeviceState *dev, Error **errp) 4127 { 4128 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4129 spapr_memory_unplug(hotplug_dev, dev); 4130 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4131 spapr_core_unplug(hotplug_dev, dev); 4132 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4133 spapr_phb_unplug(hotplug_dev, dev); 4134 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4135 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4136 } 4137 } 4138 4139 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4140 { 4141 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4142 /* 4143 * CAS will process all pending unplug requests. 4144 * 4145 * HACK: a guest could theoretically have cleared all bits in OV5, 4146 * but none of the guests we care for do. 4147 */ 4148 spapr_ovec_empty(spapr->ov5_cas); 4149 } 4150 4151 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4152 DeviceState *dev, Error **errp) 4153 { 4154 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4155 MachineClass *mc = MACHINE_GET_CLASS(sms); 4156 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4157 4158 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4159 if (spapr_memory_hot_unplug_supported(sms)) { 4160 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4161 } else { 4162 error_setg(errp, "Memory hot unplug not supported for this guest"); 4163 } 4164 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4165 if (!mc->has_hotpluggable_cpus) { 4166 error_setg(errp, "CPU hot unplug not supported on this machine"); 4167 return; 4168 } 4169 spapr_core_unplug_request(hotplug_dev, dev, errp); 4170 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4171 if (!smc->dr_phb_enabled) { 4172 error_setg(errp, "PHB hot unplug not supported on this machine"); 4173 return; 4174 } 4175 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4176 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4177 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4178 } 4179 } 4180 4181 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4182 DeviceState *dev, Error **errp) 4183 { 4184 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4185 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4186 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4187 spapr_core_pre_plug(hotplug_dev, dev, errp); 4188 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4189 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4190 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4191 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4192 } 4193 } 4194 4195 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4196 DeviceState *dev) 4197 { 4198 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4199 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4200 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4201 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4202 return HOTPLUG_HANDLER(machine); 4203 } 4204 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4205 PCIDevice *pcidev = PCI_DEVICE(dev); 4206 PCIBus *root = pci_device_root_bus(pcidev); 4207 SpaprPhbState *phb = 4208 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4209 TYPE_SPAPR_PCI_HOST_BRIDGE); 4210 4211 if (phb) { 4212 return HOTPLUG_HANDLER(phb); 4213 } 4214 } 4215 return NULL; 4216 } 4217 4218 static CpuInstanceProperties 4219 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4220 { 4221 CPUArchId *core_slot; 4222 MachineClass *mc = MACHINE_GET_CLASS(machine); 4223 4224 /* make sure possible_cpu are intialized */ 4225 mc->possible_cpu_arch_ids(machine); 4226 /* get CPU core slot containing thread that matches cpu_index */ 4227 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4228 assert(core_slot); 4229 return core_slot->props; 4230 } 4231 4232 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4233 { 4234 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4235 } 4236 4237 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4238 { 4239 int i; 4240 unsigned int smp_threads = machine->smp.threads; 4241 unsigned int smp_cpus = machine->smp.cpus; 4242 const char *core_type; 4243 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4244 MachineClass *mc = MACHINE_GET_CLASS(machine); 4245 4246 if (!mc->has_hotpluggable_cpus) { 4247 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4248 } 4249 if (machine->possible_cpus) { 4250 assert(machine->possible_cpus->len == spapr_max_cores); 4251 return machine->possible_cpus; 4252 } 4253 4254 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4255 if (!core_type) { 4256 error_report("Unable to find sPAPR CPU Core definition"); 4257 exit(1); 4258 } 4259 4260 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4261 sizeof(CPUArchId) * spapr_max_cores); 4262 machine->possible_cpus->len = spapr_max_cores; 4263 for (i = 0; i < machine->possible_cpus->len; i++) { 4264 int core_id = i * smp_threads; 4265 4266 machine->possible_cpus->cpus[i].type = core_type; 4267 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4268 machine->possible_cpus->cpus[i].arch_id = core_id; 4269 machine->possible_cpus->cpus[i].props.has_core_id = true; 4270 machine->possible_cpus->cpus[i].props.core_id = core_id; 4271 } 4272 return machine->possible_cpus; 4273 } 4274 4275 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4276 uint64_t *buid, hwaddr *pio, 4277 hwaddr *mmio32, hwaddr *mmio64, 4278 unsigned n_dma, uint32_t *liobns, 4279 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4280 { 4281 /* 4282 * New-style PHB window placement. 4283 * 4284 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4285 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4286 * windows. 4287 * 4288 * Some guest kernels can't work with MMIO windows above 1<<46 4289 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4290 * 4291 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4292 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4293 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4294 * 1TiB 64-bit MMIO windows for each PHB. 4295 */ 4296 const uint64_t base_buid = 0x800000020000000ULL; 4297 int i; 4298 4299 /* Sanity check natural alignments */ 4300 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4301 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4302 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4303 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4304 /* Sanity check bounds */ 4305 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4306 SPAPR_PCI_MEM32_WIN_SIZE); 4307 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4308 SPAPR_PCI_MEM64_WIN_SIZE); 4309 4310 if (index >= SPAPR_MAX_PHBS) { 4311 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4312 SPAPR_MAX_PHBS - 1); 4313 return false; 4314 } 4315 4316 *buid = base_buid + index; 4317 for (i = 0; i < n_dma; ++i) { 4318 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4319 } 4320 4321 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4322 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4323 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4324 4325 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4326 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4327 return true; 4328 } 4329 4330 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4331 { 4332 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4333 4334 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4335 } 4336 4337 static void spapr_ics_resend(XICSFabric *dev) 4338 { 4339 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4340 4341 ics_resend(spapr->ics); 4342 } 4343 4344 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4345 { 4346 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4347 4348 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4349 } 4350 4351 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4352 Monitor *mon) 4353 { 4354 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4355 4356 spapr_irq_print_info(spapr, mon); 4357 monitor_printf(mon, "irqchip: %s\n", 4358 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4359 } 4360 4361 /* 4362 * This is a XIVE only operation 4363 */ 4364 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4365 uint8_t nvt_blk, uint32_t nvt_idx, 4366 bool cam_ignore, uint8_t priority, 4367 uint32_t logic_serv, XiveTCTXMatch *match) 4368 { 4369 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4370 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4371 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4372 int count; 4373 4374 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4375 priority, logic_serv, match); 4376 if (count < 0) { 4377 return count; 4378 } 4379 4380 /* 4381 * When we implement the save and restore of the thread interrupt 4382 * contexts in the enter/exit CPU handlers of the machine and the 4383 * escalations in QEMU, we should be able to handle non dispatched 4384 * vCPUs. 4385 * 4386 * Until this is done, the sPAPR machine should find at least one 4387 * matching context always. 4388 */ 4389 if (count == 0) { 4390 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4391 nvt_blk, nvt_idx); 4392 } 4393 4394 return count; 4395 } 4396 4397 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4398 { 4399 return cpu->vcpu_id; 4400 } 4401 4402 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4403 { 4404 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4405 MachineState *ms = MACHINE(spapr); 4406 int vcpu_id; 4407 4408 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4409 4410 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4411 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4412 error_append_hint(errp, "Adjust the number of cpus to %d " 4413 "or try to raise the number of threads per core\n", 4414 vcpu_id * ms->smp.threads / spapr->vsmt); 4415 return false; 4416 } 4417 4418 cpu->vcpu_id = vcpu_id; 4419 return true; 4420 } 4421 4422 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4423 { 4424 CPUState *cs; 4425 4426 CPU_FOREACH(cs) { 4427 PowerPCCPU *cpu = POWERPC_CPU(cs); 4428 4429 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4430 return cpu; 4431 } 4432 } 4433 4434 return NULL; 4435 } 4436 4437 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4438 { 4439 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4440 4441 /* These are only called by TCG, KVM maintains dispatch state */ 4442 4443 spapr_cpu->prod = false; 4444 if (spapr_cpu->vpa_addr) { 4445 CPUState *cs = CPU(cpu); 4446 uint32_t dispatch; 4447 4448 dispatch = ldl_be_phys(cs->as, 4449 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4450 dispatch++; 4451 if ((dispatch & 1) != 0) { 4452 qemu_log_mask(LOG_GUEST_ERROR, 4453 "VPA: incorrect dispatch counter value for " 4454 "dispatched partition %u, correcting.\n", dispatch); 4455 dispatch++; 4456 } 4457 stl_be_phys(cs->as, 4458 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4459 } 4460 } 4461 4462 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4463 { 4464 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4465 4466 if (spapr_cpu->vpa_addr) { 4467 CPUState *cs = CPU(cpu); 4468 uint32_t dispatch; 4469 4470 dispatch = ldl_be_phys(cs->as, 4471 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4472 dispatch++; 4473 if ((dispatch & 1) != 1) { 4474 qemu_log_mask(LOG_GUEST_ERROR, 4475 "VPA: incorrect dispatch counter value for " 4476 "preempted partition %u, correcting.\n", dispatch); 4477 dispatch++; 4478 } 4479 stl_be_phys(cs->as, 4480 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4481 } 4482 } 4483 4484 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4485 { 4486 MachineClass *mc = MACHINE_CLASS(oc); 4487 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4488 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4489 NMIClass *nc = NMI_CLASS(oc); 4490 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4491 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4492 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4493 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4494 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4495 4496 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4497 mc->ignore_boot_device_suffixes = true; 4498 4499 /* 4500 * We set up the default / latest behaviour here. The class_init 4501 * functions for the specific versioned machine types can override 4502 * these details for backwards compatibility 4503 */ 4504 mc->init = spapr_machine_init; 4505 mc->reset = spapr_machine_reset; 4506 mc->block_default_type = IF_SCSI; 4507 4508 /* 4509 * Setting max_cpus to INT32_MAX. Both KVM and TCG max_cpus values 4510 * should be limited by the host capability instead of hardcoded. 4511 * max_cpus for KVM guests will be checked in kvm_init(), and TCG 4512 * guests are welcome to have as many CPUs as the host are capable 4513 * of emulate. 4514 */ 4515 mc->max_cpus = INT32_MAX; 4516 4517 mc->no_parallel = 1; 4518 mc->default_boot_order = ""; 4519 mc->default_ram_size = 512 * MiB; 4520 mc->default_ram_id = "ppc_spapr.ram"; 4521 mc->default_display = "std"; 4522 mc->kvm_type = spapr_kvm_type; 4523 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4524 mc->pci_allow_0_address = true; 4525 assert(!mc->get_hotplug_handler); 4526 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4527 hc->pre_plug = spapr_machine_device_pre_plug; 4528 hc->plug = spapr_machine_device_plug; 4529 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4530 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4531 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4532 hc->unplug_request = spapr_machine_device_unplug_request; 4533 hc->unplug = spapr_machine_device_unplug; 4534 4535 smc->dr_lmb_enabled = true; 4536 smc->update_dt_enabled = true; 4537 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4538 mc->has_hotpluggable_cpus = true; 4539 mc->nvdimm_supported = true; 4540 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4541 fwc->get_dev_path = spapr_get_fw_dev_path; 4542 nc->nmi_monitor_handler = spapr_nmi; 4543 smc->phb_placement = spapr_phb_placement; 4544 vhc->hypercall = emulate_spapr_hypercall; 4545 vhc->hpt_mask = spapr_hpt_mask; 4546 vhc->map_hptes = spapr_map_hptes; 4547 vhc->unmap_hptes = spapr_unmap_hptes; 4548 vhc->hpte_set_c = spapr_hpte_set_c; 4549 vhc->hpte_set_r = spapr_hpte_set_r; 4550 vhc->get_pate = spapr_get_pate; 4551 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4552 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4553 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4554 xic->ics_get = spapr_ics_get; 4555 xic->ics_resend = spapr_ics_resend; 4556 xic->icp_get = spapr_icp_get; 4557 ispc->print_info = spapr_pic_print_info; 4558 /* Force NUMA node memory size to be a multiple of 4559 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4560 * in which LMBs are represented and hot-added 4561 */ 4562 mc->numa_mem_align_shift = 28; 4563 mc->auto_enable_numa = true; 4564 4565 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4566 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4567 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4568 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4569 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4570 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4571 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4572 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4573 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4574 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4575 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4576 spapr_caps_add_properties(smc); 4577 smc->irq = &spapr_irq_dual; 4578 smc->dr_phb_enabled = true; 4579 smc->linux_pci_probe = true; 4580 smc->smp_threads_vsmt = true; 4581 smc->nr_xirqs = SPAPR_NR_XIRQS; 4582 xfc->match_nvt = spapr_match_nvt; 4583 } 4584 4585 static const TypeInfo spapr_machine_info = { 4586 .name = TYPE_SPAPR_MACHINE, 4587 .parent = TYPE_MACHINE, 4588 .abstract = true, 4589 .instance_size = sizeof(SpaprMachineState), 4590 .instance_init = spapr_instance_init, 4591 .instance_finalize = spapr_machine_finalizefn, 4592 .class_size = sizeof(SpaprMachineClass), 4593 .class_init = spapr_machine_class_init, 4594 .interfaces = (InterfaceInfo[]) { 4595 { TYPE_FW_PATH_PROVIDER }, 4596 { TYPE_NMI }, 4597 { TYPE_HOTPLUG_HANDLER }, 4598 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4599 { TYPE_XICS_FABRIC }, 4600 { TYPE_INTERRUPT_STATS_PROVIDER }, 4601 { TYPE_XIVE_FABRIC }, 4602 { } 4603 }, 4604 }; 4605 4606 static void spapr_machine_latest_class_options(MachineClass *mc) 4607 { 4608 mc->alias = "pseries"; 4609 mc->is_default = true; 4610 } 4611 4612 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4613 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4614 void *data) \ 4615 { \ 4616 MachineClass *mc = MACHINE_CLASS(oc); \ 4617 spapr_machine_##suffix##_class_options(mc); \ 4618 if (latest) { \ 4619 spapr_machine_latest_class_options(mc); \ 4620 } \ 4621 } \ 4622 static const TypeInfo spapr_machine_##suffix##_info = { \ 4623 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4624 .parent = TYPE_SPAPR_MACHINE, \ 4625 .class_init = spapr_machine_##suffix##_class_init, \ 4626 }; \ 4627 static void spapr_machine_register_##suffix(void) \ 4628 { \ 4629 type_register(&spapr_machine_##suffix##_info); \ 4630 } \ 4631 type_init(spapr_machine_register_##suffix) 4632 4633 /* 4634 * pseries-6.1 4635 */ 4636 static void spapr_machine_6_1_class_options(MachineClass *mc) 4637 { 4638 /* Defaults for the latest behaviour inherited from the base class */ 4639 } 4640 4641 DEFINE_SPAPR_MACHINE(6_1, "6.1", true); 4642 4643 /* 4644 * pseries-6.0 4645 */ 4646 static void spapr_machine_6_0_class_options(MachineClass *mc) 4647 { 4648 spapr_machine_6_1_class_options(mc); 4649 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 4650 } 4651 4652 DEFINE_SPAPR_MACHINE(6_0, "6.0", false); 4653 4654 /* 4655 * pseries-5.2 4656 */ 4657 static void spapr_machine_5_2_class_options(MachineClass *mc) 4658 { 4659 spapr_machine_6_0_class_options(mc); 4660 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4661 } 4662 4663 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4664 4665 /* 4666 * pseries-5.1 4667 */ 4668 static void spapr_machine_5_1_class_options(MachineClass *mc) 4669 { 4670 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4671 4672 spapr_machine_5_2_class_options(mc); 4673 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4674 smc->pre_5_2_numa_associativity = true; 4675 } 4676 4677 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4678 4679 /* 4680 * pseries-5.0 4681 */ 4682 static void spapr_machine_5_0_class_options(MachineClass *mc) 4683 { 4684 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4685 static GlobalProperty compat[] = { 4686 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4687 }; 4688 4689 spapr_machine_5_1_class_options(mc); 4690 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4691 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4692 mc->numa_mem_supported = true; 4693 smc->pre_5_1_assoc_refpoints = true; 4694 } 4695 4696 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4697 4698 /* 4699 * pseries-4.2 4700 */ 4701 static void spapr_machine_4_2_class_options(MachineClass *mc) 4702 { 4703 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4704 4705 spapr_machine_5_0_class_options(mc); 4706 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4707 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4708 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4709 smc->rma_limit = 16 * GiB; 4710 mc->nvdimm_supported = false; 4711 } 4712 4713 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4714 4715 /* 4716 * pseries-4.1 4717 */ 4718 static void spapr_machine_4_1_class_options(MachineClass *mc) 4719 { 4720 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4721 static GlobalProperty compat[] = { 4722 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4723 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4724 }; 4725 4726 spapr_machine_4_2_class_options(mc); 4727 smc->linux_pci_probe = false; 4728 smc->smp_threads_vsmt = false; 4729 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4730 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4731 } 4732 4733 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4734 4735 /* 4736 * pseries-4.0 4737 */ 4738 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4739 uint64_t *buid, hwaddr *pio, 4740 hwaddr *mmio32, hwaddr *mmio64, 4741 unsigned n_dma, uint32_t *liobns, 4742 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4743 { 4744 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 4745 liobns, nv2gpa, nv2atsd, errp)) { 4746 return false; 4747 } 4748 4749 *nv2gpa = 0; 4750 *nv2atsd = 0; 4751 return true; 4752 } 4753 static void spapr_machine_4_0_class_options(MachineClass *mc) 4754 { 4755 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4756 4757 spapr_machine_4_1_class_options(mc); 4758 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4759 smc->phb_placement = phb_placement_4_0; 4760 smc->irq = &spapr_irq_xics; 4761 smc->pre_4_1_migration = true; 4762 } 4763 4764 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4765 4766 /* 4767 * pseries-3.1 4768 */ 4769 static void spapr_machine_3_1_class_options(MachineClass *mc) 4770 { 4771 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4772 4773 spapr_machine_4_0_class_options(mc); 4774 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4775 4776 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4777 smc->update_dt_enabled = false; 4778 smc->dr_phb_enabled = false; 4779 smc->broken_host_serial_model = true; 4780 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4781 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4782 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4783 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4784 } 4785 4786 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4787 4788 /* 4789 * pseries-3.0 4790 */ 4791 4792 static void spapr_machine_3_0_class_options(MachineClass *mc) 4793 { 4794 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4795 4796 spapr_machine_3_1_class_options(mc); 4797 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4798 4799 smc->legacy_irq_allocation = true; 4800 smc->nr_xirqs = 0x400; 4801 smc->irq = &spapr_irq_xics_legacy; 4802 } 4803 4804 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4805 4806 /* 4807 * pseries-2.12 4808 */ 4809 static void spapr_machine_2_12_class_options(MachineClass *mc) 4810 { 4811 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4812 static GlobalProperty compat[] = { 4813 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4814 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4815 }; 4816 4817 spapr_machine_3_0_class_options(mc); 4818 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4819 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4820 4821 /* We depend on kvm_enabled() to choose a default value for the 4822 * hpt-max-page-size capability. Of course we can't do it here 4823 * because this is too early and the HW accelerator isn't initialzed 4824 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4825 */ 4826 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4827 } 4828 4829 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4830 4831 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4832 { 4833 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4834 4835 spapr_machine_2_12_class_options(mc); 4836 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4837 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4838 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4839 } 4840 4841 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4842 4843 /* 4844 * pseries-2.11 4845 */ 4846 4847 static void spapr_machine_2_11_class_options(MachineClass *mc) 4848 { 4849 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4850 4851 spapr_machine_2_12_class_options(mc); 4852 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4853 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4854 } 4855 4856 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4857 4858 /* 4859 * pseries-2.10 4860 */ 4861 4862 static void spapr_machine_2_10_class_options(MachineClass *mc) 4863 { 4864 spapr_machine_2_11_class_options(mc); 4865 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4866 } 4867 4868 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4869 4870 /* 4871 * pseries-2.9 4872 */ 4873 4874 static void spapr_machine_2_9_class_options(MachineClass *mc) 4875 { 4876 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4877 static GlobalProperty compat[] = { 4878 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4879 }; 4880 4881 spapr_machine_2_10_class_options(mc); 4882 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4883 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4884 smc->pre_2_10_has_unused_icps = true; 4885 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4886 } 4887 4888 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4889 4890 /* 4891 * pseries-2.8 4892 */ 4893 4894 static void spapr_machine_2_8_class_options(MachineClass *mc) 4895 { 4896 static GlobalProperty compat[] = { 4897 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4898 }; 4899 4900 spapr_machine_2_9_class_options(mc); 4901 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4902 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4903 mc->numa_mem_align_shift = 23; 4904 } 4905 4906 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4907 4908 /* 4909 * pseries-2.7 4910 */ 4911 4912 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4913 uint64_t *buid, hwaddr *pio, 4914 hwaddr *mmio32, hwaddr *mmio64, 4915 unsigned n_dma, uint32_t *liobns, 4916 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4917 { 4918 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4919 const uint64_t base_buid = 0x800000020000000ULL; 4920 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4921 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4922 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4923 const uint32_t max_index = 255; 4924 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4925 4926 uint64_t ram_top = MACHINE(spapr)->ram_size; 4927 hwaddr phb0_base, phb_base; 4928 int i; 4929 4930 /* Do we have device memory? */ 4931 if (MACHINE(spapr)->maxram_size > ram_top) { 4932 /* Can't just use maxram_size, because there may be an 4933 * alignment gap between normal and device memory regions 4934 */ 4935 ram_top = MACHINE(spapr)->device_memory->base + 4936 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4937 } 4938 4939 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4940 4941 if (index > max_index) { 4942 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4943 max_index); 4944 return false; 4945 } 4946 4947 *buid = base_buid + index; 4948 for (i = 0; i < n_dma; ++i) { 4949 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4950 } 4951 4952 phb_base = phb0_base + index * phb_spacing; 4953 *pio = phb_base + pio_offset; 4954 *mmio32 = phb_base + mmio_offset; 4955 /* 4956 * We don't set the 64-bit MMIO window, relying on the PHB's 4957 * fallback behaviour of automatically splitting a large "32-bit" 4958 * window into contiguous 32-bit and 64-bit windows 4959 */ 4960 4961 *nv2gpa = 0; 4962 *nv2atsd = 0; 4963 return true; 4964 } 4965 4966 static void spapr_machine_2_7_class_options(MachineClass *mc) 4967 { 4968 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4969 static GlobalProperty compat[] = { 4970 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4971 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4972 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4973 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4974 }; 4975 4976 spapr_machine_2_8_class_options(mc); 4977 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4978 mc->default_machine_opts = "modern-hotplug-events=off"; 4979 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4980 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4981 smc->phb_placement = phb_placement_2_7; 4982 } 4983 4984 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4985 4986 /* 4987 * pseries-2.6 4988 */ 4989 4990 static void spapr_machine_2_6_class_options(MachineClass *mc) 4991 { 4992 static GlobalProperty compat[] = { 4993 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4994 }; 4995 4996 spapr_machine_2_7_class_options(mc); 4997 mc->has_hotpluggable_cpus = false; 4998 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4999 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5000 } 5001 5002 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 5003 5004 /* 5005 * pseries-2.5 5006 */ 5007 5008 static void spapr_machine_2_5_class_options(MachineClass *mc) 5009 { 5010 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5011 static GlobalProperty compat[] = { 5012 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 5013 }; 5014 5015 spapr_machine_2_6_class_options(mc); 5016 smc->use_ohci_by_default = true; 5017 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 5018 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5019 } 5020 5021 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 5022 5023 /* 5024 * pseries-2.4 5025 */ 5026 5027 static void spapr_machine_2_4_class_options(MachineClass *mc) 5028 { 5029 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5030 5031 spapr_machine_2_5_class_options(mc); 5032 smc->dr_lmb_enabled = false; 5033 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 5034 } 5035 5036 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 5037 5038 /* 5039 * pseries-2.3 5040 */ 5041 5042 static void spapr_machine_2_3_class_options(MachineClass *mc) 5043 { 5044 static GlobalProperty compat[] = { 5045 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 5046 }; 5047 spapr_machine_2_4_class_options(mc); 5048 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 5049 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5050 } 5051 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 5052 5053 /* 5054 * pseries-2.2 5055 */ 5056 5057 static void spapr_machine_2_2_class_options(MachineClass *mc) 5058 { 5059 static GlobalProperty compat[] = { 5060 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 5061 }; 5062 5063 spapr_machine_2_3_class_options(mc); 5064 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 5065 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5066 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 5067 } 5068 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 5069 5070 /* 5071 * pseries-2.1 5072 */ 5073 5074 static void spapr_machine_2_1_class_options(MachineClass *mc) 5075 { 5076 spapr_machine_2_2_class_options(mc); 5077 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 5078 } 5079 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 5080 5081 static void spapr_machine_register_types(void) 5082 { 5083 type_register_static(&spapr_machine_info); 5084 } 5085 5086 type_init(spapr_machine_register_types) 5087