1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/numa.h" 32 #include "hw/hw.h" 33 #include "qemu/log.h" 34 #include "hw/fw-path-provider.h" 35 #include "elf.h" 36 #include "net/net.h" 37 #include "sysemu/device_tree.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/misc.h" 42 #include "migration/global_state.h" 43 #include "migration/register.h" 44 #include "mmu-hash64.h" 45 #include "mmu-book3s-v3.h" 46 #include "cpu-models.h" 47 #include "qom/cpu.h" 48 49 #include "hw/boards.h" 50 #include "hw/ppc/ppc.h" 51 #include "hw/loader.h" 52 53 #include "hw/ppc/fdt.h" 54 #include "hw/ppc/spapr.h" 55 #include "hw/ppc/spapr_vio.h" 56 #include "hw/pci-host/spapr.h" 57 #include "hw/pci/msi.h" 58 59 #include "hw/pci/pci.h" 60 #include "hw/scsi/scsi.h" 61 #include "hw/virtio/virtio-scsi.h" 62 #include "hw/virtio/vhost-scsi-common.h" 63 64 #include "exec/address-spaces.h" 65 #include "exec/ram_addr.h" 66 #include "hw/usb.h" 67 #include "qemu/config-file.h" 68 #include "qemu/error-report.h" 69 #include "trace.h" 70 #include "hw/nmi.h" 71 #include "hw/intc/intc.h" 72 73 #include "hw/compat.h" 74 #include "qemu/cutils.h" 75 #include "hw/ppc/spapr_cpu_core.h" 76 #include "hw/mem/memory-device.h" 77 78 #include <libfdt.h> 79 80 /* SLOF memory layout: 81 * 82 * SLOF raw image loaded at 0, copies its romfs right below the flat 83 * device-tree, then position SLOF itself 31M below that 84 * 85 * So we set FW_OVERHEAD to 40MB which should account for all of that 86 * and more 87 * 88 * We load our kernel at 4M, leaving space for SLOF initial image 89 */ 90 #define FDT_MAX_SIZE 0x100000 91 #define RTAS_MAX_SIZE 0x10000 92 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 93 #define FW_MAX_SIZE 0x400000 94 #define FW_FILE_NAME "slof.bin" 95 #define FW_OVERHEAD 0x2800000 96 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 97 98 #define MIN_RMA_SLOF 128UL 99 100 #define PHANDLE_XICP 0x00001111 101 102 /* These two functions implement the VCPU id numbering: one to compute them 103 * all and one to identify thread 0 of a VCORE. Any change to the first one 104 * is likely to have an impact on the second one, so let's keep them close. 105 */ 106 static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index) 107 { 108 assert(spapr->vsmt); 109 return 110 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 111 } 112 static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr, 113 PowerPCCPU *cpu) 114 { 115 assert(spapr->vsmt); 116 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 117 } 118 119 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 120 { 121 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 122 * and newer QEMUs don't even have them. In both cases, we don't want 123 * to send anything on the wire. 124 */ 125 return false; 126 } 127 128 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 129 .name = "icp/server", 130 .version_id = 1, 131 .minimum_version_id = 1, 132 .needed = pre_2_10_vmstate_dummy_icp_needed, 133 .fields = (VMStateField[]) { 134 VMSTATE_UNUSED(4), /* uint32_t xirr */ 135 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 136 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 137 VMSTATE_END_OF_LIST() 138 }, 139 }; 140 141 static void pre_2_10_vmstate_register_dummy_icp(int i) 142 { 143 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 144 (void *)(uintptr_t) i); 145 } 146 147 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 148 { 149 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 150 (void *)(uintptr_t) i); 151 } 152 153 static int xics_max_server_number(sPAPRMachineState *spapr) 154 { 155 assert(spapr->vsmt); 156 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads); 157 } 158 159 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 160 int smt_threads) 161 { 162 int i, ret = 0; 163 uint32_t servers_prop[smt_threads]; 164 uint32_t gservers_prop[smt_threads * 2]; 165 int index = spapr_get_vcpu_id(cpu); 166 167 if (cpu->compat_pvr) { 168 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 169 if (ret < 0) { 170 return ret; 171 } 172 } 173 174 /* Build interrupt servers and gservers properties */ 175 for (i = 0; i < smt_threads; i++) { 176 servers_prop[i] = cpu_to_be32(index + i); 177 /* Hack, direct the group queues back to cpu 0 */ 178 gservers_prop[i*2] = cpu_to_be32(index + i); 179 gservers_prop[i*2 + 1] = 0; 180 } 181 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 182 servers_prop, sizeof(servers_prop)); 183 if (ret < 0) { 184 return ret; 185 } 186 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 187 gservers_prop, sizeof(gservers_prop)); 188 189 return ret; 190 } 191 192 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 193 { 194 int index = spapr_get_vcpu_id(cpu); 195 uint32_t associativity[] = {cpu_to_be32(0x5), 196 cpu_to_be32(0x0), 197 cpu_to_be32(0x0), 198 cpu_to_be32(0x0), 199 cpu_to_be32(cpu->node_id), 200 cpu_to_be32(index)}; 201 202 /* Advertise NUMA via ibm,associativity */ 203 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 204 sizeof(associativity)); 205 } 206 207 /* Populate the "ibm,pa-features" property */ 208 static void spapr_populate_pa_features(sPAPRMachineState *spapr, 209 PowerPCCPU *cpu, 210 void *fdt, int offset, 211 bool legacy_guest) 212 { 213 uint8_t pa_features_206[] = { 6, 0, 214 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 215 uint8_t pa_features_207[] = { 24, 0, 216 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 217 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 218 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 219 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 220 uint8_t pa_features_300[] = { 66, 0, 221 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 222 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 223 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 224 /* 6: DS207 */ 225 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 226 /* 16: Vector */ 227 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 228 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 229 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 230 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 231 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 232 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 233 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 234 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 236 /* 42: PM, 44: PC RA, 46: SC vec'd */ 237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 238 /* 48: SIMD, 50: QP BFP, 52: String */ 239 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 240 /* 54: DecFP, 56: DecI, 58: SHA */ 241 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 242 /* 60: NM atomic, 62: RNG */ 243 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 244 }; 245 uint8_t *pa_features = NULL; 246 size_t pa_size; 247 248 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 249 pa_features = pa_features_206; 250 pa_size = sizeof(pa_features_206); 251 } 252 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 253 pa_features = pa_features_207; 254 pa_size = sizeof(pa_features_207); 255 } 256 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 257 pa_features = pa_features_300; 258 pa_size = sizeof(pa_features_300); 259 } 260 if (!pa_features) { 261 return; 262 } 263 264 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 265 /* 266 * Note: we keep CI large pages off by default because a 64K capable 267 * guest provisioned with large pages might otherwise try to map a qemu 268 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 269 * even if that qemu runs on a 4k host. 270 * We dd this bit back here if we are confident this is not an issue 271 */ 272 pa_features[3] |= 0x20; 273 } 274 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 275 pa_features[24] |= 0x80; /* Transactional memory support */ 276 } 277 if (legacy_guest && pa_size > 40) { 278 /* Workaround for broken kernels that attempt (guest) radix 279 * mode when they can't handle it, if they see the radix bit set 280 * in pa-features. So hide it from them. */ 281 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 282 } 283 284 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 285 } 286 287 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 288 { 289 int ret = 0, offset, cpus_offset; 290 CPUState *cs; 291 char cpu_model[32]; 292 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 293 294 CPU_FOREACH(cs) { 295 PowerPCCPU *cpu = POWERPC_CPU(cs); 296 DeviceClass *dc = DEVICE_GET_CLASS(cs); 297 int index = spapr_get_vcpu_id(cpu); 298 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 299 300 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 301 continue; 302 } 303 304 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 305 306 cpus_offset = fdt_path_offset(fdt, "/cpus"); 307 if (cpus_offset < 0) { 308 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 309 if (cpus_offset < 0) { 310 return cpus_offset; 311 } 312 } 313 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 314 if (offset < 0) { 315 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 316 if (offset < 0) { 317 return offset; 318 } 319 } 320 321 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 322 pft_size_prop, sizeof(pft_size_prop)); 323 if (ret < 0) { 324 return ret; 325 } 326 327 if (nb_numa_nodes > 1) { 328 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 329 if (ret < 0) { 330 return ret; 331 } 332 } 333 334 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 335 if (ret < 0) { 336 return ret; 337 } 338 339 spapr_populate_pa_features(spapr, cpu, fdt, offset, 340 spapr->cas_legacy_guest_workaround); 341 } 342 return ret; 343 } 344 345 static hwaddr spapr_node0_size(MachineState *machine) 346 { 347 if (nb_numa_nodes) { 348 int i; 349 for (i = 0; i < nb_numa_nodes; ++i) { 350 if (numa_info[i].node_mem) { 351 return MIN(pow2floor(numa_info[i].node_mem), 352 machine->ram_size); 353 } 354 } 355 } 356 return machine->ram_size; 357 } 358 359 static void add_str(GString *s, const gchar *s1) 360 { 361 g_string_append_len(s, s1, strlen(s1) + 1); 362 } 363 364 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 365 hwaddr size) 366 { 367 uint32_t associativity[] = { 368 cpu_to_be32(0x4), /* length */ 369 cpu_to_be32(0x0), cpu_to_be32(0x0), 370 cpu_to_be32(0x0), cpu_to_be32(nodeid) 371 }; 372 char mem_name[32]; 373 uint64_t mem_reg_property[2]; 374 int off; 375 376 mem_reg_property[0] = cpu_to_be64(start); 377 mem_reg_property[1] = cpu_to_be64(size); 378 379 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 380 off = fdt_add_subnode(fdt, 0, mem_name); 381 _FDT(off); 382 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 383 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 384 sizeof(mem_reg_property)))); 385 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 386 sizeof(associativity)))); 387 return off; 388 } 389 390 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 391 { 392 MachineState *machine = MACHINE(spapr); 393 hwaddr mem_start, node_size; 394 int i, nb_nodes = nb_numa_nodes; 395 NodeInfo *nodes = numa_info; 396 NodeInfo ramnode; 397 398 /* No NUMA nodes, assume there is just one node with whole RAM */ 399 if (!nb_numa_nodes) { 400 nb_nodes = 1; 401 ramnode.node_mem = machine->ram_size; 402 nodes = &ramnode; 403 } 404 405 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 406 if (!nodes[i].node_mem) { 407 continue; 408 } 409 if (mem_start >= machine->ram_size) { 410 node_size = 0; 411 } else { 412 node_size = nodes[i].node_mem; 413 if (node_size > machine->ram_size - mem_start) { 414 node_size = machine->ram_size - mem_start; 415 } 416 } 417 if (!mem_start) { 418 /* spapr_machine_init() checks for rma_size <= node0_size 419 * already */ 420 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 421 mem_start += spapr->rma_size; 422 node_size -= spapr->rma_size; 423 } 424 for ( ; node_size; ) { 425 hwaddr sizetmp = pow2floor(node_size); 426 427 /* mem_start != 0 here */ 428 if (ctzl(mem_start) < ctzl(sizetmp)) { 429 sizetmp = 1ULL << ctzl(mem_start); 430 } 431 432 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 433 node_size -= sizetmp; 434 mem_start += sizetmp; 435 } 436 } 437 438 return 0; 439 } 440 441 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 442 sPAPRMachineState *spapr) 443 { 444 PowerPCCPU *cpu = POWERPC_CPU(cs); 445 CPUPPCState *env = &cpu->env; 446 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 447 int index = spapr_get_vcpu_id(cpu); 448 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 449 0xffffffff, 0xffffffff}; 450 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 451 : SPAPR_TIMEBASE_FREQ; 452 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 453 uint32_t page_sizes_prop[64]; 454 size_t page_sizes_prop_size; 455 uint32_t vcpus_per_socket = smp_threads * smp_cores; 456 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 457 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 458 sPAPRDRConnector *drc; 459 int drc_index; 460 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 461 int i; 462 463 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 464 if (drc) { 465 drc_index = spapr_drc_index(drc); 466 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 467 } 468 469 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 470 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 471 472 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 473 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 474 env->dcache_line_size))); 475 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 476 env->dcache_line_size))); 477 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 478 env->icache_line_size))); 479 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 480 env->icache_line_size))); 481 482 if (pcc->l1_dcache_size) { 483 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 484 pcc->l1_dcache_size))); 485 } else { 486 warn_report("Unknown L1 dcache size for cpu"); 487 } 488 if (pcc->l1_icache_size) { 489 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 490 pcc->l1_icache_size))); 491 } else { 492 warn_report("Unknown L1 icache size for cpu"); 493 } 494 495 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 496 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 497 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 498 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 499 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 500 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 501 502 if (env->spr_cb[SPR_PURR].oea_read) { 503 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 504 } 505 506 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 507 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 508 segs, sizeof(segs)))); 509 } 510 511 /* Advertise VSX (vector extensions) if available 512 * 1 == VMX / Altivec available 513 * 2 == VSX available 514 * 515 * Only CPUs for which we create core types in spapr_cpu_core.c 516 * are possible, and all of those have VMX */ 517 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 518 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 519 } else { 520 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 521 } 522 523 /* Advertise DFP (Decimal Floating Point) if available 524 * 0 / no property == no DFP 525 * 1 == DFP available */ 526 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 527 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 528 } 529 530 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 531 sizeof(page_sizes_prop)); 532 if (page_sizes_prop_size) { 533 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 534 page_sizes_prop, page_sizes_prop_size))); 535 } 536 537 spapr_populate_pa_features(spapr, cpu, fdt, offset, false); 538 539 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 540 cs->cpu_index / vcpus_per_socket))); 541 542 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 543 pft_size_prop, sizeof(pft_size_prop)))); 544 545 if (nb_numa_nodes > 1) { 546 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 547 } 548 549 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 550 551 if (pcc->radix_page_info) { 552 for (i = 0; i < pcc->radix_page_info->count; i++) { 553 radix_AP_encodings[i] = 554 cpu_to_be32(pcc->radix_page_info->entries[i]); 555 } 556 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 557 radix_AP_encodings, 558 pcc->radix_page_info->count * 559 sizeof(radix_AP_encodings[0])))); 560 } 561 } 562 563 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 564 { 565 CPUState *cs; 566 int cpus_offset; 567 char *nodename; 568 569 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 570 _FDT(cpus_offset); 571 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 572 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 573 574 /* 575 * We walk the CPUs in reverse order to ensure that CPU DT nodes 576 * created by fdt_add_subnode() end up in the right order in FDT 577 * for the guest kernel the enumerate the CPUs correctly. 578 */ 579 CPU_FOREACH_REVERSE(cs) { 580 PowerPCCPU *cpu = POWERPC_CPU(cs); 581 int index = spapr_get_vcpu_id(cpu); 582 DeviceClass *dc = DEVICE_GET_CLASS(cs); 583 int offset; 584 585 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 586 continue; 587 } 588 589 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 590 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 591 g_free(nodename); 592 _FDT(offset); 593 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 594 } 595 596 } 597 598 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 599 { 600 MemoryDeviceInfoList *info; 601 602 for (info = list; info; info = info->next) { 603 MemoryDeviceInfo *value = info->value; 604 605 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 606 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 607 608 if (addr >= pcdimm_info->addr && 609 addr < (pcdimm_info->addr + pcdimm_info->size)) { 610 return pcdimm_info->node; 611 } 612 } 613 } 614 615 return -1; 616 } 617 618 struct sPAPRDrconfCellV2 { 619 uint32_t seq_lmbs; 620 uint64_t base_addr; 621 uint32_t drc_index; 622 uint32_t aa_index; 623 uint32_t flags; 624 } QEMU_PACKED; 625 626 typedef struct DrconfCellQueue { 627 struct sPAPRDrconfCellV2 cell; 628 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 629 } DrconfCellQueue; 630 631 static DrconfCellQueue * 632 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 633 uint32_t drc_index, uint32_t aa_index, 634 uint32_t flags) 635 { 636 DrconfCellQueue *elem; 637 638 elem = g_malloc0(sizeof(*elem)); 639 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 640 elem->cell.base_addr = cpu_to_be64(base_addr); 641 elem->cell.drc_index = cpu_to_be32(drc_index); 642 elem->cell.aa_index = cpu_to_be32(aa_index); 643 elem->cell.flags = cpu_to_be32(flags); 644 645 return elem; 646 } 647 648 /* ibm,dynamic-memory-v2 */ 649 static int spapr_populate_drmem_v2(sPAPRMachineState *spapr, void *fdt, 650 int offset, MemoryDeviceInfoList *dimms) 651 { 652 MachineState *machine = MACHINE(spapr); 653 uint8_t *int_buf, *cur_index, buf_len; 654 int ret; 655 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 656 uint64_t addr, cur_addr, size; 657 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 658 uint64_t mem_end = machine->device_memory->base + 659 memory_region_size(&machine->device_memory->mr); 660 uint32_t node, nr_entries = 0; 661 sPAPRDRConnector *drc; 662 DrconfCellQueue *elem, *next; 663 MemoryDeviceInfoList *info; 664 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 665 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 666 667 /* Entry to cover RAM and the gap area */ 668 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 669 SPAPR_LMB_FLAGS_RESERVED | 670 SPAPR_LMB_FLAGS_DRC_INVALID); 671 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 672 nr_entries++; 673 674 cur_addr = machine->device_memory->base; 675 for (info = dimms; info; info = info->next) { 676 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 677 678 addr = di->addr; 679 size = di->size; 680 node = di->node; 681 682 /* Entry for hot-pluggable area */ 683 if (cur_addr < addr) { 684 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 685 g_assert(drc); 686 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 687 cur_addr, spapr_drc_index(drc), -1, 0); 688 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 689 nr_entries++; 690 } 691 692 /* Entry for DIMM */ 693 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 694 g_assert(drc); 695 elem = spapr_get_drconf_cell(size / lmb_size, addr, 696 spapr_drc_index(drc), node, 697 SPAPR_LMB_FLAGS_ASSIGNED); 698 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 699 nr_entries++; 700 cur_addr = addr + size; 701 } 702 703 /* Entry for remaining hotpluggable area */ 704 if (cur_addr < mem_end) { 705 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 706 g_assert(drc); 707 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 708 cur_addr, spapr_drc_index(drc), -1, 0); 709 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 710 nr_entries++; 711 } 712 713 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 714 int_buf = cur_index = g_malloc0(buf_len); 715 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 716 cur_index += sizeof(nr_entries); 717 718 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 719 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 720 cur_index += sizeof(elem->cell); 721 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 722 g_free(elem); 723 } 724 725 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 726 g_free(int_buf); 727 if (ret < 0) { 728 return -1; 729 } 730 return 0; 731 } 732 733 /* ibm,dynamic-memory */ 734 static int spapr_populate_drmem_v1(sPAPRMachineState *spapr, void *fdt, 735 int offset, MemoryDeviceInfoList *dimms) 736 { 737 MachineState *machine = MACHINE(spapr); 738 int i, ret; 739 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 740 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 741 uint32_t nr_lmbs = (machine->device_memory->base + 742 memory_region_size(&machine->device_memory->mr)) / 743 lmb_size; 744 uint32_t *int_buf, *cur_index, buf_len; 745 746 /* 747 * Allocate enough buffer size to fit in ibm,dynamic-memory 748 */ 749 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 750 cur_index = int_buf = g_malloc0(buf_len); 751 int_buf[0] = cpu_to_be32(nr_lmbs); 752 cur_index++; 753 for (i = 0; i < nr_lmbs; i++) { 754 uint64_t addr = i * lmb_size; 755 uint32_t *dynamic_memory = cur_index; 756 757 if (i >= device_lmb_start) { 758 sPAPRDRConnector *drc; 759 760 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 761 g_assert(drc); 762 763 dynamic_memory[0] = cpu_to_be32(addr >> 32); 764 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 765 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 766 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 767 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 768 if (memory_region_present(get_system_memory(), addr)) { 769 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 770 } else { 771 dynamic_memory[5] = cpu_to_be32(0); 772 } 773 } else { 774 /* 775 * LMB information for RMA, boot time RAM and gap b/n RAM and 776 * device memory region -- all these are marked as reserved 777 * and as having no valid DRC. 778 */ 779 dynamic_memory[0] = cpu_to_be32(addr >> 32); 780 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 781 dynamic_memory[2] = cpu_to_be32(0); 782 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 783 dynamic_memory[4] = cpu_to_be32(-1); 784 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 785 SPAPR_LMB_FLAGS_DRC_INVALID); 786 } 787 788 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 789 } 790 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 791 g_free(int_buf); 792 if (ret < 0) { 793 return -1; 794 } 795 return 0; 796 } 797 798 /* 799 * Adds ibm,dynamic-reconfiguration-memory node. 800 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 801 * of this device tree node. 802 */ 803 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 804 { 805 MachineState *machine = MACHINE(spapr); 806 int ret, i, offset; 807 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 808 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 809 uint32_t *int_buf, *cur_index, buf_len; 810 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 811 MemoryDeviceInfoList *dimms = NULL; 812 813 /* 814 * Don't create the node if there is no device memory 815 */ 816 if (machine->ram_size == machine->maxram_size) { 817 return 0; 818 } 819 820 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 821 822 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 823 sizeof(prop_lmb_size)); 824 if (ret < 0) { 825 return ret; 826 } 827 828 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 829 if (ret < 0) { 830 return ret; 831 } 832 833 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 834 if (ret < 0) { 835 return ret; 836 } 837 838 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 839 dimms = qmp_memory_device_list(); 840 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 841 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 842 } else { 843 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 844 } 845 qapi_free_MemoryDeviceInfoList(dimms); 846 847 if (ret < 0) { 848 return ret; 849 } 850 851 /* ibm,associativity-lookup-arrays */ 852 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 853 cur_index = int_buf = g_malloc0(buf_len); 854 855 cur_index = int_buf; 856 int_buf[0] = cpu_to_be32(nr_nodes); 857 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 858 cur_index += 2; 859 for (i = 0; i < nr_nodes; i++) { 860 uint32_t associativity[] = { 861 cpu_to_be32(0x0), 862 cpu_to_be32(0x0), 863 cpu_to_be32(0x0), 864 cpu_to_be32(i) 865 }; 866 memcpy(cur_index, associativity, sizeof(associativity)); 867 cur_index += 4; 868 } 869 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 870 (cur_index - int_buf) * sizeof(uint32_t)); 871 g_free(int_buf); 872 873 return ret; 874 } 875 876 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 877 sPAPROptionVector *ov5_updates) 878 { 879 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 880 int ret = 0, offset; 881 882 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 883 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 884 g_assert(smc->dr_lmb_enabled); 885 ret = spapr_populate_drconf_memory(spapr, fdt); 886 if (ret) { 887 goto out; 888 } 889 } 890 891 offset = fdt_path_offset(fdt, "/chosen"); 892 if (offset < 0) { 893 offset = fdt_add_subnode(fdt, 0, "chosen"); 894 if (offset < 0) { 895 return offset; 896 } 897 } 898 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 899 "ibm,architecture-vec-5"); 900 901 out: 902 return ret; 903 } 904 905 static bool spapr_hotplugged_dev_before_cas(void) 906 { 907 Object *drc_container, *obj; 908 ObjectProperty *prop; 909 ObjectPropertyIterator iter; 910 911 drc_container = container_get(object_get_root(), "/dr-connector"); 912 object_property_iter_init(&iter, drc_container); 913 while ((prop = object_property_iter_next(&iter))) { 914 if (!strstart(prop->type, "link<", NULL)) { 915 continue; 916 } 917 obj = object_property_get_link(drc_container, prop->name, NULL); 918 if (spapr_drc_needed(obj)) { 919 return true; 920 } 921 } 922 return false; 923 } 924 925 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 926 target_ulong addr, target_ulong size, 927 sPAPROptionVector *ov5_updates) 928 { 929 void *fdt, *fdt_skel; 930 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 931 932 if (spapr_hotplugged_dev_before_cas()) { 933 return 1; 934 } 935 936 if (size < sizeof(hdr) || size > FW_MAX_SIZE) { 937 error_report("SLOF provided an unexpected CAS buffer size " 938 TARGET_FMT_lu " (min: %zu, max: %u)", 939 size, sizeof(hdr), FW_MAX_SIZE); 940 exit(EXIT_FAILURE); 941 } 942 943 size -= sizeof(hdr); 944 945 /* Create skeleton */ 946 fdt_skel = g_malloc0(size); 947 _FDT((fdt_create(fdt_skel, size))); 948 _FDT((fdt_finish_reservemap(fdt_skel))); 949 _FDT((fdt_begin_node(fdt_skel, ""))); 950 _FDT((fdt_end_node(fdt_skel))); 951 _FDT((fdt_finish(fdt_skel))); 952 fdt = g_malloc0(size); 953 _FDT((fdt_open_into(fdt_skel, fdt, size))); 954 g_free(fdt_skel); 955 956 /* Fixup cpu nodes */ 957 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 958 959 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 960 return -1; 961 } 962 963 /* Pack resulting tree */ 964 _FDT((fdt_pack(fdt))); 965 966 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 967 trace_spapr_cas_failed(size); 968 return -1; 969 } 970 971 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 972 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 973 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 974 g_free(fdt); 975 976 return 0; 977 } 978 979 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 980 { 981 int rtas; 982 GString *hypertas = g_string_sized_new(256); 983 GString *qemu_hypertas = g_string_sized_new(256); 984 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 985 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 986 memory_region_size(&MACHINE(spapr)->device_memory->mr); 987 uint32_t lrdr_capacity[] = { 988 cpu_to_be32(max_device_addr >> 32), 989 cpu_to_be32(max_device_addr & 0xffffffff), 990 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 991 cpu_to_be32(max_cpus / smp_threads), 992 }; 993 uint32_t maxdomains[] = { 994 cpu_to_be32(4), 995 cpu_to_be32(0), 996 cpu_to_be32(0), 997 cpu_to_be32(0), 998 cpu_to_be32(nb_numa_nodes ? nb_numa_nodes - 1 : 0), 999 }; 1000 1001 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 1002 1003 /* hypertas */ 1004 add_str(hypertas, "hcall-pft"); 1005 add_str(hypertas, "hcall-term"); 1006 add_str(hypertas, "hcall-dabr"); 1007 add_str(hypertas, "hcall-interrupt"); 1008 add_str(hypertas, "hcall-tce"); 1009 add_str(hypertas, "hcall-vio"); 1010 add_str(hypertas, "hcall-splpar"); 1011 add_str(hypertas, "hcall-bulk"); 1012 add_str(hypertas, "hcall-set-mode"); 1013 add_str(hypertas, "hcall-sprg0"); 1014 add_str(hypertas, "hcall-copy"); 1015 add_str(hypertas, "hcall-debug"); 1016 add_str(qemu_hypertas, "hcall-memop1"); 1017 1018 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 1019 add_str(hypertas, "hcall-multi-tce"); 1020 } 1021 1022 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 1023 add_str(hypertas, "hcall-hpt-resize"); 1024 } 1025 1026 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 1027 hypertas->str, hypertas->len)); 1028 g_string_free(hypertas, TRUE); 1029 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 1030 qemu_hypertas->str, qemu_hypertas->len)); 1031 g_string_free(qemu_hypertas, TRUE); 1032 1033 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 1034 refpoints, sizeof(refpoints))); 1035 1036 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 1037 maxdomains, sizeof(maxdomains))); 1038 1039 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 1040 RTAS_ERROR_LOG_MAX)); 1041 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 1042 RTAS_EVENT_SCAN_RATE)); 1043 1044 g_assert(msi_nonbroken); 1045 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 1046 1047 /* 1048 * According to PAPR, rtas ibm,os-term does not guarantee a return 1049 * back to the guest cpu. 1050 * 1051 * While an additional ibm,extended-os-term property indicates 1052 * that rtas call return will always occur. Set this property. 1053 */ 1054 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1055 1056 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1057 lrdr_capacity, sizeof(lrdr_capacity))); 1058 1059 spapr_dt_rtas_tokens(fdt, rtas); 1060 } 1061 1062 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features 1063 * that the guest may request and thus the valid values for bytes 24..26 of 1064 * option vector 5: */ 1065 static void spapr_dt_ov5_platform_support(void *fdt, int chosen) 1066 { 1067 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1068 1069 char val[2 * 4] = { 1070 23, 0x00, /* Xive mode, filled in below. */ 1071 24, 0x00, /* Hash/Radix, filled in below. */ 1072 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1073 26, 0x40, /* Radix options: GTSE == yes. */ 1074 }; 1075 1076 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1077 first_ppc_cpu->compat_pvr)) { 1078 /* If we're in a pre POWER9 compat mode then the guest should do hash */ 1079 val[3] = 0x00; /* Hash */ 1080 } else if (kvm_enabled()) { 1081 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1082 val[3] = 0x80; /* OV5_MMU_BOTH */ 1083 } else if (kvmppc_has_cap_mmu_radix()) { 1084 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1085 } else { 1086 val[3] = 0x00; /* Hash */ 1087 } 1088 } else { 1089 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1090 val[3] = 0xC0; 1091 } 1092 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1093 val, sizeof(val))); 1094 } 1095 1096 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 1097 { 1098 MachineState *machine = MACHINE(spapr); 1099 int chosen; 1100 const char *boot_device = machine->boot_order; 1101 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1102 size_t cb = 0; 1103 char *bootlist = get_boot_devices_list(&cb); 1104 1105 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1106 1107 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 1108 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1109 spapr->initrd_base)); 1110 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1111 spapr->initrd_base + spapr->initrd_size)); 1112 1113 if (spapr->kernel_size) { 1114 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1115 cpu_to_be64(spapr->kernel_size) }; 1116 1117 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1118 &kprop, sizeof(kprop))); 1119 if (spapr->kernel_le) { 1120 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1121 } 1122 } 1123 if (boot_menu) { 1124 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1125 } 1126 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1127 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1128 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1129 1130 if (cb && bootlist) { 1131 int i; 1132 1133 for (i = 0; i < cb; i++) { 1134 if (bootlist[i] == '\n') { 1135 bootlist[i] = ' '; 1136 } 1137 } 1138 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1139 } 1140 1141 if (boot_device && strlen(boot_device)) { 1142 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1143 } 1144 1145 if (!spapr->has_graphics && stdout_path) { 1146 /* 1147 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1148 * kernel. New platforms should only use the "stdout-path" property. Set 1149 * the new property and continue using older property to remain 1150 * compatible with the existing firmware. 1151 */ 1152 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1153 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1154 } 1155 1156 spapr_dt_ov5_platform_support(fdt, chosen); 1157 1158 g_free(stdout_path); 1159 g_free(bootlist); 1160 } 1161 1162 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 1163 { 1164 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1165 * KVM to work under pHyp with some guest co-operation */ 1166 int hypervisor; 1167 uint8_t hypercall[16]; 1168 1169 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1170 /* indicate KVM hypercall interface */ 1171 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1172 if (kvmppc_has_cap_fixup_hcalls()) { 1173 /* 1174 * Older KVM versions with older guest kernels were broken 1175 * with the magic page, don't allow the guest to map it. 1176 */ 1177 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1178 sizeof(hypercall))) { 1179 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1180 hypercall, sizeof(hypercall))); 1181 } 1182 } 1183 } 1184 1185 static void *spapr_build_fdt(sPAPRMachineState *spapr, 1186 hwaddr rtas_addr, 1187 hwaddr rtas_size) 1188 { 1189 MachineState *machine = MACHINE(spapr); 1190 MachineClass *mc = MACHINE_GET_CLASS(machine); 1191 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1192 int ret; 1193 void *fdt; 1194 sPAPRPHBState *phb; 1195 char *buf; 1196 1197 fdt = g_malloc0(FDT_MAX_SIZE); 1198 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1199 1200 /* Root node */ 1201 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1202 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1203 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1204 1205 /* 1206 * Add info to guest to indentify which host is it being run on 1207 * and what is the uuid of the guest 1208 */ 1209 if (kvmppc_get_host_model(&buf)) { 1210 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1211 g_free(buf); 1212 } 1213 if (kvmppc_get_host_serial(&buf)) { 1214 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1215 g_free(buf); 1216 } 1217 1218 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1219 1220 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1221 if (qemu_uuid_set) { 1222 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1223 } 1224 g_free(buf); 1225 1226 if (qemu_get_vm_name()) { 1227 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1228 qemu_get_vm_name())); 1229 } 1230 1231 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1232 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1233 1234 /* /interrupt controller */ 1235 spapr_dt_xics(xics_max_server_number(spapr), fdt, PHANDLE_XICP); 1236 1237 ret = spapr_populate_memory(spapr, fdt); 1238 if (ret < 0) { 1239 error_report("couldn't setup memory nodes in fdt"); 1240 exit(1); 1241 } 1242 1243 /* /vdevice */ 1244 spapr_dt_vdevice(spapr->vio_bus, fdt); 1245 1246 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1247 ret = spapr_rng_populate_dt(fdt); 1248 if (ret < 0) { 1249 error_report("could not set up rng device in the fdt"); 1250 exit(1); 1251 } 1252 } 1253 1254 QLIST_FOREACH(phb, &spapr->phbs, list) { 1255 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 1256 if (ret < 0) { 1257 error_report("couldn't setup PCI devices in fdt"); 1258 exit(1); 1259 } 1260 } 1261 1262 /* cpus */ 1263 spapr_populate_cpus_dt_node(fdt, spapr); 1264 1265 if (smc->dr_lmb_enabled) { 1266 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1267 } 1268 1269 if (mc->has_hotpluggable_cpus) { 1270 int offset = fdt_path_offset(fdt, "/cpus"); 1271 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1272 SPAPR_DR_CONNECTOR_TYPE_CPU); 1273 if (ret < 0) { 1274 error_report("Couldn't set up CPU DR device tree properties"); 1275 exit(1); 1276 } 1277 } 1278 1279 /* /event-sources */ 1280 spapr_dt_events(spapr, fdt); 1281 1282 /* /rtas */ 1283 spapr_dt_rtas(spapr, fdt); 1284 1285 /* /chosen */ 1286 spapr_dt_chosen(spapr, fdt); 1287 1288 /* /hypervisor */ 1289 if (kvm_enabled()) { 1290 spapr_dt_hypervisor(spapr, fdt); 1291 } 1292 1293 /* Build memory reserve map */ 1294 if (spapr->kernel_size) { 1295 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1296 } 1297 if (spapr->initrd_size) { 1298 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1299 } 1300 1301 /* ibm,client-architecture-support updates */ 1302 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1303 if (ret < 0) { 1304 error_report("couldn't setup CAS properties fdt"); 1305 exit(1); 1306 } 1307 1308 return fdt; 1309 } 1310 1311 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1312 { 1313 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1314 } 1315 1316 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1317 PowerPCCPU *cpu) 1318 { 1319 CPUPPCState *env = &cpu->env; 1320 1321 /* The TCG path should also be holding the BQL at this point */ 1322 g_assert(qemu_mutex_iothread_locked()); 1323 1324 if (msr_pr) { 1325 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1326 env->gpr[3] = H_PRIVILEGE; 1327 } else { 1328 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1329 } 1330 } 1331 1332 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1333 { 1334 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1335 1336 return spapr->patb_entry; 1337 } 1338 1339 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1340 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1341 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1342 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1343 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1344 1345 /* 1346 * Get the fd to access the kernel htab, re-opening it if necessary 1347 */ 1348 static int get_htab_fd(sPAPRMachineState *spapr) 1349 { 1350 Error *local_err = NULL; 1351 1352 if (spapr->htab_fd >= 0) { 1353 return spapr->htab_fd; 1354 } 1355 1356 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1357 if (spapr->htab_fd < 0) { 1358 error_report_err(local_err); 1359 } 1360 1361 return spapr->htab_fd; 1362 } 1363 1364 void close_htab_fd(sPAPRMachineState *spapr) 1365 { 1366 if (spapr->htab_fd >= 0) { 1367 close(spapr->htab_fd); 1368 } 1369 spapr->htab_fd = -1; 1370 } 1371 1372 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1373 { 1374 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1375 1376 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1377 } 1378 1379 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1380 { 1381 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1382 1383 assert(kvm_enabled()); 1384 1385 if (!spapr->htab) { 1386 return 0; 1387 } 1388 1389 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1390 } 1391 1392 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1393 hwaddr ptex, int n) 1394 { 1395 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1396 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1397 1398 if (!spapr->htab) { 1399 /* 1400 * HTAB is controlled by KVM. Fetch into temporary buffer 1401 */ 1402 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1403 kvmppc_read_hptes(hptes, ptex, n); 1404 return hptes; 1405 } 1406 1407 /* 1408 * HTAB is controlled by QEMU. Just point to the internally 1409 * accessible PTEG. 1410 */ 1411 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1412 } 1413 1414 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1415 const ppc_hash_pte64_t *hptes, 1416 hwaddr ptex, int n) 1417 { 1418 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1419 1420 if (!spapr->htab) { 1421 g_free((void *)hptes); 1422 } 1423 1424 /* Nothing to do for qemu managed HPT */ 1425 } 1426 1427 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1428 uint64_t pte0, uint64_t pte1) 1429 { 1430 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1431 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1432 1433 if (!spapr->htab) { 1434 kvmppc_write_hpte(ptex, pte0, pte1); 1435 } else { 1436 stq_p(spapr->htab + offset, pte0); 1437 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1438 } 1439 } 1440 1441 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1442 { 1443 int shift; 1444 1445 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1446 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1447 * that's much more than is needed for Linux guests */ 1448 shift = ctz64(pow2ceil(ramsize)) - 7; 1449 shift = MAX(shift, 18); /* Minimum architected size */ 1450 shift = MIN(shift, 46); /* Maximum architected size */ 1451 return shift; 1452 } 1453 1454 void spapr_free_hpt(sPAPRMachineState *spapr) 1455 { 1456 g_free(spapr->htab); 1457 spapr->htab = NULL; 1458 spapr->htab_shift = 0; 1459 close_htab_fd(spapr); 1460 } 1461 1462 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1463 Error **errp) 1464 { 1465 long rc; 1466 1467 /* Clean up any HPT info from a previous boot */ 1468 spapr_free_hpt(spapr); 1469 1470 rc = kvmppc_reset_htab(shift); 1471 if (rc < 0) { 1472 /* kernel-side HPT needed, but couldn't allocate one */ 1473 error_setg_errno(errp, errno, 1474 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1475 shift); 1476 /* This is almost certainly fatal, but if the caller really 1477 * wants to carry on with shift == 0, it's welcome to try */ 1478 } else if (rc > 0) { 1479 /* kernel-side HPT allocated */ 1480 if (rc != shift) { 1481 error_setg(errp, 1482 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1483 shift, rc); 1484 } 1485 1486 spapr->htab_shift = shift; 1487 spapr->htab = NULL; 1488 } else { 1489 /* kernel-side HPT not needed, allocate in userspace instead */ 1490 size_t size = 1ULL << shift; 1491 int i; 1492 1493 spapr->htab = qemu_memalign(size, size); 1494 if (!spapr->htab) { 1495 error_setg_errno(errp, errno, 1496 "Could not allocate HPT of order %d", shift); 1497 return; 1498 } 1499 1500 memset(spapr->htab, 0, size); 1501 spapr->htab_shift = shift; 1502 1503 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1504 DIRTY_HPTE(HPTE(spapr->htab, i)); 1505 } 1506 } 1507 /* We're setting up a hash table, so that means we're not radix */ 1508 spapr->patb_entry = 0; 1509 } 1510 1511 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1512 { 1513 int hpt_shift; 1514 1515 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1516 || (spapr->cas_reboot 1517 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1518 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1519 } else { 1520 uint64_t current_ram_size; 1521 1522 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1523 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1524 } 1525 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1526 1527 if (spapr->vrma_adjust) { 1528 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1529 spapr->htab_shift); 1530 } 1531 } 1532 1533 static int spapr_reset_drcs(Object *child, void *opaque) 1534 { 1535 sPAPRDRConnector *drc = 1536 (sPAPRDRConnector *) object_dynamic_cast(child, 1537 TYPE_SPAPR_DR_CONNECTOR); 1538 1539 if (drc) { 1540 spapr_drc_reset(drc); 1541 } 1542 1543 return 0; 1544 } 1545 1546 static void spapr_machine_reset(void) 1547 { 1548 MachineState *machine = MACHINE(qdev_get_machine()); 1549 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1550 PowerPCCPU *first_ppc_cpu; 1551 uint32_t rtas_limit; 1552 hwaddr rtas_addr, fdt_addr; 1553 void *fdt; 1554 int rc; 1555 1556 spapr_caps_apply(spapr); 1557 1558 first_ppc_cpu = POWERPC_CPU(first_cpu); 1559 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1560 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1561 spapr->max_compat_pvr)) { 1562 /* If using KVM with radix mode available, VCPUs can be started 1563 * without a HPT because KVM will start them in radix mode. 1564 * Set the GR bit in PATB so that we know there is no HPT. */ 1565 spapr->patb_entry = PATBE1_GR; 1566 } else { 1567 spapr_setup_hpt_and_vrma(spapr); 1568 } 1569 1570 /* if this reset wasn't generated by CAS, we should reset our 1571 * negotiated options and start from scratch */ 1572 if (!spapr->cas_reboot) { 1573 spapr_ovec_cleanup(spapr->ov5_cas); 1574 spapr->ov5_cas = spapr_ovec_new(); 1575 1576 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); 1577 } 1578 1579 if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 1580 spapr_irq_msi_reset(spapr); 1581 } 1582 1583 qemu_devices_reset(); 1584 1585 /* DRC reset may cause a device to be unplugged. This will cause troubles 1586 * if this device is used by another device (eg, a running vhost backend 1587 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1588 * situations, we reset DRCs after all devices have been reset. 1589 */ 1590 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1591 1592 spapr_clear_pending_events(spapr); 1593 1594 /* 1595 * We place the device tree and RTAS just below either the top of the RMA, 1596 * or just below 2GB, whichever is lowere, so that it can be 1597 * processed with 32-bit real mode code if necessary 1598 */ 1599 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1600 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1601 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1602 1603 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1604 1605 spapr_load_rtas(spapr, fdt, rtas_addr); 1606 1607 rc = fdt_pack(fdt); 1608 1609 /* Should only fail if we've built a corrupted tree */ 1610 assert(rc == 0); 1611 1612 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1613 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1614 fdt_totalsize(fdt), FDT_MAX_SIZE); 1615 exit(1); 1616 } 1617 1618 /* Load the fdt */ 1619 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1620 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1621 g_free(fdt); 1622 1623 /* Set up the entry state */ 1624 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); 1625 first_ppc_cpu->env.gpr[5] = 0; 1626 1627 spapr->cas_reboot = false; 1628 } 1629 1630 static void spapr_create_nvram(sPAPRMachineState *spapr) 1631 { 1632 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1633 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1634 1635 if (dinfo) { 1636 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1637 &error_fatal); 1638 } 1639 1640 qdev_init_nofail(dev); 1641 1642 spapr->nvram = (struct sPAPRNVRAM *)dev; 1643 } 1644 1645 static void spapr_rtc_create(sPAPRMachineState *spapr) 1646 { 1647 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1648 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1649 &error_fatal); 1650 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1651 &error_fatal); 1652 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1653 "date", &error_fatal); 1654 } 1655 1656 /* Returns whether we want to use VGA or not */ 1657 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1658 { 1659 switch (vga_interface_type) { 1660 case VGA_NONE: 1661 return false; 1662 case VGA_DEVICE: 1663 return true; 1664 case VGA_STD: 1665 case VGA_VIRTIO: 1666 return pci_vga_init(pci_bus) != NULL; 1667 default: 1668 error_setg(errp, 1669 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1670 return false; 1671 } 1672 } 1673 1674 static int spapr_pre_load(void *opaque) 1675 { 1676 int rc; 1677 1678 rc = spapr_caps_pre_load(opaque); 1679 if (rc) { 1680 return rc; 1681 } 1682 1683 return 0; 1684 } 1685 1686 static int spapr_post_load(void *opaque, int version_id) 1687 { 1688 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1689 int err = 0; 1690 1691 err = spapr_caps_post_migration(spapr); 1692 if (err) { 1693 return err; 1694 } 1695 1696 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1697 CPUState *cs; 1698 CPU_FOREACH(cs) { 1699 PowerPCCPU *cpu = POWERPC_CPU(cs); 1700 icp_resend(ICP(cpu->intc)); 1701 } 1702 } 1703 1704 /* In earlier versions, there was no separate qdev for the PAPR 1705 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1706 * So when migrating from those versions, poke the incoming offset 1707 * value into the RTC device */ 1708 if (version_id < 3) { 1709 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1710 } 1711 1712 if (kvm_enabled() && spapr->patb_entry) { 1713 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1714 bool radix = !!(spapr->patb_entry & PATBE1_GR); 1715 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1716 1717 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1718 if (err) { 1719 error_report("Process table config unsupported by the host"); 1720 return -EINVAL; 1721 } 1722 } 1723 1724 return err; 1725 } 1726 1727 static int spapr_pre_save(void *opaque) 1728 { 1729 int rc; 1730 1731 rc = spapr_caps_pre_save(opaque); 1732 if (rc) { 1733 return rc; 1734 } 1735 1736 return 0; 1737 } 1738 1739 static bool version_before_3(void *opaque, int version_id) 1740 { 1741 return version_id < 3; 1742 } 1743 1744 static bool spapr_pending_events_needed(void *opaque) 1745 { 1746 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1747 return !QTAILQ_EMPTY(&spapr->pending_events); 1748 } 1749 1750 static const VMStateDescription vmstate_spapr_event_entry = { 1751 .name = "spapr_event_log_entry", 1752 .version_id = 1, 1753 .minimum_version_id = 1, 1754 .fields = (VMStateField[]) { 1755 VMSTATE_UINT32(summary, sPAPREventLogEntry), 1756 VMSTATE_UINT32(extended_length, sPAPREventLogEntry), 1757 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, 1758 NULL, extended_length), 1759 VMSTATE_END_OF_LIST() 1760 }, 1761 }; 1762 1763 static const VMStateDescription vmstate_spapr_pending_events = { 1764 .name = "spapr_pending_events", 1765 .version_id = 1, 1766 .minimum_version_id = 1, 1767 .needed = spapr_pending_events_needed, 1768 .fields = (VMStateField[]) { 1769 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, 1770 vmstate_spapr_event_entry, sPAPREventLogEntry, next), 1771 VMSTATE_END_OF_LIST() 1772 }, 1773 }; 1774 1775 static bool spapr_ov5_cas_needed(void *opaque) 1776 { 1777 sPAPRMachineState *spapr = opaque; 1778 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1779 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1780 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1781 bool cas_needed; 1782 1783 /* Prior to the introduction of sPAPROptionVector, we had two option 1784 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1785 * Both of these options encode machine topology into the device-tree 1786 * in such a way that the now-booted OS should still be able to interact 1787 * appropriately with QEMU regardless of what options were actually 1788 * negotiatied on the source side. 1789 * 1790 * As such, we can avoid migrating the CAS-negotiated options if these 1791 * are the only options available on the current machine/platform. 1792 * Since these are the only options available for pseries-2.7 and 1793 * earlier, this allows us to maintain old->new/new->old migration 1794 * compatibility. 1795 * 1796 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1797 * via default pseries-2.8 machines and explicit command-line parameters. 1798 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1799 * of the actual CAS-negotiated values to continue working properly. For 1800 * example, availability of memory unplug depends on knowing whether 1801 * OV5_HP_EVT was negotiated via CAS. 1802 * 1803 * Thus, for any cases where the set of available CAS-negotiatable 1804 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1805 * include the CAS-negotiated options in the migration stream, unless 1806 * if they affect boot time behaviour only. 1807 */ 1808 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1809 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1810 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1811 1812 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1813 * the mask itself since in the future it's possible "legacy" bits may be 1814 * removed via machine options, which could generate a false positive 1815 * that breaks migration. 1816 */ 1817 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1818 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1819 1820 spapr_ovec_cleanup(ov5_mask); 1821 spapr_ovec_cleanup(ov5_legacy); 1822 spapr_ovec_cleanup(ov5_removed); 1823 1824 return cas_needed; 1825 } 1826 1827 static const VMStateDescription vmstate_spapr_ov5_cas = { 1828 .name = "spapr_option_vector_ov5_cas", 1829 .version_id = 1, 1830 .minimum_version_id = 1, 1831 .needed = spapr_ov5_cas_needed, 1832 .fields = (VMStateField[]) { 1833 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1834 vmstate_spapr_ovec, sPAPROptionVector), 1835 VMSTATE_END_OF_LIST() 1836 }, 1837 }; 1838 1839 static bool spapr_patb_entry_needed(void *opaque) 1840 { 1841 sPAPRMachineState *spapr = opaque; 1842 1843 return !!spapr->patb_entry; 1844 } 1845 1846 static const VMStateDescription vmstate_spapr_patb_entry = { 1847 .name = "spapr_patb_entry", 1848 .version_id = 1, 1849 .minimum_version_id = 1, 1850 .needed = spapr_patb_entry_needed, 1851 .fields = (VMStateField[]) { 1852 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1853 VMSTATE_END_OF_LIST() 1854 }, 1855 }; 1856 1857 static bool spapr_irq_map_needed(void *opaque) 1858 { 1859 sPAPRMachineState *spapr = opaque; 1860 1861 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1862 } 1863 1864 static const VMStateDescription vmstate_spapr_irq_map = { 1865 .name = "spapr_irq_map", 1866 .version_id = 1, 1867 .minimum_version_id = 1, 1868 .needed = spapr_irq_map_needed, 1869 .fields = (VMStateField[]) { 1870 VMSTATE_BITMAP(irq_map, sPAPRMachineState, 0, irq_map_nr), 1871 VMSTATE_END_OF_LIST() 1872 }, 1873 }; 1874 1875 static const VMStateDescription vmstate_spapr = { 1876 .name = "spapr", 1877 .version_id = 3, 1878 .minimum_version_id = 1, 1879 .pre_load = spapr_pre_load, 1880 .post_load = spapr_post_load, 1881 .pre_save = spapr_pre_save, 1882 .fields = (VMStateField[]) { 1883 /* used to be @next_irq */ 1884 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1885 1886 /* RTC offset */ 1887 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1888 1889 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1890 VMSTATE_END_OF_LIST() 1891 }, 1892 .subsections = (const VMStateDescription*[]) { 1893 &vmstate_spapr_ov5_cas, 1894 &vmstate_spapr_patb_entry, 1895 &vmstate_spapr_pending_events, 1896 &vmstate_spapr_cap_htm, 1897 &vmstate_spapr_cap_vsx, 1898 &vmstate_spapr_cap_dfp, 1899 &vmstate_spapr_cap_cfpc, 1900 &vmstate_spapr_cap_sbbc, 1901 &vmstate_spapr_cap_ibs, 1902 &vmstate_spapr_irq_map, 1903 NULL 1904 } 1905 }; 1906 1907 static int htab_save_setup(QEMUFile *f, void *opaque) 1908 { 1909 sPAPRMachineState *spapr = opaque; 1910 1911 /* "Iteration" header */ 1912 if (!spapr->htab_shift) { 1913 qemu_put_be32(f, -1); 1914 } else { 1915 qemu_put_be32(f, spapr->htab_shift); 1916 } 1917 1918 if (spapr->htab) { 1919 spapr->htab_save_index = 0; 1920 spapr->htab_first_pass = true; 1921 } else { 1922 if (spapr->htab_shift) { 1923 assert(kvm_enabled()); 1924 } 1925 } 1926 1927 1928 return 0; 1929 } 1930 1931 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr, 1932 int chunkstart, int n_valid, int n_invalid) 1933 { 1934 qemu_put_be32(f, chunkstart); 1935 qemu_put_be16(f, n_valid); 1936 qemu_put_be16(f, n_invalid); 1937 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1938 HASH_PTE_SIZE_64 * n_valid); 1939 } 1940 1941 static void htab_save_end_marker(QEMUFile *f) 1942 { 1943 qemu_put_be32(f, 0); 1944 qemu_put_be16(f, 0); 1945 qemu_put_be16(f, 0); 1946 } 1947 1948 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1949 int64_t max_ns) 1950 { 1951 bool has_timeout = max_ns != -1; 1952 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1953 int index = spapr->htab_save_index; 1954 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1955 1956 assert(spapr->htab_first_pass); 1957 1958 do { 1959 int chunkstart; 1960 1961 /* Consume invalid HPTEs */ 1962 while ((index < htabslots) 1963 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1964 CLEAN_HPTE(HPTE(spapr->htab, index)); 1965 index++; 1966 } 1967 1968 /* Consume valid HPTEs */ 1969 chunkstart = index; 1970 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1971 && HPTE_VALID(HPTE(spapr->htab, index))) { 1972 CLEAN_HPTE(HPTE(spapr->htab, index)); 1973 index++; 1974 } 1975 1976 if (index > chunkstart) { 1977 int n_valid = index - chunkstart; 1978 1979 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 1980 1981 if (has_timeout && 1982 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1983 break; 1984 } 1985 } 1986 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1987 1988 if (index >= htabslots) { 1989 assert(index == htabslots); 1990 index = 0; 1991 spapr->htab_first_pass = false; 1992 } 1993 spapr->htab_save_index = index; 1994 } 1995 1996 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1997 int64_t max_ns) 1998 { 1999 bool final = max_ns < 0; 2000 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2001 int examined = 0, sent = 0; 2002 int index = spapr->htab_save_index; 2003 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2004 2005 assert(!spapr->htab_first_pass); 2006 2007 do { 2008 int chunkstart, invalidstart; 2009 2010 /* Consume non-dirty HPTEs */ 2011 while ((index < htabslots) 2012 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2013 index++; 2014 examined++; 2015 } 2016 2017 chunkstart = index; 2018 /* Consume valid dirty HPTEs */ 2019 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2020 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2021 && HPTE_VALID(HPTE(spapr->htab, index))) { 2022 CLEAN_HPTE(HPTE(spapr->htab, index)); 2023 index++; 2024 examined++; 2025 } 2026 2027 invalidstart = index; 2028 /* Consume invalid dirty HPTEs */ 2029 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2030 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2031 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2032 CLEAN_HPTE(HPTE(spapr->htab, index)); 2033 index++; 2034 examined++; 2035 } 2036 2037 if (index > chunkstart) { 2038 int n_valid = invalidstart - chunkstart; 2039 int n_invalid = index - invalidstart; 2040 2041 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2042 sent += index - chunkstart; 2043 2044 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2045 break; 2046 } 2047 } 2048 2049 if (examined >= htabslots) { 2050 break; 2051 } 2052 2053 if (index >= htabslots) { 2054 assert(index == htabslots); 2055 index = 0; 2056 } 2057 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2058 2059 if (index >= htabslots) { 2060 assert(index == htabslots); 2061 index = 0; 2062 } 2063 2064 spapr->htab_save_index = index; 2065 2066 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2067 } 2068 2069 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2070 #define MAX_KVM_BUF_SIZE 2048 2071 2072 static int htab_save_iterate(QEMUFile *f, void *opaque) 2073 { 2074 sPAPRMachineState *spapr = opaque; 2075 int fd; 2076 int rc = 0; 2077 2078 /* Iteration header */ 2079 if (!spapr->htab_shift) { 2080 qemu_put_be32(f, -1); 2081 return 1; 2082 } else { 2083 qemu_put_be32(f, 0); 2084 } 2085 2086 if (!spapr->htab) { 2087 assert(kvm_enabled()); 2088 2089 fd = get_htab_fd(spapr); 2090 if (fd < 0) { 2091 return fd; 2092 } 2093 2094 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2095 if (rc < 0) { 2096 return rc; 2097 } 2098 } else if (spapr->htab_first_pass) { 2099 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2100 } else { 2101 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2102 } 2103 2104 htab_save_end_marker(f); 2105 2106 return rc; 2107 } 2108 2109 static int htab_save_complete(QEMUFile *f, void *opaque) 2110 { 2111 sPAPRMachineState *spapr = opaque; 2112 int fd; 2113 2114 /* Iteration header */ 2115 if (!spapr->htab_shift) { 2116 qemu_put_be32(f, -1); 2117 return 0; 2118 } else { 2119 qemu_put_be32(f, 0); 2120 } 2121 2122 if (!spapr->htab) { 2123 int rc; 2124 2125 assert(kvm_enabled()); 2126 2127 fd = get_htab_fd(spapr); 2128 if (fd < 0) { 2129 return fd; 2130 } 2131 2132 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2133 if (rc < 0) { 2134 return rc; 2135 } 2136 } else { 2137 if (spapr->htab_first_pass) { 2138 htab_save_first_pass(f, spapr, -1); 2139 } 2140 htab_save_later_pass(f, spapr, -1); 2141 } 2142 2143 /* End marker */ 2144 htab_save_end_marker(f); 2145 2146 return 0; 2147 } 2148 2149 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2150 { 2151 sPAPRMachineState *spapr = opaque; 2152 uint32_t section_hdr; 2153 int fd = -1; 2154 Error *local_err = NULL; 2155 2156 if (version_id < 1 || version_id > 1) { 2157 error_report("htab_load() bad version"); 2158 return -EINVAL; 2159 } 2160 2161 section_hdr = qemu_get_be32(f); 2162 2163 if (section_hdr == -1) { 2164 spapr_free_hpt(spapr); 2165 return 0; 2166 } 2167 2168 if (section_hdr) { 2169 /* First section gives the htab size */ 2170 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2171 if (local_err) { 2172 error_report_err(local_err); 2173 return -EINVAL; 2174 } 2175 return 0; 2176 } 2177 2178 if (!spapr->htab) { 2179 assert(kvm_enabled()); 2180 2181 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2182 if (fd < 0) { 2183 error_report_err(local_err); 2184 return fd; 2185 } 2186 } 2187 2188 while (true) { 2189 uint32_t index; 2190 uint16_t n_valid, n_invalid; 2191 2192 index = qemu_get_be32(f); 2193 n_valid = qemu_get_be16(f); 2194 n_invalid = qemu_get_be16(f); 2195 2196 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2197 /* End of Stream */ 2198 break; 2199 } 2200 2201 if ((index + n_valid + n_invalid) > 2202 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2203 /* Bad index in stream */ 2204 error_report( 2205 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2206 index, n_valid, n_invalid, spapr->htab_shift); 2207 return -EINVAL; 2208 } 2209 2210 if (spapr->htab) { 2211 if (n_valid) { 2212 qemu_get_buffer(f, HPTE(spapr->htab, index), 2213 HASH_PTE_SIZE_64 * n_valid); 2214 } 2215 if (n_invalid) { 2216 memset(HPTE(spapr->htab, index + n_valid), 0, 2217 HASH_PTE_SIZE_64 * n_invalid); 2218 } 2219 } else { 2220 int rc; 2221 2222 assert(fd >= 0); 2223 2224 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2225 if (rc < 0) { 2226 return rc; 2227 } 2228 } 2229 } 2230 2231 if (!spapr->htab) { 2232 assert(fd >= 0); 2233 close(fd); 2234 } 2235 2236 return 0; 2237 } 2238 2239 static void htab_save_cleanup(void *opaque) 2240 { 2241 sPAPRMachineState *spapr = opaque; 2242 2243 close_htab_fd(spapr); 2244 } 2245 2246 static SaveVMHandlers savevm_htab_handlers = { 2247 .save_setup = htab_save_setup, 2248 .save_live_iterate = htab_save_iterate, 2249 .save_live_complete_precopy = htab_save_complete, 2250 .save_cleanup = htab_save_cleanup, 2251 .load_state = htab_load, 2252 }; 2253 2254 static void spapr_boot_set(void *opaque, const char *boot_device, 2255 Error **errp) 2256 { 2257 MachineState *machine = MACHINE(opaque); 2258 machine->boot_order = g_strdup(boot_device); 2259 } 2260 2261 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 2262 { 2263 MachineState *machine = MACHINE(spapr); 2264 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2265 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2266 int i; 2267 2268 for (i = 0; i < nr_lmbs; i++) { 2269 uint64_t addr; 2270 2271 addr = i * lmb_size + machine->device_memory->base; 2272 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2273 addr / lmb_size); 2274 } 2275 } 2276 2277 /* 2278 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2279 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2280 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2281 */ 2282 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2283 { 2284 int i; 2285 2286 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2287 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2288 " is not aligned to %" PRIu64 " MiB", 2289 machine->ram_size, 2290 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2291 return; 2292 } 2293 2294 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2295 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2296 " is not aligned to %" PRIu64 " MiB", 2297 machine->ram_size, 2298 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2299 return; 2300 } 2301 2302 for (i = 0; i < nb_numa_nodes; i++) { 2303 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2304 error_setg(errp, 2305 "Node %d memory size 0x%" PRIx64 2306 " is not aligned to %" PRIu64 " MiB", 2307 i, numa_info[i].node_mem, 2308 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2309 return; 2310 } 2311 } 2312 } 2313 2314 /* find cpu slot in machine->possible_cpus by core_id */ 2315 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2316 { 2317 int index = id / smp_threads; 2318 2319 if (index >= ms->possible_cpus->len) { 2320 return NULL; 2321 } 2322 if (idx) { 2323 *idx = index; 2324 } 2325 return &ms->possible_cpus->cpus[index]; 2326 } 2327 2328 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) 2329 { 2330 Error *local_err = NULL; 2331 bool vsmt_user = !!spapr->vsmt; 2332 int kvm_smt = kvmppc_smt_threads(); 2333 int ret; 2334 2335 if (!kvm_enabled() && (smp_threads > 1)) { 2336 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2337 "on a pseries machine"); 2338 goto out; 2339 } 2340 if (!is_power_of_2(smp_threads)) { 2341 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2342 "machine because it must be a power of 2", smp_threads); 2343 goto out; 2344 } 2345 2346 /* Detemine the VSMT mode to use: */ 2347 if (vsmt_user) { 2348 if (spapr->vsmt < smp_threads) { 2349 error_setg(&local_err, "Cannot support VSMT mode %d" 2350 " because it must be >= threads/core (%d)", 2351 spapr->vsmt, smp_threads); 2352 goto out; 2353 } 2354 /* In this case, spapr->vsmt has been set by the command line */ 2355 } else { 2356 /* 2357 * Default VSMT value is tricky, because we need it to be as 2358 * consistent as possible (for migration), but this requires 2359 * changing it for at least some existing cases. We pick 8 as 2360 * the value that we'd get with KVM on POWER8, the 2361 * overwhelmingly common case in production systems. 2362 */ 2363 spapr->vsmt = MAX(8, smp_threads); 2364 } 2365 2366 /* KVM: If necessary, set the SMT mode: */ 2367 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2368 ret = kvmppc_set_smt_threads(spapr->vsmt); 2369 if (ret) { 2370 /* Looks like KVM isn't able to change VSMT mode */ 2371 error_setg(&local_err, 2372 "Failed to set KVM's VSMT mode to %d (errno %d)", 2373 spapr->vsmt, ret); 2374 /* We can live with that if the default one is big enough 2375 * for the number of threads, and a submultiple of the one 2376 * we want. In this case we'll waste some vcpu ids, but 2377 * behaviour will be correct */ 2378 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2379 warn_report_err(local_err); 2380 local_err = NULL; 2381 goto out; 2382 } else { 2383 if (!vsmt_user) { 2384 error_append_hint(&local_err, 2385 "On PPC, a VM with %d threads/core" 2386 " on a host with %d threads/core" 2387 " requires the use of VSMT mode %d.\n", 2388 smp_threads, kvm_smt, spapr->vsmt); 2389 } 2390 kvmppc_hint_smt_possible(&local_err); 2391 goto out; 2392 } 2393 } 2394 } 2395 /* else TCG: nothing to do currently */ 2396 out: 2397 error_propagate(errp, local_err); 2398 } 2399 2400 static void spapr_init_cpus(sPAPRMachineState *spapr) 2401 { 2402 MachineState *machine = MACHINE(spapr); 2403 MachineClass *mc = MACHINE_GET_CLASS(machine); 2404 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2405 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2406 const CPUArchIdList *possible_cpus; 2407 int boot_cores_nr = smp_cpus / smp_threads; 2408 int i; 2409 2410 possible_cpus = mc->possible_cpu_arch_ids(machine); 2411 if (mc->has_hotpluggable_cpus) { 2412 if (smp_cpus % smp_threads) { 2413 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2414 smp_cpus, smp_threads); 2415 exit(1); 2416 } 2417 if (max_cpus % smp_threads) { 2418 error_report("max_cpus (%u) must be multiple of threads (%u)", 2419 max_cpus, smp_threads); 2420 exit(1); 2421 } 2422 } else { 2423 if (max_cpus != smp_cpus) { 2424 error_report("This machine version does not support CPU hotplug"); 2425 exit(1); 2426 } 2427 boot_cores_nr = possible_cpus->len; 2428 } 2429 2430 /* VSMT must be set in order to be able to compute VCPU ids, ie to 2431 * call xics_max_server_number() or spapr_vcpu_id(). 2432 */ 2433 spapr_set_vsmt_mode(spapr, &error_fatal); 2434 2435 if (smc->pre_2_10_has_unused_icps) { 2436 int i; 2437 2438 for (i = 0; i < xics_max_server_number(spapr); i++) { 2439 /* Dummy entries get deregistered when real ICPState objects 2440 * are registered during CPU core hotplug. 2441 */ 2442 pre_2_10_vmstate_register_dummy_icp(i); 2443 } 2444 } 2445 2446 for (i = 0; i < possible_cpus->len; i++) { 2447 int core_id = i * smp_threads; 2448 2449 if (mc->has_hotpluggable_cpus) { 2450 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2451 spapr_vcpu_id(spapr, core_id)); 2452 } 2453 2454 if (i < boot_cores_nr) { 2455 Object *core = object_new(type); 2456 int nr_threads = smp_threads; 2457 2458 /* Handle the partially filled core for older machine types */ 2459 if ((i + 1) * smp_threads >= smp_cpus) { 2460 nr_threads = smp_cpus - i * smp_threads; 2461 } 2462 2463 object_property_set_int(core, nr_threads, "nr-threads", 2464 &error_fatal); 2465 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2466 &error_fatal); 2467 object_property_set_bool(core, true, "realized", &error_fatal); 2468 } 2469 } 2470 } 2471 2472 /* pSeries LPAR / sPAPR hardware init */ 2473 static void spapr_machine_init(MachineState *machine) 2474 { 2475 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2476 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2477 const char *kernel_filename = machine->kernel_filename; 2478 const char *initrd_filename = machine->initrd_filename; 2479 PCIHostState *phb; 2480 int i; 2481 MemoryRegion *sysmem = get_system_memory(); 2482 MemoryRegion *ram = g_new(MemoryRegion, 1); 2483 hwaddr node0_size = spapr_node0_size(machine); 2484 long load_limit, fw_size; 2485 char *filename; 2486 Error *resize_hpt_err = NULL; 2487 2488 msi_nonbroken = true; 2489 2490 QLIST_INIT(&spapr->phbs); 2491 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2492 2493 /* Determine capabilities to run with */ 2494 spapr_caps_init(spapr); 2495 2496 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2497 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2498 /* 2499 * If the user explicitly requested a mode we should either 2500 * supply it, or fail completely (which we do below). But if 2501 * it's not set explicitly, we reset our mode to something 2502 * that works 2503 */ 2504 if (resize_hpt_err) { 2505 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2506 error_free(resize_hpt_err); 2507 resize_hpt_err = NULL; 2508 } else { 2509 spapr->resize_hpt = smc->resize_hpt_default; 2510 } 2511 } 2512 2513 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2514 2515 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2516 /* 2517 * User requested HPT resize, but this host can't supply it. Bail out 2518 */ 2519 error_report_err(resize_hpt_err); 2520 exit(1); 2521 } 2522 2523 spapr->rma_size = node0_size; 2524 2525 /* With KVM, we don't actually know whether KVM supports an 2526 * unbounded RMA (PR KVM) or is limited by the hash table size 2527 * (HV KVM using VRMA), so we always assume the latter 2528 * 2529 * In that case, we also limit the initial allocations for RTAS 2530 * etc... to 256M since we have no way to know what the VRMA size 2531 * is going to be as it depends on the size of the hash table 2532 * which isn't determined yet. 2533 */ 2534 if (kvm_enabled()) { 2535 spapr->vrma_adjust = 1; 2536 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2537 } 2538 2539 /* Actually we don't support unbounded RMA anymore since we added 2540 * proper emulation of HV mode. The max we can get is 16G which 2541 * also happens to be what we configure for PAPR mode so make sure 2542 * we don't do anything bigger than that 2543 */ 2544 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2545 2546 if (spapr->rma_size > node0_size) { 2547 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2548 spapr->rma_size); 2549 exit(1); 2550 } 2551 2552 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2553 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2554 2555 /* Set up Interrupt Controller before we create the VCPUs */ 2556 smc->irq->init(spapr, &error_fatal); 2557 2558 /* Set up containers for ibm,client-architecture-support negotiated options 2559 */ 2560 spapr->ov5 = spapr_ovec_new(); 2561 spapr->ov5_cas = spapr_ovec_new(); 2562 2563 if (smc->dr_lmb_enabled) { 2564 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2565 spapr_validate_node_memory(machine, &error_fatal); 2566 } 2567 2568 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2569 2570 /* advertise support for dedicated HP event source to guests */ 2571 if (spapr->use_hotplug_event_source) { 2572 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2573 } 2574 2575 /* advertise support for HPT resizing */ 2576 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2577 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2578 } 2579 2580 /* advertise support for ibm,dyamic-memory-v2 */ 2581 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2582 2583 /* init CPUs */ 2584 spapr_init_cpus(spapr); 2585 2586 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2587 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2588 spapr->max_compat_pvr)) { 2589 /* KVM and TCG always allow GTSE with radix... */ 2590 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2591 } 2592 /* ... but not with hash (currently). */ 2593 2594 if (kvm_enabled()) { 2595 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2596 kvmppc_enable_logical_ci_hcalls(); 2597 kvmppc_enable_set_mode_hcall(); 2598 2599 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2600 kvmppc_enable_clear_ref_mod_hcalls(); 2601 } 2602 2603 /* allocate RAM */ 2604 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2605 machine->ram_size); 2606 memory_region_add_subregion(sysmem, 0, ram); 2607 2608 /* always allocate the device memory information */ 2609 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2610 2611 /* initialize hotplug memory address space */ 2612 if (machine->ram_size < machine->maxram_size) { 2613 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2614 /* 2615 * Limit the number of hotpluggable memory slots to half the number 2616 * slots that KVM supports, leaving the other half for PCI and other 2617 * devices. However ensure that number of slots doesn't drop below 32. 2618 */ 2619 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2620 SPAPR_MAX_RAM_SLOTS; 2621 2622 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2623 max_memslots = SPAPR_MAX_RAM_SLOTS; 2624 } 2625 if (machine->ram_slots > max_memslots) { 2626 error_report("Specified number of memory slots %" 2627 PRIu64" exceeds max supported %d", 2628 machine->ram_slots, max_memslots); 2629 exit(1); 2630 } 2631 2632 machine->device_memory->base = ROUND_UP(machine->ram_size, 2633 SPAPR_DEVICE_MEM_ALIGN); 2634 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2635 "device-memory", device_mem_size); 2636 memory_region_add_subregion(sysmem, machine->device_memory->base, 2637 &machine->device_memory->mr); 2638 } 2639 2640 if (smc->dr_lmb_enabled) { 2641 spapr_create_lmb_dr_connectors(spapr); 2642 } 2643 2644 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2645 if (!filename) { 2646 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2647 exit(1); 2648 } 2649 spapr->rtas_size = get_image_size(filename); 2650 if (spapr->rtas_size < 0) { 2651 error_report("Could not get size of LPAR rtas '%s'", filename); 2652 exit(1); 2653 } 2654 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2655 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2656 error_report("Could not load LPAR rtas '%s'", filename); 2657 exit(1); 2658 } 2659 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2660 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2661 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2662 exit(1); 2663 } 2664 g_free(filename); 2665 2666 /* Set up RTAS event infrastructure */ 2667 spapr_events_init(spapr); 2668 2669 /* Set up the RTC RTAS interfaces */ 2670 spapr_rtc_create(spapr); 2671 2672 /* Set up VIO bus */ 2673 spapr->vio_bus = spapr_vio_bus_init(); 2674 2675 for (i = 0; i < serial_max_hds(); i++) { 2676 if (serial_hd(i)) { 2677 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2678 } 2679 } 2680 2681 /* We always have at least the nvram device on VIO */ 2682 spapr_create_nvram(spapr); 2683 2684 /* Set up PCI */ 2685 spapr_pci_rtas_init(); 2686 2687 phb = spapr_create_phb(spapr, 0); 2688 2689 for (i = 0; i < nb_nics; i++) { 2690 NICInfo *nd = &nd_table[i]; 2691 2692 if (!nd->model) { 2693 nd->model = g_strdup("spapr-vlan"); 2694 } 2695 2696 if (g_str_equal(nd->model, "spapr-vlan") || 2697 g_str_equal(nd->model, "ibmveth")) { 2698 spapr_vlan_create(spapr->vio_bus, nd); 2699 } else { 2700 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2701 } 2702 } 2703 2704 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2705 spapr_vscsi_create(spapr->vio_bus); 2706 } 2707 2708 /* Graphics */ 2709 if (spapr_vga_init(phb->bus, &error_fatal)) { 2710 spapr->has_graphics = true; 2711 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2712 } 2713 2714 if (machine->usb) { 2715 if (smc->use_ohci_by_default) { 2716 pci_create_simple(phb->bus, -1, "pci-ohci"); 2717 } else { 2718 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2719 } 2720 2721 if (spapr->has_graphics) { 2722 USBBus *usb_bus = usb_bus_find(-1); 2723 2724 usb_create_simple(usb_bus, "usb-kbd"); 2725 usb_create_simple(usb_bus, "usb-mouse"); 2726 } 2727 } 2728 2729 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) { 2730 error_report( 2731 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2732 MIN_RMA_SLOF); 2733 exit(1); 2734 } 2735 2736 if (kernel_filename) { 2737 uint64_t lowaddr = 0; 2738 2739 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2740 NULL, NULL, &lowaddr, NULL, 1, 2741 PPC_ELF_MACHINE, 0, 0); 2742 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2743 spapr->kernel_size = load_elf(kernel_filename, 2744 translate_kernel_address, NULL, NULL, 2745 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2746 0, 0); 2747 spapr->kernel_le = spapr->kernel_size > 0; 2748 } 2749 if (spapr->kernel_size < 0) { 2750 error_report("error loading %s: %s", kernel_filename, 2751 load_elf_strerror(spapr->kernel_size)); 2752 exit(1); 2753 } 2754 2755 /* load initrd */ 2756 if (initrd_filename) { 2757 /* Try to locate the initrd in the gap between the kernel 2758 * and the firmware. Add a bit of space just in case 2759 */ 2760 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2761 + 0x1ffff) & ~0xffff; 2762 spapr->initrd_size = load_image_targphys(initrd_filename, 2763 spapr->initrd_base, 2764 load_limit 2765 - spapr->initrd_base); 2766 if (spapr->initrd_size < 0) { 2767 error_report("could not load initial ram disk '%s'", 2768 initrd_filename); 2769 exit(1); 2770 } 2771 } 2772 } 2773 2774 if (bios_name == NULL) { 2775 bios_name = FW_FILE_NAME; 2776 } 2777 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2778 if (!filename) { 2779 error_report("Could not find LPAR firmware '%s'", bios_name); 2780 exit(1); 2781 } 2782 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2783 if (fw_size <= 0) { 2784 error_report("Could not load LPAR firmware '%s'", filename); 2785 exit(1); 2786 } 2787 g_free(filename); 2788 2789 /* FIXME: Should register things through the MachineState's qdev 2790 * interface, this is a legacy from the sPAPREnvironment structure 2791 * which predated MachineState but had a similar function */ 2792 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2793 register_savevm_live(NULL, "spapr/htab", -1, 1, 2794 &savevm_htab_handlers, spapr); 2795 2796 qemu_register_boot_set(spapr_boot_set, spapr); 2797 2798 if (kvm_enabled()) { 2799 /* to stop and start vmclock */ 2800 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2801 &spapr->tb); 2802 2803 kvmppc_spapr_enable_inkernel_multitce(); 2804 } 2805 } 2806 2807 static int spapr_kvm_type(const char *vm_type) 2808 { 2809 if (!vm_type) { 2810 return 0; 2811 } 2812 2813 if (!strcmp(vm_type, "HV")) { 2814 return 1; 2815 } 2816 2817 if (!strcmp(vm_type, "PR")) { 2818 return 2; 2819 } 2820 2821 error_report("Unknown kvm-type specified '%s'", vm_type); 2822 exit(1); 2823 } 2824 2825 /* 2826 * Implementation of an interface to adjust firmware path 2827 * for the bootindex property handling. 2828 */ 2829 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2830 DeviceState *dev) 2831 { 2832 #define CAST(type, obj, name) \ 2833 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2834 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2835 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2836 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 2837 2838 if (d) { 2839 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2840 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2841 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2842 2843 if (spapr) { 2844 /* 2845 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2846 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2847 * in the top 16 bits of the 64-bit LUN 2848 */ 2849 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2850 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2851 (uint64_t)id << 48); 2852 } else if (virtio) { 2853 /* 2854 * We use SRP luns of the form 01000000 | (target << 8) | lun 2855 * in the top 32 bits of the 64-bit LUN 2856 * Note: the quote above is from SLOF and it is wrong, 2857 * the actual binding is: 2858 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2859 */ 2860 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2861 if (d->lun >= 256) { 2862 /* Use the LUN "flat space addressing method" */ 2863 id |= 0x4000; 2864 } 2865 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2866 (uint64_t)id << 32); 2867 } else if (usb) { 2868 /* 2869 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2870 * in the top 32 bits of the 64-bit LUN 2871 */ 2872 unsigned usb_port = atoi(usb->port->path); 2873 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2874 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2875 (uint64_t)id << 32); 2876 } 2877 } 2878 2879 /* 2880 * SLOF probes the USB devices, and if it recognizes that the device is a 2881 * storage device, it changes its name to "storage" instead of "usb-host", 2882 * and additionally adds a child node for the SCSI LUN, so the correct 2883 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2884 */ 2885 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2886 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2887 if (usb_host_dev_is_scsi_storage(usbdev)) { 2888 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2889 } 2890 } 2891 2892 if (phb) { 2893 /* Replace "pci" with "pci@800000020000000" */ 2894 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2895 } 2896 2897 if (vsc) { 2898 /* Same logic as virtio above */ 2899 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 2900 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 2901 } 2902 2903 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 2904 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 2905 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 2906 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 2907 } 2908 2909 return NULL; 2910 } 2911 2912 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2913 { 2914 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2915 2916 return g_strdup(spapr->kvm_type); 2917 } 2918 2919 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2920 { 2921 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2922 2923 g_free(spapr->kvm_type); 2924 spapr->kvm_type = g_strdup(value); 2925 } 2926 2927 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2928 { 2929 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2930 2931 return spapr->use_hotplug_event_source; 2932 } 2933 2934 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2935 Error **errp) 2936 { 2937 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2938 2939 spapr->use_hotplug_event_source = value; 2940 } 2941 2942 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 2943 { 2944 return true; 2945 } 2946 2947 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 2948 { 2949 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2950 2951 switch (spapr->resize_hpt) { 2952 case SPAPR_RESIZE_HPT_DEFAULT: 2953 return g_strdup("default"); 2954 case SPAPR_RESIZE_HPT_DISABLED: 2955 return g_strdup("disabled"); 2956 case SPAPR_RESIZE_HPT_ENABLED: 2957 return g_strdup("enabled"); 2958 case SPAPR_RESIZE_HPT_REQUIRED: 2959 return g_strdup("required"); 2960 } 2961 g_assert_not_reached(); 2962 } 2963 2964 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 2965 { 2966 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2967 2968 if (strcmp(value, "default") == 0) { 2969 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 2970 } else if (strcmp(value, "disabled") == 0) { 2971 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2972 } else if (strcmp(value, "enabled") == 0) { 2973 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 2974 } else if (strcmp(value, "required") == 0) { 2975 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 2976 } else { 2977 error_setg(errp, "Bad value for \"resize-hpt\" property"); 2978 } 2979 } 2980 2981 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 2982 void *opaque, Error **errp) 2983 { 2984 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 2985 } 2986 2987 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 2988 void *opaque, Error **errp) 2989 { 2990 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 2991 } 2992 2993 static void spapr_instance_init(Object *obj) 2994 { 2995 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2996 2997 spapr->htab_fd = -1; 2998 spapr->use_hotplug_event_source = true; 2999 object_property_add_str(obj, "kvm-type", 3000 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3001 object_property_set_description(obj, "kvm-type", 3002 "Specifies the KVM virtualization mode (HV, PR)", 3003 NULL); 3004 object_property_add_bool(obj, "modern-hotplug-events", 3005 spapr_get_modern_hotplug_events, 3006 spapr_set_modern_hotplug_events, 3007 NULL); 3008 object_property_set_description(obj, "modern-hotplug-events", 3009 "Use dedicated hotplug event mechanism in" 3010 " place of standard EPOW events when possible" 3011 " (required for memory hot-unplug support)", 3012 NULL); 3013 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3014 "Maximum permitted CPU compatibility mode", 3015 &error_fatal); 3016 3017 object_property_add_str(obj, "resize-hpt", 3018 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3019 object_property_set_description(obj, "resize-hpt", 3020 "Resizing of the Hash Page Table (enabled, disabled, required)", 3021 NULL); 3022 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3023 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3024 object_property_set_description(obj, "vsmt", 3025 "Virtual SMT: KVM behaves as if this were" 3026 " the host's SMT mode", &error_abort); 3027 object_property_add_bool(obj, "vfio-no-msix-emulation", 3028 spapr_get_msix_emulation, NULL, NULL); 3029 } 3030 3031 static void spapr_machine_finalizefn(Object *obj) 3032 { 3033 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3034 3035 g_free(spapr->kvm_type); 3036 } 3037 3038 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3039 { 3040 cpu_synchronize_state(cs); 3041 ppc_cpu_do_system_reset(cs); 3042 } 3043 3044 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3045 { 3046 CPUState *cs; 3047 3048 CPU_FOREACH(cs) { 3049 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3050 } 3051 } 3052 3053 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3054 uint32_t node, bool dedicated_hp_event_source, 3055 Error **errp) 3056 { 3057 sPAPRDRConnector *drc; 3058 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3059 int i, fdt_offset, fdt_size; 3060 void *fdt; 3061 uint64_t addr = addr_start; 3062 bool hotplugged = spapr_drc_hotplugged(dev); 3063 Error *local_err = NULL; 3064 3065 for (i = 0; i < nr_lmbs; i++) { 3066 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3067 addr / SPAPR_MEMORY_BLOCK_SIZE); 3068 g_assert(drc); 3069 3070 fdt = create_device_tree(&fdt_size); 3071 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 3072 SPAPR_MEMORY_BLOCK_SIZE); 3073 3074 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3075 if (local_err) { 3076 while (addr > addr_start) { 3077 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3078 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3079 addr / SPAPR_MEMORY_BLOCK_SIZE); 3080 spapr_drc_detach(drc); 3081 } 3082 g_free(fdt); 3083 error_propagate(errp, local_err); 3084 return; 3085 } 3086 if (!hotplugged) { 3087 spapr_drc_reset(drc); 3088 } 3089 addr += SPAPR_MEMORY_BLOCK_SIZE; 3090 } 3091 /* send hotplug notification to the 3092 * guest only in case of hotplugged memory 3093 */ 3094 if (hotplugged) { 3095 if (dedicated_hp_event_source) { 3096 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3097 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3098 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3099 nr_lmbs, 3100 spapr_drc_index(drc)); 3101 } else { 3102 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3103 nr_lmbs); 3104 } 3105 } 3106 } 3107 3108 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3109 Error **errp) 3110 { 3111 Error *local_err = NULL; 3112 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3113 PCDIMMDevice *dimm = PC_DIMM(dev); 3114 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3115 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3116 uint64_t align, size, addr; 3117 uint32_t node; 3118 3119 align = memory_region_get_alignment(mr); 3120 size = memory_region_size(mr); 3121 3122 pc_dimm_plug(dev, MACHINE(ms), align, &local_err); 3123 if (local_err) { 3124 goto out; 3125 } 3126 3127 addr = object_property_get_uint(OBJECT(dimm), 3128 PC_DIMM_ADDR_PROP, &local_err); 3129 if (local_err) { 3130 goto out_unplug; 3131 } 3132 3133 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, 3134 &error_abort); 3135 spapr_add_lmbs(dev, addr, size, node, 3136 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3137 &local_err); 3138 if (local_err) { 3139 goto out_unplug; 3140 } 3141 3142 return; 3143 3144 out_unplug: 3145 pc_dimm_unplug(dev, MACHINE(ms)); 3146 out: 3147 error_propagate(errp, local_err); 3148 } 3149 3150 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3151 Error **errp) 3152 { 3153 const sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3154 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3155 PCDIMMDevice *dimm = PC_DIMM(dev); 3156 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3157 MemoryRegion *mr; 3158 uint64_t size; 3159 Object *memdev; 3160 hwaddr pagesize; 3161 3162 if (!smc->dr_lmb_enabled) { 3163 error_setg(errp, "Memory hotplug not supported for this machine"); 3164 return; 3165 } 3166 3167 mr = ddc->get_memory_region(dimm, errp); 3168 if (!mr) { 3169 return; 3170 } 3171 size = memory_region_size(mr); 3172 3173 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3174 error_setg(errp, "Hotplugged memory size must be a multiple of " 3175 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3176 return; 3177 } 3178 3179 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3180 &error_abort); 3181 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3182 spapr_check_pagesize(spapr, pagesize, errp); 3183 } 3184 3185 struct sPAPRDIMMState { 3186 PCDIMMDevice *dimm; 3187 uint32_t nr_lmbs; 3188 QTAILQ_ENTRY(sPAPRDIMMState) next; 3189 }; 3190 3191 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 3192 PCDIMMDevice *dimm) 3193 { 3194 sPAPRDIMMState *dimm_state = NULL; 3195 3196 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3197 if (dimm_state->dimm == dimm) { 3198 break; 3199 } 3200 } 3201 return dimm_state; 3202 } 3203 3204 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 3205 uint32_t nr_lmbs, 3206 PCDIMMDevice *dimm) 3207 { 3208 sPAPRDIMMState *ds = NULL; 3209 3210 /* 3211 * If this request is for a DIMM whose removal had failed earlier 3212 * (due to guest's refusal to remove the LMBs), we would have this 3213 * dimm already in the pending_dimm_unplugs list. In that 3214 * case don't add again. 3215 */ 3216 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3217 if (!ds) { 3218 ds = g_malloc0(sizeof(sPAPRDIMMState)); 3219 ds->nr_lmbs = nr_lmbs; 3220 ds->dimm = dimm; 3221 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3222 } 3223 return ds; 3224 } 3225 3226 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 3227 sPAPRDIMMState *dimm_state) 3228 { 3229 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3230 g_free(dimm_state); 3231 } 3232 3233 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 3234 PCDIMMDevice *dimm) 3235 { 3236 sPAPRDRConnector *drc; 3237 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3238 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3239 uint64_t size = memory_region_size(mr); 3240 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3241 uint32_t avail_lmbs = 0; 3242 uint64_t addr_start, addr; 3243 int i; 3244 3245 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3246 &error_abort); 3247 3248 addr = addr_start; 3249 for (i = 0; i < nr_lmbs; i++) { 3250 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3251 addr / SPAPR_MEMORY_BLOCK_SIZE); 3252 g_assert(drc); 3253 if (drc->dev) { 3254 avail_lmbs++; 3255 } 3256 addr += SPAPR_MEMORY_BLOCK_SIZE; 3257 } 3258 3259 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3260 } 3261 3262 /* Callback to be called during DRC release. */ 3263 void spapr_lmb_release(DeviceState *dev) 3264 { 3265 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3266 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3267 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3268 3269 /* This information will get lost if a migration occurs 3270 * during the unplug process. In this case recover it. */ 3271 if (ds == NULL) { 3272 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3273 g_assert(ds); 3274 /* The DRC being examined by the caller at least must be counted */ 3275 g_assert(ds->nr_lmbs); 3276 } 3277 3278 if (--ds->nr_lmbs) { 3279 return; 3280 } 3281 3282 /* 3283 * Now that all the LMBs have been removed by the guest, call the 3284 * unplug handler chain. This can never fail. 3285 */ 3286 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3287 } 3288 3289 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3290 { 3291 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3292 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3293 3294 pc_dimm_unplug(dev, MACHINE(hotplug_dev)); 3295 object_unparent(OBJECT(dev)); 3296 spapr_pending_dimm_unplugs_remove(spapr, ds); 3297 } 3298 3299 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3300 DeviceState *dev, Error **errp) 3301 { 3302 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3303 Error *local_err = NULL; 3304 PCDIMMDevice *dimm = PC_DIMM(dev); 3305 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3306 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3307 uint32_t nr_lmbs; 3308 uint64_t size, addr_start, addr; 3309 int i; 3310 sPAPRDRConnector *drc; 3311 3312 size = memory_region_size(mr); 3313 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3314 3315 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3316 &local_err); 3317 if (local_err) { 3318 goto out; 3319 } 3320 3321 /* 3322 * An existing pending dimm state for this DIMM means that there is an 3323 * unplug operation in progress, waiting for the spapr_lmb_release 3324 * callback to complete the job (BQL can't cover that far). In this case, 3325 * bail out to avoid detaching DRCs that were already released. 3326 */ 3327 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3328 error_setg(&local_err, 3329 "Memory unplug already in progress for device %s", 3330 dev->id); 3331 goto out; 3332 } 3333 3334 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3335 3336 addr = addr_start; 3337 for (i = 0; i < nr_lmbs; i++) { 3338 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3339 addr / SPAPR_MEMORY_BLOCK_SIZE); 3340 g_assert(drc); 3341 3342 spapr_drc_detach(drc); 3343 addr += SPAPR_MEMORY_BLOCK_SIZE; 3344 } 3345 3346 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3347 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3348 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3349 nr_lmbs, spapr_drc_index(drc)); 3350 out: 3351 error_propagate(errp, local_err); 3352 } 3353 3354 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 3355 sPAPRMachineState *spapr) 3356 { 3357 PowerPCCPU *cpu = POWERPC_CPU(cs); 3358 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3359 int id = spapr_get_vcpu_id(cpu); 3360 void *fdt; 3361 int offset, fdt_size; 3362 char *nodename; 3363 3364 fdt = create_device_tree(&fdt_size); 3365 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3366 offset = fdt_add_subnode(fdt, 0, nodename); 3367 3368 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3369 g_free(nodename); 3370 3371 *fdt_offset = offset; 3372 return fdt; 3373 } 3374 3375 /* Callback to be called during DRC release. */ 3376 void spapr_core_release(DeviceState *dev) 3377 { 3378 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3379 3380 /* Call the unplug handler chain. This can never fail. */ 3381 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3382 } 3383 3384 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3385 { 3386 MachineState *ms = MACHINE(hotplug_dev); 3387 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3388 CPUCore *cc = CPU_CORE(dev); 3389 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3390 3391 if (smc->pre_2_10_has_unused_icps) { 3392 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3393 int i; 3394 3395 for (i = 0; i < cc->nr_threads; i++) { 3396 CPUState *cs = CPU(sc->threads[i]); 3397 3398 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3399 } 3400 } 3401 3402 assert(core_slot); 3403 core_slot->cpu = NULL; 3404 object_unparent(OBJECT(dev)); 3405 } 3406 3407 static 3408 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3409 Error **errp) 3410 { 3411 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3412 int index; 3413 sPAPRDRConnector *drc; 3414 CPUCore *cc = CPU_CORE(dev); 3415 3416 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3417 error_setg(errp, "Unable to find CPU core with core-id: %d", 3418 cc->core_id); 3419 return; 3420 } 3421 if (index == 0) { 3422 error_setg(errp, "Boot CPU core may not be unplugged"); 3423 return; 3424 } 3425 3426 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3427 spapr_vcpu_id(spapr, cc->core_id)); 3428 g_assert(drc); 3429 3430 spapr_drc_detach(drc); 3431 3432 spapr_hotplug_req_remove_by_index(drc); 3433 } 3434 3435 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3436 Error **errp) 3437 { 3438 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3439 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3440 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3441 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3442 CPUCore *cc = CPU_CORE(dev); 3443 CPUState *cs = CPU(core->threads[0]); 3444 sPAPRDRConnector *drc; 3445 Error *local_err = NULL; 3446 CPUArchId *core_slot; 3447 int index; 3448 bool hotplugged = spapr_drc_hotplugged(dev); 3449 3450 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3451 if (!core_slot) { 3452 error_setg(errp, "Unable to find CPU core with core-id: %d", 3453 cc->core_id); 3454 return; 3455 } 3456 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3457 spapr_vcpu_id(spapr, cc->core_id)); 3458 3459 g_assert(drc || !mc->has_hotpluggable_cpus); 3460 3461 if (drc) { 3462 void *fdt; 3463 int fdt_offset; 3464 3465 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 3466 3467 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3468 if (local_err) { 3469 g_free(fdt); 3470 error_propagate(errp, local_err); 3471 return; 3472 } 3473 3474 if (hotplugged) { 3475 /* 3476 * Send hotplug notification interrupt to the guest only 3477 * in case of hotplugged CPUs. 3478 */ 3479 spapr_hotplug_req_add_by_index(drc); 3480 } else { 3481 spapr_drc_reset(drc); 3482 } 3483 } 3484 3485 core_slot->cpu = OBJECT(dev); 3486 3487 if (smc->pre_2_10_has_unused_icps) { 3488 int i; 3489 3490 for (i = 0; i < cc->nr_threads; i++) { 3491 cs = CPU(core->threads[i]); 3492 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3493 } 3494 } 3495 } 3496 3497 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3498 Error **errp) 3499 { 3500 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3501 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3502 Error *local_err = NULL; 3503 CPUCore *cc = CPU_CORE(dev); 3504 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3505 const char *type = object_get_typename(OBJECT(dev)); 3506 CPUArchId *core_slot; 3507 int index; 3508 3509 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3510 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3511 goto out; 3512 } 3513 3514 if (strcmp(base_core_type, type)) { 3515 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3516 goto out; 3517 } 3518 3519 if (cc->core_id % smp_threads) { 3520 error_setg(&local_err, "invalid core id %d", cc->core_id); 3521 goto out; 3522 } 3523 3524 /* 3525 * In general we should have homogeneous threads-per-core, but old 3526 * (pre hotplug support) machine types allow the last core to have 3527 * reduced threads as a compatibility hack for when we allowed 3528 * total vcpus not a multiple of threads-per-core. 3529 */ 3530 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3531 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3532 cc->nr_threads, smp_threads); 3533 goto out; 3534 } 3535 3536 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3537 if (!core_slot) { 3538 error_setg(&local_err, "core id %d out of range", cc->core_id); 3539 goto out; 3540 } 3541 3542 if (core_slot->cpu) { 3543 error_setg(&local_err, "core %d already populated", cc->core_id); 3544 goto out; 3545 } 3546 3547 numa_cpu_pre_plug(core_slot, dev, &local_err); 3548 3549 out: 3550 error_propagate(errp, local_err); 3551 } 3552 3553 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3554 DeviceState *dev, Error **errp) 3555 { 3556 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3557 spapr_memory_plug(hotplug_dev, dev, errp); 3558 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3559 spapr_core_plug(hotplug_dev, dev, errp); 3560 } 3561 } 3562 3563 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 3564 DeviceState *dev, Error **errp) 3565 { 3566 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3567 spapr_memory_unplug(hotplug_dev, dev); 3568 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3569 spapr_core_unplug(hotplug_dev, dev); 3570 } 3571 } 3572 3573 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3574 DeviceState *dev, Error **errp) 3575 { 3576 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3577 MachineClass *mc = MACHINE_GET_CLASS(sms); 3578 3579 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3580 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3581 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3582 } else { 3583 /* NOTE: this means there is a window after guest reset, prior to 3584 * CAS negotiation, where unplug requests will fail due to the 3585 * capability not being detected yet. This is a bit different than 3586 * the case with PCI unplug, where the events will be queued and 3587 * eventually handled by the guest after boot 3588 */ 3589 error_setg(errp, "Memory hot unplug not supported for this guest"); 3590 } 3591 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3592 if (!mc->has_hotpluggable_cpus) { 3593 error_setg(errp, "CPU hot unplug not supported on this machine"); 3594 return; 3595 } 3596 spapr_core_unplug_request(hotplug_dev, dev, errp); 3597 } 3598 } 3599 3600 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3601 DeviceState *dev, Error **errp) 3602 { 3603 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3604 spapr_memory_pre_plug(hotplug_dev, dev, errp); 3605 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3606 spapr_core_pre_plug(hotplug_dev, dev, errp); 3607 } 3608 } 3609 3610 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3611 DeviceState *dev) 3612 { 3613 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3614 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3615 return HOTPLUG_HANDLER(machine); 3616 } 3617 return NULL; 3618 } 3619 3620 static CpuInstanceProperties 3621 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3622 { 3623 CPUArchId *core_slot; 3624 MachineClass *mc = MACHINE_GET_CLASS(machine); 3625 3626 /* make sure possible_cpu are intialized */ 3627 mc->possible_cpu_arch_ids(machine); 3628 /* get CPU core slot containing thread that matches cpu_index */ 3629 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3630 assert(core_slot); 3631 return core_slot->props; 3632 } 3633 3634 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 3635 { 3636 return idx / smp_cores % nb_numa_nodes; 3637 } 3638 3639 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3640 { 3641 int i; 3642 const char *core_type; 3643 int spapr_max_cores = max_cpus / smp_threads; 3644 MachineClass *mc = MACHINE_GET_CLASS(machine); 3645 3646 if (!mc->has_hotpluggable_cpus) { 3647 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3648 } 3649 if (machine->possible_cpus) { 3650 assert(machine->possible_cpus->len == spapr_max_cores); 3651 return machine->possible_cpus; 3652 } 3653 3654 core_type = spapr_get_cpu_core_type(machine->cpu_type); 3655 if (!core_type) { 3656 error_report("Unable to find sPAPR CPU Core definition"); 3657 exit(1); 3658 } 3659 3660 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3661 sizeof(CPUArchId) * spapr_max_cores); 3662 machine->possible_cpus->len = spapr_max_cores; 3663 for (i = 0; i < machine->possible_cpus->len; i++) { 3664 int core_id = i * smp_threads; 3665 3666 machine->possible_cpus->cpus[i].type = core_type; 3667 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3668 machine->possible_cpus->cpus[i].arch_id = core_id; 3669 machine->possible_cpus->cpus[i].props.has_core_id = true; 3670 machine->possible_cpus->cpus[i].props.core_id = core_id; 3671 } 3672 return machine->possible_cpus; 3673 } 3674 3675 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3676 uint64_t *buid, hwaddr *pio, 3677 hwaddr *mmio32, hwaddr *mmio64, 3678 unsigned n_dma, uint32_t *liobns, Error **errp) 3679 { 3680 /* 3681 * New-style PHB window placement. 3682 * 3683 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3684 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3685 * windows. 3686 * 3687 * Some guest kernels can't work with MMIO windows above 1<<46 3688 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3689 * 3690 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3691 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3692 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3693 * 1TiB 64-bit MMIO windows for each PHB. 3694 */ 3695 const uint64_t base_buid = 0x800000020000000ULL; 3696 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3697 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3698 int i; 3699 3700 /* Sanity check natural alignments */ 3701 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3702 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3703 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3704 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3705 /* Sanity check bounds */ 3706 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3707 SPAPR_PCI_MEM32_WIN_SIZE); 3708 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3709 SPAPR_PCI_MEM64_WIN_SIZE); 3710 3711 if (index >= SPAPR_MAX_PHBS) { 3712 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3713 SPAPR_MAX_PHBS - 1); 3714 return; 3715 } 3716 3717 *buid = base_buid + index; 3718 for (i = 0; i < n_dma; ++i) { 3719 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3720 } 3721 3722 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3723 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3724 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3725 } 3726 3727 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3728 { 3729 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3730 3731 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3732 } 3733 3734 static void spapr_ics_resend(XICSFabric *dev) 3735 { 3736 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3737 3738 ics_resend(spapr->ics); 3739 } 3740 3741 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 3742 { 3743 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 3744 3745 return cpu ? ICP(cpu->intc) : NULL; 3746 } 3747 3748 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3749 Monitor *mon) 3750 { 3751 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3752 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3753 3754 smc->irq->print_info(spapr, mon); 3755 } 3756 3757 int spapr_get_vcpu_id(PowerPCCPU *cpu) 3758 { 3759 return cpu->vcpu_id; 3760 } 3761 3762 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 3763 { 3764 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3765 int vcpu_id; 3766 3767 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 3768 3769 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 3770 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 3771 error_append_hint(errp, "Adjust the number of cpus to %d " 3772 "or try to raise the number of threads per core\n", 3773 vcpu_id * smp_threads / spapr->vsmt); 3774 return; 3775 } 3776 3777 cpu->vcpu_id = vcpu_id; 3778 } 3779 3780 PowerPCCPU *spapr_find_cpu(int vcpu_id) 3781 { 3782 CPUState *cs; 3783 3784 CPU_FOREACH(cs) { 3785 PowerPCCPU *cpu = POWERPC_CPU(cs); 3786 3787 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 3788 return cpu; 3789 } 3790 } 3791 3792 return NULL; 3793 } 3794 3795 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3796 { 3797 MachineClass *mc = MACHINE_CLASS(oc); 3798 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3799 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3800 NMIClass *nc = NMI_CLASS(oc); 3801 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3802 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3803 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3804 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3805 3806 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3807 mc->ignore_boot_device_suffixes = true; 3808 3809 /* 3810 * We set up the default / latest behaviour here. The class_init 3811 * functions for the specific versioned machine types can override 3812 * these details for backwards compatibility 3813 */ 3814 mc->init = spapr_machine_init; 3815 mc->reset = spapr_machine_reset; 3816 mc->block_default_type = IF_SCSI; 3817 mc->max_cpus = 1024; 3818 mc->no_parallel = 1; 3819 mc->default_boot_order = ""; 3820 mc->default_ram_size = 512 * MiB; 3821 mc->default_display = "std"; 3822 mc->kvm_type = spapr_kvm_type; 3823 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 3824 mc->pci_allow_0_address = true; 3825 assert(!mc->get_hotplug_handler); 3826 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3827 hc->pre_plug = spapr_machine_device_pre_plug; 3828 hc->plug = spapr_machine_device_plug; 3829 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 3830 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 3831 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3832 hc->unplug_request = spapr_machine_device_unplug_request; 3833 hc->unplug = spapr_machine_device_unplug; 3834 3835 smc->dr_lmb_enabled = true; 3836 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 3837 mc->has_hotpluggable_cpus = true; 3838 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 3839 fwc->get_dev_path = spapr_get_fw_dev_path; 3840 nc->nmi_monitor_handler = spapr_nmi; 3841 smc->phb_placement = spapr_phb_placement; 3842 vhc->hypercall = emulate_spapr_hypercall; 3843 vhc->hpt_mask = spapr_hpt_mask; 3844 vhc->map_hptes = spapr_map_hptes; 3845 vhc->unmap_hptes = spapr_unmap_hptes; 3846 vhc->store_hpte = spapr_store_hpte; 3847 vhc->get_patbe = spapr_get_patbe; 3848 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 3849 xic->ics_get = spapr_ics_get; 3850 xic->ics_resend = spapr_ics_resend; 3851 xic->icp_get = spapr_icp_get; 3852 ispc->print_info = spapr_pic_print_info; 3853 /* Force NUMA node memory size to be a multiple of 3854 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 3855 * in which LMBs are represented and hot-added 3856 */ 3857 mc->numa_mem_align_shift = 28; 3858 3859 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 3860 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 3861 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 3862 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 3863 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 3864 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 3865 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 3866 spapr_caps_add_properties(smc, &error_abort); 3867 smc->irq = &spapr_irq_xics; 3868 } 3869 3870 static const TypeInfo spapr_machine_info = { 3871 .name = TYPE_SPAPR_MACHINE, 3872 .parent = TYPE_MACHINE, 3873 .abstract = true, 3874 .instance_size = sizeof(sPAPRMachineState), 3875 .instance_init = spapr_instance_init, 3876 .instance_finalize = spapr_machine_finalizefn, 3877 .class_size = sizeof(sPAPRMachineClass), 3878 .class_init = spapr_machine_class_init, 3879 .interfaces = (InterfaceInfo[]) { 3880 { TYPE_FW_PATH_PROVIDER }, 3881 { TYPE_NMI }, 3882 { TYPE_HOTPLUG_HANDLER }, 3883 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3884 { TYPE_XICS_FABRIC }, 3885 { TYPE_INTERRUPT_STATS_PROVIDER }, 3886 { } 3887 }, 3888 }; 3889 3890 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3891 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3892 void *data) \ 3893 { \ 3894 MachineClass *mc = MACHINE_CLASS(oc); \ 3895 spapr_machine_##suffix##_class_options(mc); \ 3896 if (latest) { \ 3897 mc->alias = "pseries"; \ 3898 mc->is_default = 1; \ 3899 } \ 3900 } \ 3901 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3902 { \ 3903 MachineState *machine = MACHINE(obj); \ 3904 spapr_machine_##suffix##_instance_options(machine); \ 3905 } \ 3906 static const TypeInfo spapr_machine_##suffix##_info = { \ 3907 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3908 .parent = TYPE_SPAPR_MACHINE, \ 3909 .class_init = spapr_machine_##suffix##_class_init, \ 3910 .instance_init = spapr_machine_##suffix##_instance_init, \ 3911 }; \ 3912 static void spapr_machine_register_##suffix(void) \ 3913 { \ 3914 type_register(&spapr_machine_##suffix##_info); \ 3915 } \ 3916 type_init(spapr_machine_register_##suffix) 3917 3918 /* 3919 * pseries-3.1 3920 */ 3921 static void spapr_machine_3_1_instance_options(MachineState *machine) 3922 { 3923 } 3924 3925 static void spapr_machine_3_1_class_options(MachineClass *mc) 3926 { 3927 /* Defaults for the latest behaviour inherited from the base class */ 3928 } 3929 3930 DEFINE_SPAPR_MACHINE(3_1, "3.1", true); 3931 3932 /* 3933 * pseries-3.0 3934 */ 3935 #define SPAPR_COMPAT_3_0 \ 3936 HW_COMPAT_3_0 3937 3938 static void spapr_machine_3_0_instance_options(MachineState *machine) 3939 { 3940 spapr_machine_3_1_instance_options(machine); 3941 } 3942 3943 static void spapr_machine_3_0_class_options(MachineClass *mc) 3944 { 3945 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3946 3947 spapr_machine_3_1_class_options(mc); 3948 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_3_0); 3949 3950 smc->legacy_irq_allocation = true; 3951 } 3952 3953 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 3954 3955 /* 3956 * pseries-2.12 3957 */ 3958 #define SPAPR_COMPAT_2_12 \ 3959 HW_COMPAT_2_12 \ 3960 { \ 3961 .driver = TYPE_POWERPC_CPU, \ 3962 .property = "pre-3.0-migration", \ 3963 .value = "on", \ 3964 }, \ 3965 { \ 3966 .driver = TYPE_SPAPR_CPU_CORE, \ 3967 .property = "pre-3.0-migration", \ 3968 .value = "on", \ 3969 }, 3970 3971 static void spapr_machine_2_12_instance_options(MachineState *machine) 3972 { 3973 spapr_machine_3_0_instance_options(machine); 3974 } 3975 3976 static void spapr_machine_2_12_class_options(MachineClass *mc) 3977 { 3978 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3979 3980 spapr_machine_3_0_class_options(mc); 3981 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_12); 3982 3983 /* We depend on kvm_enabled() to choose a default value for the 3984 * hpt-max-page-size capability. Of course we can't do it here 3985 * because this is too early and the HW accelerator isn't initialzed 3986 * yet. Postpone this to machine init (see default_caps_with_cpu()). 3987 */ 3988 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 3989 } 3990 3991 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 3992 3993 static void spapr_machine_2_12_sxxm_instance_options(MachineState *machine) 3994 { 3995 spapr_machine_2_12_instance_options(machine); 3996 } 3997 3998 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 3999 { 4000 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4001 4002 spapr_machine_2_12_class_options(mc); 4003 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4004 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4005 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4006 } 4007 4008 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4009 4010 /* 4011 * pseries-2.11 4012 */ 4013 #define SPAPR_COMPAT_2_11 \ 4014 HW_COMPAT_2_11 4015 4016 static void spapr_machine_2_11_instance_options(MachineState *machine) 4017 { 4018 spapr_machine_2_12_instance_options(machine); 4019 } 4020 4021 static void spapr_machine_2_11_class_options(MachineClass *mc) 4022 { 4023 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4024 4025 spapr_machine_2_12_class_options(mc); 4026 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4027 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11); 4028 } 4029 4030 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4031 4032 /* 4033 * pseries-2.10 4034 */ 4035 #define SPAPR_COMPAT_2_10 \ 4036 HW_COMPAT_2_10 4037 4038 static void spapr_machine_2_10_instance_options(MachineState *machine) 4039 { 4040 spapr_machine_2_11_instance_options(machine); 4041 } 4042 4043 static void spapr_machine_2_10_class_options(MachineClass *mc) 4044 { 4045 spapr_machine_2_11_class_options(mc); 4046 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10); 4047 } 4048 4049 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4050 4051 /* 4052 * pseries-2.9 4053 */ 4054 #define SPAPR_COMPAT_2_9 \ 4055 HW_COMPAT_2_9 \ 4056 { \ 4057 .driver = TYPE_POWERPC_CPU, \ 4058 .property = "pre-2.10-migration", \ 4059 .value = "on", \ 4060 }, \ 4061 4062 static void spapr_machine_2_9_instance_options(MachineState *machine) 4063 { 4064 spapr_machine_2_10_instance_options(machine); 4065 } 4066 4067 static void spapr_machine_2_9_class_options(MachineClass *mc) 4068 { 4069 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4070 4071 spapr_machine_2_10_class_options(mc); 4072 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); 4073 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4074 smc->pre_2_10_has_unused_icps = true; 4075 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4076 } 4077 4078 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4079 4080 /* 4081 * pseries-2.8 4082 */ 4083 #define SPAPR_COMPAT_2_8 \ 4084 HW_COMPAT_2_8 \ 4085 { \ 4086 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4087 .property = "pcie-extended-configuration-space", \ 4088 .value = "off", \ 4089 }, 4090 4091 static void spapr_machine_2_8_instance_options(MachineState *machine) 4092 { 4093 spapr_machine_2_9_instance_options(machine); 4094 } 4095 4096 static void spapr_machine_2_8_class_options(MachineClass *mc) 4097 { 4098 spapr_machine_2_9_class_options(mc); 4099 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 4100 mc->numa_mem_align_shift = 23; 4101 } 4102 4103 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4104 4105 /* 4106 * pseries-2.7 4107 */ 4108 #define SPAPR_COMPAT_2_7 \ 4109 HW_COMPAT_2_7 \ 4110 { \ 4111 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4112 .property = "mem_win_size", \ 4113 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 4114 }, \ 4115 { \ 4116 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4117 .property = "mem64_win_size", \ 4118 .value = "0", \ 4119 }, \ 4120 { \ 4121 .driver = TYPE_POWERPC_CPU, \ 4122 .property = "pre-2.8-migration", \ 4123 .value = "on", \ 4124 }, \ 4125 { \ 4126 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4127 .property = "pre-2.8-migration", \ 4128 .value = "on", \ 4129 }, 4130 4131 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 4132 uint64_t *buid, hwaddr *pio, 4133 hwaddr *mmio32, hwaddr *mmio64, 4134 unsigned n_dma, uint32_t *liobns, Error **errp) 4135 { 4136 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4137 const uint64_t base_buid = 0x800000020000000ULL; 4138 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4139 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4140 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4141 const uint32_t max_index = 255; 4142 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4143 4144 uint64_t ram_top = MACHINE(spapr)->ram_size; 4145 hwaddr phb0_base, phb_base; 4146 int i; 4147 4148 /* Do we have device memory? */ 4149 if (MACHINE(spapr)->maxram_size > ram_top) { 4150 /* Can't just use maxram_size, because there may be an 4151 * alignment gap between normal and device memory regions 4152 */ 4153 ram_top = MACHINE(spapr)->device_memory->base + 4154 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4155 } 4156 4157 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4158 4159 if (index > max_index) { 4160 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4161 max_index); 4162 return; 4163 } 4164 4165 *buid = base_buid + index; 4166 for (i = 0; i < n_dma; ++i) { 4167 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4168 } 4169 4170 phb_base = phb0_base + index * phb_spacing; 4171 *pio = phb_base + pio_offset; 4172 *mmio32 = phb_base + mmio_offset; 4173 /* 4174 * We don't set the 64-bit MMIO window, relying on the PHB's 4175 * fallback behaviour of automatically splitting a large "32-bit" 4176 * window into contiguous 32-bit and 64-bit windows 4177 */ 4178 } 4179 4180 static void spapr_machine_2_7_instance_options(MachineState *machine) 4181 { 4182 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 4183 4184 spapr_machine_2_8_instance_options(machine); 4185 spapr->use_hotplug_event_source = false; 4186 } 4187 4188 static void spapr_machine_2_7_class_options(MachineClass *mc) 4189 { 4190 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4191 4192 spapr_machine_2_8_class_options(mc); 4193 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4194 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 4195 smc->phb_placement = phb_placement_2_7; 4196 } 4197 4198 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4199 4200 /* 4201 * pseries-2.6 4202 */ 4203 #define SPAPR_COMPAT_2_6 \ 4204 HW_COMPAT_2_6 \ 4205 { \ 4206 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 4207 .property = "ddw",\ 4208 .value = stringify(off),\ 4209 }, 4210 4211 static void spapr_machine_2_6_instance_options(MachineState *machine) 4212 { 4213 spapr_machine_2_7_instance_options(machine); 4214 } 4215 4216 static void spapr_machine_2_6_class_options(MachineClass *mc) 4217 { 4218 spapr_machine_2_7_class_options(mc); 4219 mc->has_hotpluggable_cpus = false; 4220 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 4221 } 4222 4223 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4224 4225 /* 4226 * pseries-2.5 4227 */ 4228 #define SPAPR_COMPAT_2_5 \ 4229 HW_COMPAT_2_5 \ 4230 { \ 4231 .driver = "spapr-vlan", \ 4232 .property = "use-rx-buffer-pools", \ 4233 .value = "off", \ 4234 }, 4235 4236 static void spapr_machine_2_5_instance_options(MachineState *machine) 4237 { 4238 spapr_machine_2_6_instance_options(machine); 4239 } 4240 4241 static void spapr_machine_2_5_class_options(MachineClass *mc) 4242 { 4243 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4244 4245 spapr_machine_2_6_class_options(mc); 4246 smc->use_ohci_by_default = true; 4247 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 4248 } 4249 4250 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4251 4252 /* 4253 * pseries-2.4 4254 */ 4255 #define SPAPR_COMPAT_2_4 \ 4256 HW_COMPAT_2_4 4257 4258 static void spapr_machine_2_4_instance_options(MachineState *machine) 4259 { 4260 spapr_machine_2_5_instance_options(machine); 4261 } 4262 4263 static void spapr_machine_2_4_class_options(MachineClass *mc) 4264 { 4265 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4266 4267 spapr_machine_2_5_class_options(mc); 4268 smc->dr_lmb_enabled = false; 4269 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 4270 } 4271 4272 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4273 4274 /* 4275 * pseries-2.3 4276 */ 4277 #define SPAPR_COMPAT_2_3 \ 4278 HW_COMPAT_2_3 \ 4279 {\ 4280 .driver = "spapr-pci-host-bridge",\ 4281 .property = "dynamic-reconfiguration",\ 4282 .value = "off",\ 4283 }, 4284 4285 static void spapr_machine_2_3_instance_options(MachineState *machine) 4286 { 4287 spapr_machine_2_4_instance_options(machine); 4288 } 4289 4290 static void spapr_machine_2_3_class_options(MachineClass *mc) 4291 { 4292 spapr_machine_2_4_class_options(mc); 4293 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 4294 } 4295 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4296 4297 /* 4298 * pseries-2.2 4299 */ 4300 4301 #define SPAPR_COMPAT_2_2 \ 4302 HW_COMPAT_2_2 \ 4303 {\ 4304 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 4305 .property = "mem_win_size",\ 4306 .value = "0x20000000",\ 4307 }, 4308 4309 static void spapr_machine_2_2_instance_options(MachineState *machine) 4310 { 4311 spapr_machine_2_3_instance_options(machine); 4312 machine->suppress_vmdesc = true; 4313 } 4314 4315 static void spapr_machine_2_2_class_options(MachineClass *mc) 4316 { 4317 spapr_machine_2_3_class_options(mc); 4318 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 4319 } 4320 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4321 4322 /* 4323 * pseries-2.1 4324 */ 4325 #define SPAPR_COMPAT_2_1 \ 4326 HW_COMPAT_2_1 4327 4328 static void spapr_machine_2_1_instance_options(MachineState *machine) 4329 { 4330 spapr_machine_2_2_instance_options(machine); 4331 } 4332 4333 static void spapr_machine_2_1_class_options(MachineClass *mc) 4334 { 4335 spapr_machine_2_2_class_options(mc); 4336 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 4337 } 4338 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4339 4340 static void spapr_machine_register_types(void) 4341 { 4342 type_register_static(&spapr_machine_info); 4343 } 4344 4345 type_init(spapr_machine_register_types) 4346