1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "sysemu/sysemu.h" 28 #include "hw/hw.h" 29 #include "hw/fw-path-provider.h" 30 #include "elf.h" 31 #include "net/net.h" 32 #include "sysemu/blockdev.h" 33 #include "sysemu/cpus.h" 34 #include "sysemu/kvm.h" 35 #include "kvm_ppc.h" 36 #include "mmu-hash64.h" 37 #include "qom/cpu.h" 38 39 #include "hw/boards.h" 40 #include "hw/ppc/ppc.h" 41 #include "hw/loader.h" 42 43 #include "hw/ppc/spapr.h" 44 #include "hw/ppc/spapr_vio.h" 45 #include "hw/pci-host/spapr.h" 46 #include "hw/ppc/xics.h" 47 #include "hw/pci/msi.h" 48 49 #include "hw/pci/pci.h" 50 #include "hw/scsi/scsi.h" 51 #include "hw/virtio/virtio-scsi.h" 52 53 #include "exec/address-spaces.h" 54 #include "hw/usb.h" 55 #include "qemu/config-file.h" 56 #include "qemu/error-report.h" 57 #include "trace.h" 58 59 #include <libfdt.h> 60 61 /* SLOF memory layout: 62 * 63 * SLOF raw image loaded at 0, copies its romfs right below the flat 64 * device-tree, then position SLOF itself 31M below that 65 * 66 * So we set FW_OVERHEAD to 40MB which should account for all of that 67 * and more 68 * 69 * We load our kernel at 4M, leaving space for SLOF initial image 70 */ 71 #define FDT_MAX_SIZE 0x40000 72 #define RTAS_MAX_SIZE 0x10000 73 #define FW_MAX_SIZE 0x400000 74 #define FW_FILE_NAME "slof.bin" 75 #define FW_OVERHEAD 0x2800000 76 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 77 78 #define MIN_RMA_SLOF 128UL 79 80 #define TIMEBASE_FREQ 512000000ULL 81 82 #define MAX_CPUS 256 83 84 #define PHANDLE_XICP 0x00001111 85 86 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 87 88 89 typedef struct SPAPRMachine SPAPRMachine; 90 #define TYPE_SPAPR_MACHINE "spapr-machine" 91 #define SPAPR_MACHINE(obj) \ 92 OBJECT_CHECK(SPAPRMachine, (obj), TYPE_SPAPR_MACHINE) 93 94 /** 95 * SPAPRMachine: 96 */ 97 struct SPAPRMachine { 98 /*< private >*/ 99 MachineState parent_obj; 100 101 /*< public >*/ 102 char *kvm_type; 103 }; 104 105 106 sPAPREnvironment *spapr; 107 108 int spapr_allocate_irq(int hint, bool lsi) 109 { 110 int irq; 111 112 if (hint) { 113 irq = hint; 114 if (hint >= spapr->next_irq) { 115 spapr->next_irq = hint + 1; 116 } 117 /* FIXME: we should probably check for collisions somehow */ 118 } else { 119 irq = spapr->next_irq++; 120 } 121 122 /* Configure irq type */ 123 if (!xics_get_qirq(spapr->icp, irq)) { 124 return 0; 125 } 126 127 xics_set_irq_type(spapr->icp, irq, lsi); 128 129 return irq; 130 } 131 132 /* 133 * Allocate block of consequtive IRQs, returns a number of the first. 134 * If msi==true, aligns the first IRQ number to num. 135 */ 136 int spapr_allocate_irq_block(int num, bool lsi, bool msi) 137 { 138 int first = -1; 139 int i, hint = 0; 140 141 /* 142 * MSIMesage::data is used for storing VIRQ so 143 * it has to be aligned to num to support multiple 144 * MSI vectors. MSI-X is not affected by this. 145 * The hint is used for the first IRQ, the rest should 146 * be allocated continuously. 147 */ 148 if (msi) { 149 assert((num == 1) || (num == 2) || (num == 4) || 150 (num == 8) || (num == 16) || (num == 32)); 151 hint = (spapr->next_irq + num - 1) & ~(num - 1); 152 } 153 154 for (i = 0; i < num; ++i) { 155 int irq; 156 157 irq = spapr_allocate_irq(hint, lsi); 158 if (!irq) { 159 return -1; 160 } 161 162 if (0 == i) { 163 first = irq; 164 hint = 0; 165 } 166 167 /* If the above doesn't create a consecutive block then that's 168 * an internal bug */ 169 assert(irq == (first + i)); 170 } 171 172 return first; 173 } 174 175 static XICSState *try_create_xics(const char *type, int nr_servers, 176 int nr_irqs) 177 { 178 DeviceState *dev; 179 180 dev = qdev_create(NULL, type); 181 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 182 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 183 if (qdev_init(dev) < 0) { 184 return NULL; 185 } 186 187 return XICS_COMMON(dev); 188 } 189 190 static XICSState *xics_system_init(int nr_servers, int nr_irqs) 191 { 192 XICSState *icp = NULL; 193 194 if (kvm_enabled()) { 195 QemuOpts *machine_opts = qemu_get_machine_opts(); 196 bool irqchip_allowed = qemu_opt_get_bool(machine_opts, 197 "kernel_irqchip", true); 198 bool irqchip_required = qemu_opt_get_bool(machine_opts, 199 "kernel_irqchip", false); 200 if (irqchip_allowed) { 201 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs); 202 } 203 204 if (irqchip_required && !icp) { 205 perror("Failed to create in-kernel XICS\n"); 206 abort(); 207 } 208 } 209 210 if (!icp) { 211 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs); 212 } 213 214 if (!icp) { 215 perror("Failed to create XICS\n"); 216 abort(); 217 } 218 219 return icp; 220 } 221 222 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 223 int smt_threads) 224 { 225 int i, ret = 0; 226 uint32_t servers_prop[smt_threads]; 227 uint32_t gservers_prop[smt_threads * 2]; 228 int index = ppc_get_vcpu_dt_id(cpu); 229 230 if (cpu->cpu_version) { 231 ret = fdt_setprop(fdt, offset, "cpu-version", 232 &cpu->cpu_version, sizeof(cpu->cpu_version)); 233 if (ret < 0) { 234 return ret; 235 } 236 } 237 238 /* Build interrupt servers and gservers properties */ 239 for (i = 0; i < smt_threads; i++) { 240 servers_prop[i] = cpu_to_be32(index + i); 241 /* Hack, direct the group queues back to cpu 0 */ 242 gservers_prop[i*2] = cpu_to_be32(index + i); 243 gservers_prop[i*2 + 1] = 0; 244 } 245 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 246 servers_prop, sizeof(servers_prop)); 247 if (ret < 0) { 248 return ret; 249 } 250 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 251 gservers_prop, sizeof(gservers_prop)); 252 253 return ret; 254 } 255 256 static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) 257 { 258 int ret = 0, offset, cpus_offset; 259 CPUState *cs; 260 char cpu_model[32]; 261 int smt = kvmppc_smt_threads(); 262 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 263 264 CPU_FOREACH(cs) { 265 PowerPCCPU *cpu = POWERPC_CPU(cs); 266 DeviceClass *dc = DEVICE_GET_CLASS(cs); 267 int index = ppc_get_vcpu_dt_id(cpu); 268 uint32_t associativity[] = {cpu_to_be32(0x5), 269 cpu_to_be32(0x0), 270 cpu_to_be32(0x0), 271 cpu_to_be32(0x0), 272 cpu_to_be32(cs->numa_node), 273 cpu_to_be32(index)}; 274 275 if ((index % smt) != 0) { 276 continue; 277 } 278 279 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 280 281 cpus_offset = fdt_path_offset(fdt, "/cpus"); 282 if (cpus_offset < 0) { 283 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 284 "cpus"); 285 if (cpus_offset < 0) { 286 return cpus_offset; 287 } 288 } 289 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 290 if (offset < 0) { 291 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 292 if (offset < 0) { 293 return offset; 294 } 295 } 296 297 if (nb_numa_nodes > 1) { 298 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 299 sizeof(associativity)); 300 if (ret < 0) { 301 return ret; 302 } 303 } 304 305 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 306 pft_size_prop, sizeof(pft_size_prop)); 307 if (ret < 0) { 308 return ret; 309 } 310 311 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 312 ppc_get_compat_smt_threads(cpu)); 313 if (ret < 0) { 314 return ret; 315 } 316 } 317 return ret; 318 } 319 320 321 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 322 size_t maxsize) 323 { 324 size_t maxcells = maxsize / sizeof(uint32_t); 325 int i, j, count; 326 uint32_t *p = prop; 327 328 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 329 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 330 331 if (!sps->page_shift) { 332 break; 333 } 334 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 335 if (sps->enc[count].page_shift == 0) { 336 break; 337 } 338 } 339 if ((p - prop) >= (maxcells - 3 - count * 2)) { 340 break; 341 } 342 *(p++) = cpu_to_be32(sps->page_shift); 343 *(p++) = cpu_to_be32(sps->slb_enc); 344 *(p++) = cpu_to_be32(count); 345 for (j = 0; j < count; j++) { 346 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 347 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 348 } 349 } 350 351 return (p - prop) * sizeof(uint32_t); 352 } 353 354 #define _FDT(exp) \ 355 do { \ 356 int ret = (exp); \ 357 if (ret < 0) { \ 358 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 359 #exp, fdt_strerror(ret)); \ 360 exit(1); \ 361 } \ 362 } while (0) 363 364 static void add_str(GString *s, const gchar *s1) 365 { 366 g_string_append_len(s, s1, strlen(s1) + 1); 367 } 368 369 static void *spapr_create_fdt_skel(hwaddr initrd_base, 370 hwaddr initrd_size, 371 hwaddr kernel_size, 372 bool little_endian, 373 const char *boot_device, 374 const char *kernel_cmdline, 375 uint32_t epow_irq) 376 { 377 void *fdt; 378 CPUState *cs; 379 uint32_t start_prop = cpu_to_be32(initrd_base); 380 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 381 GString *hypertas = g_string_sized_new(256); 382 GString *qemu_hypertas = g_string_sized_new(256); 383 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 384 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; 385 int smt = kvmppc_smt_threads(); 386 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 387 QemuOpts *opts = qemu_opts_find(qemu_find_opts("smp-opts"), NULL); 388 unsigned sockets = opts ? qemu_opt_get_number(opts, "sockets", 0) : 0; 389 uint32_t cpus_per_socket = sockets ? (smp_cpus / sockets) : 1; 390 391 add_str(hypertas, "hcall-pft"); 392 add_str(hypertas, "hcall-term"); 393 add_str(hypertas, "hcall-dabr"); 394 add_str(hypertas, "hcall-interrupt"); 395 add_str(hypertas, "hcall-tce"); 396 add_str(hypertas, "hcall-vio"); 397 add_str(hypertas, "hcall-splpar"); 398 add_str(hypertas, "hcall-bulk"); 399 add_str(hypertas, "hcall-set-mode"); 400 add_str(qemu_hypertas, "hcall-memop1"); 401 402 fdt = g_malloc0(FDT_MAX_SIZE); 403 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 404 405 if (kernel_size) { 406 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 407 } 408 if (initrd_size) { 409 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 410 } 411 _FDT((fdt_finish_reservemap(fdt))); 412 413 /* Root node */ 414 _FDT((fdt_begin_node(fdt, ""))); 415 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 416 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 417 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 418 419 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 420 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 421 422 /* /chosen */ 423 _FDT((fdt_begin_node(fdt, "chosen"))); 424 425 /* Set Form1_affinity */ 426 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 427 428 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 429 _FDT((fdt_property(fdt, "linux,initrd-start", 430 &start_prop, sizeof(start_prop)))); 431 _FDT((fdt_property(fdt, "linux,initrd-end", 432 &end_prop, sizeof(end_prop)))); 433 if (kernel_size) { 434 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 435 cpu_to_be64(kernel_size) }; 436 437 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 438 if (little_endian) { 439 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 440 } 441 } 442 if (boot_device) { 443 _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device))); 444 } 445 if (boot_menu) { 446 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); 447 } 448 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 449 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 450 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 451 452 _FDT((fdt_end_node(fdt))); 453 454 /* cpus */ 455 _FDT((fdt_begin_node(fdt, "cpus"))); 456 457 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 458 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 459 460 CPU_FOREACH(cs) { 461 PowerPCCPU *cpu = POWERPC_CPU(cs); 462 CPUPPCState *env = &cpu->env; 463 DeviceClass *dc = DEVICE_GET_CLASS(cs); 464 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 465 int index = ppc_get_vcpu_dt_id(cpu); 466 char *nodename; 467 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 468 0xffffffff, 0xffffffff}; 469 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 470 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 471 uint32_t page_sizes_prop[64]; 472 size_t page_sizes_prop_size; 473 474 if ((index % smt) != 0) { 475 continue; 476 } 477 478 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 479 480 _FDT((fdt_begin_node(fdt, nodename))); 481 482 g_free(nodename); 483 484 _FDT((fdt_property_cell(fdt, "reg", index))); 485 _FDT((fdt_property_string(fdt, "device_type", "cpu"))); 486 487 _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); 488 _FDT((fdt_property_cell(fdt, "d-cache-block-size", 489 env->dcache_line_size))); 490 _FDT((fdt_property_cell(fdt, "d-cache-line-size", 491 env->dcache_line_size))); 492 _FDT((fdt_property_cell(fdt, "i-cache-block-size", 493 env->icache_line_size))); 494 _FDT((fdt_property_cell(fdt, "i-cache-line-size", 495 env->icache_line_size))); 496 497 if (pcc->l1_dcache_size) { 498 _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size))); 499 } else { 500 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 501 } 502 if (pcc->l1_icache_size) { 503 _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size))); 504 } else { 505 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 506 } 507 508 _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq))); 509 _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq))); 510 _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); 511 _FDT((fdt_property_string(fdt, "status", "okay"))); 512 _FDT((fdt_property(fdt, "64-bit", NULL, 0))); 513 514 if (env->spr_cb[SPR_PURR].oea_read) { 515 _FDT((fdt_property(fdt, "ibm,purr", NULL, 0))); 516 } 517 518 if (env->mmu_model & POWERPC_MMU_1TSEG) { 519 _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", 520 segs, sizeof(segs)))); 521 } 522 523 /* Advertise VMX/VSX (vector extensions) if available 524 * 0 / no property == no vector extensions 525 * 1 == VMX / Altivec available 526 * 2 == VSX available */ 527 if (env->insns_flags & PPC_ALTIVEC) { 528 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 529 530 _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx))); 531 } 532 533 /* Advertise DFP (Decimal Floating Point) if available 534 * 0 / no property == no DFP 535 * 1 == DFP available */ 536 if (env->insns_flags2 & PPC2_DFP) { 537 _FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); 538 } 539 540 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 541 sizeof(page_sizes_prop)); 542 if (page_sizes_prop_size) { 543 _FDT((fdt_property(fdt, "ibm,segment-page-sizes", 544 page_sizes_prop, page_sizes_prop_size))); 545 } 546 547 _FDT((fdt_property_cell(fdt, "ibm,chip-id", 548 cs->cpu_index / cpus_per_socket))); 549 550 _FDT((fdt_end_node(fdt))); 551 } 552 553 _FDT((fdt_end_node(fdt))); 554 555 /* RTAS */ 556 _FDT((fdt_begin_node(fdt, "rtas"))); 557 558 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 559 add_str(hypertas, "hcall-multi-tce"); 560 } 561 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, 562 hypertas->len))); 563 g_string_free(hypertas, TRUE); 564 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, 565 qemu_hypertas->len))); 566 g_string_free(qemu_hypertas, TRUE); 567 568 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 569 refpoints, sizeof(refpoints)))); 570 571 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 572 573 _FDT((fdt_end_node(fdt))); 574 575 /* interrupt controller */ 576 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 577 578 _FDT((fdt_property_string(fdt, "device_type", 579 "PowerPC-External-Interrupt-Presentation"))); 580 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 581 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 582 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 583 interrupt_server_ranges_prop, 584 sizeof(interrupt_server_ranges_prop)))); 585 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 586 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 587 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 588 589 _FDT((fdt_end_node(fdt))); 590 591 /* vdevice */ 592 _FDT((fdt_begin_node(fdt, "vdevice"))); 593 594 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 595 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 596 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 597 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 598 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 599 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 600 601 _FDT((fdt_end_node(fdt))); 602 603 /* event-sources */ 604 spapr_events_fdt_skel(fdt, epow_irq); 605 606 /* /hypervisor node */ 607 if (kvm_enabled()) { 608 uint8_t hypercall[16]; 609 610 /* indicate KVM hypercall interface */ 611 _FDT((fdt_begin_node(fdt, "hypervisor"))); 612 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); 613 if (kvmppc_has_cap_fixup_hcalls()) { 614 /* 615 * Older KVM versions with older guest kernels were broken with the 616 * magic page, don't allow the guest to map it. 617 */ 618 kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 619 sizeof(hypercall)); 620 _FDT((fdt_property(fdt, "hcall-instructions", hypercall, 621 sizeof(hypercall)))); 622 } 623 _FDT((fdt_end_node(fdt))); 624 } 625 626 _FDT((fdt_end_node(fdt))); /* close root node */ 627 _FDT((fdt_finish(fdt))); 628 629 return fdt; 630 } 631 632 int spapr_h_cas_compose_response(target_ulong addr, target_ulong size) 633 { 634 void *fdt, *fdt_skel; 635 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 636 637 size -= sizeof(hdr); 638 639 /* Create sceleton */ 640 fdt_skel = g_malloc0(size); 641 _FDT((fdt_create(fdt_skel, size))); 642 _FDT((fdt_begin_node(fdt_skel, ""))); 643 _FDT((fdt_end_node(fdt_skel))); 644 _FDT((fdt_finish(fdt_skel))); 645 fdt = g_malloc0(size); 646 _FDT((fdt_open_into(fdt_skel, fdt, size))); 647 g_free(fdt_skel); 648 649 /* Fix skeleton up */ 650 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 651 652 /* Pack resulting tree */ 653 _FDT((fdt_pack(fdt))); 654 655 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 656 trace_spapr_cas_failed(size); 657 return -1; 658 } 659 660 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 661 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 662 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 663 g_free(fdt); 664 665 return 0; 666 } 667 668 static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt) 669 { 670 uint32_t associativity[] = {cpu_to_be32(0x4), cpu_to_be32(0x0), 671 cpu_to_be32(0x0), cpu_to_be32(0x0), 672 cpu_to_be32(0x0)}; 673 char mem_name[32]; 674 hwaddr node0_size, mem_start, node_size; 675 uint64_t mem_reg_property[2]; 676 int i, off; 677 678 /* memory node(s) */ 679 if (nb_numa_nodes > 1 && numa_info[0].node_mem < ram_size) { 680 node0_size = numa_info[0].node_mem; 681 } else { 682 node0_size = ram_size; 683 } 684 685 /* RMA */ 686 mem_reg_property[0] = 0; 687 mem_reg_property[1] = cpu_to_be64(spapr->rma_size); 688 off = fdt_add_subnode(fdt, 0, "memory@0"); 689 _FDT(off); 690 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 691 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 692 sizeof(mem_reg_property)))); 693 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 694 sizeof(associativity)))); 695 696 /* RAM: Node 0 */ 697 if (node0_size > spapr->rma_size) { 698 mem_reg_property[0] = cpu_to_be64(spapr->rma_size); 699 mem_reg_property[1] = cpu_to_be64(node0_size - spapr->rma_size); 700 701 sprintf(mem_name, "memory@" TARGET_FMT_lx, spapr->rma_size); 702 off = fdt_add_subnode(fdt, 0, mem_name); 703 _FDT(off); 704 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 705 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 706 sizeof(mem_reg_property)))); 707 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 708 sizeof(associativity)))); 709 } 710 711 /* RAM: Node 1 and beyond */ 712 mem_start = node0_size; 713 for (i = 1; i < nb_numa_nodes; i++) { 714 mem_reg_property[0] = cpu_to_be64(mem_start); 715 if (mem_start >= ram_size) { 716 node_size = 0; 717 } else { 718 node_size = numa_info[i].node_mem; 719 if (node_size > ram_size - mem_start) { 720 node_size = ram_size - mem_start; 721 } 722 } 723 mem_reg_property[1] = cpu_to_be64(node_size); 724 associativity[3] = associativity[4] = cpu_to_be32(i); 725 sprintf(mem_name, "memory@" TARGET_FMT_lx, mem_start); 726 off = fdt_add_subnode(fdt, 0, mem_name); 727 _FDT(off); 728 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 729 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 730 sizeof(mem_reg_property)))); 731 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 732 sizeof(associativity)))); 733 mem_start += node_size; 734 } 735 736 return 0; 737 } 738 739 static void spapr_finalize_fdt(sPAPREnvironment *spapr, 740 hwaddr fdt_addr, 741 hwaddr rtas_addr, 742 hwaddr rtas_size) 743 { 744 int ret, i; 745 size_t cb = 0; 746 char *bootlist; 747 void *fdt; 748 sPAPRPHBState *phb; 749 750 fdt = g_malloc(FDT_MAX_SIZE); 751 752 /* open out the base tree into a temp buffer for the final tweaks */ 753 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 754 755 ret = spapr_populate_memory(spapr, fdt); 756 if (ret < 0) { 757 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 758 exit(1); 759 } 760 761 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 762 if (ret < 0) { 763 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 764 exit(1); 765 } 766 767 QLIST_FOREACH(phb, &spapr->phbs, list) { 768 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 769 } 770 771 if (ret < 0) { 772 fprintf(stderr, "couldn't setup PCI devices in fdt\n"); 773 exit(1); 774 } 775 776 /* RTAS */ 777 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 778 if (ret < 0) { 779 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 780 } 781 782 /* Advertise NUMA via ibm,associativity */ 783 ret = spapr_fixup_cpu_dt(fdt, spapr); 784 if (ret < 0) { 785 fprintf(stderr, "Couldn't finalize CPU device tree properties\n"); 786 } 787 788 bootlist = get_boot_devices_list(&cb, true); 789 if (cb && bootlist) { 790 int offset = fdt_path_offset(fdt, "/chosen"); 791 if (offset < 0) { 792 exit(1); 793 } 794 for (i = 0; i < cb; i++) { 795 if (bootlist[i] == '\n') { 796 bootlist[i] = ' '; 797 } 798 799 } 800 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); 801 } 802 803 if (!spapr->has_graphics) { 804 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 805 } 806 807 _FDT((fdt_pack(fdt))); 808 809 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 810 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n", 811 fdt_totalsize(fdt), FDT_MAX_SIZE); 812 exit(1); 813 } 814 815 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 816 817 g_free(fdt); 818 } 819 820 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 821 { 822 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 823 } 824 825 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 826 { 827 CPUPPCState *env = &cpu->env; 828 829 if (msr_pr) { 830 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 831 env->gpr[3] = H_PRIVILEGE; 832 } else { 833 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 834 } 835 } 836 837 static void spapr_reset_htab(sPAPREnvironment *spapr) 838 { 839 long shift; 840 841 /* allocate hash page table. For now we always make this 16mb, 842 * later we should probably make it scale to the size of guest 843 * RAM */ 844 845 shift = kvmppc_reset_htab(spapr->htab_shift); 846 847 if (shift > 0) { 848 /* Kernel handles htab, we don't need to allocate one */ 849 spapr->htab_shift = shift; 850 kvmppc_kern_htab = true; 851 } else { 852 if (!spapr->htab) { 853 /* Allocate an htab if we don't yet have one */ 854 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); 855 } 856 857 /* And clear it */ 858 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 859 } 860 861 /* Update the RMA size if necessary */ 862 if (spapr->vrma_adjust) { 863 hwaddr node0_size = (nb_numa_nodes > 1) ? 864 numa_info[0].node_mem : ram_size; 865 spapr->rma_size = kvmppc_rma_size(node0_size, spapr->htab_shift); 866 } 867 } 868 869 static void ppc_spapr_reset(void) 870 { 871 PowerPCCPU *first_ppc_cpu; 872 873 /* Reset the hash table & recalc the RMA */ 874 spapr_reset_htab(spapr); 875 876 qemu_devices_reset(); 877 878 /* Load the fdt */ 879 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 880 spapr->rtas_size); 881 882 /* Set up the entry state */ 883 first_ppc_cpu = POWERPC_CPU(first_cpu); 884 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 885 first_ppc_cpu->env.gpr[5] = 0; 886 first_cpu->halted = 0; 887 first_ppc_cpu->env.nip = spapr->entry_point; 888 889 } 890 891 static void spapr_cpu_reset(void *opaque) 892 { 893 PowerPCCPU *cpu = opaque; 894 CPUState *cs = CPU(cpu); 895 CPUPPCState *env = &cpu->env; 896 897 cpu_reset(cs); 898 899 /* All CPUs start halted. CPU0 is unhalted from the machine level 900 * reset code and the rest are explicitly started up by the guest 901 * using an RTAS call */ 902 cs->halted = 1; 903 904 env->spr[SPR_HIOR] = 0; 905 906 env->external_htab = (uint8_t *)spapr->htab; 907 if (kvm_enabled() && !env->external_htab) { 908 /* 909 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte* 910 * functions do the right thing. 911 */ 912 env->external_htab = (void *)1; 913 } 914 env->htab_base = -1; 915 /* 916 * htab_mask is the mask used to normalize hash value to PTEG index. 917 * htab_shift is log2 of hash table size. 918 * We have 8 hpte per group, and each hpte is 16 bytes. 919 * ie have 128 bytes per hpte entry. 920 */ 921 env->htab_mask = (1ULL << ((spapr)->htab_shift - 7)) - 1; 922 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | 923 (spapr->htab_shift - 18); 924 } 925 926 static void spapr_create_nvram(sPAPREnvironment *spapr) 927 { 928 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 929 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 930 931 if (dinfo) { 932 qdev_prop_set_drive_nofail(dev, "drive", dinfo->bdrv); 933 } 934 935 qdev_init_nofail(dev); 936 937 spapr->nvram = (struct sPAPRNVRAM *)dev; 938 } 939 940 /* Returns whether we want to use VGA or not */ 941 static int spapr_vga_init(PCIBus *pci_bus) 942 { 943 switch (vga_interface_type) { 944 case VGA_NONE: 945 return false; 946 case VGA_DEVICE: 947 return true; 948 case VGA_STD: 949 return pci_vga_init(pci_bus) != NULL; 950 default: 951 fprintf(stderr, "This vga model is not supported," 952 "currently it only supports -vga std\n"); 953 exit(0); 954 } 955 } 956 957 static const VMStateDescription vmstate_spapr = { 958 .name = "spapr", 959 .version_id = 2, 960 .minimum_version_id = 1, 961 .fields = (VMStateField[]) { 962 VMSTATE_UINT32(next_irq, sPAPREnvironment), 963 964 /* RTC offset */ 965 VMSTATE_UINT64(rtc_offset, sPAPREnvironment), 966 VMSTATE_PPC_TIMEBASE_V(tb, sPAPREnvironment, 2), 967 VMSTATE_END_OF_LIST() 968 }, 969 }; 970 971 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 972 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 973 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 974 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 975 976 static int htab_save_setup(QEMUFile *f, void *opaque) 977 { 978 sPAPREnvironment *spapr = opaque; 979 980 /* "Iteration" header */ 981 qemu_put_be32(f, spapr->htab_shift); 982 983 if (spapr->htab) { 984 spapr->htab_save_index = 0; 985 spapr->htab_first_pass = true; 986 } else { 987 assert(kvm_enabled()); 988 989 spapr->htab_fd = kvmppc_get_htab_fd(false); 990 if (spapr->htab_fd < 0) { 991 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", 992 strerror(errno)); 993 return -1; 994 } 995 } 996 997 998 return 0; 999 } 1000 1001 static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr, 1002 int64_t max_ns) 1003 { 1004 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1005 int index = spapr->htab_save_index; 1006 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1007 1008 assert(spapr->htab_first_pass); 1009 1010 do { 1011 int chunkstart; 1012 1013 /* Consume invalid HPTEs */ 1014 while ((index < htabslots) 1015 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1016 index++; 1017 CLEAN_HPTE(HPTE(spapr->htab, index)); 1018 } 1019 1020 /* Consume valid HPTEs */ 1021 chunkstart = index; 1022 while ((index < htabslots) 1023 && HPTE_VALID(HPTE(spapr->htab, index))) { 1024 index++; 1025 CLEAN_HPTE(HPTE(spapr->htab, index)); 1026 } 1027 1028 if (index > chunkstart) { 1029 int n_valid = index - chunkstart; 1030 1031 qemu_put_be32(f, chunkstart); 1032 qemu_put_be16(f, n_valid); 1033 qemu_put_be16(f, 0); 1034 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1035 HASH_PTE_SIZE_64 * n_valid); 1036 1037 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1038 break; 1039 } 1040 } 1041 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1042 1043 if (index >= htabslots) { 1044 assert(index == htabslots); 1045 index = 0; 1046 spapr->htab_first_pass = false; 1047 } 1048 spapr->htab_save_index = index; 1049 } 1050 1051 static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, 1052 int64_t max_ns) 1053 { 1054 bool final = max_ns < 0; 1055 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1056 int examined = 0, sent = 0; 1057 int index = spapr->htab_save_index; 1058 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1059 1060 assert(!spapr->htab_first_pass); 1061 1062 do { 1063 int chunkstart, invalidstart; 1064 1065 /* Consume non-dirty HPTEs */ 1066 while ((index < htabslots) 1067 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1068 index++; 1069 examined++; 1070 } 1071 1072 chunkstart = index; 1073 /* Consume valid dirty HPTEs */ 1074 while ((index < htabslots) 1075 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1076 && HPTE_VALID(HPTE(spapr->htab, index))) { 1077 CLEAN_HPTE(HPTE(spapr->htab, index)); 1078 index++; 1079 examined++; 1080 } 1081 1082 invalidstart = index; 1083 /* Consume invalid dirty HPTEs */ 1084 while ((index < htabslots) 1085 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1086 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1087 CLEAN_HPTE(HPTE(spapr->htab, index)); 1088 index++; 1089 examined++; 1090 } 1091 1092 if (index > chunkstart) { 1093 int n_valid = invalidstart - chunkstart; 1094 int n_invalid = index - invalidstart; 1095 1096 qemu_put_be32(f, chunkstart); 1097 qemu_put_be16(f, n_valid); 1098 qemu_put_be16(f, n_invalid); 1099 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1100 HASH_PTE_SIZE_64 * n_valid); 1101 sent += index - chunkstart; 1102 1103 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1104 break; 1105 } 1106 } 1107 1108 if (examined >= htabslots) { 1109 break; 1110 } 1111 1112 if (index >= htabslots) { 1113 assert(index == htabslots); 1114 index = 0; 1115 } 1116 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1117 1118 if (index >= htabslots) { 1119 assert(index == htabslots); 1120 index = 0; 1121 } 1122 1123 spapr->htab_save_index = index; 1124 1125 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1126 } 1127 1128 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1129 #define MAX_KVM_BUF_SIZE 2048 1130 1131 static int htab_save_iterate(QEMUFile *f, void *opaque) 1132 { 1133 sPAPREnvironment *spapr = opaque; 1134 int rc = 0; 1135 1136 /* Iteration header */ 1137 qemu_put_be32(f, 0); 1138 1139 if (!spapr->htab) { 1140 assert(kvm_enabled()); 1141 1142 rc = kvmppc_save_htab(f, spapr->htab_fd, 1143 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1144 if (rc < 0) { 1145 return rc; 1146 } 1147 } else if (spapr->htab_first_pass) { 1148 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1149 } else { 1150 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1151 } 1152 1153 /* End marker */ 1154 qemu_put_be32(f, 0); 1155 qemu_put_be16(f, 0); 1156 qemu_put_be16(f, 0); 1157 1158 return rc; 1159 } 1160 1161 static int htab_save_complete(QEMUFile *f, void *opaque) 1162 { 1163 sPAPREnvironment *spapr = opaque; 1164 1165 /* Iteration header */ 1166 qemu_put_be32(f, 0); 1167 1168 if (!spapr->htab) { 1169 int rc; 1170 1171 assert(kvm_enabled()); 1172 1173 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); 1174 if (rc < 0) { 1175 return rc; 1176 } 1177 close(spapr->htab_fd); 1178 spapr->htab_fd = -1; 1179 } else { 1180 htab_save_later_pass(f, spapr, -1); 1181 } 1182 1183 /* End marker */ 1184 qemu_put_be32(f, 0); 1185 qemu_put_be16(f, 0); 1186 qemu_put_be16(f, 0); 1187 1188 return 0; 1189 } 1190 1191 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1192 { 1193 sPAPREnvironment *spapr = opaque; 1194 uint32_t section_hdr; 1195 int fd = -1; 1196 1197 if (version_id < 1 || version_id > 1) { 1198 fprintf(stderr, "htab_load() bad version\n"); 1199 return -EINVAL; 1200 } 1201 1202 section_hdr = qemu_get_be32(f); 1203 1204 if (section_hdr) { 1205 /* First section, just the hash shift */ 1206 if (spapr->htab_shift != section_hdr) { 1207 return -EINVAL; 1208 } 1209 return 0; 1210 } 1211 1212 if (!spapr->htab) { 1213 assert(kvm_enabled()); 1214 1215 fd = kvmppc_get_htab_fd(true); 1216 if (fd < 0) { 1217 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", 1218 strerror(errno)); 1219 } 1220 } 1221 1222 while (true) { 1223 uint32_t index; 1224 uint16_t n_valid, n_invalid; 1225 1226 index = qemu_get_be32(f); 1227 n_valid = qemu_get_be16(f); 1228 n_invalid = qemu_get_be16(f); 1229 1230 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1231 /* End of Stream */ 1232 break; 1233 } 1234 1235 if ((index + n_valid + n_invalid) > 1236 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1237 /* Bad index in stream */ 1238 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " 1239 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, 1240 spapr->htab_shift); 1241 return -EINVAL; 1242 } 1243 1244 if (spapr->htab) { 1245 if (n_valid) { 1246 qemu_get_buffer(f, HPTE(spapr->htab, index), 1247 HASH_PTE_SIZE_64 * n_valid); 1248 } 1249 if (n_invalid) { 1250 memset(HPTE(spapr->htab, index + n_valid), 0, 1251 HASH_PTE_SIZE_64 * n_invalid); 1252 } 1253 } else { 1254 int rc; 1255 1256 assert(fd >= 0); 1257 1258 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1259 if (rc < 0) { 1260 return rc; 1261 } 1262 } 1263 } 1264 1265 if (!spapr->htab) { 1266 assert(fd >= 0); 1267 close(fd); 1268 } 1269 1270 return 0; 1271 } 1272 1273 static SaveVMHandlers savevm_htab_handlers = { 1274 .save_live_setup = htab_save_setup, 1275 .save_live_iterate = htab_save_iterate, 1276 .save_live_complete = htab_save_complete, 1277 .load_state = htab_load, 1278 }; 1279 1280 /* pSeries LPAR / sPAPR hardware init */ 1281 static void ppc_spapr_init(MachineState *machine) 1282 { 1283 ram_addr_t ram_size = machine->ram_size; 1284 const char *cpu_model = machine->cpu_model; 1285 const char *kernel_filename = machine->kernel_filename; 1286 const char *kernel_cmdline = machine->kernel_cmdline; 1287 const char *initrd_filename = machine->initrd_filename; 1288 const char *boot_device = machine->boot_order; 1289 PowerPCCPU *cpu; 1290 CPUPPCState *env; 1291 PCIHostState *phb; 1292 int i; 1293 MemoryRegion *sysmem = get_system_memory(); 1294 MemoryRegion *ram = g_new(MemoryRegion, 1); 1295 hwaddr rma_alloc_size; 1296 hwaddr node0_size = (nb_numa_nodes > 1) ? numa_info[0].node_mem : ram_size; 1297 uint32_t initrd_base = 0; 1298 long kernel_size = 0, initrd_size = 0; 1299 long load_limit, rtas_limit, fw_size; 1300 bool kernel_le = false; 1301 char *filename; 1302 1303 msi_supported = true; 1304 1305 spapr = g_malloc0(sizeof(*spapr)); 1306 QLIST_INIT(&spapr->phbs); 1307 1308 cpu_ppc_hypercall = emulate_spapr_hypercall; 1309 1310 /* Allocate RMA if necessary */ 1311 rma_alloc_size = kvmppc_alloc_rma("ppc_spapr.rma", sysmem); 1312 1313 if (rma_alloc_size == -1) { 1314 hw_error("qemu: Unable to create RMA\n"); 1315 exit(1); 1316 } 1317 1318 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1319 spapr->rma_size = rma_alloc_size; 1320 } else { 1321 spapr->rma_size = node0_size; 1322 1323 /* With KVM, we don't actually know whether KVM supports an 1324 * unbounded RMA (PR KVM) or is limited by the hash table size 1325 * (HV KVM using VRMA), so we always assume the latter 1326 * 1327 * In that case, we also limit the initial allocations for RTAS 1328 * etc... to 256M since we have no way to know what the VRMA size 1329 * is going to be as it depends on the size of the hash table 1330 * isn't determined yet. 1331 */ 1332 if (kvm_enabled()) { 1333 spapr->vrma_adjust = 1; 1334 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1335 } 1336 } 1337 1338 if (spapr->rma_size > node0_size) { 1339 fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n", 1340 spapr->rma_size); 1341 exit(1); 1342 } 1343 1344 /* We place the device tree and RTAS just below either the top of the RMA, 1345 * or just below 2GB, whichever is lowere, so that it can be 1346 * processed with 32-bit real mode code if necessary */ 1347 rtas_limit = MIN(spapr->rma_size, 0x80000000); 1348 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1349 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 1350 load_limit = spapr->fdt_addr - FW_OVERHEAD; 1351 1352 /* We aim for a hash table of size 1/128 the size of RAM. The 1353 * normal rule of thumb is 1/64 the size of RAM, but that's much 1354 * more than needed for the Linux guests we support. */ 1355 spapr->htab_shift = 18; /* Minimum architected size */ 1356 while (spapr->htab_shift <= 46) { 1357 if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) { 1358 break; 1359 } 1360 spapr->htab_shift++; 1361 } 1362 1363 /* Set up Interrupt Controller before we create the VCPUs */ 1364 spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads, 1365 XICS_IRQS); 1366 spapr->next_irq = XICS_IRQ_BASE; 1367 1368 /* init CPUs */ 1369 if (cpu_model == NULL) { 1370 cpu_model = kvm_enabled() ? "host" : "POWER7"; 1371 } 1372 for (i = 0; i < smp_cpus; i++) { 1373 cpu = cpu_ppc_init(cpu_model); 1374 if (cpu == NULL) { 1375 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 1376 exit(1); 1377 } 1378 env = &cpu->env; 1379 1380 /* Set time-base frequency to 512 MHz */ 1381 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 1382 1383 /* PAPR always has exception vectors in RAM not ROM. To ensure this, 1384 * MSR[IP] should never be set. 1385 */ 1386 env->msr_mask &= ~(1 << 6); 1387 1388 /* Tell KVM that we're in PAPR mode */ 1389 if (kvm_enabled()) { 1390 kvmppc_set_papr(cpu); 1391 } 1392 1393 if (cpu->max_compat) { 1394 if (ppc_set_compat(cpu, cpu->max_compat) < 0) { 1395 exit(1); 1396 } 1397 } 1398 1399 xics_cpu_setup(spapr->icp, cpu); 1400 1401 qemu_register_reset(spapr_cpu_reset, cpu); 1402 } 1403 1404 /* allocate RAM */ 1405 spapr->ram_limit = ram_size; 1406 if (spapr->ram_limit > rma_alloc_size) { 1407 ram_addr_t nonrma_base = rma_alloc_size; 1408 ram_addr_t nonrma_size = spapr->ram_limit - rma_alloc_size; 1409 1410 memory_region_init_ram(ram, NULL, "ppc_spapr.ram", nonrma_size); 1411 vmstate_register_ram_global(ram); 1412 memory_region_add_subregion(sysmem, nonrma_base, ram); 1413 } 1414 1415 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1416 spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr, 1417 rtas_limit - spapr->rtas_addr); 1418 if (spapr->rtas_size < 0) { 1419 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1420 exit(1); 1421 } 1422 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1423 hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n", 1424 spapr->rtas_size, RTAS_MAX_SIZE); 1425 exit(1); 1426 } 1427 g_free(filename); 1428 1429 /* Set up EPOW events infrastructure */ 1430 spapr_events_init(spapr); 1431 1432 /* Set up VIO bus */ 1433 spapr->vio_bus = spapr_vio_bus_init(); 1434 1435 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1436 if (serial_hds[i]) { 1437 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1438 } 1439 } 1440 1441 /* We always have at least the nvram device on VIO */ 1442 spapr_create_nvram(spapr); 1443 1444 /* Set up PCI */ 1445 spapr_pci_msi_init(spapr, SPAPR_PCI_MSI_WINDOW); 1446 spapr_pci_rtas_init(); 1447 1448 phb = spapr_create_phb(spapr, 0); 1449 1450 for (i = 0; i < nb_nics; i++) { 1451 NICInfo *nd = &nd_table[i]; 1452 1453 if (!nd->model) { 1454 nd->model = g_strdup("ibmveth"); 1455 } 1456 1457 if (strcmp(nd->model, "ibmveth") == 0) { 1458 spapr_vlan_create(spapr->vio_bus, nd); 1459 } else { 1460 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1461 } 1462 } 1463 1464 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1465 spapr_vscsi_create(spapr->vio_bus); 1466 } 1467 1468 /* Graphics */ 1469 if (spapr_vga_init(phb->bus)) { 1470 spapr->has_graphics = true; 1471 } 1472 1473 if (usb_enabled(spapr->has_graphics)) { 1474 pci_create_simple(phb->bus, -1, "pci-ohci"); 1475 if (spapr->has_graphics) { 1476 usbdevice_create("keyboard"); 1477 usbdevice_create("mouse"); 1478 } 1479 } 1480 1481 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1482 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " 1483 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); 1484 exit(1); 1485 } 1486 1487 if (kernel_filename) { 1488 uint64_t lowaddr = 0; 1489 1490 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1491 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); 1492 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { 1493 kernel_size = load_elf(kernel_filename, 1494 translate_kernel_address, NULL, 1495 NULL, &lowaddr, NULL, 0, ELF_MACHINE, 0); 1496 kernel_le = kernel_size > 0; 1497 } 1498 if (kernel_size < 0) { 1499 fprintf(stderr, "qemu: error loading %s: %s\n", 1500 kernel_filename, load_elf_strerror(kernel_size)); 1501 exit(1); 1502 } 1503 1504 /* load initrd */ 1505 if (initrd_filename) { 1506 /* Try to locate the initrd in the gap between the kernel 1507 * and the firmware. Add a bit of space just in case 1508 */ 1509 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1510 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1511 load_limit - initrd_base); 1512 if (initrd_size < 0) { 1513 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 1514 initrd_filename); 1515 exit(1); 1516 } 1517 } else { 1518 initrd_base = 0; 1519 initrd_size = 0; 1520 } 1521 } 1522 1523 if (bios_name == NULL) { 1524 bios_name = FW_FILE_NAME; 1525 } 1526 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1527 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 1528 if (fw_size < 0) { 1529 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1530 exit(1); 1531 } 1532 g_free(filename); 1533 1534 spapr->entry_point = 0x100; 1535 1536 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 1537 register_savevm_live(NULL, "spapr/htab", -1, 1, 1538 &savevm_htab_handlers, spapr); 1539 1540 /* Prepare the device tree */ 1541 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 1542 kernel_size, kernel_le, 1543 boot_device, kernel_cmdline, 1544 spapr->epow_irq); 1545 assert(spapr->fdt_skel != NULL); 1546 } 1547 1548 static int spapr_kvm_type(const char *vm_type) 1549 { 1550 if (!vm_type) { 1551 return 0; 1552 } 1553 1554 if (!strcmp(vm_type, "HV")) { 1555 return 1; 1556 } 1557 1558 if (!strcmp(vm_type, "PR")) { 1559 return 2; 1560 } 1561 1562 error_report("Unknown kvm-type specified '%s'", vm_type); 1563 exit(1); 1564 } 1565 1566 /* 1567 * Implementation of an interface to adjust firmware patch 1568 * for the bootindex property handling. 1569 */ 1570 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 1571 DeviceState *dev) 1572 { 1573 #define CAST(type, obj, name) \ 1574 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 1575 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 1576 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 1577 1578 if (d) { 1579 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 1580 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 1581 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 1582 1583 if (spapr) { 1584 /* 1585 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 1586 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 1587 * in the top 16 bits of the 64-bit LUN 1588 */ 1589 unsigned id = 0x8000 | (d->id << 8) | d->lun; 1590 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1591 (uint64_t)id << 48); 1592 } else if (virtio) { 1593 /* 1594 * We use SRP luns of the form 01000000 | (target << 8) | lun 1595 * in the top 32 bits of the 64-bit LUN 1596 * Note: the quote above is from SLOF and it is wrong, 1597 * the actual binding is: 1598 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 1599 */ 1600 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 1601 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1602 (uint64_t)id << 32); 1603 } else if (usb) { 1604 /* 1605 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 1606 * in the top 32 bits of the 64-bit LUN 1607 */ 1608 unsigned usb_port = atoi(usb->port->path); 1609 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 1610 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1611 (uint64_t)id << 32); 1612 } 1613 } 1614 1615 if (phb) { 1616 /* Replace "pci" with "pci@800000020000000" */ 1617 return g_strdup_printf("pci@%"PRIX64, phb->buid); 1618 } 1619 1620 return NULL; 1621 } 1622 1623 static char *spapr_get_kvm_type(Object *obj, Error **errp) 1624 { 1625 SPAPRMachine *sm = SPAPR_MACHINE(obj); 1626 1627 return g_strdup(sm->kvm_type); 1628 } 1629 1630 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 1631 { 1632 SPAPRMachine *sm = SPAPR_MACHINE(obj); 1633 1634 g_free(sm->kvm_type); 1635 sm->kvm_type = g_strdup(value); 1636 } 1637 1638 static void spapr_machine_initfn(Object *obj) 1639 { 1640 object_property_add_str(obj, "kvm-type", 1641 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 1642 } 1643 1644 static void spapr_machine_class_init(ObjectClass *oc, void *data) 1645 { 1646 MachineClass *mc = MACHINE_CLASS(oc); 1647 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 1648 1649 mc->name = "pseries"; 1650 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 1651 mc->is_default = 1; 1652 mc->init = ppc_spapr_init; 1653 mc->reset = ppc_spapr_reset; 1654 mc->block_default_type = IF_SCSI; 1655 mc->max_cpus = MAX_CPUS; 1656 mc->no_parallel = 1; 1657 mc->default_boot_order = NULL; 1658 mc->kvm_type = spapr_kvm_type; 1659 1660 fwc->get_dev_path = spapr_get_fw_dev_path; 1661 } 1662 1663 static const TypeInfo spapr_machine_info = { 1664 .name = TYPE_SPAPR_MACHINE, 1665 .parent = TYPE_MACHINE, 1666 .instance_size = sizeof(SPAPRMachine), 1667 .instance_init = spapr_machine_initfn, 1668 .class_init = spapr_machine_class_init, 1669 .interfaces = (InterfaceInfo[]) { 1670 { TYPE_FW_PATH_PROVIDER }, 1671 { } 1672 }, 1673 }; 1674 1675 static void spapr_machine_register_types(void) 1676 { 1677 type_register_static(&spapr_machine_info); 1678 } 1679 1680 type_init(spapr_machine_register_types) 1681