1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/datadir.h" 30 #include "qapi/error.h" 31 #include "qapi/visitor.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/hostmem.h" 34 #include "sysemu/numa.h" 35 #include "sysemu/qtest.h" 36 #include "sysemu/reset.h" 37 #include "sysemu/runstate.h" 38 #include "qemu/log.h" 39 #include "hw/fw-path-provider.h" 40 #include "elf.h" 41 #include "net/net.h" 42 #include "sysemu/device_tree.h" 43 #include "sysemu/cpus.h" 44 #include "sysemu/hw_accel.h" 45 #include "kvm_ppc.h" 46 #include "migration/misc.h" 47 #include "migration/qemu-file-types.h" 48 #include "migration/global_state.h" 49 #include "migration/register.h" 50 #include "migration/blocker.h" 51 #include "mmu-hash64.h" 52 #include "mmu-book3s-v3.h" 53 #include "cpu-models.h" 54 #include "hw/core/cpu.h" 55 56 #include "hw/boards.h" 57 #include "hw/ppc/ppc.h" 58 #include "hw/loader.h" 59 60 #include "hw/ppc/fdt.h" 61 #include "hw/ppc/spapr.h" 62 #include "hw/ppc/spapr_vio.h" 63 #include "hw/qdev-properties.h" 64 #include "hw/pci-host/spapr.h" 65 #include "hw/pci/msi.h" 66 67 #include "hw/pci/pci.h" 68 #include "hw/scsi/scsi.h" 69 #include "hw/virtio/virtio-scsi.h" 70 #include "hw/virtio/vhost-scsi-common.h" 71 72 #include "exec/address-spaces.h" 73 #include "exec/ram_addr.h" 74 #include "hw/usb.h" 75 #include "qemu/config-file.h" 76 #include "qemu/error-report.h" 77 #include "trace.h" 78 #include "hw/nmi.h" 79 #include "hw/intc/intc.h" 80 81 #include "hw/ppc/spapr_cpu_core.h" 82 #include "hw/mem/memory-device.h" 83 #include "hw/ppc/spapr_tpm_proxy.h" 84 #include "hw/ppc/spapr_nvdimm.h" 85 #include "hw/ppc/spapr_numa.h" 86 #include "hw/ppc/pef.h" 87 88 #include "monitor/monitor.h" 89 90 #include <libfdt.h> 91 92 /* SLOF memory layout: 93 * 94 * SLOF raw image loaded at 0, copies its romfs right below the flat 95 * device-tree, then position SLOF itself 31M below that 96 * 97 * So we set FW_OVERHEAD to 40MB which should account for all of that 98 * and more 99 * 100 * We load our kernel at 4M, leaving space for SLOF initial image 101 */ 102 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 103 #define FW_MAX_SIZE 0x400000 104 #define FW_FILE_NAME "slof.bin" 105 #define FW_OVERHEAD 0x2800000 106 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 107 108 #define MIN_RMA_SLOF (128 * MiB) 109 110 #define PHANDLE_INTC 0x00001111 111 112 /* These two functions implement the VCPU id numbering: one to compute them 113 * all and one to identify thread 0 of a VCORE. Any change to the first one 114 * is likely to have an impact on the second one, so let's keep them close. 115 */ 116 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 117 { 118 MachineState *ms = MACHINE(spapr); 119 unsigned int smp_threads = ms->smp.threads; 120 121 assert(spapr->vsmt); 122 return 123 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 124 } 125 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 126 PowerPCCPU *cpu) 127 { 128 assert(spapr->vsmt); 129 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 130 } 131 132 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 133 { 134 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 135 * and newer QEMUs don't even have them. In both cases, we don't want 136 * to send anything on the wire. 137 */ 138 return false; 139 } 140 141 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 142 .name = "icp/server", 143 .version_id = 1, 144 .minimum_version_id = 1, 145 .needed = pre_2_10_vmstate_dummy_icp_needed, 146 .fields = (VMStateField[]) { 147 VMSTATE_UNUSED(4), /* uint32_t xirr */ 148 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 149 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 150 VMSTATE_END_OF_LIST() 151 }, 152 }; 153 154 static void pre_2_10_vmstate_register_dummy_icp(int i) 155 { 156 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 157 (void *)(uintptr_t) i); 158 } 159 160 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 161 { 162 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 163 (void *)(uintptr_t) i); 164 } 165 166 int spapr_max_server_number(SpaprMachineState *spapr) 167 { 168 MachineState *ms = MACHINE(spapr); 169 170 assert(spapr->vsmt); 171 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 172 } 173 174 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 175 int smt_threads) 176 { 177 int i, ret = 0; 178 uint32_t servers_prop[smt_threads]; 179 uint32_t gservers_prop[smt_threads * 2]; 180 int index = spapr_get_vcpu_id(cpu); 181 182 if (cpu->compat_pvr) { 183 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 184 if (ret < 0) { 185 return ret; 186 } 187 } 188 189 /* Build interrupt servers and gservers properties */ 190 for (i = 0; i < smt_threads; i++) { 191 servers_prop[i] = cpu_to_be32(index + i); 192 /* Hack, direct the group queues back to cpu 0 */ 193 gservers_prop[i*2] = cpu_to_be32(index + i); 194 gservers_prop[i*2 + 1] = 0; 195 } 196 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 197 servers_prop, sizeof(servers_prop)); 198 if (ret < 0) { 199 return ret; 200 } 201 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 202 gservers_prop, sizeof(gservers_prop)); 203 204 return ret; 205 } 206 207 static void spapr_dt_pa_features(SpaprMachineState *spapr, 208 PowerPCCPU *cpu, 209 void *fdt, int offset) 210 { 211 uint8_t pa_features_206[] = { 6, 0, 212 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 213 uint8_t pa_features_207[] = { 24, 0, 214 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 215 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 216 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 217 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 218 uint8_t pa_features_300[] = { 66, 0, 219 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 220 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 221 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 222 /* 6: DS207 */ 223 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 224 /* 16: Vector */ 225 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 226 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 227 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 228 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 229 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 230 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 231 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 232 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 233 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 234 /* 42: PM, 44: PC RA, 46: SC vec'd */ 235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 236 /* 48: SIMD, 50: QP BFP, 52: String */ 237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 238 /* 54: DecFP, 56: DecI, 58: SHA */ 239 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 240 /* 60: NM atomic, 62: RNG */ 241 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 242 }; 243 uint8_t *pa_features = NULL; 244 size_t pa_size; 245 246 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 247 pa_features = pa_features_206; 248 pa_size = sizeof(pa_features_206); 249 } 250 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 251 pa_features = pa_features_207; 252 pa_size = sizeof(pa_features_207); 253 } 254 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 255 pa_features = pa_features_300; 256 pa_size = sizeof(pa_features_300); 257 } 258 if (!pa_features) { 259 return; 260 } 261 262 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 263 /* 264 * Note: we keep CI large pages off by default because a 64K capable 265 * guest provisioned with large pages might otherwise try to map a qemu 266 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 267 * even if that qemu runs on a 4k host. 268 * We dd this bit back here if we are confident this is not an issue 269 */ 270 pa_features[3] |= 0x20; 271 } 272 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 273 pa_features[24] |= 0x80; /* Transactional memory support */ 274 } 275 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 276 /* Workaround for broken kernels that attempt (guest) radix 277 * mode when they can't handle it, if they see the radix bit set 278 * in pa-features. So hide it from them. */ 279 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 280 } 281 282 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 283 } 284 285 static hwaddr spapr_node0_size(MachineState *machine) 286 { 287 if (machine->numa_state->num_nodes) { 288 int i; 289 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 290 if (machine->numa_state->nodes[i].node_mem) { 291 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 292 machine->ram_size); 293 } 294 } 295 } 296 return machine->ram_size; 297 } 298 299 bool spapr_machine_using_legacy_numa(SpaprMachineState *spapr) 300 { 301 MachineState *machine = MACHINE(spapr); 302 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 303 304 return smc->pre_5_2_numa_associativity || 305 machine->numa_state->num_nodes <= 1; 306 } 307 308 static void add_str(GString *s, const gchar *s1) 309 { 310 g_string_append_len(s, s1, strlen(s1) + 1); 311 } 312 313 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 314 hwaddr start, hwaddr size) 315 { 316 char mem_name[32]; 317 uint64_t mem_reg_property[2]; 318 int off; 319 320 mem_reg_property[0] = cpu_to_be64(start); 321 mem_reg_property[1] = cpu_to_be64(size); 322 323 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 324 off = fdt_add_subnode(fdt, 0, mem_name); 325 _FDT(off); 326 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 327 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 328 sizeof(mem_reg_property)))); 329 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 330 return off; 331 } 332 333 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 334 { 335 MemoryDeviceInfoList *info; 336 337 for (info = list; info; info = info->next) { 338 MemoryDeviceInfo *value = info->value; 339 340 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 341 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 342 343 if (addr >= pcdimm_info->addr && 344 addr < (pcdimm_info->addr + pcdimm_info->size)) { 345 return pcdimm_info->node; 346 } 347 } 348 } 349 350 return -1; 351 } 352 353 struct sPAPRDrconfCellV2 { 354 uint32_t seq_lmbs; 355 uint64_t base_addr; 356 uint32_t drc_index; 357 uint32_t aa_index; 358 uint32_t flags; 359 } QEMU_PACKED; 360 361 typedef struct DrconfCellQueue { 362 struct sPAPRDrconfCellV2 cell; 363 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 364 } DrconfCellQueue; 365 366 static DrconfCellQueue * 367 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 368 uint32_t drc_index, uint32_t aa_index, 369 uint32_t flags) 370 { 371 DrconfCellQueue *elem; 372 373 elem = g_malloc0(sizeof(*elem)); 374 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 375 elem->cell.base_addr = cpu_to_be64(base_addr); 376 elem->cell.drc_index = cpu_to_be32(drc_index); 377 elem->cell.aa_index = cpu_to_be32(aa_index); 378 elem->cell.flags = cpu_to_be32(flags); 379 380 return elem; 381 } 382 383 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 384 int offset, MemoryDeviceInfoList *dimms) 385 { 386 MachineState *machine = MACHINE(spapr); 387 uint8_t *int_buf, *cur_index; 388 int ret; 389 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 390 uint64_t addr, cur_addr, size; 391 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 392 uint64_t mem_end = machine->device_memory->base + 393 memory_region_size(&machine->device_memory->mr); 394 uint32_t node, buf_len, nr_entries = 0; 395 SpaprDrc *drc; 396 DrconfCellQueue *elem, *next; 397 MemoryDeviceInfoList *info; 398 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 399 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 400 401 /* Entry to cover RAM and the gap area */ 402 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 403 SPAPR_LMB_FLAGS_RESERVED | 404 SPAPR_LMB_FLAGS_DRC_INVALID); 405 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 406 nr_entries++; 407 408 cur_addr = machine->device_memory->base; 409 for (info = dimms; info; info = info->next) { 410 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 411 412 addr = di->addr; 413 size = di->size; 414 node = di->node; 415 416 /* 417 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 418 * area is marked hotpluggable in the next iteration for the bigger 419 * chunk including the NVDIMM occupied area. 420 */ 421 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 422 continue; 423 424 /* Entry for hot-pluggable area */ 425 if (cur_addr < addr) { 426 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 427 g_assert(drc); 428 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 429 cur_addr, spapr_drc_index(drc), -1, 0); 430 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 431 nr_entries++; 432 } 433 434 /* Entry for DIMM */ 435 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 436 g_assert(drc); 437 elem = spapr_get_drconf_cell(size / lmb_size, addr, 438 spapr_drc_index(drc), node, 439 (SPAPR_LMB_FLAGS_ASSIGNED | 440 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 441 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 442 nr_entries++; 443 cur_addr = addr + size; 444 } 445 446 /* Entry for remaining hotpluggable area */ 447 if (cur_addr < mem_end) { 448 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 449 g_assert(drc); 450 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 451 cur_addr, spapr_drc_index(drc), -1, 0); 452 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 453 nr_entries++; 454 } 455 456 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 457 int_buf = cur_index = g_malloc0(buf_len); 458 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 459 cur_index += sizeof(nr_entries); 460 461 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 462 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 463 cur_index += sizeof(elem->cell); 464 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 465 g_free(elem); 466 } 467 468 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 469 g_free(int_buf); 470 if (ret < 0) { 471 return -1; 472 } 473 return 0; 474 } 475 476 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 477 int offset, MemoryDeviceInfoList *dimms) 478 { 479 MachineState *machine = MACHINE(spapr); 480 int i, ret; 481 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 482 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 483 uint32_t nr_lmbs = (machine->device_memory->base + 484 memory_region_size(&machine->device_memory->mr)) / 485 lmb_size; 486 uint32_t *int_buf, *cur_index, buf_len; 487 488 /* 489 * Allocate enough buffer size to fit in ibm,dynamic-memory 490 */ 491 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 492 cur_index = int_buf = g_malloc0(buf_len); 493 int_buf[0] = cpu_to_be32(nr_lmbs); 494 cur_index++; 495 for (i = 0; i < nr_lmbs; i++) { 496 uint64_t addr = i * lmb_size; 497 uint32_t *dynamic_memory = cur_index; 498 499 if (i >= device_lmb_start) { 500 SpaprDrc *drc; 501 502 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 503 g_assert(drc); 504 505 dynamic_memory[0] = cpu_to_be32(addr >> 32); 506 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 507 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 508 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 509 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 510 if (memory_region_present(get_system_memory(), addr)) { 511 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 512 } else { 513 dynamic_memory[5] = cpu_to_be32(0); 514 } 515 } else { 516 /* 517 * LMB information for RMA, boot time RAM and gap b/n RAM and 518 * device memory region -- all these are marked as reserved 519 * and as having no valid DRC. 520 */ 521 dynamic_memory[0] = cpu_to_be32(addr >> 32); 522 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 523 dynamic_memory[2] = cpu_to_be32(0); 524 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 525 dynamic_memory[4] = cpu_to_be32(-1); 526 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 527 SPAPR_LMB_FLAGS_DRC_INVALID); 528 } 529 530 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 531 } 532 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 533 g_free(int_buf); 534 if (ret < 0) { 535 return -1; 536 } 537 return 0; 538 } 539 540 /* 541 * Adds ibm,dynamic-reconfiguration-memory node. 542 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 543 * of this device tree node. 544 */ 545 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 546 void *fdt) 547 { 548 MachineState *machine = MACHINE(spapr); 549 int ret, offset; 550 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 551 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 552 cpu_to_be32(lmb_size & 0xffffffff)}; 553 MemoryDeviceInfoList *dimms = NULL; 554 555 /* 556 * Don't create the node if there is no device memory 557 */ 558 if (machine->ram_size == machine->maxram_size) { 559 return 0; 560 } 561 562 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 563 564 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 565 sizeof(prop_lmb_size)); 566 if (ret < 0) { 567 return ret; 568 } 569 570 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 571 if (ret < 0) { 572 return ret; 573 } 574 575 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 576 if (ret < 0) { 577 return ret; 578 } 579 580 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 581 dimms = qmp_memory_device_list(); 582 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 583 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 584 } else { 585 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 586 } 587 qapi_free_MemoryDeviceInfoList(dimms); 588 589 if (ret < 0) { 590 return ret; 591 } 592 593 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 594 595 return ret; 596 } 597 598 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 599 { 600 MachineState *machine = MACHINE(spapr); 601 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 602 hwaddr mem_start, node_size; 603 int i, nb_nodes = machine->numa_state->num_nodes; 604 NodeInfo *nodes = machine->numa_state->nodes; 605 606 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 607 if (!nodes[i].node_mem) { 608 continue; 609 } 610 if (mem_start >= machine->ram_size) { 611 node_size = 0; 612 } else { 613 node_size = nodes[i].node_mem; 614 if (node_size > machine->ram_size - mem_start) { 615 node_size = machine->ram_size - mem_start; 616 } 617 } 618 if (!mem_start) { 619 /* spapr_machine_init() checks for rma_size <= node0_size 620 * already */ 621 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 622 mem_start += spapr->rma_size; 623 node_size -= spapr->rma_size; 624 } 625 for ( ; node_size; ) { 626 hwaddr sizetmp = pow2floor(node_size); 627 628 /* mem_start != 0 here */ 629 if (ctzl(mem_start) < ctzl(sizetmp)) { 630 sizetmp = 1ULL << ctzl(mem_start); 631 } 632 633 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 634 node_size -= sizetmp; 635 mem_start += sizetmp; 636 } 637 } 638 639 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 640 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 641 int ret; 642 643 g_assert(smc->dr_lmb_enabled); 644 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 645 if (ret) { 646 return ret; 647 } 648 } 649 650 return 0; 651 } 652 653 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 654 SpaprMachineState *spapr) 655 { 656 MachineState *ms = MACHINE(spapr); 657 PowerPCCPU *cpu = POWERPC_CPU(cs); 658 CPUPPCState *env = &cpu->env; 659 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 660 int index = spapr_get_vcpu_id(cpu); 661 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 662 0xffffffff, 0xffffffff}; 663 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 664 : SPAPR_TIMEBASE_FREQ; 665 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 666 uint32_t page_sizes_prop[64]; 667 size_t page_sizes_prop_size; 668 unsigned int smp_threads = ms->smp.threads; 669 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 670 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 671 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 672 SpaprDrc *drc; 673 int drc_index; 674 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 675 int i; 676 677 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 678 if (drc) { 679 drc_index = spapr_drc_index(drc); 680 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 681 } 682 683 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 684 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 685 686 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 687 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 688 env->dcache_line_size))); 689 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 690 env->dcache_line_size))); 691 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 692 env->icache_line_size))); 693 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 694 env->icache_line_size))); 695 696 if (pcc->l1_dcache_size) { 697 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 698 pcc->l1_dcache_size))); 699 } else { 700 warn_report("Unknown L1 dcache size for cpu"); 701 } 702 if (pcc->l1_icache_size) { 703 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 704 pcc->l1_icache_size))); 705 } else { 706 warn_report("Unknown L1 icache size for cpu"); 707 } 708 709 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 710 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 711 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 712 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 713 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 714 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 715 716 if (env->spr_cb[SPR_PURR].oea_read) { 717 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 718 } 719 if (env->spr_cb[SPR_SPURR].oea_read) { 720 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 721 } 722 723 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 724 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 725 segs, sizeof(segs)))); 726 } 727 728 /* Advertise VSX (vector extensions) if available 729 * 1 == VMX / Altivec available 730 * 2 == VSX available 731 * 732 * Only CPUs for which we create core types in spapr_cpu_core.c 733 * are possible, and all of those have VMX */ 734 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 735 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 736 } else { 737 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 738 } 739 740 /* Advertise DFP (Decimal Floating Point) if available 741 * 0 / no property == no DFP 742 * 1 == DFP available */ 743 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 744 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 745 } 746 747 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 748 sizeof(page_sizes_prop)); 749 if (page_sizes_prop_size) { 750 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 751 page_sizes_prop, page_sizes_prop_size))); 752 } 753 754 spapr_dt_pa_features(spapr, cpu, fdt, offset); 755 756 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 757 cs->cpu_index / vcpus_per_socket))); 758 759 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 760 pft_size_prop, sizeof(pft_size_prop)))); 761 762 if (ms->numa_state->num_nodes > 1) { 763 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 764 } 765 766 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 767 768 if (pcc->radix_page_info) { 769 for (i = 0; i < pcc->radix_page_info->count; i++) { 770 radix_AP_encodings[i] = 771 cpu_to_be32(pcc->radix_page_info->entries[i]); 772 } 773 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 774 radix_AP_encodings, 775 pcc->radix_page_info->count * 776 sizeof(radix_AP_encodings[0])))); 777 } 778 779 /* 780 * We set this property to let the guest know that it can use the large 781 * decrementer and its width in bits. 782 */ 783 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 784 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 785 pcc->lrg_decr_bits))); 786 } 787 788 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 789 { 790 CPUState **rev; 791 CPUState *cs; 792 int n_cpus; 793 int cpus_offset; 794 char *nodename; 795 int i; 796 797 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 798 _FDT(cpus_offset); 799 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 800 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 801 802 /* 803 * We walk the CPUs in reverse order to ensure that CPU DT nodes 804 * created by fdt_add_subnode() end up in the right order in FDT 805 * for the guest kernel the enumerate the CPUs correctly. 806 * 807 * The CPU list cannot be traversed in reverse order, so we need 808 * to do extra work. 809 */ 810 n_cpus = 0; 811 rev = NULL; 812 CPU_FOREACH(cs) { 813 rev = g_renew(CPUState *, rev, n_cpus + 1); 814 rev[n_cpus++] = cs; 815 } 816 817 for (i = n_cpus - 1; i >= 0; i--) { 818 CPUState *cs = rev[i]; 819 PowerPCCPU *cpu = POWERPC_CPU(cs); 820 int index = spapr_get_vcpu_id(cpu); 821 DeviceClass *dc = DEVICE_GET_CLASS(cs); 822 int offset; 823 824 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 825 continue; 826 } 827 828 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 829 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 830 g_free(nodename); 831 _FDT(offset); 832 spapr_dt_cpu(cs, fdt, offset, spapr); 833 } 834 835 g_free(rev); 836 } 837 838 static int spapr_dt_rng(void *fdt) 839 { 840 int node; 841 int ret; 842 843 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 844 if (node <= 0) { 845 return -1; 846 } 847 ret = fdt_setprop_string(fdt, node, "device_type", 848 "ibm,platform-facilities"); 849 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 850 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 851 852 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 853 if (node <= 0) { 854 return -1; 855 } 856 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 857 858 return ret ? -1 : 0; 859 } 860 861 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 862 { 863 MachineState *ms = MACHINE(spapr); 864 int rtas; 865 GString *hypertas = g_string_sized_new(256); 866 GString *qemu_hypertas = g_string_sized_new(256); 867 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 868 memory_region_size(&MACHINE(spapr)->device_memory->mr); 869 uint32_t lrdr_capacity[] = { 870 cpu_to_be32(max_device_addr >> 32), 871 cpu_to_be32(max_device_addr & 0xffffffff), 872 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 873 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 874 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 875 }; 876 877 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 878 879 /* hypertas */ 880 add_str(hypertas, "hcall-pft"); 881 add_str(hypertas, "hcall-term"); 882 add_str(hypertas, "hcall-dabr"); 883 add_str(hypertas, "hcall-interrupt"); 884 add_str(hypertas, "hcall-tce"); 885 add_str(hypertas, "hcall-vio"); 886 add_str(hypertas, "hcall-splpar"); 887 add_str(hypertas, "hcall-join"); 888 add_str(hypertas, "hcall-bulk"); 889 add_str(hypertas, "hcall-set-mode"); 890 add_str(hypertas, "hcall-sprg0"); 891 add_str(hypertas, "hcall-copy"); 892 add_str(hypertas, "hcall-debug"); 893 add_str(hypertas, "hcall-vphn"); 894 add_str(qemu_hypertas, "hcall-memop1"); 895 896 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 897 add_str(hypertas, "hcall-multi-tce"); 898 } 899 900 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 901 add_str(hypertas, "hcall-hpt-resize"); 902 } 903 904 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 905 hypertas->str, hypertas->len)); 906 g_string_free(hypertas, TRUE); 907 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 908 qemu_hypertas->str, qemu_hypertas->len)); 909 g_string_free(qemu_hypertas, TRUE); 910 911 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 912 913 /* 914 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 915 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 916 * 917 * The system reset requirements are driven by existing Linux and PowerVM 918 * implementation which (contrary to PAPR) saves r3 in the error log 919 * structure like machine check, so Linux expects to find the saved r3 920 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 921 * does not look at the error value). 922 * 923 * System reset interrupts are not subject to interlock like machine 924 * check, so this memory area could be corrupted if the sreset is 925 * interrupted by a machine check (or vice versa) if it was shared. To 926 * prevent this, system reset uses per-CPU areas for the sreset save 927 * area. A system reset that interrupts a system reset handler could 928 * still overwrite this area, but Linux doesn't try to recover in that 929 * case anyway. 930 * 931 * The extra 8 bytes is required because Linux's FWNMI error log check 932 * is off-by-one. 933 */ 934 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX + 935 ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t))); 936 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 937 RTAS_ERROR_LOG_MAX)); 938 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 939 RTAS_EVENT_SCAN_RATE)); 940 941 g_assert(msi_nonbroken); 942 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 943 944 /* 945 * According to PAPR, rtas ibm,os-term does not guarantee a return 946 * back to the guest cpu. 947 * 948 * While an additional ibm,extended-os-term property indicates 949 * that rtas call return will always occur. Set this property. 950 */ 951 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 952 953 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 954 lrdr_capacity, sizeof(lrdr_capacity))); 955 956 spapr_dt_rtas_tokens(fdt, rtas); 957 } 958 959 /* 960 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 961 * and the XIVE features that the guest may request and thus the valid 962 * values for bytes 23..26 of option vector 5: 963 */ 964 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 965 int chosen) 966 { 967 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 968 969 char val[2 * 4] = { 970 23, 0x00, /* XICS / XIVE mode */ 971 24, 0x00, /* Hash/Radix, filled in below. */ 972 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 973 26, 0x40, /* Radix options: GTSE == yes. */ 974 }; 975 976 if (spapr->irq->xics && spapr->irq->xive) { 977 val[1] = SPAPR_OV5_XIVE_BOTH; 978 } else if (spapr->irq->xive) { 979 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 980 } else { 981 assert(spapr->irq->xics); 982 val[1] = SPAPR_OV5_XIVE_LEGACY; 983 } 984 985 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 986 first_ppc_cpu->compat_pvr)) { 987 /* 988 * If we're in a pre POWER9 compat mode then the guest should 989 * do hash and use the legacy interrupt mode 990 */ 991 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 992 val[3] = 0x00; /* Hash */ 993 } else if (kvm_enabled()) { 994 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 995 val[3] = 0x80; /* OV5_MMU_BOTH */ 996 } else if (kvmppc_has_cap_mmu_radix()) { 997 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 998 } else { 999 val[3] = 0x00; /* Hash */ 1000 } 1001 } else { 1002 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1003 val[3] = 0xC0; 1004 } 1005 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1006 val, sizeof(val))); 1007 } 1008 1009 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1010 { 1011 MachineState *machine = MACHINE(spapr); 1012 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1013 int chosen; 1014 1015 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1016 1017 if (reset) { 1018 const char *boot_device = machine->boot_order; 1019 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1020 size_t cb = 0; 1021 char *bootlist = get_boot_devices_list(&cb); 1022 1023 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1024 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1025 machine->kernel_cmdline)); 1026 } 1027 1028 if (spapr->initrd_size) { 1029 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1030 spapr->initrd_base)); 1031 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1032 spapr->initrd_base + spapr->initrd_size)); 1033 } 1034 1035 if (spapr->kernel_size) { 1036 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1037 cpu_to_be64(spapr->kernel_size) }; 1038 1039 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1040 &kprop, sizeof(kprop))); 1041 if (spapr->kernel_le) { 1042 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1043 } 1044 } 1045 if (boot_menu) { 1046 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1047 } 1048 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1049 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1050 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1051 1052 if (cb && bootlist) { 1053 int i; 1054 1055 for (i = 0; i < cb; i++) { 1056 if (bootlist[i] == '\n') { 1057 bootlist[i] = ' '; 1058 } 1059 } 1060 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1061 } 1062 1063 if (boot_device && strlen(boot_device)) { 1064 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1065 } 1066 1067 if (!spapr->has_graphics && stdout_path) { 1068 /* 1069 * "linux,stdout-path" and "stdout" properties are 1070 * deprecated by linux kernel. New platforms should only 1071 * use the "stdout-path" property. Set the new property 1072 * and continue using older property to remain compatible 1073 * with the existing firmware. 1074 */ 1075 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1076 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1077 } 1078 1079 /* 1080 * We can deal with BAR reallocation just fine, advertise it 1081 * to the guest 1082 */ 1083 if (smc->linux_pci_probe) { 1084 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1085 } 1086 1087 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1088 1089 g_free(stdout_path); 1090 g_free(bootlist); 1091 } 1092 1093 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1094 } 1095 1096 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1097 { 1098 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1099 * KVM to work under pHyp with some guest co-operation */ 1100 int hypervisor; 1101 uint8_t hypercall[16]; 1102 1103 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1104 /* indicate KVM hypercall interface */ 1105 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1106 if (kvmppc_has_cap_fixup_hcalls()) { 1107 /* 1108 * Older KVM versions with older guest kernels were broken 1109 * with the magic page, don't allow the guest to map it. 1110 */ 1111 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1112 sizeof(hypercall))) { 1113 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1114 hypercall, sizeof(hypercall))); 1115 } 1116 } 1117 } 1118 1119 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1120 { 1121 MachineState *machine = MACHINE(spapr); 1122 MachineClass *mc = MACHINE_GET_CLASS(machine); 1123 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1124 uint32_t root_drc_type_mask = 0; 1125 int ret; 1126 void *fdt; 1127 SpaprPhbState *phb; 1128 char *buf; 1129 1130 fdt = g_malloc0(space); 1131 _FDT((fdt_create_empty_tree(fdt, space))); 1132 1133 /* Root node */ 1134 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1135 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1136 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1137 1138 /* Guest UUID & Name*/ 1139 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1140 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1141 if (qemu_uuid_set) { 1142 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1143 } 1144 g_free(buf); 1145 1146 if (qemu_get_vm_name()) { 1147 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1148 qemu_get_vm_name())); 1149 } 1150 1151 /* Host Model & Serial Number */ 1152 if (spapr->host_model) { 1153 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1154 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1155 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1156 g_free(buf); 1157 } 1158 1159 if (spapr->host_serial) { 1160 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1161 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1162 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1163 g_free(buf); 1164 } 1165 1166 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1167 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1168 1169 /* /interrupt controller */ 1170 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1171 1172 ret = spapr_dt_memory(spapr, fdt); 1173 if (ret < 0) { 1174 error_report("couldn't setup memory nodes in fdt"); 1175 exit(1); 1176 } 1177 1178 /* /vdevice */ 1179 spapr_dt_vdevice(spapr->vio_bus, fdt); 1180 1181 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1182 ret = spapr_dt_rng(fdt); 1183 if (ret < 0) { 1184 error_report("could not set up rng device in the fdt"); 1185 exit(1); 1186 } 1187 } 1188 1189 QLIST_FOREACH(phb, &spapr->phbs, list) { 1190 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1191 if (ret < 0) { 1192 error_report("couldn't setup PCI devices in fdt"); 1193 exit(1); 1194 } 1195 } 1196 1197 spapr_dt_cpus(fdt, spapr); 1198 1199 /* ibm,drc-indexes and friends */ 1200 if (smc->dr_lmb_enabled) { 1201 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1202 } 1203 if (smc->dr_phb_enabled) { 1204 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1205 } 1206 if (mc->nvdimm_supported) { 1207 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1208 } 1209 if (root_drc_type_mask) { 1210 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1211 } 1212 1213 if (mc->has_hotpluggable_cpus) { 1214 int offset = fdt_path_offset(fdt, "/cpus"); 1215 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1216 if (ret < 0) { 1217 error_report("Couldn't set up CPU DR device tree properties"); 1218 exit(1); 1219 } 1220 } 1221 1222 /* /event-sources */ 1223 spapr_dt_events(spapr, fdt); 1224 1225 /* /rtas */ 1226 spapr_dt_rtas(spapr, fdt); 1227 1228 /* /chosen */ 1229 spapr_dt_chosen(spapr, fdt, reset); 1230 1231 /* /hypervisor */ 1232 if (kvm_enabled()) { 1233 spapr_dt_hypervisor(spapr, fdt); 1234 } 1235 1236 /* Build memory reserve map */ 1237 if (reset) { 1238 if (spapr->kernel_size) { 1239 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1240 spapr->kernel_size))); 1241 } 1242 if (spapr->initrd_size) { 1243 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1244 spapr->initrd_size))); 1245 } 1246 } 1247 1248 /* NVDIMM devices */ 1249 if (mc->nvdimm_supported) { 1250 spapr_dt_persistent_memory(spapr, fdt); 1251 } 1252 1253 return fdt; 1254 } 1255 1256 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1257 { 1258 SpaprMachineState *spapr = opaque; 1259 1260 return (addr & 0x0fffffff) + spapr->kernel_addr; 1261 } 1262 1263 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1264 PowerPCCPU *cpu) 1265 { 1266 CPUPPCState *env = &cpu->env; 1267 1268 /* The TCG path should also be holding the BQL at this point */ 1269 g_assert(qemu_mutex_iothread_locked()); 1270 1271 if (msr_pr) { 1272 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1273 env->gpr[3] = H_PRIVILEGE; 1274 } else { 1275 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1276 } 1277 } 1278 1279 struct LPCRSyncState { 1280 target_ulong value; 1281 target_ulong mask; 1282 }; 1283 1284 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1285 { 1286 struct LPCRSyncState *s = arg.host_ptr; 1287 PowerPCCPU *cpu = POWERPC_CPU(cs); 1288 CPUPPCState *env = &cpu->env; 1289 target_ulong lpcr; 1290 1291 cpu_synchronize_state(cs); 1292 lpcr = env->spr[SPR_LPCR]; 1293 lpcr &= ~s->mask; 1294 lpcr |= s->value; 1295 ppc_store_lpcr(cpu, lpcr); 1296 } 1297 1298 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1299 { 1300 CPUState *cs; 1301 struct LPCRSyncState s = { 1302 .value = value, 1303 .mask = mask 1304 }; 1305 CPU_FOREACH(cs) { 1306 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1307 } 1308 } 1309 1310 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1311 { 1312 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1313 1314 /* Copy PATE1:GR into PATE0:HR */ 1315 entry->dw0 = spapr->patb_entry & PATE0_HR; 1316 entry->dw1 = spapr->patb_entry; 1317 } 1318 1319 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1320 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1321 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1322 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1323 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1324 1325 /* 1326 * Get the fd to access the kernel htab, re-opening it if necessary 1327 */ 1328 static int get_htab_fd(SpaprMachineState *spapr) 1329 { 1330 Error *local_err = NULL; 1331 1332 if (spapr->htab_fd >= 0) { 1333 return spapr->htab_fd; 1334 } 1335 1336 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1337 if (spapr->htab_fd < 0) { 1338 error_report_err(local_err); 1339 } 1340 1341 return spapr->htab_fd; 1342 } 1343 1344 void close_htab_fd(SpaprMachineState *spapr) 1345 { 1346 if (spapr->htab_fd >= 0) { 1347 close(spapr->htab_fd); 1348 } 1349 spapr->htab_fd = -1; 1350 } 1351 1352 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1353 { 1354 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1355 1356 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1357 } 1358 1359 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1360 { 1361 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1362 1363 assert(kvm_enabled()); 1364 1365 if (!spapr->htab) { 1366 return 0; 1367 } 1368 1369 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1370 } 1371 1372 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1373 hwaddr ptex, int n) 1374 { 1375 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1376 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1377 1378 if (!spapr->htab) { 1379 /* 1380 * HTAB is controlled by KVM. Fetch into temporary buffer 1381 */ 1382 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1383 kvmppc_read_hptes(hptes, ptex, n); 1384 return hptes; 1385 } 1386 1387 /* 1388 * HTAB is controlled by QEMU. Just point to the internally 1389 * accessible PTEG. 1390 */ 1391 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1392 } 1393 1394 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1395 const ppc_hash_pte64_t *hptes, 1396 hwaddr ptex, int n) 1397 { 1398 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1399 1400 if (!spapr->htab) { 1401 g_free((void *)hptes); 1402 } 1403 1404 /* Nothing to do for qemu managed HPT */ 1405 } 1406 1407 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1408 uint64_t pte0, uint64_t pte1) 1409 { 1410 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1411 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1412 1413 if (!spapr->htab) { 1414 kvmppc_write_hpte(ptex, pte0, pte1); 1415 } else { 1416 if (pte0 & HPTE64_V_VALID) { 1417 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1418 /* 1419 * When setting valid, we write PTE1 first. This ensures 1420 * proper synchronization with the reading code in 1421 * ppc_hash64_pteg_search() 1422 */ 1423 smp_wmb(); 1424 stq_p(spapr->htab + offset, pte0); 1425 } else { 1426 stq_p(spapr->htab + offset, pte0); 1427 /* 1428 * When clearing it we set PTE0 first. This ensures proper 1429 * synchronization with the reading code in 1430 * ppc_hash64_pteg_search() 1431 */ 1432 smp_wmb(); 1433 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1434 } 1435 } 1436 } 1437 1438 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1439 uint64_t pte1) 1440 { 1441 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1442 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1443 1444 if (!spapr->htab) { 1445 /* There should always be a hash table when this is called */ 1446 error_report("spapr_hpte_set_c called with no hash table !"); 1447 return; 1448 } 1449 1450 /* The HW performs a non-atomic byte update */ 1451 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1452 } 1453 1454 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1455 uint64_t pte1) 1456 { 1457 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1458 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1459 1460 if (!spapr->htab) { 1461 /* There should always be a hash table when this is called */ 1462 error_report("spapr_hpte_set_r called with no hash table !"); 1463 return; 1464 } 1465 1466 /* The HW performs a non-atomic byte update */ 1467 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1468 } 1469 1470 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1471 { 1472 int shift; 1473 1474 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1475 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1476 * that's much more than is needed for Linux guests */ 1477 shift = ctz64(pow2ceil(ramsize)) - 7; 1478 shift = MAX(shift, 18); /* Minimum architected size */ 1479 shift = MIN(shift, 46); /* Maximum architected size */ 1480 return shift; 1481 } 1482 1483 void spapr_free_hpt(SpaprMachineState *spapr) 1484 { 1485 g_free(spapr->htab); 1486 spapr->htab = NULL; 1487 spapr->htab_shift = 0; 1488 close_htab_fd(spapr); 1489 } 1490 1491 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1492 { 1493 ERRP_GUARD(); 1494 long rc; 1495 1496 /* Clean up any HPT info from a previous boot */ 1497 spapr_free_hpt(spapr); 1498 1499 rc = kvmppc_reset_htab(shift); 1500 1501 if (rc == -EOPNOTSUPP) { 1502 error_setg(errp, "HPT not supported in nested guests"); 1503 return -EOPNOTSUPP; 1504 } 1505 1506 if (rc < 0) { 1507 /* kernel-side HPT needed, but couldn't allocate one */ 1508 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1509 shift); 1510 error_append_hint(errp, "Try smaller maxmem?\n"); 1511 return -errno; 1512 } else if (rc > 0) { 1513 /* kernel-side HPT allocated */ 1514 if (rc != shift) { 1515 error_setg(errp, 1516 "Requested order %d HPT, but kernel allocated order %ld", 1517 shift, rc); 1518 error_append_hint(errp, "Try smaller maxmem?\n"); 1519 return -ENOSPC; 1520 } 1521 1522 spapr->htab_shift = shift; 1523 spapr->htab = NULL; 1524 } else { 1525 /* kernel-side HPT not needed, allocate in userspace instead */ 1526 size_t size = 1ULL << shift; 1527 int i; 1528 1529 spapr->htab = qemu_memalign(size, size); 1530 memset(spapr->htab, 0, size); 1531 spapr->htab_shift = shift; 1532 1533 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1534 DIRTY_HPTE(HPTE(spapr->htab, i)); 1535 } 1536 } 1537 /* We're setting up a hash table, so that means we're not radix */ 1538 spapr->patb_entry = 0; 1539 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1540 return 0; 1541 } 1542 1543 void spapr_setup_hpt(SpaprMachineState *spapr) 1544 { 1545 int hpt_shift; 1546 1547 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1548 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1549 } else { 1550 uint64_t current_ram_size; 1551 1552 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1553 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1554 } 1555 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1556 1557 if (kvm_enabled()) { 1558 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1559 1560 /* Check our RMA fits in the possible VRMA */ 1561 if (vrma_limit < spapr->rma_size) { 1562 error_report("Unable to create %" HWADDR_PRIu 1563 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1564 spapr->rma_size / MiB, vrma_limit / MiB); 1565 exit(EXIT_FAILURE); 1566 } 1567 } 1568 } 1569 1570 static void spapr_machine_reset(MachineState *machine) 1571 { 1572 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1573 PowerPCCPU *first_ppc_cpu; 1574 hwaddr fdt_addr; 1575 void *fdt; 1576 int rc; 1577 1578 pef_kvm_reset(machine->cgs, &error_fatal); 1579 spapr_caps_apply(spapr); 1580 1581 first_ppc_cpu = POWERPC_CPU(first_cpu); 1582 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1583 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1584 spapr->max_compat_pvr)) { 1585 /* 1586 * If using KVM with radix mode available, VCPUs can be started 1587 * without a HPT because KVM will start them in radix mode. 1588 * Set the GR bit in PATE so that we know there is no HPT. 1589 */ 1590 spapr->patb_entry = PATE1_GR; 1591 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1592 } else { 1593 spapr_setup_hpt(spapr); 1594 } 1595 1596 qemu_devices_reset(); 1597 1598 spapr_ovec_cleanup(spapr->ov5_cas); 1599 spapr->ov5_cas = spapr_ovec_new(); 1600 1601 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1602 1603 /* 1604 * This is fixing some of the default configuration of the XIVE 1605 * devices. To be called after the reset of the machine devices. 1606 */ 1607 spapr_irq_reset(spapr, &error_fatal); 1608 1609 /* 1610 * There is no CAS under qtest. Simulate one to please the code that 1611 * depends on spapr->ov5_cas. This is especially needed to test device 1612 * unplug, so we do that before resetting the DRCs. 1613 */ 1614 if (qtest_enabled()) { 1615 spapr_ovec_cleanup(spapr->ov5_cas); 1616 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1617 } 1618 1619 /* DRC reset may cause a device to be unplugged. This will cause troubles 1620 * if this device is used by another device (eg, a running vhost backend 1621 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1622 * situations, we reset DRCs after all devices have been reset. 1623 */ 1624 spapr_drc_reset_all(spapr); 1625 1626 spapr_clear_pending_events(spapr); 1627 1628 /* 1629 * We place the device tree and RTAS just below either the top of the RMA, 1630 * or just below 2GB, whichever is lower, so that it can be 1631 * processed with 32-bit real mode code if necessary 1632 */ 1633 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1634 1635 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1636 1637 rc = fdt_pack(fdt); 1638 1639 /* Should only fail if we've built a corrupted tree */ 1640 assert(rc == 0); 1641 1642 /* Load the fdt */ 1643 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1644 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1645 g_free(spapr->fdt_blob); 1646 spapr->fdt_size = fdt_totalsize(fdt); 1647 spapr->fdt_initial_size = spapr->fdt_size; 1648 spapr->fdt_blob = fdt; 1649 1650 /* Set up the entry state */ 1651 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); 1652 first_ppc_cpu->env.gpr[5] = 0; 1653 1654 spapr->fwnmi_system_reset_addr = -1; 1655 spapr->fwnmi_machine_check_addr = -1; 1656 spapr->fwnmi_machine_check_interlock = -1; 1657 1658 /* Signal all vCPUs waiting on this condition */ 1659 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1660 1661 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1662 } 1663 1664 static void spapr_create_nvram(SpaprMachineState *spapr) 1665 { 1666 DeviceState *dev = qdev_new("spapr-nvram"); 1667 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1668 1669 if (dinfo) { 1670 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1671 &error_fatal); 1672 } 1673 1674 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1675 1676 spapr->nvram = (struct SpaprNvram *)dev; 1677 } 1678 1679 static void spapr_rtc_create(SpaprMachineState *spapr) 1680 { 1681 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1682 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1683 &error_fatal, NULL); 1684 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1685 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1686 "date"); 1687 } 1688 1689 /* Returns whether we want to use VGA or not */ 1690 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1691 { 1692 switch (vga_interface_type) { 1693 case VGA_NONE: 1694 return false; 1695 case VGA_DEVICE: 1696 return true; 1697 case VGA_STD: 1698 case VGA_VIRTIO: 1699 case VGA_CIRRUS: 1700 return pci_vga_init(pci_bus) != NULL; 1701 default: 1702 error_setg(errp, 1703 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1704 return false; 1705 } 1706 } 1707 1708 static int spapr_pre_load(void *opaque) 1709 { 1710 int rc; 1711 1712 rc = spapr_caps_pre_load(opaque); 1713 if (rc) { 1714 return rc; 1715 } 1716 1717 return 0; 1718 } 1719 1720 static int spapr_post_load(void *opaque, int version_id) 1721 { 1722 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1723 int err = 0; 1724 1725 err = spapr_caps_post_migration(spapr); 1726 if (err) { 1727 return err; 1728 } 1729 1730 /* 1731 * In earlier versions, there was no separate qdev for the PAPR 1732 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1733 * So when migrating from those versions, poke the incoming offset 1734 * value into the RTC device 1735 */ 1736 if (version_id < 3) { 1737 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1738 if (err) { 1739 return err; 1740 } 1741 } 1742 1743 if (kvm_enabled() && spapr->patb_entry) { 1744 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1745 bool radix = !!(spapr->patb_entry & PATE1_GR); 1746 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1747 1748 /* 1749 * Update LPCR:HR and UPRT as they may not be set properly in 1750 * the stream 1751 */ 1752 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1753 LPCR_HR | LPCR_UPRT); 1754 1755 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1756 if (err) { 1757 error_report("Process table config unsupported by the host"); 1758 return -EINVAL; 1759 } 1760 } 1761 1762 err = spapr_irq_post_load(spapr, version_id); 1763 if (err) { 1764 return err; 1765 } 1766 1767 return err; 1768 } 1769 1770 static int spapr_pre_save(void *opaque) 1771 { 1772 int rc; 1773 1774 rc = spapr_caps_pre_save(opaque); 1775 if (rc) { 1776 return rc; 1777 } 1778 1779 return 0; 1780 } 1781 1782 static bool version_before_3(void *opaque, int version_id) 1783 { 1784 return version_id < 3; 1785 } 1786 1787 static bool spapr_pending_events_needed(void *opaque) 1788 { 1789 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1790 return !QTAILQ_EMPTY(&spapr->pending_events); 1791 } 1792 1793 static const VMStateDescription vmstate_spapr_event_entry = { 1794 .name = "spapr_event_log_entry", 1795 .version_id = 1, 1796 .minimum_version_id = 1, 1797 .fields = (VMStateField[]) { 1798 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1799 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1800 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1801 NULL, extended_length), 1802 VMSTATE_END_OF_LIST() 1803 }, 1804 }; 1805 1806 static const VMStateDescription vmstate_spapr_pending_events = { 1807 .name = "spapr_pending_events", 1808 .version_id = 1, 1809 .minimum_version_id = 1, 1810 .needed = spapr_pending_events_needed, 1811 .fields = (VMStateField[]) { 1812 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1813 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1814 VMSTATE_END_OF_LIST() 1815 }, 1816 }; 1817 1818 static bool spapr_ov5_cas_needed(void *opaque) 1819 { 1820 SpaprMachineState *spapr = opaque; 1821 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1822 bool cas_needed; 1823 1824 /* Prior to the introduction of SpaprOptionVector, we had two option 1825 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1826 * Both of these options encode machine topology into the device-tree 1827 * in such a way that the now-booted OS should still be able to interact 1828 * appropriately with QEMU regardless of what options were actually 1829 * negotiatied on the source side. 1830 * 1831 * As such, we can avoid migrating the CAS-negotiated options if these 1832 * are the only options available on the current machine/platform. 1833 * Since these are the only options available for pseries-2.7 and 1834 * earlier, this allows us to maintain old->new/new->old migration 1835 * compatibility. 1836 * 1837 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1838 * via default pseries-2.8 machines and explicit command-line parameters. 1839 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1840 * of the actual CAS-negotiated values to continue working properly. For 1841 * example, availability of memory unplug depends on knowing whether 1842 * OV5_HP_EVT was negotiated via CAS. 1843 * 1844 * Thus, for any cases where the set of available CAS-negotiatable 1845 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1846 * include the CAS-negotiated options in the migration stream, unless 1847 * if they affect boot time behaviour only. 1848 */ 1849 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1850 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1851 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1852 1853 /* We need extra information if we have any bits outside the mask 1854 * defined above */ 1855 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1856 1857 spapr_ovec_cleanup(ov5_mask); 1858 1859 return cas_needed; 1860 } 1861 1862 static const VMStateDescription vmstate_spapr_ov5_cas = { 1863 .name = "spapr_option_vector_ov5_cas", 1864 .version_id = 1, 1865 .minimum_version_id = 1, 1866 .needed = spapr_ov5_cas_needed, 1867 .fields = (VMStateField[]) { 1868 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1869 vmstate_spapr_ovec, SpaprOptionVector), 1870 VMSTATE_END_OF_LIST() 1871 }, 1872 }; 1873 1874 static bool spapr_patb_entry_needed(void *opaque) 1875 { 1876 SpaprMachineState *spapr = opaque; 1877 1878 return !!spapr->patb_entry; 1879 } 1880 1881 static const VMStateDescription vmstate_spapr_patb_entry = { 1882 .name = "spapr_patb_entry", 1883 .version_id = 1, 1884 .minimum_version_id = 1, 1885 .needed = spapr_patb_entry_needed, 1886 .fields = (VMStateField[]) { 1887 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1888 VMSTATE_END_OF_LIST() 1889 }, 1890 }; 1891 1892 static bool spapr_irq_map_needed(void *opaque) 1893 { 1894 SpaprMachineState *spapr = opaque; 1895 1896 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1897 } 1898 1899 static const VMStateDescription vmstate_spapr_irq_map = { 1900 .name = "spapr_irq_map", 1901 .version_id = 1, 1902 .minimum_version_id = 1, 1903 .needed = spapr_irq_map_needed, 1904 .fields = (VMStateField[]) { 1905 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1906 VMSTATE_END_OF_LIST() 1907 }, 1908 }; 1909 1910 static bool spapr_dtb_needed(void *opaque) 1911 { 1912 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1913 1914 return smc->update_dt_enabled; 1915 } 1916 1917 static int spapr_dtb_pre_load(void *opaque) 1918 { 1919 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1920 1921 g_free(spapr->fdt_blob); 1922 spapr->fdt_blob = NULL; 1923 spapr->fdt_size = 0; 1924 1925 return 0; 1926 } 1927 1928 static const VMStateDescription vmstate_spapr_dtb = { 1929 .name = "spapr_dtb", 1930 .version_id = 1, 1931 .minimum_version_id = 1, 1932 .needed = spapr_dtb_needed, 1933 .pre_load = spapr_dtb_pre_load, 1934 .fields = (VMStateField[]) { 1935 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1936 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1937 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1938 fdt_size), 1939 VMSTATE_END_OF_LIST() 1940 }, 1941 }; 1942 1943 static bool spapr_fwnmi_needed(void *opaque) 1944 { 1945 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1946 1947 return spapr->fwnmi_machine_check_addr != -1; 1948 } 1949 1950 static int spapr_fwnmi_pre_save(void *opaque) 1951 { 1952 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1953 1954 /* 1955 * Check if machine check handling is in progress and print a 1956 * warning message. 1957 */ 1958 if (spapr->fwnmi_machine_check_interlock != -1) { 1959 warn_report("A machine check is being handled during migration. The" 1960 "handler may run and log hardware error on the destination"); 1961 } 1962 1963 return 0; 1964 } 1965 1966 static const VMStateDescription vmstate_spapr_fwnmi = { 1967 .name = "spapr_fwnmi", 1968 .version_id = 1, 1969 .minimum_version_id = 1, 1970 .needed = spapr_fwnmi_needed, 1971 .pre_save = spapr_fwnmi_pre_save, 1972 .fields = (VMStateField[]) { 1973 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 1974 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 1975 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 1976 VMSTATE_END_OF_LIST() 1977 }, 1978 }; 1979 1980 static const VMStateDescription vmstate_spapr = { 1981 .name = "spapr", 1982 .version_id = 3, 1983 .minimum_version_id = 1, 1984 .pre_load = spapr_pre_load, 1985 .post_load = spapr_post_load, 1986 .pre_save = spapr_pre_save, 1987 .fields = (VMStateField[]) { 1988 /* used to be @next_irq */ 1989 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1990 1991 /* RTC offset */ 1992 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 1993 1994 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 1995 VMSTATE_END_OF_LIST() 1996 }, 1997 .subsections = (const VMStateDescription*[]) { 1998 &vmstate_spapr_ov5_cas, 1999 &vmstate_spapr_patb_entry, 2000 &vmstate_spapr_pending_events, 2001 &vmstate_spapr_cap_htm, 2002 &vmstate_spapr_cap_vsx, 2003 &vmstate_spapr_cap_dfp, 2004 &vmstate_spapr_cap_cfpc, 2005 &vmstate_spapr_cap_sbbc, 2006 &vmstate_spapr_cap_ibs, 2007 &vmstate_spapr_cap_hpt_maxpagesize, 2008 &vmstate_spapr_irq_map, 2009 &vmstate_spapr_cap_nested_kvm_hv, 2010 &vmstate_spapr_dtb, 2011 &vmstate_spapr_cap_large_decr, 2012 &vmstate_spapr_cap_ccf_assist, 2013 &vmstate_spapr_cap_fwnmi, 2014 &vmstate_spapr_fwnmi, 2015 NULL 2016 } 2017 }; 2018 2019 static int htab_save_setup(QEMUFile *f, void *opaque) 2020 { 2021 SpaprMachineState *spapr = opaque; 2022 2023 /* "Iteration" header */ 2024 if (!spapr->htab_shift) { 2025 qemu_put_be32(f, -1); 2026 } else { 2027 qemu_put_be32(f, spapr->htab_shift); 2028 } 2029 2030 if (spapr->htab) { 2031 spapr->htab_save_index = 0; 2032 spapr->htab_first_pass = true; 2033 } else { 2034 if (spapr->htab_shift) { 2035 assert(kvm_enabled()); 2036 } 2037 } 2038 2039 2040 return 0; 2041 } 2042 2043 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2044 int chunkstart, int n_valid, int n_invalid) 2045 { 2046 qemu_put_be32(f, chunkstart); 2047 qemu_put_be16(f, n_valid); 2048 qemu_put_be16(f, n_invalid); 2049 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2050 HASH_PTE_SIZE_64 * n_valid); 2051 } 2052 2053 static void htab_save_end_marker(QEMUFile *f) 2054 { 2055 qemu_put_be32(f, 0); 2056 qemu_put_be16(f, 0); 2057 qemu_put_be16(f, 0); 2058 } 2059 2060 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2061 int64_t max_ns) 2062 { 2063 bool has_timeout = max_ns != -1; 2064 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2065 int index = spapr->htab_save_index; 2066 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2067 2068 assert(spapr->htab_first_pass); 2069 2070 do { 2071 int chunkstart; 2072 2073 /* Consume invalid HPTEs */ 2074 while ((index < htabslots) 2075 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2076 CLEAN_HPTE(HPTE(spapr->htab, index)); 2077 index++; 2078 } 2079 2080 /* Consume valid HPTEs */ 2081 chunkstart = index; 2082 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2083 && HPTE_VALID(HPTE(spapr->htab, index))) { 2084 CLEAN_HPTE(HPTE(spapr->htab, index)); 2085 index++; 2086 } 2087 2088 if (index > chunkstart) { 2089 int n_valid = index - chunkstart; 2090 2091 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2092 2093 if (has_timeout && 2094 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2095 break; 2096 } 2097 } 2098 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2099 2100 if (index >= htabslots) { 2101 assert(index == htabslots); 2102 index = 0; 2103 spapr->htab_first_pass = false; 2104 } 2105 spapr->htab_save_index = index; 2106 } 2107 2108 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2109 int64_t max_ns) 2110 { 2111 bool final = max_ns < 0; 2112 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2113 int examined = 0, sent = 0; 2114 int index = spapr->htab_save_index; 2115 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2116 2117 assert(!spapr->htab_first_pass); 2118 2119 do { 2120 int chunkstart, invalidstart; 2121 2122 /* Consume non-dirty HPTEs */ 2123 while ((index < htabslots) 2124 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2125 index++; 2126 examined++; 2127 } 2128 2129 chunkstart = index; 2130 /* Consume valid dirty HPTEs */ 2131 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2132 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2133 && HPTE_VALID(HPTE(spapr->htab, index))) { 2134 CLEAN_HPTE(HPTE(spapr->htab, index)); 2135 index++; 2136 examined++; 2137 } 2138 2139 invalidstart = index; 2140 /* Consume invalid dirty HPTEs */ 2141 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2142 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2143 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2144 CLEAN_HPTE(HPTE(spapr->htab, index)); 2145 index++; 2146 examined++; 2147 } 2148 2149 if (index > chunkstart) { 2150 int n_valid = invalidstart - chunkstart; 2151 int n_invalid = index - invalidstart; 2152 2153 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2154 sent += index - chunkstart; 2155 2156 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2157 break; 2158 } 2159 } 2160 2161 if (examined >= htabslots) { 2162 break; 2163 } 2164 2165 if (index >= htabslots) { 2166 assert(index == htabslots); 2167 index = 0; 2168 } 2169 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2170 2171 if (index >= htabslots) { 2172 assert(index == htabslots); 2173 index = 0; 2174 } 2175 2176 spapr->htab_save_index = index; 2177 2178 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2179 } 2180 2181 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2182 #define MAX_KVM_BUF_SIZE 2048 2183 2184 static int htab_save_iterate(QEMUFile *f, void *opaque) 2185 { 2186 SpaprMachineState *spapr = opaque; 2187 int fd; 2188 int rc = 0; 2189 2190 /* Iteration header */ 2191 if (!spapr->htab_shift) { 2192 qemu_put_be32(f, -1); 2193 return 1; 2194 } else { 2195 qemu_put_be32(f, 0); 2196 } 2197 2198 if (!spapr->htab) { 2199 assert(kvm_enabled()); 2200 2201 fd = get_htab_fd(spapr); 2202 if (fd < 0) { 2203 return fd; 2204 } 2205 2206 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2207 if (rc < 0) { 2208 return rc; 2209 } 2210 } else if (spapr->htab_first_pass) { 2211 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2212 } else { 2213 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2214 } 2215 2216 htab_save_end_marker(f); 2217 2218 return rc; 2219 } 2220 2221 static int htab_save_complete(QEMUFile *f, void *opaque) 2222 { 2223 SpaprMachineState *spapr = opaque; 2224 int fd; 2225 2226 /* Iteration header */ 2227 if (!spapr->htab_shift) { 2228 qemu_put_be32(f, -1); 2229 return 0; 2230 } else { 2231 qemu_put_be32(f, 0); 2232 } 2233 2234 if (!spapr->htab) { 2235 int rc; 2236 2237 assert(kvm_enabled()); 2238 2239 fd = get_htab_fd(spapr); 2240 if (fd < 0) { 2241 return fd; 2242 } 2243 2244 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2245 if (rc < 0) { 2246 return rc; 2247 } 2248 } else { 2249 if (spapr->htab_first_pass) { 2250 htab_save_first_pass(f, spapr, -1); 2251 } 2252 htab_save_later_pass(f, spapr, -1); 2253 } 2254 2255 /* End marker */ 2256 htab_save_end_marker(f); 2257 2258 return 0; 2259 } 2260 2261 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2262 { 2263 SpaprMachineState *spapr = opaque; 2264 uint32_t section_hdr; 2265 int fd = -1; 2266 Error *local_err = NULL; 2267 2268 if (version_id < 1 || version_id > 1) { 2269 error_report("htab_load() bad version"); 2270 return -EINVAL; 2271 } 2272 2273 section_hdr = qemu_get_be32(f); 2274 2275 if (section_hdr == -1) { 2276 spapr_free_hpt(spapr); 2277 return 0; 2278 } 2279 2280 if (section_hdr) { 2281 int ret; 2282 2283 /* First section gives the htab size */ 2284 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2285 if (ret < 0) { 2286 error_report_err(local_err); 2287 return ret; 2288 } 2289 return 0; 2290 } 2291 2292 if (!spapr->htab) { 2293 assert(kvm_enabled()); 2294 2295 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2296 if (fd < 0) { 2297 error_report_err(local_err); 2298 return fd; 2299 } 2300 } 2301 2302 while (true) { 2303 uint32_t index; 2304 uint16_t n_valid, n_invalid; 2305 2306 index = qemu_get_be32(f); 2307 n_valid = qemu_get_be16(f); 2308 n_invalid = qemu_get_be16(f); 2309 2310 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2311 /* End of Stream */ 2312 break; 2313 } 2314 2315 if ((index + n_valid + n_invalid) > 2316 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2317 /* Bad index in stream */ 2318 error_report( 2319 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2320 index, n_valid, n_invalid, spapr->htab_shift); 2321 return -EINVAL; 2322 } 2323 2324 if (spapr->htab) { 2325 if (n_valid) { 2326 qemu_get_buffer(f, HPTE(spapr->htab, index), 2327 HASH_PTE_SIZE_64 * n_valid); 2328 } 2329 if (n_invalid) { 2330 memset(HPTE(spapr->htab, index + n_valid), 0, 2331 HASH_PTE_SIZE_64 * n_invalid); 2332 } 2333 } else { 2334 int rc; 2335 2336 assert(fd >= 0); 2337 2338 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2339 &local_err); 2340 if (rc < 0) { 2341 error_report_err(local_err); 2342 return rc; 2343 } 2344 } 2345 } 2346 2347 if (!spapr->htab) { 2348 assert(fd >= 0); 2349 close(fd); 2350 } 2351 2352 return 0; 2353 } 2354 2355 static void htab_save_cleanup(void *opaque) 2356 { 2357 SpaprMachineState *spapr = opaque; 2358 2359 close_htab_fd(spapr); 2360 } 2361 2362 static SaveVMHandlers savevm_htab_handlers = { 2363 .save_setup = htab_save_setup, 2364 .save_live_iterate = htab_save_iterate, 2365 .save_live_complete_precopy = htab_save_complete, 2366 .save_cleanup = htab_save_cleanup, 2367 .load_state = htab_load, 2368 }; 2369 2370 static void spapr_boot_set(void *opaque, const char *boot_device, 2371 Error **errp) 2372 { 2373 MachineState *machine = MACHINE(opaque); 2374 machine->boot_order = g_strdup(boot_device); 2375 } 2376 2377 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2378 { 2379 MachineState *machine = MACHINE(spapr); 2380 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2381 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2382 int i; 2383 2384 for (i = 0; i < nr_lmbs; i++) { 2385 uint64_t addr; 2386 2387 addr = i * lmb_size + machine->device_memory->base; 2388 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2389 addr / lmb_size); 2390 } 2391 } 2392 2393 /* 2394 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2395 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2396 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2397 */ 2398 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2399 { 2400 int i; 2401 2402 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2403 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2404 " is not aligned to %" PRIu64 " MiB", 2405 machine->ram_size, 2406 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2407 return; 2408 } 2409 2410 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2411 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2412 " is not aligned to %" PRIu64 " MiB", 2413 machine->ram_size, 2414 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2415 return; 2416 } 2417 2418 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2419 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2420 error_setg(errp, 2421 "Node %d memory size 0x%" PRIx64 2422 " is not aligned to %" PRIu64 " MiB", 2423 i, machine->numa_state->nodes[i].node_mem, 2424 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2425 return; 2426 } 2427 } 2428 } 2429 2430 /* find cpu slot in machine->possible_cpus by core_id */ 2431 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2432 { 2433 int index = id / ms->smp.threads; 2434 2435 if (index >= ms->possible_cpus->len) { 2436 return NULL; 2437 } 2438 if (idx) { 2439 *idx = index; 2440 } 2441 return &ms->possible_cpus->cpus[index]; 2442 } 2443 2444 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2445 { 2446 MachineState *ms = MACHINE(spapr); 2447 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2448 Error *local_err = NULL; 2449 bool vsmt_user = !!spapr->vsmt; 2450 int kvm_smt = kvmppc_smt_threads(); 2451 int ret; 2452 unsigned int smp_threads = ms->smp.threads; 2453 2454 if (!kvm_enabled() && (smp_threads > 1)) { 2455 error_setg(errp, "TCG cannot support more than 1 thread/core " 2456 "on a pseries machine"); 2457 return; 2458 } 2459 if (!is_power_of_2(smp_threads)) { 2460 error_setg(errp, "Cannot support %d threads/core on a pseries " 2461 "machine because it must be a power of 2", smp_threads); 2462 return; 2463 } 2464 2465 /* Detemine the VSMT mode to use: */ 2466 if (vsmt_user) { 2467 if (spapr->vsmt < smp_threads) { 2468 error_setg(errp, "Cannot support VSMT mode %d" 2469 " because it must be >= threads/core (%d)", 2470 spapr->vsmt, smp_threads); 2471 return; 2472 } 2473 /* In this case, spapr->vsmt has been set by the command line */ 2474 } else if (!smc->smp_threads_vsmt) { 2475 /* 2476 * Default VSMT value is tricky, because we need it to be as 2477 * consistent as possible (for migration), but this requires 2478 * changing it for at least some existing cases. We pick 8 as 2479 * the value that we'd get with KVM on POWER8, the 2480 * overwhelmingly common case in production systems. 2481 */ 2482 spapr->vsmt = MAX(8, smp_threads); 2483 } else { 2484 spapr->vsmt = smp_threads; 2485 } 2486 2487 /* KVM: If necessary, set the SMT mode: */ 2488 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2489 ret = kvmppc_set_smt_threads(spapr->vsmt); 2490 if (ret) { 2491 /* Looks like KVM isn't able to change VSMT mode */ 2492 error_setg(&local_err, 2493 "Failed to set KVM's VSMT mode to %d (errno %d)", 2494 spapr->vsmt, ret); 2495 /* We can live with that if the default one is big enough 2496 * for the number of threads, and a submultiple of the one 2497 * we want. In this case we'll waste some vcpu ids, but 2498 * behaviour will be correct */ 2499 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2500 warn_report_err(local_err); 2501 } else { 2502 if (!vsmt_user) { 2503 error_append_hint(&local_err, 2504 "On PPC, a VM with %d threads/core" 2505 " on a host with %d threads/core" 2506 " requires the use of VSMT mode %d.\n", 2507 smp_threads, kvm_smt, spapr->vsmt); 2508 } 2509 kvmppc_error_append_smt_possible_hint(&local_err); 2510 error_propagate(errp, local_err); 2511 } 2512 } 2513 } 2514 /* else TCG: nothing to do currently */ 2515 } 2516 2517 static void spapr_init_cpus(SpaprMachineState *spapr) 2518 { 2519 MachineState *machine = MACHINE(spapr); 2520 MachineClass *mc = MACHINE_GET_CLASS(machine); 2521 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2522 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2523 const CPUArchIdList *possible_cpus; 2524 unsigned int smp_cpus = machine->smp.cpus; 2525 unsigned int smp_threads = machine->smp.threads; 2526 unsigned int max_cpus = machine->smp.max_cpus; 2527 int boot_cores_nr = smp_cpus / smp_threads; 2528 int i; 2529 2530 possible_cpus = mc->possible_cpu_arch_ids(machine); 2531 if (mc->has_hotpluggable_cpus) { 2532 if (smp_cpus % smp_threads) { 2533 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2534 smp_cpus, smp_threads); 2535 exit(1); 2536 } 2537 if (max_cpus % smp_threads) { 2538 error_report("max_cpus (%u) must be multiple of threads (%u)", 2539 max_cpus, smp_threads); 2540 exit(1); 2541 } 2542 } else { 2543 if (max_cpus != smp_cpus) { 2544 error_report("This machine version does not support CPU hotplug"); 2545 exit(1); 2546 } 2547 boot_cores_nr = possible_cpus->len; 2548 } 2549 2550 if (smc->pre_2_10_has_unused_icps) { 2551 int i; 2552 2553 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2554 /* Dummy entries get deregistered when real ICPState objects 2555 * are registered during CPU core hotplug. 2556 */ 2557 pre_2_10_vmstate_register_dummy_icp(i); 2558 } 2559 } 2560 2561 for (i = 0; i < possible_cpus->len; i++) { 2562 int core_id = i * smp_threads; 2563 2564 if (mc->has_hotpluggable_cpus) { 2565 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2566 spapr_vcpu_id(spapr, core_id)); 2567 } 2568 2569 if (i < boot_cores_nr) { 2570 Object *core = object_new(type); 2571 int nr_threads = smp_threads; 2572 2573 /* Handle the partially filled core for older machine types */ 2574 if ((i + 1) * smp_threads >= smp_cpus) { 2575 nr_threads = smp_cpus - i * smp_threads; 2576 } 2577 2578 object_property_set_int(core, "nr-threads", nr_threads, 2579 &error_fatal); 2580 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2581 &error_fatal); 2582 qdev_realize(DEVICE(core), NULL, &error_fatal); 2583 2584 object_unref(core); 2585 } 2586 } 2587 } 2588 2589 static PCIHostState *spapr_create_default_phb(void) 2590 { 2591 DeviceState *dev; 2592 2593 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2594 qdev_prop_set_uint32(dev, "index", 0); 2595 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2596 2597 return PCI_HOST_BRIDGE(dev); 2598 } 2599 2600 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2601 { 2602 MachineState *machine = MACHINE(spapr); 2603 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2604 hwaddr rma_size = machine->ram_size; 2605 hwaddr node0_size = spapr_node0_size(machine); 2606 2607 /* RMA has to fit in the first NUMA node */ 2608 rma_size = MIN(rma_size, node0_size); 2609 2610 /* 2611 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2612 * never exceed that 2613 */ 2614 rma_size = MIN(rma_size, 1 * TiB); 2615 2616 /* 2617 * Clamp the RMA size based on machine type. This is for 2618 * migration compatibility with older qemu versions, which limited 2619 * the RMA size for complicated and mostly bad reasons. 2620 */ 2621 if (smc->rma_limit) { 2622 rma_size = MIN(rma_size, smc->rma_limit); 2623 } 2624 2625 if (rma_size < MIN_RMA_SLOF) { 2626 error_setg(errp, 2627 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2628 "ldMiB guest RMA (Real Mode Area memory)", 2629 MIN_RMA_SLOF / MiB); 2630 return 0; 2631 } 2632 2633 return rma_size; 2634 } 2635 2636 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2637 { 2638 MachineState *machine = MACHINE(spapr); 2639 int i; 2640 2641 for (i = 0; i < machine->ram_slots; i++) { 2642 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2643 } 2644 } 2645 2646 /* pSeries LPAR / sPAPR hardware init */ 2647 static void spapr_machine_init(MachineState *machine) 2648 { 2649 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2650 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2651 MachineClass *mc = MACHINE_GET_CLASS(machine); 2652 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 2653 const char *kernel_filename = machine->kernel_filename; 2654 const char *initrd_filename = machine->initrd_filename; 2655 PCIHostState *phb; 2656 int i; 2657 MemoryRegion *sysmem = get_system_memory(); 2658 long load_limit, fw_size; 2659 char *filename; 2660 Error *resize_hpt_err = NULL; 2661 2662 /* 2663 * if Secure VM (PEF) support is configured, then initialize it 2664 */ 2665 pef_kvm_init(machine->cgs, &error_fatal); 2666 2667 msi_nonbroken = true; 2668 2669 QLIST_INIT(&spapr->phbs); 2670 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2671 2672 /* Determine capabilities to run with */ 2673 spapr_caps_init(spapr); 2674 2675 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2676 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2677 /* 2678 * If the user explicitly requested a mode we should either 2679 * supply it, or fail completely (which we do below). But if 2680 * it's not set explicitly, we reset our mode to something 2681 * that works 2682 */ 2683 if (resize_hpt_err) { 2684 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2685 error_free(resize_hpt_err); 2686 resize_hpt_err = NULL; 2687 } else { 2688 spapr->resize_hpt = smc->resize_hpt_default; 2689 } 2690 } 2691 2692 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2693 2694 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2695 /* 2696 * User requested HPT resize, but this host can't supply it. Bail out 2697 */ 2698 error_report_err(resize_hpt_err); 2699 exit(1); 2700 } 2701 error_free(resize_hpt_err); 2702 2703 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2704 2705 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2706 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2707 2708 /* 2709 * VSMT must be set in order to be able to compute VCPU ids, ie to 2710 * call spapr_max_server_number() or spapr_vcpu_id(). 2711 */ 2712 spapr_set_vsmt_mode(spapr, &error_fatal); 2713 2714 /* Set up Interrupt Controller before we create the VCPUs */ 2715 spapr_irq_init(spapr, &error_fatal); 2716 2717 /* Set up containers for ibm,client-architecture-support negotiated options 2718 */ 2719 spapr->ov5 = spapr_ovec_new(); 2720 spapr->ov5_cas = spapr_ovec_new(); 2721 2722 if (smc->dr_lmb_enabled) { 2723 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2724 spapr_validate_node_memory(machine, &error_fatal); 2725 } 2726 2727 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2728 2729 /* advertise support for dedicated HP event source to guests */ 2730 if (spapr->use_hotplug_event_source) { 2731 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2732 } 2733 2734 /* advertise support for HPT resizing */ 2735 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2736 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2737 } 2738 2739 /* advertise support for ibm,dyamic-memory-v2 */ 2740 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2741 2742 /* advertise XIVE on POWER9 machines */ 2743 if (spapr->irq->xive) { 2744 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2745 } 2746 2747 /* init CPUs */ 2748 spapr_init_cpus(spapr); 2749 2750 /* 2751 * check we don't have a memory-less/cpu-less NUMA node 2752 * Firmware relies on the existing memory/cpu topology to provide the 2753 * NUMA topology to the kernel. 2754 * And the linux kernel needs to know the NUMA topology at start 2755 * to be able to hotplug CPUs later. 2756 */ 2757 if (machine->numa_state->num_nodes) { 2758 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2759 /* check for memory-less node */ 2760 if (machine->numa_state->nodes[i].node_mem == 0) { 2761 CPUState *cs; 2762 int found = 0; 2763 /* check for cpu-less node */ 2764 CPU_FOREACH(cs) { 2765 PowerPCCPU *cpu = POWERPC_CPU(cs); 2766 if (cpu->node_id == i) { 2767 found = 1; 2768 break; 2769 } 2770 } 2771 /* memory-less and cpu-less node */ 2772 if (!found) { 2773 error_report( 2774 "Memory-less/cpu-less nodes are not supported (node %d)", 2775 i); 2776 exit(1); 2777 } 2778 } 2779 } 2780 2781 } 2782 2783 /* 2784 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2785 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2786 * called from vPHB reset handler so we initialize the counter here. 2787 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2788 * must be equally distant from any other node. 2789 * The final value of spapr->gpu_numa_id is going to be written to 2790 * max-associativity-domains in spapr_build_fdt(). 2791 */ 2792 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2793 2794 /* Init numa_assoc_array */ 2795 spapr_numa_associativity_init(spapr, machine); 2796 2797 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2798 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2799 spapr->max_compat_pvr)) { 2800 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2801 /* KVM and TCG always allow GTSE with radix... */ 2802 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2803 } 2804 /* ... but not with hash (currently). */ 2805 2806 if (kvm_enabled()) { 2807 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2808 kvmppc_enable_logical_ci_hcalls(); 2809 kvmppc_enable_set_mode_hcall(); 2810 2811 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2812 kvmppc_enable_clear_ref_mod_hcalls(); 2813 2814 /* Enable H_PAGE_INIT */ 2815 kvmppc_enable_h_page_init(); 2816 } 2817 2818 /* map RAM */ 2819 memory_region_add_subregion(sysmem, 0, machine->ram); 2820 2821 /* always allocate the device memory information */ 2822 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2823 2824 /* initialize hotplug memory address space */ 2825 if (machine->ram_size < machine->maxram_size) { 2826 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2827 /* 2828 * Limit the number of hotpluggable memory slots to half the number 2829 * slots that KVM supports, leaving the other half for PCI and other 2830 * devices. However ensure that number of slots doesn't drop below 32. 2831 */ 2832 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2833 SPAPR_MAX_RAM_SLOTS; 2834 2835 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2836 max_memslots = SPAPR_MAX_RAM_SLOTS; 2837 } 2838 if (machine->ram_slots > max_memslots) { 2839 error_report("Specified number of memory slots %" 2840 PRIu64" exceeds max supported %d", 2841 machine->ram_slots, max_memslots); 2842 exit(1); 2843 } 2844 2845 machine->device_memory->base = ROUND_UP(machine->ram_size, 2846 SPAPR_DEVICE_MEM_ALIGN); 2847 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2848 "device-memory", device_mem_size); 2849 memory_region_add_subregion(sysmem, machine->device_memory->base, 2850 &machine->device_memory->mr); 2851 } 2852 2853 if (smc->dr_lmb_enabled) { 2854 spapr_create_lmb_dr_connectors(spapr); 2855 } 2856 2857 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2858 /* Create the error string for live migration blocker */ 2859 error_setg(&spapr->fwnmi_migration_blocker, 2860 "A machine check is being handled during migration. The handler" 2861 "may run and log hardware error on the destination"); 2862 } 2863 2864 if (mc->nvdimm_supported) { 2865 spapr_create_nvdimm_dr_connectors(spapr); 2866 } 2867 2868 /* Set up RTAS event infrastructure */ 2869 spapr_events_init(spapr); 2870 2871 /* Set up the RTC RTAS interfaces */ 2872 spapr_rtc_create(spapr); 2873 2874 /* Set up VIO bus */ 2875 spapr->vio_bus = spapr_vio_bus_init(); 2876 2877 for (i = 0; serial_hd(i); i++) { 2878 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2879 } 2880 2881 /* We always have at least the nvram device on VIO */ 2882 spapr_create_nvram(spapr); 2883 2884 /* 2885 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2886 * connectors (described in root DT node's "ibm,drc-types" property) 2887 * are pre-initialized here. additional child connectors (such as 2888 * connectors for a PHBs PCI slots) are added as needed during their 2889 * parent's realization. 2890 */ 2891 if (smc->dr_phb_enabled) { 2892 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2893 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2894 } 2895 } 2896 2897 /* Set up PCI */ 2898 spapr_pci_rtas_init(); 2899 2900 phb = spapr_create_default_phb(); 2901 2902 for (i = 0; i < nb_nics; i++) { 2903 NICInfo *nd = &nd_table[i]; 2904 2905 if (!nd->model) { 2906 nd->model = g_strdup("spapr-vlan"); 2907 } 2908 2909 if (g_str_equal(nd->model, "spapr-vlan") || 2910 g_str_equal(nd->model, "ibmveth")) { 2911 spapr_vlan_create(spapr->vio_bus, nd); 2912 } else { 2913 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2914 } 2915 } 2916 2917 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2918 spapr_vscsi_create(spapr->vio_bus); 2919 } 2920 2921 /* Graphics */ 2922 if (spapr_vga_init(phb->bus, &error_fatal)) { 2923 spapr->has_graphics = true; 2924 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2925 } 2926 2927 if (machine->usb) { 2928 if (smc->use_ohci_by_default) { 2929 pci_create_simple(phb->bus, -1, "pci-ohci"); 2930 } else { 2931 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2932 } 2933 2934 if (spapr->has_graphics) { 2935 USBBus *usb_bus = usb_bus_find(-1); 2936 2937 usb_create_simple(usb_bus, "usb-kbd"); 2938 usb_create_simple(usb_bus, "usb-mouse"); 2939 } 2940 } 2941 2942 if (kernel_filename) { 2943 spapr->kernel_size = load_elf(kernel_filename, NULL, 2944 translate_kernel_address, spapr, 2945 NULL, NULL, NULL, NULL, 1, 2946 PPC_ELF_MACHINE, 0, 0); 2947 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2948 spapr->kernel_size = load_elf(kernel_filename, NULL, 2949 translate_kernel_address, spapr, 2950 NULL, NULL, NULL, NULL, 0, 2951 PPC_ELF_MACHINE, 0, 0); 2952 spapr->kernel_le = spapr->kernel_size > 0; 2953 } 2954 if (spapr->kernel_size < 0) { 2955 error_report("error loading %s: %s", kernel_filename, 2956 load_elf_strerror(spapr->kernel_size)); 2957 exit(1); 2958 } 2959 2960 /* load initrd */ 2961 if (initrd_filename) { 2962 /* Try to locate the initrd in the gap between the kernel 2963 * and the firmware. Add a bit of space just in case 2964 */ 2965 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2966 + 0x1ffff) & ~0xffff; 2967 spapr->initrd_size = load_image_targphys(initrd_filename, 2968 spapr->initrd_base, 2969 load_limit 2970 - spapr->initrd_base); 2971 if (spapr->initrd_size < 0) { 2972 error_report("could not load initial ram disk '%s'", 2973 initrd_filename); 2974 exit(1); 2975 } 2976 } 2977 } 2978 2979 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2980 if (!filename) { 2981 error_report("Could not find LPAR firmware '%s'", bios_name); 2982 exit(1); 2983 } 2984 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2985 if (fw_size <= 0) { 2986 error_report("Could not load LPAR firmware '%s'", filename); 2987 exit(1); 2988 } 2989 g_free(filename); 2990 2991 /* FIXME: Should register things through the MachineState's qdev 2992 * interface, this is a legacy from the sPAPREnvironment structure 2993 * which predated MachineState but had a similar function */ 2994 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2995 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 2996 &savevm_htab_handlers, spapr); 2997 2998 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 2999 3000 qemu_register_boot_set(spapr_boot_set, spapr); 3001 3002 /* 3003 * Nothing needs to be done to resume a suspended guest because 3004 * suspending does not change the machine state, so no need for 3005 * a ->wakeup method. 3006 */ 3007 qemu_register_wakeup_support(); 3008 3009 if (kvm_enabled()) { 3010 /* to stop and start vmclock */ 3011 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3012 &spapr->tb); 3013 3014 kvmppc_spapr_enable_inkernel_multitce(); 3015 } 3016 3017 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3018 } 3019 3020 #define DEFAULT_KVM_TYPE "auto" 3021 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3022 { 3023 /* 3024 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3025 * accomodate the 'HV' and 'PV' formats that exists in the 3026 * wild. The 'auto' mode is being introduced already as 3027 * lower-case, thus we don't need to bother checking for 3028 * "AUTO". 3029 */ 3030 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3031 return 0; 3032 } 3033 3034 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3035 return 1; 3036 } 3037 3038 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3039 return 2; 3040 } 3041 3042 error_report("Unknown kvm-type specified '%s'", vm_type); 3043 exit(1); 3044 } 3045 3046 /* 3047 * Implementation of an interface to adjust firmware path 3048 * for the bootindex property handling. 3049 */ 3050 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3051 DeviceState *dev) 3052 { 3053 #define CAST(type, obj, name) \ 3054 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3055 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3056 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3057 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3058 3059 if (d) { 3060 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3061 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3062 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3063 3064 if (spapr) { 3065 /* 3066 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3067 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3068 * 0x8000 | (target << 8) | (bus << 5) | lun 3069 * (see the "Logical unit addressing format" table in SAM5) 3070 */ 3071 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3072 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3073 (uint64_t)id << 48); 3074 } else if (virtio) { 3075 /* 3076 * We use SRP luns of the form 01000000 | (target << 8) | lun 3077 * in the top 32 bits of the 64-bit LUN 3078 * Note: the quote above is from SLOF and it is wrong, 3079 * the actual binding is: 3080 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3081 */ 3082 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3083 if (d->lun >= 256) { 3084 /* Use the LUN "flat space addressing method" */ 3085 id |= 0x4000; 3086 } 3087 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3088 (uint64_t)id << 32); 3089 } else if (usb) { 3090 /* 3091 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3092 * in the top 32 bits of the 64-bit LUN 3093 */ 3094 unsigned usb_port = atoi(usb->port->path); 3095 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3096 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3097 (uint64_t)id << 32); 3098 } 3099 } 3100 3101 /* 3102 * SLOF probes the USB devices, and if it recognizes that the device is a 3103 * storage device, it changes its name to "storage" instead of "usb-host", 3104 * and additionally adds a child node for the SCSI LUN, so the correct 3105 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3106 */ 3107 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3108 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3109 if (usb_host_dev_is_scsi_storage(usbdev)) { 3110 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3111 } 3112 } 3113 3114 if (phb) { 3115 /* Replace "pci" with "pci@800000020000000" */ 3116 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3117 } 3118 3119 if (vsc) { 3120 /* Same logic as virtio above */ 3121 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3122 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3123 } 3124 3125 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3126 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3127 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3128 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3129 } 3130 3131 return NULL; 3132 } 3133 3134 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3135 { 3136 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3137 3138 return g_strdup(spapr->kvm_type); 3139 } 3140 3141 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3142 { 3143 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3144 3145 g_free(spapr->kvm_type); 3146 spapr->kvm_type = g_strdup(value); 3147 } 3148 3149 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3150 { 3151 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3152 3153 return spapr->use_hotplug_event_source; 3154 } 3155 3156 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3157 Error **errp) 3158 { 3159 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3160 3161 spapr->use_hotplug_event_source = value; 3162 } 3163 3164 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3165 { 3166 return true; 3167 } 3168 3169 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3170 { 3171 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3172 3173 switch (spapr->resize_hpt) { 3174 case SPAPR_RESIZE_HPT_DEFAULT: 3175 return g_strdup("default"); 3176 case SPAPR_RESIZE_HPT_DISABLED: 3177 return g_strdup("disabled"); 3178 case SPAPR_RESIZE_HPT_ENABLED: 3179 return g_strdup("enabled"); 3180 case SPAPR_RESIZE_HPT_REQUIRED: 3181 return g_strdup("required"); 3182 } 3183 g_assert_not_reached(); 3184 } 3185 3186 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3187 { 3188 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3189 3190 if (strcmp(value, "default") == 0) { 3191 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3192 } else if (strcmp(value, "disabled") == 0) { 3193 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3194 } else if (strcmp(value, "enabled") == 0) { 3195 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3196 } else if (strcmp(value, "required") == 0) { 3197 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3198 } else { 3199 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3200 } 3201 } 3202 3203 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3204 { 3205 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3206 3207 if (spapr->irq == &spapr_irq_xics_legacy) { 3208 return g_strdup("legacy"); 3209 } else if (spapr->irq == &spapr_irq_xics) { 3210 return g_strdup("xics"); 3211 } else if (spapr->irq == &spapr_irq_xive) { 3212 return g_strdup("xive"); 3213 } else if (spapr->irq == &spapr_irq_dual) { 3214 return g_strdup("dual"); 3215 } 3216 g_assert_not_reached(); 3217 } 3218 3219 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3220 { 3221 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3222 3223 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3224 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3225 return; 3226 } 3227 3228 /* The legacy IRQ backend can not be set */ 3229 if (strcmp(value, "xics") == 0) { 3230 spapr->irq = &spapr_irq_xics; 3231 } else if (strcmp(value, "xive") == 0) { 3232 spapr->irq = &spapr_irq_xive; 3233 } else if (strcmp(value, "dual") == 0) { 3234 spapr->irq = &spapr_irq_dual; 3235 } else { 3236 error_setg(errp, "Bad value for \"ic-mode\" property"); 3237 } 3238 } 3239 3240 static char *spapr_get_host_model(Object *obj, Error **errp) 3241 { 3242 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3243 3244 return g_strdup(spapr->host_model); 3245 } 3246 3247 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3248 { 3249 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3250 3251 g_free(spapr->host_model); 3252 spapr->host_model = g_strdup(value); 3253 } 3254 3255 static char *spapr_get_host_serial(Object *obj, Error **errp) 3256 { 3257 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3258 3259 return g_strdup(spapr->host_serial); 3260 } 3261 3262 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3263 { 3264 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3265 3266 g_free(spapr->host_serial); 3267 spapr->host_serial = g_strdup(value); 3268 } 3269 3270 static void spapr_instance_init(Object *obj) 3271 { 3272 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3273 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3274 MachineState *ms = MACHINE(spapr); 3275 MachineClass *mc = MACHINE_GET_CLASS(ms); 3276 3277 /* 3278 * NVDIMM support went live in 5.1 without considering that, in 3279 * other archs, the user needs to enable NVDIMM support with the 3280 * 'nvdimm' machine option and the default behavior is NVDIMM 3281 * support disabled. It is too late to roll back to the standard 3282 * behavior without breaking 5.1 guests. 3283 */ 3284 if (mc->nvdimm_supported) { 3285 ms->nvdimms_state->is_enabled = true; 3286 } 3287 3288 spapr->htab_fd = -1; 3289 spapr->use_hotplug_event_source = true; 3290 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3291 object_property_add_str(obj, "kvm-type", 3292 spapr_get_kvm_type, spapr_set_kvm_type); 3293 object_property_set_description(obj, "kvm-type", 3294 "Specifies the KVM virtualization mode (auto," 3295 " hv, pr). Defaults to 'auto'. This mode will use" 3296 " any available KVM module loaded in the host," 3297 " where kvm_hv takes precedence if both kvm_hv and" 3298 " kvm_pr are loaded."); 3299 object_property_add_bool(obj, "modern-hotplug-events", 3300 spapr_get_modern_hotplug_events, 3301 spapr_set_modern_hotplug_events); 3302 object_property_set_description(obj, "modern-hotplug-events", 3303 "Use dedicated hotplug event mechanism in" 3304 " place of standard EPOW events when possible" 3305 " (required for memory hot-unplug support)"); 3306 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3307 "Maximum permitted CPU compatibility mode"); 3308 3309 object_property_add_str(obj, "resize-hpt", 3310 spapr_get_resize_hpt, spapr_set_resize_hpt); 3311 object_property_set_description(obj, "resize-hpt", 3312 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3313 object_property_add_uint32_ptr(obj, "vsmt", 3314 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3315 object_property_set_description(obj, "vsmt", 3316 "Virtual SMT: KVM behaves as if this were" 3317 " the host's SMT mode"); 3318 3319 object_property_add_bool(obj, "vfio-no-msix-emulation", 3320 spapr_get_msix_emulation, NULL); 3321 3322 object_property_add_uint64_ptr(obj, "kernel-addr", 3323 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3324 object_property_set_description(obj, "kernel-addr", 3325 stringify(KERNEL_LOAD_ADDR) 3326 " for -kernel is the default"); 3327 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3328 /* The machine class defines the default interrupt controller mode */ 3329 spapr->irq = smc->irq; 3330 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3331 spapr_set_ic_mode); 3332 object_property_set_description(obj, "ic-mode", 3333 "Specifies the interrupt controller mode (xics, xive, dual)"); 3334 3335 object_property_add_str(obj, "host-model", 3336 spapr_get_host_model, spapr_set_host_model); 3337 object_property_set_description(obj, "host-model", 3338 "Host model to advertise in guest device tree"); 3339 object_property_add_str(obj, "host-serial", 3340 spapr_get_host_serial, spapr_set_host_serial); 3341 object_property_set_description(obj, "host-serial", 3342 "Host serial number to advertise in guest device tree"); 3343 } 3344 3345 static void spapr_machine_finalizefn(Object *obj) 3346 { 3347 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3348 3349 g_free(spapr->kvm_type); 3350 } 3351 3352 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3353 { 3354 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3355 PowerPCCPU *cpu = POWERPC_CPU(cs); 3356 CPUPPCState *env = &cpu->env; 3357 3358 cpu_synchronize_state(cs); 3359 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3360 if (spapr->fwnmi_system_reset_addr != -1) { 3361 uint64_t rtas_addr, addr; 3362 3363 /* get rtas addr from fdt */ 3364 rtas_addr = spapr_get_rtas_addr(); 3365 if (!rtas_addr) { 3366 qemu_system_guest_panicked(NULL); 3367 return; 3368 } 3369 3370 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3371 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3372 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3373 env->gpr[3] = addr; 3374 } 3375 ppc_cpu_do_system_reset(cs); 3376 if (spapr->fwnmi_system_reset_addr != -1) { 3377 env->nip = spapr->fwnmi_system_reset_addr; 3378 } 3379 } 3380 3381 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3382 { 3383 CPUState *cs; 3384 3385 CPU_FOREACH(cs) { 3386 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3387 } 3388 } 3389 3390 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3391 void *fdt, int *fdt_start_offset, Error **errp) 3392 { 3393 uint64_t addr; 3394 uint32_t node; 3395 3396 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3397 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3398 &error_abort); 3399 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3400 SPAPR_MEMORY_BLOCK_SIZE); 3401 return 0; 3402 } 3403 3404 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3405 bool dedicated_hp_event_source) 3406 { 3407 SpaprDrc *drc; 3408 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3409 int i; 3410 uint64_t addr = addr_start; 3411 bool hotplugged = spapr_drc_hotplugged(dev); 3412 3413 for (i = 0; i < nr_lmbs; i++) { 3414 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3415 addr / SPAPR_MEMORY_BLOCK_SIZE); 3416 g_assert(drc); 3417 3418 /* 3419 * memory_device_get_free_addr() provided a range of free addresses 3420 * that doesn't overlap with any existing mapping at pre-plug. The 3421 * corresponding LMB DRCs are thus assumed to be all attachable. 3422 */ 3423 spapr_drc_attach(drc, dev); 3424 if (!hotplugged) { 3425 spapr_drc_reset(drc); 3426 } 3427 addr += SPAPR_MEMORY_BLOCK_SIZE; 3428 } 3429 /* send hotplug notification to the 3430 * guest only in case of hotplugged memory 3431 */ 3432 if (hotplugged) { 3433 if (dedicated_hp_event_source) { 3434 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3435 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3436 g_assert(drc); 3437 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3438 nr_lmbs, 3439 spapr_drc_index(drc)); 3440 } else { 3441 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3442 nr_lmbs); 3443 } 3444 } 3445 } 3446 3447 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3448 { 3449 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3450 PCDIMMDevice *dimm = PC_DIMM(dev); 3451 uint64_t size, addr; 3452 int64_t slot; 3453 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3454 3455 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3456 3457 pc_dimm_plug(dimm, MACHINE(ms)); 3458 3459 if (!is_nvdimm) { 3460 addr = object_property_get_uint(OBJECT(dimm), 3461 PC_DIMM_ADDR_PROP, &error_abort); 3462 spapr_add_lmbs(dev, addr, size, 3463 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3464 } else { 3465 slot = object_property_get_int(OBJECT(dimm), 3466 PC_DIMM_SLOT_PROP, &error_abort); 3467 /* We should have valid slot number at this point */ 3468 g_assert(slot >= 0); 3469 spapr_add_nvdimm(dev, slot); 3470 } 3471 } 3472 3473 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3474 Error **errp) 3475 { 3476 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3477 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3478 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3479 PCDIMMDevice *dimm = PC_DIMM(dev); 3480 Error *local_err = NULL; 3481 uint64_t size; 3482 Object *memdev; 3483 hwaddr pagesize; 3484 3485 if (!smc->dr_lmb_enabled) { 3486 error_setg(errp, "Memory hotplug not supported for this machine"); 3487 return; 3488 } 3489 3490 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3491 if (local_err) { 3492 error_propagate(errp, local_err); 3493 return; 3494 } 3495 3496 if (is_nvdimm) { 3497 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3498 return; 3499 } 3500 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3501 error_setg(errp, "Hotplugged memory size must be a multiple of " 3502 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3503 return; 3504 } 3505 3506 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3507 &error_abort); 3508 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3509 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3510 return; 3511 } 3512 3513 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3514 } 3515 3516 struct SpaprDimmState { 3517 PCDIMMDevice *dimm; 3518 uint32_t nr_lmbs; 3519 QTAILQ_ENTRY(SpaprDimmState) next; 3520 }; 3521 3522 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3523 PCDIMMDevice *dimm) 3524 { 3525 SpaprDimmState *dimm_state = NULL; 3526 3527 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3528 if (dimm_state->dimm == dimm) { 3529 break; 3530 } 3531 } 3532 return dimm_state; 3533 } 3534 3535 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3536 uint32_t nr_lmbs, 3537 PCDIMMDevice *dimm) 3538 { 3539 SpaprDimmState *ds = NULL; 3540 3541 /* 3542 * If this request is for a DIMM whose removal had failed earlier 3543 * (due to guest's refusal to remove the LMBs), we would have this 3544 * dimm already in the pending_dimm_unplugs list. In that 3545 * case don't add again. 3546 */ 3547 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3548 if (!ds) { 3549 ds = g_malloc0(sizeof(SpaprDimmState)); 3550 ds->nr_lmbs = nr_lmbs; 3551 ds->dimm = dimm; 3552 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3553 } 3554 return ds; 3555 } 3556 3557 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3558 SpaprDimmState *dimm_state) 3559 { 3560 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3561 g_free(dimm_state); 3562 } 3563 3564 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3565 PCDIMMDevice *dimm) 3566 { 3567 SpaprDrc *drc; 3568 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3569 &error_abort); 3570 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3571 uint32_t avail_lmbs = 0; 3572 uint64_t addr_start, addr; 3573 int i; 3574 3575 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3576 &error_abort); 3577 3578 addr = addr_start; 3579 for (i = 0; i < nr_lmbs; i++) { 3580 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3581 addr / SPAPR_MEMORY_BLOCK_SIZE); 3582 g_assert(drc); 3583 if (drc->dev) { 3584 avail_lmbs++; 3585 } 3586 addr += SPAPR_MEMORY_BLOCK_SIZE; 3587 } 3588 3589 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3590 } 3591 3592 /* Callback to be called during DRC release. */ 3593 void spapr_lmb_release(DeviceState *dev) 3594 { 3595 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3596 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3597 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3598 3599 /* This information will get lost if a migration occurs 3600 * during the unplug process. In this case recover it. */ 3601 if (ds == NULL) { 3602 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3603 g_assert(ds); 3604 /* The DRC being examined by the caller at least must be counted */ 3605 g_assert(ds->nr_lmbs); 3606 } 3607 3608 if (--ds->nr_lmbs) { 3609 return; 3610 } 3611 3612 /* 3613 * Now that all the LMBs have been removed by the guest, call the 3614 * unplug handler chain. This can never fail. 3615 */ 3616 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3617 object_unparent(OBJECT(dev)); 3618 } 3619 3620 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3621 { 3622 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3623 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3624 3625 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3626 qdev_unrealize(dev); 3627 spapr_pending_dimm_unplugs_remove(spapr, ds); 3628 } 3629 3630 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3631 DeviceState *dev, Error **errp) 3632 { 3633 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3634 PCDIMMDevice *dimm = PC_DIMM(dev); 3635 uint32_t nr_lmbs; 3636 uint64_t size, addr_start, addr; 3637 int i; 3638 SpaprDrc *drc; 3639 3640 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3641 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3642 return; 3643 } 3644 3645 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3646 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3647 3648 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3649 &error_abort); 3650 3651 /* 3652 * An existing pending dimm state for this DIMM means that there is an 3653 * unplug operation in progress, waiting for the spapr_lmb_release 3654 * callback to complete the job (BQL can't cover that far). In this case, 3655 * bail out to avoid detaching DRCs that were already released. 3656 */ 3657 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3658 error_setg(errp, "Memory unplug already in progress for device %s", 3659 dev->id); 3660 return; 3661 } 3662 3663 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3664 3665 addr = addr_start; 3666 for (i = 0; i < nr_lmbs; i++) { 3667 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3668 addr / SPAPR_MEMORY_BLOCK_SIZE); 3669 g_assert(drc); 3670 3671 spapr_drc_detach(drc); 3672 addr += SPAPR_MEMORY_BLOCK_SIZE; 3673 } 3674 3675 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3676 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3677 g_assert(drc); 3678 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3679 nr_lmbs, spapr_drc_index(drc)); 3680 } 3681 3682 /* Callback to be called during DRC release. */ 3683 void spapr_core_release(DeviceState *dev) 3684 { 3685 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3686 3687 /* Call the unplug handler chain. This can never fail. */ 3688 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3689 object_unparent(OBJECT(dev)); 3690 } 3691 3692 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3693 { 3694 MachineState *ms = MACHINE(hotplug_dev); 3695 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3696 CPUCore *cc = CPU_CORE(dev); 3697 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3698 3699 if (smc->pre_2_10_has_unused_icps) { 3700 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3701 int i; 3702 3703 for (i = 0; i < cc->nr_threads; i++) { 3704 CPUState *cs = CPU(sc->threads[i]); 3705 3706 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3707 } 3708 } 3709 3710 assert(core_slot); 3711 core_slot->cpu = NULL; 3712 qdev_unrealize(dev); 3713 } 3714 3715 static 3716 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3717 Error **errp) 3718 { 3719 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3720 int index; 3721 SpaprDrc *drc; 3722 CPUCore *cc = CPU_CORE(dev); 3723 3724 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3725 error_setg(errp, "Unable to find CPU core with core-id: %d", 3726 cc->core_id); 3727 return; 3728 } 3729 if (index == 0) { 3730 error_setg(errp, "Boot CPU core may not be unplugged"); 3731 return; 3732 } 3733 3734 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3735 spapr_vcpu_id(spapr, cc->core_id)); 3736 g_assert(drc); 3737 3738 if (!spapr_drc_unplug_requested(drc)) { 3739 spapr_drc_detach(drc); 3740 spapr_hotplug_req_remove_by_index(drc); 3741 } 3742 } 3743 3744 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3745 void *fdt, int *fdt_start_offset, Error **errp) 3746 { 3747 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3748 CPUState *cs = CPU(core->threads[0]); 3749 PowerPCCPU *cpu = POWERPC_CPU(cs); 3750 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3751 int id = spapr_get_vcpu_id(cpu); 3752 char *nodename; 3753 int offset; 3754 3755 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3756 offset = fdt_add_subnode(fdt, 0, nodename); 3757 g_free(nodename); 3758 3759 spapr_dt_cpu(cs, fdt, offset, spapr); 3760 3761 *fdt_start_offset = offset; 3762 return 0; 3763 } 3764 3765 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3766 { 3767 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3768 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3769 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3770 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3771 CPUCore *cc = CPU_CORE(dev); 3772 CPUState *cs; 3773 SpaprDrc *drc; 3774 CPUArchId *core_slot; 3775 int index; 3776 bool hotplugged = spapr_drc_hotplugged(dev); 3777 int i; 3778 3779 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3780 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 3781 3782 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3783 spapr_vcpu_id(spapr, cc->core_id)); 3784 3785 g_assert(drc || !mc->has_hotpluggable_cpus); 3786 3787 if (drc) { 3788 /* 3789 * spapr_core_pre_plug() already buys us this is a brand new 3790 * core being plugged into a free slot. Nothing should already 3791 * be attached to the corresponding DRC. 3792 */ 3793 spapr_drc_attach(drc, dev); 3794 3795 if (hotplugged) { 3796 /* 3797 * Send hotplug notification interrupt to the guest only 3798 * in case of hotplugged CPUs. 3799 */ 3800 spapr_hotplug_req_add_by_index(drc); 3801 } else { 3802 spapr_drc_reset(drc); 3803 } 3804 } 3805 3806 core_slot->cpu = OBJECT(dev); 3807 3808 /* 3809 * Set compatibility mode to match the boot CPU, which was either set 3810 * by the machine reset code or by CAS. This really shouldn't fail at 3811 * this point. 3812 */ 3813 if (hotplugged) { 3814 for (i = 0; i < cc->nr_threads; i++) { 3815 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3816 &error_abort); 3817 } 3818 } 3819 3820 if (smc->pre_2_10_has_unused_icps) { 3821 for (i = 0; i < cc->nr_threads; i++) { 3822 cs = CPU(core->threads[i]); 3823 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3824 } 3825 } 3826 } 3827 3828 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3829 Error **errp) 3830 { 3831 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3832 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3833 CPUCore *cc = CPU_CORE(dev); 3834 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3835 const char *type = object_get_typename(OBJECT(dev)); 3836 CPUArchId *core_slot; 3837 int index; 3838 unsigned int smp_threads = machine->smp.threads; 3839 3840 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3841 error_setg(errp, "CPU hotplug not supported for this machine"); 3842 return; 3843 } 3844 3845 if (strcmp(base_core_type, type)) { 3846 error_setg(errp, "CPU core type should be %s", base_core_type); 3847 return; 3848 } 3849 3850 if (cc->core_id % smp_threads) { 3851 error_setg(errp, "invalid core id %d", cc->core_id); 3852 return; 3853 } 3854 3855 /* 3856 * In general we should have homogeneous threads-per-core, but old 3857 * (pre hotplug support) machine types allow the last core to have 3858 * reduced threads as a compatibility hack for when we allowed 3859 * total vcpus not a multiple of threads-per-core. 3860 */ 3861 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3862 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 3863 smp_threads); 3864 return; 3865 } 3866 3867 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3868 if (!core_slot) { 3869 error_setg(errp, "core id %d out of range", cc->core_id); 3870 return; 3871 } 3872 3873 if (core_slot->cpu) { 3874 error_setg(errp, "core %d already populated", cc->core_id); 3875 return; 3876 } 3877 3878 numa_cpu_pre_plug(core_slot, dev, errp); 3879 } 3880 3881 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3882 void *fdt, int *fdt_start_offset, Error **errp) 3883 { 3884 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3885 int intc_phandle; 3886 3887 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3888 if (intc_phandle <= 0) { 3889 return -1; 3890 } 3891 3892 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3893 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3894 return -1; 3895 } 3896 3897 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3898 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3899 3900 return 0; 3901 } 3902 3903 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3904 Error **errp) 3905 { 3906 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3907 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3908 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3909 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3910 SpaprDrc *drc; 3911 3912 if (dev->hotplugged && !smc->dr_phb_enabled) { 3913 error_setg(errp, "PHB hotplug not supported for this machine"); 3914 return false; 3915 } 3916 3917 if (sphb->index == (uint32_t)-1) { 3918 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3919 return false; 3920 } 3921 3922 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3923 if (drc && drc->dev) { 3924 error_setg(errp, "PHB %d already attached", sphb->index); 3925 return false; 3926 } 3927 3928 /* 3929 * This will check that sphb->index doesn't exceed the maximum number of 3930 * PHBs for the current machine type. 3931 */ 3932 return 3933 smc->phb_placement(spapr, sphb->index, 3934 &sphb->buid, &sphb->io_win_addr, 3935 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3936 windows_supported, sphb->dma_liobn, 3937 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3938 errp); 3939 } 3940 3941 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3942 { 3943 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3944 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3945 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3946 SpaprDrc *drc; 3947 bool hotplugged = spapr_drc_hotplugged(dev); 3948 3949 if (!smc->dr_phb_enabled) { 3950 return; 3951 } 3952 3953 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3954 /* hotplug hooks should check it's enabled before getting this far */ 3955 assert(drc); 3956 3957 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 3958 spapr_drc_attach(drc, dev); 3959 3960 if (hotplugged) { 3961 spapr_hotplug_req_add_by_index(drc); 3962 } else { 3963 spapr_drc_reset(drc); 3964 } 3965 } 3966 3967 void spapr_phb_release(DeviceState *dev) 3968 { 3969 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3970 3971 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3972 object_unparent(OBJECT(dev)); 3973 } 3974 3975 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3976 { 3977 qdev_unrealize(dev); 3978 } 3979 3980 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 3981 DeviceState *dev, Error **errp) 3982 { 3983 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3984 SpaprDrc *drc; 3985 3986 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3987 assert(drc); 3988 3989 if (!spapr_drc_unplug_requested(drc)) { 3990 spapr_drc_detach(drc); 3991 spapr_hotplug_req_remove_by_index(drc); 3992 } 3993 } 3994 3995 static 3996 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3997 Error **errp) 3998 { 3999 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4000 4001 if (spapr->tpm_proxy != NULL) { 4002 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4003 return false; 4004 } 4005 4006 return true; 4007 } 4008 4009 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4010 { 4011 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4012 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4013 4014 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4015 g_assert(spapr->tpm_proxy == NULL); 4016 4017 spapr->tpm_proxy = tpm_proxy; 4018 } 4019 4020 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4021 { 4022 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4023 4024 qdev_unrealize(dev); 4025 object_unparent(OBJECT(dev)); 4026 spapr->tpm_proxy = NULL; 4027 } 4028 4029 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4030 DeviceState *dev, Error **errp) 4031 { 4032 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4033 spapr_memory_plug(hotplug_dev, dev); 4034 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4035 spapr_core_plug(hotplug_dev, dev); 4036 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4037 spapr_phb_plug(hotplug_dev, dev); 4038 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4039 spapr_tpm_proxy_plug(hotplug_dev, dev); 4040 } 4041 } 4042 4043 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4044 DeviceState *dev, Error **errp) 4045 { 4046 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4047 spapr_memory_unplug(hotplug_dev, dev); 4048 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4049 spapr_core_unplug(hotplug_dev, dev); 4050 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4051 spapr_phb_unplug(hotplug_dev, dev); 4052 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4053 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4054 } 4055 } 4056 4057 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4058 { 4059 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4060 /* 4061 * CAS will process all pending unplug requests. 4062 * 4063 * HACK: a guest could theoretically have cleared all bits in OV5, 4064 * but none of the guests we care for do. 4065 */ 4066 spapr_ovec_empty(spapr->ov5_cas); 4067 } 4068 4069 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4070 DeviceState *dev, Error **errp) 4071 { 4072 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4073 MachineClass *mc = MACHINE_GET_CLASS(sms); 4074 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4075 4076 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4077 if (spapr_memory_hot_unplug_supported(sms)) { 4078 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4079 } else { 4080 error_setg(errp, "Memory hot unplug not supported for this guest"); 4081 } 4082 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4083 if (!mc->has_hotpluggable_cpus) { 4084 error_setg(errp, "CPU hot unplug not supported on this machine"); 4085 return; 4086 } 4087 spapr_core_unplug_request(hotplug_dev, dev, errp); 4088 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4089 if (!smc->dr_phb_enabled) { 4090 error_setg(errp, "PHB hot unplug not supported on this machine"); 4091 return; 4092 } 4093 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4094 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4095 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4096 } 4097 } 4098 4099 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4100 DeviceState *dev, Error **errp) 4101 { 4102 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4103 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4104 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4105 spapr_core_pre_plug(hotplug_dev, dev, errp); 4106 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4107 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4108 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4109 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4110 } 4111 } 4112 4113 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4114 DeviceState *dev) 4115 { 4116 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4117 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4118 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4119 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4120 return HOTPLUG_HANDLER(machine); 4121 } 4122 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4123 PCIDevice *pcidev = PCI_DEVICE(dev); 4124 PCIBus *root = pci_device_root_bus(pcidev); 4125 SpaprPhbState *phb = 4126 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4127 TYPE_SPAPR_PCI_HOST_BRIDGE); 4128 4129 if (phb) { 4130 return HOTPLUG_HANDLER(phb); 4131 } 4132 } 4133 return NULL; 4134 } 4135 4136 static CpuInstanceProperties 4137 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4138 { 4139 CPUArchId *core_slot; 4140 MachineClass *mc = MACHINE_GET_CLASS(machine); 4141 4142 /* make sure possible_cpu are intialized */ 4143 mc->possible_cpu_arch_ids(machine); 4144 /* get CPU core slot containing thread that matches cpu_index */ 4145 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4146 assert(core_slot); 4147 return core_slot->props; 4148 } 4149 4150 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4151 { 4152 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4153 } 4154 4155 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4156 { 4157 int i; 4158 unsigned int smp_threads = machine->smp.threads; 4159 unsigned int smp_cpus = machine->smp.cpus; 4160 const char *core_type; 4161 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4162 MachineClass *mc = MACHINE_GET_CLASS(machine); 4163 4164 if (!mc->has_hotpluggable_cpus) { 4165 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4166 } 4167 if (machine->possible_cpus) { 4168 assert(machine->possible_cpus->len == spapr_max_cores); 4169 return machine->possible_cpus; 4170 } 4171 4172 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4173 if (!core_type) { 4174 error_report("Unable to find sPAPR CPU Core definition"); 4175 exit(1); 4176 } 4177 4178 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4179 sizeof(CPUArchId) * spapr_max_cores); 4180 machine->possible_cpus->len = spapr_max_cores; 4181 for (i = 0; i < machine->possible_cpus->len; i++) { 4182 int core_id = i * smp_threads; 4183 4184 machine->possible_cpus->cpus[i].type = core_type; 4185 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4186 machine->possible_cpus->cpus[i].arch_id = core_id; 4187 machine->possible_cpus->cpus[i].props.has_core_id = true; 4188 machine->possible_cpus->cpus[i].props.core_id = core_id; 4189 } 4190 return machine->possible_cpus; 4191 } 4192 4193 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4194 uint64_t *buid, hwaddr *pio, 4195 hwaddr *mmio32, hwaddr *mmio64, 4196 unsigned n_dma, uint32_t *liobns, 4197 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4198 { 4199 /* 4200 * New-style PHB window placement. 4201 * 4202 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4203 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4204 * windows. 4205 * 4206 * Some guest kernels can't work with MMIO windows above 1<<46 4207 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4208 * 4209 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4210 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4211 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4212 * 1TiB 64-bit MMIO windows for each PHB. 4213 */ 4214 const uint64_t base_buid = 0x800000020000000ULL; 4215 int i; 4216 4217 /* Sanity check natural alignments */ 4218 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4219 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4220 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4221 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4222 /* Sanity check bounds */ 4223 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4224 SPAPR_PCI_MEM32_WIN_SIZE); 4225 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4226 SPAPR_PCI_MEM64_WIN_SIZE); 4227 4228 if (index >= SPAPR_MAX_PHBS) { 4229 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4230 SPAPR_MAX_PHBS - 1); 4231 return false; 4232 } 4233 4234 *buid = base_buid + index; 4235 for (i = 0; i < n_dma; ++i) { 4236 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4237 } 4238 4239 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4240 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4241 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4242 4243 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4244 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4245 return true; 4246 } 4247 4248 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4249 { 4250 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4251 4252 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4253 } 4254 4255 static void spapr_ics_resend(XICSFabric *dev) 4256 { 4257 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4258 4259 ics_resend(spapr->ics); 4260 } 4261 4262 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4263 { 4264 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4265 4266 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4267 } 4268 4269 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4270 Monitor *mon) 4271 { 4272 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4273 4274 spapr_irq_print_info(spapr, mon); 4275 monitor_printf(mon, "irqchip: %s\n", 4276 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4277 } 4278 4279 /* 4280 * This is a XIVE only operation 4281 */ 4282 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4283 uint8_t nvt_blk, uint32_t nvt_idx, 4284 bool cam_ignore, uint8_t priority, 4285 uint32_t logic_serv, XiveTCTXMatch *match) 4286 { 4287 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4288 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4289 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4290 int count; 4291 4292 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4293 priority, logic_serv, match); 4294 if (count < 0) { 4295 return count; 4296 } 4297 4298 /* 4299 * When we implement the save and restore of the thread interrupt 4300 * contexts in the enter/exit CPU handlers of the machine and the 4301 * escalations in QEMU, we should be able to handle non dispatched 4302 * vCPUs. 4303 * 4304 * Until this is done, the sPAPR machine should find at least one 4305 * matching context always. 4306 */ 4307 if (count == 0) { 4308 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4309 nvt_blk, nvt_idx); 4310 } 4311 4312 return count; 4313 } 4314 4315 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4316 { 4317 return cpu->vcpu_id; 4318 } 4319 4320 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4321 { 4322 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4323 MachineState *ms = MACHINE(spapr); 4324 int vcpu_id; 4325 4326 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4327 4328 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4329 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4330 error_append_hint(errp, "Adjust the number of cpus to %d " 4331 "or try to raise the number of threads per core\n", 4332 vcpu_id * ms->smp.threads / spapr->vsmt); 4333 return false; 4334 } 4335 4336 cpu->vcpu_id = vcpu_id; 4337 return true; 4338 } 4339 4340 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4341 { 4342 CPUState *cs; 4343 4344 CPU_FOREACH(cs) { 4345 PowerPCCPU *cpu = POWERPC_CPU(cs); 4346 4347 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4348 return cpu; 4349 } 4350 } 4351 4352 return NULL; 4353 } 4354 4355 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4356 { 4357 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4358 4359 /* These are only called by TCG, KVM maintains dispatch state */ 4360 4361 spapr_cpu->prod = false; 4362 if (spapr_cpu->vpa_addr) { 4363 CPUState *cs = CPU(cpu); 4364 uint32_t dispatch; 4365 4366 dispatch = ldl_be_phys(cs->as, 4367 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4368 dispatch++; 4369 if ((dispatch & 1) != 0) { 4370 qemu_log_mask(LOG_GUEST_ERROR, 4371 "VPA: incorrect dispatch counter value for " 4372 "dispatched partition %u, correcting.\n", dispatch); 4373 dispatch++; 4374 } 4375 stl_be_phys(cs->as, 4376 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4377 } 4378 } 4379 4380 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4381 { 4382 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4383 4384 if (spapr_cpu->vpa_addr) { 4385 CPUState *cs = CPU(cpu); 4386 uint32_t dispatch; 4387 4388 dispatch = ldl_be_phys(cs->as, 4389 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4390 dispatch++; 4391 if ((dispatch & 1) != 1) { 4392 qemu_log_mask(LOG_GUEST_ERROR, 4393 "VPA: incorrect dispatch counter value for " 4394 "preempted partition %u, correcting.\n", dispatch); 4395 dispatch++; 4396 } 4397 stl_be_phys(cs->as, 4398 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4399 } 4400 } 4401 4402 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4403 { 4404 MachineClass *mc = MACHINE_CLASS(oc); 4405 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4406 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4407 NMIClass *nc = NMI_CLASS(oc); 4408 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4409 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4410 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4411 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4412 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4413 4414 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4415 mc->ignore_boot_device_suffixes = true; 4416 4417 /* 4418 * We set up the default / latest behaviour here. The class_init 4419 * functions for the specific versioned machine types can override 4420 * these details for backwards compatibility 4421 */ 4422 mc->init = spapr_machine_init; 4423 mc->reset = spapr_machine_reset; 4424 mc->block_default_type = IF_SCSI; 4425 mc->max_cpus = 1024; 4426 mc->no_parallel = 1; 4427 mc->default_boot_order = ""; 4428 mc->default_ram_size = 512 * MiB; 4429 mc->default_ram_id = "ppc_spapr.ram"; 4430 mc->default_display = "std"; 4431 mc->kvm_type = spapr_kvm_type; 4432 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4433 mc->pci_allow_0_address = true; 4434 assert(!mc->get_hotplug_handler); 4435 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4436 hc->pre_plug = spapr_machine_device_pre_plug; 4437 hc->plug = spapr_machine_device_plug; 4438 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4439 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4440 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4441 hc->unplug_request = spapr_machine_device_unplug_request; 4442 hc->unplug = spapr_machine_device_unplug; 4443 4444 smc->dr_lmb_enabled = true; 4445 smc->update_dt_enabled = true; 4446 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4447 mc->has_hotpluggable_cpus = true; 4448 mc->nvdimm_supported = true; 4449 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4450 fwc->get_dev_path = spapr_get_fw_dev_path; 4451 nc->nmi_monitor_handler = spapr_nmi; 4452 smc->phb_placement = spapr_phb_placement; 4453 vhc->hypercall = emulate_spapr_hypercall; 4454 vhc->hpt_mask = spapr_hpt_mask; 4455 vhc->map_hptes = spapr_map_hptes; 4456 vhc->unmap_hptes = spapr_unmap_hptes; 4457 vhc->hpte_set_c = spapr_hpte_set_c; 4458 vhc->hpte_set_r = spapr_hpte_set_r; 4459 vhc->get_pate = spapr_get_pate; 4460 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4461 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4462 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4463 xic->ics_get = spapr_ics_get; 4464 xic->ics_resend = spapr_ics_resend; 4465 xic->icp_get = spapr_icp_get; 4466 ispc->print_info = spapr_pic_print_info; 4467 /* Force NUMA node memory size to be a multiple of 4468 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4469 * in which LMBs are represented and hot-added 4470 */ 4471 mc->numa_mem_align_shift = 28; 4472 mc->auto_enable_numa = true; 4473 4474 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4475 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4476 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4477 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4478 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4479 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4480 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4481 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4482 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4483 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4484 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4485 spapr_caps_add_properties(smc); 4486 smc->irq = &spapr_irq_dual; 4487 smc->dr_phb_enabled = true; 4488 smc->linux_pci_probe = true; 4489 smc->smp_threads_vsmt = true; 4490 smc->nr_xirqs = SPAPR_NR_XIRQS; 4491 xfc->match_nvt = spapr_match_nvt; 4492 } 4493 4494 static const TypeInfo spapr_machine_info = { 4495 .name = TYPE_SPAPR_MACHINE, 4496 .parent = TYPE_MACHINE, 4497 .abstract = true, 4498 .instance_size = sizeof(SpaprMachineState), 4499 .instance_init = spapr_instance_init, 4500 .instance_finalize = spapr_machine_finalizefn, 4501 .class_size = sizeof(SpaprMachineClass), 4502 .class_init = spapr_machine_class_init, 4503 .interfaces = (InterfaceInfo[]) { 4504 { TYPE_FW_PATH_PROVIDER }, 4505 { TYPE_NMI }, 4506 { TYPE_HOTPLUG_HANDLER }, 4507 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4508 { TYPE_XICS_FABRIC }, 4509 { TYPE_INTERRUPT_STATS_PROVIDER }, 4510 { TYPE_XIVE_FABRIC }, 4511 { } 4512 }, 4513 }; 4514 4515 static void spapr_machine_latest_class_options(MachineClass *mc) 4516 { 4517 mc->alias = "pseries"; 4518 mc->is_default = true; 4519 } 4520 4521 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4522 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4523 void *data) \ 4524 { \ 4525 MachineClass *mc = MACHINE_CLASS(oc); \ 4526 spapr_machine_##suffix##_class_options(mc); \ 4527 if (latest) { \ 4528 spapr_machine_latest_class_options(mc); \ 4529 } \ 4530 } \ 4531 static const TypeInfo spapr_machine_##suffix##_info = { \ 4532 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4533 .parent = TYPE_SPAPR_MACHINE, \ 4534 .class_init = spapr_machine_##suffix##_class_init, \ 4535 }; \ 4536 static void spapr_machine_register_##suffix(void) \ 4537 { \ 4538 type_register(&spapr_machine_##suffix##_info); \ 4539 } \ 4540 type_init(spapr_machine_register_##suffix) 4541 4542 /* 4543 * pseries-6.0 4544 */ 4545 static void spapr_machine_6_0_class_options(MachineClass *mc) 4546 { 4547 /* Defaults for the latest behaviour inherited from the base class */ 4548 } 4549 4550 DEFINE_SPAPR_MACHINE(6_0, "6.0", true); 4551 4552 /* 4553 * pseries-5.2 4554 */ 4555 static void spapr_machine_5_2_class_options(MachineClass *mc) 4556 { 4557 spapr_machine_6_0_class_options(mc); 4558 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4559 } 4560 4561 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4562 4563 /* 4564 * pseries-5.1 4565 */ 4566 static void spapr_machine_5_1_class_options(MachineClass *mc) 4567 { 4568 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4569 4570 spapr_machine_5_2_class_options(mc); 4571 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4572 smc->pre_5_2_numa_associativity = true; 4573 } 4574 4575 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4576 4577 /* 4578 * pseries-5.0 4579 */ 4580 static void spapr_machine_5_0_class_options(MachineClass *mc) 4581 { 4582 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4583 static GlobalProperty compat[] = { 4584 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4585 }; 4586 4587 spapr_machine_5_1_class_options(mc); 4588 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4589 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4590 mc->numa_mem_supported = true; 4591 smc->pre_5_1_assoc_refpoints = true; 4592 } 4593 4594 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4595 4596 /* 4597 * pseries-4.2 4598 */ 4599 static void spapr_machine_4_2_class_options(MachineClass *mc) 4600 { 4601 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4602 4603 spapr_machine_5_0_class_options(mc); 4604 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4605 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4606 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4607 smc->rma_limit = 16 * GiB; 4608 mc->nvdimm_supported = false; 4609 } 4610 4611 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4612 4613 /* 4614 * pseries-4.1 4615 */ 4616 static void spapr_machine_4_1_class_options(MachineClass *mc) 4617 { 4618 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4619 static GlobalProperty compat[] = { 4620 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4621 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4622 }; 4623 4624 spapr_machine_4_2_class_options(mc); 4625 smc->linux_pci_probe = false; 4626 smc->smp_threads_vsmt = false; 4627 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4628 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4629 } 4630 4631 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4632 4633 /* 4634 * pseries-4.0 4635 */ 4636 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4637 uint64_t *buid, hwaddr *pio, 4638 hwaddr *mmio32, hwaddr *mmio64, 4639 unsigned n_dma, uint32_t *liobns, 4640 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4641 { 4642 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 4643 liobns, nv2gpa, nv2atsd, errp)) { 4644 return false; 4645 } 4646 4647 *nv2gpa = 0; 4648 *nv2atsd = 0; 4649 return true; 4650 } 4651 static void spapr_machine_4_0_class_options(MachineClass *mc) 4652 { 4653 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4654 4655 spapr_machine_4_1_class_options(mc); 4656 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4657 smc->phb_placement = phb_placement_4_0; 4658 smc->irq = &spapr_irq_xics; 4659 smc->pre_4_1_migration = true; 4660 } 4661 4662 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4663 4664 /* 4665 * pseries-3.1 4666 */ 4667 static void spapr_machine_3_1_class_options(MachineClass *mc) 4668 { 4669 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4670 4671 spapr_machine_4_0_class_options(mc); 4672 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4673 4674 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4675 smc->update_dt_enabled = false; 4676 smc->dr_phb_enabled = false; 4677 smc->broken_host_serial_model = true; 4678 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4679 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4680 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4681 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4682 } 4683 4684 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4685 4686 /* 4687 * pseries-3.0 4688 */ 4689 4690 static void spapr_machine_3_0_class_options(MachineClass *mc) 4691 { 4692 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4693 4694 spapr_machine_3_1_class_options(mc); 4695 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4696 4697 smc->legacy_irq_allocation = true; 4698 smc->nr_xirqs = 0x400; 4699 smc->irq = &spapr_irq_xics_legacy; 4700 } 4701 4702 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4703 4704 /* 4705 * pseries-2.12 4706 */ 4707 static void spapr_machine_2_12_class_options(MachineClass *mc) 4708 { 4709 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4710 static GlobalProperty compat[] = { 4711 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4712 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4713 }; 4714 4715 spapr_machine_3_0_class_options(mc); 4716 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4717 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4718 4719 /* We depend on kvm_enabled() to choose a default value for the 4720 * hpt-max-page-size capability. Of course we can't do it here 4721 * because this is too early and the HW accelerator isn't initialzed 4722 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4723 */ 4724 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4725 } 4726 4727 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4728 4729 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4730 { 4731 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4732 4733 spapr_machine_2_12_class_options(mc); 4734 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4735 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4736 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4737 } 4738 4739 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4740 4741 /* 4742 * pseries-2.11 4743 */ 4744 4745 static void spapr_machine_2_11_class_options(MachineClass *mc) 4746 { 4747 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4748 4749 spapr_machine_2_12_class_options(mc); 4750 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4751 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4752 } 4753 4754 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4755 4756 /* 4757 * pseries-2.10 4758 */ 4759 4760 static void spapr_machine_2_10_class_options(MachineClass *mc) 4761 { 4762 spapr_machine_2_11_class_options(mc); 4763 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4764 } 4765 4766 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4767 4768 /* 4769 * pseries-2.9 4770 */ 4771 4772 static void spapr_machine_2_9_class_options(MachineClass *mc) 4773 { 4774 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4775 static GlobalProperty compat[] = { 4776 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4777 }; 4778 4779 spapr_machine_2_10_class_options(mc); 4780 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4781 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4782 smc->pre_2_10_has_unused_icps = true; 4783 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4784 } 4785 4786 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4787 4788 /* 4789 * pseries-2.8 4790 */ 4791 4792 static void spapr_machine_2_8_class_options(MachineClass *mc) 4793 { 4794 static GlobalProperty compat[] = { 4795 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4796 }; 4797 4798 spapr_machine_2_9_class_options(mc); 4799 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4800 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4801 mc->numa_mem_align_shift = 23; 4802 } 4803 4804 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4805 4806 /* 4807 * pseries-2.7 4808 */ 4809 4810 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4811 uint64_t *buid, hwaddr *pio, 4812 hwaddr *mmio32, hwaddr *mmio64, 4813 unsigned n_dma, uint32_t *liobns, 4814 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4815 { 4816 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4817 const uint64_t base_buid = 0x800000020000000ULL; 4818 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4819 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4820 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4821 const uint32_t max_index = 255; 4822 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4823 4824 uint64_t ram_top = MACHINE(spapr)->ram_size; 4825 hwaddr phb0_base, phb_base; 4826 int i; 4827 4828 /* Do we have device memory? */ 4829 if (MACHINE(spapr)->maxram_size > ram_top) { 4830 /* Can't just use maxram_size, because there may be an 4831 * alignment gap between normal and device memory regions 4832 */ 4833 ram_top = MACHINE(spapr)->device_memory->base + 4834 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4835 } 4836 4837 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4838 4839 if (index > max_index) { 4840 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4841 max_index); 4842 return false; 4843 } 4844 4845 *buid = base_buid + index; 4846 for (i = 0; i < n_dma; ++i) { 4847 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4848 } 4849 4850 phb_base = phb0_base + index * phb_spacing; 4851 *pio = phb_base + pio_offset; 4852 *mmio32 = phb_base + mmio_offset; 4853 /* 4854 * We don't set the 64-bit MMIO window, relying on the PHB's 4855 * fallback behaviour of automatically splitting a large "32-bit" 4856 * window into contiguous 32-bit and 64-bit windows 4857 */ 4858 4859 *nv2gpa = 0; 4860 *nv2atsd = 0; 4861 return true; 4862 } 4863 4864 static void spapr_machine_2_7_class_options(MachineClass *mc) 4865 { 4866 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4867 static GlobalProperty compat[] = { 4868 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4869 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4870 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4871 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4872 }; 4873 4874 spapr_machine_2_8_class_options(mc); 4875 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4876 mc->default_machine_opts = "modern-hotplug-events=off"; 4877 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4878 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4879 smc->phb_placement = phb_placement_2_7; 4880 } 4881 4882 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4883 4884 /* 4885 * pseries-2.6 4886 */ 4887 4888 static void spapr_machine_2_6_class_options(MachineClass *mc) 4889 { 4890 static GlobalProperty compat[] = { 4891 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4892 }; 4893 4894 spapr_machine_2_7_class_options(mc); 4895 mc->has_hotpluggable_cpus = false; 4896 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4897 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4898 } 4899 4900 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4901 4902 /* 4903 * pseries-2.5 4904 */ 4905 4906 static void spapr_machine_2_5_class_options(MachineClass *mc) 4907 { 4908 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4909 static GlobalProperty compat[] = { 4910 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4911 }; 4912 4913 spapr_machine_2_6_class_options(mc); 4914 smc->use_ohci_by_default = true; 4915 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4916 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4917 } 4918 4919 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4920 4921 /* 4922 * pseries-2.4 4923 */ 4924 4925 static void spapr_machine_2_4_class_options(MachineClass *mc) 4926 { 4927 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4928 4929 spapr_machine_2_5_class_options(mc); 4930 smc->dr_lmb_enabled = false; 4931 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4932 } 4933 4934 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4935 4936 /* 4937 * pseries-2.3 4938 */ 4939 4940 static void spapr_machine_2_3_class_options(MachineClass *mc) 4941 { 4942 static GlobalProperty compat[] = { 4943 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4944 }; 4945 spapr_machine_2_4_class_options(mc); 4946 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4947 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4948 } 4949 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4950 4951 /* 4952 * pseries-2.2 4953 */ 4954 4955 static void spapr_machine_2_2_class_options(MachineClass *mc) 4956 { 4957 static GlobalProperty compat[] = { 4958 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4959 }; 4960 4961 spapr_machine_2_3_class_options(mc); 4962 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4963 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4964 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4965 } 4966 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4967 4968 /* 4969 * pseries-2.1 4970 */ 4971 4972 static void spapr_machine_2_1_class_options(MachineClass *mc) 4973 { 4974 spapr_machine_2_2_class_options(mc); 4975 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4976 } 4977 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4978 4979 static void spapr_machine_register_types(void) 4980 { 4981 type_register_static(&spapr_machine_info); 4982 } 4983 4984 type_init(spapr_machine_register_types) 4985