1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qapi/error.h" 30 #include "qapi/visitor.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/hostmem.h" 33 #include "sysemu/numa.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/runstate.h" 37 #include "qemu/log.h" 38 #include "hw/fw-path-provider.h" 39 #include "elf.h" 40 #include "net/net.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/cpus.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_ppc.h" 45 #include "migration/misc.h" 46 #include "migration/qemu-file-types.h" 47 #include "migration/global_state.h" 48 #include "migration/register.h" 49 #include "migration/blocker.h" 50 #include "mmu-hash64.h" 51 #include "mmu-book3s-v3.h" 52 #include "cpu-models.h" 53 #include "hw/core/cpu.h" 54 55 #include "hw/boards.h" 56 #include "hw/ppc/ppc.h" 57 #include "hw/loader.h" 58 59 #include "hw/ppc/fdt.h" 60 #include "hw/ppc/spapr.h" 61 #include "hw/ppc/spapr_vio.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/pci-host/spapr.h" 64 #include "hw/pci/msi.h" 65 66 #include "hw/pci/pci.h" 67 #include "hw/scsi/scsi.h" 68 #include "hw/virtio/virtio-scsi.h" 69 #include "hw/virtio/vhost-scsi-common.h" 70 71 #include "exec/address-spaces.h" 72 #include "exec/ram_addr.h" 73 #include "hw/usb.h" 74 #include "qemu/config-file.h" 75 #include "qemu/error-report.h" 76 #include "trace.h" 77 #include "hw/nmi.h" 78 #include "hw/intc/intc.h" 79 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 #include "hw/ppc/spapr_nvdimm.h" 84 #include "hw/ppc/spapr_numa.h" 85 86 #include "monitor/monitor.h" 87 88 #include <libfdt.h> 89 90 /* SLOF memory layout: 91 * 92 * SLOF raw image loaded at 0, copies its romfs right below the flat 93 * device-tree, then position SLOF itself 31M below that 94 * 95 * So we set FW_OVERHEAD to 40MB which should account for all of that 96 * and more 97 * 98 * We load our kernel at 4M, leaving space for SLOF initial image 99 */ 100 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 101 #define FW_MAX_SIZE 0x400000 102 #define FW_FILE_NAME "slof.bin" 103 #define FW_OVERHEAD 0x2800000 104 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 105 106 #define MIN_RMA_SLOF (128 * MiB) 107 108 #define PHANDLE_INTC 0x00001111 109 110 /* These two functions implement the VCPU id numbering: one to compute them 111 * all and one to identify thread 0 of a VCORE. Any change to the first one 112 * is likely to have an impact on the second one, so let's keep them close. 113 */ 114 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 115 { 116 MachineState *ms = MACHINE(spapr); 117 unsigned int smp_threads = ms->smp.threads; 118 119 assert(spapr->vsmt); 120 return 121 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 122 } 123 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 124 PowerPCCPU *cpu) 125 { 126 assert(spapr->vsmt); 127 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 128 } 129 130 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 131 { 132 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 133 * and newer QEMUs don't even have them. In both cases, we don't want 134 * to send anything on the wire. 135 */ 136 return false; 137 } 138 139 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 140 .name = "icp/server", 141 .version_id = 1, 142 .minimum_version_id = 1, 143 .needed = pre_2_10_vmstate_dummy_icp_needed, 144 .fields = (VMStateField[]) { 145 VMSTATE_UNUSED(4), /* uint32_t xirr */ 146 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 147 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 148 VMSTATE_END_OF_LIST() 149 }, 150 }; 151 152 static void pre_2_10_vmstate_register_dummy_icp(int i) 153 { 154 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 155 (void *)(uintptr_t) i); 156 } 157 158 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 159 { 160 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 161 (void *)(uintptr_t) i); 162 } 163 164 int spapr_max_server_number(SpaprMachineState *spapr) 165 { 166 MachineState *ms = MACHINE(spapr); 167 168 assert(spapr->vsmt); 169 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 170 } 171 172 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 173 int smt_threads) 174 { 175 int i, ret = 0; 176 uint32_t servers_prop[smt_threads]; 177 uint32_t gservers_prop[smt_threads * 2]; 178 int index = spapr_get_vcpu_id(cpu); 179 180 if (cpu->compat_pvr) { 181 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 182 if (ret < 0) { 183 return ret; 184 } 185 } 186 187 /* Build interrupt servers and gservers properties */ 188 for (i = 0; i < smt_threads; i++) { 189 servers_prop[i] = cpu_to_be32(index + i); 190 /* Hack, direct the group queues back to cpu 0 */ 191 gservers_prop[i*2] = cpu_to_be32(index + i); 192 gservers_prop[i*2 + 1] = 0; 193 } 194 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 195 servers_prop, sizeof(servers_prop)); 196 if (ret < 0) { 197 return ret; 198 } 199 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 200 gservers_prop, sizeof(gservers_prop)); 201 202 return ret; 203 } 204 205 static void spapr_dt_pa_features(SpaprMachineState *spapr, 206 PowerPCCPU *cpu, 207 void *fdt, int offset) 208 { 209 uint8_t pa_features_206[] = { 6, 0, 210 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 211 uint8_t pa_features_207[] = { 24, 0, 212 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 213 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 214 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 215 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 216 uint8_t pa_features_300[] = { 66, 0, 217 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 218 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 219 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 220 /* 6: DS207 */ 221 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 222 /* 16: Vector */ 223 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 224 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 225 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 226 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 227 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 228 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 229 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 230 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 231 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 232 /* 42: PM, 44: PC RA, 46: SC vec'd */ 233 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 234 /* 48: SIMD, 50: QP BFP, 52: String */ 235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 236 /* 54: DecFP, 56: DecI, 58: SHA */ 237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 238 /* 60: NM atomic, 62: RNG */ 239 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 240 }; 241 uint8_t *pa_features = NULL; 242 size_t pa_size; 243 244 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 245 pa_features = pa_features_206; 246 pa_size = sizeof(pa_features_206); 247 } 248 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 249 pa_features = pa_features_207; 250 pa_size = sizeof(pa_features_207); 251 } 252 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 253 pa_features = pa_features_300; 254 pa_size = sizeof(pa_features_300); 255 } 256 if (!pa_features) { 257 return; 258 } 259 260 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 261 /* 262 * Note: we keep CI large pages off by default because a 64K capable 263 * guest provisioned with large pages might otherwise try to map a qemu 264 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 265 * even if that qemu runs on a 4k host. 266 * We dd this bit back here if we are confident this is not an issue 267 */ 268 pa_features[3] |= 0x20; 269 } 270 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 271 pa_features[24] |= 0x80; /* Transactional memory support */ 272 } 273 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 274 /* Workaround for broken kernels that attempt (guest) radix 275 * mode when they can't handle it, if they see the radix bit set 276 * in pa-features. So hide it from them. */ 277 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 278 } 279 280 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 281 } 282 283 static hwaddr spapr_node0_size(MachineState *machine) 284 { 285 if (machine->numa_state->num_nodes) { 286 int i; 287 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 288 if (machine->numa_state->nodes[i].node_mem) { 289 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 290 machine->ram_size); 291 } 292 } 293 } 294 return machine->ram_size; 295 } 296 297 bool spapr_machine_using_legacy_numa(SpaprMachineState *spapr) 298 { 299 MachineState *machine = MACHINE(spapr); 300 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 301 302 return smc->pre_5_2_numa_associativity || 303 machine->numa_state->num_nodes <= 1; 304 } 305 306 static void add_str(GString *s, const gchar *s1) 307 { 308 g_string_append_len(s, s1, strlen(s1) + 1); 309 } 310 311 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 312 hwaddr start, hwaddr size) 313 { 314 char mem_name[32]; 315 uint64_t mem_reg_property[2]; 316 int off; 317 318 mem_reg_property[0] = cpu_to_be64(start); 319 mem_reg_property[1] = cpu_to_be64(size); 320 321 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 322 off = fdt_add_subnode(fdt, 0, mem_name); 323 _FDT(off); 324 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 325 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 326 sizeof(mem_reg_property)))); 327 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 328 return off; 329 } 330 331 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 332 { 333 MemoryDeviceInfoList *info; 334 335 for (info = list; info; info = info->next) { 336 MemoryDeviceInfo *value = info->value; 337 338 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 339 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 340 341 if (addr >= pcdimm_info->addr && 342 addr < (pcdimm_info->addr + pcdimm_info->size)) { 343 return pcdimm_info->node; 344 } 345 } 346 } 347 348 return -1; 349 } 350 351 struct sPAPRDrconfCellV2 { 352 uint32_t seq_lmbs; 353 uint64_t base_addr; 354 uint32_t drc_index; 355 uint32_t aa_index; 356 uint32_t flags; 357 } QEMU_PACKED; 358 359 typedef struct DrconfCellQueue { 360 struct sPAPRDrconfCellV2 cell; 361 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 362 } DrconfCellQueue; 363 364 static DrconfCellQueue * 365 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 366 uint32_t drc_index, uint32_t aa_index, 367 uint32_t flags) 368 { 369 DrconfCellQueue *elem; 370 371 elem = g_malloc0(sizeof(*elem)); 372 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 373 elem->cell.base_addr = cpu_to_be64(base_addr); 374 elem->cell.drc_index = cpu_to_be32(drc_index); 375 elem->cell.aa_index = cpu_to_be32(aa_index); 376 elem->cell.flags = cpu_to_be32(flags); 377 378 return elem; 379 } 380 381 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 382 int offset, MemoryDeviceInfoList *dimms) 383 { 384 MachineState *machine = MACHINE(spapr); 385 uint8_t *int_buf, *cur_index; 386 int ret; 387 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 388 uint64_t addr, cur_addr, size; 389 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 390 uint64_t mem_end = machine->device_memory->base + 391 memory_region_size(&machine->device_memory->mr); 392 uint32_t node, buf_len, nr_entries = 0; 393 SpaprDrc *drc; 394 DrconfCellQueue *elem, *next; 395 MemoryDeviceInfoList *info; 396 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 397 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 398 399 /* Entry to cover RAM and the gap area */ 400 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 401 SPAPR_LMB_FLAGS_RESERVED | 402 SPAPR_LMB_FLAGS_DRC_INVALID); 403 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 404 nr_entries++; 405 406 cur_addr = machine->device_memory->base; 407 for (info = dimms; info; info = info->next) { 408 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 409 410 addr = di->addr; 411 size = di->size; 412 node = di->node; 413 414 /* 415 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 416 * area is marked hotpluggable in the next iteration for the bigger 417 * chunk including the NVDIMM occupied area. 418 */ 419 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 420 continue; 421 422 /* Entry for hot-pluggable area */ 423 if (cur_addr < addr) { 424 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 425 g_assert(drc); 426 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 427 cur_addr, spapr_drc_index(drc), -1, 0); 428 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 429 nr_entries++; 430 } 431 432 /* Entry for DIMM */ 433 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 434 g_assert(drc); 435 elem = spapr_get_drconf_cell(size / lmb_size, addr, 436 spapr_drc_index(drc), node, 437 (SPAPR_LMB_FLAGS_ASSIGNED | 438 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 439 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 440 nr_entries++; 441 cur_addr = addr + size; 442 } 443 444 /* Entry for remaining hotpluggable area */ 445 if (cur_addr < mem_end) { 446 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 447 g_assert(drc); 448 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 449 cur_addr, spapr_drc_index(drc), -1, 0); 450 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 451 nr_entries++; 452 } 453 454 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 455 int_buf = cur_index = g_malloc0(buf_len); 456 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 457 cur_index += sizeof(nr_entries); 458 459 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 460 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 461 cur_index += sizeof(elem->cell); 462 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 463 g_free(elem); 464 } 465 466 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 467 g_free(int_buf); 468 if (ret < 0) { 469 return -1; 470 } 471 return 0; 472 } 473 474 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 475 int offset, MemoryDeviceInfoList *dimms) 476 { 477 MachineState *machine = MACHINE(spapr); 478 int i, ret; 479 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 480 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 481 uint32_t nr_lmbs = (machine->device_memory->base + 482 memory_region_size(&machine->device_memory->mr)) / 483 lmb_size; 484 uint32_t *int_buf, *cur_index, buf_len; 485 486 /* 487 * Allocate enough buffer size to fit in ibm,dynamic-memory 488 */ 489 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 490 cur_index = int_buf = g_malloc0(buf_len); 491 int_buf[0] = cpu_to_be32(nr_lmbs); 492 cur_index++; 493 for (i = 0; i < nr_lmbs; i++) { 494 uint64_t addr = i * lmb_size; 495 uint32_t *dynamic_memory = cur_index; 496 497 if (i >= device_lmb_start) { 498 SpaprDrc *drc; 499 500 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 501 g_assert(drc); 502 503 dynamic_memory[0] = cpu_to_be32(addr >> 32); 504 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 505 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 506 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 507 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 508 if (memory_region_present(get_system_memory(), addr)) { 509 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 510 } else { 511 dynamic_memory[5] = cpu_to_be32(0); 512 } 513 } else { 514 /* 515 * LMB information for RMA, boot time RAM and gap b/n RAM and 516 * device memory region -- all these are marked as reserved 517 * and as having no valid DRC. 518 */ 519 dynamic_memory[0] = cpu_to_be32(addr >> 32); 520 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 521 dynamic_memory[2] = cpu_to_be32(0); 522 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 523 dynamic_memory[4] = cpu_to_be32(-1); 524 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 525 SPAPR_LMB_FLAGS_DRC_INVALID); 526 } 527 528 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 529 } 530 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 531 g_free(int_buf); 532 if (ret < 0) { 533 return -1; 534 } 535 return 0; 536 } 537 538 /* 539 * Adds ibm,dynamic-reconfiguration-memory node. 540 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 541 * of this device tree node. 542 */ 543 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 544 void *fdt) 545 { 546 MachineState *machine = MACHINE(spapr); 547 int ret, offset; 548 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 549 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 550 cpu_to_be32(lmb_size & 0xffffffff)}; 551 MemoryDeviceInfoList *dimms = NULL; 552 553 /* 554 * Don't create the node if there is no device memory 555 */ 556 if (machine->ram_size == machine->maxram_size) { 557 return 0; 558 } 559 560 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 561 562 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 563 sizeof(prop_lmb_size)); 564 if (ret < 0) { 565 return ret; 566 } 567 568 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 569 if (ret < 0) { 570 return ret; 571 } 572 573 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 574 if (ret < 0) { 575 return ret; 576 } 577 578 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 579 dimms = qmp_memory_device_list(); 580 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 581 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 582 } else { 583 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 584 } 585 qapi_free_MemoryDeviceInfoList(dimms); 586 587 if (ret < 0) { 588 return ret; 589 } 590 591 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 592 593 return ret; 594 } 595 596 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 597 { 598 MachineState *machine = MACHINE(spapr); 599 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 600 hwaddr mem_start, node_size; 601 int i, nb_nodes = machine->numa_state->num_nodes; 602 NodeInfo *nodes = machine->numa_state->nodes; 603 604 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 605 if (!nodes[i].node_mem) { 606 continue; 607 } 608 if (mem_start >= machine->ram_size) { 609 node_size = 0; 610 } else { 611 node_size = nodes[i].node_mem; 612 if (node_size > machine->ram_size - mem_start) { 613 node_size = machine->ram_size - mem_start; 614 } 615 } 616 if (!mem_start) { 617 /* spapr_machine_init() checks for rma_size <= node0_size 618 * already */ 619 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 620 mem_start += spapr->rma_size; 621 node_size -= spapr->rma_size; 622 } 623 for ( ; node_size; ) { 624 hwaddr sizetmp = pow2floor(node_size); 625 626 /* mem_start != 0 here */ 627 if (ctzl(mem_start) < ctzl(sizetmp)) { 628 sizetmp = 1ULL << ctzl(mem_start); 629 } 630 631 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 632 node_size -= sizetmp; 633 mem_start += sizetmp; 634 } 635 } 636 637 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 638 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 639 int ret; 640 641 g_assert(smc->dr_lmb_enabled); 642 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 643 if (ret) { 644 return ret; 645 } 646 } 647 648 return 0; 649 } 650 651 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 652 SpaprMachineState *spapr) 653 { 654 MachineState *ms = MACHINE(spapr); 655 PowerPCCPU *cpu = POWERPC_CPU(cs); 656 CPUPPCState *env = &cpu->env; 657 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 658 int index = spapr_get_vcpu_id(cpu); 659 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 660 0xffffffff, 0xffffffff}; 661 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 662 : SPAPR_TIMEBASE_FREQ; 663 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 664 uint32_t page_sizes_prop[64]; 665 size_t page_sizes_prop_size; 666 unsigned int smp_threads = ms->smp.threads; 667 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 668 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 669 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 670 SpaprDrc *drc; 671 int drc_index; 672 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 673 int i; 674 675 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 676 if (drc) { 677 drc_index = spapr_drc_index(drc); 678 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 679 } 680 681 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 682 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 683 684 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 685 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 686 env->dcache_line_size))); 687 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 688 env->dcache_line_size))); 689 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 690 env->icache_line_size))); 691 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 692 env->icache_line_size))); 693 694 if (pcc->l1_dcache_size) { 695 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 696 pcc->l1_dcache_size))); 697 } else { 698 warn_report("Unknown L1 dcache size for cpu"); 699 } 700 if (pcc->l1_icache_size) { 701 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 702 pcc->l1_icache_size))); 703 } else { 704 warn_report("Unknown L1 icache size for cpu"); 705 } 706 707 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 708 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 709 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 710 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 711 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 712 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 713 714 if (env->spr_cb[SPR_PURR].oea_read) { 715 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 716 } 717 if (env->spr_cb[SPR_SPURR].oea_read) { 718 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 719 } 720 721 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 722 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 723 segs, sizeof(segs)))); 724 } 725 726 /* Advertise VSX (vector extensions) if available 727 * 1 == VMX / Altivec available 728 * 2 == VSX available 729 * 730 * Only CPUs for which we create core types in spapr_cpu_core.c 731 * are possible, and all of those have VMX */ 732 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 733 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 734 } else { 735 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 736 } 737 738 /* Advertise DFP (Decimal Floating Point) if available 739 * 0 / no property == no DFP 740 * 1 == DFP available */ 741 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 742 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 743 } 744 745 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 746 sizeof(page_sizes_prop)); 747 if (page_sizes_prop_size) { 748 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 749 page_sizes_prop, page_sizes_prop_size))); 750 } 751 752 spapr_dt_pa_features(spapr, cpu, fdt, offset); 753 754 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 755 cs->cpu_index / vcpus_per_socket))); 756 757 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 758 pft_size_prop, sizeof(pft_size_prop)))); 759 760 if (ms->numa_state->num_nodes > 1) { 761 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 762 } 763 764 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 765 766 if (pcc->radix_page_info) { 767 for (i = 0; i < pcc->radix_page_info->count; i++) { 768 radix_AP_encodings[i] = 769 cpu_to_be32(pcc->radix_page_info->entries[i]); 770 } 771 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 772 radix_AP_encodings, 773 pcc->radix_page_info->count * 774 sizeof(radix_AP_encodings[0])))); 775 } 776 777 /* 778 * We set this property to let the guest know that it can use the large 779 * decrementer and its width in bits. 780 */ 781 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 782 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 783 pcc->lrg_decr_bits))); 784 } 785 786 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 787 { 788 CPUState **rev; 789 CPUState *cs; 790 int n_cpus; 791 int cpus_offset; 792 char *nodename; 793 int i; 794 795 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 796 _FDT(cpus_offset); 797 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 798 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 799 800 /* 801 * We walk the CPUs in reverse order to ensure that CPU DT nodes 802 * created by fdt_add_subnode() end up in the right order in FDT 803 * for the guest kernel the enumerate the CPUs correctly. 804 * 805 * The CPU list cannot be traversed in reverse order, so we need 806 * to do extra work. 807 */ 808 n_cpus = 0; 809 rev = NULL; 810 CPU_FOREACH(cs) { 811 rev = g_renew(CPUState *, rev, n_cpus + 1); 812 rev[n_cpus++] = cs; 813 } 814 815 for (i = n_cpus - 1; i >= 0; i--) { 816 CPUState *cs = rev[i]; 817 PowerPCCPU *cpu = POWERPC_CPU(cs); 818 int index = spapr_get_vcpu_id(cpu); 819 DeviceClass *dc = DEVICE_GET_CLASS(cs); 820 int offset; 821 822 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 823 continue; 824 } 825 826 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 827 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 828 g_free(nodename); 829 _FDT(offset); 830 spapr_dt_cpu(cs, fdt, offset, spapr); 831 } 832 833 g_free(rev); 834 } 835 836 static int spapr_dt_rng(void *fdt) 837 { 838 int node; 839 int ret; 840 841 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 842 if (node <= 0) { 843 return -1; 844 } 845 ret = fdt_setprop_string(fdt, node, "device_type", 846 "ibm,platform-facilities"); 847 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 848 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 849 850 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 851 if (node <= 0) { 852 return -1; 853 } 854 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 855 856 return ret ? -1 : 0; 857 } 858 859 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 860 { 861 MachineState *ms = MACHINE(spapr); 862 int rtas; 863 GString *hypertas = g_string_sized_new(256); 864 GString *qemu_hypertas = g_string_sized_new(256); 865 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 866 memory_region_size(&MACHINE(spapr)->device_memory->mr); 867 uint32_t lrdr_capacity[] = { 868 cpu_to_be32(max_device_addr >> 32), 869 cpu_to_be32(max_device_addr & 0xffffffff), 870 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 871 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 872 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 873 }; 874 875 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 876 877 /* hypertas */ 878 add_str(hypertas, "hcall-pft"); 879 add_str(hypertas, "hcall-term"); 880 add_str(hypertas, "hcall-dabr"); 881 add_str(hypertas, "hcall-interrupt"); 882 add_str(hypertas, "hcall-tce"); 883 add_str(hypertas, "hcall-vio"); 884 add_str(hypertas, "hcall-splpar"); 885 add_str(hypertas, "hcall-join"); 886 add_str(hypertas, "hcall-bulk"); 887 add_str(hypertas, "hcall-set-mode"); 888 add_str(hypertas, "hcall-sprg0"); 889 add_str(hypertas, "hcall-copy"); 890 add_str(hypertas, "hcall-debug"); 891 add_str(hypertas, "hcall-vphn"); 892 add_str(qemu_hypertas, "hcall-memop1"); 893 894 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 895 add_str(hypertas, "hcall-multi-tce"); 896 } 897 898 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 899 add_str(hypertas, "hcall-hpt-resize"); 900 } 901 902 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 903 hypertas->str, hypertas->len)); 904 g_string_free(hypertas, TRUE); 905 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 906 qemu_hypertas->str, qemu_hypertas->len)); 907 g_string_free(qemu_hypertas, TRUE); 908 909 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 910 911 /* 912 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 913 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 914 * 915 * The system reset requirements are driven by existing Linux and PowerVM 916 * implementation which (contrary to PAPR) saves r3 in the error log 917 * structure like machine check, so Linux expects to find the saved r3 918 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 919 * does not look at the error value). 920 * 921 * System reset interrupts are not subject to interlock like machine 922 * check, so this memory area could be corrupted if the sreset is 923 * interrupted by a machine check (or vice versa) if it was shared. To 924 * prevent this, system reset uses per-CPU areas for the sreset save 925 * area. A system reset that interrupts a system reset handler could 926 * still overwrite this area, but Linux doesn't try to recover in that 927 * case anyway. 928 * 929 * The extra 8 bytes is required because Linux's FWNMI error log check 930 * is off-by-one. 931 */ 932 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX + 933 ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t))); 934 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 935 RTAS_ERROR_LOG_MAX)); 936 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 937 RTAS_EVENT_SCAN_RATE)); 938 939 g_assert(msi_nonbroken); 940 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 941 942 /* 943 * According to PAPR, rtas ibm,os-term does not guarantee a return 944 * back to the guest cpu. 945 * 946 * While an additional ibm,extended-os-term property indicates 947 * that rtas call return will always occur. Set this property. 948 */ 949 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 950 951 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 952 lrdr_capacity, sizeof(lrdr_capacity))); 953 954 spapr_dt_rtas_tokens(fdt, rtas); 955 } 956 957 /* 958 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 959 * and the XIVE features that the guest may request and thus the valid 960 * values for bytes 23..26 of option vector 5: 961 */ 962 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 963 int chosen) 964 { 965 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 966 967 char val[2 * 4] = { 968 23, 0x00, /* XICS / XIVE mode */ 969 24, 0x00, /* Hash/Radix, filled in below. */ 970 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 971 26, 0x40, /* Radix options: GTSE == yes. */ 972 }; 973 974 if (spapr->irq->xics && spapr->irq->xive) { 975 val[1] = SPAPR_OV5_XIVE_BOTH; 976 } else if (spapr->irq->xive) { 977 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 978 } else { 979 assert(spapr->irq->xics); 980 val[1] = SPAPR_OV5_XIVE_LEGACY; 981 } 982 983 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 984 first_ppc_cpu->compat_pvr)) { 985 /* 986 * If we're in a pre POWER9 compat mode then the guest should 987 * do hash and use the legacy interrupt mode 988 */ 989 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 990 val[3] = 0x00; /* Hash */ 991 } else if (kvm_enabled()) { 992 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 993 val[3] = 0x80; /* OV5_MMU_BOTH */ 994 } else if (kvmppc_has_cap_mmu_radix()) { 995 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 996 } else { 997 val[3] = 0x00; /* Hash */ 998 } 999 } else { 1000 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1001 val[3] = 0xC0; 1002 } 1003 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1004 val, sizeof(val))); 1005 } 1006 1007 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1008 { 1009 MachineState *machine = MACHINE(spapr); 1010 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1011 int chosen; 1012 1013 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1014 1015 if (reset) { 1016 const char *boot_device = machine->boot_order; 1017 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1018 size_t cb = 0; 1019 char *bootlist = get_boot_devices_list(&cb); 1020 1021 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1022 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1023 machine->kernel_cmdline)); 1024 } 1025 1026 if (spapr->initrd_size) { 1027 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1028 spapr->initrd_base)); 1029 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1030 spapr->initrd_base + spapr->initrd_size)); 1031 } 1032 1033 if (spapr->kernel_size) { 1034 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1035 cpu_to_be64(spapr->kernel_size) }; 1036 1037 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1038 &kprop, sizeof(kprop))); 1039 if (spapr->kernel_le) { 1040 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1041 } 1042 } 1043 if (boot_menu) { 1044 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1045 } 1046 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1047 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1048 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1049 1050 if (cb && bootlist) { 1051 int i; 1052 1053 for (i = 0; i < cb; i++) { 1054 if (bootlist[i] == '\n') { 1055 bootlist[i] = ' '; 1056 } 1057 } 1058 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1059 } 1060 1061 if (boot_device && strlen(boot_device)) { 1062 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1063 } 1064 1065 if (!spapr->has_graphics && stdout_path) { 1066 /* 1067 * "linux,stdout-path" and "stdout" properties are 1068 * deprecated by linux kernel. New platforms should only 1069 * use the "stdout-path" property. Set the new property 1070 * and continue using older property to remain compatible 1071 * with the existing firmware. 1072 */ 1073 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1074 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1075 } 1076 1077 /* 1078 * We can deal with BAR reallocation just fine, advertise it 1079 * to the guest 1080 */ 1081 if (smc->linux_pci_probe) { 1082 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1083 } 1084 1085 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1086 1087 g_free(stdout_path); 1088 g_free(bootlist); 1089 } 1090 1091 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1092 } 1093 1094 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1095 { 1096 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1097 * KVM to work under pHyp with some guest co-operation */ 1098 int hypervisor; 1099 uint8_t hypercall[16]; 1100 1101 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1102 /* indicate KVM hypercall interface */ 1103 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1104 if (kvmppc_has_cap_fixup_hcalls()) { 1105 /* 1106 * Older KVM versions with older guest kernels were broken 1107 * with the magic page, don't allow the guest to map it. 1108 */ 1109 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1110 sizeof(hypercall))) { 1111 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1112 hypercall, sizeof(hypercall))); 1113 } 1114 } 1115 } 1116 1117 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1118 { 1119 MachineState *machine = MACHINE(spapr); 1120 MachineClass *mc = MACHINE_GET_CLASS(machine); 1121 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1122 int ret; 1123 void *fdt; 1124 SpaprPhbState *phb; 1125 char *buf; 1126 1127 fdt = g_malloc0(space); 1128 _FDT((fdt_create_empty_tree(fdt, space))); 1129 1130 /* Root node */ 1131 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1132 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1133 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1134 1135 /* Guest UUID & Name*/ 1136 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1137 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1138 if (qemu_uuid_set) { 1139 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1140 } 1141 g_free(buf); 1142 1143 if (qemu_get_vm_name()) { 1144 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1145 qemu_get_vm_name())); 1146 } 1147 1148 /* Host Model & Serial Number */ 1149 if (spapr->host_model) { 1150 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1151 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1152 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1153 g_free(buf); 1154 } 1155 1156 if (spapr->host_serial) { 1157 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1158 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1159 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1160 g_free(buf); 1161 } 1162 1163 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1164 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1165 1166 /* /interrupt controller */ 1167 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1168 1169 ret = spapr_dt_memory(spapr, fdt); 1170 if (ret < 0) { 1171 error_report("couldn't setup memory nodes in fdt"); 1172 exit(1); 1173 } 1174 1175 /* /vdevice */ 1176 spapr_dt_vdevice(spapr->vio_bus, fdt); 1177 1178 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1179 ret = spapr_dt_rng(fdt); 1180 if (ret < 0) { 1181 error_report("could not set up rng device in the fdt"); 1182 exit(1); 1183 } 1184 } 1185 1186 QLIST_FOREACH(phb, &spapr->phbs, list) { 1187 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1188 if (ret < 0) { 1189 error_report("couldn't setup PCI devices in fdt"); 1190 exit(1); 1191 } 1192 } 1193 1194 spapr_dt_cpus(fdt, spapr); 1195 1196 if (smc->dr_lmb_enabled) { 1197 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1198 } 1199 1200 if (mc->has_hotpluggable_cpus) { 1201 int offset = fdt_path_offset(fdt, "/cpus"); 1202 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1203 if (ret < 0) { 1204 error_report("Couldn't set up CPU DR device tree properties"); 1205 exit(1); 1206 } 1207 } 1208 1209 /* /event-sources */ 1210 spapr_dt_events(spapr, fdt); 1211 1212 /* /rtas */ 1213 spapr_dt_rtas(spapr, fdt); 1214 1215 /* /chosen */ 1216 spapr_dt_chosen(spapr, fdt, reset); 1217 1218 /* /hypervisor */ 1219 if (kvm_enabled()) { 1220 spapr_dt_hypervisor(spapr, fdt); 1221 } 1222 1223 /* Build memory reserve map */ 1224 if (reset) { 1225 if (spapr->kernel_size) { 1226 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1227 spapr->kernel_size))); 1228 } 1229 if (spapr->initrd_size) { 1230 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1231 spapr->initrd_size))); 1232 } 1233 } 1234 1235 if (smc->dr_phb_enabled) { 1236 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); 1237 if (ret < 0) { 1238 error_report("Couldn't set up PHB DR device tree properties"); 1239 exit(1); 1240 } 1241 } 1242 1243 /* NVDIMM devices */ 1244 if (mc->nvdimm_supported) { 1245 spapr_dt_persistent_memory(spapr, fdt); 1246 } 1247 1248 return fdt; 1249 } 1250 1251 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1252 { 1253 SpaprMachineState *spapr = opaque; 1254 1255 return (addr & 0x0fffffff) + spapr->kernel_addr; 1256 } 1257 1258 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1259 PowerPCCPU *cpu) 1260 { 1261 CPUPPCState *env = &cpu->env; 1262 1263 /* The TCG path should also be holding the BQL at this point */ 1264 g_assert(qemu_mutex_iothread_locked()); 1265 1266 if (msr_pr) { 1267 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1268 env->gpr[3] = H_PRIVILEGE; 1269 } else { 1270 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1271 } 1272 } 1273 1274 struct LPCRSyncState { 1275 target_ulong value; 1276 target_ulong mask; 1277 }; 1278 1279 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1280 { 1281 struct LPCRSyncState *s = arg.host_ptr; 1282 PowerPCCPU *cpu = POWERPC_CPU(cs); 1283 CPUPPCState *env = &cpu->env; 1284 target_ulong lpcr; 1285 1286 cpu_synchronize_state(cs); 1287 lpcr = env->spr[SPR_LPCR]; 1288 lpcr &= ~s->mask; 1289 lpcr |= s->value; 1290 ppc_store_lpcr(cpu, lpcr); 1291 } 1292 1293 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1294 { 1295 CPUState *cs; 1296 struct LPCRSyncState s = { 1297 .value = value, 1298 .mask = mask 1299 }; 1300 CPU_FOREACH(cs) { 1301 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1302 } 1303 } 1304 1305 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1306 { 1307 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1308 1309 /* Copy PATE1:GR into PATE0:HR */ 1310 entry->dw0 = spapr->patb_entry & PATE0_HR; 1311 entry->dw1 = spapr->patb_entry; 1312 } 1313 1314 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1315 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1316 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1317 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1318 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1319 1320 /* 1321 * Get the fd to access the kernel htab, re-opening it if necessary 1322 */ 1323 static int get_htab_fd(SpaprMachineState *spapr) 1324 { 1325 Error *local_err = NULL; 1326 1327 if (spapr->htab_fd >= 0) { 1328 return spapr->htab_fd; 1329 } 1330 1331 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1332 if (spapr->htab_fd < 0) { 1333 error_report_err(local_err); 1334 } 1335 1336 return spapr->htab_fd; 1337 } 1338 1339 void close_htab_fd(SpaprMachineState *spapr) 1340 { 1341 if (spapr->htab_fd >= 0) { 1342 close(spapr->htab_fd); 1343 } 1344 spapr->htab_fd = -1; 1345 } 1346 1347 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1348 { 1349 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1350 1351 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1352 } 1353 1354 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1355 { 1356 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1357 1358 assert(kvm_enabled()); 1359 1360 if (!spapr->htab) { 1361 return 0; 1362 } 1363 1364 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1365 } 1366 1367 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1368 hwaddr ptex, int n) 1369 { 1370 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1371 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1372 1373 if (!spapr->htab) { 1374 /* 1375 * HTAB is controlled by KVM. Fetch into temporary buffer 1376 */ 1377 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1378 kvmppc_read_hptes(hptes, ptex, n); 1379 return hptes; 1380 } 1381 1382 /* 1383 * HTAB is controlled by QEMU. Just point to the internally 1384 * accessible PTEG. 1385 */ 1386 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1387 } 1388 1389 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1390 const ppc_hash_pte64_t *hptes, 1391 hwaddr ptex, int n) 1392 { 1393 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1394 1395 if (!spapr->htab) { 1396 g_free((void *)hptes); 1397 } 1398 1399 /* Nothing to do for qemu managed HPT */ 1400 } 1401 1402 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1403 uint64_t pte0, uint64_t pte1) 1404 { 1405 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1406 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1407 1408 if (!spapr->htab) { 1409 kvmppc_write_hpte(ptex, pte0, pte1); 1410 } else { 1411 if (pte0 & HPTE64_V_VALID) { 1412 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1413 /* 1414 * When setting valid, we write PTE1 first. This ensures 1415 * proper synchronization with the reading code in 1416 * ppc_hash64_pteg_search() 1417 */ 1418 smp_wmb(); 1419 stq_p(spapr->htab + offset, pte0); 1420 } else { 1421 stq_p(spapr->htab + offset, pte0); 1422 /* 1423 * When clearing it we set PTE0 first. This ensures proper 1424 * synchronization with the reading code in 1425 * ppc_hash64_pteg_search() 1426 */ 1427 smp_wmb(); 1428 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1429 } 1430 } 1431 } 1432 1433 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1434 uint64_t pte1) 1435 { 1436 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1437 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1438 1439 if (!spapr->htab) { 1440 /* There should always be a hash table when this is called */ 1441 error_report("spapr_hpte_set_c called with no hash table !"); 1442 return; 1443 } 1444 1445 /* The HW performs a non-atomic byte update */ 1446 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1447 } 1448 1449 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1450 uint64_t pte1) 1451 { 1452 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1453 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1454 1455 if (!spapr->htab) { 1456 /* There should always be a hash table when this is called */ 1457 error_report("spapr_hpte_set_r called with no hash table !"); 1458 return; 1459 } 1460 1461 /* The HW performs a non-atomic byte update */ 1462 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1463 } 1464 1465 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1466 { 1467 int shift; 1468 1469 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1470 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1471 * that's much more than is needed for Linux guests */ 1472 shift = ctz64(pow2ceil(ramsize)) - 7; 1473 shift = MAX(shift, 18); /* Minimum architected size */ 1474 shift = MIN(shift, 46); /* Maximum architected size */ 1475 return shift; 1476 } 1477 1478 void spapr_free_hpt(SpaprMachineState *spapr) 1479 { 1480 g_free(spapr->htab); 1481 spapr->htab = NULL; 1482 spapr->htab_shift = 0; 1483 close_htab_fd(spapr); 1484 } 1485 1486 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1487 { 1488 ERRP_GUARD(); 1489 long rc; 1490 1491 /* Clean up any HPT info from a previous boot */ 1492 spapr_free_hpt(spapr); 1493 1494 rc = kvmppc_reset_htab(shift); 1495 1496 if (rc == -EOPNOTSUPP) { 1497 error_setg(errp, "HPT not supported in nested guests"); 1498 return -EOPNOTSUPP; 1499 } 1500 1501 if (rc < 0) { 1502 /* kernel-side HPT needed, but couldn't allocate one */ 1503 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1504 shift); 1505 error_append_hint(errp, "Try smaller maxmem?\n"); 1506 return -errno; 1507 } else if (rc > 0) { 1508 /* kernel-side HPT allocated */ 1509 if (rc != shift) { 1510 error_setg(errp, 1511 "Requested order %d HPT, but kernel allocated order %ld", 1512 shift, rc); 1513 error_append_hint(errp, "Try smaller maxmem?\n"); 1514 return -ENOSPC; 1515 } 1516 1517 spapr->htab_shift = shift; 1518 spapr->htab = NULL; 1519 } else { 1520 /* kernel-side HPT not needed, allocate in userspace instead */ 1521 size_t size = 1ULL << shift; 1522 int i; 1523 1524 spapr->htab = qemu_memalign(size, size); 1525 if (!spapr->htab) { 1526 error_setg_errno(errp, errno, 1527 "Could not allocate HPT of order %d", shift); 1528 return -ENOMEM; 1529 } 1530 1531 memset(spapr->htab, 0, size); 1532 spapr->htab_shift = shift; 1533 1534 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1535 DIRTY_HPTE(HPTE(spapr->htab, i)); 1536 } 1537 } 1538 /* We're setting up a hash table, so that means we're not radix */ 1539 spapr->patb_entry = 0; 1540 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1541 return 0; 1542 } 1543 1544 void spapr_setup_hpt(SpaprMachineState *spapr) 1545 { 1546 int hpt_shift; 1547 1548 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1549 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1550 } else { 1551 uint64_t current_ram_size; 1552 1553 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1554 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1555 } 1556 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1557 1558 if (kvm_enabled()) { 1559 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1560 1561 /* Check our RMA fits in the possible VRMA */ 1562 if (vrma_limit < spapr->rma_size) { 1563 error_report("Unable to create %" HWADDR_PRIu 1564 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1565 spapr->rma_size / MiB, vrma_limit / MiB); 1566 exit(EXIT_FAILURE); 1567 } 1568 } 1569 } 1570 1571 static int spapr_reset_drcs(Object *child, void *opaque) 1572 { 1573 SpaprDrc *drc = 1574 (SpaprDrc *) object_dynamic_cast(child, 1575 TYPE_SPAPR_DR_CONNECTOR); 1576 1577 if (drc) { 1578 spapr_drc_reset(drc); 1579 } 1580 1581 return 0; 1582 } 1583 1584 static void spapr_machine_reset(MachineState *machine) 1585 { 1586 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1587 PowerPCCPU *first_ppc_cpu; 1588 hwaddr fdt_addr; 1589 void *fdt; 1590 int rc; 1591 1592 kvmppc_svm_off(&error_fatal); 1593 spapr_caps_apply(spapr); 1594 1595 first_ppc_cpu = POWERPC_CPU(first_cpu); 1596 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1597 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1598 spapr->max_compat_pvr)) { 1599 /* 1600 * If using KVM with radix mode available, VCPUs can be started 1601 * without a HPT because KVM will start them in radix mode. 1602 * Set the GR bit in PATE so that we know there is no HPT. 1603 */ 1604 spapr->patb_entry = PATE1_GR; 1605 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1606 } else { 1607 spapr_setup_hpt(spapr); 1608 } 1609 1610 qemu_devices_reset(); 1611 1612 spapr_ovec_cleanup(spapr->ov5_cas); 1613 spapr->ov5_cas = spapr_ovec_new(); 1614 1615 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1616 1617 /* 1618 * This is fixing some of the default configuration of the XIVE 1619 * devices. To be called after the reset of the machine devices. 1620 */ 1621 spapr_irq_reset(spapr, &error_fatal); 1622 1623 /* 1624 * There is no CAS under qtest. Simulate one to please the code that 1625 * depends on spapr->ov5_cas. This is especially needed to test device 1626 * unplug, so we do that before resetting the DRCs. 1627 */ 1628 if (qtest_enabled()) { 1629 spapr_ovec_cleanup(spapr->ov5_cas); 1630 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1631 } 1632 1633 /* DRC reset may cause a device to be unplugged. This will cause troubles 1634 * if this device is used by another device (eg, a running vhost backend 1635 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1636 * situations, we reset DRCs after all devices have been reset. 1637 */ 1638 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1639 1640 spapr_clear_pending_events(spapr); 1641 1642 /* 1643 * We place the device tree and RTAS just below either the top of the RMA, 1644 * or just below 2GB, whichever is lower, so that it can be 1645 * processed with 32-bit real mode code if necessary 1646 */ 1647 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1648 1649 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1650 1651 rc = fdt_pack(fdt); 1652 1653 /* Should only fail if we've built a corrupted tree */ 1654 assert(rc == 0); 1655 1656 /* Load the fdt */ 1657 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1658 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1659 g_free(spapr->fdt_blob); 1660 spapr->fdt_size = fdt_totalsize(fdt); 1661 spapr->fdt_initial_size = spapr->fdt_size; 1662 spapr->fdt_blob = fdt; 1663 1664 /* Set up the entry state */ 1665 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); 1666 first_ppc_cpu->env.gpr[5] = 0; 1667 1668 spapr->fwnmi_system_reset_addr = -1; 1669 spapr->fwnmi_machine_check_addr = -1; 1670 spapr->fwnmi_machine_check_interlock = -1; 1671 1672 /* Signal all vCPUs waiting on this condition */ 1673 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1674 1675 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1676 } 1677 1678 static void spapr_create_nvram(SpaprMachineState *spapr) 1679 { 1680 DeviceState *dev = qdev_new("spapr-nvram"); 1681 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1682 1683 if (dinfo) { 1684 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1685 &error_fatal); 1686 } 1687 1688 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1689 1690 spapr->nvram = (struct SpaprNvram *)dev; 1691 } 1692 1693 static void spapr_rtc_create(SpaprMachineState *spapr) 1694 { 1695 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1696 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1697 &error_fatal, NULL); 1698 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1699 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1700 "date"); 1701 } 1702 1703 /* Returns whether we want to use VGA or not */ 1704 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1705 { 1706 switch (vga_interface_type) { 1707 case VGA_NONE: 1708 return false; 1709 case VGA_DEVICE: 1710 return true; 1711 case VGA_STD: 1712 case VGA_VIRTIO: 1713 case VGA_CIRRUS: 1714 return pci_vga_init(pci_bus) != NULL; 1715 default: 1716 error_setg(errp, 1717 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1718 return false; 1719 } 1720 } 1721 1722 static int spapr_pre_load(void *opaque) 1723 { 1724 int rc; 1725 1726 rc = spapr_caps_pre_load(opaque); 1727 if (rc) { 1728 return rc; 1729 } 1730 1731 return 0; 1732 } 1733 1734 static int spapr_post_load(void *opaque, int version_id) 1735 { 1736 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1737 int err = 0; 1738 1739 err = spapr_caps_post_migration(spapr); 1740 if (err) { 1741 return err; 1742 } 1743 1744 /* 1745 * In earlier versions, there was no separate qdev for the PAPR 1746 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1747 * So when migrating from those versions, poke the incoming offset 1748 * value into the RTC device 1749 */ 1750 if (version_id < 3) { 1751 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1752 if (err) { 1753 return err; 1754 } 1755 } 1756 1757 if (kvm_enabled() && spapr->patb_entry) { 1758 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1759 bool radix = !!(spapr->patb_entry & PATE1_GR); 1760 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1761 1762 /* 1763 * Update LPCR:HR and UPRT as they may not be set properly in 1764 * the stream 1765 */ 1766 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1767 LPCR_HR | LPCR_UPRT); 1768 1769 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1770 if (err) { 1771 error_report("Process table config unsupported by the host"); 1772 return -EINVAL; 1773 } 1774 } 1775 1776 err = spapr_irq_post_load(spapr, version_id); 1777 if (err) { 1778 return err; 1779 } 1780 1781 return err; 1782 } 1783 1784 static int spapr_pre_save(void *opaque) 1785 { 1786 int rc; 1787 1788 rc = spapr_caps_pre_save(opaque); 1789 if (rc) { 1790 return rc; 1791 } 1792 1793 return 0; 1794 } 1795 1796 static bool version_before_3(void *opaque, int version_id) 1797 { 1798 return version_id < 3; 1799 } 1800 1801 static bool spapr_pending_events_needed(void *opaque) 1802 { 1803 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1804 return !QTAILQ_EMPTY(&spapr->pending_events); 1805 } 1806 1807 static const VMStateDescription vmstate_spapr_event_entry = { 1808 .name = "spapr_event_log_entry", 1809 .version_id = 1, 1810 .minimum_version_id = 1, 1811 .fields = (VMStateField[]) { 1812 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1813 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1814 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1815 NULL, extended_length), 1816 VMSTATE_END_OF_LIST() 1817 }, 1818 }; 1819 1820 static const VMStateDescription vmstate_spapr_pending_events = { 1821 .name = "spapr_pending_events", 1822 .version_id = 1, 1823 .minimum_version_id = 1, 1824 .needed = spapr_pending_events_needed, 1825 .fields = (VMStateField[]) { 1826 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1827 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1828 VMSTATE_END_OF_LIST() 1829 }, 1830 }; 1831 1832 static bool spapr_ov5_cas_needed(void *opaque) 1833 { 1834 SpaprMachineState *spapr = opaque; 1835 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1836 bool cas_needed; 1837 1838 /* Prior to the introduction of SpaprOptionVector, we had two option 1839 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1840 * Both of these options encode machine topology into the device-tree 1841 * in such a way that the now-booted OS should still be able to interact 1842 * appropriately with QEMU regardless of what options were actually 1843 * negotiatied on the source side. 1844 * 1845 * As such, we can avoid migrating the CAS-negotiated options if these 1846 * are the only options available on the current machine/platform. 1847 * Since these are the only options available for pseries-2.7 and 1848 * earlier, this allows us to maintain old->new/new->old migration 1849 * compatibility. 1850 * 1851 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1852 * via default pseries-2.8 machines and explicit command-line parameters. 1853 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1854 * of the actual CAS-negotiated values to continue working properly. For 1855 * example, availability of memory unplug depends on knowing whether 1856 * OV5_HP_EVT was negotiated via CAS. 1857 * 1858 * Thus, for any cases where the set of available CAS-negotiatable 1859 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1860 * include the CAS-negotiated options in the migration stream, unless 1861 * if they affect boot time behaviour only. 1862 */ 1863 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1864 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1865 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1866 1867 /* We need extra information if we have any bits outside the mask 1868 * defined above */ 1869 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1870 1871 spapr_ovec_cleanup(ov5_mask); 1872 1873 return cas_needed; 1874 } 1875 1876 static const VMStateDescription vmstate_spapr_ov5_cas = { 1877 .name = "spapr_option_vector_ov5_cas", 1878 .version_id = 1, 1879 .minimum_version_id = 1, 1880 .needed = spapr_ov5_cas_needed, 1881 .fields = (VMStateField[]) { 1882 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1883 vmstate_spapr_ovec, SpaprOptionVector), 1884 VMSTATE_END_OF_LIST() 1885 }, 1886 }; 1887 1888 static bool spapr_patb_entry_needed(void *opaque) 1889 { 1890 SpaprMachineState *spapr = opaque; 1891 1892 return !!spapr->patb_entry; 1893 } 1894 1895 static const VMStateDescription vmstate_spapr_patb_entry = { 1896 .name = "spapr_patb_entry", 1897 .version_id = 1, 1898 .minimum_version_id = 1, 1899 .needed = spapr_patb_entry_needed, 1900 .fields = (VMStateField[]) { 1901 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1902 VMSTATE_END_OF_LIST() 1903 }, 1904 }; 1905 1906 static bool spapr_irq_map_needed(void *opaque) 1907 { 1908 SpaprMachineState *spapr = opaque; 1909 1910 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1911 } 1912 1913 static const VMStateDescription vmstate_spapr_irq_map = { 1914 .name = "spapr_irq_map", 1915 .version_id = 1, 1916 .minimum_version_id = 1, 1917 .needed = spapr_irq_map_needed, 1918 .fields = (VMStateField[]) { 1919 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1920 VMSTATE_END_OF_LIST() 1921 }, 1922 }; 1923 1924 static bool spapr_dtb_needed(void *opaque) 1925 { 1926 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1927 1928 return smc->update_dt_enabled; 1929 } 1930 1931 static int spapr_dtb_pre_load(void *opaque) 1932 { 1933 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1934 1935 g_free(spapr->fdt_blob); 1936 spapr->fdt_blob = NULL; 1937 spapr->fdt_size = 0; 1938 1939 return 0; 1940 } 1941 1942 static const VMStateDescription vmstate_spapr_dtb = { 1943 .name = "spapr_dtb", 1944 .version_id = 1, 1945 .minimum_version_id = 1, 1946 .needed = spapr_dtb_needed, 1947 .pre_load = spapr_dtb_pre_load, 1948 .fields = (VMStateField[]) { 1949 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1950 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1951 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1952 fdt_size), 1953 VMSTATE_END_OF_LIST() 1954 }, 1955 }; 1956 1957 static bool spapr_fwnmi_needed(void *opaque) 1958 { 1959 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1960 1961 return spapr->fwnmi_machine_check_addr != -1; 1962 } 1963 1964 static int spapr_fwnmi_pre_save(void *opaque) 1965 { 1966 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1967 1968 /* 1969 * Check if machine check handling is in progress and print a 1970 * warning message. 1971 */ 1972 if (spapr->fwnmi_machine_check_interlock != -1) { 1973 warn_report("A machine check is being handled during migration. The" 1974 "handler may run and log hardware error on the destination"); 1975 } 1976 1977 return 0; 1978 } 1979 1980 static const VMStateDescription vmstate_spapr_fwnmi = { 1981 .name = "spapr_fwnmi", 1982 .version_id = 1, 1983 .minimum_version_id = 1, 1984 .needed = spapr_fwnmi_needed, 1985 .pre_save = spapr_fwnmi_pre_save, 1986 .fields = (VMStateField[]) { 1987 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 1988 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 1989 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 1990 VMSTATE_END_OF_LIST() 1991 }, 1992 }; 1993 1994 static const VMStateDescription vmstate_spapr = { 1995 .name = "spapr", 1996 .version_id = 3, 1997 .minimum_version_id = 1, 1998 .pre_load = spapr_pre_load, 1999 .post_load = spapr_post_load, 2000 .pre_save = spapr_pre_save, 2001 .fields = (VMStateField[]) { 2002 /* used to be @next_irq */ 2003 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2004 2005 /* RTC offset */ 2006 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2007 2008 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2009 VMSTATE_END_OF_LIST() 2010 }, 2011 .subsections = (const VMStateDescription*[]) { 2012 &vmstate_spapr_ov5_cas, 2013 &vmstate_spapr_patb_entry, 2014 &vmstate_spapr_pending_events, 2015 &vmstate_spapr_cap_htm, 2016 &vmstate_spapr_cap_vsx, 2017 &vmstate_spapr_cap_dfp, 2018 &vmstate_spapr_cap_cfpc, 2019 &vmstate_spapr_cap_sbbc, 2020 &vmstate_spapr_cap_ibs, 2021 &vmstate_spapr_cap_hpt_maxpagesize, 2022 &vmstate_spapr_irq_map, 2023 &vmstate_spapr_cap_nested_kvm_hv, 2024 &vmstate_spapr_dtb, 2025 &vmstate_spapr_cap_large_decr, 2026 &vmstate_spapr_cap_ccf_assist, 2027 &vmstate_spapr_cap_fwnmi, 2028 &vmstate_spapr_fwnmi, 2029 NULL 2030 } 2031 }; 2032 2033 static int htab_save_setup(QEMUFile *f, void *opaque) 2034 { 2035 SpaprMachineState *spapr = opaque; 2036 2037 /* "Iteration" header */ 2038 if (!spapr->htab_shift) { 2039 qemu_put_be32(f, -1); 2040 } else { 2041 qemu_put_be32(f, spapr->htab_shift); 2042 } 2043 2044 if (spapr->htab) { 2045 spapr->htab_save_index = 0; 2046 spapr->htab_first_pass = true; 2047 } else { 2048 if (spapr->htab_shift) { 2049 assert(kvm_enabled()); 2050 } 2051 } 2052 2053 2054 return 0; 2055 } 2056 2057 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2058 int chunkstart, int n_valid, int n_invalid) 2059 { 2060 qemu_put_be32(f, chunkstart); 2061 qemu_put_be16(f, n_valid); 2062 qemu_put_be16(f, n_invalid); 2063 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2064 HASH_PTE_SIZE_64 * n_valid); 2065 } 2066 2067 static void htab_save_end_marker(QEMUFile *f) 2068 { 2069 qemu_put_be32(f, 0); 2070 qemu_put_be16(f, 0); 2071 qemu_put_be16(f, 0); 2072 } 2073 2074 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2075 int64_t max_ns) 2076 { 2077 bool has_timeout = max_ns != -1; 2078 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2079 int index = spapr->htab_save_index; 2080 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2081 2082 assert(spapr->htab_first_pass); 2083 2084 do { 2085 int chunkstart; 2086 2087 /* Consume invalid HPTEs */ 2088 while ((index < htabslots) 2089 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2090 CLEAN_HPTE(HPTE(spapr->htab, index)); 2091 index++; 2092 } 2093 2094 /* Consume valid HPTEs */ 2095 chunkstart = index; 2096 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2097 && HPTE_VALID(HPTE(spapr->htab, index))) { 2098 CLEAN_HPTE(HPTE(spapr->htab, index)); 2099 index++; 2100 } 2101 2102 if (index > chunkstart) { 2103 int n_valid = index - chunkstart; 2104 2105 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2106 2107 if (has_timeout && 2108 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2109 break; 2110 } 2111 } 2112 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2113 2114 if (index >= htabslots) { 2115 assert(index == htabslots); 2116 index = 0; 2117 spapr->htab_first_pass = false; 2118 } 2119 spapr->htab_save_index = index; 2120 } 2121 2122 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2123 int64_t max_ns) 2124 { 2125 bool final = max_ns < 0; 2126 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2127 int examined = 0, sent = 0; 2128 int index = spapr->htab_save_index; 2129 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2130 2131 assert(!spapr->htab_first_pass); 2132 2133 do { 2134 int chunkstart, invalidstart; 2135 2136 /* Consume non-dirty HPTEs */ 2137 while ((index < htabslots) 2138 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2139 index++; 2140 examined++; 2141 } 2142 2143 chunkstart = index; 2144 /* Consume valid dirty HPTEs */ 2145 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2146 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2147 && HPTE_VALID(HPTE(spapr->htab, index))) { 2148 CLEAN_HPTE(HPTE(spapr->htab, index)); 2149 index++; 2150 examined++; 2151 } 2152 2153 invalidstart = index; 2154 /* Consume invalid dirty HPTEs */ 2155 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2156 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2157 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2158 CLEAN_HPTE(HPTE(spapr->htab, index)); 2159 index++; 2160 examined++; 2161 } 2162 2163 if (index > chunkstart) { 2164 int n_valid = invalidstart - chunkstart; 2165 int n_invalid = index - invalidstart; 2166 2167 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2168 sent += index - chunkstart; 2169 2170 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2171 break; 2172 } 2173 } 2174 2175 if (examined >= htabslots) { 2176 break; 2177 } 2178 2179 if (index >= htabslots) { 2180 assert(index == htabslots); 2181 index = 0; 2182 } 2183 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2184 2185 if (index >= htabslots) { 2186 assert(index == htabslots); 2187 index = 0; 2188 } 2189 2190 spapr->htab_save_index = index; 2191 2192 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2193 } 2194 2195 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2196 #define MAX_KVM_BUF_SIZE 2048 2197 2198 static int htab_save_iterate(QEMUFile *f, void *opaque) 2199 { 2200 SpaprMachineState *spapr = opaque; 2201 int fd; 2202 int rc = 0; 2203 2204 /* Iteration header */ 2205 if (!spapr->htab_shift) { 2206 qemu_put_be32(f, -1); 2207 return 1; 2208 } else { 2209 qemu_put_be32(f, 0); 2210 } 2211 2212 if (!spapr->htab) { 2213 assert(kvm_enabled()); 2214 2215 fd = get_htab_fd(spapr); 2216 if (fd < 0) { 2217 return fd; 2218 } 2219 2220 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2221 if (rc < 0) { 2222 return rc; 2223 } 2224 } else if (spapr->htab_first_pass) { 2225 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2226 } else { 2227 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2228 } 2229 2230 htab_save_end_marker(f); 2231 2232 return rc; 2233 } 2234 2235 static int htab_save_complete(QEMUFile *f, void *opaque) 2236 { 2237 SpaprMachineState *spapr = opaque; 2238 int fd; 2239 2240 /* Iteration header */ 2241 if (!spapr->htab_shift) { 2242 qemu_put_be32(f, -1); 2243 return 0; 2244 } else { 2245 qemu_put_be32(f, 0); 2246 } 2247 2248 if (!spapr->htab) { 2249 int rc; 2250 2251 assert(kvm_enabled()); 2252 2253 fd = get_htab_fd(spapr); 2254 if (fd < 0) { 2255 return fd; 2256 } 2257 2258 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2259 if (rc < 0) { 2260 return rc; 2261 } 2262 } else { 2263 if (spapr->htab_first_pass) { 2264 htab_save_first_pass(f, spapr, -1); 2265 } 2266 htab_save_later_pass(f, spapr, -1); 2267 } 2268 2269 /* End marker */ 2270 htab_save_end_marker(f); 2271 2272 return 0; 2273 } 2274 2275 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2276 { 2277 SpaprMachineState *spapr = opaque; 2278 uint32_t section_hdr; 2279 int fd = -1; 2280 Error *local_err = NULL; 2281 2282 if (version_id < 1 || version_id > 1) { 2283 error_report("htab_load() bad version"); 2284 return -EINVAL; 2285 } 2286 2287 section_hdr = qemu_get_be32(f); 2288 2289 if (section_hdr == -1) { 2290 spapr_free_hpt(spapr); 2291 return 0; 2292 } 2293 2294 if (section_hdr) { 2295 int ret; 2296 2297 /* First section gives the htab size */ 2298 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2299 if (ret < 0) { 2300 error_report_err(local_err); 2301 return ret; 2302 } 2303 return 0; 2304 } 2305 2306 if (!spapr->htab) { 2307 assert(kvm_enabled()); 2308 2309 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2310 if (fd < 0) { 2311 error_report_err(local_err); 2312 return fd; 2313 } 2314 } 2315 2316 while (true) { 2317 uint32_t index; 2318 uint16_t n_valid, n_invalid; 2319 2320 index = qemu_get_be32(f); 2321 n_valid = qemu_get_be16(f); 2322 n_invalid = qemu_get_be16(f); 2323 2324 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2325 /* End of Stream */ 2326 break; 2327 } 2328 2329 if ((index + n_valid + n_invalid) > 2330 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2331 /* Bad index in stream */ 2332 error_report( 2333 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2334 index, n_valid, n_invalid, spapr->htab_shift); 2335 return -EINVAL; 2336 } 2337 2338 if (spapr->htab) { 2339 if (n_valid) { 2340 qemu_get_buffer(f, HPTE(spapr->htab, index), 2341 HASH_PTE_SIZE_64 * n_valid); 2342 } 2343 if (n_invalid) { 2344 memset(HPTE(spapr->htab, index + n_valid), 0, 2345 HASH_PTE_SIZE_64 * n_invalid); 2346 } 2347 } else { 2348 int rc; 2349 2350 assert(fd >= 0); 2351 2352 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2353 &local_err); 2354 if (rc < 0) { 2355 error_report_err(local_err); 2356 return rc; 2357 } 2358 } 2359 } 2360 2361 if (!spapr->htab) { 2362 assert(fd >= 0); 2363 close(fd); 2364 } 2365 2366 return 0; 2367 } 2368 2369 static void htab_save_cleanup(void *opaque) 2370 { 2371 SpaprMachineState *spapr = opaque; 2372 2373 close_htab_fd(spapr); 2374 } 2375 2376 static SaveVMHandlers savevm_htab_handlers = { 2377 .save_setup = htab_save_setup, 2378 .save_live_iterate = htab_save_iterate, 2379 .save_live_complete_precopy = htab_save_complete, 2380 .save_cleanup = htab_save_cleanup, 2381 .load_state = htab_load, 2382 }; 2383 2384 static void spapr_boot_set(void *opaque, const char *boot_device, 2385 Error **errp) 2386 { 2387 MachineState *machine = MACHINE(opaque); 2388 machine->boot_order = g_strdup(boot_device); 2389 } 2390 2391 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2392 { 2393 MachineState *machine = MACHINE(spapr); 2394 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2395 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2396 int i; 2397 2398 for (i = 0; i < nr_lmbs; i++) { 2399 uint64_t addr; 2400 2401 addr = i * lmb_size + machine->device_memory->base; 2402 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2403 addr / lmb_size); 2404 } 2405 } 2406 2407 /* 2408 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2409 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2410 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2411 */ 2412 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2413 { 2414 int i; 2415 2416 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2417 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2418 " is not aligned to %" PRIu64 " MiB", 2419 machine->ram_size, 2420 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2421 return; 2422 } 2423 2424 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2425 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2426 " is not aligned to %" PRIu64 " MiB", 2427 machine->ram_size, 2428 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2429 return; 2430 } 2431 2432 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2433 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2434 error_setg(errp, 2435 "Node %d memory size 0x%" PRIx64 2436 " is not aligned to %" PRIu64 " MiB", 2437 i, machine->numa_state->nodes[i].node_mem, 2438 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2439 return; 2440 } 2441 } 2442 } 2443 2444 /* find cpu slot in machine->possible_cpus by core_id */ 2445 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2446 { 2447 int index = id / ms->smp.threads; 2448 2449 if (index >= ms->possible_cpus->len) { 2450 return NULL; 2451 } 2452 if (idx) { 2453 *idx = index; 2454 } 2455 return &ms->possible_cpus->cpus[index]; 2456 } 2457 2458 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2459 { 2460 MachineState *ms = MACHINE(spapr); 2461 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2462 Error *local_err = NULL; 2463 bool vsmt_user = !!spapr->vsmt; 2464 int kvm_smt = kvmppc_smt_threads(); 2465 int ret; 2466 unsigned int smp_threads = ms->smp.threads; 2467 2468 if (!kvm_enabled() && (smp_threads > 1)) { 2469 error_setg(errp, "TCG cannot support more than 1 thread/core " 2470 "on a pseries machine"); 2471 return; 2472 } 2473 if (!is_power_of_2(smp_threads)) { 2474 error_setg(errp, "Cannot support %d threads/core on a pseries " 2475 "machine because it must be a power of 2", smp_threads); 2476 return; 2477 } 2478 2479 /* Detemine the VSMT mode to use: */ 2480 if (vsmt_user) { 2481 if (spapr->vsmt < smp_threads) { 2482 error_setg(errp, "Cannot support VSMT mode %d" 2483 " because it must be >= threads/core (%d)", 2484 spapr->vsmt, smp_threads); 2485 return; 2486 } 2487 /* In this case, spapr->vsmt has been set by the command line */ 2488 } else if (!smc->smp_threads_vsmt) { 2489 /* 2490 * Default VSMT value is tricky, because we need it to be as 2491 * consistent as possible (for migration), but this requires 2492 * changing it for at least some existing cases. We pick 8 as 2493 * the value that we'd get with KVM on POWER8, the 2494 * overwhelmingly common case in production systems. 2495 */ 2496 spapr->vsmt = MAX(8, smp_threads); 2497 } else { 2498 spapr->vsmt = smp_threads; 2499 } 2500 2501 /* KVM: If necessary, set the SMT mode: */ 2502 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2503 ret = kvmppc_set_smt_threads(spapr->vsmt); 2504 if (ret) { 2505 /* Looks like KVM isn't able to change VSMT mode */ 2506 error_setg(&local_err, 2507 "Failed to set KVM's VSMT mode to %d (errno %d)", 2508 spapr->vsmt, ret); 2509 /* We can live with that if the default one is big enough 2510 * for the number of threads, and a submultiple of the one 2511 * we want. In this case we'll waste some vcpu ids, but 2512 * behaviour will be correct */ 2513 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2514 warn_report_err(local_err); 2515 } else { 2516 if (!vsmt_user) { 2517 error_append_hint(&local_err, 2518 "On PPC, a VM with %d threads/core" 2519 " on a host with %d threads/core" 2520 " requires the use of VSMT mode %d.\n", 2521 smp_threads, kvm_smt, spapr->vsmt); 2522 } 2523 kvmppc_error_append_smt_possible_hint(&local_err); 2524 error_propagate(errp, local_err); 2525 } 2526 } 2527 } 2528 /* else TCG: nothing to do currently */ 2529 } 2530 2531 static void spapr_init_cpus(SpaprMachineState *spapr) 2532 { 2533 MachineState *machine = MACHINE(spapr); 2534 MachineClass *mc = MACHINE_GET_CLASS(machine); 2535 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2536 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2537 const CPUArchIdList *possible_cpus; 2538 unsigned int smp_cpus = machine->smp.cpus; 2539 unsigned int smp_threads = machine->smp.threads; 2540 unsigned int max_cpus = machine->smp.max_cpus; 2541 int boot_cores_nr = smp_cpus / smp_threads; 2542 int i; 2543 2544 possible_cpus = mc->possible_cpu_arch_ids(machine); 2545 if (mc->has_hotpluggable_cpus) { 2546 if (smp_cpus % smp_threads) { 2547 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2548 smp_cpus, smp_threads); 2549 exit(1); 2550 } 2551 if (max_cpus % smp_threads) { 2552 error_report("max_cpus (%u) must be multiple of threads (%u)", 2553 max_cpus, smp_threads); 2554 exit(1); 2555 } 2556 } else { 2557 if (max_cpus != smp_cpus) { 2558 error_report("This machine version does not support CPU hotplug"); 2559 exit(1); 2560 } 2561 boot_cores_nr = possible_cpus->len; 2562 } 2563 2564 if (smc->pre_2_10_has_unused_icps) { 2565 int i; 2566 2567 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2568 /* Dummy entries get deregistered when real ICPState objects 2569 * are registered during CPU core hotplug. 2570 */ 2571 pre_2_10_vmstate_register_dummy_icp(i); 2572 } 2573 } 2574 2575 for (i = 0; i < possible_cpus->len; i++) { 2576 int core_id = i * smp_threads; 2577 2578 if (mc->has_hotpluggable_cpus) { 2579 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2580 spapr_vcpu_id(spapr, core_id)); 2581 } 2582 2583 if (i < boot_cores_nr) { 2584 Object *core = object_new(type); 2585 int nr_threads = smp_threads; 2586 2587 /* Handle the partially filled core for older machine types */ 2588 if ((i + 1) * smp_threads >= smp_cpus) { 2589 nr_threads = smp_cpus - i * smp_threads; 2590 } 2591 2592 object_property_set_int(core, "nr-threads", nr_threads, 2593 &error_fatal); 2594 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2595 &error_fatal); 2596 qdev_realize(DEVICE(core), NULL, &error_fatal); 2597 2598 object_unref(core); 2599 } 2600 } 2601 } 2602 2603 static PCIHostState *spapr_create_default_phb(void) 2604 { 2605 DeviceState *dev; 2606 2607 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2608 qdev_prop_set_uint32(dev, "index", 0); 2609 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2610 2611 return PCI_HOST_BRIDGE(dev); 2612 } 2613 2614 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2615 { 2616 MachineState *machine = MACHINE(spapr); 2617 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2618 hwaddr rma_size = machine->ram_size; 2619 hwaddr node0_size = spapr_node0_size(machine); 2620 2621 /* RMA has to fit in the first NUMA node */ 2622 rma_size = MIN(rma_size, node0_size); 2623 2624 /* 2625 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2626 * never exceed that 2627 */ 2628 rma_size = MIN(rma_size, 1 * TiB); 2629 2630 /* 2631 * Clamp the RMA size based on machine type. This is for 2632 * migration compatibility with older qemu versions, which limited 2633 * the RMA size for complicated and mostly bad reasons. 2634 */ 2635 if (smc->rma_limit) { 2636 rma_size = MIN(rma_size, smc->rma_limit); 2637 } 2638 2639 if (rma_size < MIN_RMA_SLOF) { 2640 error_setg(errp, 2641 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2642 "ldMiB guest RMA (Real Mode Area memory)", 2643 MIN_RMA_SLOF / MiB); 2644 return 0; 2645 } 2646 2647 return rma_size; 2648 } 2649 2650 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2651 { 2652 MachineState *machine = MACHINE(spapr); 2653 int i; 2654 2655 for (i = 0; i < machine->ram_slots; i++) { 2656 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2657 } 2658 } 2659 2660 /* pSeries LPAR / sPAPR hardware init */ 2661 static void spapr_machine_init(MachineState *machine) 2662 { 2663 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2664 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2665 MachineClass *mc = MACHINE_GET_CLASS(machine); 2666 const char *kernel_filename = machine->kernel_filename; 2667 const char *initrd_filename = machine->initrd_filename; 2668 PCIHostState *phb; 2669 int i; 2670 MemoryRegion *sysmem = get_system_memory(); 2671 long load_limit, fw_size; 2672 char *filename; 2673 Error *resize_hpt_err = NULL; 2674 2675 msi_nonbroken = true; 2676 2677 QLIST_INIT(&spapr->phbs); 2678 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2679 2680 /* Determine capabilities to run with */ 2681 spapr_caps_init(spapr); 2682 2683 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2684 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2685 /* 2686 * If the user explicitly requested a mode we should either 2687 * supply it, or fail completely (which we do below). But if 2688 * it's not set explicitly, we reset our mode to something 2689 * that works 2690 */ 2691 if (resize_hpt_err) { 2692 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2693 error_free(resize_hpt_err); 2694 resize_hpt_err = NULL; 2695 } else { 2696 spapr->resize_hpt = smc->resize_hpt_default; 2697 } 2698 } 2699 2700 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2701 2702 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2703 /* 2704 * User requested HPT resize, but this host can't supply it. Bail out 2705 */ 2706 error_report_err(resize_hpt_err); 2707 exit(1); 2708 } 2709 error_free(resize_hpt_err); 2710 2711 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2712 2713 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2714 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2715 2716 /* 2717 * VSMT must be set in order to be able to compute VCPU ids, ie to 2718 * call spapr_max_server_number() or spapr_vcpu_id(). 2719 */ 2720 spapr_set_vsmt_mode(spapr, &error_fatal); 2721 2722 /* Set up Interrupt Controller before we create the VCPUs */ 2723 spapr_irq_init(spapr, &error_fatal); 2724 2725 /* Set up containers for ibm,client-architecture-support negotiated options 2726 */ 2727 spapr->ov5 = spapr_ovec_new(); 2728 spapr->ov5_cas = spapr_ovec_new(); 2729 2730 if (smc->dr_lmb_enabled) { 2731 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2732 spapr_validate_node_memory(machine, &error_fatal); 2733 } 2734 2735 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2736 2737 /* advertise support for dedicated HP event source to guests */ 2738 if (spapr->use_hotplug_event_source) { 2739 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2740 } 2741 2742 /* advertise support for HPT resizing */ 2743 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2744 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2745 } 2746 2747 /* advertise support for ibm,dyamic-memory-v2 */ 2748 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2749 2750 /* advertise XIVE on POWER9 machines */ 2751 if (spapr->irq->xive) { 2752 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2753 } 2754 2755 /* init CPUs */ 2756 spapr_init_cpus(spapr); 2757 2758 /* 2759 * check we don't have a memory-less/cpu-less NUMA node 2760 * Firmware relies on the existing memory/cpu topology to provide the 2761 * NUMA topology to the kernel. 2762 * And the linux kernel needs to know the NUMA topology at start 2763 * to be able to hotplug CPUs later. 2764 */ 2765 if (machine->numa_state->num_nodes) { 2766 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2767 /* check for memory-less node */ 2768 if (machine->numa_state->nodes[i].node_mem == 0) { 2769 CPUState *cs; 2770 int found = 0; 2771 /* check for cpu-less node */ 2772 CPU_FOREACH(cs) { 2773 PowerPCCPU *cpu = POWERPC_CPU(cs); 2774 if (cpu->node_id == i) { 2775 found = 1; 2776 break; 2777 } 2778 } 2779 /* memory-less and cpu-less node */ 2780 if (!found) { 2781 error_report( 2782 "Memory-less/cpu-less nodes are not supported (node %d)", 2783 i); 2784 exit(1); 2785 } 2786 } 2787 } 2788 2789 } 2790 2791 /* 2792 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2793 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2794 * called from vPHB reset handler so we initialize the counter here. 2795 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2796 * must be equally distant from any other node. 2797 * The final value of spapr->gpu_numa_id is going to be written to 2798 * max-associativity-domains in spapr_build_fdt(). 2799 */ 2800 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2801 2802 /* Init numa_assoc_array */ 2803 spapr_numa_associativity_init(spapr, machine); 2804 2805 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2806 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2807 spapr->max_compat_pvr)) { 2808 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2809 /* KVM and TCG always allow GTSE with radix... */ 2810 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2811 } 2812 /* ... but not with hash (currently). */ 2813 2814 if (kvm_enabled()) { 2815 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2816 kvmppc_enable_logical_ci_hcalls(); 2817 kvmppc_enable_set_mode_hcall(); 2818 2819 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2820 kvmppc_enable_clear_ref_mod_hcalls(); 2821 2822 /* Enable H_PAGE_INIT */ 2823 kvmppc_enable_h_page_init(); 2824 } 2825 2826 /* map RAM */ 2827 memory_region_add_subregion(sysmem, 0, machine->ram); 2828 2829 /* always allocate the device memory information */ 2830 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2831 2832 /* initialize hotplug memory address space */ 2833 if (machine->ram_size < machine->maxram_size) { 2834 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2835 /* 2836 * Limit the number of hotpluggable memory slots to half the number 2837 * slots that KVM supports, leaving the other half for PCI and other 2838 * devices. However ensure that number of slots doesn't drop below 32. 2839 */ 2840 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2841 SPAPR_MAX_RAM_SLOTS; 2842 2843 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2844 max_memslots = SPAPR_MAX_RAM_SLOTS; 2845 } 2846 if (machine->ram_slots > max_memslots) { 2847 error_report("Specified number of memory slots %" 2848 PRIu64" exceeds max supported %d", 2849 machine->ram_slots, max_memslots); 2850 exit(1); 2851 } 2852 2853 machine->device_memory->base = ROUND_UP(machine->ram_size, 2854 SPAPR_DEVICE_MEM_ALIGN); 2855 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2856 "device-memory", device_mem_size); 2857 memory_region_add_subregion(sysmem, machine->device_memory->base, 2858 &machine->device_memory->mr); 2859 } 2860 2861 if (smc->dr_lmb_enabled) { 2862 spapr_create_lmb_dr_connectors(spapr); 2863 } 2864 2865 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2866 /* Create the error string for live migration blocker */ 2867 error_setg(&spapr->fwnmi_migration_blocker, 2868 "A machine check is being handled during migration. The handler" 2869 "may run and log hardware error on the destination"); 2870 } 2871 2872 if (mc->nvdimm_supported) { 2873 spapr_create_nvdimm_dr_connectors(spapr); 2874 } 2875 2876 /* Set up RTAS event infrastructure */ 2877 spapr_events_init(spapr); 2878 2879 /* Set up the RTC RTAS interfaces */ 2880 spapr_rtc_create(spapr); 2881 2882 /* Set up VIO bus */ 2883 spapr->vio_bus = spapr_vio_bus_init(); 2884 2885 for (i = 0; i < serial_max_hds(); i++) { 2886 if (serial_hd(i)) { 2887 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2888 } 2889 } 2890 2891 /* We always have at least the nvram device on VIO */ 2892 spapr_create_nvram(spapr); 2893 2894 /* 2895 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2896 * connectors (described in root DT node's "ibm,drc-types" property) 2897 * are pre-initialized here. additional child connectors (such as 2898 * connectors for a PHBs PCI slots) are added as needed during their 2899 * parent's realization. 2900 */ 2901 if (smc->dr_phb_enabled) { 2902 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2903 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2904 } 2905 } 2906 2907 /* Set up PCI */ 2908 spapr_pci_rtas_init(); 2909 2910 phb = spapr_create_default_phb(); 2911 2912 for (i = 0; i < nb_nics; i++) { 2913 NICInfo *nd = &nd_table[i]; 2914 2915 if (!nd->model) { 2916 nd->model = g_strdup("spapr-vlan"); 2917 } 2918 2919 if (g_str_equal(nd->model, "spapr-vlan") || 2920 g_str_equal(nd->model, "ibmveth")) { 2921 spapr_vlan_create(spapr->vio_bus, nd); 2922 } else { 2923 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2924 } 2925 } 2926 2927 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2928 spapr_vscsi_create(spapr->vio_bus); 2929 } 2930 2931 /* Graphics */ 2932 if (spapr_vga_init(phb->bus, &error_fatal)) { 2933 spapr->has_graphics = true; 2934 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2935 } 2936 2937 if (machine->usb) { 2938 if (smc->use_ohci_by_default) { 2939 pci_create_simple(phb->bus, -1, "pci-ohci"); 2940 } else { 2941 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2942 } 2943 2944 if (spapr->has_graphics) { 2945 USBBus *usb_bus = usb_bus_find(-1); 2946 2947 usb_create_simple(usb_bus, "usb-kbd"); 2948 usb_create_simple(usb_bus, "usb-mouse"); 2949 } 2950 } 2951 2952 if (kernel_filename) { 2953 spapr->kernel_size = load_elf(kernel_filename, NULL, 2954 translate_kernel_address, spapr, 2955 NULL, NULL, NULL, NULL, 1, 2956 PPC_ELF_MACHINE, 0, 0); 2957 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2958 spapr->kernel_size = load_elf(kernel_filename, NULL, 2959 translate_kernel_address, spapr, 2960 NULL, NULL, NULL, NULL, 0, 2961 PPC_ELF_MACHINE, 0, 0); 2962 spapr->kernel_le = spapr->kernel_size > 0; 2963 } 2964 if (spapr->kernel_size < 0) { 2965 error_report("error loading %s: %s", kernel_filename, 2966 load_elf_strerror(spapr->kernel_size)); 2967 exit(1); 2968 } 2969 2970 /* load initrd */ 2971 if (initrd_filename) { 2972 /* Try to locate the initrd in the gap between the kernel 2973 * and the firmware. Add a bit of space just in case 2974 */ 2975 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2976 + 0x1ffff) & ~0xffff; 2977 spapr->initrd_size = load_image_targphys(initrd_filename, 2978 spapr->initrd_base, 2979 load_limit 2980 - spapr->initrd_base); 2981 if (spapr->initrd_size < 0) { 2982 error_report("could not load initial ram disk '%s'", 2983 initrd_filename); 2984 exit(1); 2985 } 2986 } 2987 } 2988 2989 if (bios_name == NULL) { 2990 bios_name = FW_FILE_NAME; 2991 } 2992 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2993 if (!filename) { 2994 error_report("Could not find LPAR firmware '%s'", bios_name); 2995 exit(1); 2996 } 2997 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2998 if (fw_size <= 0) { 2999 error_report("Could not load LPAR firmware '%s'", filename); 3000 exit(1); 3001 } 3002 g_free(filename); 3003 3004 /* FIXME: Should register things through the MachineState's qdev 3005 * interface, this is a legacy from the sPAPREnvironment structure 3006 * which predated MachineState but had a similar function */ 3007 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3008 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3009 &savevm_htab_handlers, spapr); 3010 3011 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 3012 3013 qemu_register_boot_set(spapr_boot_set, spapr); 3014 3015 /* 3016 * Nothing needs to be done to resume a suspended guest because 3017 * suspending does not change the machine state, so no need for 3018 * a ->wakeup method. 3019 */ 3020 qemu_register_wakeup_support(); 3021 3022 if (kvm_enabled()) { 3023 /* to stop and start vmclock */ 3024 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3025 &spapr->tb); 3026 3027 kvmppc_spapr_enable_inkernel_multitce(); 3028 } 3029 3030 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3031 } 3032 3033 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3034 { 3035 if (!vm_type) { 3036 return 0; 3037 } 3038 3039 if (!strcmp(vm_type, "HV")) { 3040 return 1; 3041 } 3042 3043 if (!strcmp(vm_type, "PR")) { 3044 return 2; 3045 } 3046 3047 error_report("Unknown kvm-type specified '%s'", vm_type); 3048 exit(1); 3049 } 3050 3051 /* 3052 * Implementation of an interface to adjust firmware path 3053 * for the bootindex property handling. 3054 */ 3055 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3056 DeviceState *dev) 3057 { 3058 #define CAST(type, obj, name) \ 3059 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3060 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3061 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3062 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3063 3064 if (d) { 3065 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3066 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3067 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3068 3069 if (spapr) { 3070 /* 3071 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3072 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3073 * 0x8000 | (target << 8) | (bus << 5) | lun 3074 * (see the "Logical unit addressing format" table in SAM5) 3075 */ 3076 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3077 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3078 (uint64_t)id << 48); 3079 } else if (virtio) { 3080 /* 3081 * We use SRP luns of the form 01000000 | (target << 8) | lun 3082 * in the top 32 bits of the 64-bit LUN 3083 * Note: the quote above is from SLOF and it is wrong, 3084 * the actual binding is: 3085 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3086 */ 3087 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3088 if (d->lun >= 256) { 3089 /* Use the LUN "flat space addressing method" */ 3090 id |= 0x4000; 3091 } 3092 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3093 (uint64_t)id << 32); 3094 } else if (usb) { 3095 /* 3096 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3097 * in the top 32 bits of the 64-bit LUN 3098 */ 3099 unsigned usb_port = atoi(usb->port->path); 3100 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3101 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3102 (uint64_t)id << 32); 3103 } 3104 } 3105 3106 /* 3107 * SLOF probes the USB devices, and if it recognizes that the device is a 3108 * storage device, it changes its name to "storage" instead of "usb-host", 3109 * and additionally adds a child node for the SCSI LUN, so the correct 3110 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3111 */ 3112 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3113 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3114 if (usb_host_dev_is_scsi_storage(usbdev)) { 3115 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3116 } 3117 } 3118 3119 if (phb) { 3120 /* Replace "pci" with "pci@800000020000000" */ 3121 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3122 } 3123 3124 if (vsc) { 3125 /* Same logic as virtio above */ 3126 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3127 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3128 } 3129 3130 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3131 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3132 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3133 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3134 } 3135 3136 return NULL; 3137 } 3138 3139 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3140 { 3141 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3142 3143 return g_strdup(spapr->kvm_type); 3144 } 3145 3146 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3147 { 3148 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3149 3150 g_free(spapr->kvm_type); 3151 spapr->kvm_type = g_strdup(value); 3152 } 3153 3154 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3155 { 3156 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3157 3158 return spapr->use_hotplug_event_source; 3159 } 3160 3161 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3162 Error **errp) 3163 { 3164 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3165 3166 spapr->use_hotplug_event_source = value; 3167 } 3168 3169 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3170 { 3171 return true; 3172 } 3173 3174 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3175 { 3176 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3177 3178 switch (spapr->resize_hpt) { 3179 case SPAPR_RESIZE_HPT_DEFAULT: 3180 return g_strdup("default"); 3181 case SPAPR_RESIZE_HPT_DISABLED: 3182 return g_strdup("disabled"); 3183 case SPAPR_RESIZE_HPT_ENABLED: 3184 return g_strdup("enabled"); 3185 case SPAPR_RESIZE_HPT_REQUIRED: 3186 return g_strdup("required"); 3187 } 3188 g_assert_not_reached(); 3189 } 3190 3191 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3192 { 3193 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3194 3195 if (strcmp(value, "default") == 0) { 3196 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3197 } else if (strcmp(value, "disabled") == 0) { 3198 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3199 } else if (strcmp(value, "enabled") == 0) { 3200 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3201 } else if (strcmp(value, "required") == 0) { 3202 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3203 } else { 3204 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3205 } 3206 } 3207 3208 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3209 { 3210 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3211 3212 if (spapr->irq == &spapr_irq_xics_legacy) { 3213 return g_strdup("legacy"); 3214 } else if (spapr->irq == &spapr_irq_xics) { 3215 return g_strdup("xics"); 3216 } else if (spapr->irq == &spapr_irq_xive) { 3217 return g_strdup("xive"); 3218 } else if (spapr->irq == &spapr_irq_dual) { 3219 return g_strdup("dual"); 3220 } 3221 g_assert_not_reached(); 3222 } 3223 3224 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3225 { 3226 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3227 3228 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3229 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3230 return; 3231 } 3232 3233 /* The legacy IRQ backend can not be set */ 3234 if (strcmp(value, "xics") == 0) { 3235 spapr->irq = &spapr_irq_xics; 3236 } else if (strcmp(value, "xive") == 0) { 3237 spapr->irq = &spapr_irq_xive; 3238 } else if (strcmp(value, "dual") == 0) { 3239 spapr->irq = &spapr_irq_dual; 3240 } else { 3241 error_setg(errp, "Bad value for \"ic-mode\" property"); 3242 } 3243 } 3244 3245 static char *spapr_get_host_model(Object *obj, Error **errp) 3246 { 3247 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3248 3249 return g_strdup(spapr->host_model); 3250 } 3251 3252 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3253 { 3254 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3255 3256 g_free(spapr->host_model); 3257 spapr->host_model = g_strdup(value); 3258 } 3259 3260 static char *spapr_get_host_serial(Object *obj, Error **errp) 3261 { 3262 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3263 3264 return g_strdup(spapr->host_serial); 3265 } 3266 3267 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3268 { 3269 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3270 3271 g_free(spapr->host_serial); 3272 spapr->host_serial = g_strdup(value); 3273 } 3274 3275 static void spapr_instance_init(Object *obj) 3276 { 3277 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3278 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3279 3280 spapr->htab_fd = -1; 3281 spapr->use_hotplug_event_source = true; 3282 object_property_add_str(obj, "kvm-type", 3283 spapr_get_kvm_type, spapr_set_kvm_type); 3284 object_property_set_description(obj, "kvm-type", 3285 "Specifies the KVM virtualization mode (HV, PR)"); 3286 object_property_add_bool(obj, "modern-hotplug-events", 3287 spapr_get_modern_hotplug_events, 3288 spapr_set_modern_hotplug_events); 3289 object_property_set_description(obj, "modern-hotplug-events", 3290 "Use dedicated hotplug event mechanism in" 3291 " place of standard EPOW events when possible" 3292 " (required for memory hot-unplug support)"); 3293 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3294 "Maximum permitted CPU compatibility mode"); 3295 3296 object_property_add_str(obj, "resize-hpt", 3297 spapr_get_resize_hpt, spapr_set_resize_hpt); 3298 object_property_set_description(obj, "resize-hpt", 3299 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3300 object_property_add_uint32_ptr(obj, "vsmt", 3301 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3302 object_property_set_description(obj, "vsmt", 3303 "Virtual SMT: KVM behaves as if this were" 3304 " the host's SMT mode"); 3305 3306 object_property_add_bool(obj, "vfio-no-msix-emulation", 3307 spapr_get_msix_emulation, NULL); 3308 3309 object_property_add_uint64_ptr(obj, "kernel-addr", 3310 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3311 object_property_set_description(obj, "kernel-addr", 3312 stringify(KERNEL_LOAD_ADDR) 3313 " for -kernel is the default"); 3314 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3315 /* The machine class defines the default interrupt controller mode */ 3316 spapr->irq = smc->irq; 3317 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3318 spapr_set_ic_mode); 3319 object_property_set_description(obj, "ic-mode", 3320 "Specifies the interrupt controller mode (xics, xive, dual)"); 3321 3322 object_property_add_str(obj, "host-model", 3323 spapr_get_host_model, spapr_set_host_model); 3324 object_property_set_description(obj, "host-model", 3325 "Host model to advertise in guest device tree"); 3326 object_property_add_str(obj, "host-serial", 3327 spapr_get_host_serial, spapr_set_host_serial); 3328 object_property_set_description(obj, "host-serial", 3329 "Host serial number to advertise in guest device tree"); 3330 } 3331 3332 static void spapr_machine_finalizefn(Object *obj) 3333 { 3334 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3335 3336 g_free(spapr->kvm_type); 3337 } 3338 3339 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3340 { 3341 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3342 PowerPCCPU *cpu = POWERPC_CPU(cs); 3343 CPUPPCState *env = &cpu->env; 3344 3345 cpu_synchronize_state(cs); 3346 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3347 if (spapr->fwnmi_system_reset_addr != -1) { 3348 uint64_t rtas_addr, addr; 3349 3350 /* get rtas addr from fdt */ 3351 rtas_addr = spapr_get_rtas_addr(); 3352 if (!rtas_addr) { 3353 qemu_system_guest_panicked(NULL); 3354 return; 3355 } 3356 3357 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3358 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3359 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3360 env->gpr[3] = addr; 3361 } 3362 ppc_cpu_do_system_reset(cs); 3363 if (spapr->fwnmi_system_reset_addr != -1) { 3364 env->nip = spapr->fwnmi_system_reset_addr; 3365 } 3366 } 3367 3368 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3369 { 3370 CPUState *cs; 3371 3372 CPU_FOREACH(cs) { 3373 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3374 } 3375 } 3376 3377 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3378 void *fdt, int *fdt_start_offset, Error **errp) 3379 { 3380 uint64_t addr; 3381 uint32_t node; 3382 3383 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3384 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3385 &error_abort); 3386 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3387 SPAPR_MEMORY_BLOCK_SIZE); 3388 return 0; 3389 } 3390 3391 static bool spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3392 bool dedicated_hp_event_source, Error **errp) 3393 { 3394 SpaprDrc *drc; 3395 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3396 int i; 3397 uint64_t addr = addr_start; 3398 bool hotplugged = spapr_drc_hotplugged(dev); 3399 3400 for (i = 0; i < nr_lmbs; i++) { 3401 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3402 addr / SPAPR_MEMORY_BLOCK_SIZE); 3403 g_assert(drc); 3404 3405 if (!spapr_drc_attach(drc, dev, errp)) { 3406 while (addr > addr_start) { 3407 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3408 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3409 addr / SPAPR_MEMORY_BLOCK_SIZE); 3410 spapr_drc_detach(drc); 3411 } 3412 return false; 3413 } 3414 if (!hotplugged) { 3415 spapr_drc_reset(drc); 3416 } 3417 addr += SPAPR_MEMORY_BLOCK_SIZE; 3418 } 3419 /* send hotplug notification to the 3420 * guest only in case of hotplugged memory 3421 */ 3422 if (hotplugged) { 3423 if (dedicated_hp_event_source) { 3424 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3425 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3426 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3427 nr_lmbs, 3428 spapr_drc_index(drc)); 3429 } else { 3430 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3431 nr_lmbs); 3432 } 3433 } 3434 return true; 3435 } 3436 3437 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3438 Error **errp) 3439 { 3440 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3441 PCDIMMDevice *dimm = PC_DIMM(dev); 3442 uint64_t size, addr; 3443 int64_t slot; 3444 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3445 3446 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3447 3448 pc_dimm_plug(dimm, MACHINE(ms)); 3449 3450 if (!is_nvdimm) { 3451 addr = object_property_get_uint(OBJECT(dimm), 3452 PC_DIMM_ADDR_PROP, &error_abort); 3453 if (!spapr_add_lmbs(dev, addr, size, 3454 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), errp)) { 3455 goto out_unplug; 3456 } 3457 } else { 3458 slot = object_property_get_int(OBJECT(dimm), 3459 PC_DIMM_SLOT_PROP, &error_abort); 3460 /* We should have valid slot number at this point */ 3461 g_assert(slot >= 0); 3462 if (!spapr_add_nvdimm(dev, slot, errp)) { 3463 goto out_unplug; 3464 } 3465 } 3466 3467 return; 3468 3469 out_unplug: 3470 pc_dimm_unplug(dimm, MACHINE(ms)); 3471 } 3472 3473 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3474 Error **errp) 3475 { 3476 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3477 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3478 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3479 PCDIMMDevice *dimm = PC_DIMM(dev); 3480 Error *local_err = NULL; 3481 uint64_t size; 3482 Object *memdev; 3483 hwaddr pagesize; 3484 3485 if (!smc->dr_lmb_enabled) { 3486 error_setg(errp, "Memory hotplug not supported for this machine"); 3487 return; 3488 } 3489 3490 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3491 if (local_err) { 3492 error_propagate(errp, local_err); 3493 return; 3494 } 3495 3496 if (is_nvdimm) { 3497 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3498 return; 3499 } 3500 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3501 error_setg(errp, "Hotplugged memory size must be a multiple of " 3502 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3503 return; 3504 } 3505 3506 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3507 &error_abort); 3508 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3509 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3510 return; 3511 } 3512 3513 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3514 } 3515 3516 struct SpaprDimmState { 3517 PCDIMMDevice *dimm; 3518 uint32_t nr_lmbs; 3519 QTAILQ_ENTRY(SpaprDimmState) next; 3520 }; 3521 3522 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3523 PCDIMMDevice *dimm) 3524 { 3525 SpaprDimmState *dimm_state = NULL; 3526 3527 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3528 if (dimm_state->dimm == dimm) { 3529 break; 3530 } 3531 } 3532 return dimm_state; 3533 } 3534 3535 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3536 uint32_t nr_lmbs, 3537 PCDIMMDevice *dimm) 3538 { 3539 SpaprDimmState *ds = NULL; 3540 3541 /* 3542 * If this request is for a DIMM whose removal had failed earlier 3543 * (due to guest's refusal to remove the LMBs), we would have this 3544 * dimm already in the pending_dimm_unplugs list. In that 3545 * case don't add again. 3546 */ 3547 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3548 if (!ds) { 3549 ds = g_malloc0(sizeof(SpaprDimmState)); 3550 ds->nr_lmbs = nr_lmbs; 3551 ds->dimm = dimm; 3552 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3553 } 3554 return ds; 3555 } 3556 3557 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3558 SpaprDimmState *dimm_state) 3559 { 3560 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3561 g_free(dimm_state); 3562 } 3563 3564 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3565 PCDIMMDevice *dimm) 3566 { 3567 SpaprDrc *drc; 3568 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3569 &error_abort); 3570 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3571 uint32_t avail_lmbs = 0; 3572 uint64_t addr_start, addr; 3573 int i; 3574 3575 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3576 &error_abort); 3577 3578 addr = addr_start; 3579 for (i = 0; i < nr_lmbs; i++) { 3580 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3581 addr / SPAPR_MEMORY_BLOCK_SIZE); 3582 g_assert(drc); 3583 if (drc->dev) { 3584 avail_lmbs++; 3585 } 3586 addr += SPAPR_MEMORY_BLOCK_SIZE; 3587 } 3588 3589 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3590 } 3591 3592 /* Callback to be called during DRC release. */ 3593 void spapr_lmb_release(DeviceState *dev) 3594 { 3595 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3596 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3597 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3598 3599 /* This information will get lost if a migration occurs 3600 * during the unplug process. In this case recover it. */ 3601 if (ds == NULL) { 3602 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3603 g_assert(ds); 3604 /* The DRC being examined by the caller at least must be counted */ 3605 g_assert(ds->nr_lmbs); 3606 } 3607 3608 if (--ds->nr_lmbs) { 3609 return; 3610 } 3611 3612 /* 3613 * Now that all the LMBs have been removed by the guest, call the 3614 * unplug handler chain. This can never fail. 3615 */ 3616 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3617 object_unparent(OBJECT(dev)); 3618 } 3619 3620 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3621 { 3622 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3623 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3624 3625 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3626 qdev_unrealize(dev); 3627 spapr_pending_dimm_unplugs_remove(spapr, ds); 3628 } 3629 3630 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3631 DeviceState *dev, Error **errp) 3632 { 3633 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3634 PCDIMMDevice *dimm = PC_DIMM(dev); 3635 uint32_t nr_lmbs; 3636 uint64_t size, addr_start, addr; 3637 int i; 3638 SpaprDrc *drc; 3639 3640 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3641 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3642 return; 3643 } 3644 3645 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3646 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3647 3648 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3649 &error_abort); 3650 3651 /* 3652 * An existing pending dimm state for this DIMM means that there is an 3653 * unplug operation in progress, waiting for the spapr_lmb_release 3654 * callback to complete the job (BQL can't cover that far). In this case, 3655 * bail out to avoid detaching DRCs that were already released. 3656 */ 3657 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3658 error_setg(errp, "Memory unplug already in progress for device %s", 3659 dev->id); 3660 return; 3661 } 3662 3663 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3664 3665 addr = addr_start; 3666 for (i = 0; i < nr_lmbs; i++) { 3667 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3668 addr / SPAPR_MEMORY_BLOCK_SIZE); 3669 g_assert(drc); 3670 3671 spapr_drc_detach(drc); 3672 addr += SPAPR_MEMORY_BLOCK_SIZE; 3673 } 3674 3675 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3676 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3677 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3678 nr_lmbs, spapr_drc_index(drc)); 3679 } 3680 3681 /* Callback to be called during DRC release. */ 3682 void spapr_core_release(DeviceState *dev) 3683 { 3684 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3685 3686 /* Call the unplug handler chain. This can never fail. */ 3687 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3688 object_unparent(OBJECT(dev)); 3689 } 3690 3691 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3692 { 3693 MachineState *ms = MACHINE(hotplug_dev); 3694 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3695 CPUCore *cc = CPU_CORE(dev); 3696 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3697 3698 if (smc->pre_2_10_has_unused_icps) { 3699 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3700 int i; 3701 3702 for (i = 0; i < cc->nr_threads; i++) { 3703 CPUState *cs = CPU(sc->threads[i]); 3704 3705 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3706 } 3707 } 3708 3709 assert(core_slot); 3710 core_slot->cpu = NULL; 3711 qdev_unrealize(dev); 3712 } 3713 3714 static 3715 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3716 Error **errp) 3717 { 3718 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3719 int index; 3720 SpaprDrc *drc; 3721 CPUCore *cc = CPU_CORE(dev); 3722 3723 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3724 error_setg(errp, "Unable to find CPU core with core-id: %d", 3725 cc->core_id); 3726 return; 3727 } 3728 if (index == 0) { 3729 error_setg(errp, "Boot CPU core may not be unplugged"); 3730 return; 3731 } 3732 3733 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3734 spapr_vcpu_id(spapr, cc->core_id)); 3735 g_assert(drc); 3736 3737 if (!spapr_drc_unplug_requested(drc)) { 3738 spapr_drc_detach(drc); 3739 spapr_hotplug_req_remove_by_index(drc); 3740 } 3741 } 3742 3743 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3744 void *fdt, int *fdt_start_offset, Error **errp) 3745 { 3746 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3747 CPUState *cs = CPU(core->threads[0]); 3748 PowerPCCPU *cpu = POWERPC_CPU(cs); 3749 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3750 int id = spapr_get_vcpu_id(cpu); 3751 char *nodename; 3752 int offset; 3753 3754 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3755 offset = fdt_add_subnode(fdt, 0, nodename); 3756 g_free(nodename); 3757 3758 spapr_dt_cpu(cs, fdt, offset, spapr); 3759 3760 *fdt_start_offset = offset; 3761 return 0; 3762 } 3763 3764 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3765 Error **errp) 3766 { 3767 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3768 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3769 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3770 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3771 CPUCore *cc = CPU_CORE(dev); 3772 CPUState *cs; 3773 SpaprDrc *drc; 3774 CPUArchId *core_slot; 3775 int index; 3776 bool hotplugged = spapr_drc_hotplugged(dev); 3777 int i; 3778 3779 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3780 if (!core_slot) { 3781 error_setg(errp, "Unable to find CPU core with core-id: %d", 3782 cc->core_id); 3783 return; 3784 } 3785 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3786 spapr_vcpu_id(spapr, cc->core_id)); 3787 3788 g_assert(drc || !mc->has_hotpluggable_cpus); 3789 3790 if (drc) { 3791 if (!spapr_drc_attach(drc, dev, errp)) { 3792 return; 3793 } 3794 3795 if (hotplugged) { 3796 /* 3797 * Send hotplug notification interrupt to the guest only 3798 * in case of hotplugged CPUs. 3799 */ 3800 spapr_hotplug_req_add_by_index(drc); 3801 } else { 3802 spapr_drc_reset(drc); 3803 } 3804 } 3805 3806 core_slot->cpu = OBJECT(dev); 3807 3808 if (smc->pre_2_10_has_unused_icps) { 3809 for (i = 0; i < cc->nr_threads; i++) { 3810 cs = CPU(core->threads[i]); 3811 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3812 } 3813 } 3814 3815 /* 3816 * Set compatibility mode to match the boot CPU, which was either set 3817 * by the machine reset code or by CAS. 3818 */ 3819 if (hotplugged) { 3820 for (i = 0; i < cc->nr_threads; i++) { 3821 if (ppc_set_compat(core->threads[i], 3822 POWERPC_CPU(first_cpu)->compat_pvr, 3823 errp) < 0) { 3824 return; 3825 } 3826 } 3827 } 3828 } 3829 3830 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3831 Error **errp) 3832 { 3833 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3834 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3835 CPUCore *cc = CPU_CORE(dev); 3836 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3837 const char *type = object_get_typename(OBJECT(dev)); 3838 CPUArchId *core_slot; 3839 int index; 3840 unsigned int smp_threads = machine->smp.threads; 3841 3842 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3843 error_setg(errp, "CPU hotplug not supported for this machine"); 3844 return; 3845 } 3846 3847 if (strcmp(base_core_type, type)) { 3848 error_setg(errp, "CPU core type should be %s", base_core_type); 3849 return; 3850 } 3851 3852 if (cc->core_id % smp_threads) { 3853 error_setg(errp, "invalid core id %d", cc->core_id); 3854 return; 3855 } 3856 3857 /* 3858 * In general we should have homogeneous threads-per-core, but old 3859 * (pre hotplug support) machine types allow the last core to have 3860 * reduced threads as a compatibility hack for when we allowed 3861 * total vcpus not a multiple of threads-per-core. 3862 */ 3863 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3864 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 3865 smp_threads); 3866 return; 3867 } 3868 3869 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3870 if (!core_slot) { 3871 error_setg(errp, "core id %d out of range", cc->core_id); 3872 return; 3873 } 3874 3875 if (core_slot->cpu) { 3876 error_setg(errp, "core %d already populated", cc->core_id); 3877 return; 3878 } 3879 3880 numa_cpu_pre_plug(core_slot, dev, errp); 3881 } 3882 3883 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3884 void *fdt, int *fdt_start_offset, Error **errp) 3885 { 3886 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3887 int intc_phandle; 3888 3889 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3890 if (intc_phandle <= 0) { 3891 return -1; 3892 } 3893 3894 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3895 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3896 return -1; 3897 } 3898 3899 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3900 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3901 3902 return 0; 3903 } 3904 3905 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3906 Error **errp) 3907 { 3908 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3909 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3910 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3911 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3912 3913 if (dev->hotplugged && !smc->dr_phb_enabled) { 3914 error_setg(errp, "PHB hotplug not supported for this machine"); 3915 return; 3916 } 3917 3918 if (sphb->index == (uint32_t)-1) { 3919 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3920 return; 3921 } 3922 3923 /* 3924 * This will check that sphb->index doesn't exceed the maximum number of 3925 * PHBs for the current machine type. 3926 */ 3927 smc->phb_placement(spapr, sphb->index, 3928 &sphb->buid, &sphb->io_win_addr, 3929 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3930 windows_supported, sphb->dma_liobn, 3931 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3932 errp); 3933 } 3934 3935 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3936 Error **errp) 3937 { 3938 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3939 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3940 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3941 SpaprDrc *drc; 3942 bool hotplugged = spapr_drc_hotplugged(dev); 3943 3944 if (!smc->dr_phb_enabled) { 3945 return; 3946 } 3947 3948 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3949 /* hotplug hooks should check it's enabled before getting this far */ 3950 assert(drc); 3951 3952 if (!spapr_drc_attach(drc, dev, errp)) { 3953 return; 3954 } 3955 3956 if (hotplugged) { 3957 spapr_hotplug_req_add_by_index(drc); 3958 } else { 3959 spapr_drc_reset(drc); 3960 } 3961 } 3962 3963 void spapr_phb_release(DeviceState *dev) 3964 { 3965 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3966 3967 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3968 object_unparent(OBJECT(dev)); 3969 } 3970 3971 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3972 { 3973 qdev_unrealize(dev); 3974 } 3975 3976 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 3977 DeviceState *dev, Error **errp) 3978 { 3979 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3980 SpaprDrc *drc; 3981 3982 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3983 assert(drc); 3984 3985 if (!spapr_drc_unplug_requested(drc)) { 3986 spapr_drc_detach(drc); 3987 spapr_hotplug_req_remove_by_index(drc); 3988 } 3989 } 3990 3991 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3992 Error **errp) 3993 { 3994 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3995 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 3996 3997 if (spapr->tpm_proxy != NULL) { 3998 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 3999 return; 4000 } 4001 4002 spapr->tpm_proxy = tpm_proxy; 4003 } 4004 4005 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4006 { 4007 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4008 4009 qdev_unrealize(dev); 4010 object_unparent(OBJECT(dev)); 4011 spapr->tpm_proxy = NULL; 4012 } 4013 4014 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4015 DeviceState *dev, Error **errp) 4016 { 4017 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4018 spapr_memory_plug(hotplug_dev, dev, errp); 4019 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4020 spapr_core_plug(hotplug_dev, dev, errp); 4021 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4022 spapr_phb_plug(hotplug_dev, dev, errp); 4023 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4024 spapr_tpm_proxy_plug(hotplug_dev, dev, errp); 4025 } 4026 } 4027 4028 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4029 DeviceState *dev, Error **errp) 4030 { 4031 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4032 spapr_memory_unplug(hotplug_dev, dev); 4033 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4034 spapr_core_unplug(hotplug_dev, dev); 4035 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4036 spapr_phb_unplug(hotplug_dev, dev); 4037 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4038 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4039 } 4040 } 4041 4042 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4043 DeviceState *dev, Error **errp) 4044 { 4045 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4046 MachineClass *mc = MACHINE_GET_CLASS(sms); 4047 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4048 4049 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4050 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 4051 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4052 } else { 4053 /* NOTE: this means there is a window after guest reset, prior to 4054 * CAS negotiation, where unplug requests will fail due to the 4055 * capability not being detected yet. This is a bit different than 4056 * the case with PCI unplug, where the events will be queued and 4057 * eventually handled by the guest after boot 4058 */ 4059 error_setg(errp, "Memory hot unplug not supported for this guest"); 4060 } 4061 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4062 if (!mc->has_hotpluggable_cpus) { 4063 error_setg(errp, "CPU hot unplug not supported on this machine"); 4064 return; 4065 } 4066 spapr_core_unplug_request(hotplug_dev, dev, errp); 4067 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4068 if (!smc->dr_phb_enabled) { 4069 error_setg(errp, "PHB hot unplug not supported on this machine"); 4070 return; 4071 } 4072 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4073 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4074 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4075 } 4076 } 4077 4078 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4079 DeviceState *dev, Error **errp) 4080 { 4081 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4082 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4083 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4084 spapr_core_pre_plug(hotplug_dev, dev, errp); 4085 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4086 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4087 } 4088 } 4089 4090 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4091 DeviceState *dev) 4092 { 4093 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4094 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4095 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4096 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4097 return HOTPLUG_HANDLER(machine); 4098 } 4099 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4100 PCIDevice *pcidev = PCI_DEVICE(dev); 4101 PCIBus *root = pci_device_root_bus(pcidev); 4102 SpaprPhbState *phb = 4103 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4104 TYPE_SPAPR_PCI_HOST_BRIDGE); 4105 4106 if (phb) { 4107 return HOTPLUG_HANDLER(phb); 4108 } 4109 } 4110 return NULL; 4111 } 4112 4113 static CpuInstanceProperties 4114 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4115 { 4116 CPUArchId *core_slot; 4117 MachineClass *mc = MACHINE_GET_CLASS(machine); 4118 4119 /* make sure possible_cpu are intialized */ 4120 mc->possible_cpu_arch_ids(machine); 4121 /* get CPU core slot containing thread that matches cpu_index */ 4122 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4123 assert(core_slot); 4124 return core_slot->props; 4125 } 4126 4127 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4128 { 4129 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4130 } 4131 4132 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4133 { 4134 int i; 4135 unsigned int smp_threads = machine->smp.threads; 4136 unsigned int smp_cpus = machine->smp.cpus; 4137 const char *core_type; 4138 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4139 MachineClass *mc = MACHINE_GET_CLASS(machine); 4140 4141 if (!mc->has_hotpluggable_cpus) { 4142 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4143 } 4144 if (machine->possible_cpus) { 4145 assert(machine->possible_cpus->len == spapr_max_cores); 4146 return machine->possible_cpus; 4147 } 4148 4149 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4150 if (!core_type) { 4151 error_report("Unable to find sPAPR CPU Core definition"); 4152 exit(1); 4153 } 4154 4155 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4156 sizeof(CPUArchId) * spapr_max_cores); 4157 machine->possible_cpus->len = spapr_max_cores; 4158 for (i = 0; i < machine->possible_cpus->len; i++) { 4159 int core_id = i * smp_threads; 4160 4161 machine->possible_cpus->cpus[i].type = core_type; 4162 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4163 machine->possible_cpus->cpus[i].arch_id = core_id; 4164 machine->possible_cpus->cpus[i].props.has_core_id = true; 4165 machine->possible_cpus->cpus[i].props.core_id = core_id; 4166 } 4167 return machine->possible_cpus; 4168 } 4169 4170 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4171 uint64_t *buid, hwaddr *pio, 4172 hwaddr *mmio32, hwaddr *mmio64, 4173 unsigned n_dma, uint32_t *liobns, 4174 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4175 { 4176 /* 4177 * New-style PHB window placement. 4178 * 4179 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4180 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4181 * windows. 4182 * 4183 * Some guest kernels can't work with MMIO windows above 1<<46 4184 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4185 * 4186 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4187 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4188 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4189 * 1TiB 64-bit MMIO windows for each PHB. 4190 */ 4191 const uint64_t base_buid = 0x800000020000000ULL; 4192 int i; 4193 4194 /* Sanity check natural alignments */ 4195 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4196 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4197 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4198 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4199 /* Sanity check bounds */ 4200 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4201 SPAPR_PCI_MEM32_WIN_SIZE); 4202 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4203 SPAPR_PCI_MEM64_WIN_SIZE); 4204 4205 if (index >= SPAPR_MAX_PHBS) { 4206 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4207 SPAPR_MAX_PHBS - 1); 4208 return; 4209 } 4210 4211 *buid = base_buid + index; 4212 for (i = 0; i < n_dma; ++i) { 4213 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4214 } 4215 4216 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4217 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4218 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4219 4220 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4221 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4222 } 4223 4224 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4225 { 4226 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4227 4228 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4229 } 4230 4231 static void spapr_ics_resend(XICSFabric *dev) 4232 { 4233 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4234 4235 ics_resend(spapr->ics); 4236 } 4237 4238 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4239 { 4240 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4241 4242 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4243 } 4244 4245 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4246 Monitor *mon) 4247 { 4248 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4249 4250 spapr_irq_print_info(spapr, mon); 4251 monitor_printf(mon, "irqchip: %s\n", 4252 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4253 } 4254 4255 /* 4256 * This is a XIVE only operation 4257 */ 4258 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4259 uint8_t nvt_blk, uint32_t nvt_idx, 4260 bool cam_ignore, uint8_t priority, 4261 uint32_t logic_serv, XiveTCTXMatch *match) 4262 { 4263 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4264 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4265 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4266 int count; 4267 4268 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4269 priority, logic_serv, match); 4270 if (count < 0) { 4271 return count; 4272 } 4273 4274 /* 4275 * When we implement the save and restore of the thread interrupt 4276 * contexts in the enter/exit CPU handlers of the machine and the 4277 * escalations in QEMU, we should be able to handle non dispatched 4278 * vCPUs. 4279 * 4280 * Until this is done, the sPAPR machine should find at least one 4281 * matching context always. 4282 */ 4283 if (count == 0) { 4284 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4285 nvt_blk, nvt_idx); 4286 } 4287 4288 return count; 4289 } 4290 4291 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4292 { 4293 return cpu->vcpu_id; 4294 } 4295 4296 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4297 { 4298 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4299 MachineState *ms = MACHINE(spapr); 4300 int vcpu_id; 4301 4302 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4303 4304 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4305 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4306 error_append_hint(errp, "Adjust the number of cpus to %d " 4307 "or try to raise the number of threads per core\n", 4308 vcpu_id * ms->smp.threads / spapr->vsmt); 4309 return false; 4310 } 4311 4312 cpu->vcpu_id = vcpu_id; 4313 return true; 4314 } 4315 4316 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4317 { 4318 CPUState *cs; 4319 4320 CPU_FOREACH(cs) { 4321 PowerPCCPU *cpu = POWERPC_CPU(cs); 4322 4323 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4324 return cpu; 4325 } 4326 } 4327 4328 return NULL; 4329 } 4330 4331 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4332 { 4333 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4334 4335 /* These are only called by TCG, KVM maintains dispatch state */ 4336 4337 spapr_cpu->prod = false; 4338 if (spapr_cpu->vpa_addr) { 4339 CPUState *cs = CPU(cpu); 4340 uint32_t dispatch; 4341 4342 dispatch = ldl_be_phys(cs->as, 4343 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4344 dispatch++; 4345 if ((dispatch & 1) != 0) { 4346 qemu_log_mask(LOG_GUEST_ERROR, 4347 "VPA: incorrect dispatch counter value for " 4348 "dispatched partition %u, correcting.\n", dispatch); 4349 dispatch++; 4350 } 4351 stl_be_phys(cs->as, 4352 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4353 } 4354 } 4355 4356 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4357 { 4358 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4359 4360 if (spapr_cpu->vpa_addr) { 4361 CPUState *cs = CPU(cpu); 4362 uint32_t dispatch; 4363 4364 dispatch = ldl_be_phys(cs->as, 4365 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4366 dispatch++; 4367 if ((dispatch & 1) != 1) { 4368 qemu_log_mask(LOG_GUEST_ERROR, 4369 "VPA: incorrect dispatch counter value for " 4370 "preempted partition %u, correcting.\n", dispatch); 4371 dispatch++; 4372 } 4373 stl_be_phys(cs->as, 4374 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4375 } 4376 } 4377 4378 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4379 { 4380 MachineClass *mc = MACHINE_CLASS(oc); 4381 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4382 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4383 NMIClass *nc = NMI_CLASS(oc); 4384 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4385 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4386 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4387 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4388 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4389 4390 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4391 mc->ignore_boot_device_suffixes = true; 4392 4393 /* 4394 * We set up the default / latest behaviour here. The class_init 4395 * functions for the specific versioned machine types can override 4396 * these details for backwards compatibility 4397 */ 4398 mc->init = spapr_machine_init; 4399 mc->reset = spapr_machine_reset; 4400 mc->block_default_type = IF_SCSI; 4401 mc->max_cpus = 1024; 4402 mc->no_parallel = 1; 4403 mc->default_boot_order = ""; 4404 mc->default_ram_size = 512 * MiB; 4405 mc->default_ram_id = "ppc_spapr.ram"; 4406 mc->default_display = "std"; 4407 mc->kvm_type = spapr_kvm_type; 4408 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4409 mc->pci_allow_0_address = true; 4410 assert(!mc->get_hotplug_handler); 4411 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4412 hc->pre_plug = spapr_machine_device_pre_plug; 4413 hc->plug = spapr_machine_device_plug; 4414 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4415 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4416 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4417 hc->unplug_request = spapr_machine_device_unplug_request; 4418 hc->unplug = spapr_machine_device_unplug; 4419 4420 smc->dr_lmb_enabled = true; 4421 smc->update_dt_enabled = true; 4422 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4423 mc->has_hotpluggable_cpus = true; 4424 mc->nvdimm_supported = true; 4425 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4426 fwc->get_dev_path = spapr_get_fw_dev_path; 4427 nc->nmi_monitor_handler = spapr_nmi; 4428 smc->phb_placement = spapr_phb_placement; 4429 vhc->hypercall = emulate_spapr_hypercall; 4430 vhc->hpt_mask = spapr_hpt_mask; 4431 vhc->map_hptes = spapr_map_hptes; 4432 vhc->unmap_hptes = spapr_unmap_hptes; 4433 vhc->hpte_set_c = spapr_hpte_set_c; 4434 vhc->hpte_set_r = spapr_hpte_set_r; 4435 vhc->get_pate = spapr_get_pate; 4436 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4437 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4438 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4439 xic->ics_get = spapr_ics_get; 4440 xic->ics_resend = spapr_ics_resend; 4441 xic->icp_get = spapr_icp_get; 4442 ispc->print_info = spapr_pic_print_info; 4443 /* Force NUMA node memory size to be a multiple of 4444 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4445 * in which LMBs are represented and hot-added 4446 */ 4447 mc->numa_mem_align_shift = 28; 4448 mc->auto_enable_numa = true; 4449 4450 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4451 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4452 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4453 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4454 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4455 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4456 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4457 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4458 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4459 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4460 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4461 spapr_caps_add_properties(smc); 4462 smc->irq = &spapr_irq_dual; 4463 smc->dr_phb_enabled = true; 4464 smc->linux_pci_probe = true; 4465 smc->smp_threads_vsmt = true; 4466 smc->nr_xirqs = SPAPR_NR_XIRQS; 4467 xfc->match_nvt = spapr_match_nvt; 4468 } 4469 4470 static const TypeInfo spapr_machine_info = { 4471 .name = TYPE_SPAPR_MACHINE, 4472 .parent = TYPE_MACHINE, 4473 .abstract = true, 4474 .instance_size = sizeof(SpaprMachineState), 4475 .instance_init = spapr_instance_init, 4476 .instance_finalize = spapr_machine_finalizefn, 4477 .class_size = sizeof(SpaprMachineClass), 4478 .class_init = spapr_machine_class_init, 4479 .interfaces = (InterfaceInfo[]) { 4480 { TYPE_FW_PATH_PROVIDER }, 4481 { TYPE_NMI }, 4482 { TYPE_HOTPLUG_HANDLER }, 4483 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4484 { TYPE_XICS_FABRIC }, 4485 { TYPE_INTERRUPT_STATS_PROVIDER }, 4486 { TYPE_XIVE_FABRIC }, 4487 { } 4488 }, 4489 }; 4490 4491 static void spapr_machine_latest_class_options(MachineClass *mc) 4492 { 4493 mc->alias = "pseries"; 4494 mc->is_default = true; 4495 } 4496 4497 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4498 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4499 void *data) \ 4500 { \ 4501 MachineClass *mc = MACHINE_CLASS(oc); \ 4502 spapr_machine_##suffix##_class_options(mc); \ 4503 if (latest) { \ 4504 spapr_machine_latest_class_options(mc); \ 4505 } \ 4506 } \ 4507 static const TypeInfo spapr_machine_##suffix##_info = { \ 4508 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4509 .parent = TYPE_SPAPR_MACHINE, \ 4510 .class_init = spapr_machine_##suffix##_class_init, \ 4511 }; \ 4512 static void spapr_machine_register_##suffix(void) \ 4513 { \ 4514 type_register(&spapr_machine_##suffix##_info); \ 4515 } \ 4516 type_init(spapr_machine_register_##suffix) 4517 4518 /* 4519 * pseries-5.2 4520 */ 4521 static void spapr_machine_5_2_class_options(MachineClass *mc) 4522 { 4523 /* Defaults for the latest behaviour inherited from the base class */ 4524 } 4525 4526 DEFINE_SPAPR_MACHINE(5_2, "5.2", true); 4527 4528 /* 4529 * pseries-5.1 4530 */ 4531 static void spapr_machine_5_1_class_options(MachineClass *mc) 4532 { 4533 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4534 4535 spapr_machine_5_2_class_options(mc); 4536 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4537 smc->pre_5_2_numa_associativity = true; 4538 } 4539 4540 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4541 4542 /* 4543 * pseries-5.0 4544 */ 4545 static void spapr_machine_5_0_class_options(MachineClass *mc) 4546 { 4547 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4548 static GlobalProperty compat[] = { 4549 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4550 }; 4551 4552 spapr_machine_5_1_class_options(mc); 4553 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4554 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4555 mc->numa_mem_supported = true; 4556 smc->pre_5_1_assoc_refpoints = true; 4557 } 4558 4559 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4560 4561 /* 4562 * pseries-4.2 4563 */ 4564 static void spapr_machine_4_2_class_options(MachineClass *mc) 4565 { 4566 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4567 4568 spapr_machine_5_0_class_options(mc); 4569 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4570 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4571 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4572 smc->rma_limit = 16 * GiB; 4573 mc->nvdimm_supported = false; 4574 } 4575 4576 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4577 4578 /* 4579 * pseries-4.1 4580 */ 4581 static void spapr_machine_4_1_class_options(MachineClass *mc) 4582 { 4583 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4584 static GlobalProperty compat[] = { 4585 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4586 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4587 }; 4588 4589 spapr_machine_4_2_class_options(mc); 4590 smc->linux_pci_probe = false; 4591 smc->smp_threads_vsmt = false; 4592 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4593 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4594 } 4595 4596 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4597 4598 /* 4599 * pseries-4.0 4600 */ 4601 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4602 uint64_t *buid, hwaddr *pio, 4603 hwaddr *mmio32, hwaddr *mmio64, 4604 unsigned n_dma, uint32_t *liobns, 4605 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4606 { 4607 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, 4608 nv2gpa, nv2atsd, errp); 4609 *nv2gpa = 0; 4610 *nv2atsd = 0; 4611 } 4612 4613 static void spapr_machine_4_0_class_options(MachineClass *mc) 4614 { 4615 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4616 4617 spapr_machine_4_1_class_options(mc); 4618 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4619 smc->phb_placement = phb_placement_4_0; 4620 smc->irq = &spapr_irq_xics; 4621 smc->pre_4_1_migration = true; 4622 } 4623 4624 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4625 4626 /* 4627 * pseries-3.1 4628 */ 4629 static void spapr_machine_3_1_class_options(MachineClass *mc) 4630 { 4631 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4632 4633 spapr_machine_4_0_class_options(mc); 4634 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4635 4636 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4637 smc->update_dt_enabled = false; 4638 smc->dr_phb_enabled = false; 4639 smc->broken_host_serial_model = true; 4640 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4641 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4642 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4643 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4644 } 4645 4646 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4647 4648 /* 4649 * pseries-3.0 4650 */ 4651 4652 static void spapr_machine_3_0_class_options(MachineClass *mc) 4653 { 4654 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4655 4656 spapr_machine_3_1_class_options(mc); 4657 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4658 4659 smc->legacy_irq_allocation = true; 4660 smc->nr_xirqs = 0x400; 4661 smc->irq = &spapr_irq_xics_legacy; 4662 } 4663 4664 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4665 4666 /* 4667 * pseries-2.12 4668 */ 4669 static void spapr_machine_2_12_class_options(MachineClass *mc) 4670 { 4671 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4672 static GlobalProperty compat[] = { 4673 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4674 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4675 }; 4676 4677 spapr_machine_3_0_class_options(mc); 4678 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4679 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4680 4681 /* We depend on kvm_enabled() to choose a default value for the 4682 * hpt-max-page-size capability. Of course we can't do it here 4683 * because this is too early and the HW accelerator isn't initialzed 4684 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4685 */ 4686 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4687 } 4688 4689 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4690 4691 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4692 { 4693 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4694 4695 spapr_machine_2_12_class_options(mc); 4696 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4697 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4698 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4699 } 4700 4701 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4702 4703 /* 4704 * pseries-2.11 4705 */ 4706 4707 static void spapr_machine_2_11_class_options(MachineClass *mc) 4708 { 4709 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4710 4711 spapr_machine_2_12_class_options(mc); 4712 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4713 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4714 } 4715 4716 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4717 4718 /* 4719 * pseries-2.10 4720 */ 4721 4722 static void spapr_machine_2_10_class_options(MachineClass *mc) 4723 { 4724 spapr_machine_2_11_class_options(mc); 4725 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4726 } 4727 4728 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4729 4730 /* 4731 * pseries-2.9 4732 */ 4733 4734 static void spapr_machine_2_9_class_options(MachineClass *mc) 4735 { 4736 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4737 static GlobalProperty compat[] = { 4738 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4739 }; 4740 4741 spapr_machine_2_10_class_options(mc); 4742 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4743 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4744 smc->pre_2_10_has_unused_icps = true; 4745 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4746 } 4747 4748 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4749 4750 /* 4751 * pseries-2.8 4752 */ 4753 4754 static void spapr_machine_2_8_class_options(MachineClass *mc) 4755 { 4756 static GlobalProperty compat[] = { 4757 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4758 }; 4759 4760 spapr_machine_2_9_class_options(mc); 4761 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4762 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4763 mc->numa_mem_align_shift = 23; 4764 } 4765 4766 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4767 4768 /* 4769 * pseries-2.7 4770 */ 4771 4772 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4773 uint64_t *buid, hwaddr *pio, 4774 hwaddr *mmio32, hwaddr *mmio64, 4775 unsigned n_dma, uint32_t *liobns, 4776 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4777 { 4778 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4779 const uint64_t base_buid = 0x800000020000000ULL; 4780 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4781 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4782 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4783 const uint32_t max_index = 255; 4784 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4785 4786 uint64_t ram_top = MACHINE(spapr)->ram_size; 4787 hwaddr phb0_base, phb_base; 4788 int i; 4789 4790 /* Do we have device memory? */ 4791 if (MACHINE(spapr)->maxram_size > ram_top) { 4792 /* Can't just use maxram_size, because there may be an 4793 * alignment gap between normal and device memory regions 4794 */ 4795 ram_top = MACHINE(spapr)->device_memory->base + 4796 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4797 } 4798 4799 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4800 4801 if (index > max_index) { 4802 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4803 max_index); 4804 return; 4805 } 4806 4807 *buid = base_buid + index; 4808 for (i = 0; i < n_dma; ++i) { 4809 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4810 } 4811 4812 phb_base = phb0_base + index * phb_spacing; 4813 *pio = phb_base + pio_offset; 4814 *mmio32 = phb_base + mmio_offset; 4815 /* 4816 * We don't set the 64-bit MMIO window, relying on the PHB's 4817 * fallback behaviour of automatically splitting a large "32-bit" 4818 * window into contiguous 32-bit and 64-bit windows 4819 */ 4820 4821 *nv2gpa = 0; 4822 *nv2atsd = 0; 4823 } 4824 4825 static void spapr_machine_2_7_class_options(MachineClass *mc) 4826 { 4827 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4828 static GlobalProperty compat[] = { 4829 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4830 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4831 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4832 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4833 }; 4834 4835 spapr_machine_2_8_class_options(mc); 4836 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4837 mc->default_machine_opts = "modern-hotplug-events=off"; 4838 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4839 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4840 smc->phb_placement = phb_placement_2_7; 4841 } 4842 4843 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4844 4845 /* 4846 * pseries-2.6 4847 */ 4848 4849 static void spapr_machine_2_6_class_options(MachineClass *mc) 4850 { 4851 static GlobalProperty compat[] = { 4852 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4853 }; 4854 4855 spapr_machine_2_7_class_options(mc); 4856 mc->has_hotpluggable_cpus = false; 4857 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4858 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4859 } 4860 4861 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4862 4863 /* 4864 * pseries-2.5 4865 */ 4866 4867 static void spapr_machine_2_5_class_options(MachineClass *mc) 4868 { 4869 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4870 static GlobalProperty compat[] = { 4871 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4872 }; 4873 4874 spapr_machine_2_6_class_options(mc); 4875 smc->use_ohci_by_default = true; 4876 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4877 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4878 } 4879 4880 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4881 4882 /* 4883 * pseries-2.4 4884 */ 4885 4886 static void spapr_machine_2_4_class_options(MachineClass *mc) 4887 { 4888 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4889 4890 spapr_machine_2_5_class_options(mc); 4891 smc->dr_lmb_enabled = false; 4892 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4893 } 4894 4895 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4896 4897 /* 4898 * pseries-2.3 4899 */ 4900 4901 static void spapr_machine_2_3_class_options(MachineClass *mc) 4902 { 4903 static GlobalProperty compat[] = { 4904 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4905 }; 4906 spapr_machine_2_4_class_options(mc); 4907 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4908 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4909 } 4910 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4911 4912 /* 4913 * pseries-2.2 4914 */ 4915 4916 static void spapr_machine_2_2_class_options(MachineClass *mc) 4917 { 4918 static GlobalProperty compat[] = { 4919 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4920 }; 4921 4922 spapr_machine_2_3_class_options(mc); 4923 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4924 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4925 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4926 } 4927 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4928 4929 /* 4930 * pseries-2.1 4931 */ 4932 4933 static void spapr_machine_2_1_class_options(MachineClass *mc) 4934 { 4935 spapr_machine_2_2_class_options(mc); 4936 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4937 } 4938 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4939 4940 static void spapr_machine_register_types(void) 4941 { 4942 type_register_static(&spapr_machine_info); 4943 } 4944 4945 type_init(spapr_machine_register_types) 4946