1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/numa.h" 31 #include "hw/hw.h" 32 #include "qemu/log.h" 33 #include "hw/fw-path-provider.h" 34 #include "elf.h" 35 #include "net/net.h" 36 #include "sysemu/device_tree.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/migration.h" 42 #include "mmu-hash64.h" 43 #include "qom/cpu.h" 44 45 #include "hw/boards.h" 46 #include "hw/ppc/ppc.h" 47 #include "hw/loader.h" 48 49 #include "hw/ppc/fdt.h" 50 #include "hw/ppc/spapr.h" 51 #include "hw/ppc/spapr_vio.h" 52 #include "hw/pci-host/spapr.h" 53 #include "hw/ppc/xics.h" 54 #include "hw/pci/msi.h" 55 56 #include "hw/pci/pci.h" 57 #include "hw/scsi/scsi.h" 58 #include "hw/virtio/virtio-scsi.h" 59 60 #include "exec/address-spaces.h" 61 #include "hw/usb.h" 62 #include "qemu/config-file.h" 63 #include "qemu/error-report.h" 64 #include "trace.h" 65 #include "hw/nmi.h" 66 67 #include "hw/compat.h" 68 #include "qemu/cutils.h" 69 #include "hw/ppc/spapr_cpu_core.h" 70 #include "qmp-commands.h" 71 72 #include <libfdt.h> 73 74 /* SLOF memory layout: 75 * 76 * SLOF raw image loaded at 0, copies its romfs right below the flat 77 * device-tree, then position SLOF itself 31M below that 78 * 79 * So we set FW_OVERHEAD to 40MB which should account for all of that 80 * and more 81 * 82 * We load our kernel at 4M, leaving space for SLOF initial image 83 */ 84 #define FDT_MAX_SIZE 0x100000 85 #define RTAS_MAX_SIZE 0x10000 86 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 87 #define FW_MAX_SIZE 0x400000 88 #define FW_FILE_NAME "slof.bin" 89 #define FW_OVERHEAD 0x2800000 90 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 91 92 #define MIN_RMA_SLOF 128UL 93 94 #define PHANDLE_XICP 0x00001111 95 96 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 97 98 static XICSState *try_create_xics(sPAPRMachineState *spapr, 99 const char *type, const char *type_ics, 100 const char *type_icp, int nr_servers, 101 int nr_irqs, Error **errp) 102 { 103 XICSFabric *xi = XICS_FABRIC(spapr); 104 Error *err = NULL, *local_err = NULL; 105 XICSState *xics; 106 ICSState *ics = NULL; 107 int i; 108 109 xics = XICS_COMMON(object_new(type)); 110 qdev_set_parent_bus(DEVICE(xics), sysbus_get_default()); 111 object_property_set_bool(OBJECT(xics), true, "realized", &err); 112 if (err) { 113 goto error; 114 } 115 116 ics = ICS_SIMPLE(object_new(type_ics)); 117 qdev_set_parent_bus(DEVICE(ics), sysbus_get_default()); 118 object_property_add_child(OBJECT(spapr), "ics", OBJECT(ics), NULL); 119 object_property_set_int(OBJECT(ics), nr_irqs, "nr-irqs", &err); 120 object_property_add_const_link(OBJECT(ics), "xics", OBJECT(xi), NULL); 121 object_property_set_bool(OBJECT(ics), true, "realized", &local_err); 122 error_propagate(&err, local_err); 123 if (err) { 124 goto error; 125 } 126 127 spapr->icps = g_malloc0(nr_servers * sizeof(ICPState)); 128 spapr->nr_servers = nr_servers; 129 130 for (i = 0; i < nr_servers; i++) { 131 ICPState *icp = &spapr->icps[i]; 132 133 object_initialize(icp, sizeof(*icp), type_icp); 134 qdev_set_parent_bus(DEVICE(icp), sysbus_get_default()); 135 object_property_add_child(OBJECT(spapr), "icp[*]", OBJECT(icp), NULL); 136 object_property_add_const_link(OBJECT(icp), "xics", OBJECT(xi), NULL); 137 object_property_set_bool(OBJECT(icp), true, "realized", &err); 138 if (err) { 139 goto error; 140 } 141 object_unref(OBJECT(icp)); 142 } 143 144 spapr->ics = ics; 145 return xics; 146 147 error: 148 error_propagate(errp, err); 149 if (ics) { 150 object_unparent(OBJECT(ics)); 151 } 152 object_unparent(OBJECT(xics)); 153 return NULL; 154 } 155 156 static XICSState *xics_system_init(MachineState *machine, 157 int nr_servers, int nr_irqs, Error **errp) 158 { 159 XICSState *xics = NULL; 160 161 if (kvm_enabled()) { 162 Error *err = NULL; 163 164 if (machine_kernel_irqchip_allowed(machine) && 165 !xics_kvm_init(SPAPR_MACHINE(machine), errp)) { 166 xics = try_create_xics(SPAPR_MACHINE(machine), 167 TYPE_XICS_SPAPR_KVM, TYPE_ICS_KVM, 168 TYPE_KVM_ICP, nr_servers, nr_irqs, &err); 169 } 170 if (machine_kernel_irqchip_required(machine) && !xics) { 171 error_reportf_err(err, 172 "kernel_irqchip requested but unavailable: "); 173 } else { 174 error_free(err); 175 } 176 } 177 178 if (!xics) { 179 xics_spapr_init(SPAPR_MACHINE(machine), errp); 180 xics = try_create_xics(SPAPR_MACHINE(machine), 181 TYPE_XICS_SPAPR, TYPE_ICS_SIMPLE, 182 TYPE_ICP, nr_servers, nr_irqs, errp); 183 } 184 185 return xics; 186 } 187 188 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 189 int smt_threads) 190 { 191 int i, ret = 0; 192 uint32_t servers_prop[smt_threads]; 193 uint32_t gservers_prop[smt_threads * 2]; 194 int index = ppc_get_vcpu_dt_id(cpu); 195 196 if (cpu->compat_pvr) { 197 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 198 if (ret < 0) { 199 return ret; 200 } 201 } 202 203 /* Build interrupt servers and gservers properties */ 204 for (i = 0; i < smt_threads; i++) { 205 servers_prop[i] = cpu_to_be32(index + i); 206 /* Hack, direct the group queues back to cpu 0 */ 207 gservers_prop[i*2] = cpu_to_be32(index + i); 208 gservers_prop[i*2 + 1] = 0; 209 } 210 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 211 servers_prop, sizeof(servers_prop)); 212 if (ret < 0) { 213 return ret; 214 } 215 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 216 gservers_prop, sizeof(gservers_prop)); 217 218 return ret; 219 } 220 221 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) 222 { 223 int ret = 0; 224 PowerPCCPU *cpu = POWERPC_CPU(cs); 225 int index = ppc_get_vcpu_dt_id(cpu); 226 uint32_t associativity[] = {cpu_to_be32(0x5), 227 cpu_to_be32(0x0), 228 cpu_to_be32(0x0), 229 cpu_to_be32(0x0), 230 cpu_to_be32(cs->numa_node), 231 cpu_to_be32(index)}; 232 233 /* Advertise NUMA via ibm,associativity */ 234 if (nb_numa_nodes > 1) { 235 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 236 sizeof(associativity)); 237 } 238 239 return ret; 240 } 241 242 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 243 { 244 int ret = 0, offset, cpus_offset; 245 CPUState *cs; 246 char cpu_model[32]; 247 int smt = kvmppc_smt_threads(); 248 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 249 250 CPU_FOREACH(cs) { 251 PowerPCCPU *cpu = POWERPC_CPU(cs); 252 DeviceClass *dc = DEVICE_GET_CLASS(cs); 253 int index = ppc_get_vcpu_dt_id(cpu); 254 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 255 256 if ((index % smt) != 0) { 257 continue; 258 } 259 260 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 261 262 cpus_offset = fdt_path_offset(fdt, "/cpus"); 263 if (cpus_offset < 0) { 264 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 265 "cpus"); 266 if (cpus_offset < 0) { 267 return cpus_offset; 268 } 269 } 270 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 271 if (offset < 0) { 272 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 273 if (offset < 0) { 274 return offset; 275 } 276 } 277 278 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 279 pft_size_prop, sizeof(pft_size_prop)); 280 if (ret < 0) { 281 return ret; 282 } 283 284 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); 285 if (ret < 0) { 286 return ret; 287 } 288 289 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 290 if (ret < 0) { 291 return ret; 292 } 293 } 294 return ret; 295 } 296 297 static hwaddr spapr_node0_size(void) 298 { 299 MachineState *machine = MACHINE(qdev_get_machine()); 300 301 if (nb_numa_nodes) { 302 int i; 303 for (i = 0; i < nb_numa_nodes; ++i) { 304 if (numa_info[i].node_mem) { 305 return MIN(pow2floor(numa_info[i].node_mem), 306 machine->ram_size); 307 } 308 } 309 } 310 return machine->ram_size; 311 } 312 313 static void add_str(GString *s, const gchar *s1) 314 { 315 g_string_append_len(s, s1, strlen(s1) + 1); 316 } 317 318 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 319 hwaddr size) 320 { 321 uint32_t associativity[] = { 322 cpu_to_be32(0x4), /* length */ 323 cpu_to_be32(0x0), cpu_to_be32(0x0), 324 cpu_to_be32(0x0), cpu_to_be32(nodeid) 325 }; 326 char mem_name[32]; 327 uint64_t mem_reg_property[2]; 328 int off; 329 330 mem_reg_property[0] = cpu_to_be64(start); 331 mem_reg_property[1] = cpu_to_be64(size); 332 333 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 334 off = fdt_add_subnode(fdt, 0, mem_name); 335 _FDT(off); 336 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 337 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 338 sizeof(mem_reg_property)))); 339 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 340 sizeof(associativity)))); 341 return off; 342 } 343 344 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 345 { 346 MachineState *machine = MACHINE(spapr); 347 hwaddr mem_start, node_size; 348 int i, nb_nodes = nb_numa_nodes; 349 NodeInfo *nodes = numa_info; 350 NodeInfo ramnode; 351 352 /* No NUMA nodes, assume there is just one node with whole RAM */ 353 if (!nb_numa_nodes) { 354 nb_nodes = 1; 355 ramnode.node_mem = machine->ram_size; 356 nodes = &ramnode; 357 } 358 359 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 360 if (!nodes[i].node_mem) { 361 continue; 362 } 363 if (mem_start >= machine->ram_size) { 364 node_size = 0; 365 } else { 366 node_size = nodes[i].node_mem; 367 if (node_size > machine->ram_size - mem_start) { 368 node_size = machine->ram_size - mem_start; 369 } 370 } 371 if (!mem_start) { 372 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 373 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 374 mem_start += spapr->rma_size; 375 node_size -= spapr->rma_size; 376 } 377 for ( ; node_size; ) { 378 hwaddr sizetmp = pow2floor(node_size); 379 380 /* mem_start != 0 here */ 381 if (ctzl(mem_start) < ctzl(sizetmp)) { 382 sizetmp = 1ULL << ctzl(mem_start); 383 } 384 385 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 386 node_size -= sizetmp; 387 mem_start += sizetmp; 388 } 389 } 390 391 return 0; 392 } 393 394 /* Populate the "ibm,pa-features" property */ 395 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset) 396 { 397 uint8_t pa_features_206[] = { 6, 0, 398 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 399 uint8_t pa_features_207[] = { 24, 0, 400 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 401 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 402 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 403 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 404 uint8_t *pa_features; 405 size_t pa_size; 406 407 switch (env->mmu_model) { 408 case POWERPC_MMU_2_06: 409 case POWERPC_MMU_2_06a: 410 pa_features = pa_features_206; 411 pa_size = sizeof(pa_features_206); 412 break; 413 case POWERPC_MMU_2_07: 414 case POWERPC_MMU_2_07a: 415 pa_features = pa_features_207; 416 pa_size = sizeof(pa_features_207); 417 break; 418 default: 419 return; 420 } 421 422 if (env->ci_large_pages) { 423 /* 424 * Note: we keep CI large pages off by default because a 64K capable 425 * guest provisioned with large pages might otherwise try to map a qemu 426 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 427 * even if that qemu runs on a 4k host. 428 * We dd this bit back here if we are confident this is not an issue 429 */ 430 pa_features[3] |= 0x20; 431 } 432 if (kvmppc_has_cap_htm() && pa_size > 24) { 433 pa_features[24] |= 0x80; /* Transactional memory support */ 434 } 435 436 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 437 } 438 439 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 440 sPAPRMachineState *spapr) 441 { 442 PowerPCCPU *cpu = POWERPC_CPU(cs); 443 CPUPPCState *env = &cpu->env; 444 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 445 int index = ppc_get_vcpu_dt_id(cpu); 446 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 447 0xffffffff, 0xffffffff}; 448 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 449 : SPAPR_TIMEBASE_FREQ; 450 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 451 uint32_t page_sizes_prop[64]; 452 size_t page_sizes_prop_size; 453 uint32_t vcpus_per_socket = smp_threads * smp_cores; 454 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 455 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 456 sPAPRDRConnector *drc; 457 sPAPRDRConnectorClass *drck; 458 int drc_index; 459 460 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index); 461 if (drc) { 462 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 463 drc_index = drck->get_index(drc); 464 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 465 } 466 467 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 468 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 469 470 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 471 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 472 env->dcache_line_size))); 473 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 474 env->dcache_line_size))); 475 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 476 env->icache_line_size))); 477 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 478 env->icache_line_size))); 479 480 if (pcc->l1_dcache_size) { 481 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 482 pcc->l1_dcache_size))); 483 } else { 484 error_report("Warning: Unknown L1 dcache size for cpu"); 485 } 486 if (pcc->l1_icache_size) { 487 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 488 pcc->l1_icache_size))); 489 } else { 490 error_report("Warning: Unknown L1 icache size for cpu"); 491 } 492 493 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 494 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 495 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 496 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 497 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 498 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 499 500 if (env->spr_cb[SPR_PURR].oea_read) { 501 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 502 } 503 504 if (env->mmu_model & POWERPC_MMU_1TSEG) { 505 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 506 segs, sizeof(segs)))); 507 } 508 509 /* Advertise VMX/VSX (vector extensions) if available 510 * 0 / no property == no vector extensions 511 * 1 == VMX / Altivec available 512 * 2 == VSX available */ 513 if (env->insns_flags & PPC_ALTIVEC) { 514 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 515 516 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 517 } 518 519 /* Advertise DFP (Decimal Floating Point) if available 520 * 0 / no property == no DFP 521 * 1 == DFP available */ 522 if (env->insns_flags2 & PPC2_DFP) { 523 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 524 } 525 526 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 527 sizeof(page_sizes_prop)); 528 if (page_sizes_prop_size) { 529 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 530 page_sizes_prop, page_sizes_prop_size))); 531 } 532 533 spapr_populate_pa_features(env, fdt, offset); 534 535 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 536 cs->cpu_index / vcpus_per_socket))); 537 538 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 539 pft_size_prop, sizeof(pft_size_prop)))); 540 541 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); 542 543 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 544 } 545 546 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 547 { 548 CPUState *cs; 549 int cpus_offset; 550 char *nodename; 551 int smt = kvmppc_smt_threads(); 552 553 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 554 _FDT(cpus_offset); 555 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 556 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 557 558 /* 559 * We walk the CPUs in reverse order to ensure that CPU DT nodes 560 * created by fdt_add_subnode() end up in the right order in FDT 561 * for the guest kernel the enumerate the CPUs correctly. 562 */ 563 CPU_FOREACH_REVERSE(cs) { 564 PowerPCCPU *cpu = POWERPC_CPU(cs); 565 int index = ppc_get_vcpu_dt_id(cpu); 566 DeviceClass *dc = DEVICE_GET_CLASS(cs); 567 int offset; 568 569 if ((index % smt) != 0) { 570 continue; 571 } 572 573 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 574 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 575 g_free(nodename); 576 _FDT(offset); 577 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 578 } 579 580 } 581 582 /* 583 * Adds ibm,dynamic-reconfiguration-memory node. 584 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 585 * of this device tree node. 586 */ 587 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 588 { 589 MachineState *machine = MACHINE(spapr); 590 int ret, i, offset; 591 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 592 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 593 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 594 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 595 memory_region_size(&spapr->hotplug_memory.mr)) / 596 lmb_size; 597 uint32_t *int_buf, *cur_index, buf_len; 598 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 599 600 /* 601 * Don't create the node if there is no hotpluggable memory 602 */ 603 if (machine->ram_size == machine->maxram_size) { 604 return 0; 605 } 606 607 /* 608 * Allocate enough buffer size to fit in ibm,dynamic-memory 609 * or ibm,associativity-lookup-arrays 610 */ 611 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 612 * sizeof(uint32_t); 613 cur_index = int_buf = g_malloc0(buf_len); 614 615 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 616 617 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 618 sizeof(prop_lmb_size)); 619 if (ret < 0) { 620 goto out; 621 } 622 623 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 624 if (ret < 0) { 625 goto out; 626 } 627 628 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 629 if (ret < 0) { 630 goto out; 631 } 632 633 /* ibm,dynamic-memory */ 634 int_buf[0] = cpu_to_be32(nr_lmbs); 635 cur_index++; 636 for (i = 0; i < nr_lmbs; i++) { 637 uint64_t addr = i * lmb_size; 638 uint32_t *dynamic_memory = cur_index; 639 640 if (i >= hotplug_lmb_start) { 641 sPAPRDRConnector *drc; 642 sPAPRDRConnectorClass *drck; 643 644 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i); 645 g_assert(drc); 646 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 647 648 dynamic_memory[0] = cpu_to_be32(addr >> 32); 649 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 650 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); 651 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 652 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 653 if (memory_region_present(get_system_memory(), addr)) { 654 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 655 } else { 656 dynamic_memory[5] = cpu_to_be32(0); 657 } 658 } else { 659 /* 660 * LMB information for RMA, boot time RAM and gap b/n RAM and 661 * hotplug memory region -- all these are marked as reserved 662 * and as having no valid DRC. 663 */ 664 dynamic_memory[0] = cpu_to_be32(addr >> 32); 665 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 666 dynamic_memory[2] = cpu_to_be32(0); 667 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 668 dynamic_memory[4] = cpu_to_be32(-1); 669 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 670 SPAPR_LMB_FLAGS_DRC_INVALID); 671 } 672 673 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 674 } 675 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 676 if (ret < 0) { 677 goto out; 678 } 679 680 /* ibm,associativity-lookup-arrays */ 681 cur_index = int_buf; 682 int_buf[0] = cpu_to_be32(nr_nodes); 683 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 684 cur_index += 2; 685 for (i = 0; i < nr_nodes; i++) { 686 uint32_t associativity[] = { 687 cpu_to_be32(0x0), 688 cpu_to_be32(0x0), 689 cpu_to_be32(0x0), 690 cpu_to_be32(i) 691 }; 692 memcpy(cur_index, associativity, sizeof(associativity)); 693 cur_index += 4; 694 } 695 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 696 (cur_index - int_buf) * sizeof(uint32_t)); 697 out: 698 g_free(int_buf); 699 return ret; 700 } 701 702 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 703 sPAPROptionVector *ov5_updates) 704 { 705 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 706 int ret = 0, offset; 707 708 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 709 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 710 g_assert(smc->dr_lmb_enabled); 711 ret = spapr_populate_drconf_memory(spapr, fdt); 712 if (ret) { 713 goto out; 714 } 715 } 716 717 offset = fdt_path_offset(fdt, "/chosen"); 718 if (offset < 0) { 719 offset = fdt_add_subnode(fdt, 0, "chosen"); 720 if (offset < 0) { 721 return offset; 722 } 723 } 724 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 725 "ibm,architecture-vec-5"); 726 727 out: 728 return ret; 729 } 730 731 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 732 target_ulong addr, target_ulong size, 733 sPAPROptionVector *ov5_updates) 734 { 735 void *fdt, *fdt_skel; 736 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 737 738 size -= sizeof(hdr); 739 740 /* Create sceleton */ 741 fdt_skel = g_malloc0(size); 742 _FDT((fdt_create(fdt_skel, size))); 743 _FDT((fdt_begin_node(fdt_skel, ""))); 744 _FDT((fdt_end_node(fdt_skel))); 745 _FDT((fdt_finish(fdt_skel))); 746 fdt = g_malloc0(size); 747 _FDT((fdt_open_into(fdt_skel, fdt, size))); 748 g_free(fdt_skel); 749 750 /* Fixup cpu nodes */ 751 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 752 753 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 754 return -1; 755 } 756 757 /* Pack resulting tree */ 758 _FDT((fdt_pack(fdt))); 759 760 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 761 trace_spapr_cas_failed(size); 762 return -1; 763 } 764 765 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 766 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 767 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 768 g_free(fdt); 769 770 return 0; 771 } 772 773 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 774 { 775 int rtas; 776 GString *hypertas = g_string_sized_new(256); 777 GString *qemu_hypertas = g_string_sized_new(256); 778 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 779 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 780 memory_region_size(&spapr->hotplug_memory.mr); 781 uint32_t lrdr_capacity[] = { 782 cpu_to_be32(max_hotplug_addr >> 32), 783 cpu_to_be32(max_hotplug_addr & 0xffffffff), 784 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 785 cpu_to_be32(max_cpus / smp_threads), 786 }; 787 788 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 789 790 /* hypertas */ 791 add_str(hypertas, "hcall-pft"); 792 add_str(hypertas, "hcall-term"); 793 add_str(hypertas, "hcall-dabr"); 794 add_str(hypertas, "hcall-interrupt"); 795 add_str(hypertas, "hcall-tce"); 796 add_str(hypertas, "hcall-vio"); 797 add_str(hypertas, "hcall-splpar"); 798 add_str(hypertas, "hcall-bulk"); 799 add_str(hypertas, "hcall-set-mode"); 800 add_str(hypertas, "hcall-sprg0"); 801 add_str(hypertas, "hcall-copy"); 802 add_str(hypertas, "hcall-debug"); 803 add_str(qemu_hypertas, "hcall-memop1"); 804 805 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 806 add_str(hypertas, "hcall-multi-tce"); 807 } 808 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 809 hypertas->str, hypertas->len)); 810 g_string_free(hypertas, TRUE); 811 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 812 qemu_hypertas->str, qemu_hypertas->len)); 813 g_string_free(qemu_hypertas, TRUE); 814 815 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 816 refpoints, sizeof(refpoints))); 817 818 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 819 RTAS_ERROR_LOG_MAX)); 820 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 821 RTAS_EVENT_SCAN_RATE)); 822 823 if (msi_nonbroken) { 824 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 825 } 826 827 /* 828 * According to PAPR, rtas ibm,os-term does not guarantee a return 829 * back to the guest cpu. 830 * 831 * While an additional ibm,extended-os-term property indicates 832 * that rtas call return will always occur. Set this property. 833 */ 834 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 835 836 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 837 lrdr_capacity, sizeof(lrdr_capacity))); 838 839 spapr_dt_rtas_tokens(fdt, rtas); 840 } 841 842 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 843 { 844 MachineState *machine = MACHINE(spapr); 845 int chosen; 846 const char *boot_device = machine->boot_order; 847 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 848 size_t cb = 0; 849 char *bootlist = get_boot_devices_list(&cb, true); 850 851 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 852 853 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 854 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 855 spapr->initrd_base)); 856 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 857 spapr->initrd_base + spapr->initrd_size)); 858 859 if (spapr->kernel_size) { 860 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 861 cpu_to_be64(spapr->kernel_size) }; 862 863 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 864 &kprop, sizeof(kprop))); 865 if (spapr->kernel_le) { 866 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 867 } 868 } 869 if (boot_menu) { 870 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 871 } 872 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 873 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 874 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 875 876 if (cb && bootlist) { 877 int i; 878 879 for (i = 0; i < cb; i++) { 880 if (bootlist[i] == '\n') { 881 bootlist[i] = ' '; 882 } 883 } 884 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 885 } 886 887 if (boot_device && strlen(boot_device)) { 888 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 889 } 890 891 if (!spapr->has_graphics && stdout_path) { 892 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 893 } 894 895 g_free(stdout_path); 896 g_free(bootlist); 897 } 898 899 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 900 { 901 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 902 * KVM to work under pHyp with some guest co-operation */ 903 int hypervisor; 904 uint8_t hypercall[16]; 905 906 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 907 /* indicate KVM hypercall interface */ 908 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 909 if (kvmppc_has_cap_fixup_hcalls()) { 910 /* 911 * Older KVM versions with older guest kernels were broken 912 * with the magic page, don't allow the guest to map it. 913 */ 914 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 915 sizeof(hypercall))) { 916 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 917 hypercall, sizeof(hypercall))); 918 } 919 } 920 } 921 922 static void *spapr_build_fdt(sPAPRMachineState *spapr, 923 hwaddr rtas_addr, 924 hwaddr rtas_size) 925 { 926 MachineState *machine = MACHINE(qdev_get_machine()); 927 MachineClass *mc = MACHINE_GET_CLASS(machine); 928 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 929 int ret; 930 void *fdt; 931 sPAPRPHBState *phb; 932 char *buf; 933 934 fdt = g_malloc0(FDT_MAX_SIZE); 935 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 936 937 /* Root node */ 938 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 939 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 940 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 941 942 /* 943 * Add info to guest to indentify which host is it being run on 944 * and what is the uuid of the guest 945 */ 946 if (kvmppc_get_host_model(&buf)) { 947 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 948 g_free(buf); 949 } 950 if (kvmppc_get_host_serial(&buf)) { 951 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 952 g_free(buf); 953 } 954 955 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 956 957 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 958 if (qemu_uuid_set) { 959 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 960 } 961 g_free(buf); 962 963 if (qemu_get_vm_name()) { 964 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 965 qemu_get_vm_name())); 966 } 967 968 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 969 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 970 971 /* /interrupt controller */ 972 spapr_dt_xics(spapr->nr_servers, fdt, PHANDLE_XICP); 973 974 ret = spapr_populate_memory(spapr, fdt); 975 if (ret < 0) { 976 error_report("couldn't setup memory nodes in fdt"); 977 exit(1); 978 } 979 980 /* /vdevice */ 981 spapr_dt_vdevice(spapr->vio_bus, fdt); 982 983 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 984 ret = spapr_rng_populate_dt(fdt); 985 if (ret < 0) { 986 error_report("could not set up rng device in the fdt"); 987 exit(1); 988 } 989 } 990 991 QLIST_FOREACH(phb, &spapr->phbs, list) { 992 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 993 if (ret < 0) { 994 error_report("couldn't setup PCI devices in fdt"); 995 exit(1); 996 } 997 } 998 999 /* cpus */ 1000 spapr_populate_cpus_dt_node(fdt, spapr); 1001 1002 if (smc->dr_lmb_enabled) { 1003 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1004 } 1005 1006 if (mc->has_hotpluggable_cpus) { 1007 int offset = fdt_path_offset(fdt, "/cpus"); 1008 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1009 SPAPR_DR_CONNECTOR_TYPE_CPU); 1010 if (ret < 0) { 1011 error_report("Couldn't set up CPU DR device tree properties"); 1012 exit(1); 1013 } 1014 } 1015 1016 /* /event-sources */ 1017 spapr_dt_events(spapr, fdt); 1018 1019 /* /rtas */ 1020 spapr_dt_rtas(spapr, fdt); 1021 1022 /* /chosen */ 1023 spapr_dt_chosen(spapr, fdt); 1024 1025 /* /hypervisor */ 1026 if (kvm_enabled()) { 1027 spapr_dt_hypervisor(spapr, fdt); 1028 } 1029 1030 /* Build memory reserve map */ 1031 if (spapr->kernel_size) { 1032 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1033 } 1034 if (spapr->initrd_size) { 1035 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1036 } 1037 1038 /* ibm,client-architecture-support updates */ 1039 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1040 if (ret < 0) { 1041 error_report("couldn't setup CAS properties fdt"); 1042 exit(1); 1043 } 1044 1045 return fdt; 1046 } 1047 1048 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1049 { 1050 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1051 } 1052 1053 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1054 PowerPCCPU *cpu) 1055 { 1056 CPUPPCState *env = &cpu->env; 1057 1058 /* The TCG path should also be holding the BQL at this point */ 1059 g_assert(qemu_mutex_iothread_locked()); 1060 1061 if (msr_pr) { 1062 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1063 env->gpr[3] = H_PRIVILEGE; 1064 } else { 1065 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1066 } 1067 } 1068 1069 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1070 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1071 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1072 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1073 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1074 1075 /* 1076 * Get the fd to access the kernel htab, re-opening it if necessary 1077 */ 1078 static int get_htab_fd(sPAPRMachineState *spapr) 1079 { 1080 if (spapr->htab_fd >= 0) { 1081 return spapr->htab_fd; 1082 } 1083 1084 spapr->htab_fd = kvmppc_get_htab_fd(false); 1085 if (spapr->htab_fd < 0) { 1086 error_report("Unable to open fd for reading hash table from KVM: %s", 1087 strerror(errno)); 1088 } 1089 1090 return spapr->htab_fd; 1091 } 1092 1093 static void close_htab_fd(sPAPRMachineState *spapr) 1094 { 1095 if (spapr->htab_fd >= 0) { 1096 close(spapr->htab_fd); 1097 } 1098 spapr->htab_fd = -1; 1099 } 1100 1101 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1102 { 1103 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1104 1105 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1106 } 1107 1108 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1109 hwaddr ptex, int n) 1110 { 1111 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1112 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1113 1114 if (!spapr->htab) { 1115 /* 1116 * HTAB is controlled by KVM. Fetch into temporary buffer 1117 */ 1118 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1119 kvmppc_read_hptes(hptes, ptex, n); 1120 return hptes; 1121 } 1122 1123 /* 1124 * HTAB is controlled by QEMU. Just point to the internally 1125 * accessible PTEG. 1126 */ 1127 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1128 } 1129 1130 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1131 const ppc_hash_pte64_t *hptes, 1132 hwaddr ptex, int n) 1133 { 1134 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1135 1136 if (!spapr->htab) { 1137 g_free((void *)hptes); 1138 } 1139 1140 /* Nothing to do for qemu managed HPT */ 1141 } 1142 1143 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1144 uint64_t pte0, uint64_t pte1) 1145 { 1146 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1147 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1148 1149 if (!spapr->htab) { 1150 kvmppc_write_hpte(ptex, pte0, pte1); 1151 } else { 1152 stq_p(spapr->htab + offset, pte0); 1153 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1154 } 1155 } 1156 1157 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1158 { 1159 int shift; 1160 1161 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1162 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1163 * that's much more than is needed for Linux guests */ 1164 shift = ctz64(pow2ceil(ramsize)) - 7; 1165 shift = MAX(shift, 18); /* Minimum architected size */ 1166 shift = MIN(shift, 46); /* Maximum architected size */ 1167 return shift; 1168 } 1169 1170 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1171 Error **errp) 1172 { 1173 long rc; 1174 1175 /* Clean up any HPT info from a previous boot */ 1176 g_free(spapr->htab); 1177 spapr->htab = NULL; 1178 spapr->htab_shift = 0; 1179 close_htab_fd(spapr); 1180 1181 rc = kvmppc_reset_htab(shift); 1182 if (rc < 0) { 1183 /* kernel-side HPT needed, but couldn't allocate one */ 1184 error_setg_errno(errp, errno, 1185 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1186 shift); 1187 /* This is almost certainly fatal, but if the caller really 1188 * wants to carry on with shift == 0, it's welcome to try */ 1189 } else if (rc > 0) { 1190 /* kernel-side HPT allocated */ 1191 if (rc != shift) { 1192 error_setg(errp, 1193 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1194 shift, rc); 1195 } 1196 1197 spapr->htab_shift = shift; 1198 spapr->htab = NULL; 1199 } else { 1200 /* kernel-side HPT not needed, allocate in userspace instead */ 1201 size_t size = 1ULL << shift; 1202 int i; 1203 1204 spapr->htab = qemu_memalign(size, size); 1205 if (!spapr->htab) { 1206 error_setg_errno(errp, errno, 1207 "Could not allocate HPT of order %d", shift); 1208 return; 1209 } 1210 1211 memset(spapr->htab, 0, size); 1212 spapr->htab_shift = shift; 1213 1214 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1215 DIRTY_HPTE(HPTE(spapr->htab, i)); 1216 } 1217 } 1218 } 1219 1220 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1221 { 1222 bool matched = false; 1223 1224 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1225 matched = true; 1226 } 1227 1228 if (!matched) { 1229 error_report("Device %s is not supported by this machine yet.", 1230 qdev_fw_name(DEVICE(sbdev))); 1231 exit(1); 1232 } 1233 } 1234 1235 static void ppc_spapr_reset(void) 1236 { 1237 MachineState *machine = MACHINE(qdev_get_machine()); 1238 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1239 PowerPCCPU *first_ppc_cpu; 1240 uint32_t rtas_limit; 1241 hwaddr rtas_addr, fdt_addr; 1242 void *fdt; 1243 int rc; 1244 1245 /* Check for unknown sysbus devices */ 1246 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1247 1248 /* Allocate and/or reset the hash page table */ 1249 spapr_reallocate_hpt(spapr, 1250 spapr_hpt_shift_for_ramsize(machine->maxram_size), 1251 &error_fatal); 1252 1253 /* Update the RMA size if necessary */ 1254 if (spapr->vrma_adjust) { 1255 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1256 spapr->htab_shift); 1257 } 1258 1259 qemu_devices_reset(); 1260 1261 /* 1262 * We place the device tree and RTAS just below either the top of the RMA, 1263 * or just below 2GB, whichever is lowere, so that it can be 1264 * processed with 32-bit real mode code if necessary 1265 */ 1266 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1267 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1268 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1269 1270 /* if this reset wasn't generated by CAS, we should reset our 1271 * negotiated options and start from scratch */ 1272 if (!spapr->cas_reboot) { 1273 spapr_ovec_cleanup(spapr->ov5_cas); 1274 spapr->ov5_cas = spapr_ovec_new(); 1275 } 1276 1277 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1278 1279 spapr_load_rtas(spapr, fdt, rtas_addr); 1280 1281 rc = fdt_pack(fdt); 1282 1283 /* Should only fail if we've built a corrupted tree */ 1284 assert(rc == 0); 1285 1286 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1287 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1288 fdt_totalsize(fdt), FDT_MAX_SIZE); 1289 exit(1); 1290 } 1291 1292 /* Load the fdt */ 1293 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1294 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1295 g_free(fdt); 1296 1297 /* Set up the entry state */ 1298 first_ppc_cpu = POWERPC_CPU(first_cpu); 1299 first_ppc_cpu->env.gpr[3] = fdt_addr; 1300 first_ppc_cpu->env.gpr[5] = 0; 1301 first_cpu->halted = 0; 1302 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1303 1304 spapr->cas_reboot = false; 1305 } 1306 1307 static void spapr_create_nvram(sPAPRMachineState *spapr) 1308 { 1309 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1310 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1311 1312 if (dinfo) { 1313 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1314 &error_fatal); 1315 } 1316 1317 qdev_init_nofail(dev); 1318 1319 spapr->nvram = (struct sPAPRNVRAM *)dev; 1320 } 1321 1322 static void spapr_rtc_create(sPAPRMachineState *spapr) 1323 { 1324 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); 1325 1326 qdev_init_nofail(dev); 1327 spapr->rtc = dev; 1328 1329 object_property_add_alias(qdev_get_machine(), "rtc-time", 1330 OBJECT(spapr->rtc), "date", NULL); 1331 } 1332 1333 /* Returns whether we want to use VGA or not */ 1334 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1335 { 1336 switch (vga_interface_type) { 1337 case VGA_NONE: 1338 return false; 1339 case VGA_DEVICE: 1340 return true; 1341 case VGA_STD: 1342 case VGA_VIRTIO: 1343 return pci_vga_init(pci_bus) != NULL; 1344 default: 1345 error_setg(errp, 1346 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1347 return false; 1348 } 1349 } 1350 1351 static int spapr_post_load(void *opaque, int version_id) 1352 { 1353 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1354 int err = 0; 1355 1356 /* In earlier versions, there was no separate qdev for the PAPR 1357 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1358 * So when migrating from those versions, poke the incoming offset 1359 * value into the RTC device */ 1360 if (version_id < 3) { 1361 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); 1362 } 1363 1364 return err; 1365 } 1366 1367 static bool version_before_3(void *opaque, int version_id) 1368 { 1369 return version_id < 3; 1370 } 1371 1372 static bool spapr_ov5_cas_needed(void *opaque) 1373 { 1374 sPAPRMachineState *spapr = opaque; 1375 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1376 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1377 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1378 bool cas_needed; 1379 1380 /* Prior to the introduction of sPAPROptionVector, we had two option 1381 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1382 * Both of these options encode machine topology into the device-tree 1383 * in such a way that the now-booted OS should still be able to interact 1384 * appropriately with QEMU regardless of what options were actually 1385 * negotiatied on the source side. 1386 * 1387 * As such, we can avoid migrating the CAS-negotiated options if these 1388 * are the only options available on the current machine/platform. 1389 * Since these are the only options available for pseries-2.7 and 1390 * earlier, this allows us to maintain old->new/new->old migration 1391 * compatibility. 1392 * 1393 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1394 * via default pseries-2.8 machines and explicit command-line parameters. 1395 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1396 * of the actual CAS-negotiated values to continue working properly. For 1397 * example, availability of memory unplug depends on knowing whether 1398 * OV5_HP_EVT was negotiated via CAS. 1399 * 1400 * Thus, for any cases where the set of available CAS-negotiatable 1401 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1402 * include the CAS-negotiated options in the migration stream. 1403 */ 1404 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1405 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1406 1407 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1408 * the mask itself since in the future it's possible "legacy" bits may be 1409 * removed via machine options, which could generate a false positive 1410 * that breaks migration. 1411 */ 1412 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1413 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1414 1415 spapr_ovec_cleanup(ov5_mask); 1416 spapr_ovec_cleanup(ov5_legacy); 1417 spapr_ovec_cleanup(ov5_removed); 1418 1419 return cas_needed; 1420 } 1421 1422 static const VMStateDescription vmstate_spapr_ov5_cas = { 1423 .name = "spapr_option_vector_ov5_cas", 1424 .version_id = 1, 1425 .minimum_version_id = 1, 1426 .needed = spapr_ov5_cas_needed, 1427 .fields = (VMStateField[]) { 1428 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1429 vmstate_spapr_ovec, sPAPROptionVector), 1430 VMSTATE_END_OF_LIST() 1431 }, 1432 }; 1433 1434 static const VMStateDescription vmstate_spapr = { 1435 .name = "spapr", 1436 .version_id = 3, 1437 .minimum_version_id = 1, 1438 .post_load = spapr_post_load, 1439 .fields = (VMStateField[]) { 1440 /* used to be @next_irq */ 1441 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1442 1443 /* RTC offset */ 1444 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1445 1446 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1447 VMSTATE_END_OF_LIST() 1448 }, 1449 .subsections = (const VMStateDescription*[]) { 1450 &vmstate_spapr_ov5_cas, 1451 NULL 1452 } 1453 }; 1454 1455 static int htab_save_setup(QEMUFile *f, void *opaque) 1456 { 1457 sPAPRMachineState *spapr = opaque; 1458 1459 /* "Iteration" header */ 1460 qemu_put_be32(f, spapr->htab_shift); 1461 1462 if (spapr->htab) { 1463 spapr->htab_save_index = 0; 1464 spapr->htab_first_pass = true; 1465 } else { 1466 assert(kvm_enabled()); 1467 } 1468 1469 1470 return 0; 1471 } 1472 1473 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1474 int64_t max_ns) 1475 { 1476 bool has_timeout = max_ns != -1; 1477 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1478 int index = spapr->htab_save_index; 1479 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1480 1481 assert(spapr->htab_first_pass); 1482 1483 do { 1484 int chunkstart; 1485 1486 /* Consume invalid HPTEs */ 1487 while ((index < htabslots) 1488 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1489 index++; 1490 CLEAN_HPTE(HPTE(spapr->htab, index)); 1491 } 1492 1493 /* Consume valid HPTEs */ 1494 chunkstart = index; 1495 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1496 && HPTE_VALID(HPTE(spapr->htab, index))) { 1497 index++; 1498 CLEAN_HPTE(HPTE(spapr->htab, index)); 1499 } 1500 1501 if (index > chunkstart) { 1502 int n_valid = index - chunkstart; 1503 1504 qemu_put_be32(f, chunkstart); 1505 qemu_put_be16(f, n_valid); 1506 qemu_put_be16(f, 0); 1507 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1508 HASH_PTE_SIZE_64 * n_valid); 1509 1510 if (has_timeout && 1511 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1512 break; 1513 } 1514 } 1515 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1516 1517 if (index >= htabslots) { 1518 assert(index == htabslots); 1519 index = 0; 1520 spapr->htab_first_pass = false; 1521 } 1522 spapr->htab_save_index = index; 1523 } 1524 1525 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1526 int64_t max_ns) 1527 { 1528 bool final = max_ns < 0; 1529 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1530 int examined = 0, sent = 0; 1531 int index = spapr->htab_save_index; 1532 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1533 1534 assert(!spapr->htab_first_pass); 1535 1536 do { 1537 int chunkstart, invalidstart; 1538 1539 /* Consume non-dirty HPTEs */ 1540 while ((index < htabslots) 1541 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1542 index++; 1543 examined++; 1544 } 1545 1546 chunkstart = index; 1547 /* Consume valid dirty HPTEs */ 1548 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1549 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1550 && HPTE_VALID(HPTE(spapr->htab, index))) { 1551 CLEAN_HPTE(HPTE(spapr->htab, index)); 1552 index++; 1553 examined++; 1554 } 1555 1556 invalidstart = index; 1557 /* Consume invalid dirty HPTEs */ 1558 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1559 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1560 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1561 CLEAN_HPTE(HPTE(spapr->htab, index)); 1562 index++; 1563 examined++; 1564 } 1565 1566 if (index > chunkstart) { 1567 int n_valid = invalidstart - chunkstart; 1568 int n_invalid = index - invalidstart; 1569 1570 qemu_put_be32(f, chunkstart); 1571 qemu_put_be16(f, n_valid); 1572 qemu_put_be16(f, n_invalid); 1573 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1574 HASH_PTE_SIZE_64 * n_valid); 1575 sent += index - chunkstart; 1576 1577 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1578 break; 1579 } 1580 } 1581 1582 if (examined >= htabslots) { 1583 break; 1584 } 1585 1586 if (index >= htabslots) { 1587 assert(index == htabslots); 1588 index = 0; 1589 } 1590 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1591 1592 if (index >= htabslots) { 1593 assert(index == htabslots); 1594 index = 0; 1595 } 1596 1597 spapr->htab_save_index = index; 1598 1599 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1600 } 1601 1602 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1603 #define MAX_KVM_BUF_SIZE 2048 1604 1605 static int htab_save_iterate(QEMUFile *f, void *opaque) 1606 { 1607 sPAPRMachineState *spapr = opaque; 1608 int fd; 1609 int rc = 0; 1610 1611 /* Iteration header */ 1612 qemu_put_be32(f, 0); 1613 1614 if (!spapr->htab) { 1615 assert(kvm_enabled()); 1616 1617 fd = get_htab_fd(spapr); 1618 if (fd < 0) { 1619 return fd; 1620 } 1621 1622 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1623 if (rc < 0) { 1624 return rc; 1625 } 1626 } else if (spapr->htab_first_pass) { 1627 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1628 } else { 1629 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1630 } 1631 1632 /* End marker */ 1633 qemu_put_be32(f, 0); 1634 qemu_put_be16(f, 0); 1635 qemu_put_be16(f, 0); 1636 1637 return rc; 1638 } 1639 1640 static int htab_save_complete(QEMUFile *f, void *opaque) 1641 { 1642 sPAPRMachineState *spapr = opaque; 1643 int fd; 1644 1645 /* Iteration header */ 1646 qemu_put_be32(f, 0); 1647 1648 if (!spapr->htab) { 1649 int rc; 1650 1651 assert(kvm_enabled()); 1652 1653 fd = get_htab_fd(spapr); 1654 if (fd < 0) { 1655 return fd; 1656 } 1657 1658 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1659 if (rc < 0) { 1660 return rc; 1661 } 1662 } else { 1663 if (spapr->htab_first_pass) { 1664 htab_save_first_pass(f, spapr, -1); 1665 } 1666 htab_save_later_pass(f, spapr, -1); 1667 } 1668 1669 /* End marker */ 1670 qemu_put_be32(f, 0); 1671 qemu_put_be16(f, 0); 1672 qemu_put_be16(f, 0); 1673 1674 return 0; 1675 } 1676 1677 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1678 { 1679 sPAPRMachineState *spapr = opaque; 1680 uint32_t section_hdr; 1681 int fd = -1; 1682 1683 if (version_id < 1 || version_id > 1) { 1684 error_report("htab_load() bad version"); 1685 return -EINVAL; 1686 } 1687 1688 section_hdr = qemu_get_be32(f); 1689 1690 if (section_hdr) { 1691 Error *local_err = NULL; 1692 1693 /* First section gives the htab size */ 1694 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1695 if (local_err) { 1696 error_report_err(local_err); 1697 return -EINVAL; 1698 } 1699 return 0; 1700 } 1701 1702 if (!spapr->htab) { 1703 assert(kvm_enabled()); 1704 1705 fd = kvmppc_get_htab_fd(true); 1706 if (fd < 0) { 1707 error_report("Unable to open fd to restore KVM hash table: %s", 1708 strerror(errno)); 1709 } 1710 } 1711 1712 while (true) { 1713 uint32_t index; 1714 uint16_t n_valid, n_invalid; 1715 1716 index = qemu_get_be32(f); 1717 n_valid = qemu_get_be16(f); 1718 n_invalid = qemu_get_be16(f); 1719 1720 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1721 /* End of Stream */ 1722 break; 1723 } 1724 1725 if ((index + n_valid + n_invalid) > 1726 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1727 /* Bad index in stream */ 1728 error_report( 1729 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1730 index, n_valid, n_invalid, spapr->htab_shift); 1731 return -EINVAL; 1732 } 1733 1734 if (spapr->htab) { 1735 if (n_valid) { 1736 qemu_get_buffer(f, HPTE(spapr->htab, index), 1737 HASH_PTE_SIZE_64 * n_valid); 1738 } 1739 if (n_invalid) { 1740 memset(HPTE(spapr->htab, index + n_valid), 0, 1741 HASH_PTE_SIZE_64 * n_invalid); 1742 } 1743 } else { 1744 int rc; 1745 1746 assert(fd >= 0); 1747 1748 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1749 if (rc < 0) { 1750 return rc; 1751 } 1752 } 1753 } 1754 1755 if (!spapr->htab) { 1756 assert(fd >= 0); 1757 close(fd); 1758 } 1759 1760 return 0; 1761 } 1762 1763 static void htab_cleanup(void *opaque) 1764 { 1765 sPAPRMachineState *spapr = opaque; 1766 1767 close_htab_fd(spapr); 1768 } 1769 1770 static SaveVMHandlers savevm_htab_handlers = { 1771 .save_live_setup = htab_save_setup, 1772 .save_live_iterate = htab_save_iterate, 1773 .save_live_complete_precopy = htab_save_complete, 1774 .cleanup = htab_cleanup, 1775 .load_state = htab_load, 1776 }; 1777 1778 static void spapr_boot_set(void *opaque, const char *boot_device, 1779 Error **errp) 1780 { 1781 MachineState *machine = MACHINE(qdev_get_machine()); 1782 machine->boot_order = g_strdup(boot_device); 1783 } 1784 1785 /* 1786 * Reset routine for LMB DR devices. 1787 * 1788 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1789 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1790 * when it walks all its children devices. LMB devices reset occurs 1791 * as part of spapr_ppc_reset(). 1792 */ 1793 static void spapr_drc_reset(void *opaque) 1794 { 1795 sPAPRDRConnector *drc = opaque; 1796 DeviceState *d = DEVICE(drc); 1797 1798 if (d) { 1799 device_reset(d); 1800 } 1801 } 1802 1803 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1804 { 1805 MachineState *machine = MACHINE(spapr); 1806 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1807 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1808 int i; 1809 1810 for (i = 0; i < nr_lmbs; i++) { 1811 sPAPRDRConnector *drc; 1812 uint64_t addr; 1813 1814 addr = i * lmb_size + spapr->hotplug_memory.base; 1815 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, 1816 addr/lmb_size); 1817 qemu_register_reset(spapr_drc_reset, drc); 1818 } 1819 } 1820 1821 /* 1822 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1823 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1824 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1825 */ 1826 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 1827 { 1828 int i; 1829 1830 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1831 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 1832 " is not aligned to %llu MiB", 1833 machine->ram_size, 1834 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1835 return; 1836 } 1837 1838 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1839 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 1840 " is not aligned to %llu MiB", 1841 machine->ram_size, 1842 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1843 return; 1844 } 1845 1846 for (i = 0; i < nb_numa_nodes; i++) { 1847 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 1848 error_setg(errp, 1849 "Node %d memory size 0x%" PRIx64 1850 " is not aligned to %llu MiB", 1851 i, numa_info[i].node_mem, 1852 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1853 return; 1854 } 1855 } 1856 } 1857 1858 /* find cpu slot in machine->possible_cpus by core_id */ 1859 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 1860 { 1861 int index = id / smp_threads; 1862 1863 if (index >= ms->possible_cpus->len) { 1864 return NULL; 1865 } 1866 if (idx) { 1867 *idx = index; 1868 } 1869 return &ms->possible_cpus->cpus[index]; 1870 } 1871 1872 static void spapr_init_cpus(sPAPRMachineState *spapr) 1873 { 1874 MachineState *machine = MACHINE(spapr); 1875 MachineClass *mc = MACHINE_GET_CLASS(machine); 1876 char *type = spapr_get_cpu_core_type(machine->cpu_model); 1877 int smt = kvmppc_smt_threads(); 1878 const CPUArchIdList *possible_cpus; 1879 int boot_cores_nr = smp_cpus / smp_threads; 1880 int i; 1881 1882 if (!type) { 1883 error_report("Unable to find sPAPR CPU Core definition"); 1884 exit(1); 1885 } 1886 1887 possible_cpus = mc->possible_cpu_arch_ids(machine); 1888 if (mc->has_hotpluggable_cpus) { 1889 if (smp_cpus % smp_threads) { 1890 error_report("smp_cpus (%u) must be multiple of threads (%u)", 1891 smp_cpus, smp_threads); 1892 exit(1); 1893 } 1894 if (max_cpus % smp_threads) { 1895 error_report("max_cpus (%u) must be multiple of threads (%u)", 1896 max_cpus, smp_threads); 1897 exit(1); 1898 } 1899 } else { 1900 if (max_cpus != smp_cpus) { 1901 error_report("This machine version does not support CPU hotplug"); 1902 exit(1); 1903 } 1904 boot_cores_nr = possible_cpus->len; 1905 } 1906 1907 for (i = 0; i < possible_cpus->len; i++) { 1908 int core_id = i * smp_threads; 1909 1910 if (mc->has_hotpluggable_cpus) { 1911 sPAPRDRConnector *drc = 1912 spapr_dr_connector_new(OBJECT(spapr), 1913 SPAPR_DR_CONNECTOR_TYPE_CPU, 1914 (core_id / smp_threads) * smt); 1915 1916 qemu_register_reset(spapr_drc_reset, drc); 1917 } 1918 1919 if (i < boot_cores_nr) { 1920 Object *core = object_new(type); 1921 int nr_threads = smp_threads; 1922 1923 /* Handle the partially filled core for older machine types */ 1924 if ((i + 1) * smp_threads >= smp_cpus) { 1925 nr_threads = smp_cpus - i * smp_threads; 1926 } 1927 1928 object_property_set_int(core, nr_threads, "nr-threads", 1929 &error_fatal); 1930 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 1931 &error_fatal); 1932 object_property_set_bool(core, true, "realized", &error_fatal); 1933 } 1934 } 1935 g_free(type); 1936 } 1937 1938 /* pSeries LPAR / sPAPR hardware init */ 1939 static void ppc_spapr_init(MachineState *machine) 1940 { 1941 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1942 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1943 const char *kernel_filename = machine->kernel_filename; 1944 const char *initrd_filename = machine->initrd_filename; 1945 PCIHostState *phb; 1946 int i; 1947 MemoryRegion *sysmem = get_system_memory(); 1948 MemoryRegion *ram = g_new(MemoryRegion, 1); 1949 MemoryRegion *rma_region; 1950 void *rma = NULL; 1951 hwaddr rma_alloc_size; 1952 hwaddr node0_size = spapr_node0_size(); 1953 long load_limit, fw_size; 1954 char *filename; 1955 int smt = kvmppc_smt_threads(); 1956 1957 msi_nonbroken = true; 1958 1959 QLIST_INIT(&spapr->phbs); 1960 1961 /* Allocate RMA if necessary */ 1962 rma_alloc_size = kvmppc_alloc_rma(&rma); 1963 1964 if (rma_alloc_size == -1) { 1965 error_report("Unable to create RMA"); 1966 exit(1); 1967 } 1968 1969 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1970 spapr->rma_size = rma_alloc_size; 1971 } else { 1972 spapr->rma_size = node0_size; 1973 1974 /* With KVM, we don't actually know whether KVM supports an 1975 * unbounded RMA (PR KVM) or is limited by the hash table size 1976 * (HV KVM using VRMA), so we always assume the latter 1977 * 1978 * In that case, we also limit the initial allocations for RTAS 1979 * etc... to 256M since we have no way to know what the VRMA size 1980 * is going to be as it depends on the size of the hash table 1981 * isn't determined yet. 1982 */ 1983 if (kvm_enabled()) { 1984 spapr->vrma_adjust = 1; 1985 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1986 } 1987 1988 /* Actually we don't support unbounded RMA anymore since we 1989 * added proper emulation of HV mode. The max we can get is 1990 * 16G which also happens to be what we configure for PAPR 1991 * mode so make sure we don't do anything bigger than that 1992 */ 1993 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 1994 } 1995 1996 if (spapr->rma_size > node0_size) { 1997 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 1998 spapr->rma_size); 1999 exit(1); 2000 } 2001 2002 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2003 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2004 2005 /* Set up Interrupt Controller before we create the VCPUs */ 2006 spapr->xics = xics_system_init(machine, 2007 DIV_ROUND_UP(max_cpus * smt, smp_threads), 2008 XICS_IRQS_SPAPR, &error_fatal); 2009 2010 /* Set up containers for ibm,client-set-architecture negotiated options */ 2011 spapr->ov5 = spapr_ovec_new(); 2012 spapr->ov5_cas = spapr_ovec_new(); 2013 2014 if (smc->dr_lmb_enabled) { 2015 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2016 spapr_validate_node_memory(machine, &error_fatal); 2017 } 2018 2019 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2020 2021 /* advertise support for dedicated HP event source to guests */ 2022 if (spapr->use_hotplug_event_source) { 2023 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2024 } 2025 2026 /* init CPUs */ 2027 if (machine->cpu_model == NULL) { 2028 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; 2029 } 2030 2031 ppc_cpu_parse_features(machine->cpu_model); 2032 2033 spapr_init_cpus(spapr); 2034 2035 if (kvm_enabled()) { 2036 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2037 kvmppc_enable_logical_ci_hcalls(); 2038 kvmppc_enable_set_mode_hcall(); 2039 2040 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2041 kvmppc_enable_clear_ref_mod_hcalls(); 2042 } 2043 2044 /* allocate RAM */ 2045 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2046 machine->ram_size); 2047 memory_region_add_subregion(sysmem, 0, ram); 2048 2049 if (rma_alloc_size && rma) { 2050 rma_region = g_new(MemoryRegion, 1); 2051 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 2052 rma_alloc_size, rma); 2053 vmstate_register_ram_global(rma_region); 2054 memory_region_add_subregion(sysmem, 0, rma_region); 2055 } 2056 2057 /* initialize hotplug memory address space */ 2058 if (machine->ram_size < machine->maxram_size) { 2059 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2060 /* 2061 * Limit the number of hotpluggable memory slots to half the number 2062 * slots that KVM supports, leaving the other half for PCI and other 2063 * devices. However ensure that number of slots doesn't drop below 32. 2064 */ 2065 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2066 SPAPR_MAX_RAM_SLOTS; 2067 2068 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2069 max_memslots = SPAPR_MAX_RAM_SLOTS; 2070 } 2071 if (machine->ram_slots > max_memslots) { 2072 error_report("Specified number of memory slots %" 2073 PRIu64" exceeds max supported %d", 2074 machine->ram_slots, max_memslots); 2075 exit(1); 2076 } 2077 2078 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2079 SPAPR_HOTPLUG_MEM_ALIGN); 2080 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2081 "hotplug-memory", hotplug_mem_size); 2082 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2083 &spapr->hotplug_memory.mr); 2084 } 2085 2086 if (smc->dr_lmb_enabled) { 2087 spapr_create_lmb_dr_connectors(spapr); 2088 } 2089 2090 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2091 if (!filename) { 2092 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2093 exit(1); 2094 } 2095 spapr->rtas_size = get_image_size(filename); 2096 if (spapr->rtas_size < 0) { 2097 error_report("Could not get size of LPAR rtas '%s'", filename); 2098 exit(1); 2099 } 2100 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2101 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2102 error_report("Could not load LPAR rtas '%s'", filename); 2103 exit(1); 2104 } 2105 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2106 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2107 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2108 exit(1); 2109 } 2110 g_free(filename); 2111 2112 /* Set up RTAS event infrastructure */ 2113 spapr_events_init(spapr); 2114 2115 /* Set up the RTC RTAS interfaces */ 2116 spapr_rtc_create(spapr); 2117 2118 /* Set up VIO bus */ 2119 spapr->vio_bus = spapr_vio_bus_init(); 2120 2121 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 2122 if (serial_hds[i]) { 2123 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 2124 } 2125 } 2126 2127 /* We always have at least the nvram device on VIO */ 2128 spapr_create_nvram(spapr); 2129 2130 /* Set up PCI */ 2131 spapr_pci_rtas_init(); 2132 2133 phb = spapr_create_phb(spapr, 0); 2134 2135 for (i = 0; i < nb_nics; i++) { 2136 NICInfo *nd = &nd_table[i]; 2137 2138 if (!nd->model) { 2139 nd->model = g_strdup("ibmveth"); 2140 } 2141 2142 if (strcmp(nd->model, "ibmveth") == 0) { 2143 spapr_vlan_create(spapr->vio_bus, nd); 2144 } else { 2145 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2146 } 2147 } 2148 2149 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2150 spapr_vscsi_create(spapr->vio_bus); 2151 } 2152 2153 /* Graphics */ 2154 if (spapr_vga_init(phb->bus, &error_fatal)) { 2155 spapr->has_graphics = true; 2156 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2157 } 2158 2159 if (machine->usb) { 2160 if (smc->use_ohci_by_default) { 2161 pci_create_simple(phb->bus, -1, "pci-ohci"); 2162 } else { 2163 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2164 } 2165 2166 if (spapr->has_graphics) { 2167 USBBus *usb_bus = usb_bus_find(-1); 2168 2169 usb_create_simple(usb_bus, "usb-kbd"); 2170 usb_create_simple(usb_bus, "usb-mouse"); 2171 } 2172 } 2173 2174 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2175 error_report( 2176 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2177 MIN_RMA_SLOF); 2178 exit(1); 2179 } 2180 2181 if (kernel_filename) { 2182 uint64_t lowaddr = 0; 2183 2184 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2185 NULL, NULL, &lowaddr, NULL, 1, 2186 PPC_ELF_MACHINE, 0, 0); 2187 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2188 spapr->kernel_size = load_elf(kernel_filename, 2189 translate_kernel_address, NULL, NULL, 2190 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2191 0, 0); 2192 spapr->kernel_le = spapr->kernel_size > 0; 2193 } 2194 if (spapr->kernel_size < 0) { 2195 error_report("error loading %s: %s", kernel_filename, 2196 load_elf_strerror(spapr->kernel_size)); 2197 exit(1); 2198 } 2199 2200 /* load initrd */ 2201 if (initrd_filename) { 2202 /* Try to locate the initrd in the gap between the kernel 2203 * and the firmware. Add a bit of space just in case 2204 */ 2205 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2206 + 0x1ffff) & ~0xffff; 2207 spapr->initrd_size = load_image_targphys(initrd_filename, 2208 spapr->initrd_base, 2209 load_limit 2210 - spapr->initrd_base); 2211 if (spapr->initrd_size < 0) { 2212 error_report("could not load initial ram disk '%s'", 2213 initrd_filename); 2214 exit(1); 2215 } 2216 } 2217 } 2218 2219 if (bios_name == NULL) { 2220 bios_name = FW_FILE_NAME; 2221 } 2222 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2223 if (!filename) { 2224 error_report("Could not find LPAR firmware '%s'", bios_name); 2225 exit(1); 2226 } 2227 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2228 if (fw_size <= 0) { 2229 error_report("Could not load LPAR firmware '%s'", filename); 2230 exit(1); 2231 } 2232 g_free(filename); 2233 2234 /* FIXME: Should register things through the MachineState's qdev 2235 * interface, this is a legacy from the sPAPREnvironment structure 2236 * which predated MachineState but had a similar function */ 2237 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2238 register_savevm_live(NULL, "spapr/htab", -1, 1, 2239 &savevm_htab_handlers, spapr); 2240 2241 /* used by RTAS */ 2242 QTAILQ_INIT(&spapr->ccs_list); 2243 qemu_register_reset(spapr_ccs_reset_hook, spapr); 2244 2245 qemu_register_boot_set(spapr_boot_set, spapr); 2246 2247 /* to stop and start vmclock */ 2248 if (kvm_enabled()) { 2249 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2250 &spapr->tb); 2251 } 2252 } 2253 2254 static int spapr_kvm_type(const char *vm_type) 2255 { 2256 if (!vm_type) { 2257 return 0; 2258 } 2259 2260 if (!strcmp(vm_type, "HV")) { 2261 return 1; 2262 } 2263 2264 if (!strcmp(vm_type, "PR")) { 2265 return 2; 2266 } 2267 2268 error_report("Unknown kvm-type specified '%s'", vm_type); 2269 exit(1); 2270 } 2271 2272 /* 2273 * Implementation of an interface to adjust firmware path 2274 * for the bootindex property handling. 2275 */ 2276 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2277 DeviceState *dev) 2278 { 2279 #define CAST(type, obj, name) \ 2280 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2281 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2282 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2283 2284 if (d) { 2285 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2286 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2287 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2288 2289 if (spapr) { 2290 /* 2291 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2292 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2293 * in the top 16 bits of the 64-bit LUN 2294 */ 2295 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2296 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2297 (uint64_t)id << 48); 2298 } else if (virtio) { 2299 /* 2300 * We use SRP luns of the form 01000000 | (target << 8) | lun 2301 * in the top 32 bits of the 64-bit LUN 2302 * Note: the quote above is from SLOF and it is wrong, 2303 * the actual binding is: 2304 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2305 */ 2306 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2307 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2308 (uint64_t)id << 32); 2309 } else if (usb) { 2310 /* 2311 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2312 * in the top 32 bits of the 64-bit LUN 2313 */ 2314 unsigned usb_port = atoi(usb->port->path); 2315 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2316 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2317 (uint64_t)id << 32); 2318 } 2319 } 2320 2321 /* 2322 * SLOF probes the USB devices, and if it recognizes that the device is a 2323 * storage device, it changes its name to "storage" instead of "usb-host", 2324 * and additionally adds a child node for the SCSI LUN, so the correct 2325 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2326 */ 2327 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2328 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2329 if (usb_host_dev_is_scsi_storage(usbdev)) { 2330 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2331 } 2332 } 2333 2334 if (phb) { 2335 /* Replace "pci" with "pci@800000020000000" */ 2336 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2337 } 2338 2339 return NULL; 2340 } 2341 2342 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2343 { 2344 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2345 2346 return g_strdup(spapr->kvm_type); 2347 } 2348 2349 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2350 { 2351 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2352 2353 g_free(spapr->kvm_type); 2354 spapr->kvm_type = g_strdup(value); 2355 } 2356 2357 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2358 { 2359 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2360 2361 return spapr->use_hotplug_event_source; 2362 } 2363 2364 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2365 Error **errp) 2366 { 2367 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2368 2369 spapr->use_hotplug_event_source = value; 2370 } 2371 2372 static void spapr_machine_initfn(Object *obj) 2373 { 2374 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2375 2376 spapr->htab_fd = -1; 2377 spapr->use_hotplug_event_source = true; 2378 object_property_add_str(obj, "kvm-type", 2379 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2380 object_property_set_description(obj, "kvm-type", 2381 "Specifies the KVM virtualization mode (HV, PR)", 2382 NULL); 2383 object_property_add_bool(obj, "modern-hotplug-events", 2384 spapr_get_modern_hotplug_events, 2385 spapr_set_modern_hotplug_events, 2386 NULL); 2387 object_property_set_description(obj, "modern-hotplug-events", 2388 "Use dedicated hotplug event mechanism in" 2389 " place of standard EPOW events when possible" 2390 " (required for memory hot-unplug support)", 2391 NULL); 2392 } 2393 2394 static void spapr_machine_finalizefn(Object *obj) 2395 { 2396 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2397 2398 g_free(spapr->kvm_type); 2399 } 2400 2401 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 2402 { 2403 cpu_synchronize_state(cs); 2404 ppc_cpu_do_system_reset(cs); 2405 } 2406 2407 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2408 { 2409 CPUState *cs; 2410 2411 CPU_FOREACH(cs) { 2412 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 2413 } 2414 } 2415 2416 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2417 uint32_t node, bool dedicated_hp_event_source, 2418 Error **errp) 2419 { 2420 sPAPRDRConnector *drc; 2421 sPAPRDRConnectorClass *drck; 2422 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2423 int i, fdt_offset, fdt_size; 2424 void *fdt; 2425 uint64_t addr = addr_start; 2426 2427 for (i = 0; i < nr_lmbs; i++) { 2428 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2429 addr/SPAPR_MEMORY_BLOCK_SIZE); 2430 g_assert(drc); 2431 2432 fdt = create_device_tree(&fdt_size); 2433 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2434 SPAPR_MEMORY_BLOCK_SIZE); 2435 2436 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2437 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2438 addr += SPAPR_MEMORY_BLOCK_SIZE; 2439 if (!dev->hotplugged) { 2440 /* guests expect coldplugged LMBs to be pre-allocated */ 2441 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2442 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2443 } 2444 } 2445 /* send hotplug notification to the 2446 * guest only in case of hotplugged memory 2447 */ 2448 if (dev->hotplugged) { 2449 if (dedicated_hp_event_source) { 2450 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2451 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2452 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2453 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2454 nr_lmbs, 2455 drck->get_index(drc)); 2456 } else { 2457 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 2458 nr_lmbs); 2459 } 2460 } 2461 } 2462 2463 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2464 uint32_t node, Error **errp) 2465 { 2466 Error *local_err = NULL; 2467 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2468 PCDIMMDevice *dimm = PC_DIMM(dev); 2469 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2470 MemoryRegion *mr = ddc->get_memory_region(dimm); 2471 uint64_t align = memory_region_get_alignment(mr); 2472 uint64_t size = memory_region_size(mr); 2473 uint64_t addr; 2474 char *mem_dev; 2475 2476 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2477 error_setg(&local_err, "Hotplugged memory size must be a multiple of " 2478 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 2479 goto out; 2480 } 2481 2482 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 2483 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 2484 error_setg(&local_err, "Memory backend has bad page size. " 2485 "Use 'memory-backend-file' with correct mem-path."); 2486 goto out; 2487 } 2488 2489 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2490 if (local_err) { 2491 goto out; 2492 } 2493 2494 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2495 if (local_err) { 2496 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2497 goto out; 2498 } 2499 2500 spapr_add_lmbs(dev, addr, size, node, 2501 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 2502 &error_abort); 2503 2504 out: 2505 error_propagate(errp, local_err); 2506 } 2507 2508 typedef struct sPAPRDIMMState { 2509 uint32_t nr_lmbs; 2510 } sPAPRDIMMState; 2511 2512 static void spapr_lmb_release(DeviceState *dev, void *opaque) 2513 { 2514 sPAPRDIMMState *ds = (sPAPRDIMMState *)opaque; 2515 HotplugHandler *hotplug_ctrl; 2516 2517 if (--ds->nr_lmbs) { 2518 return; 2519 } 2520 2521 g_free(ds); 2522 2523 /* 2524 * Now that all the LMBs have been removed by the guest, call the 2525 * pc-dimm unplug handler to cleanup up the pc-dimm device. 2526 */ 2527 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2528 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2529 } 2530 2531 static void spapr_del_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2532 Error **errp) 2533 { 2534 sPAPRDRConnector *drc; 2535 sPAPRDRConnectorClass *drck; 2536 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2537 int i; 2538 sPAPRDIMMState *ds = g_malloc0(sizeof(sPAPRDIMMState)); 2539 uint64_t addr = addr_start; 2540 2541 ds->nr_lmbs = nr_lmbs; 2542 for (i = 0; i < nr_lmbs; i++) { 2543 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2544 addr / SPAPR_MEMORY_BLOCK_SIZE); 2545 g_assert(drc); 2546 2547 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2548 drck->detach(drc, dev, spapr_lmb_release, ds, errp); 2549 addr += SPAPR_MEMORY_BLOCK_SIZE; 2550 } 2551 2552 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2553 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2554 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2555 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2556 nr_lmbs, 2557 drck->get_index(drc)); 2558 } 2559 2560 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2561 Error **errp) 2562 { 2563 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2564 PCDIMMDevice *dimm = PC_DIMM(dev); 2565 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2566 MemoryRegion *mr = ddc->get_memory_region(dimm); 2567 2568 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2569 object_unparent(OBJECT(dev)); 2570 } 2571 2572 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 2573 DeviceState *dev, Error **errp) 2574 { 2575 Error *local_err = NULL; 2576 PCDIMMDevice *dimm = PC_DIMM(dev); 2577 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2578 MemoryRegion *mr = ddc->get_memory_region(dimm); 2579 uint64_t size = memory_region_size(mr); 2580 uint64_t addr; 2581 2582 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2583 if (local_err) { 2584 goto out; 2585 } 2586 2587 spapr_del_lmbs(dev, addr, size, &error_abort); 2588 out: 2589 error_propagate(errp, local_err); 2590 } 2591 2592 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 2593 sPAPRMachineState *spapr) 2594 { 2595 PowerPCCPU *cpu = POWERPC_CPU(cs); 2596 DeviceClass *dc = DEVICE_GET_CLASS(cs); 2597 int id = ppc_get_vcpu_dt_id(cpu); 2598 void *fdt; 2599 int offset, fdt_size; 2600 char *nodename; 2601 2602 fdt = create_device_tree(&fdt_size); 2603 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 2604 offset = fdt_add_subnode(fdt, 0, nodename); 2605 2606 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 2607 g_free(nodename); 2608 2609 *fdt_offset = offset; 2610 return fdt; 2611 } 2612 2613 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2614 Error **errp) 2615 { 2616 MachineState *ms = MACHINE(qdev_get_machine()); 2617 CPUCore *cc = CPU_CORE(dev); 2618 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 2619 2620 core_slot->cpu = NULL; 2621 object_unparent(OBJECT(dev)); 2622 } 2623 2624 static void spapr_core_release(DeviceState *dev, void *opaque) 2625 { 2626 HotplugHandler *hotplug_ctrl; 2627 2628 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2629 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2630 } 2631 2632 static 2633 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 2634 Error **errp) 2635 { 2636 int index; 2637 sPAPRDRConnector *drc; 2638 sPAPRDRConnectorClass *drck; 2639 Error *local_err = NULL; 2640 CPUCore *cc = CPU_CORE(dev); 2641 int smt = kvmppc_smt_threads(); 2642 2643 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 2644 error_setg(errp, "Unable to find CPU core with core-id: %d", 2645 cc->core_id); 2646 return; 2647 } 2648 if (index == 0) { 2649 error_setg(errp, "Boot CPU core may not be unplugged"); 2650 return; 2651 } 2652 2653 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2654 g_assert(drc); 2655 2656 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2657 drck->detach(drc, dev, spapr_core_release, NULL, &local_err); 2658 if (local_err) { 2659 error_propagate(errp, local_err); 2660 return; 2661 } 2662 2663 spapr_hotplug_req_remove_by_index(drc); 2664 } 2665 2666 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2667 Error **errp) 2668 { 2669 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 2670 MachineClass *mc = MACHINE_GET_CLASS(spapr); 2671 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 2672 CPUCore *cc = CPU_CORE(dev); 2673 CPUState *cs = CPU(core->threads); 2674 sPAPRDRConnector *drc; 2675 Error *local_err = NULL; 2676 void *fdt = NULL; 2677 int fdt_offset = 0; 2678 int smt = kvmppc_smt_threads(); 2679 CPUArchId *core_slot; 2680 int index; 2681 2682 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2683 if (!core_slot) { 2684 error_setg(errp, "Unable to find CPU core with core-id: %d", 2685 cc->core_id); 2686 return; 2687 } 2688 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2689 2690 g_assert(drc || !mc->has_hotpluggable_cpus); 2691 2692 /* 2693 * Setup CPU DT entries only for hotplugged CPUs. For boot time or 2694 * coldplugged CPUs DT entries are setup in spapr_build_fdt(). 2695 */ 2696 if (dev->hotplugged) { 2697 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 2698 } 2699 2700 if (drc) { 2701 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2702 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err); 2703 if (local_err) { 2704 g_free(fdt); 2705 error_propagate(errp, local_err); 2706 return; 2707 } 2708 } 2709 2710 if (dev->hotplugged) { 2711 /* 2712 * Send hotplug notification interrupt to the guest only in case 2713 * of hotplugged CPUs. 2714 */ 2715 spapr_hotplug_req_add_by_index(drc); 2716 } else { 2717 /* 2718 * Set the right DRC states for cold plugged CPU. 2719 */ 2720 if (drc) { 2721 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2722 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2723 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2724 } 2725 } 2726 core_slot->cpu = OBJECT(dev); 2727 } 2728 2729 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2730 Error **errp) 2731 { 2732 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 2733 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 2734 Error *local_err = NULL; 2735 CPUCore *cc = CPU_CORE(dev); 2736 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model); 2737 const char *type = object_get_typename(OBJECT(dev)); 2738 CPUArchId *core_slot; 2739 int index; 2740 2741 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 2742 error_setg(&local_err, "CPU hotplug not supported for this machine"); 2743 goto out; 2744 } 2745 2746 if (strcmp(base_core_type, type)) { 2747 error_setg(&local_err, "CPU core type should be %s", base_core_type); 2748 goto out; 2749 } 2750 2751 if (cc->core_id % smp_threads) { 2752 error_setg(&local_err, "invalid core id %d", cc->core_id); 2753 goto out; 2754 } 2755 2756 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2757 if (!core_slot) { 2758 error_setg(&local_err, "core id %d out of range", cc->core_id); 2759 goto out; 2760 } 2761 2762 if (core_slot->cpu) { 2763 error_setg(&local_err, "core %d already populated", cc->core_id); 2764 goto out; 2765 } 2766 2767 out: 2768 g_free(base_core_type); 2769 error_propagate(errp, local_err); 2770 } 2771 2772 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 2773 DeviceState *dev, Error **errp) 2774 { 2775 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2776 2777 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2778 int node; 2779 2780 if (!smc->dr_lmb_enabled) { 2781 error_setg(errp, "Memory hotplug not supported for this machine"); 2782 return; 2783 } 2784 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 2785 if (*errp) { 2786 return; 2787 } 2788 if (node < 0 || node >= MAX_NODES) { 2789 error_setg(errp, "Invaild node %d", node); 2790 return; 2791 } 2792 2793 /* 2794 * Currently PowerPC kernel doesn't allow hot-adding memory to 2795 * memory-less node, but instead will silently add the memory 2796 * to the first node that has some memory. This causes two 2797 * unexpected behaviours for the user. 2798 * 2799 * - Memory gets hotplugged to a different node than what the user 2800 * specified. 2801 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 2802 * to memory-less node, a reboot will set things accordingly 2803 * and the previously hotplugged memory now ends in the right node. 2804 * This appears as if some memory moved from one node to another. 2805 * 2806 * So until kernel starts supporting memory hotplug to memory-less 2807 * nodes, just prevent such attempts upfront in QEMU. 2808 */ 2809 if (nb_numa_nodes && !numa_info[node].node_mem) { 2810 error_setg(errp, "Can't hotplug memory to memory-less node %d", 2811 node); 2812 return; 2813 } 2814 2815 spapr_memory_plug(hotplug_dev, dev, node, errp); 2816 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2817 spapr_core_plug(hotplug_dev, dev, errp); 2818 } 2819 } 2820 2821 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 2822 DeviceState *dev, Error **errp) 2823 { 2824 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2825 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2826 2827 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2828 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2829 spapr_memory_unplug(hotplug_dev, dev, errp); 2830 } else { 2831 error_setg(errp, "Memory hot unplug not supported for this guest"); 2832 } 2833 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2834 if (!mc->has_hotpluggable_cpus) { 2835 error_setg(errp, "CPU hot unplug not supported on this machine"); 2836 return; 2837 } 2838 spapr_core_unplug(hotplug_dev, dev, errp); 2839 } 2840 } 2841 2842 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 2843 DeviceState *dev, Error **errp) 2844 { 2845 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2846 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2847 2848 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2849 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2850 spapr_memory_unplug_request(hotplug_dev, dev, errp); 2851 } else { 2852 /* NOTE: this means there is a window after guest reset, prior to 2853 * CAS negotiation, where unplug requests will fail due to the 2854 * capability not being detected yet. This is a bit different than 2855 * the case with PCI unplug, where the events will be queued and 2856 * eventually handled by the guest after boot 2857 */ 2858 error_setg(errp, "Memory hot unplug not supported for this guest"); 2859 } 2860 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2861 if (!mc->has_hotpluggable_cpus) { 2862 error_setg(errp, "CPU hot unplug not supported on this machine"); 2863 return; 2864 } 2865 spapr_core_unplug_request(hotplug_dev, dev, errp); 2866 } 2867 } 2868 2869 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 2870 DeviceState *dev, Error **errp) 2871 { 2872 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2873 spapr_core_pre_plug(hotplug_dev, dev, errp); 2874 } 2875 } 2876 2877 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 2878 DeviceState *dev) 2879 { 2880 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2881 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2882 return HOTPLUG_HANDLER(machine); 2883 } 2884 return NULL; 2885 } 2886 2887 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index) 2888 { 2889 /* Allocate to NUMA nodes on a "socket" basis (not that concept of 2890 * socket means much for the paravirtualized PAPR platform) */ 2891 return cpu_index / smp_threads / smp_cores; 2892 } 2893 2894 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 2895 { 2896 int i; 2897 int spapr_max_cores = max_cpus / smp_threads; 2898 MachineClass *mc = MACHINE_GET_CLASS(machine); 2899 2900 if (!mc->has_hotpluggable_cpus) { 2901 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 2902 } 2903 if (machine->possible_cpus) { 2904 assert(machine->possible_cpus->len == spapr_max_cores); 2905 return machine->possible_cpus; 2906 } 2907 2908 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2909 sizeof(CPUArchId) * spapr_max_cores); 2910 machine->possible_cpus->len = spapr_max_cores; 2911 for (i = 0; i < machine->possible_cpus->len; i++) { 2912 int core_id = i * smp_threads; 2913 2914 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 2915 machine->possible_cpus->cpus[i].arch_id = core_id; 2916 machine->possible_cpus->cpus[i].props.has_core_id = true; 2917 machine->possible_cpus->cpus[i].props.core_id = core_id; 2918 /* TODO: add 'has_node/node' here to describe 2919 to which node core belongs */ 2920 } 2921 return machine->possible_cpus; 2922 } 2923 2924 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 2925 uint64_t *buid, hwaddr *pio, 2926 hwaddr *mmio32, hwaddr *mmio64, 2927 unsigned n_dma, uint32_t *liobns, Error **errp) 2928 { 2929 /* 2930 * New-style PHB window placement. 2931 * 2932 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 2933 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 2934 * windows. 2935 * 2936 * Some guest kernels can't work with MMIO windows above 1<<46 2937 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 2938 * 2939 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 2940 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 2941 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 2942 * 1TiB 64-bit MMIO windows for each PHB. 2943 */ 2944 const uint64_t base_buid = 0x800000020000000ULL; 2945 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 2946 SPAPR_PCI_MEM64_WIN_SIZE - 1) 2947 int i; 2948 2949 /* Sanity check natural alignments */ 2950 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 2951 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 2952 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 2953 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 2954 /* Sanity check bounds */ 2955 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 2956 SPAPR_PCI_MEM32_WIN_SIZE); 2957 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 2958 SPAPR_PCI_MEM64_WIN_SIZE); 2959 2960 if (index >= SPAPR_MAX_PHBS) { 2961 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 2962 SPAPR_MAX_PHBS - 1); 2963 return; 2964 } 2965 2966 *buid = base_buid + index; 2967 for (i = 0; i < n_dma; ++i) { 2968 liobns[i] = SPAPR_PCI_LIOBN(index, i); 2969 } 2970 2971 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 2972 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 2973 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 2974 } 2975 2976 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 2977 { 2978 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 2979 2980 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 2981 } 2982 2983 static void spapr_ics_resend(XICSFabric *dev) 2984 { 2985 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 2986 2987 ics_resend(spapr->ics); 2988 } 2989 2990 static ICPState *spapr_icp_get(XICSFabric *xi, int server) 2991 { 2992 sPAPRMachineState *spapr = SPAPR_MACHINE(xi); 2993 2994 return (server < spapr->nr_servers) ? &spapr->icps[server] : NULL; 2995 } 2996 2997 static void spapr_icp_resend(XICSFabric *xi) 2998 { 2999 sPAPRMachineState *spapr = SPAPR_MACHINE(xi); 3000 int i; 3001 3002 for (i = 0; i < spapr->nr_servers; i++) { 3003 icp_resend(&spapr->icps[i]); 3004 } 3005 } 3006 3007 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3008 { 3009 MachineClass *mc = MACHINE_CLASS(oc); 3010 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3011 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3012 NMIClass *nc = NMI_CLASS(oc); 3013 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3014 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3015 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3016 3017 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3018 3019 /* 3020 * We set up the default / latest behaviour here. The class_init 3021 * functions for the specific versioned machine types can override 3022 * these details for backwards compatibility 3023 */ 3024 mc->init = ppc_spapr_init; 3025 mc->reset = ppc_spapr_reset; 3026 mc->block_default_type = IF_SCSI; 3027 mc->max_cpus = 1024; 3028 mc->no_parallel = 1; 3029 mc->default_boot_order = ""; 3030 mc->default_ram_size = 512 * M_BYTE; 3031 mc->kvm_type = spapr_kvm_type; 3032 mc->has_dynamic_sysbus = true; 3033 mc->pci_allow_0_address = true; 3034 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3035 hc->pre_plug = spapr_machine_device_pre_plug; 3036 hc->plug = spapr_machine_device_plug; 3037 hc->unplug = spapr_machine_device_unplug; 3038 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; 3039 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3040 hc->unplug_request = spapr_machine_device_unplug_request; 3041 3042 smc->dr_lmb_enabled = true; 3043 smc->tcg_default_cpu = "POWER8"; 3044 mc->has_hotpluggable_cpus = true; 3045 fwc->get_dev_path = spapr_get_fw_dev_path; 3046 nc->nmi_monitor_handler = spapr_nmi; 3047 smc->phb_placement = spapr_phb_placement; 3048 vhc->hypercall = emulate_spapr_hypercall; 3049 vhc->hpt_mask = spapr_hpt_mask; 3050 vhc->map_hptes = spapr_map_hptes; 3051 vhc->unmap_hptes = spapr_unmap_hptes; 3052 vhc->store_hpte = spapr_store_hpte; 3053 xic->ics_get = spapr_ics_get; 3054 xic->ics_resend = spapr_ics_resend; 3055 xic->icp_get = spapr_icp_get; 3056 xic->icp_resend = spapr_icp_resend; 3057 } 3058 3059 static const TypeInfo spapr_machine_info = { 3060 .name = TYPE_SPAPR_MACHINE, 3061 .parent = TYPE_MACHINE, 3062 .abstract = true, 3063 .instance_size = sizeof(sPAPRMachineState), 3064 .instance_init = spapr_machine_initfn, 3065 .instance_finalize = spapr_machine_finalizefn, 3066 .class_size = sizeof(sPAPRMachineClass), 3067 .class_init = spapr_machine_class_init, 3068 .interfaces = (InterfaceInfo[]) { 3069 { TYPE_FW_PATH_PROVIDER }, 3070 { TYPE_NMI }, 3071 { TYPE_HOTPLUG_HANDLER }, 3072 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3073 { TYPE_XICS_FABRIC }, 3074 { } 3075 }, 3076 }; 3077 3078 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3079 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3080 void *data) \ 3081 { \ 3082 MachineClass *mc = MACHINE_CLASS(oc); \ 3083 spapr_machine_##suffix##_class_options(mc); \ 3084 if (latest) { \ 3085 mc->alias = "pseries"; \ 3086 mc->is_default = 1; \ 3087 } \ 3088 } \ 3089 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3090 { \ 3091 MachineState *machine = MACHINE(obj); \ 3092 spapr_machine_##suffix##_instance_options(machine); \ 3093 } \ 3094 static const TypeInfo spapr_machine_##suffix##_info = { \ 3095 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3096 .parent = TYPE_SPAPR_MACHINE, \ 3097 .class_init = spapr_machine_##suffix##_class_init, \ 3098 .instance_init = spapr_machine_##suffix##_instance_init, \ 3099 }; \ 3100 static void spapr_machine_register_##suffix(void) \ 3101 { \ 3102 type_register(&spapr_machine_##suffix##_info); \ 3103 } \ 3104 type_init(spapr_machine_register_##suffix) 3105 3106 /* 3107 * pseries-2.9 3108 */ 3109 static void spapr_machine_2_9_instance_options(MachineState *machine) 3110 { 3111 } 3112 3113 static void spapr_machine_2_9_class_options(MachineClass *mc) 3114 { 3115 /* Defaults for the latest behaviour inherited from the base class */ 3116 } 3117 3118 DEFINE_SPAPR_MACHINE(2_9, "2.9", true); 3119 3120 /* 3121 * pseries-2.8 3122 */ 3123 #define SPAPR_COMPAT_2_8 \ 3124 HW_COMPAT_2_8 3125 3126 static void spapr_machine_2_8_instance_options(MachineState *machine) 3127 { 3128 spapr_machine_2_9_instance_options(machine); 3129 } 3130 3131 static void spapr_machine_2_8_class_options(MachineClass *mc) 3132 { 3133 spapr_machine_2_9_class_options(mc); 3134 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 3135 } 3136 3137 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 3138 3139 /* 3140 * pseries-2.7 3141 */ 3142 #define SPAPR_COMPAT_2_7 \ 3143 HW_COMPAT_2_7 \ 3144 { \ 3145 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3146 .property = "mem_win_size", \ 3147 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 3148 }, \ 3149 { \ 3150 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3151 .property = "mem64_win_size", \ 3152 .value = "0", \ 3153 }, \ 3154 { \ 3155 .driver = TYPE_POWERPC_CPU, \ 3156 .property = "pre-2.8-migration", \ 3157 .value = "on", \ 3158 }, \ 3159 { \ 3160 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3161 .property = "pre-2.8-migration", \ 3162 .value = "on", \ 3163 }, 3164 3165 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 3166 uint64_t *buid, hwaddr *pio, 3167 hwaddr *mmio32, hwaddr *mmio64, 3168 unsigned n_dma, uint32_t *liobns, Error **errp) 3169 { 3170 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 3171 const uint64_t base_buid = 0x800000020000000ULL; 3172 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 3173 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 3174 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 3175 const uint32_t max_index = 255; 3176 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 3177 3178 uint64_t ram_top = MACHINE(spapr)->ram_size; 3179 hwaddr phb0_base, phb_base; 3180 int i; 3181 3182 /* Do we have hotpluggable memory? */ 3183 if (MACHINE(spapr)->maxram_size > ram_top) { 3184 /* Can't just use maxram_size, because there may be an 3185 * alignment gap between normal and hotpluggable memory 3186 * regions */ 3187 ram_top = spapr->hotplug_memory.base + 3188 memory_region_size(&spapr->hotplug_memory.mr); 3189 } 3190 3191 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 3192 3193 if (index > max_index) { 3194 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 3195 max_index); 3196 return; 3197 } 3198 3199 *buid = base_buid + index; 3200 for (i = 0; i < n_dma; ++i) { 3201 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3202 } 3203 3204 phb_base = phb0_base + index * phb_spacing; 3205 *pio = phb_base + pio_offset; 3206 *mmio32 = phb_base + mmio_offset; 3207 /* 3208 * We don't set the 64-bit MMIO window, relying on the PHB's 3209 * fallback behaviour of automatically splitting a large "32-bit" 3210 * window into contiguous 32-bit and 64-bit windows 3211 */ 3212 } 3213 3214 static void spapr_machine_2_7_instance_options(MachineState *machine) 3215 { 3216 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 3217 3218 spapr_machine_2_8_instance_options(machine); 3219 spapr->use_hotplug_event_source = false; 3220 } 3221 3222 static void spapr_machine_2_7_class_options(MachineClass *mc) 3223 { 3224 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3225 3226 spapr_machine_2_8_class_options(mc); 3227 smc->tcg_default_cpu = "POWER7"; 3228 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 3229 smc->phb_placement = phb_placement_2_7; 3230 } 3231 3232 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 3233 3234 /* 3235 * pseries-2.6 3236 */ 3237 #define SPAPR_COMPAT_2_6 \ 3238 HW_COMPAT_2_6 \ 3239 { \ 3240 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3241 .property = "ddw",\ 3242 .value = stringify(off),\ 3243 }, 3244 3245 static void spapr_machine_2_6_instance_options(MachineState *machine) 3246 { 3247 spapr_machine_2_7_instance_options(machine); 3248 } 3249 3250 static void spapr_machine_2_6_class_options(MachineClass *mc) 3251 { 3252 spapr_machine_2_7_class_options(mc); 3253 mc->has_hotpluggable_cpus = false; 3254 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 3255 } 3256 3257 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 3258 3259 /* 3260 * pseries-2.5 3261 */ 3262 #define SPAPR_COMPAT_2_5 \ 3263 HW_COMPAT_2_5 \ 3264 { \ 3265 .driver = "spapr-vlan", \ 3266 .property = "use-rx-buffer-pools", \ 3267 .value = "off", \ 3268 }, 3269 3270 static void spapr_machine_2_5_instance_options(MachineState *machine) 3271 { 3272 spapr_machine_2_6_instance_options(machine); 3273 } 3274 3275 static void spapr_machine_2_5_class_options(MachineClass *mc) 3276 { 3277 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3278 3279 spapr_machine_2_6_class_options(mc); 3280 smc->use_ohci_by_default = true; 3281 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 3282 } 3283 3284 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 3285 3286 /* 3287 * pseries-2.4 3288 */ 3289 #define SPAPR_COMPAT_2_4 \ 3290 HW_COMPAT_2_4 3291 3292 static void spapr_machine_2_4_instance_options(MachineState *machine) 3293 { 3294 spapr_machine_2_5_instance_options(machine); 3295 } 3296 3297 static void spapr_machine_2_4_class_options(MachineClass *mc) 3298 { 3299 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3300 3301 spapr_machine_2_5_class_options(mc); 3302 smc->dr_lmb_enabled = false; 3303 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 3304 } 3305 3306 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 3307 3308 /* 3309 * pseries-2.3 3310 */ 3311 #define SPAPR_COMPAT_2_3 \ 3312 HW_COMPAT_2_3 \ 3313 {\ 3314 .driver = "spapr-pci-host-bridge",\ 3315 .property = "dynamic-reconfiguration",\ 3316 .value = "off",\ 3317 }, 3318 3319 static void spapr_machine_2_3_instance_options(MachineState *machine) 3320 { 3321 spapr_machine_2_4_instance_options(machine); 3322 savevm_skip_section_footers(); 3323 global_state_set_optional(); 3324 savevm_skip_configuration(); 3325 } 3326 3327 static void spapr_machine_2_3_class_options(MachineClass *mc) 3328 { 3329 spapr_machine_2_4_class_options(mc); 3330 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 3331 } 3332 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 3333 3334 /* 3335 * pseries-2.2 3336 */ 3337 3338 #define SPAPR_COMPAT_2_2 \ 3339 HW_COMPAT_2_2 \ 3340 {\ 3341 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3342 .property = "mem_win_size",\ 3343 .value = "0x20000000",\ 3344 }, 3345 3346 static void spapr_machine_2_2_instance_options(MachineState *machine) 3347 { 3348 spapr_machine_2_3_instance_options(machine); 3349 machine->suppress_vmdesc = true; 3350 } 3351 3352 static void spapr_machine_2_2_class_options(MachineClass *mc) 3353 { 3354 spapr_machine_2_3_class_options(mc); 3355 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 3356 } 3357 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 3358 3359 /* 3360 * pseries-2.1 3361 */ 3362 #define SPAPR_COMPAT_2_1 \ 3363 HW_COMPAT_2_1 3364 3365 static void spapr_machine_2_1_instance_options(MachineState *machine) 3366 { 3367 spapr_machine_2_2_instance_options(machine); 3368 } 3369 3370 static void spapr_machine_2_1_class_options(MachineClass *mc) 3371 { 3372 spapr_machine_2_2_class_options(mc); 3373 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 3374 } 3375 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 3376 3377 static void spapr_machine_register_types(void) 3378 { 3379 type_register_static(&spapr_machine_info); 3380 } 3381 3382 type_init(spapr_machine_register_types) 3383