1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/numa.h" 31 #include "hw/hw.h" 32 #include "qemu/log.h" 33 #include "hw/fw-path-provider.h" 34 #include "elf.h" 35 #include "net/net.h" 36 #include "sysemu/device_tree.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/migration.h" 42 #include "mmu-hash64.h" 43 #include "qom/cpu.h" 44 45 #include "hw/boards.h" 46 #include "hw/ppc/ppc.h" 47 #include "hw/loader.h" 48 49 #include "hw/ppc/fdt.h" 50 #include "hw/ppc/spapr.h" 51 #include "hw/ppc/spapr_vio.h" 52 #include "hw/pci-host/spapr.h" 53 #include "hw/ppc/xics.h" 54 #include "hw/pci/msi.h" 55 56 #include "hw/pci/pci.h" 57 #include "hw/scsi/scsi.h" 58 #include "hw/virtio/virtio-scsi.h" 59 60 #include "exec/address-spaces.h" 61 #include "hw/usb.h" 62 #include "qemu/config-file.h" 63 #include "qemu/error-report.h" 64 #include "trace.h" 65 #include "hw/nmi.h" 66 67 #include "hw/compat.h" 68 #include "qemu/cutils.h" 69 #include "hw/ppc/spapr_cpu_core.h" 70 #include "qmp-commands.h" 71 72 #include <libfdt.h> 73 74 /* SLOF memory layout: 75 * 76 * SLOF raw image loaded at 0, copies its romfs right below the flat 77 * device-tree, then position SLOF itself 31M below that 78 * 79 * So we set FW_OVERHEAD to 40MB which should account for all of that 80 * and more 81 * 82 * We load our kernel at 4M, leaving space for SLOF initial image 83 */ 84 #define FDT_MAX_SIZE 0x100000 85 #define RTAS_MAX_SIZE 0x10000 86 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 87 #define FW_MAX_SIZE 0x400000 88 #define FW_FILE_NAME "slof.bin" 89 #define FW_OVERHEAD 0x2800000 90 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 91 92 #define MIN_RMA_SLOF 128UL 93 94 #define PHANDLE_XICP 0x00001111 95 96 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 97 98 static XICSState *try_create_xics(sPAPRMachineState *spapr, 99 const char *type, const char *type_ics, 100 const char *type_icp, int nr_servers, 101 int nr_irqs, Error **errp) 102 { 103 XICSFabric *xi = XICS_FABRIC(spapr); 104 Error *err = NULL, *local_err = NULL; 105 XICSState *xics; 106 ICSState *ics = NULL; 107 int i; 108 109 xics = XICS_COMMON(object_new(type)); 110 qdev_set_parent_bus(DEVICE(xics), sysbus_get_default()); 111 object_property_set_bool(OBJECT(xics), true, "realized", &err); 112 if (err) { 113 goto error; 114 } 115 116 ics = ICS_SIMPLE(object_new(type_ics)); 117 qdev_set_parent_bus(DEVICE(ics), sysbus_get_default()); 118 object_property_add_child(OBJECT(spapr), "ics", OBJECT(ics), NULL); 119 object_property_set_int(OBJECT(ics), nr_irqs, "nr-irqs", &err); 120 object_property_add_const_link(OBJECT(ics), "xics", OBJECT(xi), NULL); 121 object_property_set_bool(OBJECT(ics), true, "realized", &local_err); 122 error_propagate(&err, local_err); 123 if (err) { 124 goto error; 125 } 126 127 xics->ss = g_malloc0(nr_servers * sizeof(ICPState)); 128 xics->nr_servers = nr_servers; 129 130 for (i = 0; i < nr_servers; i++) { 131 ICPState *icp = &xics->ss[i]; 132 133 object_initialize(icp, sizeof(*icp), type_icp); 134 qdev_set_parent_bus(DEVICE(icp), sysbus_get_default()); 135 object_property_add_child(OBJECT(xics), "icp[*]", OBJECT(icp), NULL); 136 object_property_add_const_link(OBJECT(icp), "xics", OBJECT(xi), NULL); 137 object_property_set_bool(OBJECT(icp), true, "realized", &err); 138 if (err) { 139 goto error; 140 } 141 object_unref(OBJECT(icp)); 142 } 143 144 spapr->ics = ics; 145 return xics; 146 147 error: 148 error_propagate(errp, err); 149 if (ics) { 150 object_unparent(OBJECT(ics)); 151 } 152 object_unparent(OBJECT(xics)); 153 return NULL; 154 } 155 156 static XICSState *xics_system_init(MachineState *machine, 157 int nr_servers, int nr_irqs, Error **errp) 158 { 159 XICSState *xics = NULL; 160 161 if (kvm_enabled()) { 162 Error *err = NULL; 163 164 if (machine_kernel_irqchip_allowed(machine)) { 165 xics = try_create_xics(SPAPR_MACHINE(machine), 166 TYPE_XICS_SPAPR_KVM, TYPE_ICS_KVM, 167 TYPE_KVM_ICP, nr_servers, nr_irqs, &err); 168 } 169 if (machine_kernel_irqchip_required(machine) && !xics) { 170 error_reportf_err(err, 171 "kernel_irqchip requested but unavailable: "); 172 } else { 173 error_free(err); 174 } 175 } 176 177 if (!xics) { 178 xics = try_create_xics(SPAPR_MACHINE(machine), 179 TYPE_XICS_SPAPR, TYPE_ICS_SIMPLE, 180 TYPE_ICP, nr_servers, nr_irqs, errp); 181 } 182 183 return xics; 184 } 185 186 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 187 int smt_threads) 188 { 189 int i, ret = 0; 190 uint32_t servers_prop[smt_threads]; 191 uint32_t gservers_prop[smt_threads * 2]; 192 int index = ppc_get_vcpu_dt_id(cpu); 193 194 if (cpu->compat_pvr) { 195 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 196 if (ret < 0) { 197 return ret; 198 } 199 } 200 201 /* Build interrupt servers and gservers properties */ 202 for (i = 0; i < smt_threads; i++) { 203 servers_prop[i] = cpu_to_be32(index + i); 204 /* Hack, direct the group queues back to cpu 0 */ 205 gservers_prop[i*2] = cpu_to_be32(index + i); 206 gservers_prop[i*2 + 1] = 0; 207 } 208 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 209 servers_prop, sizeof(servers_prop)); 210 if (ret < 0) { 211 return ret; 212 } 213 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 214 gservers_prop, sizeof(gservers_prop)); 215 216 return ret; 217 } 218 219 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) 220 { 221 int ret = 0; 222 PowerPCCPU *cpu = POWERPC_CPU(cs); 223 int index = ppc_get_vcpu_dt_id(cpu); 224 uint32_t associativity[] = {cpu_to_be32(0x5), 225 cpu_to_be32(0x0), 226 cpu_to_be32(0x0), 227 cpu_to_be32(0x0), 228 cpu_to_be32(cs->numa_node), 229 cpu_to_be32(index)}; 230 231 /* Advertise NUMA via ibm,associativity */ 232 if (nb_numa_nodes > 1) { 233 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 234 sizeof(associativity)); 235 } 236 237 return ret; 238 } 239 240 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 241 { 242 int ret = 0, offset, cpus_offset; 243 CPUState *cs; 244 char cpu_model[32]; 245 int smt = kvmppc_smt_threads(); 246 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 247 248 CPU_FOREACH(cs) { 249 PowerPCCPU *cpu = POWERPC_CPU(cs); 250 DeviceClass *dc = DEVICE_GET_CLASS(cs); 251 int index = ppc_get_vcpu_dt_id(cpu); 252 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 253 254 if ((index % smt) != 0) { 255 continue; 256 } 257 258 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 259 260 cpus_offset = fdt_path_offset(fdt, "/cpus"); 261 if (cpus_offset < 0) { 262 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 263 "cpus"); 264 if (cpus_offset < 0) { 265 return cpus_offset; 266 } 267 } 268 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 269 if (offset < 0) { 270 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 271 if (offset < 0) { 272 return offset; 273 } 274 } 275 276 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 277 pft_size_prop, sizeof(pft_size_prop)); 278 if (ret < 0) { 279 return ret; 280 } 281 282 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); 283 if (ret < 0) { 284 return ret; 285 } 286 287 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 288 if (ret < 0) { 289 return ret; 290 } 291 } 292 return ret; 293 } 294 295 static hwaddr spapr_node0_size(void) 296 { 297 MachineState *machine = MACHINE(qdev_get_machine()); 298 299 if (nb_numa_nodes) { 300 int i; 301 for (i = 0; i < nb_numa_nodes; ++i) { 302 if (numa_info[i].node_mem) { 303 return MIN(pow2floor(numa_info[i].node_mem), 304 machine->ram_size); 305 } 306 } 307 } 308 return machine->ram_size; 309 } 310 311 static void add_str(GString *s, const gchar *s1) 312 { 313 g_string_append_len(s, s1, strlen(s1) + 1); 314 } 315 316 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 317 hwaddr size) 318 { 319 uint32_t associativity[] = { 320 cpu_to_be32(0x4), /* length */ 321 cpu_to_be32(0x0), cpu_to_be32(0x0), 322 cpu_to_be32(0x0), cpu_to_be32(nodeid) 323 }; 324 char mem_name[32]; 325 uint64_t mem_reg_property[2]; 326 int off; 327 328 mem_reg_property[0] = cpu_to_be64(start); 329 mem_reg_property[1] = cpu_to_be64(size); 330 331 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 332 off = fdt_add_subnode(fdt, 0, mem_name); 333 _FDT(off); 334 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 335 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 336 sizeof(mem_reg_property)))); 337 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 338 sizeof(associativity)))); 339 return off; 340 } 341 342 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 343 { 344 MachineState *machine = MACHINE(spapr); 345 hwaddr mem_start, node_size; 346 int i, nb_nodes = nb_numa_nodes; 347 NodeInfo *nodes = numa_info; 348 NodeInfo ramnode; 349 350 /* No NUMA nodes, assume there is just one node with whole RAM */ 351 if (!nb_numa_nodes) { 352 nb_nodes = 1; 353 ramnode.node_mem = machine->ram_size; 354 nodes = &ramnode; 355 } 356 357 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 358 if (!nodes[i].node_mem) { 359 continue; 360 } 361 if (mem_start >= machine->ram_size) { 362 node_size = 0; 363 } else { 364 node_size = nodes[i].node_mem; 365 if (node_size > machine->ram_size - mem_start) { 366 node_size = machine->ram_size - mem_start; 367 } 368 } 369 if (!mem_start) { 370 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 371 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 372 mem_start += spapr->rma_size; 373 node_size -= spapr->rma_size; 374 } 375 for ( ; node_size; ) { 376 hwaddr sizetmp = pow2floor(node_size); 377 378 /* mem_start != 0 here */ 379 if (ctzl(mem_start) < ctzl(sizetmp)) { 380 sizetmp = 1ULL << ctzl(mem_start); 381 } 382 383 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 384 node_size -= sizetmp; 385 mem_start += sizetmp; 386 } 387 } 388 389 return 0; 390 } 391 392 /* Populate the "ibm,pa-features" property */ 393 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset) 394 { 395 uint8_t pa_features_206[] = { 6, 0, 396 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 397 uint8_t pa_features_207[] = { 24, 0, 398 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 399 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 400 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 401 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 402 uint8_t *pa_features; 403 size_t pa_size; 404 405 switch (env->mmu_model) { 406 case POWERPC_MMU_2_06: 407 case POWERPC_MMU_2_06a: 408 pa_features = pa_features_206; 409 pa_size = sizeof(pa_features_206); 410 break; 411 case POWERPC_MMU_2_07: 412 case POWERPC_MMU_2_07a: 413 pa_features = pa_features_207; 414 pa_size = sizeof(pa_features_207); 415 break; 416 default: 417 return; 418 } 419 420 if (env->ci_large_pages) { 421 /* 422 * Note: we keep CI large pages off by default because a 64K capable 423 * guest provisioned with large pages might otherwise try to map a qemu 424 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 425 * even if that qemu runs on a 4k host. 426 * We dd this bit back here if we are confident this is not an issue 427 */ 428 pa_features[3] |= 0x20; 429 } 430 if (kvmppc_has_cap_htm() && pa_size > 24) { 431 pa_features[24] |= 0x80; /* Transactional memory support */ 432 } 433 434 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 435 } 436 437 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 438 sPAPRMachineState *spapr) 439 { 440 PowerPCCPU *cpu = POWERPC_CPU(cs); 441 CPUPPCState *env = &cpu->env; 442 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 443 int index = ppc_get_vcpu_dt_id(cpu); 444 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 445 0xffffffff, 0xffffffff}; 446 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 447 : SPAPR_TIMEBASE_FREQ; 448 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 449 uint32_t page_sizes_prop[64]; 450 size_t page_sizes_prop_size; 451 uint32_t vcpus_per_socket = smp_threads * smp_cores; 452 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 453 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 454 sPAPRDRConnector *drc; 455 sPAPRDRConnectorClass *drck; 456 int drc_index; 457 458 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index); 459 if (drc) { 460 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 461 drc_index = drck->get_index(drc); 462 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 463 } 464 465 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 466 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 467 468 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 469 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 470 env->dcache_line_size))); 471 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 472 env->dcache_line_size))); 473 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 474 env->icache_line_size))); 475 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 476 env->icache_line_size))); 477 478 if (pcc->l1_dcache_size) { 479 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 480 pcc->l1_dcache_size))); 481 } else { 482 error_report("Warning: Unknown L1 dcache size for cpu"); 483 } 484 if (pcc->l1_icache_size) { 485 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 486 pcc->l1_icache_size))); 487 } else { 488 error_report("Warning: Unknown L1 icache size for cpu"); 489 } 490 491 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 492 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 493 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 494 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 495 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 496 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 497 498 if (env->spr_cb[SPR_PURR].oea_read) { 499 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 500 } 501 502 if (env->mmu_model & POWERPC_MMU_1TSEG) { 503 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 504 segs, sizeof(segs)))); 505 } 506 507 /* Advertise VMX/VSX (vector extensions) if available 508 * 0 / no property == no vector extensions 509 * 1 == VMX / Altivec available 510 * 2 == VSX available */ 511 if (env->insns_flags & PPC_ALTIVEC) { 512 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 513 514 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 515 } 516 517 /* Advertise DFP (Decimal Floating Point) if available 518 * 0 / no property == no DFP 519 * 1 == DFP available */ 520 if (env->insns_flags2 & PPC2_DFP) { 521 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 522 } 523 524 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 525 sizeof(page_sizes_prop)); 526 if (page_sizes_prop_size) { 527 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 528 page_sizes_prop, page_sizes_prop_size))); 529 } 530 531 spapr_populate_pa_features(env, fdt, offset); 532 533 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 534 cs->cpu_index / vcpus_per_socket))); 535 536 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 537 pft_size_prop, sizeof(pft_size_prop)))); 538 539 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); 540 541 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 542 } 543 544 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 545 { 546 CPUState *cs; 547 int cpus_offset; 548 char *nodename; 549 int smt = kvmppc_smt_threads(); 550 551 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 552 _FDT(cpus_offset); 553 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 554 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 555 556 /* 557 * We walk the CPUs in reverse order to ensure that CPU DT nodes 558 * created by fdt_add_subnode() end up in the right order in FDT 559 * for the guest kernel the enumerate the CPUs correctly. 560 */ 561 CPU_FOREACH_REVERSE(cs) { 562 PowerPCCPU *cpu = POWERPC_CPU(cs); 563 int index = ppc_get_vcpu_dt_id(cpu); 564 DeviceClass *dc = DEVICE_GET_CLASS(cs); 565 int offset; 566 567 if ((index % smt) != 0) { 568 continue; 569 } 570 571 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 572 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 573 g_free(nodename); 574 _FDT(offset); 575 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 576 } 577 578 } 579 580 /* 581 * Adds ibm,dynamic-reconfiguration-memory node. 582 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 583 * of this device tree node. 584 */ 585 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 586 { 587 MachineState *machine = MACHINE(spapr); 588 int ret, i, offset; 589 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 590 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 591 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 592 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 593 memory_region_size(&spapr->hotplug_memory.mr)) / 594 lmb_size; 595 uint32_t *int_buf, *cur_index, buf_len; 596 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 597 598 /* 599 * Don't create the node if there is no hotpluggable memory 600 */ 601 if (machine->ram_size == machine->maxram_size) { 602 return 0; 603 } 604 605 /* 606 * Allocate enough buffer size to fit in ibm,dynamic-memory 607 * or ibm,associativity-lookup-arrays 608 */ 609 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 610 * sizeof(uint32_t); 611 cur_index = int_buf = g_malloc0(buf_len); 612 613 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 614 615 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 616 sizeof(prop_lmb_size)); 617 if (ret < 0) { 618 goto out; 619 } 620 621 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 622 if (ret < 0) { 623 goto out; 624 } 625 626 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 627 if (ret < 0) { 628 goto out; 629 } 630 631 /* ibm,dynamic-memory */ 632 int_buf[0] = cpu_to_be32(nr_lmbs); 633 cur_index++; 634 for (i = 0; i < nr_lmbs; i++) { 635 uint64_t addr = i * lmb_size; 636 uint32_t *dynamic_memory = cur_index; 637 638 if (i >= hotplug_lmb_start) { 639 sPAPRDRConnector *drc; 640 sPAPRDRConnectorClass *drck; 641 642 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i); 643 g_assert(drc); 644 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 645 646 dynamic_memory[0] = cpu_to_be32(addr >> 32); 647 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 648 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); 649 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 650 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 651 if (memory_region_present(get_system_memory(), addr)) { 652 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 653 } else { 654 dynamic_memory[5] = cpu_to_be32(0); 655 } 656 } else { 657 /* 658 * LMB information for RMA, boot time RAM and gap b/n RAM and 659 * hotplug memory region -- all these are marked as reserved 660 * and as having no valid DRC. 661 */ 662 dynamic_memory[0] = cpu_to_be32(addr >> 32); 663 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 664 dynamic_memory[2] = cpu_to_be32(0); 665 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 666 dynamic_memory[4] = cpu_to_be32(-1); 667 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 668 SPAPR_LMB_FLAGS_DRC_INVALID); 669 } 670 671 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 672 } 673 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 674 if (ret < 0) { 675 goto out; 676 } 677 678 /* ibm,associativity-lookup-arrays */ 679 cur_index = int_buf; 680 int_buf[0] = cpu_to_be32(nr_nodes); 681 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 682 cur_index += 2; 683 for (i = 0; i < nr_nodes; i++) { 684 uint32_t associativity[] = { 685 cpu_to_be32(0x0), 686 cpu_to_be32(0x0), 687 cpu_to_be32(0x0), 688 cpu_to_be32(i) 689 }; 690 memcpy(cur_index, associativity, sizeof(associativity)); 691 cur_index += 4; 692 } 693 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 694 (cur_index - int_buf) * sizeof(uint32_t)); 695 out: 696 g_free(int_buf); 697 return ret; 698 } 699 700 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 701 sPAPROptionVector *ov5_updates) 702 { 703 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 704 int ret = 0, offset; 705 706 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 707 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 708 g_assert(smc->dr_lmb_enabled); 709 ret = spapr_populate_drconf_memory(spapr, fdt); 710 if (ret) { 711 goto out; 712 } 713 } 714 715 offset = fdt_path_offset(fdt, "/chosen"); 716 if (offset < 0) { 717 offset = fdt_add_subnode(fdt, 0, "chosen"); 718 if (offset < 0) { 719 return offset; 720 } 721 } 722 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 723 "ibm,architecture-vec-5"); 724 725 out: 726 return ret; 727 } 728 729 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 730 target_ulong addr, target_ulong size, 731 sPAPROptionVector *ov5_updates) 732 { 733 void *fdt, *fdt_skel; 734 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 735 736 size -= sizeof(hdr); 737 738 /* Create sceleton */ 739 fdt_skel = g_malloc0(size); 740 _FDT((fdt_create(fdt_skel, size))); 741 _FDT((fdt_begin_node(fdt_skel, ""))); 742 _FDT((fdt_end_node(fdt_skel))); 743 _FDT((fdt_finish(fdt_skel))); 744 fdt = g_malloc0(size); 745 _FDT((fdt_open_into(fdt_skel, fdt, size))); 746 g_free(fdt_skel); 747 748 /* Fixup cpu nodes */ 749 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 750 751 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 752 return -1; 753 } 754 755 /* Pack resulting tree */ 756 _FDT((fdt_pack(fdt))); 757 758 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 759 trace_spapr_cas_failed(size); 760 return -1; 761 } 762 763 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 764 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 765 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 766 g_free(fdt); 767 768 return 0; 769 } 770 771 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 772 { 773 int rtas; 774 GString *hypertas = g_string_sized_new(256); 775 GString *qemu_hypertas = g_string_sized_new(256); 776 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 777 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 778 memory_region_size(&spapr->hotplug_memory.mr); 779 uint32_t lrdr_capacity[] = { 780 cpu_to_be32(max_hotplug_addr >> 32), 781 cpu_to_be32(max_hotplug_addr & 0xffffffff), 782 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 783 cpu_to_be32(max_cpus / smp_threads), 784 }; 785 786 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 787 788 /* hypertas */ 789 add_str(hypertas, "hcall-pft"); 790 add_str(hypertas, "hcall-term"); 791 add_str(hypertas, "hcall-dabr"); 792 add_str(hypertas, "hcall-interrupt"); 793 add_str(hypertas, "hcall-tce"); 794 add_str(hypertas, "hcall-vio"); 795 add_str(hypertas, "hcall-splpar"); 796 add_str(hypertas, "hcall-bulk"); 797 add_str(hypertas, "hcall-set-mode"); 798 add_str(hypertas, "hcall-sprg0"); 799 add_str(hypertas, "hcall-copy"); 800 add_str(hypertas, "hcall-debug"); 801 add_str(qemu_hypertas, "hcall-memop1"); 802 803 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 804 add_str(hypertas, "hcall-multi-tce"); 805 } 806 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 807 hypertas->str, hypertas->len)); 808 g_string_free(hypertas, TRUE); 809 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 810 qemu_hypertas->str, qemu_hypertas->len)); 811 g_string_free(qemu_hypertas, TRUE); 812 813 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 814 refpoints, sizeof(refpoints))); 815 816 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 817 RTAS_ERROR_LOG_MAX)); 818 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 819 RTAS_EVENT_SCAN_RATE)); 820 821 if (msi_nonbroken) { 822 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 823 } 824 825 /* 826 * According to PAPR, rtas ibm,os-term does not guarantee a return 827 * back to the guest cpu. 828 * 829 * While an additional ibm,extended-os-term property indicates 830 * that rtas call return will always occur. Set this property. 831 */ 832 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 833 834 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 835 lrdr_capacity, sizeof(lrdr_capacity))); 836 837 spapr_dt_rtas_tokens(fdt, rtas); 838 } 839 840 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 841 { 842 MachineState *machine = MACHINE(spapr); 843 int chosen; 844 const char *boot_device = machine->boot_order; 845 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 846 size_t cb = 0; 847 char *bootlist = get_boot_devices_list(&cb, true); 848 849 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 850 851 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 852 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 853 spapr->initrd_base)); 854 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 855 spapr->initrd_base + spapr->initrd_size)); 856 857 if (spapr->kernel_size) { 858 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 859 cpu_to_be64(spapr->kernel_size) }; 860 861 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 862 &kprop, sizeof(kprop))); 863 if (spapr->kernel_le) { 864 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 865 } 866 } 867 if (boot_menu) { 868 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 869 } 870 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 871 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 872 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 873 874 if (cb && bootlist) { 875 int i; 876 877 for (i = 0; i < cb; i++) { 878 if (bootlist[i] == '\n') { 879 bootlist[i] = ' '; 880 } 881 } 882 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 883 } 884 885 if (boot_device && strlen(boot_device)) { 886 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 887 } 888 889 if (!spapr->has_graphics && stdout_path) { 890 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 891 } 892 893 g_free(stdout_path); 894 g_free(bootlist); 895 } 896 897 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 898 { 899 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 900 * KVM to work under pHyp with some guest co-operation */ 901 int hypervisor; 902 uint8_t hypercall[16]; 903 904 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 905 /* indicate KVM hypercall interface */ 906 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 907 if (kvmppc_has_cap_fixup_hcalls()) { 908 /* 909 * Older KVM versions with older guest kernels were broken 910 * with the magic page, don't allow the guest to map it. 911 */ 912 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 913 sizeof(hypercall))) { 914 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 915 hypercall, sizeof(hypercall))); 916 } 917 } 918 } 919 920 static void *spapr_build_fdt(sPAPRMachineState *spapr, 921 hwaddr rtas_addr, 922 hwaddr rtas_size) 923 { 924 MachineState *machine = MACHINE(qdev_get_machine()); 925 MachineClass *mc = MACHINE_GET_CLASS(machine); 926 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 927 int ret; 928 void *fdt; 929 sPAPRPHBState *phb; 930 char *buf; 931 932 fdt = g_malloc0(FDT_MAX_SIZE); 933 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 934 935 /* Root node */ 936 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 937 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 938 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 939 940 /* 941 * Add info to guest to indentify which host is it being run on 942 * and what is the uuid of the guest 943 */ 944 if (kvmppc_get_host_model(&buf)) { 945 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 946 g_free(buf); 947 } 948 if (kvmppc_get_host_serial(&buf)) { 949 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 950 g_free(buf); 951 } 952 953 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 954 955 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 956 if (qemu_uuid_set) { 957 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 958 } 959 g_free(buf); 960 961 if (qemu_get_vm_name()) { 962 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 963 qemu_get_vm_name())); 964 } 965 966 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 967 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 968 969 /* /interrupt controller */ 970 spapr_dt_xics(spapr->xics->nr_servers, fdt, PHANDLE_XICP); 971 972 ret = spapr_populate_memory(spapr, fdt); 973 if (ret < 0) { 974 error_report("couldn't setup memory nodes in fdt"); 975 exit(1); 976 } 977 978 /* /vdevice */ 979 spapr_dt_vdevice(spapr->vio_bus, fdt); 980 981 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 982 ret = spapr_rng_populate_dt(fdt); 983 if (ret < 0) { 984 error_report("could not set up rng device in the fdt"); 985 exit(1); 986 } 987 } 988 989 QLIST_FOREACH(phb, &spapr->phbs, list) { 990 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 991 if (ret < 0) { 992 error_report("couldn't setup PCI devices in fdt"); 993 exit(1); 994 } 995 } 996 997 /* cpus */ 998 spapr_populate_cpus_dt_node(fdt, spapr); 999 1000 if (smc->dr_lmb_enabled) { 1001 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1002 } 1003 1004 if (mc->has_hotpluggable_cpus) { 1005 int offset = fdt_path_offset(fdt, "/cpus"); 1006 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1007 SPAPR_DR_CONNECTOR_TYPE_CPU); 1008 if (ret < 0) { 1009 error_report("Couldn't set up CPU DR device tree properties"); 1010 exit(1); 1011 } 1012 } 1013 1014 /* /event-sources */ 1015 spapr_dt_events(spapr, fdt); 1016 1017 /* /rtas */ 1018 spapr_dt_rtas(spapr, fdt); 1019 1020 /* /chosen */ 1021 spapr_dt_chosen(spapr, fdt); 1022 1023 /* /hypervisor */ 1024 if (kvm_enabled()) { 1025 spapr_dt_hypervisor(spapr, fdt); 1026 } 1027 1028 /* Build memory reserve map */ 1029 if (spapr->kernel_size) { 1030 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1031 } 1032 if (spapr->initrd_size) { 1033 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1034 } 1035 1036 /* ibm,client-architecture-support updates */ 1037 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1038 if (ret < 0) { 1039 error_report("couldn't setup CAS properties fdt"); 1040 exit(1); 1041 } 1042 1043 return fdt; 1044 } 1045 1046 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1047 { 1048 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1049 } 1050 1051 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1052 PowerPCCPU *cpu) 1053 { 1054 CPUPPCState *env = &cpu->env; 1055 1056 /* The TCG path should also be holding the BQL at this point */ 1057 g_assert(qemu_mutex_iothread_locked()); 1058 1059 if (msr_pr) { 1060 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1061 env->gpr[3] = H_PRIVILEGE; 1062 } else { 1063 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1064 } 1065 } 1066 1067 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1068 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1069 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1070 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1071 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1072 1073 /* 1074 * Get the fd to access the kernel htab, re-opening it if necessary 1075 */ 1076 static int get_htab_fd(sPAPRMachineState *spapr) 1077 { 1078 if (spapr->htab_fd >= 0) { 1079 return spapr->htab_fd; 1080 } 1081 1082 spapr->htab_fd = kvmppc_get_htab_fd(false); 1083 if (spapr->htab_fd < 0) { 1084 error_report("Unable to open fd for reading hash table from KVM: %s", 1085 strerror(errno)); 1086 } 1087 1088 return spapr->htab_fd; 1089 } 1090 1091 static void close_htab_fd(sPAPRMachineState *spapr) 1092 { 1093 if (spapr->htab_fd >= 0) { 1094 close(spapr->htab_fd); 1095 } 1096 spapr->htab_fd = -1; 1097 } 1098 1099 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1100 { 1101 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1102 1103 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1104 } 1105 1106 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1107 hwaddr ptex, int n) 1108 { 1109 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1110 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1111 1112 if (!spapr->htab) { 1113 /* 1114 * HTAB is controlled by KVM. Fetch into temporary buffer 1115 */ 1116 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1117 kvmppc_read_hptes(hptes, ptex, n); 1118 return hptes; 1119 } 1120 1121 /* 1122 * HTAB is controlled by QEMU. Just point to the internally 1123 * accessible PTEG. 1124 */ 1125 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1126 } 1127 1128 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1129 const ppc_hash_pte64_t *hptes, 1130 hwaddr ptex, int n) 1131 { 1132 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1133 1134 if (!spapr->htab) { 1135 g_free((void *)hptes); 1136 } 1137 1138 /* Nothing to do for qemu managed HPT */ 1139 } 1140 1141 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1142 uint64_t pte0, uint64_t pte1) 1143 { 1144 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1145 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1146 1147 if (!spapr->htab) { 1148 kvmppc_write_hpte(ptex, pte0, pte1); 1149 } else { 1150 stq_p(spapr->htab + offset, pte0); 1151 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1152 } 1153 } 1154 1155 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1156 { 1157 int shift; 1158 1159 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1160 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1161 * that's much more than is needed for Linux guests */ 1162 shift = ctz64(pow2ceil(ramsize)) - 7; 1163 shift = MAX(shift, 18); /* Minimum architected size */ 1164 shift = MIN(shift, 46); /* Maximum architected size */ 1165 return shift; 1166 } 1167 1168 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1169 Error **errp) 1170 { 1171 long rc; 1172 1173 /* Clean up any HPT info from a previous boot */ 1174 g_free(spapr->htab); 1175 spapr->htab = NULL; 1176 spapr->htab_shift = 0; 1177 close_htab_fd(spapr); 1178 1179 rc = kvmppc_reset_htab(shift); 1180 if (rc < 0) { 1181 /* kernel-side HPT needed, but couldn't allocate one */ 1182 error_setg_errno(errp, errno, 1183 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1184 shift); 1185 /* This is almost certainly fatal, but if the caller really 1186 * wants to carry on with shift == 0, it's welcome to try */ 1187 } else if (rc > 0) { 1188 /* kernel-side HPT allocated */ 1189 if (rc != shift) { 1190 error_setg(errp, 1191 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1192 shift, rc); 1193 } 1194 1195 spapr->htab_shift = shift; 1196 spapr->htab = NULL; 1197 } else { 1198 /* kernel-side HPT not needed, allocate in userspace instead */ 1199 size_t size = 1ULL << shift; 1200 int i; 1201 1202 spapr->htab = qemu_memalign(size, size); 1203 if (!spapr->htab) { 1204 error_setg_errno(errp, errno, 1205 "Could not allocate HPT of order %d", shift); 1206 return; 1207 } 1208 1209 memset(spapr->htab, 0, size); 1210 spapr->htab_shift = shift; 1211 1212 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1213 DIRTY_HPTE(HPTE(spapr->htab, i)); 1214 } 1215 } 1216 } 1217 1218 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1219 { 1220 bool matched = false; 1221 1222 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1223 matched = true; 1224 } 1225 1226 if (!matched) { 1227 error_report("Device %s is not supported by this machine yet.", 1228 qdev_fw_name(DEVICE(sbdev))); 1229 exit(1); 1230 } 1231 } 1232 1233 static void ppc_spapr_reset(void) 1234 { 1235 MachineState *machine = MACHINE(qdev_get_machine()); 1236 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1237 PowerPCCPU *first_ppc_cpu; 1238 uint32_t rtas_limit; 1239 hwaddr rtas_addr, fdt_addr; 1240 void *fdt; 1241 int rc; 1242 1243 /* Check for unknown sysbus devices */ 1244 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1245 1246 /* Allocate and/or reset the hash page table */ 1247 spapr_reallocate_hpt(spapr, 1248 spapr_hpt_shift_for_ramsize(machine->maxram_size), 1249 &error_fatal); 1250 1251 /* Update the RMA size if necessary */ 1252 if (spapr->vrma_adjust) { 1253 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1254 spapr->htab_shift); 1255 } 1256 1257 qemu_devices_reset(); 1258 1259 /* 1260 * We place the device tree and RTAS just below either the top of the RMA, 1261 * or just below 2GB, whichever is lowere, so that it can be 1262 * processed with 32-bit real mode code if necessary 1263 */ 1264 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1265 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1266 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1267 1268 /* if this reset wasn't generated by CAS, we should reset our 1269 * negotiated options and start from scratch */ 1270 if (!spapr->cas_reboot) { 1271 spapr_ovec_cleanup(spapr->ov5_cas); 1272 spapr->ov5_cas = spapr_ovec_new(); 1273 } 1274 1275 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1276 1277 spapr_load_rtas(spapr, fdt, rtas_addr); 1278 1279 rc = fdt_pack(fdt); 1280 1281 /* Should only fail if we've built a corrupted tree */ 1282 assert(rc == 0); 1283 1284 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1285 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1286 fdt_totalsize(fdt), FDT_MAX_SIZE); 1287 exit(1); 1288 } 1289 1290 /* Load the fdt */ 1291 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1292 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1293 g_free(fdt); 1294 1295 /* Set up the entry state */ 1296 first_ppc_cpu = POWERPC_CPU(first_cpu); 1297 first_ppc_cpu->env.gpr[3] = fdt_addr; 1298 first_ppc_cpu->env.gpr[5] = 0; 1299 first_cpu->halted = 0; 1300 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1301 1302 spapr->cas_reboot = false; 1303 } 1304 1305 static void spapr_create_nvram(sPAPRMachineState *spapr) 1306 { 1307 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1308 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1309 1310 if (dinfo) { 1311 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1312 &error_fatal); 1313 } 1314 1315 qdev_init_nofail(dev); 1316 1317 spapr->nvram = (struct sPAPRNVRAM *)dev; 1318 } 1319 1320 static void spapr_rtc_create(sPAPRMachineState *spapr) 1321 { 1322 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); 1323 1324 qdev_init_nofail(dev); 1325 spapr->rtc = dev; 1326 1327 object_property_add_alias(qdev_get_machine(), "rtc-time", 1328 OBJECT(spapr->rtc), "date", NULL); 1329 } 1330 1331 /* Returns whether we want to use VGA or not */ 1332 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1333 { 1334 switch (vga_interface_type) { 1335 case VGA_NONE: 1336 return false; 1337 case VGA_DEVICE: 1338 return true; 1339 case VGA_STD: 1340 case VGA_VIRTIO: 1341 return pci_vga_init(pci_bus) != NULL; 1342 default: 1343 error_setg(errp, 1344 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1345 return false; 1346 } 1347 } 1348 1349 static int spapr_post_load(void *opaque, int version_id) 1350 { 1351 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1352 int err = 0; 1353 1354 /* In earlier versions, there was no separate qdev for the PAPR 1355 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1356 * So when migrating from those versions, poke the incoming offset 1357 * value into the RTC device */ 1358 if (version_id < 3) { 1359 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); 1360 } 1361 1362 return err; 1363 } 1364 1365 static bool version_before_3(void *opaque, int version_id) 1366 { 1367 return version_id < 3; 1368 } 1369 1370 static bool spapr_ov5_cas_needed(void *opaque) 1371 { 1372 sPAPRMachineState *spapr = opaque; 1373 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1374 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1375 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1376 bool cas_needed; 1377 1378 /* Prior to the introduction of sPAPROptionVector, we had two option 1379 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1380 * Both of these options encode machine topology into the device-tree 1381 * in such a way that the now-booted OS should still be able to interact 1382 * appropriately with QEMU regardless of what options were actually 1383 * negotiatied on the source side. 1384 * 1385 * As such, we can avoid migrating the CAS-negotiated options if these 1386 * are the only options available on the current machine/platform. 1387 * Since these are the only options available for pseries-2.7 and 1388 * earlier, this allows us to maintain old->new/new->old migration 1389 * compatibility. 1390 * 1391 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1392 * via default pseries-2.8 machines and explicit command-line parameters. 1393 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1394 * of the actual CAS-negotiated values to continue working properly. For 1395 * example, availability of memory unplug depends on knowing whether 1396 * OV5_HP_EVT was negotiated via CAS. 1397 * 1398 * Thus, for any cases where the set of available CAS-negotiatable 1399 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1400 * include the CAS-negotiated options in the migration stream. 1401 */ 1402 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1403 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1404 1405 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1406 * the mask itself since in the future it's possible "legacy" bits may be 1407 * removed via machine options, which could generate a false positive 1408 * that breaks migration. 1409 */ 1410 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1411 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1412 1413 spapr_ovec_cleanup(ov5_mask); 1414 spapr_ovec_cleanup(ov5_legacy); 1415 spapr_ovec_cleanup(ov5_removed); 1416 1417 return cas_needed; 1418 } 1419 1420 static const VMStateDescription vmstate_spapr_ov5_cas = { 1421 .name = "spapr_option_vector_ov5_cas", 1422 .version_id = 1, 1423 .minimum_version_id = 1, 1424 .needed = spapr_ov5_cas_needed, 1425 .fields = (VMStateField[]) { 1426 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1427 vmstate_spapr_ovec, sPAPROptionVector), 1428 VMSTATE_END_OF_LIST() 1429 }, 1430 }; 1431 1432 static const VMStateDescription vmstate_spapr = { 1433 .name = "spapr", 1434 .version_id = 3, 1435 .minimum_version_id = 1, 1436 .post_load = spapr_post_load, 1437 .fields = (VMStateField[]) { 1438 /* used to be @next_irq */ 1439 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1440 1441 /* RTC offset */ 1442 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1443 1444 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1445 VMSTATE_END_OF_LIST() 1446 }, 1447 .subsections = (const VMStateDescription*[]) { 1448 &vmstate_spapr_ov5_cas, 1449 NULL 1450 } 1451 }; 1452 1453 static int htab_save_setup(QEMUFile *f, void *opaque) 1454 { 1455 sPAPRMachineState *spapr = opaque; 1456 1457 /* "Iteration" header */ 1458 qemu_put_be32(f, spapr->htab_shift); 1459 1460 if (spapr->htab) { 1461 spapr->htab_save_index = 0; 1462 spapr->htab_first_pass = true; 1463 } else { 1464 assert(kvm_enabled()); 1465 } 1466 1467 1468 return 0; 1469 } 1470 1471 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1472 int64_t max_ns) 1473 { 1474 bool has_timeout = max_ns != -1; 1475 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1476 int index = spapr->htab_save_index; 1477 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1478 1479 assert(spapr->htab_first_pass); 1480 1481 do { 1482 int chunkstart; 1483 1484 /* Consume invalid HPTEs */ 1485 while ((index < htabslots) 1486 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1487 index++; 1488 CLEAN_HPTE(HPTE(spapr->htab, index)); 1489 } 1490 1491 /* Consume valid HPTEs */ 1492 chunkstart = index; 1493 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1494 && HPTE_VALID(HPTE(spapr->htab, index))) { 1495 index++; 1496 CLEAN_HPTE(HPTE(spapr->htab, index)); 1497 } 1498 1499 if (index > chunkstart) { 1500 int n_valid = index - chunkstart; 1501 1502 qemu_put_be32(f, chunkstart); 1503 qemu_put_be16(f, n_valid); 1504 qemu_put_be16(f, 0); 1505 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1506 HASH_PTE_SIZE_64 * n_valid); 1507 1508 if (has_timeout && 1509 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1510 break; 1511 } 1512 } 1513 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1514 1515 if (index >= htabslots) { 1516 assert(index == htabslots); 1517 index = 0; 1518 spapr->htab_first_pass = false; 1519 } 1520 spapr->htab_save_index = index; 1521 } 1522 1523 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1524 int64_t max_ns) 1525 { 1526 bool final = max_ns < 0; 1527 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1528 int examined = 0, sent = 0; 1529 int index = spapr->htab_save_index; 1530 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1531 1532 assert(!spapr->htab_first_pass); 1533 1534 do { 1535 int chunkstart, invalidstart; 1536 1537 /* Consume non-dirty HPTEs */ 1538 while ((index < htabslots) 1539 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1540 index++; 1541 examined++; 1542 } 1543 1544 chunkstart = index; 1545 /* Consume valid dirty HPTEs */ 1546 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1547 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1548 && HPTE_VALID(HPTE(spapr->htab, index))) { 1549 CLEAN_HPTE(HPTE(spapr->htab, index)); 1550 index++; 1551 examined++; 1552 } 1553 1554 invalidstart = index; 1555 /* Consume invalid dirty HPTEs */ 1556 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1557 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1558 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1559 CLEAN_HPTE(HPTE(spapr->htab, index)); 1560 index++; 1561 examined++; 1562 } 1563 1564 if (index > chunkstart) { 1565 int n_valid = invalidstart - chunkstart; 1566 int n_invalid = index - invalidstart; 1567 1568 qemu_put_be32(f, chunkstart); 1569 qemu_put_be16(f, n_valid); 1570 qemu_put_be16(f, n_invalid); 1571 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1572 HASH_PTE_SIZE_64 * n_valid); 1573 sent += index - chunkstart; 1574 1575 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1576 break; 1577 } 1578 } 1579 1580 if (examined >= htabslots) { 1581 break; 1582 } 1583 1584 if (index >= htabslots) { 1585 assert(index == htabslots); 1586 index = 0; 1587 } 1588 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1589 1590 if (index >= htabslots) { 1591 assert(index == htabslots); 1592 index = 0; 1593 } 1594 1595 spapr->htab_save_index = index; 1596 1597 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1598 } 1599 1600 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1601 #define MAX_KVM_BUF_SIZE 2048 1602 1603 static int htab_save_iterate(QEMUFile *f, void *opaque) 1604 { 1605 sPAPRMachineState *spapr = opaque; 1606 int fd; 1607 int rc = 0; 1608 1609 /* Iteration header */ 1610 qemu_put_be32(f, 0); 1611 1612 if (!spapr->htab) { 1613 assert(kvm_enabled()); 1614 1615 fd = get_htab_fd(spapr); 1616 if (fd < 0) { 1617 return fd; 1618 } 1619 1620 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1621 if (rc < 0) { 1622 return rc; 1623 } 1624 } else if (spapr->htab_first_pass) { 1625 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1626 } else { 1627 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1628 } 1629 1630 /* End marker */ 1631 qemu_put_be32(f, 0); 1632 qemu_put_be16(f, 0); 1633 qemu_put_be16(f, 0); 1634 1635 return rc; 1636 } 1637 1638 static int htab_save_complete(QEMUFile *f, void *opaque) 1639 { 1640 sPAPRMachineState *spapr = opaque; 1641 int fd; 1642 1643 /* Iteration header */ 1644 qemu_put_be32(f, 0); 1645 1646 if (!spapr->htab) { 1647 int rc; 1648 1649 assert(kvm_enabled()); 1650 1651 fd = get_htab_fd(spapr); 1652 if (fd < 0) { 1653 return fd; 1654 } 1655 1656 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1657 if (rc < 0) { 1658 return rc; 1659 } 1660 } else { 1661 if (spapr->htab_first_pass) { 1662 htab_save_first_pass(f, spapr, -1); 1663 } 1664 htab_save_later_pass(f, spapr, -1); 1665 } 1666 1667 /* End marker */ 1668 qemu_put_be32(f, 0); 1669 qemu_put_be16(f, 0); 1670 qemu_put_be16(f, 0); 1671 1672 return 0; 1673 } 1674 1675 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1676 { 1677 sPAPRMachineState *spapr = opaque; 1678 uint32_t section_hdr; 1679 int fd = -1; 1680 1681 if (version_id < 1 || version_id > 1) { 1682 error_report("htab_load() bad version"); 1683 return -EINVAL; 1684 } 1685 1686 section_hdr = qemu_get_be32(f); 1687 1688 if (section_hdr) { 1689 Error *local_err = NULL; 1690 1691 /* First section gives the htab size */ 1692 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1693 if (local_err) { 1694 error_report_err(local_err); 1695 return -EINVAL; 1696 } 1697 return 0; 1698 } 1699 1700 if (!spapr->htab) { 1701 assert(kvm_enabled()); 1702 1703 fd = kvmppc_get_htab_fd(true); 1704 if (fd < 0) { 1705 error_report("Unable to open fd to restore KVM hash table: %s", 1706 strerror(errno)); 1707 } 1708 } 1709 1710 while (true) { 1711 uint32_t index; 1712 uint16_t n_valid, n_invalid; 1713 1714 index = qemu_get_be32(f); 1715 n_valid = qemu_get_be16(f); 1716 n_invalid = qemu_get_be16(f); 1717 1718 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1719 /* End of Stream */ 1720 break; 1721 } 1722 1723 if ((index + n_valid + n_invalid) > 1724 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1725 /* Bad index in stream */ 1726 error_report( 1727 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1728 index, n_valid, n_invalid, spapr->htab_shift); 1729 return -EINVAL; 1730 } 1731 1732 if (spapr->htab) { 1733 if (n_valid) { 1734 qemu_get_buffer(f, HPTE(spapr->htab, index), 1735 HASH_PTE_SIZE_64 * n_valid); 1736 } 1737 if (n_invalid) { 1738 memset(HPTE(spapr->htab, index + n_valid), 0, 1739 HASH_PTE_SIZE_64 * n_invalid); 1740 } 1741 } else { 1742 int rc; 1743 1744 assert(fd >= 0); 1745 1746 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1747 if (rc < 0) { 1748 return rc; 1749 } 1750 } 1751 } 1752 1753 if (!spapr->htab) { 1754 assert(fd >= 0); 1755 close(fd); 1756 } 1757 1758 return 0; 1759 } 1760 1761 static void htab_cleanup(void *opaque) 1762 { 1763 sPAPRMachineState *spapr = opaque; 1764 1765 close_htab_fd(spapr); 1766 } 1767 1768 static SaveVMHandlers savevm_htab_handlers = { 1769 .save_live_setup = htab_save_setup, 1770 .save_live_iterate = htab_save_iterate, 1771 .save_live_complete_precopy = htab_save_complete, 1772 .cleanup = htab_cleanup, 1773 .load_state = htab_load, 1774 }; 1775 1776 static void spapr_boot_set(void *opaque, const char *boot_device, 1777 Error **errp) 1778 { 1779 MachineState *machine = MACHINE(qdev_get_machine()); 1780 machine->boot_order = g_strdup(boot_device); 1781 } 1782 1783 /* 1784 * Reset routine for LMB DR devices. 1785 * 1786 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1787 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1788 * when it walks all its children devices. LMB devices reset occurs 1789 * as part of spapr_ppc_reset(). 1790 */ 1791 static void spapr_drc_reset(void *opaque) 1792 { 1793 sPAPRDRConnector *drc = opaque; 1794 DeviceState *d = DEVICE(drc); 1795 1796 if (d) { 1797 device_reset(d); 1798 } 1799 } 1800 1801 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1802 { 1803 MachineState *machine = MACHINE(spapr); 1804 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1805 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1806 int i; 1807 1808 for (i = 0; i < nr_lmbs; i++) { 1809 sPAPRDRConnector *drc; 1810 uint64_t addr; 1811 1812 addr = i * lmb_size + spapr->hotplug_memory.base; 1813 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, 1814 addr/lmb_size); 1815 qemu_register_reset(spapr_drc_reset, drc); 1816 } 1817 } 1818 1819 /* 1820 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1821 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1822 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1823 */ 1824 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 1825 { 1826 int i; 1827 1828 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1829 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 1830 " is not aligned to %llu MiB", 1831 machine->ram_size, 1832 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1833 return; 1834 } 1835 1836 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1837 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 1838 " is not aligned to %llu MiB", 1839 machine->ram_size, 1840 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1841 return; 1842 } 1843 1844 for (i = 0; i < nb_numa_nodes; i++) { 1845 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 1846 error_setg(errp, 1847 "Node %d memory size 0x%" PRIx64 1848 " is not aligned to %llu MiB", 1849 i, numa_info[i].node_mem, 1850 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1851 return; 1852 } 1853 } 1854 } 1855 1856 /* find cpu slot in machine->possible_cpus by core_id */ 1857 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 1858 { 1859 int index = id / smp_threads; 1860 1861 if (index >= ms->possible_cpus->len) { 1862 return NULL; 1863 } 1864 if (idx) { 1865 *idx = index; 1866 } 1867 return &ms->possible_cpus->cpus[index]; 1868 } 1869 1870 static void spapr_init_cpus(sPAPRMachineState *spapr) 1871 { 1872 MachineState *machine = MACHINE(spapr); 1873 MachineClass *mc = MACHINE_GET_CLASS(machine); 1874 char *type = spapr_get_cpu_core_type(machine->cpu_model); 1875 int smt = kvmppc_smt_threads(); 1876 const CPUArchIdList *possible_cpus; 1877 int boot_cores_nr = smp_cpus / smp_threads; 1878 int i; 1879 1880 if (!type) { 1881 error_report("Unable to find sPAPR CPU Core definition"); 1882 exit(1); 1883 } 1884 1885 possible_cpus = mc->possible_cpu_arch_ids(machine); 1886 if (mc->has_hotpluggable_cpus) { 1887 if (smp_cpus % smp_threads) { 1888 error_report("smp_cpus (%u) must be multiple of threads (%u)", 1889 smp_cpus, smp_threads); 1890 exit(1); 1891 } 1892 if (max_cpus % smp_threads) { 1893 error_report("max_cpus (%u) must be multiple of threads (%u)", 1894 max_cpus, smp_threads); 1895 exit(1); 1896 } 1897 } else { 1898 if (max_cpus != smp_cpus) { 1899 error_report("This machine version does not support CPU hotplug"); 1900 exit(1); 1901 } 1902 boot_cores_nr = possible_cpus->len; 1903 } 1904 1905 for (i = 0; i < possible_cpus->len; i++) { 1906 int core_id = i * smp_threads; 1907 1908 if (mc->has_hotpluggable_cpus) { 1909 sPAPRDRConnector *drc = 1910 spapr_dr_connector_new(OBJECT(spapr), 1911 SPAPR_DR_CONNECTOR_TYPE_CPU, 1912 (core_id / smp_threads) * smt); 1913 1914 qemu_register_reset(spapr_drc_reset, drc); 1915 } 1916 1917 if (i < boot_cores_nr) { 1918 Object *core = object_new(type); 1919 int nr_threads = smp_threads; 1920 1921 /* Handle the partially filled core for older machine types */ 1922 if ((i + 1) * smp_threads >= smp_cpus) { 1923 nr_threads = smp_cpus - i * smp_threads; 1924 } 1925 1926 object_property_set_int(core, nr_threads, "nr-threads", 1927 &error_fatal); 1928 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 1929 &error_fatal); 1930 object_property_set_bool(core, true, "realized", &error_fatal); 1931 } 1932 } 1933 g_free(type); 1934 } 1935 1936 /* pSeries LPAR / sPAPR hardware init */ 1937 static void ppc_spapr_init(MachineState *machine) 1938 { 1939 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1940 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1941 const char *kernel_filename = machine->kernel_filename; 1942 const char *initrd_filename = machine->initrd_filename; 1943 PCIHostState *phb; 1944 int i; 1945 MemoryRegion *sysmem = get_system_memory(); 1946 MemoryRegion *ram = g_new(MemoryRegion, 1); 1947 MemoryRegion *rma_region; 1948 void *rma = NULL; 1949 hwaddr rma_alloc_size; 1950 hwaddr node0_size = spapr_node0_size(); 1951 long load_limit, fw_size; 1952 char *filename; 1953 int smt = kvmppc_smt_threads(); 1954 1955 msi_nonbroken = true; 1956 1957 QLIST_INIT(&spapr->phbs); 1958 1959 /* Allocate RMA if necessary */ 1960 rma_alloc_size = kvmppc_alloc_rma(&rma); 1961 1962 if (rma_alloc_size == -1) { 1963 error_report("Unable to create RMA"); 1964 exit(1); 1965 } 1966 1967 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1968 spapr->rma_size = rma_alloc_size; 1969 } else { 1970 spapr->rma_size = node0_size; 1971 1972 /* With KVM, we don't actually know whether KVM supports an 1973 * unbounded RMA (PR KVM) or is limited by the hash table size 1974 * (HV KVM using VRMA), so we always assume the latter 1975 * 1976 * In that case, we also limit the initial allocations for RTAS 1977 * etc... to 256M since we have no way to know what the VRMA size 1978 * is going to be as it depends on the size of the hash table 1979 * isn't determined yet. 1980 */ 1981 if (kvm_enabled()) { 1982 spapr->vrma_adjust = 1; 1983 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1984 } 1985 1986 /* Actually we don't support unbounded RMA anymore since we 1987 * added proper emulation of HV mode. The max we can get is 1988 * 16G which also happens to be what we configure for PAPR 1989 * mode so make sure we don't do anything bigger than that 1990 */ 1991 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 1992 } 1993 1994 if (spapr->rma_size > node0_size) { 1995 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 1996 spapr->rma_size); 1997 exit(1); 1998 } 1999 2000 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2001 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2002 2003 /* Set up Interrupt Controller before we create the VCPUs */ 2004 spapr->xics = xics_system_init(machine, 2005 DIV_ROUND_UP(max_cpus * smt, smp_threads), 2006 XICS_IRQS_SPAPR, &error_fatal); 2007 2008 /* Set up containers for ibm,client-set-architecture negotiated options */ 2009 spapr->ov5 = spapr_ovec_new(); 2010 spapr->ov5_cas = spapr_ovec_new(); 2011 2012 if (smc->dr_lmb_enabled) { 2013 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2014 spapr_validate_node_memory(machine, &error_fatal); 2015 } 2016 2017 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2018 2019 /* advertise support for dedicated HP event source to guests */ 2020 if (spapr->use_hotplug_event_source) { 2021 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2022 } 2023 2024 /* init CPUs */ 2025 if (machine->cpu_model == NULL) { 2026 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; 2027 } 2028 2029 ppc_cpu_parse_features(machine->cpu_model); 2030 2031 spapr_init_cpus(spapr); 2032 2033 if (kvm_enabled()) { 2034 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2035 kvmppc_enable_logical_ci_hcalls(); 2036 kvmppc_enable_set_mode_hcall(); 2037 2038 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2039 kvmppc_enable_clear_ref_mod_hcalls(); 2040 } 2041 2042 /* allocate RAM */ 2043 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2044 machine->ram_size); 2045 memory_region_add_subregion(sysmem, 0, ram); 2046 2047 if (rma_alloc_size && rma) { 2048 rma_region = g_new(MemoryRegion, 1); 2049 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 2050 rma_alloc_size, rma); 2051 vmstate_register_ram_global(rma_region); 2052 memory_region_add_subregion(sysmem, 0, rma_region); 2053 } 2054 2055 /* initialize hotplug memory address space */ 2056 if (machine->ram_size < machine->maxram_size) { 2057 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2058 /* 2059 * Limit the number of hotpluggable memory slots to half the number 2060 * slots that KVM supports, leaving the other half for PCI and other 2061 * devices. However ensure that number of slots doesn't drop below 32. 2062 */ 2063 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2064 SPAPR_MAX_RAM_SLOTS; 2065 2066 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2067 max_memslots = SPAPR_MAX_RAM_SLOTS; 2068 } 2069 if (machine->ram_slots > max_memslots) { 2070 error_report("Specified number of memory slots %" 2071 PRIu64" exceeds max supported %d", 2072 machine->ram_slots, max_memslots); 2073 exit(1); 2074 } 2075 2076 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2077 SPAPR_HOTPLUG_MEM_ALIGN); 2078 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2079 "hotplug-memory", hotplug_mem_size); 2080 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2081 &spapr->hotplug_memory.mr); 2082 } 2083 2084 if (smc->dr_lmb_enabled) { 2085 spapr_create_lmb_dr_connectors(spapr); 2086 } 2087 2088 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2089 if (!filename) { 2090 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2091 exit(1); 2092 } 2093 spapr->rtas_size = get_image_size(filename); 2094 if (spapr->rtas_size < 0) { 2095 error_report("Could not get size of LPAR rtas '%s'", filename); 2096 exit(1); 2097 } 2098 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2099 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2100 error_report("Could not load LPAR rtas '%s'", filename); 2101 exit(1); 2102 } 2103 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2104 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2105 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2106 exit(1); 2107 } 2108 g_free(filename); 2109 2110 /* Set up RTAS event infrastructure */ 2111 spapr_events_init(spapr); 2112 2113 /* Set up the RTC RTAS interfaces */ 2114 spapr_rtc_create(spapr); 2115 2116 /* Set up VIO bus */ 2117 spapr->vio_bus = spapr_vio_bus_init(); 2118 2119 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 2120 if (serial_hds[i]) { 2121 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 2122 } 2123 } 2124 2125 /* We always have at least the nvram device on VIO */ 2126 spapr_create_nvram(spapr); 2127 2128 /* Set up PCI */ 2129 spapr_pci_rtas_init(); 2130 2131 phb = spapr_create_phb(spapr, 0); 2132 2133 for (i = 0; i < nb_nics; i++) { 2134 NICInfo *nd = &nd_table[i]; 2135 2136 if (!nd->model) { 2137 nd->model = g_strdup("ibmveth"); 2138 } 2139 2140 if (strcmp(nd->model, "ibmveth") == 0) { 2141 spapr_vlan_create(spapr->vio_bus, nd); 2142 } else { 2143 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2144 } 2145 } 2146 2147 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2148 spapr_vscsi_create(spapr->vio_bus); 2149 } 2150 2151 /* Graphics */ 2152 if (spapr_vga_init(phb->bus, &error_fatal)) { 2153 spapr->has_graphics = true; 2154 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2155 } 2156 2157 if (machine->usb) { 2158 if (smc->use_ohci_by_default) { 2159 pci_create_simple(phb->bus, -1, "pci-ohci"); 2160 } else { 2161 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2162 } 2163 2164 if (spapr->has_graphics) { 2165 USBBus *usb_bus = usb_bus_find(-1); 2166 2167 usb_create_simple(usb_bus, "usb-kbd"); 2168 usb_create_simple(usb_bus, "usb-mouse"); 2169 } 2170 } 2171 2172 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2173 error_report( 2174 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2175 MIN_RMA_SLOF); 2176 exit(1); 2177 } 2178 2179 if (kernel_filename) { 2180 uint64_t lowaddr = 0; 2181 2182 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2183 NULL, NULL, &lowaddr, NULL, 1, 2184 PPC_ELF_MACHINE, 0, 0); 2185 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2186 spapr->kernel_size = load_elf(kernel_filename, 2187 translate_kernel_address, NULL, NULL, 2188 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2189 0, 0); 2190 spapr->kernel_le = spapr->kernel_size > 0; 2191 } 2192 if (spapr->kernel_size < 0) { 2193 error_report("error loading %s: %s", kernel_filename, 2194 load_elf_strerror(spapr->kernel_size)); 2195 exit(1); 2196 } 2197 2198 /* load initrd */ 2199 if (initrd_filename) { 2200 /* Try to locate the initrd in the gap between the kernel 2201 * and the firmware. Add a bit of space just in case 2202 */ 2203 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2204 + 0x1ffff) & ~0xffff; 2205 spapr->initrd_size = load_image_targphys(initrd_filename, 2206 spapr->initrd_base, 2207 load_limit 2208 - spapr->initrd_base); 2209 if (spapr->initrd_size < 0) { 2210 error_report("could not load initial ram disk '%s'", 2211 initrd_filename); 2212 exit(1); 2213 } 2214 } 2215 } 2216 2217 if (bios_name == NULL) { 2218 bios_name = FW_FILE_NAME; 2219 } 2220 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2221 if (!filename) { 2222 error_report("Could not find LPAR firmware '%s'", bios_name); 2223 exit(1); 2224 } 2225 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2226 if (fw_size <= 0) { 2227 error_report("Could not load LPAR firmware '%s'", filename); 2228 exit(1); 2229 } 2230 g_free(filename); 2231 2232 /* FIXME: Should register things through the MachineState's qdev 2233 * interface, this is a legacy from the sPAPREnvironment structure 2234 * which predated MachineState but had a similar function */ 2235 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2236 register_savevm_live(NULL, "spapr/htab", -1, 1, 2237 &savevm_htab_handlers, spapr); 2238 2239 /* used by RTAS */ 2240 QTAILQ_INIT(&spapr->ccs_list); 2241 qemu_register_reset(spapr_ccs_reset_hook, spapr); 2242 2243 qemu_register_boot_set(spapr_boot_set, spapr); 2244 2245 /* to stop and start vmclock */ 2246 if (kvm_enabled()) { 2247 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2248 &spapr->tb); 2249 } 2250 } 2251 2252 static int spapr_kvm_type(const char *vm_type) 2253 { 2254 if (!vm_type) { 2255 return 0; 2256 } 2257 2258 if (!strcmp(vm_type, "HV")) { 2259 return 1; 2260 } 2261 2262 if (!strcmp(vm_type, "PR")) { 2263 return 2; 2264 } 2265 2266 error_report("Unknown kvm-type specified '%s'", vm_type); 2267 exit(1); 2268 } 2269 2270 /* 2271 * Implementation of an interface to adjust firmware path 2272 * for the bootindex property handling. 2273 */ 2274 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2275 DeviceState *dev) 2276 { 2277 #define CAST(type, obj, name) \ 2278 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2279 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2280 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2281 2282 if (d) { 2283 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2284 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2285 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2286 2287 if (spapr) { 2288 /* 2289 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2290 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2291 * in the top 16 bits of the 64-bit LUN 2292 */ 2293 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2294 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2295 (uint64_t)id << 48); 2296 } else if (virtio) { 2297 /* 2298 * We use SRP luns of the form 01000000 | (target << 8) | lun 2299 * in the top 32 bits of the 64-bit LUN 2300 * Note: the quote above is from SLOF and it is wrong, 2301 * the actual binding is: 2302 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2303 */ 2304 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2305 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2306 (uint64_t)id << 32); 2307 } else if (usb) { 2308 /* 2309 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2310 * in the top 32 bits of the 64-bit LUN 2311 */ 2312 unsigned usb_port = atoi(usb->port->path); 2313 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2314 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2315 (uint64_t)id << 32); 2316 } 2317 } 2318 2319 /* 2320 * SLOF probes the USB devices, and if it recognizes that the device is a 2321 * storage device, it changes its name to "storage" instead of "usb-host", 2322 * and additionally adds a child node for the SCSI LUN, so the correct 2323 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2324 */ 2325 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2326 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2327 if (usb_host_dev_is_scsi_storage(usbdev)) { 2328 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2329 } 2330 } 2331 2332 if (phb) { 2333 /* Replace "pci" with "pci@800000020000000" */ 2334 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2335 } 2336 2337 return NULL; 2338 } 2339 2340 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2341 { 2342 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2343 2344 return g_strdup(spapr->kvm_type); 2345 } 2346 2347 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2348 { 2349 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2350 2351 g_free(spapr->kvm_type); 2352 spapr->kvm_type = g_strdup(value); 2353 } 2354 2355 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2356 { 2357 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2358 2359 return spapr->use_hotplug_event_source; 2360 } 2361 2362 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2363 Error **errp) 2364 { 2365 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2366 2367 spapr->use_hotplug_event_source = value; 2368 } 2369 2370 static void spapr_machine_initfn(Object *obj) 2371 { 2372 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2373 2374 spapr->htab_fd = -1; 2375 spapr->use_hotplug_event_source = true; 2376 object_property_add_str(obj, "kvm-type", 2377 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2378 object_property_set_description(obj, "kvm-type", 2379 "Specifies the KVM virtualization mode (HV, PR)", 2380 NULL); 2381 object_property_add_bool(obj, "modern-hotplug-events", 2382 spapr_get_modern_hotplug_events, 2383 spapr_set_modern_hotplug_events, 2384 NULL); 2385 object_property_set_description(obj, "modern-hotplug-events", 2386 "Use dedicated hotplug event mechanism in" 2387 " place of standard EPOW events when possible" 2388 " (required for memory hot-unplug support)", 2389 NULL); 2390 } 2391 2392 static void spapr_machine_finalizefn(Object *obj) 2393 { 2394 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2395 2396 g_free(spapr->kvm_type); 2397 } 2398 2399 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 2400 { 2401 cpu_synchronize_state(cs); 2402 ppc_cpu_do_system_reset(cs); 2403 } 2404 2405 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2406 { 2407 CPUState *cs; 2408 2409 CPU_FOREACH(cs) { 2410 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 2411 } 2412 } 2413 2414 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2415 uint32_t node, bool dedicated_hp_event_source, 2416 Error **errp) 2417 { 2418 sPAPRDRConnector *drc; 2419 sPAPRDRConnectorClass *drck; 2420 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2421 int i, fdt_offset, fdt_size; 2422 void *fdt; 2423 uint64_t addr = addr_start; 2424 2425 for (i = 0; i < nr_lmbs; i++) { 2426 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2427 addr/SPAPR_MEMORY_BLOCK_SIZE); 2428 g_assert(drc); 2429 2430 fdt = create_device_tree(&fdt_size); 2431 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2432 SPAPR_MEMORY_BLOCK_SIZE); 2433 2434 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2435 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2436 addr += SPAPR_MEMORY_BLOCK_SIZE; 2437 if (!dev->hotplugged) { 2438 /* guests expect coldplugged LMBs to be pre-allocated */ 2439 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2440 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2441 } 2442 } 2443 /* send hotplug notification to the 2444 * guest only in case of hotplugged memory 2445 */ 2446 if (dev->hotplugged) { 2447 if (dedicated_hp_event_source) { 2448 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2449 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2450 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2451 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2452 nr_lmbs, 2453 drck->get_index(drc)); 2454 } else { 2455 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 2456 nr_lmbs); 2457 } 2458 } 2459 } 2460 2461 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2462 uint32_t node, Error **errp) 2463 { 2464 Error *local_err = NULL; 2465 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2466 PCDIMMDevice *dimm = PC_DIMM(dev); 2467 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2468 MemoryRegion *mr = ddc->get_memory_region(dimm); 2469 uint64_t align = memory_region_get_alignment(mr); 2470 uint64_t size = memory_region_size(mr); 2471 uint64_t addr; 2472 char *mem_dev; 2473 2474 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2475 error_setg(&local_err, "Hotplugged memory size must be a multiple of " 2476 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 2477 goto out; 2478 } 2479 2480 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 2481 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 2482 error_setg(&local_err, "Memory backend has bad page size. " 2483 "Use 'memory-backend-file' with correct mem-path."); 2484 goto out; 2485 } 2486 2487 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2488 if (local_err) { 2489 goto out; 2490 } 2491 2492 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2493 if (local_err) { 2494 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2495 goto out; 2496 } 2497 2498 spapr_add_lmbs(dev, addr, size, node, 2499 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 2500 &error_abort); 2501 2502 out: 2503 error_propagate(errp, local_err); 2504 } 2505 2506 typedef struct sPAPRDIMMState { 2507 uint32_t nr_lmbs; 2508 } sPAPRDIMMState; 2509 2510 static void spapr_lmb_release(DeviceState *dev, void *opaque) 2511 { 2512 sPAPRDIMMState *ds = (sPAPRDIMMState *)opaque; 2513 HotplugHandler *hotplug_ctrl; 2514 2515 if (--ds->nr_lmbs) { 2516 return; 2517 } 2518 2519 g_free(ds); 2520 2521 /* 2522 * Now that all the LMBs have been removed by the guest, call the 2523 * pc-dimm unplug handler to cleanup up the pc-dimm device. 2524 */ 2525 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2526 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2527 } 2528 2529 static void spapr_del_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2530 Error **errp) 2531 { 2532 sPAPRDRConnector *drc; 2533 sPAPRDRConnectorClass *drck; 2534 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2535 int i; 2536 sPAPRDIMMState *ds = g_malloc0(sizeof(sPAPRDIMMState)); 2537 uint64_t addr = addr_start; 2538 2539 ds->nr_lmbs = nr_lmbs; 2540 for (i = 0; i < nr_lmbs; i++) { 2541 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2542 addr / SPAPR_MEMORY_BLOCK_SIZE); 2543 g_assert(drc); 2544 2545 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2546 drck->detach(drc, dev, spapr_lmb_release, ds, errp); 2547 addr += SPAPR_MEMORY_BLOCK_SIZE; 2548 } 2549 2550 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2551 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2552 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2553 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2554 nr_lmbs, 2555 drck->get_index(drc)); 2556 } 2557 2558 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2559 Error **errp) 2560 { 2561 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2562 PCDIMMDevice *dimm = PC_DIMM(dev); 2563 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2564 MemoryRegion *mr = ddc->get_memory_region(dimm); 2565 2566 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2567 object_unparent(OBJECT(dev)); 2568 } 2569 2570 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 2571 DeviceState *dev, Error **errp) 2572 { 2573 Error *local_err = NULL; 2574 PCDIMMDevice *dimm = PC_DIMM(dev); 2575 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2576 MemoryRegion *mr = ddc->get_memory_region(dimm); 2577 uint64_t size = memory_region_size(mr); 2578 uint64_t addr; 2579 2580 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2581 if (local_err) { 2582 goto out; 2583 } 2584 2585 spapr_del_lmbs(dev, addr, size, &error_abort); 2586 out: 2587 error_propagate(errp, local_err); 2588 } 2589 2590 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 2591 sPAPRMachineState *spapr) 2592 { 2593 PowerPCCPU *cpu = POWERPC_CPU(cs); 2594 DeviceClass *dc = DEVICE_GET_CLASS(cs); 2595 int id = ppc_get_vcpu_dt_id(cpu); 2596 void *fdt; 2597 int offset, fdt_size; 2598 char *nodename; 2599 2600 fdt = create_device_tree(&fdt_size); 2601 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 2602 offset = fdt_add_subnode(fdt, 0, nodename); 2603 2604 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 2605 g_free(nodename); 2606 2607 *fdt_offset = offset; 2608 return fdt; 2609 } 2610 2611 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2612 Error **errp) 2613 { 2614 MachineState *ms = MACHINE(qdev_get_machine()); 2615 CPUCore *cc = CPU_CORE(dev); 2616 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 2617 2618 core_slot->cpu = NULL; 2619 object_unparent(OBJECT(dev)); 2620 } 2621 2622 static void spapr_core_release(DeviceState *dev, void *opaque) 2623 { 2624 HotplugHandler *hotplug_ctrl; 2625 2626 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2627 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2628 } 2629 2630 static 2631 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 2632 Error **errp) 2633 { 2634 int index; 2635 sPAPRDRConnector *drc; 2636 sPAPRDRConnectorClass *drck; 2637 Error *local_err = NULL; 2638 CPUCore *cc = CPU_CORE(dev); 2639 int smt = kvmppc_smt_threads(); 2640 2641 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 2642 error_setg(errp, "Unable to find CPU core with core-id: %d", 2643 cc->core_id); 2644 return; 2645 } 2646 if (index == 0) { 2647 error_setg(errp, "Boot CPU core may not be unplugged"); 2648 return; 2649 } 2650 2651 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2652 g_assert(drc); 2653 2654 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2655 drck->detach(drc, dev, spapr_core_release, NULL, &local_err); 2656 if (local_err) { 2657 error_propagate(errp, local_err); 2658 return; 2659 } 2660 2661 spapr_hotplug_req_remove_by_index(drc); 2662 } 2663 2664 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2665 Error **errp) 2666 { 2667 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 2668 MachineClass *mc = MACHINE_GET_CLASS(spapr); 2669 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 2670 CPUCore *cc = CPU_CORE(dev); 2671 CPUState *cs = CPU(core->threads); 2672 sPAPRDRConnector *drc; 2673 Error *local_err = NULL; 2674 void *fdt = NULL; 2675 int fdt_offset = 0; 2676 int smt = kvmppc_smt_threads(); 2677 CPUArchId *core_slot; 2678 int index; 2679 2680 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2681 if (!core_slot) { 2682 error_setg(errp, "Unable to find CPU core with core-id: %d", 2683 cc->core_id); 2684 return; 2685 } 2686 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2687 2688 g_assert(drc || !mc->has_hotpluggable_cpus); 2689 2690 /* 2691 * Setup CPU DT entries only for hotplugged CPUs. For boot time or 2692 * coldplugged CPUs DT entries are setup in spapr_build_fdt(). 2693 */ 2694 if (dev->hotplugged) { 2695 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 2696 } 2697 2698 if (drc) { 2699 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2700 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err); 2701 if (local_err) { 2702 g_free(fdt); 2703 error_propagate(errp, local_err); 2704 return; 2705 } 2706 } 2707 2708 if (dev->hotplugged) { 2709 /* 2710 * Send hotplug notification interrupt to the guest only in case 2711 * of hotplugged CPUs. 2712 */ 2713 spapr_hotplug_req_add_by_index(drc); 2714 } else { 2715 /* 2716 * Set the right DRC states for cold plugged CPU. 2717 */ 2718 if (drc) { 2719 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2720 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2721 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2722 } 2723 } 2724 core_slot->cpu = OBJECT(dev); 2725 } 2726 2727 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2728 Error **errp) 2729 { 2730 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 2731 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 2732 Error *local_err = NULL; 2733 CPUCore *cc = CPU_CORE(dev); 2734 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model); 2735 const char *type = object_get_typename(OBJECT(dev)); 2736 CPUArchId *core_slot; 2737 int index; 2738 2739 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 2740 error_setg(&local_err, "CPU hotplug not supported for this machine"); 2741 goto out; 2742 } 2743 2744 if (strcmp(base_core_type, type)) { 2745 error_setg(&local_err, "CPU core type should be %s", base_core_type); 2746 goto out; 2747 } 2748 2749 if (cc->core_id % smp_threads) { 2750 error_setg(&local_err, "invalid core id %d", cc->core_id); 2751 goto out; 2752 } 2753 2754 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2755 if (!core_slot) { 2756 error_setg(&local_err, "core id %d out of range", cc->core_id); 2757 goto out; 2758 } 2759 2760 if (core_slot->cpu) { 2761 error_setg(&local_err, "core %d already populated", cc->core_id); 2762 goto out; 2763 } 2764 2765 out: 2766 g_free(base_core_type); 2767 error_propagate(errp, local_err); 2768 } 2769 2770 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 2771 DeviceState *dev, Error **errp) 2772 { 2773 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2774 2775 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2776 int node; 2777 2778 if (!smc->dr_lmb_enabled) { 2779 error_setg(errp, "Memory hotplug not supported for this machine"); 2780 return; 2781 } 2782 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 2783 if (*errp) { 2784 return; 2785 } 2786 if (node < 0 || node >= MAX_NODES) { 2787 error_setg(errp, "Invaild node %d", node); 2788 return; 2789 } 2790 2791 /* 2792 * Currently PowerPC kernel doesn't allow hot-adding memory to 2793 * memory-less node, but instead will silently add the memory 2794 * to the first node that has some memory. This causes two 2795 * unexpected behaviours for the user. 2796 * 2797 * - Memory gets hotplugged to a different node than what the user 2798 * specified. 2799 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 2800 * to memory-less node, a reboot will set things accordingly 2801 * and the previously hotplugged memory now ends in the right node. 2802 * This appears as if some memory moved from one node to another. 2803 * 2804 * So until kernel starts supporting memory hotplug to memory-less 2805 * nodes, just prevent such attempts upfront in QEMU. 2806 */ 2807 if (nb_numa_nodes && !numa_info[node].node_mem) { 2808 error_setg(errp, "Can't hotplug memory to memory-less node %d", 2809 node); 2810 return; 2811 } 2812 2813 spapr_memory_plug(hotplug_dev, dev, node, errp); 2814 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2815 spapr_core_plug(hotplug_dev, dev, errp); 2816 } 2817 } 2818 2819 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 2820 DeviceState *dev, Error **errp) 2821 { 2822 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2823 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2824 2825 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2826 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2827 spapr_memory_unplug(hotplug_dev, dev, errp); 2828 } else { 2829 error_setg(errp, "Memory hot unplug not supported for this guest"); 2830 } 2831 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2832 if (!mc->has_hotpluggable_cpus) { 2833 error_setg(errp, "CPU hot unplug not supported on this machine"); 2834 return; 2835 } 2836 spapr_core_unplug(hotplug_dev, dev, errp); 2837 } 2838 } 2839 2840 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 2841 DeviceState *dev, Error **errp) 2842 { 2843 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2844 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2845 2846 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2847 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2848 spapr_memory_unplug_request(hotplug_dev, dev, errp); 2849 } else { 2850 /* NOTE: this means there is a window after guest reset, prior to 2851 * CAS negotiation, where unplug requests will fail due to the 2852 * capability not being detected yet. This is a bit different than 2853 * the case with PCI unplug, where the events will be queued and 2854 * eventually handled by the guest after boot 2855 */ 2856 error_setg(errp, "Memory hot unplug not supported for this guest"); 2857 } 2858 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2859 if (!mc->has_hotpluggable_cpus) { 2860 error_setg(errp, "CPU hot unplug not supported on this machine"); 2861 return; 2862 } 2863 spapr_core_unplug_request(hotplug_dev, dev, errp); 2864 } 2865 } 2866 2867 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 2868 DeviceState *dev, Error **errp) 2869 { 2870 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2871 spapr_core_pre_plug(hotplug_dev, dev, errp); 2872 } 2873 } 2874 2875 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 2876 DeviceState *dev) 2877 { 2878 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2879 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2880 return HOTPLUG_HANDLER(machine); 2881 } 2882 return NULL; 2883 } 2884 2885 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index) 2886 { 2887 /* Allocate to NUMA nodes on a "socket" basis (not that concept of 2888 * socket means much for the paravirtualized PAPR platform) */ 2889 return cpu_index / smp_threads / smp_cores; 2890 } 2891 2892 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 2893 { 2894 int i; 2895 int spapr_max_cores = max_cpus / smp_threads; 2896 MachineClass *mc = MACHINE_GET_CLASS(machine); 2897 2898 if (!mc->has_hotpluggable_cpus) { 2899 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 2900 } 2901 if (machine->possible_cpus) { 2902 assert(machine->possible_cpus->len == spapr_max_cores); 2903 return machine->possible_cpus; 2904 } 2905 2906 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2907 sizeof(CPUArchId) * spapr_max_cores); 2908 machine->possible_cpus->len = spapr_max_cores; 2909 for (i = 0; i < machine->possible_cpus->len; i++) { 2910 int core_id = i * smp_threads; 2911 2912 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 2913 machine->possible_cpus->cpus[i].arch_id = core_id; 2914 machine->possible_cpus->cpus[i].props.has_core_id = true; 2915 machine->possible_cpus->cpus[i].props.core_id = core_id; 2916 /* TODO: add 'has_node/node' here to describe 2917 to which node core belongs */ 2918 } 2919 return machine->possible_cpus; 2920 } 2921 2922 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 2923 uint64_t *buid, hwaddr *pio, 2924 hwaddr *mmio32, hwaddr *mmio64, 2925 unsigned n_dma, uint32_t *liobns, Error **errp) 2926 { 2927 /* 2928 * New-style PHB window placement. 2929 * 2930 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 2931 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 2932 * windows. 2933 * 2934 * Some guest kernels can't work with MMIO windows above 1<<46 2935 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 2936 * 2937 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 2938 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 2939 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 2940 * 1TiB 64-bit MMIO windows for each PHB. 2941 */ 2942 const uint64_t base_buid = 0x800000020000000ULL; 2943 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 2944 SPAPR_PCI_MEM64_WIN_SIZE - 1) 2945 int i; 2946 2947 /* Sanity check natural alignments */ 2948 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 2949 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 2950 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 2951 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 2952 /* Sanity check bounds */ 2953 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 2954 SPAPR_PCI_MEM32_WIN_SIZE); 2955 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 2956 SPAPR_PCI_MEM64_WIN_SIZE); 2957 2958 if (index >= SPAPR_MAX_PHBS) { 2959 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 2960 SPAPR_MAX_PHBS - 1); 2961 return; 2962 } 2963 2964 *buid = base_buid + index; 2965 for (i = 0; i < n_dma; ++i) { 2966 liobns[i] = SPAPR_PCI_LIOBN(index, i); 2967 } 2968 2969 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 2970 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 2971 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 2972 } 2973 2974 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 2975 { 2976 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 2977 2978 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 2979 } 2980 2981 static void spapr_ics_resend(XICSFabric *dev) 2982 { 2983 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 2984 2985 ics_resend(spapr->ics); 2986 } 2987 2988 static ICPState *spapr_icp_get(XICSFabric *xi, int server) 2989 { 2990 sPAPRMachineState *spapr = SPAPR_MACHINE(xi); 2991 2992 return (server < spapr->xics->nr_servers) ? &spapr->xics->ss[server] : 2993 NULL; 2994 } 2995 2996 static void spapr_icp_resend(XICSFabric *xi) 2997 { 2998 sPAPRMachineState *spapr = SPAPR_MACHINE(xi); 2999 int i; 3000 3001 for (i = 0; i < spapr->xics->nr_servers; i++) { 3002 icp_resend(&spapr->xics->ss[i]); 3003 } 3004 } 3005 3006 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3007 { 3008 MachineClass *mc = MACHINE_CLASS(oc); 3009 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3010 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3011 NMIClass *nc = NMI_CLASS(oc); 3012 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3013 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3014 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3015 3016 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3017 3018 /* 3019 * We set up the default / latest behaviour here. The class_init 3020 * functions for the specific versioned machine types can override 3021 * these details for backwards compatibility 3022 */ 3023 mc->init = ppc_spapr_init; 3024 mc->reset = ppc_spapr_reset; 3025 mc->block_default_type = IF_SCSI; 3026 mc->max_cpus = 1024; 3027 mc->no_parallel = 1; 3028 mc->default_boot_order = ""; 3029 mc->default_ram_size = 512 * M_BYTE; 3030 mc->kvm_type = spapr_kvm_type; 3031 mc->has_dynamic_sysbus = true; 3032 mc->pci_allow_0_address = true; 3033 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3034 hc->pre_plug = spapr_machine_device_pre_plug; 3035 hc->plug = spapr_machine_device_plug; 3036 hc->unplug = spapr_machine_device_unplug; 3037 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; 3038 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3039 hc->unplug_request = spapr_machine_device_unplug_request; 3040 3041 smc->dr_lmb_enabled = true; 3042 smc->tcg_default_cpu = "POWER8"; 3043 mc->has_hotpluggable_cpus = true; 3044 fwc->get_dev_path = spapr_get_fw_dev_path; 3045 nc->nmi_monitor_handler = spapr_nmi; 3046 smc->phb_placement = spapr_phb_placement; 3047 vhc->hypercall = emulate_spapr_hypercall; 3048 vhc->hpt_mask = spapr_hpt_mask; 3049 vhc->map_hptes = spapr_map_hptes; 3050 vhc->unmap_hptes = spapr_unmap_hptes; 3051 vhc->store_hpte = spapr_store_hpte; 3052 xic->ics_get = spapr_ics_get; 3053 xic->ics_resend = spapr_ics_resend; 3054 xic->icp_get = spapr_icp_get; 3055 xic->icp_resend = spapr_icp_resend; 3056 } 3057 3058 static const TypeInfo spapr_machine_info = { 3059 .name = TYPE_SPAPR_MACHINE, 3060 .parent = TYPE_MACHINE, 3061 .abstract = true, 3062 .instance_size = sizeof(sPAPRMachineState), 3063 .instance_init = spapr_machine_initfn, 3064 .instance_finalize = spapr_machine_finalizefn, 3065 .class_size = sizeof(sPAPRMachineClass), 3066 .class_init = spapr_machine_class_init, 3067 .interfaces = (InterfaceInfo[]) { 3068 { TYPE_FW_PATH_PROVIDER }, 3069 { TYPE_NMI }, 3070 { TYPE_HOTPLUG_HANDLER }, 3071 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3072 { TYPE_XICS_FABRIC }, 3073 { } 3074 }, 3075 }; 3076 3077 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3078 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3079 void *data) \ 3080 { \ 3081 MachineClass *mc = MACHINE_CLASS(oc); \ 3082 spapr_machine_##suffix##_class_options(mc); \ 3083 if (latest) { \ 3084 mc->alias = "pseries"; \ 3085 mc->is_default = 1; \ 3086 } \ 3087 } \ 3088 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3089 { \ 3090 MachineState *machine = MACHINE(obj); \ 3091 spapr_machine_##suffix##_instance_options(machine); \ 3092 } \ 3093 static const TypeInfo spapr_machine_##suffix##_info = { \ 3094 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3095 .parent = TYPE_SPAPR_MACHINE, \ 3096 .class_init = spapr_machine_##suffix##_class_init, \ 3097 .instance_init = spapr_machine_##suffix##_instance_init, \ 3098 }; \ 3099 static void spapr_machine_register_##suffix(void) \ 3100 { \ 3101 type_register(&spapr_machine_##suffix##_info); \ 3102 } \ 3103 type_init(spapr_machine_register_##suffix) 3104 3105 /* 3106 * pseries-2.9 3107 */ 3108 static void spapr_machine_2_9_instance_options(MachineState *machine) 3109 { 3110 } 3111 3112 static void spapr_machine_2_9_class_options(MachineClass *mc) 3113 { 3114 /* Defaults for the latest behaviour inherited from the base class */ 3115 } 3116 3117 DEFINE_SPAPR_MACHINE(2_9, "2.9", true); 3118 3119 /* 3120 * pseries-2.8 3121 */ 3122 #define SPAPR_COMPAT_2_8 \ 3123 HW_COMPAT_2_8 3124 3125 static void spapr_machine_2_8_instance_options(MachineState *machine) 3126 { 3127 spapr_machine_2_9_instance_options(machine); 3128 } 3129 3130 static void spapr_machine_2_8_class_options(MachineClass *mc) 3131 { 3132 spapr_machine_2_9_class_options(mc); 3133 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 3134 } 3135 3136 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 3137 3138 /* 3139 * pseries-2.7 3140 */ 3141 #define SPAPR_COMPAT_2_7 \ 3142 HW_COMPAT_2_7 \ 3143 { \ 3144 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3145 .property = "mem_win_size", \ 3146 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 3147 }, \ 3148 { \ 3149 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3150 .property = "mem64_win_size", \ 3151 .value = "0", \ 3152 }, \ 3153 { \ 3154 .driver = TYPE_POWERPC_CPU, \ 3155 .property = "pre-2.8-migration", \ 3156 .value = "on", \ 3157 }, \ 3158 { \ 3159 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3160 .property = "pre-2.8-migration", \ 3161 .value = "on", \ 3162 }, 3163 3164 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 3165 uint64_t *buid, hwaddr *pio, 3166 hwaddr *mmio32, hwaddr *mmio64, 3167 unsigned n_dma, uint32_t *liobns, Error **errp) 3168 { 3169 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 3170 const uint64_t base_buid = 0x800000020000000ULL; 3171 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 3172 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 3173 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 3174 const uint32_t max_index = 255; 3175 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 3176 3177 uint64_t ram_top = MACHINE(spapr)->ram_size; 3178 hwaddr phb0_base, phb_base; 3179 int i; 3180 3181 /* Do we have hotpluggable memory? */ 3182 if (MACHINE(spapr)->maxram_size > ram_top) { 3183 /* Can't just use maxram_size, because there may be an 3184 * alignment gap between normal and hotpluggable memory 3185 * regions */ 3186 ram_top = spapr->hotplug_memory.base + 3187 memory_region_size(&spapr->hotplug_memory.mr); 3188 } 3189 3190 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 3191 3192 if (index > max_index) { 3193 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 3194 max_index); 3195 return; 3196 } 3197 3198 *buid = base_buid + index; 3199 for (i = 0; i < n_dma; ++i) { 3200 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3201 } 3202 3203 phb_base = phb0_base + index * phb_spacing; 3204 *pio = phb_base + pio_offset; 3205 *mmio32 = phb_base + mmio_offset; 3206 /* 3207 * We don't set the 64-bit MMIO window, relying on the PHB's 3208 * fallback behaviour of automatically splitting a large "32-bit" 3209 * window into contiguous 32-bit and 64-bit windows 3210 */ 3211 } 3212 3213 static void spapr_machine_2_7_instance_options(MachineState *machine) 3214 { 3215 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 3216 3217 spapr_machine_2_8_instance_options(machine); 3218 spapr->use_hotplug_event_source = false; 3219 } 3220 3221 static void spapr_machine_2_7_class_options(MachineClass *mc) 3222 { 3223 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3224 3225 spapr_machine_2_8_class_options(mc); 3226 smc->tcg_default_cpu = "POWER7"; 3227 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 3228 smc->phb_placement = phb_placement_2_7; 3229 } 3230 3231 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 3232 3233 /* 3234 * pseries-2.6 3235 */ 3236 #define SPAPR_COMPAT_2_6 \ 3237 HW_COMPAT_2_6 \ 3238 { \ 3239 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3240 .property = "ddw",\ 3241 .value = stringify(off),\ 3242 }, 3243 3244 static void spapr_machine_2_6_instance_options(MachineState *machine) 3245 { 3246 spapr_machine_2_7_instance_options(machine); 3247 } 3248 3249 static void spapr_machine_2_6_class_options(MachineClass *mc) 3250 { 3251 spapr_machine_2_7_class_options(mc); 3252 mc->has_hotpluggable_cpus = false; 3253 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 3254 } 3255 3256 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 3257 3258 /* 3259 * pseries-2.5 3260 */ 3261 #define SPAPR_COMPAT_2_5 \ 3262 HW_COMPAT_2_5 \ 3263 { \ 3264 .driver = "spapr-vlan", \ 3265 .property = "use-rx-buffer-pools", \ 3266 .value = "off", \ 3267 }, 3268 3269 static void spapr_machine_2_5_instance_options(MachineState *machine) 3270 { 3271 spapr_machine_2_6_instance_options(machine); 3272 } 3273 3274 static void spapr_machine_2_5_class_options(MachineClass *mc) 3275 { 3276 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3277 3278 spapr_machine_2_6_class_options(mc); 3279 smc->use_ohci_by_default = true; 3280 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 3281 } 3282 3283 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 3284 3285 /* 3286 * pseries-2.4 3287 */ 3288 #define SPAPR_COMPAT_2_4 \ 3289 HW_COMPAT_2_4 3290 3291 static void spapr_machine_2_4_instance_options(MachineState *machine) 3292 { 3293 spapr_machine_2_5_instance_options(machine); 3294 } 3295 3296 static void spapr_machine_2_4_class_options(MachineClass *mc) 3297 { 3298 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3299 3300 spapr_machine_2_5_class_options(mc); 3301 smc->dr_lmb_enabled = false; 3302 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 3303 } 3304 3305 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 3306 3307 /* 3308 * pseries-2.3 3309 */ 3310 #define SPAPR_COMPAT_2_3 \ 3311 HW_COMPAT_2_3 \ 3312 {\ 3313 .driver = "spapr-pci-host-bridge",\ 3314 .property = "dynamic-reconfiguration",\ 3315 .value = "off",\ 3316 }, 3317 3318 static void spapr_machine_2_3_instance_options(MachineState *machine) 3319 { 3320 spapr_machine_2_4_instance_options(machine); 3321 savevm_skip_section_footers(); 3322 global_state_set_optional(); 3323 savevm_skip_configuration(); 3324 } 3325 3326 static void spapr_machine_2_3_class_options(MachineClass *mc) 3327 { 3328 spapr_machine_2_4_class_options(mc); 3329 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 3330 } 3331 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 3332 3333 /* 3334 * pseries-2.2 3335 */ 3336 3337 #define SPAPR_COMPAT_2_2 \ 3338 HW_COMPAT_2_2 \ 3339 {\ 3340 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3341 .property = "mem_win_size",\ 3342 .value = "0x20000000",\ 3343 }, 3344 3345 static void spapr_machine_2_2_instance_options(MachineState *machine) 3346 { 3347 spapr_machine_2_3_instance_options(machine); 3348 machine->suppress_vmdesc = true; 3349 } 3350 3351 static void spapr_machine_2_2_class_options(MachineClass *mc) 3352 { 3353 spapr_machine_2_3_class_options(mc); 3354 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 3355 } 3356 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 3357 3358 /* 3359 * pseries-2.1 3360 */ 3361 #define SPAPR_COMPAT_2_1 \ 3362 HW_COMPAT_2_1 3363 3364 static void spapr_machine_2_1_instance_options(MachineState *machine) 3365 { 3366 spapr_machine_2_2_instance_options(machine); 3367 } 3368 3369 static void spapr_machine_2_1_class_options(MachineClass *mc) 3370 { 3371 spapr_machine_2_2_class_options(mc); 3372 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 3373 } 3374 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 3375 3376 static void spapr_machine_register_types(void) 3377 { 3378 type_register_static(&spapr_machine_info); 3379 } 3380 3381 type_init(spapr_machine_register_types) 3382