1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/numa.h" 31 #include "hw/hw.h" 32 #include "qemu/log.h" 33 #include "hw/fw-path-provider.h" 34 #include "elf.h" 35 #include "net/net.h" 36 #include "sysemu/device_tree.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/misc.h" 42 #include "migration/global_state.h" 43 #include "migration/register.h" 44 #include "mmu-hash64.h" 45 #include "mmu-book3s-v3.h" 46 #include "qom/cpu.h" 47 48 #include "hw/boards.h" 49 #include "hw/ppc/ppc.h" 50 #include "hw/loader.h" 51 52 #include "hw/ppc/fdt.h" 53 #include "hw/ppc/spapr.h" 54 #include "hw/ppc/spapr_vio.h" 55 #include "hw/pci-host/spapr.h" 56 #include "hw/ppc/xics.h" 57 #include "hw/pci/msi.h" 58 59 #include "hw/pci/pci.h" 60 #include "hw/scsi/scsi.h" 61 #include "hw/virtio/virtio-scsi.h" 62 #include "hw/virtio/vhost-scsi-common.h" 63 64 #include "exec/address-spaces.h" 65 #include "hw/usb.h" 66 #include "qemu/config-file.h" 67 #include "qemu/error-report.h" 68 #include "trace.h" 69 #include "hw/nmi.h" 70 #include "hw/intc/intc.h" 71 72 #include "hw/compat.h" 73 #include "qemu/cutils.h" 74 #include "hw/ppc/spapr_cpu_core.h" 75 #include "qmp-commands.h" 76 77 #include <libfdt.h> 78 79 /* SLOF memory layout: 80 * 81 * SLOF raw image loaded at 0, copies its romfs right below the flat 82 * device-tree, then position SLOF itself 31M below that 83 * 84 * So we set FW_OVERHEAD to 40MB which should account for all of that 85 * and more 86 * 87 * We load our kernel at 4M, leaving space for SLOF initial image 88 */ 89 #define FDT_MAX_SIZE 0x100000 90 #define RTAS_MAX_SIZE 0x10000 91 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 92 #define FW_MAX_SIZE 0x400000 93 #define FW_FILE_NAME "slof.bin" 94 #define FW_OVERHEAD 0x2800000 95 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 96 97 #define MIN_RMA_SLOF 128UL 98 99 #define PHANDLE_XICP 0x00001111 100 101 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 102 103 static ICSState *spapr_ics_create(sPAPRMachineState *spapr, 104 const char *type_ics, 105 int nr_irqs, Error **errp) 106 { 107 Error *local_err = NULL; 108 Object *obj; 109 110 obj = object_new(type_ics); 111 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); 112 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), 113 &error_abort); 114 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); 115 if (local_err) { 116 goto error; 117 } 118 object_property_set_bool(obj, true, "realized", &local_err); 119 if (local_err) { 120 goto error; 121 } 122 123 return ICS_SIMPLE(obj); 124 125 error: 126 error_propagate(errp, local_err); 127 return NULL; 128 } 129 130 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 131 { 132 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 133 * and newer QEMUs don't even have them. In both cases, we don't want 134 * to send anything on the wire. 135 */ 136 return false; 137 } 138 139 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 140 .name = "icp/server", 141 .version_id = 1, 142 .minimum_version_id = 1, 143 .needed = pre_2_10_vmstate_dummy_icp_needed, 144 .fields = (VMStateField[]) { 145 VMSTATE_UNUSED(4), /* uint32_t xirr */ 146 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 147 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 148 VMSTATE_END_OF_LIST() 149 }, 150 }; 151 152 static void pre_2_10_vmstate_register_dummy_icp(int i) 153 { 154 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 155 (void *)(uintptr_t) i); 156 } 157 158 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 159 { 160 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 161 (void *)(uintptr_t) i); 162 } 163 164 static inline int xics_max_server_number(void) 165 { 166 return DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), smp_threads); 167 } 168 169 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) 170 { 171 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 172 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 173 174 if (kvm_enabled()) { 175 if (machine_kernel_irqchip_allowed(machine) && 176 !xics_kvm_init(spapr, errp)) { 177 spapr->icp_type = TYPE_KVM_ICP; 178 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp); 179 } 180 if (machine_kernel_irqchip_required(machine) && !spapr->ics) { 181 error_prepend(errp, "kernel_irqchip requested but unavailable: "); 182 return; 183 } 184 } 185 186 if (!spapr->ics) { 187 xics_spapr_init(spapr); 188 spapr->icp_type = TYPE_ICP; 189 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp); 190 if (!spapr->ics) { 191 return; 192 } 193 } 194 195 if (smc->pre_2_10_has_unused_icps) { 196 int i; 197 198 for (i = 0; i < xics_max_server_number(); i++) { 199 /* Dummy entries get deregistered when real ICPState objects 200 * are registered during CPU core hotplug. 201 */ 202 pre_2_10_vmstate_register_dummy_icp(i); 203 } 204 } 205 } 206 207 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 208 int smt_threads) 209 { 210 int i, ret = 0; 211 uint32_t servers_prop[smt_threads]; 212 uint32_t gservers_prop[smt_threads * 2]; 213 int index = ppc_get_vcpu_dt_id(cpu); 214 215 if (cpu->compat_pvr) { 216 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 217 if (ret < 0) { 218 return ret; 219 } 220 } 221 222 /* Build interrupt servers and gservers properties */ 223 for (i = 0; i < smt_threads; i++) { 224 servers_prop[i] = cpu_to_be32(index + i); 225 /* Hack, direct the group queues back to cpu 0 */ 226 gservers_prop[i*2] = cpu_to_be32(index + i); 227 gservers_prop[i*2 + 1] = 0; 228 } 229 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 230 servers_prop, sizeof(servers_prop)); 231 if (ret < 0) { 232 return ret; 233 } 234 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 235 gservers_prop, sizeof(gservers_prop)); 236 237 return ret; 238 } 239 240 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 241 { 242 int index = ppc_get_vcpu_dt_id(cpu); 243 uint32_t associativity[] = {cpu_to_be32(0x5), 244 cpu_to_be32(0x0), 245 cpu_to_be32(0x0), 246 cpu_to_be32(0x0), 247 cpu_to_be32(cpu->node_id), 248 cpu_to_be32(index)}; 249 250 /* Advertise NUMA via ibm,associativity */ 251 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 252 sizeof(associativity)); 253 } 254 255 /* Populate the "ibm,pa-features" property */ 256 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset, 257 bool legacy_guest) 258 { 259 uint8_t pa_features_206[] = { 6, 0, 260 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 261 uint8_t pa_features_207[] = { 24, 0, 262 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 263 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 264 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 265 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 266 uint8_t pa_features_300[] = { 66, 0, 267 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 268 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 269 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 270 /* 6: DS207 */ 271 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 272 /* 16: Vector */ 273 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 274 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 275 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 276 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 277 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 278 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 279 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 280 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 281 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 282 /* 42: PM, 44: PC RA, 46: SC vec'd */ 283 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 284 /* 48: SIMD, 50: QP BFP, 52: String */ 285 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 286 /* 54: DecFP, 56: DecI, 58: SHA */ 287 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 288 /* 60: NM atomic, 62: RNG */ 289 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 290 }; 291 uint8_t *pa_features; 292 size_t pa_size; 293 294 switch (POWERPC_MMU_VER(env->mmu_model)) { 295 case POWERPC_MMU_VER_2_06: 296 pa_features = pa_features_206; 297 pa_size = sizeof(pa_features_206); 298 break; 299 case POWERPC_MMU_VER_2_07: 300 pa_features = pa_features_207; 301 pa_size = sizeof(pa_features_207); 302 break; 303 case POWERPC_MMU_VER_3_00: 304 pa_features = pa_features_300; 305 pa_size = sizeof(pa_features_300); 306 break; 307 default: 308 return; 309 } 310 311 if (env->ci_large_pages) { 312 /* 313 * Note: we keep CI large pages off by default because a 64K capable 314 * guest provisioned with large pages might otherwise try to map a qemu 315 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 316 * even if that qemu runs on a 4k host. 317 * We dd this bit back here if we are confident this is not an issue 318 */ 319 pa_features[3] |= 0x20; 320 } 321 if (kvmppc_has_cap_htm() && pa_size > 24) { 322 pa_features[24] |= 0x80; /* Transactional memory support */ 323 } 324 if (legacy_guest && pa_size > 40) { 325 /* Workaround for broken kernels that attempt (guest) radix 326 * mode when they can't handle it, if they see the radix bit set 327 * in pa-features. So hide it from them. */ 328 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 329 } 330 331 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 332 } 333 334 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 335 { 336 int ret = 0, offset, cpus_offset; 337 CPUState *cs; 338 char cpu_model[32]; 339 int smt = kvmppc_smt_threads(); 340 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 341 342 CPU_FOREACH(cs) { 343 PowerPCCPU *cpu = POWERPC_CPU(cs); 344 CPUPPCState *env = &cpu->env; 345 DeviceClass *dc = DEVICE_GET_CLASS(cs); 346 int index = ppc_get_vcpu_dt_id(cpu); 347 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 348 349 if ((index % smt) != 0) { 350 continue; 351 } 352 353 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 354 355 cpus_offset = fdt_path_offset(fdt, "/cpus"); 356 if (cpus_offset < 0) { 357 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 358 "cpus"); 359 if (cpus_offset < 0) { 360 return cpus_offset; 361 } 362 } 363 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 364 if (offset < 0) { 365 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 366 if (offset < 0) { 367 return offset; 368 } 369 } 370 371 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 372 pft_size_prop, sizeof(pft_size_prop)); 373 if (ret < 0) { 374 return ret; 375 } 376 377 if (nb_numa_nodes > 1) { 378 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 379 if (ret < 0) { 380 return ret; 381 } 382 } 383 384 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 385 if (ret < 0) { 386 return ret; 387 } 388 389 spapr_populate_pa_features(env, fdt, offset, 390 spapr->cas_legacy_guest_workaround); 391 } 392 return ret; 393 } 394 395 static hwaddr spapr_node0_size(void) 396 { 397 MachineState *machine = MACHINE(qdev_get_machine()); 398 399 if (nb_numa_nodes) { 400 int i; 401 for (i = 0; i < nb_numa_nodes; ++i) { 402 if (numa_info[i].node_mem) { 403 return MIN(pow2floor(numa_info[i].node_mem), 404 machine->ram_size); 405 } 406 } 407 } 408 return machine->ram_size; 409 } 410 411 static void add_str(GString *s, const gchar *s1) 412 { 413 g_string_append_len(s, s1, strlen(s1) + 1); 414 } 415 416 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 417 hwaddr size) 418 { 419 uint32_t associativity[] = { 420 cpu_to_be32(0x4), /* length */ 421 cpu_to_be32(0x0), cpu_to_be32(0x0), 422 cpu_to_be32(0x0), cpu_to_be32(nodeid) 423 }; 424 char mem_name[32]; 425 uint64_t mem_reg_property[2]; 426 int off; 427 428 mem_reg_property[0] = cpu_to_be64(start); 429 mem_reg_property[1] = cpu_to_be64(size); 430 431 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 432 off = fdt_add_subnode(fdt, 0, mem_name); 433 _FDT(off); 434 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 435 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 436 sizeof(mem_reg_property)))); 437 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 438 sizeof(associativity)))); 439 return off; 440 } 441 442 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 443 { 444 MachineState *machine = MACHINE(spapr); 445 hwaddr mem_start, node_size; 446 int i, nb_nodes = nb_numa_nodes; 447 NodeInfo *nodes = numa_info; 448 NodeInfo ramnode; 449 450 /* No NUMA nodes, assume there is just one node with whole RAM */ 451 if (!nb_numa_nodes) { 452 nb_nodes = 1; 453 ramnode.node_mem = machine->ram_size; 454 nodes = &ramnode; 455 } 456 457 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 458 if (!nodes[i].node_mem) { 459 continue; 460 } 461 if (mem_start >= machine->ram_size) { 462 node_size = 0; 463 } else { 464 node_size = nodes[i].node_mem; 465 if (node_size > machine->ram_size - mem_start) { 466 node_size = machine->ram_size - mem_start; 467 } 468 } 469 if (!mem_start) { 470 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 471 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 472 mem_start += spapr->rma_size; 473 node_size -= spapr->rma_size; 474 } 475 for ( ; node_size; ) { 476 hwaddr sizetmp = pow2floor(node_size); 477 478 /* mem_start != 0 here */ 479 if (ctzl(mem_start) < ctzl(sizetmp)) { 480 sizetmp = 1ULL << ctzl(mem_start); 481 } 482 483 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 484 node_size -= sizetmp; 485 mem_start += sizetmp; 486 } 487 } 488 489 return 0; 490 } 491 492 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 493 sPAPRMachineState *spapr) 494 { 495 PowerPCCPU *cpu = POWERPC_CPU(cs); 496 CPUPPCState *env = &cpu->env; 497 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 498 int index = ppc_get_vcpu_dt_id(cpu); 499 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 500 0xffffffff, 0xffffffff}; 501 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 502 : SPAPR_TIMEBASE_FREQ; 503 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 504 uint32_t page_sizes_prop[64]; 505 size_t page_sizes_prop_size; 506 uint32_t vcpus_per_socket = smp_threads * smp_cores; 507 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 508 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 509 sPAPRDRConnector *drc; 510 int drc_index; 511 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 512 int i; 513 514 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 515 if (drc) { 516 drc_index = spapr_drc_index(drc); 517 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 518 } 519 520 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 521 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 522 523 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 524 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 525 env->dcache_line_size))); 526 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 527 env->dcache_line_size))); 528 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 529 env->icache_line_size))); 530 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 531 env->icache_line_size))); 532 533 if (pcc->l1_dcache_size) { 534 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 535 pcc->l1_dcache_size))); 536 } else { 537 warn_report("Unknown L1 dcache size for cpu"); 538 } 539 if (pcc->l1_icache_size) { 540 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 541 pcc->l1_icache_size))); 542 } else { 543 warn_report("Unknown L1 icache size for cpu"); 544 } 545 546 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 547 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 548 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 549 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 550 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 551 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 552 553 if (env->spr_cb[SPR_PURR].oea_read) { 554 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 555 } 556 557 if (env->mmu_model & POWERPC_MMU_1TSEG) { 558 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 559 segs, sizeof(segs)))); 560 } 561 562 /* Advertise VMX/VSX (vector extensions) if available 563 * 0 / no property == no vector extensions 564 * 1 == VMX / Altivec available 565 * 2 == VSX available */ 566 if (env->insns_flags & PPC_ALTIVEC) { 567 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 568 569 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 570 } 571 572 /* Advertise DFP (Decimal Floating Point) if available 573 * 0 / no property == no DFP 574 * 1 == DFP available */ 575 if (env->insns_flags2 & PPC2_DFP) { 576 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 577 } 578 579 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 580 sizeof(page_sizes_prop)); 581 if (page_sizes_prop_size) { 582 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 583 page_sizes_prop, page_sizes_prop_size))); 584 } 585 586 spapr_populate_pa_features(env, fdt, offset, false); 587 588 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 589 cs->cpu_index / vcpus_per_socket))); 590 591 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 592 pft_size_prop, sizeof(pft_size_prop)))); 593 594 if (nb_numa_nodes > 1) { 595 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 596 } 597 598 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 599 600 if (pcc->radix_page_info) { 601 for (i = 0; i < pcc->radix_page_info->count; i++) { 602 radix_AP_encodings[i] = 603 cpu_to_be32(pcc->radix_page_info->entries[i]); 604 } 605 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 606 radix_AP_encodings, 607 pcc->radix_page_info->count * 608 sizeof(radix_AP_encodings[0])))); 609 } 610 } 611 612 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 613 { 614 CPUState *cs; 615 int cpus_offset; 616 char *nodename; 617 int smt = kvmppc_smt_threads(); 618 619 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 620 _FDT(cpus_offset); 621 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 622 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 623 624 /* 625 * We walk the CPUs in reverse order to ensure that CPU DT nodes 626 * created by fdt_add_subnode() end up in the right order in FDT 627 * for the guest kernel the enumerate the CPUs correctly. 628 */ 629 CPU_FOREACH_REVERSE(cs) { 630 PowerPCCPU *cpu = POWERPC_CPU(cs); 631 int index = ppc_get_vcpu_dt_id(cpu); 632 DeviceClass *dc = DEVICE_GET_CLASS(cs); 633 int offset; 634 635 if ((index % smt) != 0) { 636 continue; 637 } 638 639 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 640 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 641 g_free(nodename); 642 _FDT(offset); 643 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 644 } 645 646 } 647 648 /* 649 * Adds ibm,dynamic-reconfiguration-memory node. 650 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 651 * of this device tree node. 652 */ 653 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 654 { 655 MachineState *machine = MACHINE(spapr); 656 int ret, i, offset; 657 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 658 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 659 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 660 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 661 memory_region_size(&spapr->hotplug_memory.mr)) / 662 lmb_size; 663 uint32_t *int_buf, *cur_index, buf_len; 664 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 665 666 /* 667 * Don't create the node if there is no hotpluggable memory 668 */ 669 if (machine->ram_size == machine->maxram_size) { 670 return 0; 671 } 672 673 /* 674 * Allocate enough buffer size to fit in ibm,dynamic-memory 675 * or ibm,associativity-lookup-arrays 676 */ 677 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 678 * sizeof(uint32_t); 679 cur_index = int_buf = g_malloc0(buf_len); 680 681 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 682 683 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 684 sizeof(prop_lmb_size)); 685 if (ret < 0) { 686 goto out; 687 } 688 689 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 690 if (ret < 0) { 691 goto out; 692 } 693 694 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 695 if (ret < 0) { 696 goto out; 697 } 698 699 /* ibm,dynamic-memory */ 700 int_buf[0] = cpu_to_be32(nr_lmbs); 701 cur_index++; 702 for (i = 0; i < nr_lmbs; i++) { 703 uint64_t addr = i * lmb_size; 704 uint32_t *dynamic_memory = cur_index; 705 706 if (i >= hotplug_lmb_start) { 707 sPAPRDRConnector *drc; 708 709 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 710 g_assert(drc); 711 712 dynamic_memory[0] = cpu_to_be32(addr >> 32); 713 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 714 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 715 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 716 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 717 if (memory_region_present(get_system_memory(), addr)) { 718 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 719 } else { 720 dynamic_memory[5] = cpu_to_be32(0); 721 } 722 } else { 723 /* 724 * LMB information for RMA, boot time RAM and gap b/n RAM and 725 * hotplug memory region -- all these are marked as reserved 726 * and as having no valid DRC. 727 */ 728 dynamic_memory[0] = cpu_to_be32(addr >> 32); 729 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 730 dynamic_memory[2] = cpu_to_be32(0); 731 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 732 dynamic_memory[4] = cpu_to_be32(-1); 733 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 734 SPAPR_LMB_FLAGS_DRC_INVALID); 735 } 736 737 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 738 } 739 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 740 if (ret < 0) { 741 goto out; 742 } 743 744 /* ibm,associativity-lookup-arrays */ 745 cur_index = int_buf; 746 int_buf[0] = cpu_to_be32(nr_nodes); 747 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 748 cur_index += 2; 749 for (i = 0; i < nr_nodes; i++) { 750 uint32_t associativity[] = { 751 cpu_to_be32(0x0), 752 cpu_to_be32(0x0), 753 cpu_to_be32(0x0), 754 cpu_to_be32(i) 755 }; 756 memcpy(cur_index, associativity, sizeof(associativity)); 757 cur_index += 4; 758 } 759 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 760 (cur_index - int_buf) * sizeof(uint32_t)); 761 out: 762 g_free(int_buf); 763 return ret; 764 } 765 766 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 767 sPAPROptionVector *ov5_updates) 768 { 769 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 770 int ret = 0, offset; 771 772 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 773 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 774 g_assert(smc->dr_lmb_enabled); 775 ret = spapr_populate_drconf_memory(spapr, fdt); 776 if (ret) { 777 goto out; 778 } 779 } 780 781 /* /interrupt controller */ 782 if (!spapr_ovec_test(ov5_updates, OV5_XIVE_EXPLOIT)) { 783 spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP); 784 } 785 786 offset = fdt_path_offset(fdt, "/chosen"); 787 if (offset < 0) { 788 offset = fdt_add_subnode(fdt, 0, "chosen"); 789 if (offset < 0) { 790 return offset; 791 } 792 } 793 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 794 "ibm,architecture-vec-5"); 795 796 out: 797 return ret; 798 } 799 800 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 801 target_ulong addr, target_ulong size, 802 sPAPROptionVector *ov5_updates) 803 { 804 void *fdt, *fdt_skel; 805 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 806 807 size -= sizeof(hdr); 808 809 /* Create skeleton */ 810 fdt_skel = g_malloc0(size); 811 _FDT((fdt_create(fdt_skel, size))); 812 _FDT((fdt_begin_node(fdt_skel, ""))); 813 _FDT((fdt_end_node(fdt_skel))); 814 _FDT((fdt_finish(fdt_skel))); 815 fdt = g_malloc0(size); 816 _FDT((fdt_open_into(fdt_skel, fdt, size))); 817 g_free(fdt_skel); 818 819 /* Fixup cpu nodes */ 820 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 821 822 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 823 return -1; 824 } 825 826 /* Pack resulting tree */ 827 _FDT((fdt_pack(fdt))); 828 829 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 830 trace_spapr_cas_failed(size); 831 return -1; 832 } 833 834 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 835 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 836 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 837 g_free(fdt); 838 839 return 0; 840 } 841 842 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 843 { 844 int rtas; 845 GString *hypertas = g_string_sized_new(256); 846 GString *qemu_hypertas = g_string_sized_new(256); 847 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 848 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 849 memory_region_size(&spapr->hotplug_memory.mr); 850 uint32_t lrdr_capacity[] = { 851 cpu_to_be32(max_hotplug_addr >> 32), 852 cpu_to_be32(max_hotplug_addr & 0xffffffff), 853 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 854 cpu_to_be32(max_cpus / smp_threads), 855 }; 856 857 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 858 859 /* hypertas */ 860 add_str(hypertas, "hcall-pft"); 861 add_str(hypertas, "hcall-term"); 862 add_str(hypertas, "hcall-dabr"); 863 add_str(hypertas, "hcall-interrupt"); 864 add_str(hypertas, "hcall-tce"); 865 add_str(hypertas, "hcall-vio"); 866 add_str(hypertas, "hcall-splpar"); 867 add_str(hypertas, "hcall-bulk"); 868 add_str(hypertas, "hcall-set-mode"); 869 add_str(hypertas, "hcall-sprg0"); 870 add_str(hypertas, "hcall-copy"); 871 add_str(hypertas, "hcall-debug"); 872 add_str(qemu_hypertas, "hcall-memop1"); 873 874 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 875 add_str(hypertas, "hcall-multi-tce"); 876 } 877 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 878 hypertas->str, hypertas->len)); 879 g_string_free(hypertas, TRUE); 880 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 881 qemu_hypertas->str, qemu_hypertas->len)); 882 g_string_free(qemu_hypertas, TRUE); 883 884 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 885 refpoints, sizeof(refpoints))); 886 887 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 888 RTAS_ERROR_LOG_MAX)); 889 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 890 RTAS_EVENT_SCAN_RATE)); 891 892 if (msi_nonbroken) { 893 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 894 } 895 896 /* 897 * According to PAPR, rtas ibm,os-term does not guarantee a return 898 * back to the guest cpu. 899 * 900 * While an additional ibm,extended-os-term property indicates 901 * that rtas call return will always occur. Set this property. 902 */ 903 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 904 905 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 906 lrdr_capacity, sizeof(lrdr_capacity))); 907 908 spapr_dt_rtas_tokens(fdt, rtas); 909 } 910 911 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features 912 * that the guest may request and thus the valid values for bytes 24..26 of 913 * option vector 5: */ 914 static void spapr_dt_ov5_platform_support(void *fdt, int chosen) 915 { 916 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 917 918 char val[2 * 4] = { 919 23, 0x00, /* Xive mode: 0 = legacy (as in ISA 2.7), 1 = Exploitation */ 920 24, 0x00, /* Hash/Radix, filled in below. */ 921 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 922 26, 0x40, /* Radix options: GTSE == yes. */ 923 }; 924 925 if (kvm_enabled()) { 926 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 927 val[3] = 0x80; /* OV5_MMU_BOTH */ 928 } else if (kvmppc_has_cap_mmu_radix()) { 929 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 930 } else { 931 val[3] = 0x00; /* Hash */ 932 } 933 } else { 934 if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) { 935 /* V3 MMU supports both hash and radix (with dynamic switching) */ 936 val[3] = 0xC0; 937 } else { 938 /* Otherwise we can only do hash */ 939 val[3] = 0x00; 940 } 941 } 942 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 943 val, sizeof(val))); 944 } 945 946 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 947 { 948 MachineState *machine = MACHINE(spapr); 949 int chosen; 950 const char *boot_device = machine->boot_order; 951 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 952 size_t cb = 0; 953 char *bootlist = get_boot_devices_list(&cb, true); 954 955 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 956 957 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 958 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 959 spapr->initrd_base)); 960 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 961 spapr->initrd_base + spapr->initrd_size)); 962 963 if (spapr->kernel_size) { 964 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 965 cpu_to_be64(spapr->kernel_size) }; 966 967 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 968 &kprop, sizeof(kprop))); 969 if (spapr->kernel_le) { 970 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 971 } 972 } 973 if (boot_menu) { 974 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 975 } 976 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 977 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 978 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 979 980 if (cb && bootlist) { 981 int i; 982 983 for (i = 0; i < cb; i++) { 984 if (bootlist[i] == '\n') { 985 bootlist[i] = ' '; 986 } 987 } 988 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 989 } 990 991 if (boot_device && strlen(boot_device)) { 992 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 993 } 994 995 if (!spapr->has_graphics && stdout_path) { 996 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 997 } 998 999 spapr_dt_ov5_platform_support(fdt, chosen); 1000 1001 g_free(stdout_path); 1002 g_free(bootlist); 1003 } 1004 1005 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 1006 { 1007 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1008 * KVM to work under pHyp with some guest co-operation */ 1009 int hypervisor; 1010 uint8_t hypercall[16]; 1011 1012 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1013 /* indicate KVM hypercall interface */ 1014 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1015 if (kvmppc_has_cap_fixup_hcalls()) { 1016 /* 1017 * Older KVM versions with older guest kernels were broken 1018 * with the magic page, don't allow the guest to map it. 1019 */ 1020 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1021 sizeof(hypercall))) { 1022 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1023 hypercall, sizeof(hypercall))); 1024 } 1025 } 1026 } 1027 1028 static void *spapr_build_fdt(sPAPRMachineState *spapr, 1029 hwaddr rtas_addr, 1030 hwaddr rtas_size) 1031 { 1032 MachineState *machine = MACHINE(qdev_get_machine()); 1033 MachineClass *mc = MACHINE_GET_CLASS(machine); 1034 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1035 int ret; 1036 void *fdt; 1037 sPAPRPHBState *phb; 1038 char *buf; 1039 1040 fdt = g_malloc0(FDT_MAX_SIZE); 1041 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1042 1043 /* Root node */ 1044 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1045 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1046 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1047 1048 /* 1049 * Add info to guest to indentify which host is it being run on 1050 * and what is the uuid of the guest 1051 */ 1052 if (kvmppc_get_host_model(&buf)) { 1053 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1054 g_free(buf); 1055 } 1056 if (kvmppc_get_host_serial(&buf)) { 1057 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1058 g_free(buf); 1059 } 1060 1061 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1062 1063 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1064 if (qemu_uuid_set) { 1065 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1066 } 1067 g_free(buf); 1068 1069 if (qemu_get_vm_name()) { 1070 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1071 qemu_get_vm_name())); 1072 } 1073 1074 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1075 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1076 1077 ret = spapr_populate_memory(spapr, fdt); 1078 if (ret < 0) { 1079 error_report("couldn't setup memory nodes in fdt"); 1080 exit(1); 1081 } 1082 1083 /* /vdevice */ 1084 spapr_dt_vdevice(spapr->vio_bus, fdt); 1085 1086 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1087 ret = spapr_rng_populate_dt(fdt); 1088 if (ret < 0) { 1089 error_report("could not set up rng device in the fdt"); 1090 exit(1); 1091 } 1092 } 1093 1094 QLIST_FOREACH(phb, &spapr->phbs, list) { 1095 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 1096 if (ret < 0) { 1097 error_report("couldn't setup PCI devices in fdt"); 1098 exit(1); 1099 } 1100 } 1101 1102 /* cpus */ 1103 spapr_populate_cpus_dt_node(fdt, spapr); 1104 1105 if (smc->dr_lmb_enabled) { 1106 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1107 } 1108 1109 if (mc->has_hotpluggable_cpus) { 1110 int offset = fdt_path_offset(fdt, "/cpus"); 1111 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1112 SPAPR_DR_CONNECTOR_TYPE_CPU); 1113 if (ret < 0) { 1114 error_report("Couldn't set up CPU DR device tree properties"); 1115 exit(1); 1116 } 1117 } 1118 1119 /* /event-sources */ 1120 spapr_dt_events(spapr, fdt); 1121 1122 /* /rtas */ 1123 spapr_dt_rtas(spapr, fdt); 1124 1125 /* /chosen */ 1126 spapr_dt_chosen(spapr, fdt); 1127 1128 /* /hypervisor */ 1129 if (kvm_enabled()) { 1130 spapr_dt_hypervisor(spapr, fdt); 1131 } 1132 1133 /* Build memory reserve map */ 1134 if (spapr->kernel_size) { 1135 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1136 } 1137 if (spapr->initrd_size) { 1138 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1139 } 1140 1141 /* ibm,client-architecture-support updates */ 1142 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1143 if (ret < 0) { 1144 error_report("couldn't setup CAS properties fdt"); 1145 exit(1); 1146 } 1147 1148 return fdt; 1149 } 1150 1151 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1152 { 1153 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1154 } 1155 1156 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1157 PowerPCCPU *cpu) 1158 { 1159 CPUPPCState *env = &cpu->env; 1160 1161 /* The TCG path should also be holding the BQL at this point */ 1162 g_assert(qemu_mutex_iothread_locked()); 1163 1164 if (msr_pr) { 1165 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1166 env->gpr[3] = H_PRIVILEGE; 1167 } else { 1168 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1169 } 1170 } 1171 1172 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1173 { 1174 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1175 1176 return spapr->patb_entry; 1177 } 1178 1179 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1180 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1181 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1182 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1183 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1184 1185 /* 1186 * Get the fd to access the kernel htab, re-opening it if necessary 1187 */ 1188 static int get_htab_fd(sPAPRMachineState *spapr) 1189 { 1190 if (spapr->htab_fd >= 0) { 1191 return spapr->htab_fd; 1192 } 1193 1194 spapr->htab_fd = kvmppc_get_htab_fd(false); 1195 if (spapr->htab_fd < 0) { 1196 error_report("Unable to open fd for reading hash table from KVM: %s", 1197 strerror(errno)); 1198 } 1199 1200 return spapr->htab_fd; 1201 } 1202 1203 void close_htab_fd(sPAPRMachineState *spapr) 1204 { 1205 if (spapr->htab_fd >= 0) { 1206 close(spapr->htab_fd); 1207 } 1208 spapr->htab_fd = -1; 1209 } 1210 1211 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1212 { 1213 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1214 1215 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1216 } 1217 1218 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1219 hwaddr ptex, int n) 1220 { 1221 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1222 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1223 1224 if (!spapr->htab) { 1225 /* 1226 * HTAB is controlled by KVM. Fetch into temporary buffer 1227 */ 1228 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1229 kvmppc_read_hptes(hptes, ptex, n); 1230 return hptes; 1231 } 1232 1233 /* 1234 * HTAB is controlled by QEMU. Just point to the internally 1235 * accessible PTEG. 1236 */ 1237 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1238 } 1239 1240 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1241 const ppc_hash_pte64_t *hptes, 1242 hwaddr ptex, int n) 1243 { 1244 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1245 1246 if (!spapr->htab) { 1247 g_free((void *)hptes); 1248 } 1249 1250 /* Nothing to do for qemu managed HPT */ 1251 } 1252 1253 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1254 uint64_t pte0, uint64_t pte1) 1255 { 1256 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1257 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1258 1259 if (!spapr->htab) { 1260 kvmppc_write_hpte(ptex, pte0, pte1); 1261 } else { 1262 stq_p(spapr->htab + offset, pte0); 1263 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1264 } 1265 } 1266 1267 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1268 { 1269 int shift; 1270 1271 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1272 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1273 * that's much more than is needed for Linux guests */ 1274 shift = ctz64(pow2ceil(ramsize)) - 7; 1275 shift = MAX(shift, 18); /* Minimum architected size */ 1276 shift = MIN(shift, 46); /* Maximum architected size */ 1277 return shift; 1278 } 1279 1280 void spapr_free_hpt(sPAPRMachineState *spapr) 1281 { 1282 g_free(spapr->htab); 1283 spapr->htab = NULL; 1284 spapr->htab_shift = 0; 1285 close_htab_fd(spapr); 1286 } 1287 1288 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1289 Error **errp) 1290 { 1291 long rc; 1292 1293 /* Clean up any HPT info from a previous boot */ 1294 spapr_free_hpt(spapr); 1295 1296 rc = kvmppc_reset_htab(shift); 1297 if (rc < 0) { 1298 /* kernel-side HPT needed, but couldn't allocate one */ 1299 error_setg_errno(errp, errno, 1300 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1301 shift); 1302 /* This is almost certainly fatal, but if the caller really 1303 * wants to carry on with shift == 0, it's welcome to try */ 1304 } else if (rc > 0) { 1305 /* kernel-side HPT allocated */ 1306 if (rc != shift) { 1307 error_setg(errp, 1308 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1309 shift, rc); 1310 } 1311 1312 spapr->htab_shift = shift; 1313 spapr->htab = NULL; 1314 } else { 1315 /* kernel-side HPT not needed, allocate in userspace instead */ 1316 size_t size = 1ULL << shift; 1317 int i; 1318 1319 spapr->htab = qemu_memalign(size, size); 1320 if (!spapr->htab) { 1321 error_setg_errno(errp, errno, 1322 "Could not allocate HPT of order %d", shift); 1323 return; 1324 } 1325 1326 memset(spapr->htab, 0, size); 1327 spapr->htab_shift = shift; 1328 1329 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1330 DIRTY_HPTE(HPTE(spapr->htab, i)); 1331 } 1332 } 1333 } 1334 1335 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1336 { 1337 spapr_reallocate_hpt(spapr, 1338 spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size), 1339 &error_fatal); 1340 if (spapr->vrma_adjust) { 1341 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1342 spapr->htab_shift); 1343 } 1344 /* We're setting up a hash table, so that means we're not radix */ 1345 spapr->patb_entry = 0; 1346 } 1347 1348 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1349 { 1350 bool matched = false; 1351 1352 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1353 matched = true; 1354 } 1355 1356 if (!matched) { 1357 error_report("Device %s is not supported by this machine yet.", 1358 qdev_fw_name(DEVICE(sbdev))); 1359 exit(1); 1360 } 1361 } 1362 1363 static void ppc_spapr_reset(void) 1364 { 1365 MachineState *machine = MACHINE(qdev_get_machine()); 1366 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1367 PowerPCCPU *first_ppc_cpu; 1368 uint32_t rtas_limit; 1369 hwaddr rtas_addr, fdt_addr; 1370 void *fdt; 1371 int rc; 1372 1373 /* Check for unknown sysbus devices */ 1374 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1375 1376 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()) { 1377 /* If using KVM with radix mode available, VCPUs can be started 1378 * without a HPT because KVM will start them in radix mode. 1379 * Set the GR bit in PATB so that we know there is no HPT. */ 1380 spapr->patb_entry = PATBE1_GR; 1381 } else { 1382 spapr_setup_hpt_and_vrma(spapr); 1383 } 1384 1385 qemu_devices_reset(); 1386 1387 /* 1388 * We place the device tree and RTAS just below either the top of the RMA, 1389 * or just below 2GB, whichever is lowere, so that it can be 1390 * processed with 32-bit real mode code if necessary 1391 */ 1392 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1393 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1394 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1395 1396 /* if this reset wasn't generated by CAS, we should reset our 1397 * negotiated options and start from scratch */ 1398 if (!spapr->cas_reboot) { 1399 spapr_ovec_cleanup(spapr->ov5_cas); 1400 spapr->ov5_cas = spapr_ovec_new(); 1401 1402 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1403 } 1404 1405 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1406 1407 spapr_load_rtas(spapr, fdt, rtas_addr); 1408 1409 rc = fdt_pack(fdt); 1410 1411 /* Should only fail if we've built a corrupted tree */ 1412 assert(rc == 0); 1413 1414 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1415 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1416 fdt_totalsize(fdt), FDT_MAX_SIZE); 1417 exit(1); 1418 } 1419 1420 /* Load the fdt */ 1421 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1422 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1423 g_free(fdt); 1424 1425 /* Set up the entry state */ 1426 first_ppc_cpu = POWERPC_CPU(first_cpu); 1427 first_ppc_cpu->env.gpr[3] = fdt_addr; 1428 first_ppc_cpu->env.gpr[5] = 0; 1429 first_cpu->halted = 0; 1430 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1431 1432 spapr->cas_reboot = false; 1433 } 1434 1435 static void spapr_create_nvram(sPAPRMachineState *spapr) 1436 { 1437 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1438 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1439 1440 if (dinfo) { 1441 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1442 &error_fatal); 1443 } 1444 1445 qdev_init_nofail(dev); 1446 1447 spapr->nvram = (struct sPAPRNVRAM *)dev; 1448 } 1449 1450 static void spapr_rtc_create(sPAPRMachineState *spapr) 1451 { 1452 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1453 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1454 &error_fatal); 1455 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1456 &error_fatal); 1457 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1458 "date", &error_fatal); 1459 } 1460 1461 /* Returns whether we want to use VGA or not */ 1462 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1463 { 1464 switch (vga_interface_type) { 1465 case VGA_NONE: 1466 return false; 1467 case VGA_DEVICE: 1468 return true; 1469 case VGA_STD: 1470 case VGA_VIRTIO: 1471 return pci_vga_init(pci_bus) != NULL; 1472 default: 1473 error_setg(errp, 1474 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1475 return false; 1476 } 1477 } 1478 1479 static int spapr_post_load(void *opaque, int version_id) 1480 { 1481 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1482 int err = 0; 1483 1484 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1485 CPUState *cs; 1486 CPU_FOREACH(cs) { 1487 PowerPCCPU *cpu = POWERPC_CPU(cs); 1488 icp_resend(ICP(cpu->intc)); 1489 } 1490 } 1491 1492 /* In earlier versions, there was no separate qdev for the PAPR 1493 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1494 * So when migrating from those versions, poke the incoming offset 1495 * value into the RTC device */ 1496 if (version_id < 3) { 1497 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1498 } 1499 1500 if (spapr->patb_entry) { 1501 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1502 bool radix = !!(spapr->patb_entry & PATBE1_GR); 1503 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1504 1505 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1506 if (err) { 1507 error_report("Process table config unsupported by the host"); 1508 return -EINVAL; 1509 } 1510 } 1511 1512 return err; 1513 } 1514 1515 static bool version_before_3(void *opaque, int version_id) 1516 { 1517 return version_id < 3; 1518 } 1519 1520 static bool spapr_ov5_cas_needed(void *opaque) 1521 { 1522 sPAPRMachineState *spapr = opaque; 1523 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1524 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1525 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1526 bool cas_needed; 1527 1528 /* Prior to the introduction of sPAPROptionVector, we had two option 1529 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1530 * Both of these options encode machine topology into the device-tree 1531 * in such a way that the now-booted OS should still be able to interact 1532 * appropriately with QEMU regardless of what options were actually 1533 * negotiatied on the source side. 1534 * 1535 * As such, we can avoid migrating the CAS-negotiated options if these 1536 * are the only options available on the current machine/platform. 1537 * Since these are the only options available for pseries-2.7 and 1538 * earlier, this allows us to maintain old->new/new->old migration 1539 * compatibility. 1540 * 1541 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1542 * via default pseries-2.8 machines and explicit command-line parameters. 1543 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1544 * of the actual CAS-negotiated values to continue working properly. For 1545 * example, availability of memory unplug depends on knowing whether 1546 * OV5_HP_EVT was negotiated via CAS. 1547 * 1548 * Thus, for any cases where the set of available CAS-negotiatable 1549 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1550 * include the CAS-negotiated options in the migration stream. 1551 */ 1552 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1553 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1554 1555 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1556 * the mask itself since in the future it's possible "legacy" bits may be 1557 * removed via machine options, which could generate a false positive 1558 * that breaks migration. 1559 */ 1560 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1561 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1562 1563 spapr_ovec_cleanup(ov5_mask); 1564 spapr_ovec_cleanup(ov5_legacy); 1565 spapr_ovec_cleanup(ov5_removed); 1566 1567 return cas_needed; 1568 } 1569 1570 static const VMStateDescription vmstate_spapr_ov5_cas = { 1571 .name = "spapr_option_vector_ov5_cas", 1572 .version_id = 1, 1573 .minimum_version_id = 1, 1574 .needed = spapr_ov5_cas_needed, 1575 .fields = (VMStateField[]) { 1576 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1577 vmstate_spapr_ovec, sPAPROptionVector), 1578 VMSTATE_END_OF_LIST() 1579 }, 1580 }; 1581 1582 static bool spapr_patb_entry_needed(void *opaque) 1583 { 1584 sPAPRMachineState *spapr = opaque; 1585 1586 return !!spapr->patb_entry; 1587 } 1588 1589 static const VMStateDescription vmstate_spapr_patb_entry = { 1590 .name = "spapr_patb_entry", 1591 .version_id = 1, 1592 .minimum_version_id = 1, 1593 .needed = spapr_patb_entry_needed, 1594 .fields = (VMStateField[]) { 1595 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1596 VMSTATE_END_OF_LIST() 1597 }, 1598 }; 1599 1600 static const VMStateDescription vmstate_spapr = { 1601 .name = "spapr", 1602 .version_id = 3, 1603 .minimum_version_id = 1, 1604 .post_load = spapr_post_load, 1605 .fields = (VMStateField[]) { 1606 /* used to be @next_irq */ 1607 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1608 1609 /* RTC offset */ 1610 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1611 1612 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1613 VMSTATE_END_OF_LIST() 1614 }, 1615 .subsections = (const VMStateDescription*[]) { 1616 &vmstate_spapr_ov5_cas, 1617 &vmstate_spapr_patb_entry, 1618 NULL 1619 } 1620 }; 1621 1622 static int htab_save_setup(QEMUFile *f, void *opaque) 1623 { 1624 sPAPRMachineState *spapr = opaque; 1625 1626 /* "Iteration" header */ 1627 if (!spapr->htab_shift) { 1628 qemu_put_be32(f, -1); 1629 } else { 1630 qemu_put_be32(f, spapr->htab_shift); 1631 } 1632 1633 if (spapr->htab) { 1634 spapr->htab_save_index = 0; 1635 spapr->htab_first_pass = true; 1636 } else { 1637 if (spapr->htab_shift) { 1638 assert(kvm_enabled()); 1639 } 1640 } 1641 1642 1643 return 0; 1644 } 1645 1646 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1647 int64_t max_ns) 1648 { 1649 bool has_timeout = max_ns != -1; 1650 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1651 int index = spapr->htab_save_index; 1652 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1653 1654 assert(spapr->htab_first_pass); 1655 1656 do { 1657 int chunkstart; 1658 1659 /* Consume invalid HPTEs */ 1660 while ((index < htabslots) 1661 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1662 CLEAN_HPTE(HPTE(spapr->htab, index)); 1663 index++; 1664 } 1665 1666 /* Consume valid HPTEs */ 1667 chunkstart = index; 1668 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1669 && HPTE_VALID(HPTE(spapr->htab, index))) { 1670 CLEAN_HPTE(HPTE(spapr->htab, index)); 1671 index++; 1672 } 1673 1674 if (index > chunkstart) { 1675 int n_valid = index - chunkstart; 1676 1677 qemu_put_be32(f, chunkstart); 1678 qemu_put_be16(f, n_valid); 1679 qemu_put_be16(f, 0); 1680 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1681 HASH_PTE_SIZE_64 * n_valid); 1682 1683 if (has_timeout && 1684 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1685 break; 1686 } 1687 } 1688 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1689 1690 if (index >= htabslots) { 1691 assert(index == htabslots); 1692 index = 0; 1693 spapr->htab_first_pass = false; 1694 } 1695 spapr->htab_save_index = index; 1696 } 1697 1698 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1699 int64_t max_ns) 1700 { 1701 bool final = max_ns < 0; 1702 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1703 int examined = 0, sent = 0; 1704 int index = spapr->htab_save_index; 1705 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1706 1707 assert(!spapr->htab_first_pass); 1708 1709 do { 1710 int chunkstart, invalidstart; 1711 1712 /* Consume non-dirty HPTEs */ 1713 while ((index < htabslots) 1714 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1715 index++; 1716 examined++; 1717 } 1718 1719 chunkstart = index; 1720 /* Consume valid dirty HPTEs */ 1721 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1722 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1723 && HPTE_VALID(HPTE(spapr->htab, index))) { 1724 CLEAN_HPTE(HPTE(spapr->htab, index)); 1725 index++; 1726 examined++; 1727 } 1728 1729 invalidstart = index; 1730 /* Consume invalid dirty HPTEs */ 1731 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1732 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1733 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1734 CLEAN_HPTE(HPTE(spapr->htab, index)); 1735 index++; 1736 examined++; 1737 } 1738 1739 if (index > chunkstart) { 1740 int n_valid = invalidstart - chunkstart; 1741 int n_invalid = index - invalidstart; 1742 1743 qemu_put_be32(f, chunkstart); 1744 qemu_put_be16(f, n_valid); 1745 qemu_put_be16(f, n_invalid); 1746 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1747 HASH_PTE_SIZE_64 * n_valid); 1748 sent += index - chunkstart; 1749 1750 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1751 break; 1752 } 1753 } 1754 1755 if (examined >= htabslots) { 1756 break; 1757 } 1758 1759 if (index >= htabslots) { 1760 assert(index == htabslots); 1761 index = 0; 1762 } 1763 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1764 1765 if (index >= htabslots) { 1766 assert(index == htabslots); 1767 index = 0; 1768 } 1769 1770 spapr->htab_save_index = index; 1771 1772 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1773 } 1774 1775 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1776 #define MAX_KVM_BUF_SIZE 2048 1777 1778 static int htab_save_iterate(QEMUFile *f, void *opaque) 1779 { 1780 sPAPRMachineState *spapr = opaque; 1781 int fd; 1782 int rc = 0; 1783 1784 /* Iteration header */ 1785 if (!spapr->htab_shift) { 1786 qemu_put_be32(f, -1); 1787 return 0; 1788 } else { 1789 qemu_put_be32(f, 0); 1790 } 1791 1792 if (!spapr->htab) { 1793 assert(kvm_enabled()); 1794 1795 fd = get_htab_fd(spapr); 1796 if (fd < 0) { 1797 return fd; 1798 } 1799 1800 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1801 if (rc < 0) { 1802 return rc; 1803 } 1804 } else if (spapr->htab_first_pass) { 1805 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1806 } else { 1807 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1808 } 1809 1810 /* End marker */ 1811 qemu_put_be32(f, 0); 1812 qemu_put_be16(f, 0); 1813 qemu_put_be16(f, 0); 1814 1815 return rc; 1816 } 1817 1818 static int htab_save_complete(QEMUFile *f, void *opaque) 1819 { 1820 sPAPRMachineState *spapr = opaque; 1821 int fd; 1822 1823 /* Iteration header */ 1824 if (!spapr->htab_shift) { 1825 qemu_put_be32(f, -1); 1826 return 0; 1827 } else { 1828 qemu_put_be32(f, 0); 1829 } 1830 1831 if (!spapr->htab) { 1832 int rc; 1833 1834 assert(kvm_enabled()); 1835 1836 fd = get_htab_fd(spapr); 1837 if (fd < 0) { 1838 return fd; 1839 } 1840 1841 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1842 if (rc < 0) { 1843 return rc; 1844 } 1845 } else { 1846 if (spapr->htab_first_pass) { 1847 htab_save_first_pass(f, spapr, -1); 1848 } 1849 htab_save_later_pass(f, spapr, -1); 1850 } 1851 1852 /* End marker */ 1853 qemu_put_be32(f, 0); 1854 qemu_put_be16(f, 0); 1855 qemu_put_be16(f, 0); 1856 1857 return 0; 1858 } 1859 1860 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1861 { 1862 sPAPRMachineState *spapr = opaque; 1863 uint32_t section_hdr; 1864 int fd = -1; 1865 1866 if (version_id < 1 || version_id > 1) { 1867 error_report("htab_load() bad version"); 1868 return -EINVAL; 1869 } 1870 1871 section_hdr = qemu_get_be32(f); 1872 1873 if (section_hdr == -1) { 1874 spapr_free_hpt(spapr); 1875 return 0; 1876 } 1877 1878 if (section_hdr) { 1879 Error *local_err = NULL; 1880 1881 /* First section gives the htab size */ 1882 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1883 if (local_err) { 1884 error_report_err(local_err); 1885 return -EINVAL; 1886 } 1887 return 0; 1888 } 1889 1890 if (!spapr->htab) { 1891 assert(kvm_enabled()); 1892 1893 fd = kvmppc_get_htab_fd(true); 1894 if (fd < 0) { 1895 error_report("Unable to open fd to restore KVM hash table: %s", 1896 strerror(errno)); 1897 } 1898 } 1899 1900 while (true) { 1901 uint32_t index; 1902 uint16_t n_valid, n_invalid; 1903 1904 index = qemu_get_be32(f); 1905 n_valid = qemu_get_be16(f); 1906 n_invalid = qemu_get_be16(f); 1907 1908 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1909 /* End of Stream */ 1910 break; 1911 } 1912 1913 if ((index + n_valid + n_invalid) > 1914 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1915 /* Bad index in stream */ 1916 error_report( 1917 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1918 index, n_valid, n_invalid, spapr->htab_shift); 1919 return -EINVAL; 1920 } 1921 1922 if (spapr->htab) { 1923 if (n_valid) { 1924 qemu_get_buffer(f, HPTE(spapr->htab, index), 1925 HASH_PTE_SIZE_64 * n_valid); 1926 } 1927 if (n_invalid) { 1928 memset(HPTE(spapr->htab, index + n_valid), 0, 1929 HASH_PTE_SIZE_64 * n_invalid); 1930 } 1931 } else { 1932 int rc; 1933 1934 assert(fd >= 0); 1935 1936 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1937 if (rc < 0) { 1938 return rc; 1939 } 1940 } 1941 } 1942 1943 if (!spapr->htab) { 1944 assert(fd >= 0); 1945 close(fd); 1946 } 1947 1948 return 0; 1949 } 1950 1951 static void htab_save_cleanup(void *opaque) 1952 { 1953 sPAPRMachineState *spapr = opaque; 1954 1955 close_htab_fd(spapr); 1956 } 1957 1958 static SaveVMHandlers savevm_htab_handlers = { 1959 .save_setup = htab_save_setup, 1960 .save_live_iterate = htab_save_iterate, 1961 .save_live_complete_precopy = htab_save_complete, 1962 .save_cleanup = htab_save_cleanup, 1963 .load_state = htab_load, 1964 }; 1965 1966 static void spapr_boot_set(void *opaque, const char *boot_device, 1967 Error **errp) 1968 { 1969 MachineState *machine = MACHINE(qdev_get_machine()); 1970 machine->boot_order = g_strdup(boot_device); 1971 } 1972 1973 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1974 { 1975 MachineState *machine = MACHINE(spapr); 1976 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1977 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1978 int i; 1979 1980 for (i = 0; i < nr_lmbs; i++) { 1981 uint64_t addr; 1982 1983 addr = i * lmb_size + spapr->hotplug_memory.base; 1984 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 1985 addr / lmb_size); 1986 } 1987 } 1988 1989 /* 1990 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1991 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1992 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1993 */ 1994 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 1995 { 1996 int i; 1997 1998 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1999 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2000 " is not aligned to %llu MiB", 2001 machine->ram_size, 2002 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2003 return; 2004 } 2005 2006 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2007 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2008 " is not aligned to %llu MiB", 2009 machine->ram_size, 2010 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2011 return; 2012 } 2013 2014 for (i = 0; i < nb_numa_nodes; i++) { 2015 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2016 error_setg(errp, 2017 "Node %d memory size 0x%" PRIx64 2018 " is not aligned to %llu MiB", 2019 i, numa_info[i].node_mem, 2020 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2021 return; 2022 } 2023 } 2024 } 2025 2026 /* find cpu slot in machine->possible_cpus by core_id */ 2027 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2028 { 2029 int index = id / smp_threads; 2030 2031 if (index >= ms->possible_cpus->len) { 2032 return NULL; 2033 } 2034 if (idx) { 2035 *idx = index; 2036 } 2037 return &ms->possible_cpus->cpus[index]; 2038 } 2039 2040 static void spapr_init_cpus(sPAPRMachineState *spapr) 2041 { 2042 MachineState *machine = MACHINE(spapr); 2043 MachineClass *mc = MACHINE_GET_CLASS(machine); 2044 char *type = spapr_get_cpu_core_type(machine->cpu_model); 2045 int smt = kvmppc_smt_threads(); 2046 const CPUArchIdList *possible_cpus; 2047 int boot_cores_nr = smp_cpus / smp_threads; 2048 int i; 2049 2050 if (!type) { 2051 error_report("Unable to find sPAPR CPU Core definition"); 2052 exit(1); 2053 } 2054 2055 possible_cpus = mc->possible_cpu_arch_ids(machine); 2056 if (mc->has_hotpluggable_cpus) { 2057 if (smp_cpus % smp_threads) { 2058 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2059 smp_cpus, smp_threads); 2060 exit(1); 2061 } 2062 if (max_cpus % smp_threads) { 2063 error_report("max_cpus (%u) must be multiple of threads (%u)", 2064 max_cpus, smp_threads); 2065 exit(1); 2066 } 2067 } else { 2068 if (max_cpus != smp_cpus) { 2069 error_report("This machine version does not support CPU hotplug"); 2070 exit(1); 2071 } 2072 boot_cores_nr = possible_cpus->len; 2073 } 2074 2075 for (i = 0; i < possible_cpus->len; i++) { 2076 int core_id = i * smp_threads; 2077 2078 if (mc->has_hotpluggable_cpus) { 2079 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2080 (core_id / smp_threads) * smt); 2081 } 2082 2083 if (i < boot_cores_nr) { 2084 Object *core = object_new(type); 2085 int nr_threads = smp_threads; 2086 2087 /* Handle the partially filled core for older machine types */ 2088 if ((i + 1) * smp_threads >= smp_cpus) { 2089 nr_threads = smp_cpus - i * smp_threads; 2090 } 2091 2092 object_property_set_int(core, nr_threads, "nr-threads", 2093 &error_fatal); 2094 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2095 &error_fatal); 2096 object_property_set_bool(core, true, "realized", &error_fatal); 2097 } 2098 } 2099 g_free(type); 2100 } 2101 2102 /* pSeries LPAR / sPAPR hardware init */ 2103 static void ppc_spapr_init(MachineState *machine) 2104 { 2105 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2106 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2107 const char *kernel_filename = machine->kernel_filename; 2108 const char *initrd_filename = machine->initrd_filename; 2109 PCIHostState *phb; 2110 int i; 2111 MemoryRegion *sysmem = get_system_memory(); 2112 MemoryRegion *ram = g_new(MemoryRegion, 1); 2113 MemoryRegion *rma_region; 2114 void *rma = NULL; 2115 hwaddr rma_alloc_size; 2116 hwaddr node0_size = spapr_node0_size(); 2117 long load_limit, fw_size; 2118 char *filename; 2119 2120 msi_nonbroken = true; 2121 2122 QLIST_INIT(&spapr->phbs); 2123 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2124 2125 /* Allocate RMA if necessary */ 2126 rma_alloc_size = kvmppc_alloc_rma(&rma); 2127 2128 if (rma_alloc_size == -1) { 2129 error_report("Unable to create RMA"); 2130 exit(1); 2131 } 2132 2133 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 2134 spapr->rma_size = rma_alloc_size; 2135 } else { 2136 spapr->rma_size = node0_size; 2137 2138 /* With KVM, we don't actually know whether KVM supports an 2139 * unbounded RMA (PR KVM) or is limited by the hash table size 2140 * (HV KVM using VRMA), so we always assume the latter 2141 * 2142 * In that case, we also limit the initial allocations for RTAS 2143 * etc... to 256M since we have no way to know what the VRMA size 2144 * is going to be as it depends on the size of the hash table 2145 * isn't determined yet. 2146 */ 2147 if (kvm_enabled()) { 2148 spapr->vrma_adjust = 1; 2149 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2150 } 2151 2152 /* Actually we don't support unbounded RMA anymore since we 2153 * added proper emulation of HV mode. The max we can get is 2154 * 16G which also happens to be what we configure for PAPR 2155 * mode so make sure we don't do anything bigger than that 2156 */ 2157 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2158 } 2159 2160 if (spapr->rma_size > node0_size) { 2161 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2162 spapr->rma_size); 2163 exit(1); 2164 } 2165 2166 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2167 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2168 2169 /* Set up Interrupt Controller before we create the VCPUs */ 2170 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); 2171 2172 /* Set up containers for ibm,client-set-architecture negotiated options */ 2173 spapr->ov5 = spapr_ovec_new(); 2174 spapr->ov5_cas = spapr_ovec_new(); 2175 2176 if (smc->dr_lmb_enabled) { 2177 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2178 spapr_validate_node_memory(machine, &error_fatal); 2179 } 2180 2181 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2182 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) { 2183 /* KVM and TCG always allow GTSE with radix... */ 2184 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2185 } 2186 /* ... but not with hash (currently). */ 2187 2188 /* advertise support for dedicated HP event source to guests */ 2189 if (spapr->use_hotplug_event_source) { 2190 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2191 } 2192 2193 /* init CPUs */ 2194 if (machine->cpu_model == NULL) { 2195 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; 2196 } 2197 2198 spapr_cpu_parse_features(spapr); 2199 2200 spapr_init_cpus(spapr); 2201 2202 if (kvm_enabled()) { 2203 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2204 kvmppc_enable_logical_ci_hcalls(); 2205 kvmppc_enable_set_mode_hcall(); 2206 2207 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2208 kvmppc_enable_clear_ref_mod_hcalls(); 2209 } 2210 2211 /* allocate RAM */ 2212 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2213 machine->ram_size); 2214 memory_region_add_subregion(sysmem, 0, ram); 2215 2216 if (rma_alloc_size && rma) { 2217 rma_region = g_new(MemoryRegion, 1); 2218 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 2219 rma_alloc_size, rma); 2220 vmstate_register_ram_global(rma_region); 2221 memory_region_add_subregion(sysmem, 0, rma_region); 2222 } 2223 2224 /* initialize hotplug memory address space */ 2225 if (machine->ram_size < machine->maxram_size) { 2226 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2227 /* 2228 * Limit the number of hotpluggable memory slots to half the number 2229 * slots that KVM supports, leaving the other half for PCI and other 2230 * devices. However ensure that number of slots doesn't drop below 32. 2231 */ 2232 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2233 SPAPR_MAX_RAM_SLOTS; 2234 2235 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2236 max_memslots = SPAPR_MAX_RAM_SLOTS; 2237 } 2238 if (machine->ram_slots > max_memslots) { 2239 error_report("Specified number of memory slots %" 2240 PRIu64" exceeds max supported %d", 2241 machine->ram_slots, max_memslots); 2242 exit(1); 2243 } 2244 2245 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2246 SPAPR_HOTPLUG_MEM_ALIGN); 2247 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2248 "hotplug-memory", hotplug_mem_size); 2249 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2250 &spapr->hotplug_memory.mr); 2251 } 2252 2253 if (smc->dr_lmb_enabled) { 2254 spapr_create_lmb_dr_connectors(spapr); 2255 } 2256 2257 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2258 if (!filename) { 2259 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2260 exit(1); 2261 } 2262 spapr->rtas_size = get_image_size(filename); 2263 if (spapr->rtas_size < 0) { 2264 error_report("Could not get size of LPAR rtas '%s'", filename); 2265 exit(1); 2266 } 2267 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2268 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2269 error_report("Could not load LPAR rtas '%s'", filename); 2270 exit(1); 2271 } 2272 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2273 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2274 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2275 exit(1); 2276 } 2277 g_free(filename); 2278 2279 /* Set up RTAS event infrastructure */ 2280 spapr_events_init(spapr); 2281 2282 /* Set up the RTC RTAS interfaces */ 2283 spapr_rtc_create(spapr); 2284 2285 /* Set up VIO bus */ 2286 spapr->vio_bus = spapr_vio_bus_init(); 2287 2288 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 2289 if (serial_hds[i]) { 2290 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 2291 } 2292 } 2293 2294 /* We always have at least the nvram device on VIO */ 2295 spapr_create_nvram(spapr); 2296 2297 /* Set up PCI */ 2298 spapr_pci_rtas_init(); 2299 2300 phb = spapr_create_phb(spapr, 0); 2301 2302 for (i = 0; i < nb_nics; i++) { 2303 NICInfo *nd = &nd_table[i]; 2304 2305 if (!nd->model) { 2306 nd->model = g_strdup("ibmveth"); 2307 } 2308 2309 if (strcmp(nd->model, "ibmveth") == 0) { 2310 spapr_vlan_create(spapr->vio_bus, nd); 2311 } else { 2312 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2313 } 2314 } 2315 2316 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2317 spapr_vscsi_create(spapr->vio_bus); 2318 } 2319 2320 /* Graphics */ 2321 if (spapr_vga_init(phb->bus, &error_fatal)) { 2322 spapr->has_graphics = true; 2323 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2324 } 2325 2326 if (machine->usb) { 2327 if (smc->use_ohci_by_default) { 2328 pci_create_simple(phb->bus, -1, "pci-ohci"); 2329 } else { 2330 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2331 } 2332 2333 if (spapr->has_graphics) { 2334 USBBus *usb_bus = usb_bus_find(-1); 2335 2336 usb_create_simple(usb_bus, "usb-kbd"); 2337 usb_create_simple(usb_bus, "usb-mouse"); 2338 } 2339 } 2340 2341 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2342 error_report( 2343 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2344 MIN_RMA_SLOF); 2345 exit(1); 2346 } 2347 2348 if (kernel_filename) { 2349 uint64_t lowaddr = 0; 2350 2351 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2352 NULL, NULL, &lowaddr, NULL, 1, 2353 PPC_ELF_MACHINE, 0, 0); 2354 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2355 spapr->kernel_size = load_elf(kernel_filename, 2356 translate_kernel_address, NULL, NULL, 2357 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2358 0, 0); 2359 spapr->kernel_le = spapr->kernel_size > 0; 2360 } 2361 if (spapr->kernel_size < 0) { 2362 error_report("error loading %s: %s", kernel_filename, 2363 load_elf_strerror(spapr->kernel_size)); 2364 exit(1); 2365 } 2366 2367 /* load initrd */ 2368 if (initrd_filename) { 2369 /* Try to locate the initrd in the gap between the kernel 2370 * and the firmware. Add a bit of space just in case 2371 */ 2372 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2373 + 0x1ffff) & ~0xffff; 2374 spapr->initrd_size = load_image_targphys(initrd_filename, 2375 spapr->initrd_base, 2376 load_limit 2377 - spapr->initrd_base); 2378 if (spapr->initrd_size < 0) { 2379 error_report("could not load initial ram disk '%s'", 2380 initrd_filename); 2381 exit(1); 2382 } 2383 } 2384 } 2385 2386 if (bios_name == NULL) { 2387 bios_name = FW_FILE_NAME; 2388 } 2389 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2390 if (!filename) { 2391 error_report("Could not find LPAR firmware '%s'", bios_name); 2392 exit(1); 2393 } 2394 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2395 if (fw_size <= 0) { 2396 error_report("Could not load LPAR firmware '%s'", filename); 2397 exit(1); 2398 } 2399 g_free(filename); 2400 2401 /* FIXME: Should register things through the MachineState's qdev 2402 * interface, this is a legacy from the sPAPREnvironment structure 2403 * which predated MachineState but had a similar function */ 2404 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2405 register_savevm_live(NULL, "spapr/htab", -1, 1, 2406 &savevm_htab_handlers, spapr); 2407 2408 qemu_register_boot_set(spapr_boot_set, spapr); 2409 2410 if (kvm_enabled()) { 2411 /* to stop and start vmclock */ 2412 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2413 &spapr->tb); 2414 2415 kvmppc_spapr_enable_inkernel_multitce(); 2416 } 2417 } 2418 2419 static int spapr_kvm_type(const char *vm_type) 2420 { 2421 if (!vm_type) { 2422 return 0; 2423 } 2424 2425 if (!strcmp(vm_type, "HV")) { 2426 return 1; 2427 } 2428 2429 if (!strcmp(vm_type, "PR")) { 2430 return 2; 2431 } 2432 2433 error_report("Unknown kvm-type specified '%s'", vm_type); 2434 exit(1); 2435 } 2436 2437 /* 2438 * Implementation of an interface to adjust firmware path 2439 * for the bootindex property handling. 2440 */ 2441 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2442 DeviceState *dev) 2443 { 2444 #define CAST(type, obj, name) \ 2445 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2446 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2447 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2448 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 2449 2450 if (d) { 2451 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2452 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2453 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2454 2455 if (spapr) { 2456 /* 2457 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2458 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2459 * in the top 16 bits of the 64-bit LUN 2460 */ 2461 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2462 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2463 (uint64_t)id << 48); 2464 } else if (virtio) { 2465 /* 2466 * We use SRP luns of the form 01000000 | (target << 8) | lun 2467 * in the top 32 bits of the 64-bit LUN 2468 * Note: the quote above is from SLOF and it is wrong, 2469 * the actual binding is: 2470 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2471 */ 2472 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2473 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2474 (uint64_t)id << 32); 2475 } else if (usb) { 2476 /* 2477 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2478 * in the top 32 bits of the 64-bit LUN 2479 */ 2480 unsigned usb_port = atoi(usb->port->path); 2481 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2482 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2483 (uint64_t)id << 32); 2484 } 2485 } 2486 2487 /* 2488 * SLOF probes the USB devices, and if it recognizes that the device is a 2489 * storage device, it changes its name to "storage" instead of "usb-host", 2490 * and additionally adds a child node for the SCSI LUN, so the correct 2491 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2492 */ 2493 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2494 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2495 if (usb_host_dev_is_scsi_storage(usbdev)) { 2496 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2497 } 2498 } 2499 2500 if (phb) { 2501 /* Replace "pci" with "pci@800000020000000" */ 2502 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2503 } 2504 2505 if (vsc) { 2506 /* Same logic as virtio above */ 2507 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 2508 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 2509 } 2510 2511 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 2512 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 2513 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 2514 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 2515 } 2516 2517 return NULL; 2518 } 2519 2520 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2521 { 2522 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2523 2524 return g_strdup(spapr->kvm_type); 2525 } 2526 2527 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2528 { 2529 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2530 2531 g_free(spapr->kvm_type); 2532 spapr->kvm_type = g_strdup(value); 2533 } 2534 2535 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2536 { 2537 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2538 2539 return spapr->use_hotplug_event_source; 2540 } 2541 2542 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2543 Error **errp) 2544 { 2545 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2546 2547 spapr->use_hotplug_event_source = value; 2548 } 2549 2550 static void spapr_machine_initfn(Object *obj) 2551 { 2552 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2553 2554 spapr->htab_fd = -1; 2555 spapr->use_hotplug_event_source = true; 2556 object_property_add_str(obj, "kvm-type", 2557 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2558 object_property_set_description(obj, "kvm-type", 2559 "Specifies the KVM virtualization mode (HV, PR)", 2560 NULL); 2561 object_property_add_bool(obj, "modern-hotplug-events", 2562 spapr_get_modern_hotplug_events, 2563 spapr_set_modern_hotplug_events, 2564 NULL); 2565 object_property_set_description(obj, "modern-hotplug-events", 2566 "Use dedicated hotplug event mechanism in" 2567 " place of standard EPOW events when possible" 2568 " (required for memory hot-unplug support)", 2569 NULL); 2570 2571 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 2572 "Maximum permitted CPU compatibility mode", 2573 &error_fatal); 2574 } 2575 2576 static void spapr_machine_finalizefn(Object *obj) 2577 { 2578 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2579 2580 g_free(spapr->kvm_type); 2581 } 2582 2583 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 2584 { 2585 cpu_synchronize_state(cs); 2586 ppc_cpu_do_system_reset(cs); 2587 } 2588 2589 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2590 { 2591 CPUState *cs; 2592 2593 CPU_FOREACH(cs) { 2594 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 2595 } 2596 } 2597 2598 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2599 uint32_t node, bool dedicated_hp_event_source, 2600 Error **errp) 2601 { 2602 sPAPRDRConnector *drc; 2603 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2604 int i, fdt_offset, fdt_size; 2605 void *fdt; 2606 uint64_t addr = addr_start; 2607 Error *local_err = NULL; 2608 2609 for (i = 0; i < nr_lmbs; i++) { 2610 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2611 addr / SPAPR_MEMORY_BLOCK_SIZE); 2612 g_assert(drc); 2613 2614 fdt = create_device_tree(&fdt_size); 2615 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2616 SPAPR_MEMORY_BLOCK_SIZE); 2617 2618 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 2619 if (local_err) { 2620 while (addr > addr_start) { 2621 addr -= SPAPR_MEMORY_BLOCK_SIZE; 2622 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2623 addr / SPAPR_MEMORY_BLOCK_SIZE); 2624 spapr_drc_detach(drc, dev, NULL); 2625 } 2626 g_free(fdt); 2627 error_propagate(errp, local_err); 2628 return; 2629 } 2630 addr += SPAPR_MEMORY_BLOCK_SIZE; 2631 } 2632 /* send hotplug notification to the 2633 * guest only in case of hotplugged memory 2634 */ 2635 if (dev->hotplugged) { 2636 if (dedicated_hp_event_source) { 2637 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2638 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2639 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2640 nr_lmbs, 2641 spapr_drc_index(drc)); 2642 } else { 2643 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 2644 nr_lmbs); 2645 } 2646 } 2647 } 2648 2649 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2650 uint32_t node, Error **errp) 2651 { 2652 Error *local_err = NULL; 2653 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2654 PCDIMMDevice *dimm = PC_DIMM(dev); 2655 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2656 MemoryRegion *mr = ddc->get_memory_region(dimm); 2657 uint64_t align = memory_region_get_alignment(mr); 2658 uint64_t size = memory_region_size(mr); 2659 uint64_t addr; 2660 2661 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2662 if (local_err) { 2663 goto out; 2664 } 2665 2666 addr = object_property_get_uint(OBJECT(dimm), 2667 PC_DIMM_ADDR_PROP, &local_err); 2668 if (local_err) { 2669 goto out_unplug; 2670 } 2671 2672 spapr_add_lmbs(dev, addr, size, node, 2673 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 2674 &local_err); 2675 if (local_err) { 2676 goto out_unplug; 2677 } 2678 2679 return; 2680 2681 out_unplug: 2682 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2683 out: 2684 error_propagate(errp, local_err); 2685 } 2686 2687 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2688 Error **errp) 2689 { 2690 PCDIMMDevice *dimm = PC_DIMM(dev); 2691 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2692 MemoryRegion *mr = ddc->get_memory_region(dimm); 2693 uint64_t size = memory_region_size(mr); 2694 char *mem_dev; 2695 2696 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2697 error_setg(errp, "Hotplugged memory size must be a multiple of " 2698 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2699 return; 2700 } 2701 2702 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 2703 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 2704 error_setg(errp, "Memory backend has bad page size. " 2705 "Use 'memory-backend-file' with correct mem-path."); 2706 goto out; 2707 } 2708 2709 out: 2710 g_free(mem_dev); 2711 } 2712 2713 struct sPAPRDIMMState { 2714 PCDIMMDevice *dimm; 2715 uint32_t nr_lmbs; 2716 QTAILQ_ENTRY(sPAPRDIMMState) next; 2717 }; 2718 2719 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 2720 PCDIMMDevice *dimm) 2721 { 2722 sPAPRDIMMState *dimm_state = NULL; 2723 2724 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 2725 if (dimm_state->dimm == dimm) { 2726 break; 2727 } 2728 } 2729 return dimm_state; 2730 } 2731 2732 static void spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 2733 sPAPRDIMMState *dimm_state) 2734 { 2735 g_assert(!spapr_pending_dimm_unplugs_find(spapr, dimm_state->dimm)); 2736 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, dimm_state, next); 2737 } 2738 2739 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 2740 sPAPRDIMMState *dimm_state) 2741 { 2742 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 2743 g_free(dimm_state); 2744 } 2745 2746 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 2747 PCDIMMDevice *dimm) 2748 { 2749 sPAPRDRConnector *drc; 2750 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2751 MemoryRegion *mr = ddc->get_memory_region(dimm); 2752 uint64_t size = memory_region_size(mr); 2753 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2754 uint32_t avail_lmbs = 0; 2755 uint64_t addr_start, addr; 2756 int i; 2757 sPAPRDIMMState *ds; 2758 2759 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 2760 &error_abort); 2761 2762 addr = addr_start; 2763 for (i = 0; i < nr_lmbs; i++) { 2764 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2765 addr / SPAPR_MEMORY_BLOCK_SIZE); 2766 g_assert(drc); 2767 if (drc->dev) { 2768 avail_lmbs++; 2769 } 2770 addr += SPAPR_MEMORY_BLOCK_SIZE; 2771 } 2772 2773 ds = g_malloc0(sizeof(sPAPRDIMMState)); 2774 ds->nr_lmbs = avail_lmbs; 2775 ds->dimm = dimm; 2776 spapr_pending_dimm_unplugs_add(ms, ds); 2777 return ds; 2778 } 2779 2780 /* Callback to be called during DRC release. */ 2781 void spapr_lmb_release(DeviceState *dev) 2782 { 2783 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 2784 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 2785 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 2786 2787 /* This information will get lost if a migration occurs 2788 * during the unplug process. In this case recover it. */ 2789 if (ds == NULL) { 2790 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 2791 /* The DRC being examined by the caller at least must be counted */ 2792 g_assert(ds->nr_lmbs); 2793 } 2794 2795 if (--ds->nr_lmbs) { 2796 return; 2797 } 2798 2799 spapr_pending_dimm_unplugs_remove(spapr, ds); 2800 2801 /* 2802 * Now that all the LMBs have been removed by the guest, call the 2803 * pc-dimm unplug handler to cleanup up the pc-dimm device. 2804 */ 2805 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2806 } 2807 2808 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2809 Error **errp) 2810 { 2811 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2812 PCDIMMDevice *dimm = PC_DIMM(dev); 2813 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2814 MemoryRegion *mr = ddc->get_memory_region(dimm); 2815 2816 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2817 object_unparent(OBJECT(dev)); 2818 } 2819 2820 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 2821 DeviceState *dev, Error **errp) 2822 { 2823 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 2824 Error *local_err = NULL; 2825 PCDIMMDevice *dimm = PC_DIMM(dev); 2826 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2827 MemoryRegion *mr = ddc->get_memory_region(dimm); 2828 uint64_t size = memory_region_size(mr); 2829 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2830 uint64_t addr_start, addr; 2831 int i; 2832 sPAPRDRConnector *drc; 2833 sPAPRDIMMState *ds; 2834 2835 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 2836 &local_err); 2837 if (local_err) { 2838 goto out; 2839 } 2840 2841 ds = g_malloc0(sizeof(sPAPRDIMMState)); 2842 ds->nr_lmbs = nr_lmbs; 2843 ds->dimm = dimm; 2844 spapr_pending_dimm_unplugs_add(spapr, ds); 2845 2846 addr = addr_start; 2847 for (i = 0; i < nr_lmbs; i++) { 2848 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2849 addr / SPAPR_MEMORY_BLOCK_SIZE); 2850 g_assert(drc); 2851 2852 spapr_drc_detach(drc, dev, errp); 2853 addr += SPAPR_MEMORY_BLOCK_SIZE; 2854 } 2855 2856 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2857 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2858 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2859 nr_lmbs, spapr_drc_index(drc)); 2860 out: 2861 error_propagate(errp, local_err); 2862 } 2863 2864 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 2865 sPAPRMachineState *spapr) 2866 { 2867 PowerPCCPU *cpu = POWERPC_CPU(cs); 2868 DeviceClass *dc = DEVICE_GET_CLASS(cs); 2869 int id = ppc_get_vcpu_dt_id(cpu); 2870 void *fdt; 2871 int offset, fdt_size; 2872 char *nodename; 2873 2874 fdt = create_device_tree(&fdt_size); 2875 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 2876 offset = fdt_add_subnode(fdt, 0, nodename); 2877 2878 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 2879 g_free(nodename); 2880 2881 *fdt_offset = offset; 2882 return fdt; 2883 } 2884 2885 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2886 Error **errp) 2887 { 2888 MachineState *ms = MACHINE(qdev_get_machine()); 2889 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 2890 CPUCore *cc = CPU_CORE(dev); 2891 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 2892 2893 if (smc->pre_2_10_has_unused_icps) { 2894 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 2895 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc)); 2896 const char *typename = object_class_get_name(scc->cpu_class); 2897 size_t size = object_type_get_instance_size(typename); 2898 int i; 2899 2900 for (i = 0; i < cc->nr_threads; i++) { 2901 CPUState *cs = CPU(sc->threads + i * size); 2902 2903 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 2904 } 2905 } 2906 2907 assert(core_slot); 2908 core_slot->cpu = NULL; 2909 object_unparent(OBJECT(dev)); 2910 } 2911 2912 /* Callback to be called during DRC release. */ 2913 void spapr_core_release(DeviceState *dev) 2914 { 2915 HotplugHandler *hotplug_ctrl; 2916 2917 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2918 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2919 } 2920 2921 static 2922 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 2923 Error **errp) 2924 { 2925 int index; 2926 sPAPRDRConnector *drc; 2927 Error *local_err = NULL; 2928 CPUCore *cc = CPU_CORE(dev); 2929 int smt = kvmppc_smt_threads(); 2930 2931 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 2932 error_setg(errp, "Unable to find CPU core with core-id: %d", 2933 cc->core_id); 2934 return; 2935 } 2936 if (index == 0) { 2937 error_setg(errp, "Boot CPU core may not be unplugged"); 2938 return; 2939 } 2940 2941 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); 2942 g_assert(drc); 2943 2944 spapr_drc_detach(drc, dev, &local_err); 2945 if (local_err) { 2946 error_propagate(errp, local_err); 2947 return; 2948 } 2949 2950 spapr_hotplug_req_remove_by_index(drc); 2951 } 2952 2953 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2954 Error **errp) 2955 { 2956 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 2957 MachineClass *mc = MACHINE_GET_CLASS(spapr); 2958 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 2959 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 2960 CPUCore *cc = CPU_CORE(dev); 2961 CPUState *cs = CPU(core->threads); 2962 sPAPRDRConnector *drc; 2963 Error *local_err = NULL; 2964 void *fdt = NULL; 2965 int fdt_offset = 0; 2966 int smt = kvmppc_smt_threads(); 2967 CPUArchId *core_slot; 2968 int index; 2969 2970 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2971 if (!core_slot) { 2972 error_setg(errp, "Unable to find CPU core with core-id: %d", 2973 cc->core_id); 2974 return; 2975 } 2976 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); 2977 2978 g_assert(drc || !mc->has_hotpluggable_cpus); 2979 2980 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 2981 2982 if (drc) { 2983 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 2984 if (local_err) { 2985 g_free(fdt); 2986 error_propagate(errp, local_err); 2987 return; 2988 } 2989 } 2990 2991 if (dev->hotplugged) { 2992 /* 2993 * Send hotplug notification interrupt to the guest only in case 2994 * of hotplugged CPUs. 2995 */ 2996 spapr_hotplug_req_add_by_index(drc); 2997 } 2998 core_slot->cpu = OBJECT(dev); 2999 3000 if (smc->pre_2_10_has_unused_icps) { 3001 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc)); 3002 const char *typename = object_class_get_name(scc->cpu_class); 3003 size_t size = object_type_get_instance_size(typename); 3004 int i; 3005 3006 for (i = 0; i < cc->nr_threads; i++) { 3007 sPAPRCPUCore *sc = SPAPR_CPU_CORE(dev); 3008 void *obj = sc->threads + i * size; 3009 3010 cs = CPU(obj); 3011 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3012 } 3013 } 3014 } 3015 3016 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3017 Error **errp) 3018 { 3019 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3020 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3021 Error *local_err = NULL; 3022 CPUCore *cc = CPU_CORE(dev); 3023 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model); 3024 const char *type = object_get_typename(OBJECT(dev)); 3025 CPUArchId *core_slot; 3026 int index; 3027 3028 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3029 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3030 goto out; 3031 } 3032 3033 if (strcmp(base_core_type, type)) { 3034 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3035 goto out; 3036 } 3037 3038 if (cc->core_id % smp_threads) { 3039 error_setg(&local_err, "invalid core id %d", cc->core_id); 3040 goto out; 3041 } 3042 3043 /* 3044 * In general we should have homogeneous threads-per-core, but old 3045 * (pre hotplug support) machine types allow the last core to have 3046 * reduced threads as a compatibility hack for when we allowed 3047 * total vcpus not a multiple of threads-per-core. 3048 */ 3049 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3050 error_setg(errp, "invalid nr-threads %d, must be %d", 3051 cc->nr_threads, smp_threads); 3052 return; 3053 } 3054 3055 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3056 if (!core_slot) { 3057 error_setg(&local_err, "core id %d out of range", cc->core_id); 3058 goto out; 3059 } 3060 3061 if (core_slot->cpu) { 3062 error_setg(&local_err, "core %d already populated", cc->core_id); 3063 goto out; 3064 } 3065 3066 numa_cpu_pre_plug(core_slot, dev, &local_err); 3067 3068 out: 3069 g_free(base_core_type); 3070 error_propagate(errp, local_err); 3071 } 3072 3073 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3074 DeviceState *dev, Error **errp) 3075 { 3076 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 3077 3078 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3079 int node; 3080 3081 if (!smc->dr_lmb_enabled) { 3082 error_setg(errp, "Memory hotplug not supported for this machine"); 3083 return; 3084 } 3085 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 3086 if (*errp) { 3087 return; 3088 } 3089 if (node < 0 || node >= MAX_NODES) { 3090 error_setg(errp, "Invaild node %d", node); 3091 return; 3092 } 3093 3094 /* 3095 * Currently PowerPC kernel doesn't allow hot-adding memory to 3096 * memory-less node, but instead will silently add the memory 3097 * to the first node that has some memory. This causes two 3098 * unexpected behaviours for the user. 3099 * 3100 * - Memory gets hotplugged to a different node than what the user 3101 * specified. 3102 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 3103 * to memory-less node, a reboot will set things accordingly 3104 * and the previously hotplugged memory now ends in the right node. 3105 * This appears as if some memory moved from one node to another. 3106 * 3107 * So until kernel starts supporting memory hotplug to memory-less 3108 * nodes, just prevent such attempts upfront in QEMU. 3109 */ 3110 if (nb_numa_nodes && !numa_info[node].node_mem) { 3111 error_setg(errp, "Can't hotplug memory to memory-less node %d", 3112 node); 3113 return; 3114 } 3115 3116 spapr_memory_plug(hotplug_dev, dev, node, errp); 3117 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3118 spapr_core_plug(hotplug_dev, dev, errp); 3119 } 3120 } 3121 3122 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 3123 DeviceState *dev, Error **errp) 3124 { 3125 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 3126 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 3127 3128 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3129 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3130 spapr_memory_unplug(hotplug_dev, dev, errp); 3131 } else { 3132 error_setg(errp, "Memory hot unplug not supported for this guest"); 3133 } 3134 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3135 if (!mc->has_hotpluggable_cpus) { 3136 error_setg(errp, "CPU hot unplug not supported on this machine"); 3137 return; 3138 } 3139 spapr_core_unplug(hotplug_dev, dev, errp); 3140 } 3141 } 3142 3143 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3144 DeviceState *dev, Error **errp) 3145 { 3146 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 3147 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 3148 3149 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3150 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3151 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3152 } else { 3153 /* NOTE: this means there is a window after guest reset, prior to 3154 * CAS negotiation, where unplug requests will fail due to the 3155 * capability not being detected yet. This is a bit different than 3156 * the case with PCI unplug, where the events will be queued and 3157 * eventually handled by the guest after boot 3158 */ 3159 error_setg(errp, "Memory hot unplug not supported for this guest"); 3160 } 3161 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3162 if (!mc->has_hotpluggable_cpus) { 3163 error_setg(errp, "CPU hot unplug not supported on this machine"); 3164 return; 3165 } 3166 spapr_core_unplug_request(hotplug_dev, dev, errp); 3167 } 3168 } 3169 3170 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3171 DeviceState *dev, Error **errp) 3172 { 3173 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3174 spapr_memory_pre_plug(hotplug_dev, dev, errp); 3175 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3176 spapr_core_pre_plug(hotplug_dev, dev, errp); 3177 } 3178 } 3179 3180 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3181 DeviceState *dev) 3182 { 3183 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3184 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3185 return HOTPLUG_HANDLER(machine); 3186 } 3187 return NULL; 3188 } 3189 3190 static CpuInstanceProperties 3191 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3192 { 3193 CPUArchId *core_slot; 3194 MachineClass *mc = MACHINE_GET_CLASS(machine); 3195 3196 /* make sure possible_cpu are intialized */ 3197 mc->possible_cpu_arch_ids(machine); 3198 /* get CPU core slot containing thread that matches cpu_index */ 3199 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3200 assert(core_slot); 3201 return core_slot->props; 3202 } 3203 3204 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3205 { 3206 int i; 3207 int spapr_max_cores = max_cpus / smp_threads; 3208 MachineClass *mc = MACHINE_GET_CLASS(machine); 3209 3210 if (!mc->has_hotpluggable_cpus) { 3211 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3212 } 3213 if (machine->possible_cpus) { 3214 assert(machine->possible_cpus->len == spapr_max_cores); 3215 return machine->possible_cpus; 3216 } 3217 3218 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3219 sizeof(CPUArchId) * spapr_max_cores); 3220 machine->possible_cpus->len = spapr_max_cores; 3221 for (i = 0; i < machine->possible_cpus->len; i++) { 3222 int core_id = i * smp_threads; 3223 3224 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3225 machine->possible_cpus->cpus[i].arch_id = core_id; 3226 machine->possible_cpus->cpus[i].props.has_core_id = true; 3227 machine->possible_cpus->cpus[i].props.core_id = core_id; 3228 3229 /* default distribution of CPUs over NUMA nodes */ 3230 if (nb_numa_nodes) { 3231 /* preset values but do not enable them i.e. 'has_node_id = false', 3232 * numa init code will enable them later if manual mapping wasn't 3233 * present on CLI */ 3234 machine->possible_cpus->cpus[i].props.node_id = 3235 core_id / smp_threads / smp_cores % nb_numa_nodes; 3236 } 3237 } 3238 return machine->possible_cpus; 3239 } 3240 3241 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3242 uint64_t *buid, hwaddr *pio, 3243 hwaddr *mmio32, hwaddr *mmio64, 3244 unsigned n_dma, uint32_t *liobns, Error **errp) 3245 { 3246 /* 3247 * New-style PHB window placement. 3248 * 3249 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3250 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3251 * windows. 3252 * 3253 * Some guest kernels can't work with MMIO windows above 1<<46 3254 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3255 * 3256 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3257 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3258 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3259 * 1TiB 64-bit MMIO windows for each PHB. 3260 */ 3261 const uint64_t base_buid = 0x800000020000000ULL; 3262 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3263 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3264 int i; 3265 3266 /* Sanity check natural alignments */ 3267 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3268 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3269 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3270 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3271 /* Sanity check bounds */ 3272 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3273 SPAPR_PCI_MEM32_WIN_SIZE); 3274 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3275 SPAPR_PCI_MEM64_WIN_SIZE); 3276 3277 if (index >= SPAPR_MAX_PHBS) { 3278 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3279 SPAPR_MAX_PHBS - 1); 3280 return; 3281 } 3282 3283 *buid = base_buid + index; 3284 for (i = 0; i < n_dma; ++i) { 3285 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3286 } 3287 3288 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3289 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3290 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3291 } 3292 3293 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3294 { 3295 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3296 3297 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3298 } 3299 3300 static void spapr_ics_resend(XICSFabric *dev) 3301 { 3302 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3303 3304 ics_resend(spapr->ics); 3305 } 3306 3307 static ICPState *spapr_icp_get(XICSFabric *xi, int cpu_dt_id) 3308 { 3309 PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id); 3310 3311 return cpu ? ICP(cpu->intc) : NULL; 3312 } 3313 3314 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3315 Monitor *mon) 3316 { 3317 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3318 CPUState *cs; 3319 3320 CPU_FOREACH(cs) { 3321 PowerPCCPU *cpu = POWERPC_CPU(cs); 3322 3323 icp_pic_print_info(ICP(cpu->intc), mon); 3324 } 3325 3326 ics_pic_print_info(spapr->ics, mon); 3327 } 3328 3329 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3330 { 3331 MachineClass *mc = MACHINE_CLASS(oc); 3332 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3333 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3334 NMIClass *nc = NMI_CLASS(oc); 3335 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3336 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3337 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3338 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3339 3340 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3341 3342 /* 3343 * We set up the default / latest behaviour here. The class_init 3344 * functions for the specific versioned machine types can override 3345 * these details for backwards compatibility 3346 */ 3347 mc->init = ppc_spapr_init; 3348 mc->reset = ppc_spapr_reset; 3349 mc->block_default_type = IF_SCSI; 3350 mc->max_cpus = 1024; 3351 mc->no_parallel = 1; 3352 mc->default_boot_order = ""; 3353 mc->default_ram_size = 512 * M_BYTE; 3354 mc->kvm_type = spapr_kvm_type; 3355 mc->has_dynamic_sysbus = true; 3356 mc->pci_allow_0_address = true; 3357 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3358 hc->pre_plug = spapr_machine_device_pre_plug; 3359 hc->plug = spapr_machine_device_plug; 3360 hc->unplug = spapr_machine_device_unplug; 3361 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 3362 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3363 hc->unplug_request = spapr_machine_device_unplug_request; 3364 3365 smc->dr_lmb_enabled = true; 3366 smc->tcg_default_cpu = "POWER8"; 3367 mc->has_hotpluggable_cpus = true; 3368 fwc->get_dev_path = spapr_get_fw_dev_path; 3369 nc->nmi_monitor_handler = spapr_nmi; 3370 smc->phb_placement = spapr_phb_placement; 3371 vhc->hypercall = emulate_spapr_hypercall; 3372 vhc->hpt_mask = spapr_hpt_mask; 3373 vhc->map_hptes = spapr_map_hptes; 3374 vhc->unmap_hptes = spapr_unmap_hptes; 3375 vhc->store_hpte = spapr_store_hpte; 3376 vhc->get_patbe = spapr_get_patbe; 3377 xic->ics_get = spapr_ics_get; 3378 xic->ics_resend = spapr_ics_resend; 3379 xic->icp_get = spapr_icp_get; 3380 ispc->print_info = spapr_pic_print_info; 3381 /* Force NUMA node memory size to be a multiple of 3382 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 3383 * in which LMBs are represented and hot-added 3384 */ 3385 mc->numa_mem_align_shift = 28; 3386 } 3387 3388 static const TypeInfo spapr_machine_info = { 3389 .name = TYPE_SPAPR_MACHINE, 3390 .parent = TYPE_MACHINE, 3391 .abstract = true, 3392 .instance_size = sizeof(sPAPRMachineState), 3393 .instance_init = spapr_machine_initfn, 3394 .instance_finalize = spapr_machine_finalizefn, 3395 .class_size = sizeof(sPAPRMachineClass), 3396 .class_init = spapr_machine_class_init, 3397 .interfaces = (InterfaceInfo[]) { 3398 { TYPE_FW_PATH_PROVIDER }, 3399 { TYPE_NMI }, 3400 { TYPE_HOTPLUG_HANDLER }, 3401 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3402 { TYPE_XICS_FABRIC }, 3403 { TYPE_INTERRUPT_STATS_PROVIDER }, 3404 { } 3405 }, 3406 }; 3407 3408 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3409 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3410 void *data) \ 3411 { \ 3412 MachineClass *mc = MACHINE_CLASS(oc); \ 3413 spapr_machine_##suffix##_class_options(mc); \ 3414 if (latest) { \ 3415 mc->alias = "pseries"; \ 3416 mc->is_default = 1; \ 3417 } \ 3418 } \ 3419 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3420 { \ 3421 MachineState *machine = MACHINE(obj); \ 3422 spapr_machine_##suffix##_instance_options(machine); \ 3423 } \ 3424 static const TypeInfo spapr_machine_##suffix##_info = { \ 3425 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3426 .parent = TYPE_SPAPR_MACHINE, \ 3427 .class_init = spapr_machine_##suffix##_class_init, \ 3428 .instance_init = spapr_machine_##suffix##_instance_init, \ 3429 }; \ 3430 static void spapr_machine_register_##suffix(void) \ 3431 { \ 3432 type_register(&spapr_machine_##suffix##_info); \ 3433 } \ 3434 type_init(spapr_machine_register_##suffix) 3435 3436 /* 3437 * pseries-2.10 3438 */ 3439 static void spapr_machine_2_10_instance_options(MachineState *machine) 3440 { 3441 } 3442 3443 static void spapr_machine_2_10_class_options(MachineClass *mc) 3444 { 3445 /* Defaults for the latest behaviour inherited from the base class */ 3446 } 3447 3448 DEFINE_SPAPR_MACHINE(2_10, "2.10", true); 3449 3450 /* 3451 * pseries-2.9 3452 */ 3453 #define SPAPR_COMPAT_2_9 \ 3454 HW_COMPAT_2_9 \ 3455 { \ 3456 .driver = TYPE_POWERPC_CPU, \ 3457 .property = "pre-2.10-migration", \ 3458 .value = "on", \ 3459 }, \ 3460 3461 static void spapr_machine_2_9_instance_options(MachineState *machine) 3462 { 3463 spapr_machine_2_10_instance_options(machine); 3464 } 3465 3466 static void spapr_machine_2_9_class_options(MachineClass *mc) 3467 { 3468 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3469 3470 spapr_machine_2_10_class_options(mc); 3471 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); 3472 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 3473 smc->pre_2_10_has_unused_icps = true; 3474 } 3475 3476 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 3477 3478 /* 3479 * pseries-2.8 3480 */ 3481 #define SPAPR_COMPAT_2_8 \ 3482 HW_COMPAT_2_8 \ 3483 { \ 3484 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3485 .property = "pcie-extended-configuration-space", \ 3486 .value = "off", \ 3487 }, 3488 3489 static void spapr_machine_2_8_instance_options(MachineState *machine) 3490 { 3491 spapr_machine_2_9_instance_options(machine); 3492 } 3493 3494 static void spapr_machine_2_8_class_options(MachineClass *mc) 3495 { 3496 spapr_machine_2_9_class_options(mc); 3497 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 3498 mc->numa_mem_align_shift = 23; 3499 } 3500 3501 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 3502 3503 /* 3504 * pseries-2.7 3505 */ 3506 #define SPAPR_COMPAT_2_7 \ 3507 HW_COMPAT_2_7 \ 3508 { \ 3509 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3510 .property = "mem_win_size", \ 3511 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 3512 }, \ 3513 { \ 3514 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3515 .property = "mem64_win_size", \ 3516 .value = "0", \ 3517 }, \ 3518 { \ 3519 .driver = TYPE_POWERPC_CPU, \ 3520 .property = "pre-2.8-migration", \ 3521 .value = "on", \ 3522 }, \ 3523 { \ 3524 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3525 .property = "pre-2.8-migration", \ 3526 .value = "on", \ 3527 }, 3528 3529 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 3530 uint64_t *buid, hwaddr *pio, 3531 hwaddr *mmio32, hwaddr *mmio64, 3532 unsigned n_dma, uint32_t *liobns, Error **errp) 3533 { 3534 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 3535 const uint64_t base_buid = 0x800000020000000ULL; 3536 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 3537 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 3538 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 3539 const uint32_t max_index = 255; 3540 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 3541 3542 uint64_t ram_top = MACHINE(spapr)->ram_size; 3543 hwaddr phb0_base, phb_base; 3544 int i; 3545 3546 /* Do we have hotpluggable memory? */ 3547 if (MACHINE(spapr)->maxram_size > ram_top) { 3548 /* Can't just use maxram_size, because there may be an 3549 * alignment gap between normal and hotpluggable memory 3550 * regions */ 3551 ram_top = spapr->hotplug_memory.base + 3552 memory_region_size(&spapr->hotplug_memory.mr); 3553 } 3554 3555 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 3556 3557 if (index > max_index) { 3558 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 3559 max_index); 3560 return; 3561 } 3562 3563 *buid = base_buid + index; 3564 for (i = 0; i < n_dma; ++i) { 3565 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3566 } 3567 3568 phb_base = phb0_base + index * phb_spacing; 3569 *pio = phb_base + pio_offset; 3570 *mmio32 = phb_base + mmio_offset; 3571 /* 3572 * We don't set the 64-bit MMIO window, relying on the PHB's 3573 * fallback behaviour of automatically splitting a large "32-bit" 3574 * window into contiguous 32-bit and 64-bit windows 3575 */ 3576 } 3577 3578 static void spapr_machine_2_7_instance_options(MachineState *machine) 3579 { 3580 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 3581 3582 spapr_machine_2_8_instance_options(machine); 3583 spapr->use_hotplug_event_source = false; 3584 } 3585 3586 static void spapr_machine_2_7_class_options(MachineClass *mc) 3587 { 3588 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3589 3590 spapr_machine_2_8_class_options(mc); 3591 smc->tcg_default_cpu = "POWER7"; 3592 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 3593 smc->phb_placement = phb_placement_2_7; 3594 } 3595 3596 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 3597 3598 /* 3599 * pseries-2.6 3600 */ 3601 #define SPAPR_COMPAT_2_6 \ 3602 HW_COMPAT_2_6 \ 3603 { \ 3604 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3605 .property = "ddw",\ 3606 .value = stringify(off),\ 3607 }, 3608 3609 static void spapr_machine_2_6_instance_options(MachineState *machine) 3610 { 3611 spapr_machine_2_7_instance_options(machine); 3612 } 3613 3614 static void spapr_machine_2_6_class_options(MachineClass *mc) 3615 { 3616 spapr_machine_2_7_class_options(mc); 3617 mc->has_hotpluggable_cpus = false; 3618 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 3619 } 3620 3621 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 3622 3623 /* 3624 * pseries-2.5 3625 */ 3626 #define SPAPR_COMPAT_2_5 \ 3627 HW_COMPAT_2_5 \ 3628 { \ 3629 .driver = "spapr-vlan", \ 3630 .property = "use-rx-buffer-pools", \ 3631 .value = "off", \ 3632 }, 3633 3634 static void spapr_machine_2_5_instance_options(MachineState *machine) 3635 { 3636 spapr_machine_2_6_instance_options(machine); 3637 } 3638 3639 static void spapr_machine_2_5_class_options(MachineClass *mc) 3640 { 3641 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3642 3643 spapr_machine_2_6_class_options(mc); 3644 smc->use_ohci_by_default = true; 3645 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 3646 } 3647 3648 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 3649 3650 /* 3651 * pseries-2.4 3652 */ 3653 #define SPAPR_COMPAT_2_4 \ 3654 HW_COMPAT_2_4 3655 3656 static void spapr_machine_2_4_instance_options(MachineState *machine) 3657 { 3658 spapr_machine_2_5_instance_options(machine); 3659 } 3660 3661 static void spapr_machine_2_4_class_options(MachineClass *mc) 3662 { 3663 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3664 3665 spapr_machine_2_5_class_options(mc); 3666 smc->dr_lmb_enabled = false; 3667 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 3668 } 3669 3670 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 3671 3672 /* 3673 * pseries-2.3 3674 */ 3675 #define SPAPR_COMPAT_2_3 \ 3676 HW_COMPAT_2_3 \ 3677 {\ 3678 .driver = "spapr-pci-host-bridge",\ 3679 .property = "dynamic-reconfiguration",\ 3680 .value = "off",\ 3681 }, 3682 3683 static void spapr_machine_2_3_instance_options(MachineState *machine) 3684 { 3685 spapr_machine_2_4_instance_options(machine); 3686 } 3687 3688 static void spapr_machine_2_3_class_options(MachineClass *mc) 3689 { 3690 spapr_machine_2_4_class_options(mc); 3691 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 3692 } 3693 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 3694 3695 /* 3696 * pseries-2.2 3697 */ 3698 3699 #define SPAPR_COMPAT_2_2 \ 3700 HW_COMPAT_2_2 \ 3701 {\ 3702 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3703 .property = "mem_win_size",\ 3704 .value = "0x20000000",\ 3705 }, 3706 3707 static void spapr_machine_2_2_instance_options(MachineState *machine) 3708 { 3709 spapr_machine_2_3_instance_options(machine); 3710 machine->suppress_vmdesc = true; 3711 } 3712 3713 static void spapr_machine_2_2_class_options(MachineClass *mc) 3714 { 3715 spapr_machine_2_3_class_options(mc); 3716 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 3717 } 3718 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 3719 3720 /* 3721 * pseries-2.1 3722 */ 3723 #define SPAPR_COMPAT_2_1 \ 3724 HW_COMPAT_2_1 3725 3726 static void spapr_machine_2_1_instance_options(MachineState *machine) 3727 { 3728 spapr_machine_2_2_instance_options(machine); 3729 } 3730 3731 static void spapr_machine_2_1_class_options(MachineClass *mc) 3732 { 3733 spapr_machine_2_2_class_options(mc); 3734 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 3735 } 3736 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 3737 3738 static void spapr_machine_register_types(void) 3739 { 3740 type_register_static(&spapr_machine_info); 3741 } 3742 3743 type_init(spapr_machine_register_types) 3744