1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "sysemu/sysemu.h" 28 #include "hw/hw.h" 29 #include "hw/fw-path-provider.h" 30 #include "elf.h" 31 #include "net/net.h" 32 #include "sysemu/blockdev.h" 33 #include "sysemu/cpus.h" 34 #include "sysemu/kvm.h" 35 #include "kvm_ppc.h" 36 #include "mmu-hash64.h" 37 #include "qom/cpu.h" 38 39 #include "hw/boards.h" 40 #include "hw/ppc/ppc.h" 41 #include "hw/loader.h" 42 43 #include "hw/ppc/spapr.h" 44 #include "hw/ppc/spapr_vio.h" 45 #include "hw/pci-host/spapr.h" 46 #include "hw/ppc/xics.h" 47 #include "hw/pci/msi.h" 48 49 #include "hw/pci/pci.h" 50 #include "hw/scsi/scsi.h" 51 #include "hw/virtio/virtio-scsi.h" 52 53 #include "exec/address-spaces.h" 54 #include "hw/usb.h" 55 #include "qemu/config-file.h" 56 #include "qemu/error-report.h" 57 #include "trace.h" 58 #include "hw/nmi.h" 59 60 #include <libfdt.h> 61 62 /* SLOF memory layout: 63 * 64 * SLOF raw image loaded at 0, copies its romfs right below the flat 65 * device-tree, then position SLOF itself 31M below that 66 * 67 * So we set FW_OVERHEAD to 40MB which should account for all of that 68 * and more 69 * 70 * We load our kernel at 4M, leaving space for SLOF initial image 71 */ 72 #define FDT_MAX_SIZE 0x40000 73 #define RTAS_MAX_SIZE 0x10000 74 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 75 #define FW_MAX_SIZE 0x400000 76 #define FW_FILE_NAME "slof.bin" 77 #define FW_OVERHEAD 0x2800000 78 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 79 80 #define MIN_RMA_SLOF 128UL 81 82 #define TIMEBASE_FREQ 512000000ULL 83 84 #define MAX_CPUS 255 85 86 #define PHANDLE_XICP 0x00001111 87 88 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 89 90 typedef struct sPAPRMachineState sPAPRMachineState; 91 92 #define TYPE_SPAPR_MACHINE "spapr-machine" 93 #define SPAPR_MACHINE(obj) \ 94 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 95 96 /** 97 * sPAPRMachineState: 98 */ 99 struct sPAPRMachineState { 100 /*< private >*/ 101 MachineState parent_obj; 102 103 /*< public >*/ 104 char *kvm_type; 105 }; 106 107 sPAPREnvironment *spapr; 108 109 static XICSState *try_create_xics(const char *type, int nr_servers, 110 int nr_irqs) 111 { 112 DeviceState *dev; 113 114 dev = qdev_create(NULL, type); 115 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 116 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 117 if (qdev_init(dev) < 0) { 118 return NULL; 119 } 120 121 return XICS_COMMON(dev); 122 } 123 124 static XICSState *xics_system_init(int nr_servers, int nr_irqs) 125 { 126 XICSState *icp = NULL; 127 128 if (kvm_enabled()) { 129 QemuOpts *machine_opts = qemu_get_machine_opts(); 130 bool irqchip_allowed = qemu_opt_get_bool(machine_opts, 131 "kernel_irqchip", true); 132 bool irqchip_required = qemu_opt_get_bool(machine_opts, 133 "kernel_irqchip", false); 134 if (irqchip_allowed) { 135 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs); 136 } 137 138 if (irqchip_required && !icp) { 139 perror("Failed to create in-kernel XICS\n"); 140 abort(); 141 } 142 } 143 144 if (!icp) { 145 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs); 146 } 147 148 if (!icp) { 149 perror("Failed to create XICS\n"); 150 abort(); 151 } 152 153 return icp; 154 } 155 156 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 157 int smt_threads) 158 { 159 int i, ret = 0; 160 uint32_t servers_prop[smt_threads]; 161 uint32_t gservers_prop[smt_threads * 2]; 162 int index = ppc_get_vcpu_dt_id(cpu); 163 164 if (cpu->cpu_version) { 165 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); 166 if (ret < 0) { 167 return ret; 168 } 169 } 170 171 /* Build interrupt servers and gservers properties */ 172 for (i = 0; i < smt_threads; i++) { 173 servers_prop[i] = cpu_to_be32(index + i); 174 /* Hack, direct the group queues back to cpu 0 */ 175 gservers_prop[i*2] = cpu_to_be32(index + i); 176 gservers_prop[i*2 + 1] = 0; 177 } 178 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 179 servers_prop, sizeof(servers_prop)); 180 if (ret < 0) { 181 return ret; 182 } 183 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 184 gservers_prop, sizeof(gservers_prop)); 185 186 return ret; 187 } 188 189 static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) 190 { 191 int ret = 0, offset, cpus_offset; 192 CPUState *cs; 193 char cpu_model[32]; 194 int smt = kvmppc_smt_threads(); 195 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 196 197 CPU_FOREACH(cs) { 198 PowerPCCPU *cpu = POWERPC_CPU(cs); 199 DeviceClass *dc = DEVICE_GET_CLASS(cs); 200 int index = ppc_get_vcpu_dt_id(cpu); 201 uint32_t associativity[] = {cpu_to_be32(0x5), 202 cpu_to_be32(0x0), 203 cpu_to_be32(0x0), 204 cpu_to_be32(0x0), 205 cpu_to_be32(cs->numa_node), 206 cpu_to_be32(index)}; 207 208 if ((index % smt) != 0) { 209 continue; 210 } 211 212 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 213 214 cpus_offset = fdt_path_offset(fdt, "/cpus"); 215 if (cpus_offset < 0) { 216 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 217 "cpus"); 218 if (cpus_offset < 0) { 219 return cpus_offset; 220 } 221 } 222 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 223 if (offset < 0) { 224 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 225 if (offset < 0) { 226 return offset; 227 } 228 } 229 230 if (nb_numa_nodes > 1) { 231 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 232 sizeof(associativity)); 233 if (ret < 0) { 234 return ret; 235 } 236 } 237 238 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 239 pft_size_prop, sizeof(pft_size_prop)); 240 if (ret < 0) { 241 return ret; 242 } 243 244 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 245 ppc_get_compat_smt_threads(cpu)); 246 if (ret < 0) { 247 return ret; 248 } 249 } 250 return ret; 251 } 252 253 254 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 255 size_t maxsize) 256 { 257 size_t maxcells = maxsize / sizeof(uint32_t); 258 int i, j, count; 259 uint32_t *p = prop; 260 261 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 262 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 263 264 if (!sps->page_shift) { 265 break; 266 } 267 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 268 if (sps->enc[count].page_shift == 0) { 269 break; 270 } 271 } 272 if ((p - prop) >= (maxcells - 3 - count * 2)) { 273 break; 274 } 275 *(p++) = cpu_to_be32(sps->page_shift); 276 *(p++) = cpu_to_be32(sps->slb_enc); 277 *(p++) = cpu_to_be32(count); 278 for (j = 0; j < count; j++) { 279 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 280 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 281 } 282 } 283 284 return (p - prop) * sizeof(uint32_t); 285 } 286 287 static hwaddr spapr_node0_size(void) 288 { 289 if (nb_numa_nodes) { 290 int i; 291 for (i = 0; i < nb_numa_nodes; ++i) { 292 if (numa_info[i].node_mem) { 293 return MIN(pow2floor(numa_info[i].node_mem), ram_size); 294 } 295 } 296 } 297 return ram_size; 298 } 299 300 #define _FDT(exp) \ 301 do { \ 302 int ret = (exp); \ 303 if (ret < 0) { \ 304 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 305 #exp, fdt_strerror(ret)); \ 306 exit(1); \ 307 } \ 308 } while (0) 309 310 static void add_str(GString *s, const gchar *s1) 311 { 312 g_string_append_len(s, s1, strlen(s1) + 1); 313 } 314 315 static void *spapr_create_fdt_skel(hwaddr initrd_base, 316 hwaddr initrd_size, 317 hwaddr kernel_size, 318 bool little_endian, 319 const char *boot_device, 320 const char *kernel_cmdline, 321 uint32_t epow_irq) 322 { 323 void *fdt; 324 CPUState *cs; 325 uint32_t start_prop = cpu_to_be32(initrd_base); 326 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 327 GString *hypertas = g_string_sized_new(256); 328 GString *qemu_hypertas = g_string_sized_new(256); 329 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 330 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; 331 int smt = kvmppc_smt_threads(); 332 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 333 QemuOpts *opts = qemu_opts_find(qemu_find_opts("smp-opts"), NULL); 334 unsigned sockets = opts ? qemu_opt_get_number(opts, "sockets", 0) : 0; 335 uint32_t cpus_per_socket = sockets ? (smp_cpus / sockets) : 1; 336 char *buf; 337 338 add_str(hypertas, "hcall-pft"); 339 add_str(hypertas, "hcall-term"); 340 add_str(hypertas, "hcall-dabr"); 341 add_str(hypertas, "hcall-interrupt"); 342 add_str(hypertas, "hcall-tce"); 343 add_str(hypertas, "hcall-vio"); 344 add_str(hypertas, "hcall-splpar"); 345 add_str(hypertas, "hcall-bulk"); 346 add_str(hypertas, "hcall-set-mode"); 347 add_str(qemu_hypertas, "hcall-memop1"); 348 349 fdt = g_malloc0(FDT_MAX_SIZE); 350 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 351 352 if (kernel_size) { 353 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 354 } 355 if (initrd_size) { 356 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 357 } 358 _FDT((fdt_finish_reservemap(fdt))); 359 360 /* Root node */ 361 _FDT((fdt_begin_node(fdt, ""))); 362 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 363 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 364 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 365 366 /* 367 * Add info to guest to indentify which host is it being run on 368 * and what is the uuid of the guest 369 */ 370 if (kvmppc_get_host_model(&buf)) { 371 _FDT((fdt_property_string(fdt, "host-model", buf))); 372 g_free(buf); 373 } 374 if (kvmppc_get_host_serial(&buf)) { 375 _FDT((fdt_property_string(fdt, "host-serial", buf))); 376 g_free(buf); 377 } 378 379 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1], 380 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4], 381 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7], 382 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10], 383 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13], 384 qemu_uuid[14], qemu_uuid[15]); 385 386 _FDT((fdt_property_string(fdt, "vm,uuid", buf))); 387 g_free(buf); 388 389 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 390 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 391 392 /* /chosen */ 393 _FDT((fdt_begin_node(fdt, "chosen"))); 394 395 /* Set Form1_affinity */ 396 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 397 398 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 399 _FDT((fdt_property(fdt, "linux,initrd-start", 400 &start_prop, sizeof(start_prop)))); 401 _FDT((fdt_property(fdt, "linux,initrd-end", 402 &end_prop, sizeof(end_prop)))); 403 if (kernel_size) { 404 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 405 cpu_to_be64(kernel_size) }; 406 407 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 408 if (little_endian) { 409 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 410 } 411 } 412 if (boot_device) { 413 _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device))); 414 } 415 if (boot_menu) { 416 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); 417 } 418 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 419 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 420 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 421 422 _FDT((fdt_end_node(fdt))); 423 424 /* cpus */ 425 _FDT((fdt_begin_node(fdt, "cpus"))); 426 427 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 428 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 429 430 CPU_FOREACH(cs) { 431 PowerPCCPU *cpu = POWERPC_CPU(cs); 432 CPUPPCState *env = &cpu->env; 433 DeviceClass *dc = DEVICE_GET_CLASS(cs); 434 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 435 int index = ppc_get_vcpu_dt_id(cpu); 436 char *nodename; 437 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 438 0xffffffff, 0xffffffff}; 439 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 440 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 441 uint32_t page_sizes_prop[64]; 442 size_t page_sizes_prop_size; 443 444 if ((index % smt) != 0) { 445 continue; 446 } 447 448 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 449 450 _FDT((fdt_begin_node(fdt, nodename))); 451 452 g_free(nodename); 453 454 _FDT((fdt_property_cell(fdt, "reg", index))); 455 _FDT((fdt_property_string(fdt, "device_type", "cpu"))); 456 457 _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); 458 _FDT((fdt_property_cell(fdt, "d-cache-block-size", 459 env->dcache_line_size))); 460 _FDT((fdt_property_cell(fdt, "d-cache-line-size", 461 env->dcache_line_size))); 462 _FDT((fdt_property_cell(fdt, "i-cache-block-size", 463 env->icache_line_size))); 464 _FDT((fdt_property_cell(fdt, "i-cache-line-size", 465 env->icache_line_size))); 466 467 if (pcc->l1_dcache_size) { 468 _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size))); 469 } else { 470 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 471 } 472 if (pcc->l1_icache_size) { 473 _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size))); 474 } else { 475 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 476 } 477 478 _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq))); 479 _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq))); 480 _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); 481 _FDT((fdt_property_string(fdt, "status", "okay"))); 482 _FDT((fdt_property(fdt, "64-bit", NULL, 0))); 483 484 if (env->spr_cb[SPR_PURR].oea_read) { 485 _FDT((fdt_property(fdt, "ibm,purr", NULL, 0))); 486 } 487 488 if (env->mmu_model & POWERPC_MMU_1TSEG) { 489 _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", 490 segs, sizeof(segs)))); 491 } 492 493 /* Advertise VMX/VSX (vector extensions) if available 494 * 0 / no property == no vector extensions 495 * 1 == VMX / Altivec available 496 * 2 == VSX available */ 497 if (env->insns_flags & PPC_ALTIVEC) { 498 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 499 500 _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx))); 501 } 502 503 /* Advertise DFP (Decimal Floating Point) if available 504 * 0 / no property == no DFP 505 * 1 == DFP available */ 506 if (env->insns_flags2 & PPC2_DFP) { 507 _FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); 508 } 509 510 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 511 sizeof(page_sizes_prop)); 512 if (page_sizes_prop_size) { 513 _FDT((fdt_property(fdt, "ibm,segment-page-sizes", 514 page_sizes_prop, page_sizes_prop_size))); 515 } 516 517 _FDT((fdt_property_cell(fdt, "ibm,chip-id", 518 cs->cpu_index / cpus_per_socket))); 519 520 _FDT((fdt_end_node(fdt))); 521 } 522 523 _FDT((fdt_end_node(fdt))); 524 525 /* RTAS */ 526 _FDT((fdt_begin_node(fdt, "rtas"))); 527 528 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 529 add_str(hypertas, "hcall-multi-tce"); 530 } 531 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, 532 hypertas->len))); 533 g_string_free(hypertas, TRUE); 534 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, 535 qemu_hypertas->len))); 536 g_string_free(qemu_hypertas, TRUE); 537 538 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 539 refpoints, sizeof(refpoints)))); 540 541 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 542 543 /* 544 * According to PAPR, rtas ibm,os-term does not guarantee a return 545 * back to the guest cpu. 546 * 547 * While an additional ibm,extended-os-term property indicates that 548 * rtas call return will always occur. Set this property. 549 */ 550 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0))); 551 552 _FDT((fdt_end_node(fdt))); 553 554 /* interrupt controller */ 555 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 556 557 _FDT((fdt_property_string(fdt, "device_type", 558 "PowerPC-External-Interrupt-Presentation"))); 559 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 560 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 561 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 562 interrupt_server_ranges_prop, 563 sizeof(interrupt_server_ranges_prop)))); 564 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 565 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 566 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 567 568 _FDT((fdt_end_node(fdt))); 569 570 /* vdevice */ 571 _FDT((fdt_begin_node(fdt, "vdevice"))); 572 573 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 574 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 575 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 576 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 577 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 578 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 579 580 _FDT((fdt_end_node(fdt))); 581 582 /* event-sources */ 583 spapr_events_fdt_skel(fdt, epow_irq); 584 585 /* /hypervisor node */ 586 if (kvm_enabled()) { 587 uint8_t hypercall[16]; 588 589 /* indicate KVM hypercall interface */ 590 _FDT((fdt_begin_node(fdt, "hypervisor"))); 591 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); 592 if (kvmppc_has_cap_fixup_hcalls()) { 593 /* 594 * Older KVM versions with older guest kernels were broken with the 595 * magic page, don't allow the guest to map it. 596 */ 597 kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 598 sizeof(hypercall)); 599 _FDT((fdt_property(fdt, "hcall-instructions", hypercall, 600 sizeof(hypercall)))); 601 } 602 _FDT((fdt_end_node(fdt))); 603 } 604 605 _FDT((fdt_end_node(fdt))); /* close root node */ 606 _FDT((fdt_finish(fdt))); 607 608 return fdt; 609 } 610 611 int spapr_h_cas_compose_response(target_ulong addr, target_ulong size) 612 { 613 void *fdt, *fdt_skel; 614 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 615 616 size -= sizeof(hdr); 617 618 /* Create sceleton */ 619 fdt_skel = g_malloc0(size); 620 _FDT((fdt_create(fdt_skel, size))); 621 _FDT((fdt_begin_node(fdt_skel, ""))); 622 _FDT((fdt_end_node(fdt_skel))); 623 _FDT((fdt_finish(fdt_skel))); 624 fdt = g_malloc0(size); 625 _FDT((fdt_open_into(fdt_skel, fdt, size))); 626 g_free(fdt_skel); 627 628 /* Fix skeleton up */ 629 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 630 631 /* Pack resulting tree */ 632 _FDT((fdt_pack(fdt))); 633 634 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 635 trace_spapr_cas_failed(size); 636 return -1; 637 } 638 639 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 640 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 641 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 642 g_free(fdt); 643 644 return 0; 645 } 646 647 static void spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 648 hwaddr size) 649 { 650 uint32_t associativity[] = { 651 cpu_to_be32(0x4), /* length */ 652 cpu_to_be32(0x0), cpu_to_be32(0x0), 653 cpu_to_be32(0x0), cpu_to_be32(nodeid) 654 }; 655 char mem_name[32]; 656 uint64_t mem_reg_property[2]; 657 int off; 658 659 mem_reg_property[0] = cpu_to_be64(start); 660 mem_reg_property[1] = cpu_to_be64(size); 661 662 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 663 off = fdt_add_subnode(fdt, 0, mem_name); 664 _FDT(off); 665 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 666 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 667 sizeof(mem_reg_property)))); 668 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 669 sizeof(associativity)))); 670 } 671 672 static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt) 673 { 674 hwaddr mem_start, node_size; 675 int i, nb_nodes = nb_numa_nodes; 676 NodeInfo *nodes = numa_info; 677 NodeInfo ramnode; 678 679 /* No NUMA nodes, assume there is just one node with whole RAM */ 680 if (!nb_numa_nodes) { 681 nb_nodes = 1; 682 ramnode.node_mem = ram_size; 683 nodes = &ramnode; 684 } 685 686 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 687 if (!nodes[i].node_mem) { 688 continue; 689 } 690 if (mem_start >= ram_size) { 691 node_size = 0; 692 } else { 693 node_size = nodes[i].node_mem; 694 if (node_size > ram_size - mem_start) { 695 node_size = ram_size - mem_start; 696 } 697 } 698 if (!mem_start) { 699 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 700 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 701 mem_start += spapr->rma_size; 702 node_size -= spapr->rma_size; 703 } 704 for ( ; node_size; ) { 705 hwaddr sizetmp = pow2floor(node_size); 706 707 /* mem_start != 0 here */ 708 if (ctzl(mem_start) < ctzl(sizetmp)) { 709 sizetmp = 1ULL << ctzl(mem_start); 710 } 711 712 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 713 node_size -= sizetmp; 714 mem_start += sizetmp; 715 } 716 } 717 718 return 0; 719 } 720 721 static void spapr_finalize_fdt(sPAPREnvironment *spapr, 722 hwaddr fdt_addr, 723 hwaddr rtas_addr, 724 hwaddr rtas_size) 725 { 726 int ret, i; 727 size_t cb = 0; 728 char *bootlist; 729 void *fdt; 730 sPAPRPHBState *phb; 731 732 fdt = g_malloc(FDT_MAX_SIZE); 733 734 /* open out the base tree into a temp buffer for the final tweaks */ 735 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 736 737 ret = spapr_populate_memory(spapr, fdt); 738 if (ret < 0) { 739 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 740 exit(1); 741 } 742 743 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 744 if (ret < 0) { 745 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 746 exit(1); 747 } 748 749 QLIST_FOREACH(phb, &spapr->phbs, list) { 750 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 751 } 752 753 if (ret < 0) { 754 fprintf(stderr, "couldn't setup PCI devices in fdt\n"); 755 exit(1); 756 } 757 758 /* RTAS */ 759 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 760 if (ret < 0) { 761 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 762 } 763 764 /* Advertise NUMA via ibm,associativity */ 765 ret = spapr_fixup_cpu_dt(fdt, spapr); 766 if (ret < 0) { 767 fprintf(stderr, "Couldn't finalize CPU device tree properties\n"); 768 } 769 770 bootlist = get_boot_devices_list(&cb, true); 771 if (cb && bootlist) { 772 int offset = fdt_path_offset(fdt, "/chosen"); 773 if (offset < 0) { 774 exit(1); 775 } 776 for (i = 0; i < cb; i++) { 777 if (bootlist[i] == '\n') { 778 bootlist[i] = ' '; 779 } 780 781 } 782 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); 783 } 784 785 if (!spapr->has_graphics) { 786 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 787 } 788 789 _FDT((fdt_pack(fdt))); 790 791 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 792 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n", 793 fdt_totalsize(fdt), FDT_MAX_SIZE); 794 exit(1); 795 } 796 797 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 798 799 g_free(bootlist); 800 g_free(fdt); 801 } 802 803 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 804 { 805 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 806 } 807 808 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 809 { 810 CPUPPCState *env = &cpu->env; 811 812 if (msr_pr) { 813 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 814 env->gpr[3] = H_PRIVILEGE; 815 } else { 816 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 817 } 818 } 819 820 static void spapr_reset_htab(sPAPREnvironment *spapr) 821 { 822 long shift; 823 824 /* allocate hash page table. For now we always make this 16mb, 825 * later we should probably make it scale to the size of guest 826 * RAM */ 827 828 shift = kvmppc_reset_htab(spapr->htab_shift); 829 830 if (shift > 0) { 831 /* Kernel handles htab, we don't need to allocate one */ 832 spapr->htab_shift = shift; 833 kvmppc_kern_htab = true; 834 } else { 835 if (!spapr->htab) { 836 /* Allocate an htab if we don't yet have one */ 837 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); 838 } 839 840 /* And clear it */ 841 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 842 } 843 844 /* Update the RMA size if necessary */ 845 if (spapr->vrma_adjust) { 846 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 847 spapr->htab_shift); 848 } 849 } 850 851 static void ppc_spapr_reset(void) 852 { 853 PowerPCCPU *first_ppc_cpu; 854 uint32_t rtas_limit; 855 856 /* Reset the hash table & recalc the RMA */ 857 spapr_reset_htab(spapr); 858 859 qemu_devices_reset(); 860 861 /* 862 * We place the device tree and RTAS just below either the top of the RMA, 863 * or just below 2GB, whichever is lowere, so that it can be 864 * processed with 32-bit real mode code if necessary 865 */ 866 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 867 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 868 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 869 870 /* Load the fdt */ 871 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 872 spapr->rtas_size); 873 874 /* Copy RTAS over */ 875 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob, 876 spapr->rtas_size); 877 878 /* Set up the entry state */ 879 first_ppc_cpu = POWERPC_CPU(first_cpu); 880 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 881 first_ppc_cpu->env.gpr[5] = 0; 882 first_cpu->halted = 0; 883 first_ppc_cpu->env.nip = spapr->entry_point; 884 885 } 886 887 static void spapr_cpu_reset(void *opaque) 888 { 889 PowerPCCPU *cpu = opaque; 890 CPUState *cs = CPU(cpu); 891 CPUPPCState *env = &cpu->env; 892 893 cpu_reset(cs); 894 895 /* All CPUs start halted. CPU0 is unhalted from the machine level 896 * reset code and the rest are explicitly started up by the guest 897 * using an RTAS call */ 898 cs->halted = 1; 899 900 env->spr[SPR_HIOR] = 0; 901 902 env->external_htab = (uint8_t *)spapr->htab; 903 if (kvm_enabled() && !env->external_htab) { 904 /* 905 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte* 906 * functions do the right thing. 907 */ 908 env->external_htab = (void *)1; 909 } 910 env->htab_base = -1; 911 /* 912 * htab_mask is the mask used to normalize hash value to PTEG index. 913 * htab_shift is log2 of hash table size. 914 * We have 8 hpte per group, and each hpte is 16 bytes. 915 * ie have 128 bytes per hpte entry. 916 */ 917 env->htab_mask = (1ULL << ((spapr)->htab_shift - 7)) - 1; 918 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | 919 (spapr->htab_shift - 18); 920 } 921 922 static void spapr_create_nvram(sPAPREnvironment *spapr) 923 { 924 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 925 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 926 927 if (dinfo) { 928 qdev_prop_set_drive_nofail(dev, "drive", dinfo->bdrv); 929 } 930 931 qdev_init_nofail(dev); 932 933 spapr->nvram = (struct sPAPRNVRAM *)dev; 934 } 935 936 /* Returns whether we want to use VGA or not */ 937 static int spapr_vga_init(PCIBus *pci_bus) 938 { 939 switch (vga_interface_type) { 940 case VGA_NONE: 941 return false; 942 case VGA_DEVICE: 943 return true; 944 case VGA_STD: 945 return pci_vga_init(pci_bus) != NULL; 946 default: 947 fprintf(stderr, "This vga model is not supported," 948 "currently it only supports -vga std\n"); 949 exit(0); 950 } 951 } 952 953 static const VMStateDescription vmstate_spapr = { 954 .name = "spapr", 955 .version_id = 2, 956 .minimum_version_id = 1, 957 .fields = (VMStateField[]) { 958 VMSTATE_UNUSED(4), /* used to be @next_irq */ 959 960 /* RTC offset */ 961 VMSTATE_UINT64(rtc_offset, sPAPREnvironment), 962 VMSTATE_PPC_TIMEBASE_V(tb, sPAPREnvironment, 2), 963 VMSTATE_END_OF_LIST() 964 }, 965 }; 966 967 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 968 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 969 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 970 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 971 972 static int htab_save_setup(QEMUFile *f, void *opaque) 973 { 974 sPAPREnvironment *spapr = opaque; 975 976 /* "Iteration" header */ 977 qemu_put_be32(f, spapr->htab_shift); 978 979 if (spapr->htab) { 980 spapr->htab_save_index = 0; 981 spapr->htab_first_pass = true; 982 } else { 983 assert(kvm_enabled()); 984 985 spapr->htab_fd = kvmppc_get_htab_fd(false); 986 if (spapr->htab_fd < 0) { 987 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", 988 strerror(errno)); 989 return -1; 990 } 991 } 992 993 994 return 0; 995 } 996 997 static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr, 998 int64_t max_ns) 999 { 1000 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1001 int index = spapr->htab_save_index; 1002 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1003 1004 assert(spapr->htab_first_pass); 1005 1006 do { 1007 int chunkstart; 1008 1009 /* Consume invalid HPTEs */ 1010 while ((index < htabslots) 1011 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1012 index++; 1013 CLEAN_HPTE(HPTE(spapr->htab, index)); 1014 } 1015 1016 /* Consume valid HPTEs */ 1017 chunkstart = index; 1018 while ((index < htabslots) 1019 && HPTE_VALID(HPTE(spapr->htab, index))) { 1020 index++; 1021 CLEAN_HPTE(HPTE(spapr->htab, index)); 1022 } 1023 1024 if (index > chunkstart) { 1025 int n_valid = index - chunkstart; 1026 1027 qemu_put_be32(f, chunkstart); 1028 qemu_put_be16(f, n_valid); 1029 qemu_put_be16(f, 0); 1030 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1031 HASH_PTE_SIZE_64 * n_valid); 1032 1033 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1034 break; 1035 } 1036 } 1037 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1038 1039 if (index >= htabslots) { 1040 assert(index == htabslots); 1041 index = 0; 1042 spapr->htab_first_pass = false; 1043 } 1044 spapr->htab_save_index = index; 1045 } 1046 1047 static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, 1048 int64_t max_ns) 1049 { 1050 bool final = max_ns < 0; 1051 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1052 int examined = 0, sent = 0; 1053 int index = spapr->htab_save_index; 1054 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1055 1056 assert(!spapr->htab_first_pass); 1057 1058 do { 1059 int chunkstart, invalidstart; 1060 1061 /* Consume non-dirty HPTEs */ 1062 while ((index < htabslots) 1063 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1064 index++; 1065 examined++; 1066 } 1067 1068 chunkstart = index; 1069 /* Consume valid dirty HPTEs */ 1070 while ((index < htabslots) 1071 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1072 && HPTE_VALID(HPTE(spapr->htab, index))) { 1073 CLEAN_HPTE(HPTE(spapr->htab, index)); 1074 index++; 1075 examined++; 1076 } 1077 1078 invalidstart = index; 1079 /* Consume invalid dirty HPTEs */ 1080 while ((index < htabslots) 1081 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1082 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1083 CLEAN_HPTE(HPTE(spapr->htab, index)); 1084 index++; 1085 examined++; 1086 } 1087 1088 if (index > chunkstart) { 1089 int n_valid = invalidstart - chunkstart; 1090 int n_invalid = index - invalidstart; 1091 1092 qemu_put_be32(f, chunkstart); 1093 qemu_put_be16(f, n_valid); 1094 qemu_put_be16(f, n_invalid); 1095 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1096 HASH_PTE_SIZE_64 * n_valid); 1097 sent += index - chunkstart; 1098 1099 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1100 break; 1101 } 1102 } 1103 1104 if (examined >= htabslots) { 1105 break; 1106 } 1107 1108 if (index >= htabslots) { 1109 assert(index == htabslots); 1110 index = 0; 1111 } 1112 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1113 1114 if (index >= htabslots) { 1115 assert(index == htabslots); 1116 index = 0; 1117 } 1118 1119 spapr->htab_save_index = index; 1120 1121 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1122 } 1123 1124 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1125 #define MAX_KVM_BUF_SIZE 2048 1126 1127 static int htab_save_iterate(QEMUFile *f, void *opaque) 1128 { 1129 sPAPREnvironment *spapr = opaque; 1130 int rc = 0; 1131 1132 /* Iteration header */ 1133 qemu_put_be32(f, 0); 1134 1135 if (!spapr->htab) { 1136 assert(kvm_enabled()); 1137 1138 rc = kvmppc_save_htab(f, spapr->htab_fd, 1139 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1140 if (rc < 0) { 1141 return rc; 1142 } 1143 } else if (spapr->htab_first_pass) { 1144 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1145 } else { 1146 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1147 } 1148 1149 /* End marker */ 1150 qemu_put_be32(f, 0); 1151 qemu_put_be16(f, 0); 1152 qemu_put_be16(f, 0); 1153 1154 return rc; 1155 } 1156 1157 static int htab_save_complete(QEMUFile *f, void *opaque) 1158 { 1159 sPAPREnvironment *spapr = opaque; 1160 1161 /* Iteration header */ 1162 qemu_put_be32(f, 0); 1163 1164 if (!spapr->htab) { 1165 int rc; 1166 1167 assert(kvm_enabled()); 1168 1169 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); 1170 if (rc < 0) { 1171 return rc; 1172 } 1173 close(spapr->htab_fd); 1174 spapr->htab_fd = -1; 1175 } else { 1176 htab_save_later_pass(f, spapr, -1); 1177 } 1178 1179 /* End marker */ 1180 qemu_put_be32(f, 0); 1181 qemu_put_be16(f, 0); 1182 qemu_put_be16(f, 0); 1183 1184 return 0; 1185 } 1186 1187 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1188 { 1189 sPAPREnvironment *spapr = opaque; 1190 uint32_t section_hdr; 1191 int fd = -1; 1192 1193 if (version_id < 1 || version_id > 1) { 1194 fprintf(stderr, "htab_load() bad version\n"); 1195 return -EINVAL; 1196 } 1197 1198 section_hdr = qemu_get_be32(f); 1199 1200 if (section_hdr) { 1201 /* First section, just the hash shift */ 1202 if (spapr->htab_shift != section_hdr) { 1203 return -EINVAL; 1204 } 1205 return 0; 1206 } 1207 1208 if (!spapr->htab) { 1209 assert(kvm_enabled()); 1210 1211 fd = kvmppc_get_htab_fd(true); 1212 if (fd < 0) { 1213 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", 1214 strerror(errno)); 1215 } 1216 } 1217 1218 while (true) { 1219 uint32_t index; 1220 uint16_t n_valid, n_invalid; 1221 1222 index = qemu_get_be32(f); 1223 n_valid = qemu_get_be16(f); 1224 n_invalid = qemu_get_be16(f); 1225 1226 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1227 /* End of Stream */ 1228 break; 1229 } 1230 1231 if ((index + n_valid + n_invalid) > 1232 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1233 /* Bad index in stream */ 1234 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " 1235 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, 1236 spapr->htab_shift); 1237 return -EINVAL; 1238 } 1239 1240 if (spapr->htab) { 1241 if (n_valid) { 1242 qemu_get_buffer(f, HPTE(spapr->htab, index), 1243 HASH_PTE_SIZE_64 * n_valid); 1244 } 1245 if (n_invalid) { 1246 memset(HPTE(spapr->htab, index + n_valid), 0, 1247 HASH_PTE_SIZE_64 * n_invalid); 1248 } 1249 } else { 1250 int rc; 1251 1252 assert(fd >= 0); 1253 1254 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1255 if (rc < 0) { 1256 return rc; 1257 } 1258 } 1259 } 1260 1261 if (!spapr->htab) { 1262 assert(fd >= 0); 1263 close(fd); 1264 } 1265 1266 return 0; 1267 } 1268 1269 static SaveVMHandlers savevm_htab_handlers = { 1270 .save_live_setup = htab_save_setup, 1271 .save_live_iterate = htab_save_iterate, 1272 .save_live_complete = htab_save_complete, 1273 .load_state = htab_load, 1274 }; 1275 1276 /* pSeries LPAR / sPAPR hardware init */ 1277 static void ppc_spapr_init(MachineState *machine) 1278 { 1279 ram_addr_t ram_size = machine->ram_size; 1280 const char *cpu_model = machine->cpu_model; 1281 const char *kernel_filename = machine->kernel_filename; 1282 const char *kernel_cmdline = machine->kernel_cmdline; 1283 const char *initrd_filename = machine->initrd_filename; 1284 const char *boot_device = machine->boot_order; 1285 PowerPCCPU *cpu; 1286 CPUPPCState *env; 1287 PCIHostState *phb; 1288 int i; 1289 MemoryRegion *sysmem = get_system_memory(); 1290 MemoryRegion *ram = g_new(MemoryRegion, 1); 1291 MemoryRegion *rma_region; 1292 void *rma = NULL; 1293 hwaddr rma_alloc_size; 1294 hwaddr node0_size = spapr_node0_size(); 1295 uint32_t initrd_base = 0; 1296 long kernel_size = 0, initrd_size = 0; 1297 long load_limit, fw_size; 1298 bool kernel_le = false; 1299 char *filename; 1300 1301 msi_supported = true; 1302 1303 spapr = g_malloc0(sizeof(*spapr)); 1304 QLIST_INIT(&spapr->phbs); 1305 1306 cpu_ppc_hypercall = emulate_spapr_hypercall; 1307 1308 /* Allocate RMA if necessary */ 1309 rma_alloc_size = kvmppc_alloc_rma(&rma); 1310 1311 if (rma_alloc_size == -1) { 1312 hw_error("qemu: Unable to create RMA\n"); 1313 exit(1); 1314 } 1315 1316 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1317 spapr->rma_size = rma_alloc_size; 1318 } else { 1319 spapr->rma_size = node0_size; 1320 1321 /* With KVM, we don't actually know whether KVM supports an 1322 * unbounded RMA (PR KVM) or is limited by the hash table size 1323 * (HV KVM using VRMA), so we always assume the latter 1324 * 1325 * In that case, we also limit the initial allocations for RTAS 1326 * etc... to 256M since we have no way to know what the VRMA size 1327 * is going to be as it depends on the size of the hash table 1328 * isn't determined yet. 1329 */ 1330 if (kvm_enabled()) { 1331 spapr->vrma_adjust = 1; 1332 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1333 } 1334 } 1335 1336 if (spapr->rma_size > node0_size) { 1337 fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n", 1338 spapr->rma_size); 1339 exit(1); 1340 } 1341 1342 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 1343 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 1344 1345 /* We aim for a hash table of size 1/128 the size of RAM. The 1346 * normal rule of thumb is 1/64 the size of RAM, but that's much 1347 * more than needed for the Linux guests we support. */ 1348 spapr->htab_shift = 18; /* Minimum architected size */ 1349 while (spapr->htab_shift <= 46) { 1350 if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) { 1351 break; 1352 } 1353 spapr->htab_shift++; 1354 } 1355 1356 /* Set up Interrupt Controller before we create the VCPUs */ 1357 spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads, 1358 XICS_IRQS); 1359 1360 /* init CPUs */ 1361 if (cpu_model == NULL) { 1362 cpu_model = kvm_enabled() ? "host" : "POWER7"; 1363 } 1364 for (i = 0; i < smp_cpus; i++) { 1365 cpu = cpu_ppc_init(cpu_model); 1366 if (cpu == NULL) { 1367 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 1368 exit(1); 1369 } 1370 env = &cpu->env; 1371 1372 /* Set time-base frequency to 512 MHz */ 1373 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 1374 1375 /* PAPR always has exception vectors in RAM not ROM. To ensure this, 1376 * MSR[IP] should never be set. 1377 */ 1378 env->msr_mask &= ~(1 << 6); 1379 1380 /* Tell KVM that we're in PAPR mode */ 1381 if (kvm_enabled()) { 1382 kvmppc_set_papr(cpu); 1383 } 1384 1385 if (cpu->max_compat) { 1386 if (ppc_set_compat(cpu, cpu->max_compat) < 0) { 1387 exit(1); 1388 } 1389 } 1390 1391 xics_cpu_setup(spapr->icp, cpu); 1392 1393 qemu_register_reset(spapr_cpu_reset, cpu); 1394 } 1395 1396 /* allocate RAM */ 1397 spapr->ram_limit = ram_size; 1398 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 1399 spapr->ram_limit); 1400 memory_region_add_subregion(sysmem, 0, ram); 1401 1402 if (rma_alloc_size && rma) { 1403 rma_region = g_new(MemoryRegion, 1); 1404 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 1405 rma_alloc_size, rma); 1406 vmstate_register_ram_global(rma_region); 1407 memory_region_add_subregion(sysmem, 0, rma_region); 1408 } 1409 1410 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1411 spapr->rtas_size = get_image_size(filename); 1412 spapr->rtas_blob = g_malloc(spapr->rtas_size); 1413 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 1414 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1415 exit(1); 1416 } 1417 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1418 hw_error("RTAS too big ! 0x%zx bytes (max is 0x%x)\n", 1419 spapr->rtas_size, RTAS_MAX_SIZE); 1420 exit(1); 1421 } 1422 g_free(filename); 1423 1424 /* Set up EPOW events infrastructure */ 1425 spapr_events_init(spapr); 1426 1427 /* Set up VIO bus */ 1428 spapr->vio_bus = spapr_vio_bus_init(); 1429 1430 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1431 if (serial_hds[i]) { 1432 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1433 } 1434 } 1435 1436 /* We always have at least the nvram device on VIO */ 1437 spapr_create_nvram(spapr); 1438 1439 /* Set up PCI */ 1440 spapr_pci_rtas_init(); 1441 1442 phb = spapr_create_phb(spapr, 0); 1443 1444 for (i = 0; i < nb_nics; i++) { 1445 NICInfo *nd = &nd_table[i]; 1446 1447 if (!nd->model) { 1448 nd->model = g_strdup("ibmveth"); 1449 } 1450 1451 if (strcmp(nd->model, "ibmveth") == 0) { 1452 spapr_vlan_create(spapr->vio_bus, nd); 1453 } else { 1454 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1455 } 1456 } 1457 1458 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1459 spapr_vscsi_create(spapr->vio_bus); 1460 } 1461 1462 /* Graphics */ 1463 if (spapr_vga_init(phb->bus)) { 1464 spapr->has_graphics = true; 1465 } 1466 1467 if (usb_enabled(spapr->has_graphics)) { 1468 pci_create_simple(phb->bus, -1, "pci-ohci"); 1469 if (spapr->has_graphics) { 1470 usbdevice_create("keyboard"); 1471 usbdevice_create("mouse"); 1472 } 1473 } 1474 1475 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1476 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " 1477 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); 1478 exit(1); 1479 } 1480 1481 if (kernel_filename) { 1482 uint64_t lowaddr = 0; 1483 1484 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1485 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); 1486 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { 1487 kernel_size = load_elf(kernel_filename, 1488 translate_kernel_address, NULL, 1489 NULL, &lowaddr, NULL, 0, ELF_MACHINE, 0); 1490 kernel_le = kernel_size > 0; 1491 } 1492 if (kernel_size < 0) { 1493 fprintf(stderr, "qemu: error loading %s: %s\n", 1494 kernel_filename, load_elf_strerror(kernel_size)); 1495 exit(1); 1496 } 1497 1498 /* load initrd */ 1499 if (initrd_filename) { 1500 /* Try to locate the initrd in the gap between the kernel 1501 * and the firmware. Add a bit of space just in case 1502 */ 1503 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1504 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1505 load_limit - initrd_base); 1506 if (initrd_size < 0) { 1507 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 1508 initrd_filename); 1509 exit(1); 1510 } 1511 } else { 1512 initrd_base = 0; 1513 initrd_size = 0; 1514 } 1515 } 1516 1517 if (bios_name == NULL) { 1518 bios_name = FW_FILE_NAME; 1519 } 1520 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1521 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 1522 if (fw_size < 0) { 1523 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1524 exit(1); 1525 } 1526 g_free(filename); 1527 1528 spapr->entry_point = 0x100; 1529 1530 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 1531 register_savevm_live(NULL, "spapr/htab", -1, 1, 1532 &savevm_htab_handlers, spapr); 1533 1534 /* Prepare the device tree */ 1535 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 1536 kernel_size, kernel_le, 1537 boot_device, kernel_cmdline, 1538 spapr->epow_irq); 1539 assert(spapr->fdt_skel != NULL); 1540 } 1541 1542 static int spapr_kvm_type(const char *vm_type) 1543 { 1544 if (!vm_type) { 1545 return 0; 1546 } 1547 1548 if (!strcmp(vm_type, "HV")) { 1549 return 1; 1550 } 1551 1552 if (!strcmp(vm_type, "PR")) { 1553 return 2; 1554 } 1555 1556 error_report("Unknown kvm-type specified '%s'", vm_type); 1557 exit(1); 1558 } 1559 1560 /* 1561 * Implementation of an interface to adjust firmware patch 1562 * for the bootindex property handling. 1563 */ 1564 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 1565 DeviceState *dev) 1566 { 1567 #define CAST(type, obj, name) \ 1568 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 1569 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 1570 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 1571 1572 if (d) { 1573 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 1574 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 1575 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 1576 1577 if (spapr) { 1578 /* 1579 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 1580 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 1581 * in the top 16 bits of the 64-bit LUN 1582 */ 1583 unsigned id = 0x8000 | (d->id << 8) | d->lun; 1584 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1585 (uint64_t)id << 48); 1586 } else if (virtio) { 1587 /* 1588 * We use SRP luns of the form 01000000 | (target << 8) | lun 1589 * in the top 32 bits of the 64-bit LUN 1590 * Note: the quote above is from SLOF and it is wrong, 1591 * the actual binding is: 1592 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 1593 */ 1594 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 1595 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1596 (uint64_t)id << 32); 1597 } else if (usb) { 1598 /* 1599 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 1600 * in the top 32 bits of the 64-bit LUN 1601 */ 1602 unsigned usb_port = atoi(usb->port->path); 1603 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 1604 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1605 (uint64_t)id << 32); 1606 } 1607 } 1608 1609 if (phb) { 1610 /* Replace "pci" with "pci@800000020000000" */ 1611 return g_strdup_printf("pci@%"PRIX64, phb->buid); 1612 } 1613 1614 return NULL; 1615 } 1616 1617 static char *spapr_get_kvm_type(Object *obj, Error **errp) 1618 { 1619 sPAPRMachineState *sm = SPAPR_MACHINE(obj); 1620 1621 return g_strdup(sm->kvm_type); 1622 } 1623 1624 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 1625 { 1626 sPAPRMachineState *sm = SPAPR_MACHINE(obj); 1627 1628 g_free(sm->kvm_type); 1629 sm->kvm_type = g_strdup(value); 1630 } 1631 1632 static void spapr_machine_initfn(Object *obj) 1633 { 1634 object_property_add_str(obj, "kvm-type", 1635 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 1636 } 1637 1638 static void ppc_cpu_do_nmi_on_cpu(void *arg) 1639 { 1640 CPUState *cs = arg; 1641 1642 cpu_synchronize_state(cs); 1643 ppc_cpu_do_system_reset(cs); 1644 } 1645 1646 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 1647 { 1648 CPUState *cs; 1649 1650 CPU_FOREACH(cs) { 1651 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs); 1652 } 1653 } 1654 1655 static void spapr_machine_class_init(ObjectClass *oc, void *data) 1656 { 1657 MachineClass *mc = MACHINE_CLASS(oc); 1658 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 1659 NMIClass *nc = NMI_CLASS(oc); 1660 1661 mc->name = "pseries"; 1662 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 1663 mc->is_default = 1; 1664 mc->init = ppc_spapr_init; 1665 mc->reset = ppc_spapr_reset; 1666 mc->block_default_type = IF_SCSI; 1667 mc->max_cpus = MAX_CPUS; 1668 mc->no_parallel = 1; 1669 mc->default_boot_order = NULL; 1670 mc->kvm_type = spapr_kvm_type; 1671 1672 fwc->get_dev_path = spapr_get_fw_dev_path; 1673 nc->nmi_monitor_handler = spapr_nmi; 1674 } 1675 1676 static const TypeInfo spapr_machine_info = { 1677 .name = TYPE_SPAPR_MACHINE, 1678 .parent = TYPE_MACHINE, 1679 .instance_size = sizeof(sPAPRMachineState), 1680 .instance_init = spapr_machine_initfn, 1681 .class_init = spapr_machine_class_init, 1682 .interfaces = (InterfaceInfo[]) { 1683 { TYPE_FW_PATH_PROVIDER }, 1684 { TYPE_NMI }, 1685 { } 1686 }, 1687 }; 1688 1689 static void spapr_machine_2_1_class_init(ObjectClass *oc, void *data) 1690 { 1691 MachineClass *mc = MACHINE_CLASS(oc); 1692 1693 mc->name = "pseries-2.1"; 1694 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.1"; 1695 mc->is_default = 0; 1696 } 1697 1698 static const TypeInfo spapr_machine_2_1_info = { 1699 .name = TYPE_SPAPR_MACHINE "2.1", 1700 .parent = TYPE_SPAPR_MACHINE, 1701 .class_init = spapr_machine_2_1_class_init, 1702 }; 1703 1704 static void spapr_machine_register_types(void) 1705 { 1706 type_register_static(&spapr_machine_info); 1707 type_register_static(&spapr_machine_2_1_info); 1708 } 1709 1710 type_init(spapr_machine_register_types) 1711