1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qapi/error.h" 30 #include "qapi/visitor.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/hostmem.h" 33 #include "sysemu/numa.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/runstate.h" 37 #include "qemu/log.h" 38 #include "hw/fw-path-provider.h" 39 #include "elf.h" 40 #include "net/net.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/cpus.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_ppc.h" 45 #include "migration/misc.h" 46 #include "migration/qemu-file-types.h" 47 #include "migration/global_state.h" 48 #include "migration/register.h" 49 #include "migration/blocker.h" 50 #include "mmu-hash64.h" 51 #include "mmu-book3s-v3.h" 52 #include "cpu-models.h" 53 #include "hw/core/cpu.h" 54 55 #include "hw/boards.h" 56 #include "hw/ppc/ppc.h" 57 #include "hw/loader.h" 58 59 #include "hw/ppc/fdt.h" 60 #include "hw/ppc/spapr.h" 61 #include "hw/ppc/spapr_vio.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/pci-host/spapr.h" 64 #include "hw/pci/msi.h" 65 66 #include "hw/pci/pci.h" 67 #include "hw/scsi/scsi.h" 68 #include "hw/virtio/virtio-scsi.h" 69 #include "hw/virtio/vhost-scsi-common.h" 70 71 #include "exec/address-spaces.h" 72 #include "exec/ram_addr.h" 73 #include "hw/usb.h" 74 #include "qemu/config-file.h" 75 #include "qemu/error-report.h" 76 #include "trace.h" 77 #include "hw/nmi.h" 78 #include "hw/intc/intc.h" 79 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 #include "hw/ppc/spapr_nvdimm.h" 84 85 #include "monitor/monitor.h" 86 87 #include <libfdt.h> 88 89 /* SLOF memory layout: 90 * 91 * SLOF raw image loaded at 0, copies its romfs right below the flat 92 * device-tree, then position SLOF itself 31M below that 93 * 94 * So we set FW_OVERHEAD to 40MB which should account for all of that 95 * and more 96 * 97 * We load our kernel at 4M, leaving space for SLOF initial image 98 */ 99 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 100 #define FW_MAX_SIZE 0x400000 101 #define FW_FILE_NAME "slof.bin" 102 #define FW_OVERHEAD 0x2800000 103 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 104 105 #define MIN_RMA_SLOF (128 * MiB) 106 107 #define PHANDLE_INTC 0x00001111 108 109 /* These two functions implement the VCPU id numbering: one to compute them 110 * all and one to identify thread 0 of a VCORE. Any change to the first one 111 * is likely to have an impact on the second one, so let's keep them close. 112 */ 113 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 114 { 115 MachineState *ms = MACHINE(spapr); 116 unsigned int smp_threads = ms->smp.threads; 117 118 assert(spapr->vsmt); 119 return 120 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 121 } 122 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 123 PowerPCCPU *cpu) 124 { 125 assert(spapr->vsmt); 126 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 127 } 128 129 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 130 { 131 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 132 * and newer QEMUs don't even have them. In both cases, we don't want 133 * to send anything on the wire. 134 */ 135 return false; 136 } 137 138 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 139 .name = "icp/server", 140 .version_id = 1, 141 .minimum_version_id = 1, 142 .needed = pre_2_10_vmstate_dummy_icp_needed, 143 .fields = (VMStateField[]) { 144 VMSTATE_UNUSED(4), /* uint32_t xirr */ 145 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 146 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 147 VMSTATE_END_OF_LIST() 148 }, 149 }; 150 151 static void pre_2_10_vmstate_register_dummy_icp(int i) 152 { 153 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 154 (void *)(uintptr_t) i); 155 } 156 157 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 158 { 159 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 160 (void *)(uintptr_t) i); 161 } 162 163 int spapr_max_server_number(SpaprMachineState *spapr) 164 { 165 MachineState *ms = MACHINE(spapr); 166 167 assert(spapr->vsmt); 168 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 169 } 170 171 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 172 int smt_threads) 173 { 174 int i, ret = 0; 175 uint32_t servers_prop[smt_threads]; 176 uint32_t gservers_prop[smt_threads * 2]; 177 int index = spapr_get_vcpu_id(cpu); 178 179 if (cpu->compat_pvr) { 180 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 181 if (ret < 0) { 182 return ret; 183 } 184 } 185 186 /* Build interrupt servers and gservers properties */ 187 for (i = 0; i < smt_threads; i++) { 188 servers_prop[i] = cpu_to_be32(index + i); 189 /* Hack, direct the group queues back to cpu 0 */ 190 gservers_prop[i*2] = cpu_to_be32(index + i); 191 gservers_prop[i*2 + 1] = 0; 192 } 193 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 194 servers_prop, sizeof(servers_prop)); 195 if (ret < 0) { 196 return ret; 197 } 198 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 199 gservers_prop, sizeof(gservers_prop)); 200 201 return ret; 202 } 203 204 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 205 { 206 int index = spapr_get_vcpu_id(cpu); 207 uint32_t associativity[] = {cpu_to_be32(0x5), 208 cpu_to_be32(0x0), 209 cpu_to_be32(0x0), 210 cpu_to_be32(0x0), 211 cpu_to_be32(cpu->node_id), 212 cpu_to_be32(index)}; 213 214 /* Advertise NUMA via ibm,associativity */ 215 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 216 sizeof(associativity)); 217 } 218 219 static void spapr_dt_pa_features(SpaprMachineState *spapr, 220 PowerPCCPU *cpu, 221 void *fdt, int offset) 222 { 223 uint8_t pa_features_206[] = { 6, 0, 224 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 225 uint8_t pa_features_207[] = { 24, 0, 226 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 227 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 228 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 229 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 230 uint8_t pa_features_300[] = { 66, 0, 231 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 232 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 233 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 234 /* 6: DS207 */ 235 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 236 /* 16: Vector */ 237 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 238 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 239 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 240 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 241 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 242 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 243 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 244 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 245 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 246 /* 42: PM, 44: PC RA, 46: SC vec'd */ 247 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 248 /* 48: SIMD, 50: QP BFP, 52: String */ 249 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 250 /* 54: DecFP, 56: DecI, 58: SHA */ 251 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 252 /* 60: NM atomic, 62: RNG */ 253 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 254 }; 255 uint8_t *pa_features = NULL; 256 size_t pa_size; 257 258 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 259 pa_features = pa_features_206; 260 pa_size = sizeof(pa_features_206); 261 } 262 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 263 pa_features = pa_features_207; 264 pa_size = sizeof(pa_features_207); 265 } 266 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 267 pa_features = pa_features_300; 268 pa_size = sizeof(pa_features_300); 269 } 270 if (!pa_features) { 271 return; 272 } 273 274 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 275 /* 276 * Note: we keep CI large pages off by default because a 64K capable 277 * guest provisioned with large pages might otherwise try to map a qemu 278 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 279 * even if that qemu runs on a 4k host. 280 * We dd this bit back here if we are confident this is not an issue 281 */ 282 pa_features[3] |= 0x20; 283 } 284 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 285 pa_features[24] |= 0x80; /* Transactional memory support */ 286 } 287 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 288 /* Workaround for broken kernels that attempt (guest) radix 289 * mode when they can't handle it, if they see the radix bit set 290 * in pa-features. So hide it from them. */ 291 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 292 } 293 294 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 295 } 296 297 static hwaddr spapr_node0_size(MachineState *machine) 298 { 299 if (machine->numa_state->num_nodes) { 300 int i; 301 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 302 if (machine->numa_state->nodes[i].node_mem) { 303 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 304 machine->ram_size); 305 } 306 } 307 } 308 return machine->ram_size; 309 } 310 311 static void add_str(GString *s, const gchar *s1) 312 { 313 g_string_append_len(s, s1, strlen(s1) + 1); 314 } 315 316 static int spapr_dt_memory_node(void *fdt, int nodeid, hwaddr start, 317 hwaddr size) 318 { 319 uint32_t associativity[] = { 320 cpu_to_be32(0x4), /* length */ 321 cpu_to_be32(0x0), cpu_to_be32(0x0), 322 cpu_to_be32(0x0), cpu_to_be32(nodeid) 323 }; 324 char mem_name[32]; 325 uint64_t mem_reg_property[2]; 326 int off; 327 328 mem_reg_property[0] = cpu_to_be64(start); 329 mem_reg_property[1] = cpu_to_be64(size); 330 331 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 332 off = fdt_add_subnode(fdt, 0, mem_name); 333 _FDT(off); 334 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 335 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 336 sizeof(mem_reg_property)))); 337 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 338 sizeof(associativity)))); 339 return off; 340 } 341 342 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 343 { 344 MemoryDeviceInfoList *info; 345 346 for (info = list; info; info = info->next) { 347 MemoryDeviceInfo *value = info->value; 348 349 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 350 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 351 352 if (addr >= pcdimm_info->addr && 353 addr < (pcdimm_info->addr + pcdimm_info->size)) { 354 return pcdimm_info->node; 355 } 356 } 357 } 358 359 return -1; 360 } 361 362 struct sPAPRDrconfCellV2 { 363 uint32_t seq_lmbs; 364 uint64_t base_addr; 365 uint32_t drc_index; 366 uint32_t aa_index; 367 uint32_t flags; 368 } QEMU_PACKED; 369 370 typedef struct DrconfCellQueue { 371 struct sPAPRDrconfCellV2 cell; 372 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 373 } DrconfCellQueue; 374 375 static DrconfCellQueue * 376 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 377 uint32_t drc_index, uint32_t aa_index, 378 uint32_t flags) 379 { 380 DrconfCellQueue *elem; 381 382 elem = g_malloc0(sizeof(*elem)); 383 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 384 elem->cell.base_addr = cpu_to_be64(base_addr); 385 elem->cell.drc_index = cpu_to_be32(drc_index); 386 elem->cell.aa_index = cpu_to_be32(aa_index); 387 elem->cell.flags = cpu_to_be32(flags); 388 389 return elem; 390 } 391 392 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 393 int offset, MemoryDeviceInfoList *dimms) 394 { 395 MachineState *machine = MACHINE(spapr); 396 uint8_t *int_buf, *cur_index; 397 int ret; 398 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 399 uint64_t addr, cur_addr, size; 400 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 401 uint64_t mem_end = machine->device_memory->base + 402 memory_region_size(&machine->device_memory->mr); 403 uint32_t node, buf_len, nr_entries = 0; 404 SpaprDrc *drc; 405 DrconfCellQueue *elem, *next; 406 MemoryDeviceInfoList *info; 407 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 408 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 409 410 /* Entry to cover RAM and the gap area */ 411 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 412 SPAPR_LMB_FLAGS_RESERVED | 413 SPAPR_LMB_FLAGS_DRC_INVALID); 414 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 415 nr_entries++; 416 417 cur_addr = machine->device_memory->base; 418 for (info = dimms; info; info = info->next) { 419 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 420 421 addr = di->addr; 422 size = di->size; 423 node = di->node; 424 425 /* 426 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 427 * area is marked hotpluggable in the next iteration for the bigger 428 * chunk including the NVDIMM occupied area. 429 */ 430 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 431 continue; 432 433 /* Entry for hot-pluggable area */ 434 if (cur_addr < addr) { 435 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 436 g_assert(drc); 437 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 438 cur_addr, spapr_drc_index(drc), -1, 0); 439 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 440 nr_entries++; 441 } 442 443 /* Entry for DIMM */ 444 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 445 g_assert(drc); 446 elem = spapr_get_drconf_cell(size / lmb_size, addr, 447 spapr_drc_index(drc), node, 448 (SPAPR_LMB_FLAGS_ASSIGNED | 449 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 450 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 451 nr_entries++; 452 cur_addr = addr + size; 453 } 454 455 /* Entry for remaining hotpluggable area */ 456 if (cur_addr < mem_end) { 457 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 458 g_assert(drc); 459 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 460 cur_addr, spapr_drc_index(drc), -1, 0); 461 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 462 nr_entries++; 463 } 464 465 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 466 int_buf = cur_index = g_malloc0(buf_len); 467 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 468 cur_index += sizeof(nr_entries); 469 470 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 471 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 472 cur_index += sizeof(elem->cell); 473 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 474 g_free(elem); 475 } 476 477 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 478 g_free(int_buf); 479 if (ret < 0) { 480 return -1; 481 } 482 return 0; 483 } 484 485 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 486 int offset, MemoryDeviceInfoList *dimms) 487 { 488 MachineState *machine = MACHINE(spapr); 489 int i, ret; 490 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 491 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 492 uint32_t nr_lmbs = (machine->device_memory->base + 493 memory_region_size(&machine->device_memory->mr)) / 494 lmb_size; 495 uint32_t *int_buf, *cur_index, buf_len; 496 497 /* 498 * Allocate enough buffer size to fit in ibm,dynamic-memory 499 */ 500 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 501 cur_index = int_buf = g_malloc0(buf_len); 502 int_buf[0] = cpu_to_be32(nr_lmbs); 503 cur_index++; 504 for (i = 0; i < nr_lmbs; i++) { 505 uint64_t addr = i * lmb_size; 506 uint32_t *dynamic_memory = cur_index; 507 508 if (i >= device_lmb_start) { 509 SpaprDrc *drc; 510 511 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 512 g_assert(drc); 513 514 dynamic_memory[0] = cpu_to_be32(addr >> 32); 515 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 516 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 517 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 518 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 519 if (memory_region_present(get_system_memory(), addr)) { 520 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 521 } else { 522 dynamic_memory[5] = cpu_to_be32(0); 523 } 524 } else { 525 /* 526 * LMB information for RMA, boot time RAM and gap b/n RAM and 527 * device memory region -- all these are marked as reserved 528 * and as having no valid DRC. 529 */ 530 dynamic_memory[0] = cpu_to_be32(addr >> 32); 531 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 532 dynamic_memory[2] = cpu_to_be32(0); 533 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 534 dynamic_memory[4] = cpu_to_be32(-1); 535 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 536 SPAPR_LMB_FLAGS_DRC_INVALID); 537 } 538 539 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 540 } 541 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 542 g_free(int_buf); 543 if (ret < 0) { 544 return -1; 545 } 546 return 0; 547 } 548 549 /* 550 * Adds ibm,dynamic-reconfiguration-memory node. 551 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 552 * of this device tree node. 553 */ 554 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 555 void *fdt) 556 { 557 MachineState *machine = MACHINE(spapr); 558 int nb_numa_nodes = machine->numa_state->num_nodes; 559 int ret, i, offset; 560 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 561 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 562 cpu_to_be32(lmb_size & 0xffffffff)}; 563 uint32_t *int_buf, *cur_index, buf_len; 564 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 565 MemoryDeviceInfoList *dimms = NULL; 566 567 /* 568 * Don't create the node if there is no device memory 569 */ 570 if (machine->ram_size == machine->maxram_size) { 571 return 0; 572 } 573 574 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 575 576 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 577 sizeof(prop_lmb_size)); 578 if (ret < 0) { 579 return ret; 580 } 581 582 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 583 if (ret < 0) { 584 return ret; 585 } 586 587 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 588 if (ret < 0) { 589 return ret; 590 } 591 592 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 593 dimms = qmp_memory_device_list(); 594 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 595 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 596 } else { 597 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 598 } 599 qapi_free_MemoryDeviceInfoList(dimms); 600 601 if (ret < 0) { 602 return ret; 603 } 604 605 /* ibm,associativity-lookup-arrays */ 606 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 607 cur_index = int_buf = g_malloc0(buf_len); 608 int_buf[0] = cpu_to_be32(nr_nodes); 609 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 610 cur_index += 2; 611 for (i = 0; i < nr_nodes; i++) { 612 uint32_t associativity[] = { 613 cpu_to_be32(0x0), 614 cpu_to_be32(0x0), 615 cpu_to_be32(0x0), 616 cpu_to_be32(i) 617 }; 618 memcpy(cur_index, associativity, sizeof(associativity)); 619 cur_index += 4; 620 } 621 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 622 (cur_index - int_buf) * sizeof(uint32_t)); 623 g_free(int_buf); 624 625 return ret; 626 } 627 628 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 629 { 630 MachineState *machine = MACHINE(spapr); 631 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 632 hwaddr mem_start, node_size; 633 int i, nb_nodes = machine->numa_state->num_nodes; 634 NodeInfo *nodes = machine->numa_state->nodes; 635 636 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 637 if (!nodes[i].node_mem) { 638 continue; 639 } 640 if (mem_start >= machine->ram_size) { 641 node_size = 0; 642 } else { 643 node_size = nodes[i].node_mem; 644 if (node_size > machine->ram_size - mem_start) { 645 node_size = machine->ram_size - mem_start; 646 } 647 } 648 if (!mem_start) { 649 /* spapr_machine_init() checks for rma_size <= node0_size 650 * already */ 651 spapr_dt_memory_node(fdt, i, 0, spapr->rma_size); 652 mem_start += spapr->rma_size; 653 node_size -= spapr->rma_size; 654 } 655 for ( ; node_size; ) { 656 hwaddr sizetmp = pow2floor(node_size); 657 658 /* mem_start != 0 here */ 659 if (ctzl(mem_start) < ctzl(sizetmp)) { 660 sizetmp = 1ULL << ctzl(mem_start); 661 } 662 663 spapr_dt_memory_node(fdt, i, mem_start, sizetmp); 664 node_size -= sizetmp; 665 mem_start += sizetmp; 666 } 667 } 668 669 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 670 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 671 int ret; 672 673 g_assert(smc->dr_lmb_enabled); 674 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 675 if (ret) { 676 return ret; 677 } 678 } 679 680 return 0; 681 } 682 683 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 684 SpaprMachineState *spapr) 685 { 686 MachineState *ms = MACHINE(spapr); 687 PowerPCCPU *cpu = POWERPC_CPU(cs); 688 CPUPPCState *env = &cpu->env; 689 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 690 int index = spapr_get_vcpu_id(cpu); 691 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 692 0xffffffff, 0xffffffff}; 693 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 694 : SPAPR_TIMEBASE_FREQ; 695 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 696 uint32_t page_sizes_prop[64]; 697 size_t page_sizes_prop_size; 698 unsigned int smp_threads = ms->smp.threads; 699 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 700 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 701 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 702 SpaprDrc *drc; 703 int drc_index; 704 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 705 int i; 706 707 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 708 if (drc) { 709 drc_index = spapr_drc_index(drc); 710 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 711 } 712 713 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 714 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 715 716 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 717 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 718 env->dcache_line_size))); 719 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 720 env->dcache_line_size))); 721 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 722 env->icache_line_size))); 723 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 724 env->icache_line_size))); 725 726 if (pcc->l1_dcache_size) { 727 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 728 pcc->l1_dcache_size))); 729 } else { 730 warn_report("Unknown L1 dcache size for cpu"); 731 } 732 if (pcc->l1_icache_size) { 733 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 734 pcc->l1_icache_size))); 735 } else { 736 warn_report("Unknown L1 icache size for cpu"); 737 } 738 739 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 740 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 741 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 742 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 743 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 744 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 745 746 if (env->spr_cb[SPR_PURR].oea_read) { 747 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 748 } 749 if (env->spr_cb[SPR_SPURR].oea_read) { 750 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 751 } 752 753 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 754 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 755 segs, sizeof(segs)))); 756 } 757 758 /* Advertise VSX (vector extensions) if available 759 * 1 == VMX / Altivec available 760 * 2 == VSX available 761 * 762 * Only CPUs for which we create core types in spapr_cpu_core.c 763 * are possible, and all of those have VMX */ 764 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 765 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 766 } else { 767 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 768 } 769 770 /* Advertise DFP (Decimal Floating Point) if available 771 * 0 / no property == no DFP 772 * 1 == DFP available */ 773 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 774 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 775 } 776 777 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 778 sizeof(page_sizes_prop)); 779 if (page_sizes_prop_size) { 780 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 781 page_sizes_prop, page_sizes_prop_size))); 782 } 783 784 spapr_dt_pa_features(spapr, cpu, fdt, offset); 785 786 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 787 cs->cpu_index / vcpus_per_socket))); 788 789 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 790 pft_size_prop, sizeof(pft_size_prop)))); 791 792 if (ms->numa_state->num_nodes > 1) { 793 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 794 } 795 796 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 797 798 if (pcc->radix_page_info) { 799 for (i = 0; i < pcc->radix_page_info->count; i++) { 800 radix_AP_encodings[i] = 801 cpu_to_be32(pcc->radix_page_info->entries[i]); 802 } 803 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 804 radix_AP_encodings, 805 pcc->radix_page_info->count * 806 sizeof(radix_AP_encodings[0])))); 807 } 808 809 /* 810 * We set this property to let the guest know that it can use the large 811 * decrementer and its width in bits. 812 */ 813 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 814 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 815 pcc->lrg_decr_bits))); 816 } 817 818 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 819 { 820 CPUState **rev; 821 CPUState *cs; 822 int n_cpus; 823 int cpus_offset; 824 char *nodename; 825 int i; 826 827 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 828 _FDT(cpus_offset); 829 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 830 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 831 832 /* 833 * We walk the CPUs in reverse order to ensure that CPU DT nodes 834 * created by fdt_add_subnode() end up in the right order in FDT 835 * for the guest kernel the enumerate the CPUs correctly. 836 * 837 * The CPU list cannot be traversed in reverse order, so we need 838 * to do extra work. 839 */ 840 n_cpus = 0; 841 rev = NULL; 842 CPU_FOREACH(cs) { 843 rev = g_renew(CPUState *, rev, n_cpus + 1); 844 rev[n_cpus++] = cs; 845 } 846 847 for (i = n_cpus - 1; i >= 0; i--) { 848 CPUState *cs = rev[i]; 849 PowerPCCPU *cpu = POWERPC_CPU(cs); 850 int index = spapr_get_vcpu_id(cpu); 851 DeviceClass *dc = DEVICE_GET_CLASS(cs); 852 int offset; 853 854 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 855 continue; 856 } 857 858 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 859 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 860 g_free(nodename); 861 _FDT(offset); 862 spapr_dt_cpu(cs, fdt, offset, spapr); 863 } 864 865 g_free(rev); 866 } 867 868 static int spapr_dt_rng(void *fdt) 869 { 870 int node; 871 int ret; 872 873 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 874 if (node <= 0) { 875 return -1; 876 } 877 ret = fdt_setprop_string(fdt, node, "device_type", 878 "ibm,platform-facilities"); 879 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 880 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 881 882 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 883 if (node <= 0) { 884 return -1; 885 } 886 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 887 888 return ret ? -1 : 0; 889 } 890 891 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 892 { 893 MachineState *ms = MACHINE(spapr); 894 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 895 int rtas; 896 GString *hypertas = g_string_sized_new(256); 897 GString *qemu_hypertas = g_string_sized_new(256); 898 uint32_t refpoints[] = { 899 cpu_to_be32(0x4), 900 cpu_to_be32(0x4), 901 cpu_to_be32(0x2), 902 }; 903 uint32_t nr_refpoints = ARRAY_SIZE(refpoints); 904 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 905 memory_region_size(&MACHINE(spapr)->device_memory->mr); 906 uint32_t lrdr_capacity[] = { 907 cpu_to_be32(max_device_addr >> 32), 908 cpu_to_be32(max_device_addr & 0xffffffff), 909 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 910 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 911 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 912 }; 913 uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0); 914 uint32_t maxdomains[] = { 915 cpu_to_be32(4), 916 maxdomain, 917 maxdomain, 918 maxdomain, 919 cpu_to_be32(spapr->gpu_numa_id), 920 }; 921 922 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 923 924 /* hypertas */ 925 add_str(hypertas, "hcall-pft"); 926 add_str(hypertas, "hcall-term"); 927 add_str(hypertas, "hcall-dabr"); 928 add_str(hypertas, "hcall-interrupt"); 929 add_str(hypertas, "hcall-tce"); 930 add_str(hypertas, "hcall-vio"); 931 add_str(hypertas, "hcall-splpar"); 932 add_str(hypertas, "hcall-join"); 933 add_str(hypertas, "hcall-bulk"); 934 add_str(hypertas, "hcall-set-mode"); 935 add_str(hypertas, "hcall-sprg0"); 936 add_str(hypertas, "hcall-copy"); 937 add_str(hypertas, "hcall-debug"); 938 add_str(hypertas, "hcall-vphn"); 939 add_str(qemu_hypertas, "hcall-memop1"); 940 941 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 942 add_str(hypertas, "hcall-multi-tce"); 943 } 944 945 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 946 add_str(hypertas, "hcall-hpt-resize"); 947 } 948 949 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 950 hypertas->str, hypertas->len)); 951 g_string_free(hypertas, TRUE); 952 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 953 qemu_hypertas->str, qemu_hypertas->len)); 954 g_string_free(qemu_hypertas, TRUE); 955 956 if (smc->pre_5_1_assoc_refpoints) { 957 nr_refpoints = 2; 958 } 959 960 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 961 refpoints, nr_refpoints * sizeof(refpoints[0]))); 962 963 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 964 maxdomains, sizeof(maxdomains))); 965 966 /* 967 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 968 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 969 * 970 * The system reset requirements are driven by existing Linux and PowerVM 971 * implementation which (contrary to PAPR) saves r3 in the error log 972 * structure like machine check, so Linux expects to find the saved r3 973 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 974 * does not look at the error value). 975 * 976 * System reset interrupts are not subject to interlock like machine 977 * check, so this memory area could be corrupted if the sreset is 978 * interrupted by a machine check (or vice versa) if it was shared. To 979 * prevent this, system reset uses per-CPU areas for the sreset save 980 * area. A system reset that interrupts a system reset handler could 981 * still overwrite this area, but Linux doesn't try to recover in that 982 * case anyway. 983 * 984 * The extra 8 bytes is required because Linux's FWNMI error log check 985 * is off-by-one. 986 */ 987 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX + 988 ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t))); 989 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 990 RTAS_ERROR_LOG_MAX)); 991 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 992 RTAS_EVENT_SCAN_RATE)); 993 994 g_assert(msi_nonbroken); 995 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 996 997 /* 998 * According to PAPR, rtas ibm,os-term does not guarantee a return 999 * back to the guest cpu. 1000 * 1001 * While an additional ibm,extended-os-term property indicates 1002 * that rtas call return will always occur. Set this property. 1003 */ 1004 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1005 1006 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1007 lrdr_capacity, sizeof(lrdr_capacity))); 1008 1009 spapr_dt_rtas_tokens(fdt, rtas); 1010 } 1011 1012 /* 1013 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 1014 * and the XIVE features that the guest may request and thus the valid 1015 * values for bytes 23..26 of option vector 5: 1016 */ 1017 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 1018 int chosen) 1019 { 1020 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1021 1022 char val[2 * 4] = { 1023 23, 0x00, /* XICS / XIVE mode */ 1024 24, 0x00, /* Hash/Radix, filled in below. */ 1025 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1026 26, 0x40, /* Radix options: GTSE == yes. */ 1027 }; 1028 1029 if (spapr->irq->xics && spapr->irq->xive) { 1030 val[1] = SPAPR_OV5_XIVE_BOTH; 1031 } else if (spapr->irq->xive) { 1032 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1033 } else { 1034 assert(spapr->irq->xics); 1035 val[1] = SPAPR_OV5_XIVE_LEGACY; 1036 } 1037 1038 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1039 first_ppc_cpu->compat_pvr)) { 1040 /* 1041 * If we're in a pre POWER9 compat mode then the guest should 1042 * do hash and use the legacy interrupt mode 1043 */ 1044 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1045 val[3] = 0x00; /* Hash */ 1046 } else if (kvm_enabled()) { 1047 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1048 val[3] = 0x80; /* OV5_MMU_BOTH */ 1049 } else if (kvmppc_has_cap_mmu_radix()) { 1050 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1051 } else { 1052 val[3] = 0x00; /* Hash */ 1053 } 1054 } else { 1055 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1056 val[3] = 0xC0; 1057 } 1058 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1059 val, sizeof(val))); 1060 } 1061 1062 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1063 { 1064 MachineState *machine = MACHINE(spapr); 1065 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1066 int chosen; 1067 1068 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1069 1070 if (reset) { 1071 const char *boot_device = machine->boot_order; 1072 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1073 size_t cb = 0; 1074 char *bootlist = get_boot_devices_list(&cb); 1075 1076 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1077 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1078 machine->kernel_cmdline)); 1079 } 1080 1081 if (spapr->initrd_size) { 1082 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1083 spapr->initrd_base)); 1084 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1085 spapr->initrd_base + spapr->initrd_size)); 1086 } 1087 1088 if (spapr->kernel_size) { 1089 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1090 cpu_to_be64(spapr->kernel_size) }; 1091 1092 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1093 &kprop, sizeof(kprop))); 1094 if (spapr->kernel_le) { 1095 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1096 } 1097 } 1098 if (boot_menu) { 1099 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1100 } 1101 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1102 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1103 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1104 1105 if (cb && bootlist) { 1106 int i; 1107 1108 for (i = 0; i < cb; i++) { 1109 if (bootlist[i] == '\n') { 1110 bootlist[i] = ' '; 1111 } 1112 } 1113 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1114 } 1115 1116 if (boot_device && strlen(boot_device)) { 1117 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1118 } 1119 1120 if (!spapr->has_graphics && stdout_path) { 1121 /* 1122 * "linux,stdout-path" and "stdout" properties are 1123 * deprecated by linux kernel. New platforms should only 1124 * use the "stdout-path" property. Set the new property 1125 * and continue using older property to remain compatible 1126 * with the existing firmware. 1127 */ 1128 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1129 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1130 } 1131 1132 /* 1133 * We can deal with BAR reallocation just fine, advertise it 1134 * to the guest 1135 */ 1136 if (smc->linux_pci_probe) { 1137 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1138 } 1139 1140 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1141 1142 g_free(stdout_path); 1143 g_free(bootlist); 1144 } 1145 1146 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1147 } 1148 1149 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1150 { 1151 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1152 * KVM to work under pHyp with some guest co-operation */ 1153 int hypervisor; 1154 uint8_t hypercall[16]; 1155 1156 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1157 /* indicate KVM hypercall interface */ 1158 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1159 if (kvmppc_has_cap_fixup_hcalls()) { 1160 /* 1161 * Older KVM versions with older guest kernels were broken 1162 * with the magic page, don't allow the guest to map it. 1163 */ 1164 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1165 sizeof(hypercall))) { 1166 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1167 hypercall, sizeof(hypercall))); 1168 } 1169 } 1170 } 1171 1172 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1173 { 1174 MachineState *machine = MACHINE(spapr); 1175 MachineClass *mc = MACHINE_GET_CLASS(machine); 1176 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1177 int ret; 1178 void *fdt; 1179 SpaprPhbState *phb; 1180 char *buf; 1181 1182 fdt = g_malloc0(space); 1183 _FDT((fdt_create_empty_tree(fdt, space))); 1184 1185 /* Root node */ 1186 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1187 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1188 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1189 1190 /* Guest UUID & Name*/ 1191 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1192 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1193 if (qemu_uuid_set) { 1194 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1195 } 1196 g_free(buf); 1197 1198 if (qemu_get_vm_name()) { 1199 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1200 qemu_get_vm_name())); 1201 } 1202 1203 /* Host Model & Serial Number */ 1204 if (spapr->host_model) { 1205 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1206 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1207 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1208 g_free(buf); 1209 } 1210 1211 if (spapr->host_serial) { 1212 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1213 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1214 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1215 g_free(buf); 1216 } 1217 1218 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1219 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1220 1221 /* /interrupt controller */ 1222 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1223 1224 ret = spapr_dt_memory(spapr, fdt); 1225 if (ret < 0) { 1226 error_report("couldn't setup memory nodes in fdt"); 1227 exit(1); 1228 } 1229 1230 /* /vdevice */ 1231 spapr_dt_vdevice(spapr->vio_bus, fdt); 1232 1233 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1234 ret = spapr_dt_rng(fdt); 1235 if (ret < 0) { 1236 error_report("could not set up rng device in the fdt"); 1237 exit(1); 1238 } 1239 } 1240 1241 QLIST_FOREACH(phb, &spapr->phbs, list) { 1242 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1243 if (ret < 0) { 1244 error_report("couldn't setup PCI devices in fdt"); 1245 exit(1); 1246 } 1247 } 1248 1249 spapr_dt_cpus(fdt, spapr); 1250 1251 if (smc->dr_lmb_enabled) { 1252 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1253 } 1254 1255 if (mc->has_hotpluggable_cpus) { 1256 int offset = fdt_path_offset(fdt, "/cpus"); 1257 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1258 if (ret < 0) { 1259 error_report("Couldn't set up CPU DR device tree properties"); 1260 exit(1); 1261 } 1262 } 1263 1264 /* /event-sources */ 1265 spapr_dt_events(spapr, fdt); 1266 1267 /* /rtas */ 1268 spapr_dt_rtas(spapr, fdt); 1269 1270 /* /chosen */ 1271 spapr_dt_chosen(spapr, fdt, reset); 1272 1273 /* /hypervisor */ 1274 if (kvm_enabled()) { 1275 spapr_dt_hypervisor(spapr, fdt); 1276 } 1277 1278 /* Build memory reserve map */ 1279 if (reset) { 1280 if (spapr->kernel_size) { 1281 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1282 spapr->kernel_size))); 1283 } 1284 if (spapr->initrd_size) { 1285 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1286 spapr->initrd_size))); 1287 } 1288 } 1289 1290 if (smc->dr_phb_enabled) { 1291 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); 1292 if (ret < 0) { 1293 error_report("Couldn't set up PHB DR device tree properties"); 1294 exit(1); 1295 } 1296 } 1297 1298 /* NVDIMM devices */ 1299 if (mc->nvdimm_supported) { 1300 spapr_dt_persistent_memory(fdt); 1301 } 1302 1303 return fdt; 1304 } 1305 1306 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1307 { 1308 SpaprMachineState *spapr = opaque; 1309 1310 return (addr & 0x0fffffff) + spapr->kernel_addr; 1311 } 1312 1313 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1314 PowerPCCPU *cpu) 1315 { 1316 CPUPPCState *env = &cpu->env; 1317 1318 /* The TCG path should also be holding the BQL at this point */ 1319 g_assert(qemu_mutex_iothread_locked()); 1320 1321 if (msr_pr) { 1322 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1323 env->gpr[3] = H_PRIVILEGE; 1324 } else { 1325 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1326 } 1327 } 1328 1329 struct LPCRSyncState { 1330 target_ulong value; 1331 target_ulong mask; 1332 }; 1333 1334 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1335 { 1336 struct LPCRSyncState *s = arg.host_ptr; 1337 PowerPCCPU *cpu = POWERPC_CPU(cs); 1338 CPUPPCState *env = &cpu->env; 1339 target_ulong lpcr; 1340 1341 cpu_synchronize_state(cs); 1342 lpcr = env->spr[SPR_LPCR]; 1343 lpcr &= ~s->mask; 1344 lpcr |= s->value; 1345 ppc_store_lpcr(cpu, lpcr); 1346 } 1347 1348 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1349 { 1350 CPUState *cs; 1351 struct LPCRSyncState s = { 1352 .value = value, 1353 .mask = mask 1354 }; 1355 CPU_FOREACH(cs) { 1356 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1357 } 1358 } 1359 1360 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1361 { 1362 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1363 1364 /* Copy PATE1:GR into PATE0:HR */ 1365 entry->dw0 = spapr->patb_entry & PATE0_HR; 1366 entry->dw1 = spapr->patb_entry; 1367 } 1368 1369 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1370 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1371 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1372 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1373 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1374 1375 /* 1376 * Get the fd to access the kernel htab, re-opening it if necessary 1377 */ 1378 static int get_htab_fd(SpaprMachineState *spapr) 1379 { 1380 Error *local_err = NULL; 1381 1382 if (spapr->htab_fd >= 0) { 1383 return spapr->htab_fd; 1384 } 1385 1386 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1387 if (spapr->htab_fd < 0) { 1388 error_report_err(local_err); 1389 } 1390 1391 return spapr->htab_fd; 1392 } 1393 1394 void close_htab_fd(SpaprMachineState *spapr) 1395 { 1396 if (spapr->htab_fd >= 0) { 1397 close(spapr->htab_fd); 1398 } 1399 spapr->htab_fd = -1; 1400 } 1401 1402 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1403 { 1404 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1405 1406 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1407 } 1408 1409 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1410 { 1411 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1412 1413 assert(kvm_enabled()); 1414 1415 if (!spapr->htab) { 1416 return 0; 1417 } 1418 1419 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1420 } 1421 1422 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1423 hwaddr ptex, int n) 1424 { 1425 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1426 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1427 1428 if (!spapr->htab) { 1429 /* 1430 * HTAB is controlled by KVM. Fetch into temporary buffer 1431 */ 1432 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1433 kvmppc_read_hptes(hptes, ptex, n); 1434 return hptes; 1435 } 1436 1437 /* 1438 * HTAB is controlled by QEMU. Just point to the internally 1439 * accessible PTEG. 1440 */ 1441 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1442 } 1443 1444 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1445 const ppc_hash_pte64_t *hptes, 1446 hwaddr ptex, int n) 1447 { 1448 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1449 1450 if (!spapr->htab) { 1451 g_free((void *)hptes); 1452 } 1453 1454 /* Nothing to do for qemu managed HPT */ 1455 } 1456 1457 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1458 uint64_t pte0, uint64_t pte1) 1459 { 1460 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1461 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1462 1463 if (!spapr->htab) { 1464 kvmppc_write_hpte(ptex, pte0, pte1); 1465 } else { 1466 if (pte0 & HPTE64_V_VALID) { 1467 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1468 /* 1469 * When setting valid, we write PTE1 first. This ensures 1470 * proper synchronization with the reading code in 1471 * ppc_hash64_pteg_search() 1472 */ 1473 smp_wmb(); 1474 stq_p(spapr->htab + offset, pte0); 1475 } else { 1476 stq_p(spapr->htab + offset, pte0); 1477 /* 1478 * When clearing it we set PTE0 first. This ensures proper 1479 * synchronization with the reading code in 1480 * ppc_hash64_pteg_search() 1481 */ 1482 smp_wmb(); 1483 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1484 } 1485 } 1486 } 1487 1488 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1489 uint64_t pte1) 1490 { 1491 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1492 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1493 1494 if (!spapr->htab) { 1495 /* There should always be a hash table when this is called */ 1496 error_report("spapr_hpte_set_c called with no hash table !"); 1497 return; 1498 } 1499 1500 /* The HW performs a non-atomic byte update */ 1501 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1502 } 1503 1504 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1505 uint64_t pte1) 1506 { 1507 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1508 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1509 1510 if (!spapr->htab) { 1511 /* There should always be a hash table when this is called */ 1512 error_report("spapr_hpte_set_r called with no hash table !"); 1513 return; 1514 } 1515 1516 /* The HW performs a non-atomic byte update */ 1517 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1518 } 1519 1520 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1521 { 1522 int shift; 1523 1524 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1525 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1526 * that's much more than is needed for Linux guests */ 1527 shift = ctz64(pow2ceil(ramsize)) - 7; 1528 shift = MAX(shift, 18); /* Minimum architected size */ 1529 shift = MIN(shift, 46); /* Maximum architected size */ 1530 return shift; 1531 } 1532 1533 void spapr_free_hpt(SpaprMachineState *spapr) 1534 { 1535 g_free(spapr->htab); 1536 spapr->htab = NULL; 1537 spapr->htab_shift = 0; 1538 close_htab_fd(spapr); 1539 } 1540 1541 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 1542 Error **errp) 1543 { 1544 long rc; 1545 1546 /* Clean up any HPT info from a previous boot */ 1547 spapr_free_hpt(spapr); 1548 1549 rc = kvmppc_reset_htab(shift); 1550 if (rc < 0) { 1551 /* kernel-side HPT needed, but couldn't allocate one */ 1552 error_setg_errno(errp, errno, 1553 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1554 shift); 1555 /* This is almost certainly fatal, but if the caller really 1556 * wants to carry on with shift == 0, it's welcome to try */ 1557 } else if (rc > 0) { 1558 /* kernel-side HPT allocated */ 1559 if (rc != shift) { 1560 error_setg(errp, 1561 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1562 shift, rc); 1563 } 1564 1565 spapr->htab_shift = shift; 1566 spapr->htab = NULL; 1567 } else { 1568 /* kernel-side HPT not needed, allocate in userspace instead */ 1569 size_t size = 1ULL << shift; 1570 int i; 1571 1572 spapr->htab = qemu_memalign(size, size); 1573 if (!spapr->htab) { 1574 error_setg_errno(errp, errno, 1575 "Could not allocate HPT of order %d", shift); 1576 return; 1577 } 1578 1579 memset(spapr->htab, 0, size); 1580 spapr->htab_shift = shift; 1581 1582 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1583 DIRTY_HPTE(HPTE(spapr->htab, i)); 1584 } 1585 } 1586 /* We're setting up a hash table, so that means we're not radix */ 1587 spapr->patb_entry = 0; 1588 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1589 } 1590 1591 void spapr_setup_hpt(SpaprMachineState *spapr) 1592 { 1593 int hpt_shift; 1594 1595 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1596 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1597 } else { 1598 uint64_t current_ram_size; 1599 1600 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1601 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1602 } 1603 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1604 1605 if (kvm_enabled()) { 1606 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1607 1608 /* Check our RMA fits in the possible VRMA */ 1609 if (vrma_limit < spapr->rma_size) { 1610 error_report("Unable to create %" HWADDR_PRIu 1611 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1612 spapr->rma_size / MiB, vrma_limit / MiB); 1613 exit(EXIT_FAILURE); 1614 } 1615 } 1616 } 1617 1618 static int spapr_reset_drcs(Object *child, void *opaque) 1619 { 1620 SpaprDrc *drc = 1621 (SpaprDrc *) object_dynamic_cast(child, 1622 TYPE_SPAPR_DR_CONNECTOR); 1623 1624 if (drc) { 1625 spapr_drc_reset(drc); 1626 } 1627 1628 return 0; 1629 } 1630 1631 static void spapr_machine_reset(MachineState *machine) 1632 { 1633 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1634 PowerPCCPU *first_ppc_cpu; 1635 hwaddr fdt_addr; 1636 void *fdt; 1637 int rc; 1638 1639 kvmppc_svm_off(&error_fatal); 1640 spapr_caps_apply(spapr); 1641 1642 first_ppc_cpu = POWERPC_CPU(first_cpu); 1643 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1644 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1645 spapr->max_compat_pvr)) { 1646 /* 1647 * If using KVM with radix mode available, VCPUs can be started 1648 * without a HPT because KVM will start them in radix mode. 1649 * Set the GR bit in PATE so that we know there is no HPT. 1650 */ 1651 spapr->patb_entry = PATE1_GR; 1652 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1653 } else { 1654 spapr_setup_hpt(spapr); 1655 } 1656 1657 qemu_devices_reset(); 1658 1659 spapr_ovec_cleanup(spapr->ov5_cas); 1660 spapr->ov5_cas = spapr_ovec_new(); 1661 1662 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1663 1664 /* 1665 * This is fixing some of the default configuration of the XIVE 1666 * devices. To be called after the reset of the machine devices. 1667 */ 1668 spapr_irq_reset(spapr, &error_fatal); 1669 1670 /* 1671 * There is no CAS under qtest. Simulate one to please the code that 1672 * depends on spapr->ov5_cas. This is especially needed to test device 1673 * unplug, so we do that before resetting the DRCs. 1674 */ 1675 if (qtest_enabled()) { 1676 spapr_ovec_cleanup(spapr->ov5_cas); 1677 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1678 } 1679 1680 /* DRC reset may cause a device to be unplugged. This will cause troubles 1681 * if this device is used by another device (eg, a running vhost backend 1682 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1683 * situations, we reset DRCs after all devices have been reset. 1684 */ 1685 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1686 1687 spapr_clear_pending_events(spapr); 1688 1689 /* 1690 * We place the device tree and RTAS just below either the top of the RMA, 1691 * or just below 2GB, whichever is lower, so that it can be 1692 * processed with 32-bit real mode code if necessary 1693 */ 1694 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1695 1696 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1697 1698 rc = fdt_pack(fdt); 1699 1700 /* Should only fail if we've built a corrupted tree */ 1701 assert(rc == 0); 1702 1703 /* Load the fdt */ 1704 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1705 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1706 g_free(spapr->fdt_blob); 1707 spapr->fdt_size = fdt_totalsize(fdt); 1708 spapr->fdt_initial_size = spapr->fdt_size; 1709 spapr->fdt_blob = fdt; 1710 1711 /* Set up the entry state */ 1712 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); 1713 first_ppc_cpu->env.gpr[5] = 0; 1714 1715 spapr->fwnmi_system_reset_addr = -1; 1716 spapr->fwnmi_machine_check_addr = -1; 1717 spapr->fwnmi_machine_check_interlock = -1; 1718 1719 /* Signal all vCPUs waiting on this condition */ 1720 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1721 1722 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1723 } 1724 1725 static void spapr_create_nvram(SpaprMachineState *spapr) 1726 { 1727 DeviceState *dev = qdev_new("spapr-nvram"); 1728 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1729 1730 if (dinfo) { 1731 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1732 &error_fatal); 1733 } 1734 1735 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1736 1737 spapr->nvram = (struct SpaprNvram *)dev; 1738 } 1739 1740 static void spapr_rtc_create(SpaprMachineState *spapr) 1741 { 1742 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1743 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1744 &error_fatal, NULL); 1745 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1746 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1747 "date"); 1748 } 1749 1750 /* Returns whether we want to use VGA or not */ 1751 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1752 { 1753 switch (vga_interface_type) { 1754 case VGA_NONE: 1755 return false; 1756 case VGA_DEVICE: 1757 return true; 1758 case VGA_STD: 1759 case VGA_VIRTIO: 1760 case VGA_CIRRUS: 1761 return pci_vga_init(pci_bus) != NULL; 1762 default: 1763 error_setg(errp, 1764 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1765 return false; 1766 } 1767 } 1768 1769 static int spapr_pre_load(void *opaque) 1770 { 1771 int rc; 1772 1773 rc = spapr_caps_pre_load(opaque); 1774 if (rc) { 1775 return rc; 1776 } 1777 1778 return 0; 1779 } 1780 1781 static int spapr_post_load(void *opaque, int version_id) 1782 { 1783 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1784 int err = 0; 1785 1786 err = spapr_caps_post_migration(spapr); 1787 if (err) { 1788 return err; 1789 } 1790 1791 /* 1792 * In earlier versions, there was no separate qdev for the PAPR 1793 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1794 * So when migrating from those versions, poke the incoming offset 1795 * value into the RTC device 1796 */ 1797 if (version_id < 3) { 1798 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1799 if (err) { 1800 return err; 1801 } 1802 } 1803 1804 if (kvm_enabled() && spapr->patb_entry) { 1805 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1806 bool radix = !!(spapr->patb_entry & PATE1_GR); 1807 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1808 1809 /* 1810 * Update LPCR:HR and UPRT as they may not be set properly in 1811 * the stream 1812 */ 1813 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1814 LPCR_HR | LPCR_UPRT); 1815 1816 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1817 if (err) { 1818 error_report("Process table config unsupported by the host"); 1819 return -EINVAL; 1820 } 1821 } 1822 1823 err = spapr_irq_post_load(spapr, version_id); 1824 if (err) { 1825 return err; 1826 } 1827 1828 return err; 1829 } 1830 1831 static int spapr_pre_save(void *opaque) 1832 { 1833 int rc; 1834 1835 rc = spapr_caps_pre_save(opaque); 1836 if (rc) { 1837 return rc; 1838 } 1839 1840 return 0; 1841 } 1842 1843 static bool version_before_3(void *opaque, int version_id) 1844 { 1845 return version_id < 3; 1846 } 1847 1848 static bool spapr_pending_events_needed(void *opaque) 1849 { 1850 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1851 return !QTAILQ_EMPTY(&spapr->pending_events); 1852 } 1853 1854 static const VMStateDescription vmstate_spapr_event_entry = { 1855 .name = "spapr_event_log_entry", 1856 .version_id = 1, 1857 .minimum_version_id = 1, 1858 .fields = (VMStateField[]) { 1859 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1860 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1861 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1862 NULL, extended_length), 1863 VMSTATE_END_OF_LIST() 1864 }, 1865 }; 1866 1867 static const VMStateDescription vmstate_spapr_pending_events = { 1868 .name = "spapr_pending_events", 1869 .version_id = 1, 1870 .minimum_version_id = 1, 1871 .needed = spapr_pending_events_needed, 1872 .fields = (VMStateField[]) { 1873 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1874 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1875 VMSTATE_END_OF_LIST() 1876 }, 1877 }; 1878 1879 static bool spapr_ov5_cas_needed(void *opaque) 1880 { 1881 SpaprMachineState *spapr = opaque; 1882 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1883 bool cas_needed; 1884 1885 /* Prior to the introduction of SpaprOptionVector, we had two option 1886 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1887 * Both of these options encode machine topology into the device-tree 1888 * in such a way that the now-booted OS should still be able to interact 1889 * appropriately with QEMU regardless of what options were actually 1890 * negotiatied on the source side. 1891 * 1892 * As such, we can avoid migrating the CAS-negotiated options if these 1893 * are the only options available on the current machine/platform. 1894 * Since these are the only options available for pseries-2.7 and 1895 * earlier, this allows us to maintain old->new/new->old migration 1896 * compatibility. 1897 * 1898 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1899 * via default pseries-2.8 machines and explicit command-line parameters. 1900 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1901 * of the actual CAS-negotiated values to continue working properly. For 1902 * example, availability of memory unplug depends on knowing whether 1903 * OV5_HP_EVT was negotiated via CAS. 1904 * 1905 * Thus, for any cases where the set of available CAS-negotiatable 1906 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1907 * include the CAS-negotiated options in the migration stream, unless 1908 * if they affect boot time behaviour only. 1909 */ 1910 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1911 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1912 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1913 1914 /* We need extra information if we have any bits outside the mask 1915 * defined above */ 1916 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1917 1918 spapr_ovec_cleanup(ov5_mask); 1919 1920 return cas_needed; 1921 } 1922 1923 static const VMStateDescription vmstate_spapr_ov5_cas = { 1924 .name = "spapr_option_vector_ov5_cas", 1925 .version_id = 1, 1926 .minimum_version_id = 1, 1927 .needed = spapr_ov5_cas_needed, 1928 .fields = (VMStateField[]) { 1929 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1930 vmstate_spapr_ovec, SpaprOptionVector), 1931 VMSTATE_END_OF_LIST() 1932 }, 1933 }; 1934 1935 static bool spapr_patb_entry_needed(void *opaque) 1936 { 1937 SpaprMachineState *spapr = opaque; 1938 1939 return !!spapr->patb_entry; 1940 } 1941 1942 static const VMStateDescription vmstate_spapr_patb_entry = { 1943 .name = "spapr_patb_entry", 1944 .version_id = 1, 1945 .minimum_version_id = 1, 1946 .needed = spapr_patb_entry_needed, 1947 .fields = (VMStateField[]) { 1948 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1949 VMSTATE_END_OF_LIST() 1950 }, 1951 }; 1952 1953 static bool spapr_irq_map_needed(void *opaque) 1954 { 1955 SpaprMachineState *spapr = opaque; 1956 1957 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1958 } 1959 1960 static const VMStateDescription vmstate_spapr_irq_map = { 1961 .name = "spapr_irq_map", 1962 .version_id = 1, 1963 .minimum_version_id = 1, 1964 .needed = spapr_irq_map_needed, 1965 .fields = (VMStateField[]) { 1966 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1967 VMSTATE_END_OF_LIST() 1968 }, 1969 }; 1970 1971 static bool spapr_dtb_needed(void *opaque) 1972 { 1973 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1974 1975 return smc->update_dt_enabled; 1976 } 1977 1978 static int spapr_dtb_pre_load(void *opaque) 1979 { 1980 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1981 1982 g_free(spapr->fdt_blob); 1983 spapr->fdt_blob = NULL; 1984 spapr->fdt_size = 0; 1985 1986 return 0; 1987 } 1988 1989 static const VMStateDescription vmstate_spapr_dtb = { 1990 .name = "spapr_dtb", 1991 .version_id = 1, 1992 .minimum_version_id = 1, 1993 .needed = spapr_dtb_needed, 1994 .pre_load = spapr_dtb_pre_load, 1995 .fields = (VMStateField[]) { 1996 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1997 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1998 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1999 fdt_size), 2000 VMSTATE_END_OF_LIST() 2001 }, 2002 }; 2003 2004 static bool spapr_fwnmi_needed(void *opaque) 2005 { 2006 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2007 2008 return spapr->fwnmi_machine_check_addr != -1; 2009 } 2010 2011 static int spapr_fwnmi_pre_save(void *opaque) 2012 { 2013 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2014 2015 /* 2016 * Check if machine check handling is in progress and print a 2017 * warning message. 2018 */ 2019 if (spapr->fwnmi_machine_check_interlock != -1) { 2020 warn_report("A machine check is being handled during migration. The" 2021 "handler may run and log hardware error on the destination"); 2022 } 2023 2024 return 0; 2025 } 2026 2027 static const VMStateDescription vmstate_spapr_fwnmi = { 2028 .name = "spapr_fwnmi", 2029 .version_id = 1, 2030 .minimum_version_id = 1, 2031 .needed = spapr_fwnmi_needed, 2032 .pre_save = spapr_fwnmi_pre_save, 2033 .fields = (VMStateField[]) { 2034 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 2035 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 2036 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 2037 VMSTATE_END_OF_LIST() 2038 }, 2039 }; 2040 2041 static const VMStateDescription vmstate_spapr = { 2042 .name = "spapr", 2043 .version_id = 3, 2044 .minimum_version_id = 1, 2045 .pre_load = spapr_pre_load, 2046 .post_load = spapr_post_load, 2047 .pre_save = spapr_pre_save, 2048 .fields = (VMStateField[]) { 2049 /* used to be @next_irq */ 2050 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2051 2052 /* RTC offset */ 2053 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2054 2055 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2056 VMSTATE_END_OF_LIST() 2057 }, 2058 .subsections = (const VMStateDescription*[]) { 2059 &vmstate_spapr_ov5_cas, 2060 &vmstate_spapr_patb_entry, 2061 &vmstate_spapr_pending_events, 2062 &vmstate_spapr_cap_htm, 2063 &vmstate_spapr_cap_vsx, 2064 &vmstate_spapr_cap_dfp, 2065 &vmstate_spapr_cap_cfpc, 2066 &vmstate_spapr_cap_sbbc, 2067 &vmstate_spapr_cap_ibs, 2068 &vmstate_spapr_cap_hpt_maxpagesize, 2069 &vmstate_spapr_irq_map, 2070 &vmstate_spapr_cap_nested_kvm_hv, 2071 &vmstate_spapr_dtb, 2072 &vmstate_spapr_cap_large_decr, 2073 &vmstate_spapr_cap_ccf_assist, 2074 &vmstate_spapr_cap_fwnmi, 2075 &vmstate_spapr_fwnmi, 2076 NULL 2077 } 2078 }; 2079 2080 static int htab_save_setup(QEMUFile *f, void *opaque) 2081 { 2082 SpaprMachineState *spapr = opaque; 2083 2084 /* "Iteration" header */ 2085 if (!spapr->htab_shift) { 2086 qemu_put_be32(f, -1); 2087 } else { 2088 qemu_put_be32(f, spapr->htab_shift); 2089 } 2090 2091 if (spapr->htab) { 2092 spapr->htab_save_index = 0; 2093 spapr->htab_first_pass = true; 2094 } else { 2095 if (spapr->htab_shift) { 2096 assert(kvm_enabled()); 2097 } 2098 } 2099 2100 2101 return 0; 2102 } 2103 2104 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2105 int chunkstart, int n_valid, int n_invalid) 2106 { 2107 qemu_put_be32(f, chunkstart); 2108 qemu_put_be16(f, n_valid); 2109 qemu_put_be16(f, n_invalid); 2110 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2111 HASH_PTE_SIZE_64 * n_valid); 2112 } 2113 2114 static void htab_save_end_marker(QEMUFile *f) 2115 { 2116 qemu_put_be32(f, 0); 2117 qemu_put_be16(f, 0); 2118 qemu_put_be16(f, 0); 2119 } 2120 2121 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2122 int64_t max_ns) 2123 { 2124 bool has_timeout = max_ns != -1; 2125 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2126 int index = spapr->htab_save_index; 2127 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2128 2129 assert(spapr->htab_first_pass); 2130 2131 do { 2132 int chunkstart; 2133 2134 /* Consume invalid HPTEs */ 2135 while ((index < htabslots) 2136 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2137 CLEAN_HPTE(HPTE(spapr->htab, index)); 2138 index++; 2139 } 2140 2141 /* Consume valid HPTEs */ 2142 chunkstart = index; 2143 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2144 && HPTE_VALID(HPTE(spapr->htab, index))) { 2145 CLEAN_HPTE(HPTE(spapr->htab, index)); 2146 index++; 2147 } 2148 2149 if (index > chunkstart) { 2150 int n_valid = index - chunkstart; 2151 2152 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2153 2154 if (has_timeout && 2155 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2156 break; 2157 } 2158 } 2159 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2160 2161 if (index >= htabslots) { 2162 assert(index == htabslots); 2163 index = 0; 2164 spapr->htab_first_pass = false; 2165 } 2166 spapr->htab_save_index = index; 2167 } 2168 2169 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2170 int64_t max_ns) 2171 { 2172 bool final = max_ns < 0; 2173 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2174 int examined = 0, sent = 0; 2175 int index = spapr->htab_save_index; 2176 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2177 2178 assert(!spapr->htab_first_pass); 2179 2180 do { 2181 int chunkstart, invalidstart; 2182 2183 /* Consume non-dirty HPTEs */ 2184 while ((index < htabslots) 2185 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2186 index++; 2187 examined++; 2188 } 2189 2190 chunkstart = index; 2191 /* Consume valid dirty HPTEs */ 2192 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2193 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2194 && HPTE_VALID(HPTE(spapr->htab, index))) { 2195 CLEAN_HPTE(HPTE(spapr->htab, index)); 2196 index++; 2197 examined++; 2198 } 2199 2200 invalidstart = index; 2201 /* Consume invalid dirty HPTEs */ 2202 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2203 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2204 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2205 CLEAN_HPTE(HPTE(spapr->htab, index)); 2206 index++; 2207 examined++; 2208 } 2209 2210 if (index > chunkstart) { 2211 int n_valid = invalidstart - chunkstart; 2212 int n_invalid = index - invalidstart; 2213 2214 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2215 sent += index - chunkstart; 2216 2217 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2218 break; 2219 } 2220 } 2221 2222 if (examined >= htabslots) { 2223 break; 2224 } 2225 2226 if (index >= htabslots) { 2227 assert(index == htabslots); 2228 index = 0; 2229 } 2230 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2231 2232 if (index >= htabslots) { 2233 assert(index == htabslots); 2234 index = 0; 2235 } 2236 2237 spapr->htab_save_index = index; 2238 2239 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2240 } 2241 2242 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2243 #define MAX_KVM_BUF_SIZE 2048 2244 2245 static int htab_save_iterate(QEMUFile *f, void *opaque) 2246 { 2247 SpaprMachineState *spapr = opaque; 2248 int fd; 2249 int rc = 0; 2250 2251 /* Iteration header */ 2252 if (!spapr->htab_shift) { 2253 qemu_put_be32(f, -1); 2254 return 1; 2255 } else { 2256 qemu_put_be32(f, 0); 2257 } 2258 2259 if (!spapr->htab) { 2260 assert(kvm_enabled()); 2261 2262 fd = get_htab_fd(spapr); 2263 if (fd < 0) { 2264 return fd; 2265 } 2266 2267 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2268 if (rc < 0) { 2269 return rc; 2270 } 2271 } else if (spapr->htab_first_pass) { 2272 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2273 } else { 2274 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2275 } 2276 2277 htab_save_end_marker(f); 2278 2279 return rc; 2280 } 2281 2282 static int htab_save_complete(QEMUFile *f, void *opaque) 2283 { 2284 SpaprMachineState *spapr = opaque; 2285 int fd; 2286 2287 /* Iteration header */ 2288 if (!spapr->htab_shift) { 2289 qemu_put_be32(f, -1); 2290 return 0; 2291 } else { 2292 qemu_put_be32(f, 0); 2293 } 2294 2295 if (!spapr->htab) { 2296 int rc; 2297 2298 assert(kvm_enabled()); 2299 2300 fd = get_htab_fd(spapr); 2301 if (fd < 0) { 2302 return fd; 2303 } 2304 2305 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2306 if (rc < 0) { 2307 return rc; 2308 } 2309 } else { 2310 if (spapr->htab_first_pass) { 2311 htab_save_first_pass(f, spapr, -1); 2312 } 2313 htab_save_later_pass(f, spapr, -1); 2314 } 2315 2316 /* End marker */ 2317 htab_save_end_marker(f); 2318 2319 return 0; 2320 } 2321 2322 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2323 { 2324 SpaprMachineState *spapr = opaque; 2325 uint32_t section_hdr; 2326 int fd = -1; 2327 Error *local_err = NULL; 2328 2329 if (version_id < 1 || version_id > 1) { 2330 error_report("htab_load() bad version"); 2331 return -EINVAL; 2332 } 2333 2334 section_hdr = qemu_get_be32(f); 2335 2336 if (section_hdr == -1) { 2337 spapr_free_hpt(spapr); 2338 return 0; 2339 } 2340 2341 if (section_hdr) { 2342 /* First section gives the htab size */ 2343 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2344 if (local_err) { 2345 error_report_err(local_err); 2346 return -EINVAL; 2347 } 2348 return 0; 2349 } 2350 2351 if (!spapr->htab) { 2352 assert(kvm_enabled()); 2353 2354 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2355 if (fd < 0) { 2356 error_report_err(local_err); 2357 return fd; 2358 } 2359 } 2360 2361 while (true) { 2362 uint32_t index; 2363 uint16_t n_valid, n_invalid; 2364 2365 index = qemu_get_be32(f); 2366 n_valid = qemu_get_be16(f); 2367 n_invalid = qemu_get_be16(f); 2368 2369 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2370 /* End of Stream */ 2371 break; 2372 } 2373 2374 if ((index + n_valid + n_invalid) > 2375 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2376 /* Bad index in stream */ 2377 error_report( 2378 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2379 index, n_valid, n_invalid, spapr->htab_shift); 2380 return -EINVAL; 2381 } 2382 2383 if (spapr->htab) { 2384 if (n_valid) { 2385 qemu_get_buffer(f, HPTE(spapr->htab, index), 2386 HASH_PTE_SIZE_64 * n_valid); 2387 } 2388 if (n_invalid) { 2389 memset(HPTE(spapr->htab, index + n_valid), 0, 2390 HASH_PTE_SIZE_64 * n_invalid); 2391 } 2392 } else { 2393 int rc; 2394 2395 assert(fd >= 0); 2396 2397 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2398 if (rc < 0) { 2399 return rc; 2400 } 2401 } 2402 } 2403 2404 if (!spapr->htab) { 2405 assert(fd >= 0); 2406 close(fd); 2407 } 2408 2409 return 0; 2410 } 2411 2412 static void htab_save_cleanup(void *opaque) 2413 { 2414 SpaprMachineState *spapr = opaque; 2415 2416 close_htab_fd(spapr); 2417 } 2418 2419 static SaveVMHandlers savevm_htab_handlers = { 2420 .save_setup = htab_save_setup, 2421 .save_live_iterate = htab_save_iterate, 2422 .save_live_complete_precopy = htab_save_complete, 2423 .save_cleanup = htab_save_cleanup, 2424 .load_state = htab_load, 2425 }; 2426 2427 static void spapr_boot_set(void *opaque, const char *boot_device, 2428 Error **errp) 2429 { 2430 MachineState *machine = MACHINE(opaque); 2431 machine->boot_order = g_strdup(boot_device); 2432 } 2433 2434 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2435 { 2436 MachineState *machine = MACHINE(spapr); 2437 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2438 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2439 int i; 2440 2441 for (i = 0; i < nr_lmbs; i++) { 2442 uint64_t addr; 2443 2444 addr = i * lmb_size + machine->device_memory->base; 2445 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2446 addr / lmb_size); 2447 } 2448 } 2449 2450 /* 2451 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2452 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2453 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2454 */ 2455 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2456 { 2457 int i; 2458 2459 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2460 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2461 " is not aligned to %" PRIu64 " MiB", 2462 machine->ram_size, 2463 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2464 return; 2465 } 2466 2467 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2468 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2469 " is not aligned to %" PRIu64 " MiB", 2470 machine->ram_size, 2471 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2472 return; 2473 } 2474 2475 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2476 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2477 error_setg(errp, 2478 "Node %d memory size 0x%" PRIx64 2479 " is not aligned to %" PRIu64 " MiB", 2480 i, machine->numa_state->nodes[i].node_mem, 2481 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2482 return; 2483 } 2484 } 2485 } 2486 2487 /* find cpu slot in machine->possible_cpus by core_id */ 2488 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2489 { 2490 int index = id / ms->smp.threads; 2491 2492 if (index >= ms->possible_cpus->len) { 2493 return NULL; 2494 } 2495 if (idx) { 2496 *idx = index; 2497 } 2498 return &ms->possible_cpus->cpus[index]; 2499 } 2500 2501 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2502 { 2503 MachineState *ms = MACHINE(spapr); 2504 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2505 Error *local_err = NULL; 2506 bool vsmt_user = !!spapr->vsmt; 2507 int kvm_smt = kvmppc_smt_threads(); 2508 int ret; 2509 unsigned int smp_threads = ms->smp.threads; 2510 2511 if (!kvm_enabled() && (smp_threads > 1)) { 2512 error_setg(errp, "TCG cannot support more than 1 thread/core " 2513 "on a pseries machine"); 2514 return; 2515 } 2516 if (!is_power_of_2(smp_threads)) { 2517 error_setg(errp, "Cannot support %d threads/core on a pseries " 2518 "machine because it must be a power of 2", smp_threads); 2519 return; 2520 } 2521 2522 /* Detemine the VSMT mode to use: */ 2523 if (vsmt_user) { 2524 if (spapr->vsmt < smp_threads) { 2525 error_setg(errp, "Cannot support VSMT mode %d" 2526 " because it must be >= threads/core (%d)", 2527 spapr->vsmt, smp_threads); 2528 return; 2529 } 2530 /* In this case, spapr->vsmt has been set by the command line */ 2531 } else if (!smc->smp_threads_vsmt) { 2532 /* 2533 * Default VSMT value is tricky, because we need it to be as 2534 * consistent as possible (for migration), but this requires 2535 * changing it for at least some existing cases. We pick 8 as 2536 * the value that we'd get with KVM on POWER8, the 2537 * overwhelmingly common case in production systems. 2538 */ 2539 spapr->vsmt = MAX(8, smp_threads); 2540 } else { 2541 spapr->vsmt = smp_threads; 2542 } 2543 2544 /* KVM: If necessary, set the SMT mode: */ 2545 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2546 ret = kvmppc_set_smt_threads(spapr->vsmt); 2547 if (ret) { 2548 /* Looks like KVM isn't able to change VSMT mode */ 2549 error_setg(&local_err, 2550 "Failed to set KVM's VSMT mode to %d (errno %d)", 2551 spapr->vsmt, ret); 2552 /* We can live with that if the default one is big enough 2553 * for the number of threads, and a submultiple of the one 2554 * we want. In this case we'll waste some vcpu ids, but 2555 * behaviour will be correct */ 2556 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2557 warn_report_err(local_err); 2558 } else { 2559 if (!vsmt_user) { 2560 error_append_hint(&local_err, 2561 "On PPC, a VM with %d threads/core" 2562 " on a host with %d threads/core" 2563 " requires the use of VSMT mode %d.\n", 2564 smp_threads, kvm_smt, spapr->vsmt); 2565 } 2566 kvmppc_error_append_smt_possible_hint(&local_err); 2567 error_propagate(errp, local_err); 2568 } 2569 } 2570 } 2571 /* else TCG: nothing to do currently */ 2572 } 2573 2574 static void spapr_init_cpus(SpaprMachineState *spapr) 2575 { 2576 MachineState *machine = MACHINE(spapr); 2577 MachineClass *mc = MACHINE_GET_CLASS(machine); 2578 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2579 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2580 const CPUArchIdList *possible_cpus; 2581 unsigned int smp_cpus = machine->smp.cpus; 2582 unsigned int smp_threads = machine->smp.threads; 2583 unsigned int max_cpus = machine->smp.max_cpus; 2584 int boot_cores_nr = smp_cpus / smp_threads; 2585 int i; 2586 2587 possible_cpus = mc->possible_cpu_arch_ids(machine); 2588 if (mc->has_hotpluggable_cpus) { 2589 if (smp_cpus % smp_threads) { 2590 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2591 smp_cpus, smp_threads); 2592 exit(1); 2593 } 2594 if (max_cpus % smp_threads) { 2595 error_report("max_cpus (%u) must be multiple of threads (%u)", 2596 max_cpus, smp_threads); 2597 exit(1); 2598 } 2599 } else { 2600 if (max_cpus != smp_cpus) { 2601 error_report("This machine version does not support CPU hotplug"); 2602 exit(1); 2603 } 2604 boot_cores_nr = possible_cpus->len; 2605 } 2606 2607 if (smc->pre_2_10_has_unused_icps) { 2608 int i; 2609 2610 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2611 /* Dummy entries get deregistered when real ICPState objects 2612 * are registered during CPU core hotplug. 2613 */ 2614 pre_2_10_vmstate_register_dummy_icp(i); 2615 } 2616 } 2617 2618 for (i = 0; i < possible_cpus->len; i++) { 2619 int core_id = i * smp_threads; 2620 2621 if (mc->has_hotpluggable_cpus) { 2622 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2623 spapr_vcpu_id(spapr, core_id)); 2624 } 2625 2626 if (i < boot_cores_nr) { 2627 Object *core = object_new(type); 2628 int nr_threads = smp_threads; 2629 2630 /* Handle the partially filled core for older machine types */ 2631 if ((i + 1) * smp_threads >= smp_cpus) { 2632 nr_threads = smp_cpus - i * smp_threads; 2633 } 2634 2635 object_property_set_int(core, "nr-threads", nr_threads, 2636 &error_fatal); 2637 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2638 &error_fatal); 2639 qdev_realize(DEVICE(core), NULL, &error_fatal); 2640 2641 object_unref(core); 2642 } 2643 } 2644 } 2645 2646 static PCIHostState *spapr_create_default_phb(void) 2647 { 2648 DeviceState *dev; 2649 2650 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2651 qdev_prop_set_uint32(dev, "index", 0); 2652 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2653 2654 return PCI_HOST_BRIDGE(dev); 2655 } 2656 2657 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2658 { 2659 MachineState *machine = MACHINE(spapr); 2660 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2661 hwaddr rma_size = machine->ram_size; 2662 hwaddr node0_size = spapr_node0_size(machine); 2663 2664 /* RMA has to fit in the first NUMA node */ 2665 rma_size = MIN(rma_size, node0_size); 2666 2667 /* 2668 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2669 * never exceed that 2670 */ 2671 rma_size = MIN(rma_size, 1 * TiB); 2672 2673 /* 2674 * Clamp the RMA size based on machine type. This is for 2675 * migration compatibility with older qemu versions, which limited 2676 * the RMA size for complicated and mostly bad reasons. 2677 */ 2678 if (smc->rma_limit) { 2679 rma_size = MIN(rma_size, smc->rma_limit); 2680 } 2681 2682 if (rma_size < MIN_RMA_SLOF) { 2683 error_setg(errp, 2684 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2685 "ldMiB guest RMA (Real Mode Area memory)", 2686 MIN_RMA_SLOF / MiB); 2687 return 0; 2688 } 2689 2690 return rma_size; 2691 } 2692 2693 /* pSeries LPAR / sPAPR hardware init */ 2694 static void spapr_machine_init(MachineState *machine) 2695 { 2696 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2697 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2698 MachineClass *mc = MACHINE_GET_CLASS(machine); 2699 const char *kernel_filename = machine->kernel_filename; 2700 const char *initrd_filename = machine->initrd_filename; 2701 PCIHostState *phb; 2702 int i; 2703 MemoryRegion *sysmem = get_system_memory(); 2704 long load_limit, fw_size; 2705 char *filename; 2706 Error *resize_hpt_err = NULL; 2707 2708 msi_nonbroken = true; 2709 2710 QLIST_INIT(&spapr->phbs); 2711 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2712 2713 /* Determine capabilities to run with */ 2714 spapr_caps_init(spapr); 2715 2716 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2717 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2718 /* 2719 * If the user explicitly requested a mode we should either 2720 * supply it, or fail completely (which we do below). But if 2721 * it's not set explicitly, we reset our mode to something 2722 * that works 2723 */ 2724 if (resize_hpt_err) { 2725 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2726 error_free(resize_hpt_err); 2727 resize_hpt_err = NULL; 2728 } else { 2729 spapr->resize_hpt = smc->resize_hpt_default; 2730 } 2731 } 2732 2733 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2734 2735 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2736 /* 2737 * User requested HPT resize, but this host can't supply it. Bail out 2738 */ 2739 error_report_err(resize_hpt_err); 2740 exit(1); 2741 } 2742 error_free(resize_hpt_err); 2743 2744 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2745 2746 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2747 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2748 2749 /* 2750 * VSMT must be set in order to be able to compute VCPU ids, ie to 2751 * call spapr_max_server_number() or spapr_vcpu_id(). 2752 */ 2753 spapr_set_vsmt_mode(spapr, &error_fatal); 2754 2755 /* Set up Interrupt Controller before we create the VCPUs */ 2756 spapr_irq_init(spapr, &error_fatal); 2757 2758 /* Set up containers for ibm,client-architecture-support negotiated options 2759 */ 2760 spapr->ov5 = spapr_ovec_new(); 2761 spapr->ov5_cas = spapr_ovec_new(); 2762 2763 if (smc->dr_lmb_enabled) { 2764 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2765 spapr_validate_node_memory(machine, &error_fatal); 2766 } 2767 2768 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2769 2770 /* advertise support for dedicated HP event source to guests */ 2771 if (spapr->use_hotplug_event_source) { 2772 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2773 } 2774 2775 /* advertise support for HPT resizing */ 2776 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2777 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2778 } 2779 2780 /* advertise support for ibm,dyamic-memory-v2 */ 2781 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2782 2783 /* advertise XIVE on POWER9 machines */ 2784 if (spapr->irq->xive) { 2785 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2786 } 2787 2788 /* init CPUs */ 2789 spapr_init_cpus(spapr); 2790 2791 /* 2792 * check we don't have a memory-less/cpu-less NUMA node 2793 * Firmware relies on the existing memory/cpu topology to provide the 2794 * NUMA topology to the kernel. 2795 * And the linux kernel needs to know the NUMA topology at start 2796 * to be able to hotplug CPUs later. 2797 */ 2798 if (machine->numa_state->num_nodes) { 2799 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2800 /* check for memory-less node */ 2801 if (machine->numa_state->nodes[i].node_mem == 0) { 2802 CPUState *cs; 2803 int found = 0; 2804 /* check for cpu-less node */ 2805 CPU_FOREACH(cs) { 2806 PowerPCCPU *cpu = POWERPC_CPU(cs); 2807 if (cpu->node_id == i) { 2808 found = 1; 2809 break; 2810 } 2811 } 2812 /* memory-less and cpu-less node */ 2813 if (!found) { 2814 error_report( 2815 "Memory-less/cpu-less nodes are not supported (node %d)", 2816 i); 2817 exit(1); 2818 } 2819 } 2820 } 2821 2822 } 2823 2824 /* 2825 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2826 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2827 * called from vPHB reset handler so we initialize the counter here. 2828 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2829 * must be equally distant from any other node. 2830 * The final value of spapr->gpu_numa_id is going to be written to 2831 * max-associativity-domains in spapr_build_fdt(). 2832 */ 2833 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2834 2835 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2836 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2837 spapr->max_compat_pvr)) { 2838 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2839 /* KVM and TCG always allow GTSE with radix... */ 2840 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2841 } 2842 /* ... but not with hash (currently). */ 2843 2844 if (kvm_enabled()) { 2845 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2846 kvmppc_enable_logical_ci_hcalls(); 2847 kvmppc_enable_set_mode_hcall(); 2848 2849 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2850 kvmppc_enable_clear_ref_mod_hcalls(); 2851 2852 /* Enable H_PAGE_INIT */ 2853 kvmppc_enable_h_page_init(); 2854 } 2855 2856 /* map RAM */ 2857 memory_region_add_subregion(sysmem, 0, machine->ram); 2858 2859 /* always allocate the device memory information */ 2860 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2861 2862 /* initialize hotplug memory address space */ 2863 if (machine->ram_size < machine->maxram_size) { 2864 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2865 /* 2866 * Limit the number of hotpluggable memory slots to half the number 2867 * slots that KVM supports, leaving the other half for PCI and other 2868 * devices. However ensure that number of slots doesn't drop below 32. 2869 */ 2870 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2871 SPAPR_MAX_RAM_SLOTS; 2872 2873 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2874 max_memslots = SPAPR_MAX_RAM_SLOTS; 2875 } 2876 if (machine->ram_slots > max_memslots) { 2877 error_report("Specified number of memory slots %" 2878 PRIu64" exceeds max supported %d", 2879 machine->ram_slots, max_memslots); 2880 exit(1); 2881 } 2882 2883 machine->device_memory->base = ROUND_UP(machine->ram_size, 2884 SPAPR_DEVICE_MEM_ALIGN); 2885 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2886 "device-memory", device_mem_size); 2887 memory_region_add_subregion(sysmem, machine->device_memory->base, 2888 &machine->device_memory->mr); 2889 } 2890 2891 if (smc->dr_lmb_enabled) { 2892 spapr_create_lmb_dr_connectors(spapr); 2893 } 2894 2895 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2896 /* Create the error string for live migration blocker */ 2897 error_setg(&spapr->fwnmi_migration_blocker, 2898 "A machine check is being handled during migration. The handler" 2899 "may run and log hardware error on the destination"); 2900 } 2901 2902 if (mc->nvdimm_supported) { 2903 spapr_create_nvdimm_dr_connectors(spapr); 2904 } 2905 2906 /* Set up RTAS event infrastructure */ 2907 spapr_events_init(spapr); 2908 2909 /* Set up the RTC RTAS interfaces */ 2910 spapr_rtc_create(spapr); 2911 2912 /* Set up VIO bus */ 2913 spapr->vio_bus = spapr_vio_bus_init(); 2914 2915 for (i = 0; i < serial_max_hds(); i++) { 2916 if (serial_hd(i)) { 2917 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2918 } 2919 } 2920 2921 /* We always have at least the nvram device on VIO */ 2922 spapr_create_nvram(spapr); 2923 2924 /* 2925 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2926 * connectors (described in root DT node's "ibm,drc-types" property) 2927 * are pre-initialized here. additional child connectors (such as 2928 * connectors for a PHBs PCI slots) are added as needed during their 2929 * parent's realization. 2930 */ 2931 if (smc->dr_phb_enabled) { 2932 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2933 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2934 } 2935 } 2936 2937 /* Set up PCI */ 2938 spapr_pci_rtas_init(); 2939 2940 phb = spapr_create_default_phb(); 2941 2942 for (i = 0; i < nb_nics; i++) { 2943 NICInfo *nd = &nd_table[i]; 2944 2945 if (!nd->model) { 2946 nd->model = g_strdup("spapr-vlan"); 2947 } 2948 2949 if (g_str_equal(nd->model, "spapr-vlan") || 2950 g_str_equal(nd->model, "ibmveth")) { 2951 spapr_vlan_create(spapr->vio_bus, nd); 2952 } else { 2953 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2954 } 2955 } 2956 2957 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2958 spapr_vscsi_create(spapr->vio_bus); 2959 } 2960 2961 /* Graphics */ 2962 if (spapr_vga_init(phb->bus, &error_fatal)) { 2963 spapr->has_graphics = true; 2964 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2965 } 2966 2967 if (machine->usb) { 2968 if (smc->use_ohci_by_default) { 2969 pci_create_simple(phb->bus, -1, "pci-ohci"); 2970 } else { 2971 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2972 } 2973 2974 if (spapr->has_graphics) { 2975 USBBus *usb_bus = usb_bus_find(-1); 2976 2977 usb_create_simple(usb_bus, "usb-kbd"); 2978 usb_create_simple(usb_bus, "usb-mouse"); 2979 } 2980 } 2981 2982 if (kernel_filename) { 2983 uint64_t lowaddr = 0; 2984 2985 spapr->kernel_size = load_elf(kernel_filename, NULL, 2986 translate_kernel_address, spapr, 2987 NULL, &lowaddr, NULL, NULL, 1, 2988 PPC_ELF_MACHINE, 0, 0); 2989 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2990 spapr->kernel_size = load_elf(kernel_filename, NULL, 2991 translate_kernel_address, spapr, NULL, 2992 &lowaddr, NULL, NULL, 0, 2993 PPC_ELF_MACHINE, 2994 0, 0); 2995 spapr->kernel_le = spapr->kernel_size > 0; 2996 } 2997 if (spapr->kernel_size < 0) { 2998 error_report("error loading %s: %s", kernel_filename, 2999 load_elf_strerror(spapr->kernel_size)); 3000 exit(1); 3001 } 3002 3003 /* load initrd */ 3004 if (initrd_filename) { 3005 /* Try to locate the initrd in the gap between the kernel 3006 * and the firmware. Add a bit of space just in case 3007 */ 3008 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 3009 + 0x1ffff) & ~0xffff; 3010 spapr->initrd_size = load_image_targphys(initrd_filename, 3011 spapr->initrd_base, 3012 load_limit 3013 - spapr->initrd_base); 3014 if (spapr->initrd_size < 0) { 3015 error_report("could not load initial ram disk '%s'", 3016 initrd_filename); 3017 exit(1); 3018 } 3019 } 3020 } 3021 3022 if (bios_name == NULL) { 3023 bios_name = FW_FILE_NAME; 3024 } 3025 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 3026 if (!filename) { 3027 error_report("Could not find LPAR firmware '%s'", bios_name); 3028 exit(1); 3029 } 3030 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 3031 if (fw_size <= 0) { 3032 error_report("Could not load LPAR firmware '%s'", filename); 3033 exit(1); 3034 } 3035 g_free(filename); 3036 3037 /* FIXME: Should register things through the MachineState's qdev 3038 * interface, this is a legacy from the sPAPREnvironment structure 3039 * which predated MachineState but had a similar function */ 3040 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3041 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3042 &savevm_htab_handlers, spapr); 3043 3044 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 3045 3046 qemu_register_boot_set(spapr_boot_set, spapr); 3047 3048 /* 3049 * Nothing needs to be done to resume a suspended guest because 3050 * suspending does not change the machine state, so no need for 3051 * a ->wakeup method. 3052 */ 3053 qemu_register_wakeup_support(); 3054 3055 if (kvm_enabled()) { 3056 /* to stop and start vmclock */ 3057 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3058 &spapr->tb); 3059 3060 kvmppc_spapr_enable_inkernel_multitce(); 3061 } 3062 3063 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3064 } 3065 3066 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3067 { 3068 if (!vm_type) { 3069 return 0; 3070 } 3071 3072 if (!strcmp(vm_type, "HV")) { 3073 return 1; 3074 } 3075 3076 if (!strcmp(vm_type, "PR")) { 3077 return 2; 3078 } 3079 3080 error_report("Unknown kvm-type specified '%s'", vm_type); 3081 exit(1); 3082 } 3083 3084 /* 3085 * Implementation of an interface to adjust firmware path 3086 * for the bootindex property handling. 3087 */ 3088 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3089 DeviceState *dev) 3090 { 3091 #define CAST(type, obj, name) \ 3092 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3093 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3094 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3095 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3096 3097 if (d) { 3098 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3099 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3100 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3101 3102 if (spapr) { 3103 /* 3104 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3105 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3106 * 0x8000 | (target << 8) | (bus << 5) | lun 3107 * (see the "Logical unit addressing format" table in SAM5) 3108 */ 3109 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3110 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3111 (uint64_t)id << 48); 3112 } else if (virtio) { 3113 /* 3114 * We use SRP luns of the form 01000000 | (target << 8) | lun 3115 * in the top 32 bits of the 64-bit LUN 3116 * Note: the quote above is from SLOF and it is wrong, 3117 * the actual binding is: 3118 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3119 */ 3120 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3121 if (d->lun >= 256) { 3122 /* Use the LUN "flat space addressing method" */ 3123 id |= 0x4000; 3124 } 3125 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3126 (uint64_t)id << 32); 3127 } else if (usb) { 3128 /* 3129 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3130 * in the top 32 bits of the 64-bit LUN 3131 */ 3132 unsigned usb_port = atoi(usb->port->path); 3133 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3134 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3135 (uint64_t)id << 32); 3136 } 3137 } 3138 3139 /* 3140 * SLOF probes the USB devices, and if it recognizes that the device is a 3141 * storage device, it changes its name to "storage" instead of "usb-host", 3142 * and additionally adds a child node for the SCSI LUN, so the correct 3143 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3144 */ 3145 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3146 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3147 if (usb_host_dev_is_scsi_storage(usbdev)) { 3148 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3149 } 3150 } 3151 3152 if (phb) { 3153 /* Replace "pci" with "pci@800000020000000" */ 3154 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3155 } 3156 3157 if (vsc) { 3158 /* Same logic as virtio above */ 3159 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3160 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3161 } 3162 3163 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3164 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3165 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3166 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3167 } 3168 3169 return NULL; 3170 } 3171 3172 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3173 { 3174 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3175 3176 return g_strdup(spapr->kvm_type); 3177 } 3178 3179 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3180 { 3181 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3182 3183 g_free(spapr->kvm_type); 3184 spapr->kvm_type = g_strdup(value); 3185 } 3186 3187 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3188 { 3189 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3190 3191 return spapr->use_hotplug_event_source; 3192 } 3193 3194 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3195 Error **errp) 3196 { 3197 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3198 3199 spapr->use_hotplug_event_source = value; 3200 } 3201 3202 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3203 { 3204 return true; 3205 } 3206 3207 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3208 { 3209 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3210 3211 switch (spapr->resize_hpt) { 3212 case SPAPR_RESIZE_HPT_DEFAULT: 3213 return g_strdup("default"); 3214 case SPAPR_RESIZE_HPT_DISABLED: 3215 return g_strdup("disabled"); 3216 case SPAPR_RESIZE_HPT_ENABLED: 3217 return g_strdup("enabled"); 3218 case SPAPR_RESIZE_HPT_REQUIRED: 3219 return g_strdup("required"); 3220 } 3221 g_assert_not_reached(); 3222 } 3223 3224 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3225 { 3226 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3227 3228 if (strcmp(value, "default") == 0) { 3229 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3230 } else if (strcmp(value, "disabled") == 0) { 3231 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3232 } else if (strcmp(value, "enabled") == 0) { 3233 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3234 } else if (strcmp(value, "required") == 0) { 3235 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3236 } else { 3237 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3238 } 3239 } 3240 3241 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3242 { 3243 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3244 3245 if (spapr->irq == &spapr_irq_xics_legacy) { 3246 return g_strdup("legacy"); 3247 } else if (spapr->irq == &spapr_irq_xics) { 3248 return g_strdup("xics"); 3249 } else if (spapr->irq == &spapr_irq_xive) { 3250 return g_strdup("xive"); 3251 } else if (spapr->irq == &spapr_irq_dual) { 3252 return g_strdup("dual"); 3253 } 3254 g_assert_not_reached(); 3255 } 3256 3257 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3258 { 3259 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3260 3261 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3262 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3263 return; 3264 } 3265 3266 /* The legacy IRQ backend can not be set */ 3267 if (strcmp(value, "xics") == 0) { 3268 spapr->irq = &spapr_irq_xics; 3269 } else if (strcmp(value, "xive") == 0) { 3270 spapr->irq = &spapr_irq_xive; 3271 } else if (strcmp(value, "dual") == 0) { 3272 spapr->irq = &spapr_irq_dual; 3273 } else { 3274 error_setg(errp, "Bad value for \"ic-mode\" property"); 3275 } 3276 } 3277 3278 static char *spapr_get_host_model(Object *obj, Error **errp) 3279 { 3280 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3281 3282 return g_strdup(spapr->host_model); 3283 } 3284 3285 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3286 { 3287 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3288 3289 g_free(spapr->host_model); 3290 spapr->host_model = g_strdup(value); 3291 } 3292 3293 static char *spapr_get_host_serial(Object *obj, Error **errp) 3294 { 3295 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3296 3297 return g_strdup(spapr->host_serial); 3298 } 3299 3300 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3301 { 3302 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3303 3304 g_free(spapr->host_serial); 3305 spapr->host_serial = g_strdup(value); 3306 } 3307 3308 static void spapr_instance_init(Object *obj) 3309 { 3310 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3311 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3312 3313 spapr->htab_fd = -1; 3314 spapr->use_hotplug_event_source = true; 3315 object_property_add_str(obj, "kvm-type", 3316 spapr_get_kvm_type, spapr_set_kvm_type); 3317 object_property_set_description(obj, "kvm-type", 3318 "Specifies the KVM virtualization mode (HV, PR)"); 3319 object_property_add_bool(obj, "modern-hotplug-events", 3320 spapr_get_modern_hotplug_events, 3321 spapr_set_modern_hotplug_events); 3322 object_property_set_description(obj, "modern-hotplug-events", 3323 "Use dedicated hotplug event mechanism in" 3324 " place of standard EPOW events when possible" 3325 " (required for memory hot-unplug support)"); 3326 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3327 "Maximum permitted CPU compatibility mode"); 3328 3329 object_property_add_str(obj, "resize-hpt", 3330 spapr_get_resize_hpt, spapr_set_resize_hpt); 3331 object_property_set_description(obj, "resize-hpt", 3332 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3333 object_property_add_uint32_ptr(obj, "vsmt", 3334 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3335 object_property_set_description(obj, "vsmt", 3336 "Virtual SMT: KVM behaves as if this were" 3337 " the host's SMT mode"); 3338 3339 object_property_add_bool(obj, "vfio-no-msix-emulation", 3340 spapr_get_msix_emulation, NULL); 3341 3342 object_property_add_uint64_ptr(obj, "kernel-addr", 3343 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3344 object_property_set_description(obj, "kernel-addr", 3345 stringify(KERNEL_LOAD_ADDR) 3346 " for -kernel is the default"); 3347 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3348 /* The machine class defines the default interrupt controller mode */ 3349 spapr->irq = smc->irq; 3350 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3351 spapr_set_ic_mode); 3352 object_property_set_description(obj, "ic-mode", 3353 "Specifies the interrupt controller mode (xics, xive, dual)"); 3354 3355 object_property_add_str(obj, "host-model", 3356 spapr_get_host_model, spapr_set_host_model); 3357 object_property_set_description(obj, "host-model", 3358 "Host model to advertise in guest device tree"); 3359 object_property_add_str(obj, "host-serial", 3360 spapr_get_host_serial, spapr_set_host_serial); 3361 object_property_set_description(obj, "host-serial", 3362 "Host serial number to advertise in guest device tree"); 3363 } 3364 3365 static void spapr_machine_finalizefn(Object *obj) 3366 { 3367 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3368 3369 g_free(spapr->kvm_type); 3370 } 3371 3372 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3373 { 3374 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3375 PowerPCCPU *cpu = POWERPC_CPU(cs); 3376 CPUPPCState *env = &cpu->env; 3377 3378 cpu_synchronize_state(cs); 3379 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3380 if (spapr->fwnmi_system_reset_addr != -1) { 3381 uint64_t rtas_addr, addr; 3382 3383 /* get rtas addr from fdt */ 3384 rtas_addr = spapr_get_rtas_addr(); 3385 if (!rtas_addr) { 3386 qemu_system_guest_panicked(NULL); 3387 return; 3388 } 3389 3390 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3391 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3392 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3393 env->gpr[3] = addr; 3394 } 3395 ppc_cpu_do_system_reset(cs); 3396 if (spapr->fwnmi_system_reset_addr != -1) { 3397 env->nip = spapr->fwnmi_system_reset_addr; 3398 } 3399 } 3400 3401 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3402 { 3403 CPUState *cs; 3404 3405 CPU_FOREACH(cs) { 3406 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3407 } 3408 } 3409 3410 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3411 void *fdt, int *fdt_start_offset, Error **errp) 3412 { 3413 uint64_t addr; 3414 uint32_t node; 3415 3416 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3417 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3418 &error_abort); 3419 *fdt_start_offset = spapr_dt_memory_node(fdt, node, addr, 3420 SPAPR_MEMORY_BLOCK_SIZE); 3421 return 0; 3422 } 3423 3424 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3425 bool dedicated_hp_event_source, Error **errp) 3426 { 3427 SpaprDrc *drc; 3428 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3429 int i; 3430 uint64_t addr = addr_start; 3431 bool hotplugged = spapr_drc_hotplugged(dev); 3432 Error *local_err = NULL; 3433 3434 for (i = 0; i < nr_lmbs; i++) { 3435 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3436 addr / SPAPR_MEMORY_BLOCK_SIZE); 3437 g_assert(drc); 3438 3439 spapr_drc_attach(drc, dev, &local_err); 3440 if (local_err) { 3441 while (addr > addr_start) { 3442 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3443 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3444 addr / SPAPR_MEMORY_BLOCK_SIZE); 3445 spapr_drc_detach(drc); 3446 } 3447 error_propagate(errp, local_err); 3448 return; 3449 } 3450 if (!hotplugged) { 3451 spapr_drc_reset(drc); 3452 } 3453 addr += SPAPR_MEMORY_BLOCK_SIZE; 3454 } 3455 /* send hotplug notification to the 3456 * guest only in case of hotplugged memory 3457 */ 3458 if (hotplugged) { 3459 if (dedicated_hp_event_source) { 3460 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3461 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3462 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3463 nr_lmbs, 3464 spapr_drc_index(drc)); 3465 } else { 3466 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3467 nr_lmbs); 3468 } 3469 } 3470 } 3471 3472 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3473 Error **errp) 3474 { 3475 Error *local_err = NULL; 3476 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3477 PCDIMMDevice *dimm = PC_DIMM(dev); 3478 uint64_t size, addr, slot; 3479 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3480 3481 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3482 3483 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3484 if (local_err) { 3485 goto out; 3486 } 3487 3488 if (!is_nvdimm) { 3489 addr = object_property_get_uint(OBJECT(dimm), 3490 PC_DIMM_ADDR_PROP, &local_err); 3491 if (local_err) { 3492 goto out_unplug; 3493 } 3494 spapr_add_lmbs(dev, addr, size, 3495 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3496 &local_err); 3497 } else { 3498 slot = object_property_get_uint(OBJECT(dimm), 3499 PC_DIMM_SLOT_PROP, &local_err); 3500 if (local_err) { 3501 goto out_unplug; 3502 } 3503 spapr_add_nvdimm(dev, slot, &local_err); 3504 } 3505 3506 if (local_err) { 3507 goto out_unplug; 3508 } 3509 3510 return; 3511 3512 out_unplug: 3513 pc_dimm_unplug(dimm, MACHINE(ms)); 3514 out: 3515 error_propagate(errp, local_err); 3516 } 3517 3518 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3519 Error **errp) 3520 { 3521 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3522 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3523 const MachineClass *mc = MACHINE_CLASS(smc); 3524 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3525 PCDIMMDevice *dimm = PC_DIMM(dev); 3526 Error *local_err = NULL; 3527 uint64_t size; 3528 Object *memdev; 3529 hwaddr pagesize; 3530 3531 if (!smc->dr_lmb_enabled) { 3532 error_setg(errp, "Memory hotplug not supported for this machine"); 3533 return; 3534 } 3535 3536 if (is_nvdimm && !mc->nvdimm_supported) { 3537 error_setg(errp, "NVDIMM hotplug not supported for this machine"); 3538 return; 3539 } 3540 3541 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3542 if (local_err) { 3543 error_propagate(errp, local_err); 3544 return; 3545 } 3546 3547 if (!is_nvdimm && size % SPAPR_MEMORY_BLOCK_SIZE) { 3548 error_setg(errp, "Hotplugged memory size must be a multiple of " 3549 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3550 return; 3551 } else if (is_nvdimm) { 3552 spapr_nvdimm_validate_opts(NVDIMM(dev), size, &local_err); 3553 if (local_err) { 3554 error_propagate(errp, local_err); 3555 return; 3556 } 3557 } 3558 3559 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3560 &error_abort); 3561 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3562 spapr_check_pagesize(spapr, pagesize, &local_err); 3563 if (local_err) { 3564 error_propagate(errp, local_err); 3565 return; 3566 } 3567 3568 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3569 } 3570 3571 struct SpaprDimmState { 3572 PCDIMMDevice *dimm; 3573 uint32_t nr_lmbs; 3574 QTAILQ_ENTRY(SpaprDimmState) next; 3575 }; 3576 3577 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3578 PCDIMMDevice *dimm) 3579 { 3580 SpaprDimmState *dimm_state = NULL; 3581 3582 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3583 if (dimm_state->dimm == dimm) { 3584 break; 3585 } 3586 } 3587 return dimm_state; 3588 } 3589 3590 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3591 uint32_t nr_lmbs, 3592 PCDIMMDevice *dimm) 3593 { 3594 SpaprDimmState *ds = NULL; 3595 3596 /* 3597 * If this request is for a DIMM whose removal had failed earlier 3598 * (due to guest's refusal to remove the LMBs), we would have this 3599 * dimm already in the pending_dimm_unplugs list. In that 3600 * case don't add again. 3601 */ 3602 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3603 if (!ds) { 3604 ds = g_malloc0(sizeof(SpaprDimmState)); 3605 ds->nr_lmbs = nr_lmbs; 3606 ds->dimm = dimm; 3607 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3608 } 3609 return ds; 3610 } 3611 3612 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3613 SpaprDimmState *dimm_state) 3614 { 3615 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3616 g_free(dimm_state); 3617 } 3618 3619 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3620 PCDIMMDevice *dimm) 3621 { 3622 SpaprDrc *drc; 3623 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3624 &error_abort); 3625 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3626 uint32_t avail_lmbs = 0; 3627 uint64_t addr_start, addr; 3628 int i; 3629 3630 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3631 &error_abort); 3632 3633 addr = addr_start; 3634 for (i = 0; i < nr_lmbs; i++) { 3635 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3636 addr / SPAPR_MEMORY_BLOCK_SIZE); 3637 g_assert(drc); 3638 if (drc->dev) { 3639 avail_lmbs++; 3640 } 3641 addr += SPAPR_MEMORY_BLOCK_SIZE; 3642 } 3643 3644 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3645 } 3646 3647 /* Callback to be called during DRC release. */ 3648 void spapr_lmb_release(DeviceState *dev) 3649 { 3650 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3651 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3652 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3653 3654 /* This information will get lost if a migration occurs 3655 * during the unplug process. In this case recover it. */ 3656 if (ds == NULL) { 3657 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3658 g_assert(ds); 3659 /* The DRC being examined by the caller at least must be counted */ 3660 g_assert(ds->nr_lmbs); 3661 } 3662 3663 if (--ds->nr_lmbs) { 3664 return; 3665 } 3666 3667 /* 3668 * Now that all the LMBs have been removed by the guest, call the 3669 * unplug handler chain. This can never fail. 3670 */ 3671 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3672 object_unparent(OBJECT(dev)); 3673 } 3674 3675 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3676 { 3677 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3678 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3679 3680 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3681 qdev_unrealize(dev); 3682 spapr_pending_dimm_unplugs_remove(spapr, ds); 3683 } 3684 3685 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3686 DeviceState *dev, Error **errp) 3687 { 3688 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3689 Error *local_err = NULL; 3690 PCDIMMDevice *dimm = PC_DIMM(dev); 3691 uint32_t nr_lmbs; 3692 uint64_t size, addr_start, addr; 3693 int i; 3694 SpaprDrc *drc; 3695 3696 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3697 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3698 return; 3699 } 3700 3701 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3702 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3703 3704 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3705 &local_err); 3706 if (local_err) { 3707 error_propagate(errp, local_err); 3708 return; 3709 } 3710 3711 /* 3712 * An existing pending dimm state for this DIMM means that there is an 3713 * unplug operation in progress, waiting for the spapr_lmb_release 3714 * callback to complete the job (BQL can't cover that far). In this case, 3715 * bail out to avoid detaching DRCs that were already released. 3716 */ 3717 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3718 error_setg(errp, "Memory unplug already in progress for device %s", 3719 dev->id); 3720 return; 3721 } 3722 3723 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3724 3725 addr = addr_start; 3726 for (i = 0; i < nr_lmbs; i++) { 3727 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3728 addr / SPAPR_MEMORY_BLOCK_SIZE); 3729 g_assert(drc); 3730 3731 spapr_drc_detach(drc); 3732 addr += SPAPR_MEMORY_BLOCK_SIZE; 3733 } 3734 3735 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3736 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3737 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3738 nr_lmbs, spapr_drc_index(drc)); 3739 } 3740 3741 /* Callback to be called during DRC release. */ 3742 void spapr_core_release(DeviceState *dev) 3743 { 3744 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3745 3746 /* Call the unplug handler chain. This can never fail. */ 3747 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3748 object_unparent(OBJECT(dev)); 3749 } 3750 3751 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3752 { 3753 MachineState *ms = MACHINE(hotplug_dev); 3754 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3755 CPUCore *cc = CPU_CORE(dev); 3756 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3757 3758 if (smc->pre_2_10_has_unused_icps) { 3759 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3760 int i; 3761 3762 for (i = 0; i < cc->nr_threads; i++) { 3763 CPUState *cs = CPU(sc->threads[i]); 3764 3765 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3766 } 3767 } 3768 3769 assert(core_slot); 3770 core_slot->cpu = NULL; 3771 qdev_unrealize(dev); 3772 } 3773 3774 static 3775 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3776 Error **errp) 3777 { 3778 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3779 int index; 3780 SpaprDrc *drc; 3781 CPUCore *cc = CPU_CORE(dev); 3782 3783 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3784 error_setg(errp, "Unable to find CPU core with core-id: %d", 3785 cc->core_id); 3786 return; 3787 } 3788 if (index == 0) { 3789 error_setg(errp, "Boot CPU core may not be unplugged"); 3790 return; 3791 } 3792 3793 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3794 spapr_vcpu_id(spapr, cc->core_id)); 3795 g_assert(drc); 3796 3797 if (!spapr_drc_unplug_requested(drc)) { 3798 spapr_drc_detach(drc); 3799 spapr_hotplug_req_remove_by_index(drc); 3800 } 3801 } 3802 3803 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3804 void *fdt, int *fdt_start_offset, Error **errp) 3805 { 3806 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3807 CPUState *cs = CPU(core->threads[0]); 3808 PowerPCCPU *cpu = POWERPC_CPU(cs); 3809 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3810 int id = spapr_get_vcpu_id(cpu); 3811 char *nodename; 3812 int offset; 3813 3814 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3815 offset = fdt_add_subnode(fdt, 0, nodename); 3816 g_free(nodename); 3817 3818 spapr_dt_cpu(cs, fdt, offset, spapr); 3819 3820 *fdt_start_offset = offset; 3821 return 0; 3822 } 3823 3824 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3825 Error **errp) 3826 { 3827 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3828 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3829 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3830 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3831 CPUCore *cc = CPU_CORE(dev); 3832 CPUState *cs; 3833 SpaprDrc *drc; 3834 Error *local_err = NULL; 3835 CPUArchId *core_slot; 3836 int index; 3837 bool hotplugged = spapr_drc_hotplugged(dev); 3838 int i; 3839 3840 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3841 if (!core_slot) { 3842 error_setg(errp, "Unable to find CPU core with core-id: %d", 3843 cc->core_id); 3844 return; 3845 } 3846 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3847 spapr_vcpu_id(spapr, cc->core_id)); 3848 3849 g_assert(drc || !mc->has_hotpluggable_cpus); 3850 3851 if (drc) { 3852 spapr_drc_attach(drc, dev, &local_err); 3853 if (local_err) { 3854 error_propagate(errp, local_err); 3855 return; 3856 } 3857 3858 if (hotplugged) { 3859 /* 3860 * Send hotplug notification interrupt to the guest only 3861 * in case of hotplugged CPUs. 3862 */ 3863 spapr_hotplug_req_add_by_index(drc); 3864 } else { 3865 spapr_drc_reset(drc); 3866 } 3867 } 3868 3869 core_slot->cpu = OBJECT(dev); 3870 3871 if (smc->pre_2_10_has_unused_icps) { 3872 for (i = 0; i < cc->nr_threads; i++) { 3873 cs = CPU(core->threads[i]); 3874 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3875 } 3876 } 3877 3878 /* 3879 * Set compatibility mode to match the boot CPU, which was either set 3880 * by the machine reset code or by CAS. 3881 */ 3882 if (hotplugged) { 3883 for (i = 0; i < cc->nr_threads; i++) { 3884 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3885 &local_err); 3886 if (local_err) { 3887 error_propagate(errp, local_err); 3888 return; 3889 } 3890 } 3891 } 3892 } 3893 3894 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3895 Error **errp) 3896 { 3897 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3898 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3899 CPUCore *cc = CPU_CORE(dev); 3900 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3901 const char *type = object_get_typename(OBJECT(dev)); 3902 CPUArchId *core_slot; 3903 int index; 3904 unsigned int smp_threads = machine->smp.threads; 3905 3906 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3907 error_setg(errp, "CPU hotplug not supported for this machine"); 3908 return; 3909 } 3910 3911 if (strcmp(base_core_type, type)) { 3912 error_setg(errp, "CPU core type should be %s", base_core_type); 3913 return; 3914 } 3915 3916 if (cc->core_id % smp_threads) { 3917 error_setg(errp, "invalid core id %d", cc->core_id); 3918 return; 3919 } 3920 3921 /* 3922 * In general we should have homogeneous threads-per-core, but old 3923 * (pre hotplug support) machine types allow the last core to have 3924 * reduced threads as a compatibility hack for when we allowed 3925 * total vcpus not a multiple of threads-per-core. 3926 */ 3927 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3928 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 3929 smp_threads); 3930 return; 3931 } 3932 3933 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3934 if (!core_slot) { 3935 error_setg(errp, "core id %d out of range", cc->core_id); 3936 return; 3937 } 3938 3939 if (core_slot->cpu) { 3940 error_setg(errp, "core %d already populated", cc->core_id); 3941 return; 3942 } 3943 3944 numa_cpu_pre_plug(core_slot, dev, errp); 3945 } 3946 3947 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3948 void *fdt, int *fdt_start_offset, Error **errp) 3949 { 3950 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3951 int intc_phandle; 3952 3953 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3954 if (intc_phandle <= 0) { 3955 return -1; 3956 } 3957 3958 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3959 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3960 return -1; 3961 } 3962 3963 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3964 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3965 3966 return 0; 3967 } 3968 3969 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3970 Error **errp) 3971 { 3972 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3973 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3974 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3975 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3976 3977 if (dev->hotplugged && !smc->dr_phb_enabled) { 3978 error_setg(errp, "PHB hotplug not supported for this machine"); 3979 return; 3980 } 3981 3982 if (sphb->index == (uint32_t)-1) { 3983 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3984 return; 3985 } 3986 3987 /* 3988 * This will check that sphb->index doesn't exceed the maximum number of 3989 * PHBs for the current machine type. 3990 */ 3991 smc->phb_placement(spapr, sphb->index, 3992 &sphb->buid, &sphb->io_win_addr, 3993 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3994 windows_supported, sphb->dma_liobn, 3995 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3996 errp); 3997 } 3998 3999 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4000 Error **errp) 4001 { 4002 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4003 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4004 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4005 SpaprDrc *drc; 4006 bool hotplugged = spapr_drc_hotplugged(dev); 4007 Error *local_err = NULL; 4008 4009 if (!smc->dr_phb_enabled) { 4010 return; 4011 } 4012 4013 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4014 /* hotplug hooks should check it's enabled before getting this far */ 4015 assert(drc); 4016 4017 spapr_drc_attach(drc, dev, &local_err); 4018 if (local_err) { 4019 error_propagate(errp, local_err); 4020 return; 4021 } 4022 4023 if (hotplugged) { 4024 spapr_hotplug_req_add_by_index(drc); 4025 } else { 4026 spapr_drc_reset(drc); 4027 } 4028 } 4029 4030 void spapr_phb_release(DeviceState *dev) 4031 { 4032 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4033 4034 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4035 object_unparent(OBJECT(dev)); 4036 } 4037 4038 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4039 { 4040 qdev_unrealize(dev); 4041 } 4042 4043 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4044 DeviceState *dev, Error **errp) 4045 { 4046 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4047 SpaprDrc *drc; 4048 4049 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4050 assert(drc); 4051 4052 if (!spapr_drc_unplug_requested(drc)) { 4053 spapr_drc_detach(drc); 4054 spapr_hotplug_req_remove_by_index(drc); 4055 } 4056 } 4057 4058 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4059 Error **errp) 4060 { 4061 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4062 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4063 4064 if (spapr->tpm_proxy != NULL) { 4065 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4066 return; 4067 } 4068 4069 spapr->tpm_proxy = tpm_proxy; 4070 } 4071 4072 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4073 { 4074 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4075 4076 qdev_unrealize(dev); 4077 object_unparent(OBJECT(dev)); 4078 spapr->tpm_proxy = NULL; 4079 } 4080 4081 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4082 DeviceState *dev, Error **errp) 4083 { 4084 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4085 spapr_memory_plug(hotplug_dev, dev, errp); 4086 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4087 spapr_core_plug(hotplug_dev, dev, errp); 4088 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4089 spapr_phb_plug(hotplug_dev, dev, errp); 4090 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4091 spapr_tpm_proxy_plug(hotplug_dev, dev, errp); 4092 } 4093 } 4094 4095 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4096 DeviceState *dev, Error **errp) 4097 { 4098 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4099 spapr_memory_unplug(hotplug_dev, dev); 4100 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4101 spapr_core_unplug(hotplug_dev, dev); 4102 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4103 spapr_phb_unplug(hotplug_dev, dev); 4104 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4105 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4106 } 4107 } 4108 4109 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4110 DeviceState *dev, Error **errp) 4111 { 4112 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4113 MachineClass *mc = MACHINE_GET_CLASS(sms); 4114 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4115 4116 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4117 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 4118 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4119 } else { 4120 /* NOTE: this means there is a window after guest reset, prior to 4121 * CAS negotiation, where unplug requests will fail due to the 4122 * capability not being detected yet. This is a bit different than 4123 * the case with PCI unplug, where the events will be queued and 4124 * eventually handled by the guest after boot 4125 */ 4126 error_setg(errp, "Memory hot unplug not supported for this guest"); 4127 } 4128 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4129 if (!mc->has_hotpluggable_cpus) { 4130 error_setg(errp, "CPU hot unplug not supported on this machine"); 4131 return; 4132 } 4133 spapr_core_unplug_request(hotplug_dev, dev, errp); 4134 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4135 if (!smc->dr_phb_enabled) { 4136 error_setg(errp, "PHB hot unplug not supported on this machine"); 4137 return; 4138 } 4139 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4140 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4141 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4142 } 4143 } 4144 4145 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4146 DeviceState *dev, Error **errp) 4147 { 4148 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4149 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4150 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4151 spapr_core_pre_plug(hotplug_dev, dev, errp); 4152 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4153 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4154 } 4155 } 4156 4157 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4158 DeviceState *dev) 4159 { 4160 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4161 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4162 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4163 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4164 return HOTPLUG_HANDLER(machine); 4165 } 4166 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4167 PCIDevice *pcidev = PCI_DEVICE(dev); 4168 PCIBus *root = pci_device_root_bus(pcidev); 4169 SpaprPhbState *phb = 4170 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4171 TYPE_SPAPR_PCI_HOST_BRIDGE); 4172 4173 if (phb) { 4174 return HOTPLUG_HANDLER(phb); 4175 } 4176 } 4177 return NULL; 4178 } 4179 4180 static CpuInstanceProperties 4181 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4182 { 4183 CPUArchId *core_slot; 4184 MachineClass *mc = MACHINE_GET_CLASS(machine); 4185 4186 /* make sure possible_cpu are intialized */ 4187 mc->possible_cpu_arch_ids(machine); 4188 /* get CPU core slot containing thread that matches cpu_index */ 4189 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4190 assert(core_slot); 4191 return core_slot->props; 4192 } 4193 4194 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4195 { 4196 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4197 } 4198 4199 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4200 { 4201 int i; 4202 unsigned int smp_threads = machine->smp.threads; 4203 unsigned int smp_cpus = machine->smp.cpus; 4204 const char *core_type; 4205 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4206 MachineClass *mc = MACHINE_GET_CLASS(machine); 4207 4208 if (!mc->has_hotpluggable_cpus) { 4209 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4210 } 4211 if (machine->possible_cpus) { 4212 assert(machine->possible_cpus->len == spapr_max_cores); 4213 return machine->possible_cpus; 4214 } 4215 4216 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4217 if (!core_type) { 4218 error_report("Unable to find sPAPR CPU Core definition"); 4219 exit(1); 4220 } 4221 4222 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4223 sizeof(CPUArchId) * spapr_max_cores); 4224 machine->possible_cpus->len = spapr_max_cores; 4225 for (i = 0; i < machine->possible_cpus->len; i++) { 4226 int core_id = i * smp_threads; 4227 4228 machine->possible_cpus->cpus[i].type = core_type; 4229 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4230 machine->possible_cpus->cpus[i].arch_id = core_id; 4231 machine->possible_cpus->cpus[i].props.has_core_id = true; 4232 machine->possible_cpus->cpus[i].props.core_id = core_id; 4233 } 4234 return machine->possible_cpus; 4235 } 4236 4237 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4238 uint64_t *buid, hwaddr *pio, 4239 hwaddr *mmio32, hwaddr *mmio64, 4240 unsigned n_dma, uint32_t *liobns, 4241 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4242 { 4243 /* 4244 * New-style PHB window placement. 4245 * 4246 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4247 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4248 * windows. 4249 * 4250 * Some guest kernels can't work with MMIO windows above 1<<46 4251 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4252 * 4253 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4254 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4255 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4256 * 1TiB 64-bit MMIO windows for each PHB. 4257 */ 4258 const uint64_t base_buid = 0x800000020000000ULL; 4259 int i; 4260 4261 /* Sanity check natural alignments */ 4262 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4263 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4264 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4265 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4266 /* Sanity check bounds */ 4267 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4268 SPAPR_PCI_MEM32_WIN_SIZE); 4269 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4270 SPAPR_PCI_MEM64_WIN_SIZE); 4271 4272 if (index >= SPAPR_MAX_PHBS) { 4273 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4274 SPAPR_MAX_PHBS - 1); 4275 return; 4276 } 4277 4278 *buid = base_buid + index; 4279 for (i = 0; i < n_dma; ++i) { 4280 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4281 } 4282 4283 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4284 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4285 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4286 4287 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4288 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4289 } 4290 4291 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4292 { 4293 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4294 4295 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4296 } 4297 4298 static void spapr_ics_resend(XICSFabric *dev) 4299 { 4300 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4301 4302 ics_resend(spapr->ics); 4303 } 4304 4305 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4306 { 4307 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4308 4309 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4310 } 4311 4312 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4313 Monitor *mon) 4314 { 4315 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4316 4317 spapr_irq_print_info(spapr, mon); 4318 monitor_printf(mon, "irqchip: %s\n", 4319 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4320 } 4321 4322 /* 4323 * This is a XIVE only operation 4324 */ 4325 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4326 uint8_t nvt_blk, uint32_t nvt_idx, 4327 bool cam_ignore, uint8_t priority, 4328 uint32_t logic_serv, XiveTCTXMatch *match) 4329 { 4330 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4331 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4332 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4333 int count; 4334 4335 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4336 priority, logic_serv, match); 4337 if (count < 0) { 4338 return count; 4339 } 4340 4341 /* 4342 * When we implement the save and restore of the thread interrupt 4343 * contexts in the enter/exit CPU handlers of the machine and the 4344 * escalations in QEMU, we should be able to handle non dispatched 4345 * vCPUs. 4346 * 4347 * Until this is done, the sPAPR machine should find at least one 4348 * matching context always. 4349 */ 4350 if (count == 0) { 4351 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4352 nvt_blk, nvt_idx); 4353 } 4354 4355 return count; 4356 } 4357 4358 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4359 { 4360 return cpu->vcpu_id; 4361 } 4362 4363 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4364 { 4365 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4366 MachineState *ms = MACHINE(spapr); 4367 int vcpu_id; 4368 4369 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4370 4371 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4372 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4373 error_append_hint(errp, "Adjust the number of cpus to %d " 4374 "or try to raise the number of threads per core\n", 4375 vcpu_id * ms->smp.threads / spapr->vsmt); 4376 return; 4377 } 4378 4379 cpu->vcpu_id = vcpu_id; 4380 } 4381 4382 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4383 { 4384 CPUState *cs; 4385 4386 CPU_FOREACH(cs) { 4387 PowerPCCPU *cpu = POWERPC_CPU(cs); 4388 4389 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4390 return cpu; 4391 } 4392 } 4393 4394 return NULL; 4395 } 4396 4397 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4398 { 4399 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4400 4401 /* These are only called by TCG, KVM maintains dispatch state */ 4402 4403 spapr_cpu->prod = false; 4404 if (spapr_cpu->vpa_addr) { 4405 CPUState *cs = CPU(cpu); 4406 uint32_t dispatch; 4407 4408 dispatch = ldl_be_phys(cs->as, 4409 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4410 dispatch++; 4411 if ((dispatch & 1) != 0) { 4412 qemu_log_mask(LOG_GUEST_ERROR, 4413 "VPA: incorrect dispatch counter value for " 4414 "dispatched partition %u, correcting.\n", dispatch); 4415 dispatch++; 4416 } 4417 stl_be_phys(cs->as, 4418 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4419 } 4420 } 4421 4422 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4423 { 4424 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4425 4426 if (spapr_cpu->vpa_addr) { 4427 CPUState *cs = CPU(cpu); 4428 uint32_t dispatch; 4429 4430 dispatch = ldl_be_phys(cs->as, 4431 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4432 dispatch++; 4433 if ((dispatch & 1) != 1) { 4434 qemu_log_mask(LOG_GUEST_ERROR, 4435 "VPA: incorrect dispatch counter value for " 4436 "preempted partition %u, correcting.\n", dispatch); 4437 dispatch++; 4438 } 4439 stl_be_phys(cs->as, 4440 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4441 } 4442 } 4443 4444 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4445 { 4446 MachineClass *mc = MACHINE_CLASS(oc); 4447 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4448 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4449 NMIClass *nc = NMI_CLASS(oc); 4450 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4451 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4452 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4453 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4454 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4455 4456 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4457 mc->ignore_boot_device_suffixes = true; 4458 4459 /* 4460 * We set up the default / latest behaviour here. The class_init 4461 * functions for the specific versioned machine types can override 4462 * these details for backwards compatibility 4463 */ 4464 mc->init = spapr_machine_init; 4465 mc->reset = spapr_machine_reset; 4466 mc->block_default_type = IF_SCSI; 4467 mc->max_cpus = 1024; 4468 mc->no_parallel = 1; 4469 mc->default_boot_order = ""; 4470 mc->default_ram_size = 512 * MiB; 4471 mc->default_ram_id = "ppc_spapr.ram"; 4472 mc->default_display = "std"; 4473 mc->kvm_type = spapr_kvm_type; 4474 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4475 mc->pci_allow_0_address = true; 4476 assert(!mc->get_hotplug_handler); 4477 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4478 hc->pre_plug = spapr_machine_device_pre_plug; 4479 hc->plug = spapr_machine_device_plug; 4480 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4481 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4482 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4483 hc->unplug_request = spapr_machine_device_unplug_request; 4484 hc->unplug = spapr_machine_device_unplug; 4485 4486 smc->dr_lmb_enabled = true; 4487 smc->update_dt_enabled = true; 4488 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4489 mc->has_hotpluggable_cpus = true; 4490 mc->nvdimm_supported = true; 4491 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4492 fwc->get_dev_path = spapr_get_fw_dev_path; 4493 nc->nmi_monitor_handler = spapr_nmi; 4494 smc->phb_placement = spapr_phb_placement; 4495 vhc->hypercall = emulate_spapr_hypercall; 4496 vhc->hpt_mask = spapr_hpt_mask; 4497 vhc->map_hptes = spapr_map_hptes; 4498 vhc->unmap_hptes = spapr_unmap_hptes; 4499 vhc->hpte_set_c = spapr_hpte_set_c; 4500 vhc->hpte_set_r = spapr_hpte_set_r; 4501 vhc->get_pate = spapr_get_pate; 4502 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4503 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4504 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4505 xic->ics_get = spapr_ics_get; 4506 xic->ics_resend = spapr_ics_resend; 4507 xic->icp_get = spapr_icp_get; 4508 ispc->print_info = spapr_pic_print_info; 4509 /* Force NUMA node memory size to be a multiple of 4510 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4511 * in which LMBs are represented and hot-added 4512 */ 4513 mc->numa_mem_align_shift = 28; 4514 mc->auto_enable_numa = true; 4515 4516 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4517 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4518 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4519 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4520 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4521 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4522 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4523 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4524 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4525 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4526 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4527 spapr_caps_add_properties(smc); 4528 smc->irq = &spapr_irq_dual; 4529 smc->dr_phb_enabled = true; 4530 smc->linux_pci_probe = true; 4531 smc->smp_threads_vsmt = true; 4532 smc->nr_xirqs = SPAPR_NR_XIRQS; 4533 xfc->match_nvt = spapr_match_nvt; 4534 } 4535 4536 static const TypeInfo spapr_machine_info = { 4537 .name = TYPE_SPAPR_MACHINE, 4538 .parent = TYPE_MACHINE, 4539 .abstract = true, 4540 .instance_size = sizeof(SpaprMachineState), 4541 .instance_init = spapr_instance_init, 4542 .instance_finalize = spapr_machine_finalizefn, 4543 .class_size = sizeof(SpaprMachineClass), 4544 .class_init = spapr_machine_class_init, 4545 .interfaces = (InterfaceInfo[]) { 4546 { TYPE_FW_PATH_PROVIDER }, 4547 { TYPE_NMI }, 4548 { TYPE_HOTPLUG_HANDLER }, 4549 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4550 { TYPE_XICS_FABRIC }, 4551 { TYPE_INTERRUPT_STATS_PROVIDER }, 4552 { TYPE_XIVE_FABRIC }, 4553 { } 4554 }, 4555 }; 4556 4557 static void spapr_machine_latest_class_options(MachineClass *mc) 4558 { 4559 mc->alias = "pseries"; 4560 mc->is_default = true; 4561 } 4562 4563 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4564 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4565 void *data) \ 4566 { \ 4567 MachineClass *mc = MACHINE_CLASS(oc); \ 4568 spapr_machine_##suffix##_class_options(mc); \ 4569 if (latest) { \ 4570 spapr_machine_latest_class_options(mc); \ 4571 } \ 4572 } \ 4573 static const TypeInfo spapr_machine_##suffix##_info = { \ 4574 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4575 .parent = TYPE_SPAPR_MACHINE, \ 4576 .class_init = spapr_machine_##suffix##_class_init, \ 4577 }; \ 4578 static void spapr_machine_register_##suffix(void) \ 4579 { \ 4580 type_register(&spapr_machine_##suffix##_info); \ 4581 } \ 4582 type_init(spapr_machine_register_##suffix) 4583 4584 /* 4585 * pseries-5.2 4586 */ 4587 static void spapr_machine_5_2_class_options(MachineClass *mc) 4588 { 4589 /* Defaults for the latest behaviour inherited from the base class */ 4590 } 4591 4592 DEFINE_SPAPR_MACHINE(5_2, "5.2", true); 4593 4594 /* 4595 * pseries-5.1 4596 */ 4597 static void spapr_machine_5_1_class_options(MachineClass *mc) 4598 { 4599 spapr_machine_5_2_class_options(mc); 4600 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4601 } 4602 4603 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4604 4605 /* 4606 * pseries-5.0 4607 */ 4608 static void spapr_machine_5_0_class_options(MachineClass *mc) 4609 { 4610 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4611 static GlobalProperty compat[] = { 4612 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4613 }; 4614 4615 spapr_machine_5_1_class_options(mc); 4616 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4617 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4618 mc->numa_mem_supported = true; 4619 smc->pre_5_1_assoc_refpoints = true; 4620 } 4621 4622 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4623 4624 /* 4625 * pseries-4.2 4626 */ 4627 static void spapr_machine_4_2_class_options(MachineClass *mc) 4628 { 4629 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4630 4631 spapr_machine_5_0_class_options(mc); 4632 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4633 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4634 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4635 smc->rma_limit = 16 * GiB; 4636 mc->nvdimm_supported = false; 4637 } 4638 4639 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4640 4641 /* 4642 * pseries-4.1 4643 */ 4644 static void spapr_machine_4_1_class_options(MachineClass *mc) 4645 { 4646 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4647 static GlobalProperty compat[] = { 4648 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4649 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4650 }; 4651 4652 spapr_machine_4_2_class_options(mc); 4653 smc->linux_pci_probe = false; 4654 smc->smp_threads_vsmt = false; 4655 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4656 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4657 } 4658 4659 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4660 4661 /* 4662 * pseries-4.0 4663 */ 4664 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4665 uint64_t *buid, hwaddr *pio, 4666 hwaddr *mmio32, hwaddr *mmio64, 4667 unsigned n_dma, uint32_t *liobns, 4668 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4669 { 4670 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, 4671 nv2gpa, nv2atsd, errp); 4672 *nv2gpa = 0; 4673 *nv2atsd = 0; 4674 } 4675 4676 static void spapr_machine_4_0_class_options(MachineClass *mc) 4677 { 4678 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4679 4680 spapr_machine_4_1_class_options(mc); 4681 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4682 smc->phb_placement = phb_placement_4_0; 4683 smc->irq = &spapr_irq_xics; 4684 smc->pre_4_1_migration = true; 4685 } 4686 4687 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4688 4689 /* 4690 * pseries-3.1 4691 */ 4692 static void spapr_machine_3_1_class_options(MachineClass *mc) 4693 { 4694 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4695 4696 spapr_machine_4_0_class_options(mc); 4697 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4698 4699 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4700 smc->update_dt_enabled = false; 4701 smc->dr_phb_enabled = false; 4702 smc->broken_host_serial_model = true; 4703 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4704 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4705 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4706 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4707 } 4708 4709 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4710 4711 /* 4712 * pseries-3.0 4713 */ 4714 4715 static void spapr_machine_3_0_class_options(MachineClass *mc) 4716 { 4717 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4718 4719 spapr_machine_3_1_class_options(mc); 4720 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4721 4722 smc->legacy_irq_allocation = true; 4723 smc->nr_xirqs = 0x400; 4724 smc->irq = &spapr_irq_xics_legacy; 4725 } 4726 4727 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4728 4729 /* 4730 * pseries-2.12 4731 */ 4732 static void spapr_machine_2_12_class_options(MachineClass *mc) 4733 { 4734 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4735 static GlobalProperty compat[] = { 4736 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4737 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4738 }; 4739 4740 spapr_machine_3_0_class_options(mc); 4741 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4742 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4743 4744 /* We depend on kvm_enabled() to choose a default value for the 4745 * hpt-max-page-size capability. Of course we can't do it here 4746 * because this is too early and the HW accelerator isn't initialzed 4747 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4748 */ 4749 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4750 } 4751 4752 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4753 4754 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4755 { 4756 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4757 4758 spapr_machine_2_12_class_options(mc); 4759 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4760 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4761 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4762 } 4763 4764 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4765 4766 /* 4767 * pseries-2.11 4768 */ 4769 4770 static void spapr_machine_2_11_class_options(MachineClass *mc) 4771 { 4772 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4773 4774 spapr_machine_2_12_class_options(mc); 4775 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4776 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4777 } 4778 4779 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4780 4781 /* 4782 * pseries-2.10 4783 */ 4784 4785 static void spapr_machine_2_10_class_options(MachineClass *mc) 4786 { 4787 spapr_machine_2_11_class_options(mc); 4788 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4789 } 4790 4791 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4792 4793 /* 4794 * pseries-2.9 4795 */ 4796 4797 static void spapr_machine_2_9_class_options(MachineClass *mc) 4798 { 4799 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4800 static GlobalProperty compat[] = { 4801 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4802 }; 4803 4804 spapr_machine_2_10_class_options(mc); 4805 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4806 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4807 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4808 smc->pre_2_10_has_unused_icps = true; 4809 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4810 } 4811 4812 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4813 4814 /* 4815 * pseries-2.8 4816 */ 4817 4818 static void spapr_machine_2_8_class_options(MachineClass *mc) 4819 { 4820 static GlobalProperty compat[] = { 4821 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4822 }; 4823 4824 spapr_machine_2_9_class_options(mc); 4825 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4826 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4827 mc->numa_mem_align_shift = 23; 4828 } 4829 4830 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4831 4832 /* 4833 * pseries-2.7 4834 */ 4835 4836 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4837 uint64_t *buid, hwaddr *pio, 4838 hwaddr *mmio32, hwaddr *mmio64, 4839 unsigned n_dma, uint32_t *liobns, 4840 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4841 { 4842 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4843 const uint64_t base_buid = 0x800000020000000ULL; 4844 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4845 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4846 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4847 const uint32_t max_index = 255; 4848 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4849 4850 uint64_t ram_top = MACHINE(spapr)->ram_size; 4851 hwaddr phb0_base, phb_base; 4852 int i; 4853 4854 /* Do we have device memory? */ 4855 if (MACHINE(spapr)->maxram_size > ram_top) { 4856 /* Can't just use maxram_size, because there may be an 4857 * alignment gap between normal and device memory regions 4858 */ 4859 ram_top = MACHINE(spapr)->device_memory->base + 4860 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4861 } 4862 4863 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4864 4865 if (index > max_index) { 4866 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4867 max_index); 4868 return; 4869 } 4870 4871 *buid = base_buid + index; 4872 for (i = 0; i < n_dma; ++i) { 4873 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4874 } 4875 4876 phb_base = phb0_base + index * phb_spacing; 4877 *pio = phb_base + pio_offset; 4878 *mmio32 = phb_base + mmio_offset; 4879 /* 4880 * We don't set the 64-bit MMIO window, relying on the PHB's 4881 * fallback behaviour of automatically splitting a large "32-bit" 4882 * window into contiguous 32-bit and 64-bit windows 4883 */ 4884 4885 *nv2gpa = 0; 4886 *nv2atsd = 0; 4887 } 4888 4889 static void spapr_machine_2_7_class_options(MachineClass *mc) 4890 { 4891 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4892 static GlobalProperty compat[] = { 4893 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4894 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4895 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4896 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4897 }; 4898 4899 spapr_machine_2_8_class_options(mc); 4900 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4901 mc->default_machine_opts = "modern-hotplug-events=off"; 4902 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4903 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4904 smc->phb_placement = phb_placement_2_7; 4905 } 4906 4907 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4908 4909 /* 4910 * pseries-2.6 4911 */ 4912 4913 static void spapr_machine_2_6_class_options(MachineClass *mc) 4914 { 4915 static GlobalProperty compat[] = { 4916 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4917 }; 4918 4919 spapr_machine_2_7_class_options(mc); 4920 mc->has_hotpluggable_cpus = false; 4921 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4922 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4923 } 4924 4925 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4926 4927 /* 4928 * pseries-2.5 4929 */ 4930 4931 static void spapr_machine_2_5_class_options(MachineClass *mc) 4932 { 4933 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4934 static GlobalProperty compat[] = { 4935 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4936 }; 4937 4938 spapr_machine_2_6_class_options(mc); 4939 smc->use_ohci_by_default = true; 4940 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4941 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4942 } 4943 4944 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4945 4946 /* 4947 * pseries-2.4 4948 */ 4949 4950 static void spapr_machine_2_4_class_options(MachineClass *mc) 4951 { 4952 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4953 4954 spapr_machine_2_5_class_options(mc); 4955 smc->dr_lmb_enabled = false; 4956 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4957 } 4958 4959 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4960 4961 /* 4962 * pseries-2.3 4963 */ 4964 4965 static void spapr_machine_2_3_class_options(MachineClass *mc) 4966 { 4967 static GlobalProperty compat[] = { 4968 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4969 }; 4970 spapr_machine_2_4_class_options(mc); 4971 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4972 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4973 } 4974 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4975 4976 /* 4977 * pseries-2.2 4978 */ 4979 4980 static void spapr_machine_2_2_class_options(MachineClass *mc) 4981 { 4982 static GlobalProperty compat[] = { 4983 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4984 }; 4985 4986 spapr_machine_2_3_class_options(mc); 4987 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4988 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4989 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4990 } 4991 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4992 4993 /* 4994 * pseries-2.1 4995 */ 4996 4997 static void spapr_machine_2_1_class_options(MachineClass *mc) 4998 { 4999 spapr_machine_2_2_class_options(mc); 5000 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 5001 } 5002 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 5003 5004 static void spapr_machine_register_types(void) 5005 { 5006 type_register_static(&spapr_machine_info); 5007 } 5008 5009 type_init(spapr_machine_register_types) 5010