1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "sysemu/sysemu.h" 28 #include "hw/hw.h" 29 #include "elf.h" 30 #include "net/net.h" 31 #include "sysemu/blockdev.h" 32 #include "sysemu/cpus.h" 33 #include "sysemu/kvm.h" 34 #include "kvm_ppc.h" 35 #include "mmu-hash64.h" 36 37 #include "hw/boards.h" 38 #include "hw/ppc/ppc.h" 39 #include "hw/loader.h" 40 41 #include "hw/ppc/spapr.h" 42 #include "hw/ppc/spapr_vio.h" 43 #include "hw/pci-host/spapr.h" 44 #include "hw/ppc/xics.h" 45 #include "hw/pci/msi.h" 46 47 #include "hw/pci/pci.h" 48 49 #include "exec/address-spaces.h" 50 #include "hw/usb.h" 51 #include "qemu/config-file.h" 52 53 #include <libfdt.h> 54 55 /* SLOF memory layout: 56 * 57 * SLOF raw image loaded at 0, copies its romfs right below the flat 58 * device-tree, then position SLOF itself 31M below that 59 * 60 * So we set FW_OVERHEAD to 40MB which should account for all of that 61 * and more 62 * 63 * We load our kernel at 4M, leaving space for SLOF initial image 64 */ 65 #define FDT_MAX_SIZE 0x40000 66 #define RTAS_MAX_SIZE 0x10000 67 #define FW_MAX_SIZE 0x400000 68 #define FW_FILE_NAME "slof.bin" 69 #define FW_OVERHEAD 0x2800000 70 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 71 72 #define MIN_RMA_SLOF 128UL 73 74 #define TIMEBASE_FREQ 512000000ULL 75 76 #define MAX_CPUS 256 77 #define XICS_IRQS 1024 78 79 #define PHANDLE_XICP 0x00001111 80 81 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 82 83 sPAPREnvironment *spapr; 84 85 int spapr_allocate_irq(int hint, bool lsi) 86 { 87 int irq; 88 89 if (hint) { 90 irq = hint; 91 if (hint >= spapr->next_irq) { 92 spapr->next_irq = hint + 1; 93 } 94 /* FIXME: we should probably check for collisions somehow */ 95 } else { 96 irq = spapr->next_irq++; 97 } 98 99 /* Configure irq type */ 100 if (!xics_get_qirq(spapr->icp, irq)) { 101 return 0; 102 } 103 104 xics_set_irq_type(spapr->icp, irq, lsi); 105 106 return irq; 107 } 108 109 /* 110 * Allocate block of consequtive IRQs, returns a number of the first. 111 * If msi==true, aligns the first IRQ number to num. 112 */ 113 int spapr_allocate_irq_block(int num, bool lsi, bool msi) 114 { 115 int first = -1; 116 int i, hint = 0; 117 118 /* 119 * MSIMesage::data is used for storing VIRQ so 120 * it has to be aligned to num to support multiple 121 * MSI vectors. MSI-X is not affected by this. 122 * The hint is used for the first IRQ, the rest should 123 * be allocated continously. 124 */ 125 if (msi) { 126 assert((num == 1) || (num == 2) || (num == 4) || 127 (num == 8) || (num == 16) || (num == 32)); 128 hint = (spapr->next_irq + num - 1) & ~(num - 1); 129 } 130 131 for (i = 0; i < num; ++i) { 132 int irq; 133 134 irq = spapr_allocate_irq(hint, lsi); 135 if (!irq) { 136 return -1; 137 } 138 139 if (0 == i) { 140 first = irq; 141 hint = 0; 142 } 143 144 /* If the above doesn't create a consecutive block then that's 145 * an internal bug */ 146 assert(irq == (first + i)); 147 } 148 149 return first; 150 } 151 152 static XICSState *try_create_xics(const char *type, int nr_servers, 153 int nr_irqs) 154 { 155 DeviceState *dev; 156 157 dev = qdev_create(NULL, type); 158 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 159 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 160 if (qdev_init(dev) < 0) { 161 return NULL; 162 } 163 164 return XICS_COMMON(dev); 165 } 166 167 static XICSState *xics_system_init(int nr_servers, int nr_irqs) 168 { 169 XICSState *icp = NULL; 170 171 if (kvm_enabled()) { 172 QemuOpts *machine_opts = qemu_get_machine_opts(); 173 bool irqchip_allowed = qemu_opt_get_bool(machine_opts, 174 "kernel_irqchip", true); 175 bool irqchip_required = qemu_opt_get_bool(machine_opts, 176 "kernel_irqchip", false); 177 if (irqchip_allowed) { 178 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs); 179 } 180 181 if (irqchip_required && !icp) { 182 perror("Failed to create in-kernel XICS\n"); 183 abort(); 184 } 185 } 186 187 if (!icp) { 188 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs); 189 } 190 191 if (!icp) { 192 perror("Failed to create XICS\n"); 193 abort(); 194 } 195 196 return icp; 197 } 198 199 static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) 200 { 201 int ret = 0, offset; 202 CPUState *cpu; 203 char cpu_model[32]; 204 int smt = kvmppc_smt_threads(); 205 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 206 207 assert(spapr->cpu_model); 208 209 CPU_FOREACH(cpu) { 210 uint32_t associativity[] = {cpu_to_be32(0x5), 211 cpu_to_be32(0x0), 212 cpu_to_be32(0x0), 213 cpu_to_be32(0x0), 214 cpu_to_be32(cpu->numa_node), 215 cpu_to_be32(cpu->cpu_index)}; 216 217 if ((cpu->cpu_index % smt) != 0) { 218 continue; 219 } 220 221 snprintf(cpu_model, 32, "/cpus/%s@%x", spapr->cpu_model, 222 cpu->cpu_index); 223 224 offset = fdt_path_offset(fdt, cpu_model); 225 if (offset < 0) { 226 return offset; 227 } 228 229 if (nb_numa_nodes > 1) { 230 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 231 sizeof(associativity)); 232 if (ret < 0) { 233 return ret; 234 } 235 } 236 237 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 238 pft_size_prop, sizeof(pft_size_prop)); 239 if (ret < 0) { 240 return ret; 241 } 242 } 243 return ret; 244 } 245 246 247 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 248 size_t maxsize) 249 { 250 size_t maxcells = maxsize / sizeof(uint32_t); 251 int i, j, count; 252 uint32_t *p = prop; 253 254 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 255 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 256 257 if (!sps->page_shift) { 258 break; 259 } 260 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 261 if (sps->enc[count].page_shift == 0) { 262 break; 263 } 264 } 265 if ((p - prop) >= (maxcells - 3 - count * 2)) { 266 break; 267 } 268 *(p++) = cpu_to_be32(sps->page_shift); 269 *(p++) = cpu_to_be32(sps->slb_enc); 270 *(p++) = cpu_to_be32(count); 271 for (j = 0; j < count; j++) { 272 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 273 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 274 } 275 } 276 277 return (p - prop) * sizeof(uint32_t); 278 } 279 280 #define _FDT(exp) \ 281 do { \ 282 int ret = (exp); \ 283 if (ret < 0) { \ 284 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 285 #exp, fdt_strerror(ret)); \ 286 exit(1); \ 287 } \ 288 } while (0) 289 290 291 static void *spapr_create_fdt_skel(const char *cpu_model, 292 hwaddr initrd_base, 293 hwaddr initrd_size, 294 hwaddr kernel_size, 295 bool little_endian, 296 const char *boot_device, 297 const char *kernel_cmdline, 298 uint32_t epow_irq) 299 { 300 void *fdt; 301 CPUState *cs; 302 uint32_t start_prop = cpu_to_be32(initrd_base); 303 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 304 char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt" 305 "\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk\0hcall-set-mode"; 306 char qemu_hypertas_prop[] = "hcall-memop1"; 307 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 308 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; 309 char *modelname; 310 int i, smt = kvmppc_smt_threads(); 311 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 312 313 fdt = g_malloc0(FDT_MAX_SIZE); 314 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 315 316 if (kernel_size) { 317 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 318 } 319 if (initrd_size) { 320 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 321 } 322 _FDT((fdt_finish_reservemap(fdt))); 323 324 /* Root node */ 325 _FDT((fdt_begin_node(fdt, ""))); 326 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 327 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 328 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 329 330 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 331 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 332 333 /* /chosen */ 334 _FDT((fdt_begin_node(fdt, "chosen"))); 335 336 /* Set Form1_affinity */ 337 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 338 339 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 340 _FDT((fdt_property(fdt, "linux,initrd-start", 341 &start_prop, sizeof(start_prop)))); 342 _FDT((fdt_property(fdt, "linux,initrd-end", 343 &end_prop, sizeof(end_prop)))); 344 if (kernel_size) { 345 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 346 cpu_to_be64(kernel_size) }; 347 348 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 349 if (little_endian) { 350 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 351 } 352 } 353 if (boot_device) { 354 _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device))); 355 } 356 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 357 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 358 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 359 360 _FDT((fdt_end_node(fdt))); 361 362 /* cpus */ 363 _FDT((fdt_begin_node(fdt, "cpus"))); 364 365 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 366 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 367 368 modelname = g_strdup(cpu_model); 369 370 for (i = 0; i < strlen(modelname); i++) { 371 modelname[i] = toupper(modelname[i]); 372 } 373 374 /* This is needed during FDT finalization */ 375 spapr->cpu_model = g_strdup(modelname); 376 377 CPU_FOREACH(cs) { 378 PowerPCCPU *cpu = POWERPC_CPU(cs); 379 CPUPPCState *env = &cpu->env; 380 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 381 int index = cs->cpu_index; 382 uint32_t servers_prop[smp_threads]; 383 uint32_t gservers_prop[smp_threads * 2]; 384 char *nodename; 385 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 386 0xffffffff, 0xffffffff}; 387 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 388 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 389 uint32_t page_sizes_prop[64]; 390 size_t page_sizes_prop_size; 391 392 if ((index % smt) != 0) { 393 continue; 394 } 395 396 nodename = g_strdup_printf("%s@%x", modelname, index); 397 398 _FDT((fdt_begin_node(fdt, nodename))); 399 400 g_free(nodename); 401 402 _FDT((fdt_property_cell(fdt, "reg", index))); 403 _FDT((fdt_property_string(fdt, "device_type", "cpu"))); 404 405 _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); 406 _FDT((fdt_property_cell(fdt, "d-cache-block-size", 407 env->dcache_line_size))); 408 _FDT((fdt_property_cell(fdt, "d-cache-line-size", 409 env->dcache_line_size))); 410 _FDT((fdt_property_cell(fdt, "i-cache-block-size", 411 env->icache_line_size))); 412 _FDT((fdt_property_cell(fdt, "i-cache-line-size", 413 env->icache_line_size))); 414 415 if (pcc->l1_dcache_size) { 416 _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size))); 417 } else { 418 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 419 } 420 if (pcc->l1_icache_size) { 421 _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size))); 422 } else { 423 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 424 } 425 426 _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq))); 427 _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq))); 428 _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); 429 _FDT((fdt_property_string(fdt, "status", "okay"))); 430 _FDT((fdt_property(fdt, "64-bit", NULL, 0))); 431 432 /* Build interrupt servers and gservers properties */ 433 for (i = 0; i < smp_threads; i++) { 434 servers_prop[i] = cpu_to_be32(index + i); 435 /* Hack, direct the group queues back to cpu 0 */ 436 gservers_prop[i*2] = cpu_to_be32(index + i); 437 gservers_prop[i*2 + 1] = 0; 438 } 439 _FDT((fdt_property(fdt, "ibm,ppc-interrupt-server#s", 440 servers_prop, sizeof(servers_prop)))); 441 _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s", 442 gservers_prop, sizeof(gservers_prop)))); 443 444 if (env->spr_cb[SPR_PURR].oea_read) { 445 _FDT((fdt_property(fdt, "ibm,purr", NULL, 0))); 446 } 447 448 if (env->mmu_model & POWERPC_MMU_1TSEG) { 449 _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", 450 segs, sizeof(segs)))); 451 } 452 453 /* Advertise VMX/VSX (vector extensions) if available 454 * 0 / no property == no vector extensions 455 * 1 == VMX / Altivec available 456 * 2 == VSX available */ 457 if (env->insns_flags & PPC_ALTIVEC) { 458 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 459 460 _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx))); 461 } 462 463 /* Advertise DFP (Decimal Floating Point) if available 464 * 0 / no property == no DFP 465 * 1 == DFP available */ 466 if (env->insns_flags2 & PPC2_DFP) { 467 _FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); 468 } 469 470 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 471 sizeof(page_sizes_prop)); 472 if (page_sizes_prop_size) { 473 _FDT((fdt_property(fdt, "ibm,segment-page-sizes", 474 page_sizes_prop, page_sizes_prop_size))); 475 } 476 477 _FDT((fdt_end_node(fdt))); 478 } 479 480 g_free(modelname); 481 482 _FDT((fdt_end_node(fdt))); 483 484 /* RTAS */ 485 _FDT((fdt_begin_node(fdt, "rtas"))); 486 487 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop, 488 sizeof(hypertas_prop)))); 489 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas_prop, 490 sizeof(qemu_hypertas_prop)))); 491 492 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 493 refpoints, sizeof(refpoints)))); 494 495 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 496 497 _FDT((fdt_end_node(fdt))); 498 499 /* interrupt controller */ 500 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 501 502 _FDT((fdt_property_string(fdt, "device_type", 503 "PowerPC-External-Interrupt-Presentation"))); 504 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 505 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 506 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 507 interrupt_server_ranges_prop, 508 sizeof(interrupt_server_ranges_prop)))); 509 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 510 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 511 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 512 513 _FDT((fdt_end_node(fdt))); 514 515 /* vdevice */ 516 _FDT((fdt_begin_node(fdt, "vdevice"))); 517 518 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 519 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 520 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 521 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 522 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 523 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 524 525 _FDT((fdt_end_node(fdt))); 526 527 /* event-sources */ 528 spapr_events_fdt_skel(fdt, epow_irq); 529 530 _FDT((fdt_end_node(fdt))); /* close root node */ 531 _FDT((fdt_finish(fdt))); 532 533 return fdt; 534 } 535 536 static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt) 537 { 538 uint32_t associativity[] = {cpu_to_be32(0x4), cpu_to_be32(0x0), 539 cpu_to_be32(0x0), cpu_to_be32(0x0), 540 cpu_to_be32(0x0)}; 541 char mem_name[32]; 542 hwaddr node0_size, mem_start; 543 uint64_t mem_reg_property[2]; 544 int i, off; 545 546 /* memory node(s) */ 547 node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size; 548 if (spapr->rma_size > node0_size) { 549 spapr->rma_size = node0_size; 550 } 551 552 /* RMA */ 553 mem_reg_property[0] = 0; 554 mem_reg_property[1] = cpu_to_be64(spapr->rma_size); 555 off = fdt_add_subnode(fdt, 0, "memory@0"); 556 _FDT(off); 557 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 558 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 559 sizeof(mem_reg_property)))); 560 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 561 sizeof(associativity)))); 562 563 /* RAM: Node 0 */ 564 if (node0_size > spapr->rma_size) { 565 mem_reg_property[0] = cpu_to_be64(spapr->rma_size); 566 mem_reg_property[1] = cpu_to_be64(node0_size - spapr->rma_size); 567 568 sprintf(mem_name, "memory@" TARGET_FMT_lx, spapr->rma_size); 569 off = fdt_add_subnode(fdt, 0, mem_name); 570 _FDT(off); 571 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 572 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 573 sizeof(mem_reg_property)))); 574 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 575 sizeof(associativity)))); 576 } 577 578 /* RAM: Node 1 and beyond */ 579 mem_start = node0_size; 580 for (i = 1; i < nb_numa_nodes; i++) { 581 mem_reg_property[0] = cpu_to_be64(mem_start); 582 mem_reg_property[1] = cpu_to_be64(node_mem[i]); 583 associativity[3] = associativity[4] = cpu_to_be32(i); 584 sprintf(mem_name, "memory@" TARGET_FMT_lx, mem_start); 585 off = fdt_add_subnode(fdt, 0, mem_name); 586 _FDT(off); 587 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 588 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 589 sizeof(mem_reg_property)))); 590 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 591 sizeof(associativity)))); 592 mem_start += node_mem[i]; 593 } 594 595 return 0; 596 } 597 598 static void spapr_finalize_fdt(sPAPREnvironment *spapr, 599 hwaddr fdt_addr, 600 hwaddr rtas_addr, 601 hwaddr rtas_size) 602 { 603 int ret; 604 void *fdt; 605 sPAPRPHBState *phb; 606 607 fdt = g_malloc(FDT_MAX_SIZE); 608 609 /* open out the base tree into a temp buffer for the final tweaks */ 610 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 611 612 ret = spapr_populate_memory(spapr, fdt); 613 if (ret < 0) { 614 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 615 exit(1); 616 } 617 618 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 619 if (ret < 0) { 620 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 621 exit(1); 622 } 623 624 QLIST_FOREACH(phb, &spapr->phbs, list) { 625 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 626 } 627 628 if (ret < 0) { 629 fprintf(stderr, "couldn't setup PCI devices in fdt\n"); 630 exit(1); 631 } 632 633 /* RTAS */ 634 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 635 if (ret < 0) { 636 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 637 } 638 639 /* Advertise NUMA via ibm,associativity */ 640 ret = spapr_fixup_cpu_dt(fdt, spapr); 641 if (ret < 0) { 642 fprintf(stderr, "Couldn't finalize CPU device tree properties\n"); 643 } 644 645 if (!spapr->has_graphics) { 646 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 647 } 648 649 _FDT((fdt_pack(fdt))); 650 651 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 652 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n", 653 fdt_totalsize(fdt), FDT_MAX_SIZE); 654 exit(1); 655 } 656 657 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 658 659 g_free(fdt); 660 } 661 662 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 663 { 664 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 665 } 666 667 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 668 { 669 CPUPPCState *env = &cpu->env; 670 671 if (msr_pr) { 672 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 673 env->gpr[3] = H_PRIVILEGE; 674 } else { 675 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 676 } 677 } 678 679 static void spapr_reset_htab(sPAPREnvironment *spapr) 680 { 681 long shift; 682 683 /* allocate hash page table. For now we always make this 16mb, 684 * later we should probably make it scale to the size of guest 685 * RAM */ 686 687 shift = kvmppc_reset_htab(spapr->htab_shift); 688 689 if (shift > 0) { 690 /* Kernel handles htab, we don't need to allocate one */ 691 spapr->htab_shift = shift; 692 } else { 693 if (!spapr->htab) { 694 /* Allocate an htab if we don't yet have one */ 695 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); 696 } 697 698 /* And clear it */ 699 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 700 } 701 702 /* Update the RMA size if necessary */ 703 if (spapr->vrma_adjust) { 704 spapr->rma_size = kvmppc_rma_size(ram_size, spapr->htab_shift); 705 } 706 } 707 708 static void ppc_spapr_reset(void) 709 { 710 PowerPCCPU *first_ppc_cpu; 711 712 /* Reset the hash table & recalc the RMA */ 713 spapr_reset_htab(spapr); 714 715 qemu_devices_reset(); 716 717 /* Load the fdt */ 718 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 719 spapr->rtas_size); 720 721 /* Set up the entry state */ 722 first_ppc_cpu = POWERPC_CPU(first_cpu); 723 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 724 first_ppc_cpu->env.gpr[5] = 0; 725 first_cpu->halted = 0; 726 first_ppc_cpu->env.nip = spapr->entry_point; 727 728 } 729 730 static void spapr_cpu_reset(void *opaque) 731 { 732 PowerPCCPU *cpu = opaque; 733 CPUState *cs = CPU(cpu); 734 CPUPPCState *env = &cpu->env; 735 736 cpu_reset(cs); 737 738 /* All CPUs start halted. CPU0 is unhalted from the machine level 739 * reset code and the rest are explicitly started up by the guest 740 * using an RTAS call */ 741 cs->halted = 1; 742 743 env->spr[SPR_HIOR] = 0; 744 745 env->external_htab = (uint8_t *)spapr->htab; 746 env->htab_base = -1; 747 env->htab_mask = HTAB_SIZE(spapr) - 1; 748 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | 749 (spapr->htab_shift - 18); 750 } 751 752 static void spapr_create_nvram(sPAPREnvironment *spapr) 753 { 754 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 755 const char *drivename = qemu_opt_get(qemu_get_machine_opts(), "nvram"); 756 757 if (drivename) { 758 BlockDriverState *bs; 759 760 bs = bdrv_find(drivename); 761 if (!bs) { 762 fprintf(stderr, "No such block device \"%s\" for nvram\n", 763 drivename); 764 exit(1); 765 } 766 qdev_prop_set_drive_nofail(dev, "drive", bs); 767 } 768 769 qdev_init_nofail(dev); 770 771 spapr->nvram = (struct sPAPRNVRAM *)dev; 772 } 773 774 /* Returns whether we want to use VGA or not */ 775 static int spapr_vga_init(PCIBus *pci_bus) 776 { 777 switch (vga_interface_type) { 778 case VGA_NONE: 779 case VGA_STD: 780 return pci_vga_init(pci_bus) != NULL; 781 default: 782 fprintf(stderr, "This vga model is not supported," 783 "currently it only supports -vga std\n"); 784 exit(0); 785 break; 786 } 787 } 788 789 static const VMStateDescription vmstate_spapr = { 790 .name = "spapr", 791 .version_id = 1, 792 .minimum_version_id = 1, 793 .minimum_version_id_old = 1, 794 .fields = (VMStateField []) { 795 VMSTATE_UINT32(next_irq, sPAPREnvironment), 796 797 /* RTC offset */ 798 VMSTATE_UINT64(rtc_offset, sPAPREnvironment), 799 800 VMSTATE_END_OF_LIST() 801 }, 802 }; 803 804 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 805 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 806 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 807 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 808 809 static int htab_save_setup(QEMUFile *f, void *opaque) 810 { 811 sPAPREnvironment *spapr = opaque; 812 813 /* "Iteration" header */ 814 qemu_put_be32(f, spapr->htab_shift); 815 816 if (spapr->htab) { 817 spapr->htab_save_index = 0; 818 spapr->htab_first_pass = true; 819 } else { 820 assert(kvm_enabled()); 821 822 spapr->htab_fd = kvmppc_get_htab_fd(false); 823 if (spapr->htab_fd < 0) { 824 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", 825 strerror(errno)); 826 return -1; 827 } 828 } 829 830 831 return 0; 832 } 833 834 static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr, 835 int64_t max_ns) 836 { 837 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 838 int index = spapr->htab_save_index; 839 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 840 841 assert(spapr->htab_first_pass); 842 843 do { 844 int chunkstart; 845 846 /* Consume invalid HPTEs */ 847 while ((index < htabslots) 848 && !HPTE_VALID(HPTE(spapr->htab, index))) { 849 index++; 850 CLEAN_HPTE(HPTE(spapr->htab, index)); 851 } 852 853 /* Consume valid HPTEs */ 854 chunkstart = index; 855 while ((index < htabslots) 856 && HPTE_VALID(HPTE(spapr->htab, index))) { 857 index++; 858 CLEAN_HPTE(HPTE(spapr->htab, index)); 859 } 860 861 if (index > chunkstart) { 862 int n_valid = index - chunkstart; 863 864 qemu_put_be32(f, chunkstart); 865 qemu_put_be16(f, n_valid); 866 qemu_put_be16(f, 0); 867 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 868 HASH_PTE_SIZE_64 * n_valid); 869 870 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 871 break; 872 } 873 } 874 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 875 876 if (index >= htabslots) { 877 assert(index == htabslots); 878 index = 0; 879 spapr->htab_first_pass = false; 880 } 881 spapr->htab_save_index = index; 882 } 883 884 static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, 885 int64_t max_ns) 886 { 887 bool final = max_ns < 0; 888 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 889 int examined = 0, sent = 0; 890 int index = spapr->htab_save_index; 891 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 892 893 assert(!spapr->htab_first_pass); 894 895 do { 896 int chunkstart, invalidstart; 897 898 /* Consume non-dirty HPTEs */ 899 while ((index < htabslots) 900 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 901 index++; 902 examined++; 903 } 904 905 chunkstart = index; 906 /* Consume valid dirty HPTEs */ 907 while ((index < htabslots) 908 && HPTE_DIRTY(HPTE(spapr->htab, index)) 909 && HPTE_VALID(HPTE(spapr->htab, index))) { 910 CLEAN_HPTE(HPTE(spapr->htab, index)); 911 index++; 912 examined++; 913 } 914 915 invalidstart = index; 916 /* Consume invalid dirty HPTEs */ 917 while ((index < htabslots) 918 && HPTE_DIRTY(HPTE(spapr->htab, index)) 919 && !HPTE_VALID(HPTE(spapr->htab, index))) { 920 CLEAN_HPTE(HPTE(spapr->htab, index)); 921 index++; 922 examined++; 923 } 924 925 if (index > chunkstart) { 926 int n_valid = invalidstart - chunkstart; 927 int n_invalid = index - invalidstart; 928 929 qemu_put_be32(f, chunkstart); 930 qemu_put_be16(f, n_valid); 931 qemu_put_be16(f, n_invalid); 932 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 933 HASH_PTE_SIZE_64 * n_valid); 934 sent += index - chunkstart; 935 936 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 937 break; 938 } 939 } 940 941 if (examined >= htabslots) { 942 break; 943 } 944 945 if (index >= htabslots) { 946 assert(index == htabslots); 947 index = 0; 948 } 949 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 950 951 if (index >= htabslots) { 952 assert(index == htabslots); 953 index = 0; 954 } 955 956 spapr->htab_save_index = index; 957 958 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 959 } 960 961 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 962 #define MAX_KVM_BUF_SIZE 2048 963 964 static int htab_save_iterate(QEMUFile *f, void *opaque) 965 { 966 sPAPREnvironment *spapr = opaque; 967 int rc = 0; 968 969 /* Iteration header */ 970 qemu_put_be32(f, 0); 971 972 if (!spapr->htab) { 973 assert(kvm_enabled()); 974 975 rc = kvmppc_save_htab(f, spapr->htab_fd, 976 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 977 if (rc < 0) { 978 return rc; 979 } 980 } else if (spapr->htab_first_pass) { 981 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 982 } else { 983 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 984 } 985 986 /* End marker */ 987 qemu_put_be32(f, 0); 988 qemu_put_be16(f, 0); 989 qemu_put_be16(f, 0); 990 991 return rc; 992 } 993 994 static int htab_save_complete(QEMUFile *f, void *opaque) 995 { 996 sPAPREnvironment *spapr = opaque; 997 998 /* Iteration header */ 999 qemu_put_be32(f, 0); 1000 1001 if (!spapr->htab) { 1002 int rc; 1003 1004 assert(kvm_enabled()); 1005 1006 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); 1007 if (rc < 0) { 1008 return rc; 1009 } 1010 close(spapr->htab_fd); 1011 spapr->htab_fd = -1; 1012 } else { 1013 htab_save_later_pass(f, spapr, -1); 1014 } 1015 1016 /* End marker */ 1017 qemu_put_be32(f, 0); 1018 qemu_put_be16(f, 0); 1019 qemu_put_be16(f, 0); 1020 1021 return 0; 1022 } 1023 1024 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1025 { 1026 sPAPREnvironment *spapr = opaque; 1027 uint32_t section_hdr; 1028 int fd = -1; 1029 1030 if (version_id < 1 || version_id > 1) { 1031 fprintf(stderr, "htab_load() bad version\n"); 1032 return -EINVAL; 1033 } 1034 1035 section_hdr = qemu_get_be32(f); 1036 1037 if (section_hdr) { 1038 /* First section, just the hash shift */ 1039 if (spapr->htab_shift != section_hdr) { 1040 return -EINVAL; 1041 } 1042 return 0; 1043 } 1044 1045 if (!spapr->htab) { 1046 assert(kvm_enabled()); 1047 1048 fd = kvmppc_get_htab_fd(true); 1049 if (fd < 0) { 1050 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", 1051 strerror(errno)); 1052 } 1053 } 1054 1055 while (true) { 1056 uint32_t index; 1057 uint16_t n_valid, n_invalid; 1058 1059 index = qemu_get_be32(f); 1060 n_valid = qemu_get_be16(f); 1061 n_invalid = qemu_get_be16(f); 1062 1063 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1064 /* End of Stream */ 1065 break; 1066 } 1067 1068 if ((index + n_valid + n_invalid) > 1069 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1070 /* Bad index in stream */ 1071 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " 1072 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, 1073 spapr->htab_shift); 1074 return -EINVAL; 1075 } 1076 1077 if (spapr->htab) { 1078 if (n_valid) { 1079 qemu_get_buffer(f, HPTE(spapr->htab, index), 1080 HASH_PTE_SIZE_64 * n_valid); 1081 } 1082 if (n_invalid) { 1083 memset(HPTE(spapr->htab, index + n_valid), 0, 1084 HASH_PTE_SIZE_64 * n_invalid); 1085 } 1086 } else { 1087 int rc; 1088 1089 assert(fd >= 0); 1090 1091 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1092 if (rc < 0) { 1093 return rc; 1094 } 1095 } 1096 } 1097 1098 if (!spapr->htab) { 1099 assert(fd >= 0); 1100 close(fd); 1101 } 1102 1103 return 0; 1104 } 1105 1106 static SaveVMHandlers savevm_htab_handlers = { 1107 .save_live_setup = htab_save_setup, 1108 .save_live_iterate = htab_save_iterate, 1109 .save_live_complete = htab_save_complete, 1110 .load_state = htab_load, 1111 }; 1112 1113 /* pSeries LPAR / sPAPR hardware init */ 1114 static void ppc_spapr_init(QEMUMachineInitArgs *args) 1115 { 1116 ram_addr_t ram_size = args->ram_size; 1117 const char *cpu_model = args->cpu_model; 1118 const char *kernel_filename = args->kernel_filename; 1119 const char *kernel_cmdline = args->kernel_cmdline; 1120 const char *initrd_filename = args->initrd_filename; 1121 const char *boot_device = args->boot_order; 1122 PowerPCCPU *cpu; 1123 CPUPPCState *env; 1124 PCIHostState *phb; 1125 int i; 1126 MemoryRegion *sysmem = get_system_memory(); 1127 MemoryRegion *ram = g_new(MemoryRegion, 1); 1128 hwaddr rma_alloc_size; 1129 uint32_t initrd_base = 0; 1130 long kernel_size = 0, initrd_size = 0; 1131 long load_limit, rtas_limit, fw_size; 1132 bool kernel_le = false; 1133 char *filename; 1134 1135 msi_supported = true; 1136 1137 spapr = g_malloc0(sizeof(*spapr)); 1138 QLIST_INIT(&spapr->phbs); 1139 1140 cpu_ppc_hypercall = emulate_spapr_hypercall; 1141 1142 /* Allocate RMA if necessary */ 1143 rma_alloc_size = kvmppc_alloc_rma("ppc_spapr.rma", sysmem); 1144 1145 if (rma_alloc_size == -1) { 1146 hw_error("qemu: Unable to create RMA\n"); 1147 exit(1); 1148 } 1149 1150 if (rma_alloc_size && (rma_alloc_size < ram_size)) { 1151 spapr->rma_size = rma_alloc_size; 1152 } else { 1153 spapr->rma_size = ram_size; 1154 1155 /* With KVM, we don't actually know whether KVM supports an 1156 * unbounded RMA (PR KVM) or is limited by the hash table size 1157 * (HV KVM using VRMA), so we always assume the latter 1158 * 1159 * In that case, we also limit the initial allocations for RTAS 1160 * etc... to 256M since we have no way to know what the VRMA size 1161 * is going to be as it depends on the size of the hash table 1162 * isn't determined yet. 1163 */ 1164 if (kvm_enabled()) { 1165 spapr->vrma_adjust = 1; 1166 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1167 } 1168 } 1169 1170 /* We place the device tree and RTAS just below either the top of the RMA, 1171 * or just below 2GB, whichever is lowere, so that it can be 1172 * processed with 32-bit real mode code if necessary */ 1173 rtas_limit = MIN(spapr->rma_size, 0x80000000); 1174 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1175 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 1176 load_limit = spapr->fdt_addr - FW_OVERHEAD; 1177 1178 /* We aim for a hash table of size 1/128 the size of RAM. The 1179 * normal rule of thumb is 1/64 the size of RAM, but that's much 1180 * more than needed for the Linux guests we support. */ 1181 spapr->htab_shift = 18; /* Minimum architected size */ 1182 while (spapr->htab_shift <= 46) { 1183 if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) { 1184 break; 1185 } 1186 spapr->htab_shift++; 1187 } 1188 1189 /* Set up Interrupt Controller before we create the VCPUs */ 1190 spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads, 1191 XICS_IRQS); 1192 spapr->next_irq = XICS_IRQ_BASE; 1193 1194 /* init CPUs */ 1195 if (cpu_model == NULL) { 1196 cpu_model = kvm_enabled() ? "host" : "POWER7"; 1197 } 1198 for (i = 0; i < smp_cpus; i++) { 1199 cpu = cpu_ppc_init(cpu_model); 1200 if (cpu == NULL) { 1201 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 1202 exit(1); 1203 } 1204 env = &cpu->env; 1205 1206 /* Set time-base frequency to 512 MHz */ 1207 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 1208 1209 /* PAPR always has exception vectors in RAM not ROM. To ensure this, 1210 * MSR[IP] should never be set. 1211 */ 1212 env->msr_mask &= ~(1 << 6); 1213 1214 /* Tell KVM that we're in PAPR mode */ 1215 if (kvm_enabled()) { 1216 kvmppc_set_papr(cpu); 1217 } 1218 1219 xics_cpu_setup(spapr->icp, cpu); 1220 1221 qemu_register_reset(spapr_cpu_reset, cpu); 1222 } 1223 1224 /* allocate RAM */ 1225 spapr->ram_limit = ram_size; 1226 if (spapr->ram_limit > rma_alloc_size) { 1227 ram_addr_t nonrma_base = rma_alloc_size; 1228 ram_addr_t nonrma_size = spapr->ram_limit - rma_alloc_size; 1229 1230 memory_region_init_ram(ram, NULL, "ppc_spapr.ram", nonrma_size); 1231 vmstate_register_ram_global(ram); 1232 memory_region_add_subregion(sysmem, nonrma_base, ram); 1233 } 1234 1235 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1236 spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr, 1237 rtas_limit - spapr->rtas_addr); 1238 if (spapr->rtas_size < 0) { 1239 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1240 exit(1); 1241 } 1242 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1243 hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n", 1244 spapr->rtas_size, RTAS_MAX_SIZE); 1245 exit(1); 1246 } 1247 g_free(filename); 1248 1249 /* Set up EPOW events infrastructure */ 1250 spapr_events_init(spapr); 1251 1252 /* Set up VIO bus */ 1253 spapr->vio_bus = spapr_vio_bus_init(); 1254 1255 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1256 if (serial_hds[i]) { 1257 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1258 } 1259 } 1260 1261 /* We always have at least the nvram device on VIO */ 1262 spapr_create_nvram(spapr); 1263 1264 /* Set up PCI */ 1265 spapr_pci_msi_init(spapr, SPAPR_PCI_MSI_WINDOW); 1266 spapr_pci_rtas_init(); 1267 1268 phb = spapr_create_phb(spapr, 0); 1269 1270 for (i = 0; i < nb_nics; i++) { 1271 NICInfo *nd = &nd_table[i]; 1272 1273 if (!nd->model) { 1274 nd->model = g_strdup("ibmveth"); 1275 } 1276 1277 if (strcmp(nd->model, "ibmveth") == 0) { 1278 spapr_vlan_create(spapr->vio_bus, nd); 1279 } else { 1280 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1281 } 1282 } 1283 1284 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1285 spapr_vscsi_create(spapr->vio_bus); 1286 } 1287 1288 /* Graphics */ 1289 if (spapr_vga_init(phb->bus)) { 1290 spapr->has_graphics = true; 1291 } 1292 1293 if (usb_enabled(spapr->has_graphics)) { 1294 pci_create_simple(phb->bus, -1, "pci-ohci"); 1295 if (spapr->has_graphics) { 1296 usbdevice_create("keyboard"); 1297 usbdevice_create("mouse"); 1298 } 1299 } 1300 1301 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1302 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " 1303 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); 1304 exit(1); 1305 } 1306 1307 if (kernel_filename) { 1308 uint64_t lowaddr = 0; 1309 1310 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1311 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); 1312 if (kernel_size < 0) { 1313 kernel_size = load_elf(kernel_filename, 1314 translate_kernel_address, NULL, 1315 NULL, &lowaddr, NULL, 0, ELF_MACHINE, 0); 1316 kernel_le = kernel_size > 0; 1317 } 1318 if (kernel_size < 0) { 1319 kernel_size = load_image_targphys(kernel_filename, 1320 KERNEL_LOAD_ADDR, 1321 load_limit - KERNEL_LOAD_ADDR); 1322 } 1323 if (kernel_size < 0) { 1324 fprintf(stderr, "qemu: could not load kernel '%s'\n", 1325 kernel_filename); 1326 exit(1); 1327 } 1328 1329 /* load initrd */ 1330 if (initrd_filename) { 1331 /* Try to locate the initrd in the gap between the kernel 1332 * and the firmware. Add a bit of space just in case 1333 */ 1334 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1335 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1336 load_limit - initrd_base); 1337 if (initrd_size < 0) { 1338 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 1339 initrd_filename); 1340 exit(1); 1341 } 1342 } else { 1343 initrd_base = 0; 1344 initrd_size = 0; 1345 } 1346 } 1347 1348 if (bios_name == NULL) { 1349 bios_name = FW_FILE_NAME; 1350 } 1351 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1352 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 1353 if (fw_size < 0) { 1354 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1355 exit(1); 1356 } 1357 g_free(filename); 1358 1359 spapr->entry_point = 0x100; 1360 1361 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 1362 register_savevm_live(NULL, "spapr/htab", -1, 1, 1363 &savevm_htab_handlers, spapr); 1364 1365 /* Prepare the device tree */ 1366 spapr->fdt_skel = spapr_create_fdt_skel(cpu_model, 1367 initrd_base, initrd_size, 1368 kernel_size, kernel_le, 1369 boot_device, kernel_cmdline, 1370 spapr->epow_irq); 1371 assert(spapr->fdt_skel != NULL); 1372 } 1373 1374 static QEMUMachine spapr_machine = { 1375 .name = "pseries", 1376 .desc = "pSeries Logical Partition (PAPR compliant)", 1377 .is_default = 1, 1378 .init = ppc_spapr_init, 1379 .reset = ppc_spapr_reset, 1380 .block_default_type = IF_SCSI, 1381 .max_cpus = MAX_CPUS, 1382 .no_parallel = 1, 1383 .default_boot_order = NULL, 1384 }; 1385 1386 static void spapr_machine_init(void) 1387 { 1388 qemu_register_machine(&spapr_machine); 1389 } 1390 1391 machine_init(spapr_machine_init); 1392