1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "sysemu/sysemu.h" 28 #include "hw/hw.h" 29 #include "elf.h" 30 #include "net/net.h" 31 #include "sysemu/blockdev.h" 32 #include "sysemu/cpus.h" 33 #include "sysemu/kvm.h" 34 #include "kvm_ppc.h" 35 #include "mmu-hash64.h" 36 37 #include "hw/boards.h" 38 #include "hw/ppc/ppc.h" 39 #include "hw/loader.h" 40 41 #include "hw/ppc/spapr.h" 42 #include "hw/ppc/spapr_vio.h" 43 #include "hw/pci-host/spapr.h" 44 #include "hw/ppc/xics.h" 45 #include "hw/pci/msi.h" 46 47 #include "hw/pci/pci.h" 48 49 #include "exec/address-spaces.h" 50 #include "hw/usb.h" 51 #include "qemu/config-file.h" 52 53 #include <libfdt.h> 54 55 /* SLOF memory layout: 56 * 57 * SLOF raw image loaded at 0, copies its romfs right below the flat 58 * device-tree, then position SLOF itself 31M below that 59 * 60 * So we set FW_OVERHEAD to 40MB which should account for all of that 61 * and more 62 * 63 * We load our kernel at 4M, leaving space for SLOF initial image 64 */ 65 #define FDT_MAX_SIZE 0x10000 66 #define RTAS_MAX_SIZE 0x10000 67 #define FW_MAX_SIZE 0x400000 68 #define FW_FILE_NAME "slof.bin" 69 #define FW_OVERHEAD 0x2800000 70 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 71 72 #define MIN_RMA_SLOF 128UL 73 74 #define TIMEBASE_FREQ 512000000ULL 75 76 #define MAX_CPUS 256 77 #define XICS_IRQS 1024 78 79 #define PHANDLE_XICP 0x00001111 80 81 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 82 83 sPAPREnvironment *spapr; 84 85 int spapr_allocate_irq(int hint, bool lsi) 86 { 87 int irq; 88 89 if (hint) { 90 irq = hint; 91 /* FIXME: we should probably check for collisions somehow */ 92 } else { 93 irq = spapr->next_irq++; 94 } 95 96 /* Configure irq type */ 97 if (!xics_get_qirq(spapr->icp, irq)) { 98 return 0; 99 } 100 101 xics_set_irq_type(spapr->icp, irq, lsi); 102 103 return irq; 104 } 105 106 /* Allocate block of consequtive IRQs, returns a number of the first */ 107 int spapr_allocate_irq_block(int num, bool lsi) 108 { 109 int first = -1; 110 int i; 111 112 for (i = 0; i < num; ++i) { 113 int irq; 114 115 irq = spapr_allocate_irq(0, lsi); 116 if (!irq) { 117 return -1; 118 } 119 120 if (0 == i) { 121 first = irq; 122 } 123 124 /* If the above doesn't create a consecutive block then that's 125 * an internal bug */ 126 assert(irq == (first + i)); 127 } 128 129 return first; 130 } 131 132 static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) 133 { 134 int ret = 0, offset; 135 CPUState *cpu; 136 char cpu_model[32]; 137 int smt = kvmppc_smt_threads(); 138 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 139 140 assert(spapr->cpu_model); 141 142 for (cpu = first_cpu; cpu != NULL; cpu = cpu->next_cpu) { 143 uint32_t associativity[] = {cpu_to_be32(0x5), 144 cpu_to_be32(0x0), 145 cpu_to_be32(0x0), 146 cpu_to_be32(0x0), 147 cpu_to_be32(cpu->numa_node), 148 cpu_to_be32(cpu->cpu_index)}; 149 150 if ((cpu->cpu_index % smt) != 0) { 151 continue; 152 } 153 154 snprintf(cpu_model, 32, "/cpus/%s@%x", spapr->cpu_model, 155 cpu->cpu_index); 156 157 offset = fdt_path_offset(fdt, cpu_model); 158 if (offset < 0) { 159 return offset; 160 } 161 162 if (nb_numa_nodes > 1) { 163 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 164 sizeof(associativity)); 165 if (ret < 0) { 166 return ret; 167 } 168 } 169 170 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 171 pft_size_prop, sizeof(pft_size_prop)); 172 if (ret < 0) { 173 return ret; 174 } 175 } 176 return ret; 177 } 178 179 180 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 181 size_t maxsize) 182 { 183 size_t maxcells = maxsize / sizeof(uint32_t); 184 int i, j, count; 185 uint32_t *p = prop; 186 187 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 188 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 189 190 if (!sps->page_shift) { 191 break; 192 } 193 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 194 if (sps->enc[count].page_shift == 0) { 195 break; 196 } 197 } 198 if ((p - prop) >= (maxcells - 3 - count * 2)) { 199 break; 200 } 201 *(p++) = cpu_to_be32(sps->page_shift); 202 *(p++) = cpu_to_be32(sps->slb_enc); 203 *(p++) = cpu_to_be32(count); 204 for (j = 0; j < count; j++) { 205 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 206 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 207 } 208 } 209 210 return (p - prop) * sizeof(uint32_t); 211 } 212 213 #define _FDT(exp) \ 214 do { \ 215 int ret = (exp); \ 216 if (ret < 0) { \ 217 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 218 #exp, fdt_strerror(ret)); \ 219 exit(1); \ 220 } \ 221 } while (0) 222 223 224 static void *spapr_create_fdt_skel(const char *cpu_model, 225 hwaddr initrd_base, 226 hwaddr initrd_size, 227 hwaddr kernel_size, 228 const char *boot_device, 229 const char *kernel_cmdline, 230 uint32_t epow_irq) 231 { 232 void *fdt; 233 CPUState *cs; 234 uint32_t start_prop = cpu_to_be32(initrd_base); 235 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 236 char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt" 237 "\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk"; 238 char qemu_hypertas_prop[] = "hcall-memop1"; 239 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 240 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; 241 char *modelname; 242 int i, smt = kvmppc_smt_threads(); 243 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 244 245 fdt = g_malloc0(FDT_MAX_SIZE); 246 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 247 248 if (kernel_size) { 249 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 250 } 251 if (initrd_size) { 252 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 253 } 254 _FDT((fdt_finish_reservemap(fdt))); 255 256 /* Root node */ 257 _FDT((fdt_begin_node(fdt, ""))); 258 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 259 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 260 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 261 262 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 263 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 264 265 /* /chosen */ 266 _FDT((fdt_begin_node(fdt, "chosen"))); 267 268 /* Set Form1_affinity */ 269 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 270 271 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 272 _FDT((fdt_property(fdt, "linux,initrd-start", 273 &start_prop, sizeof(start_prop)))); 274 _FDT((fdt_property(fdt, "linux,initrd-end", 275 &end_prop, sizeof(end_prop)))); 276 if (kernel_size) { 277 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 278 cpu_to_be64(kernel_size) }; 279 280 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 281 } 282 if (boot_device) { 283 _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device))); 284 } 285 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 286 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 287 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 288 289 _FDT((fdt_end_node(fdt))); 290 291 /* cpus */ 292 _FDT((fdt_begin_node(fdt, "cpus"))); 293 294 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 295 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 296 297 modelname = g_strdup(cpu_model); 298 299 for (i = 0; i < strlen(modelname); i++) { 300 modelname[i] = toupper(modelname[i]); 301 } 302 303 /* This is needed during FDT finalization */ 304 spapr->cpu_model = g_strdup(modelname); 305 306 for (cs = first_cpu; cs != NULL; cs = cs->next_cpu) { 307 PowerPCCPU *cpu = POWERPC_CPU(cs); 308 CPUPPCState *env = &cpu->env; 309 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 310 int index = cs->cpu_index; 311 uint32_t servers_prop[smp_threads]; 312 uint32_t gservers_prop[smp_threads * 2]; 313 char *nodename; 314 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 315 0xffffffff, 0xffffffff}; 316 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 317 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 318 uint32_t page_sizes_prop[64]; 319 size_t page_sizes_prop_size; 320 321 if ((index % smt) != 0) { 322 continue; 323 } 324 325 nodename = g_strdup_printf("%s@%x", modelname, index); 326 327 _FDT((fdt_begin_node(fdt, nodename))); 328 329 g_free(nodename); 330 331 _FDT((fdt_property_cell(fdt, "reg", index))); 332 _FDT((fdt_property_string(fdt, "device_type", "cpu"))); 333 334 _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); 335 _FDT((fdt_property_cell(fdt, "d-cache-block-size", 336 env->dcache_line_size))); 337 _FDT((fdt_property_cell(fdt, "d-cache-line-size", 338 env->dcache_line_size))); 339 _FDT((fdt_property_cell(fdt, "i-cache-block-size", 340 env->icache_line_size))); 341 _FDT((fdt_property_cell(fdt, "i-cache-line-size", 342 env->icache_line_size))); 343 344 if (pcc->l1_dcache_size) { 345 _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size))); 346 } else { 347 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 348 } 349 if (pcc->l1_icache_size) { 350 _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size))); 351 } else { 352 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 353 } 354 355 _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq))); 356 _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq))); 357 _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); 358 _FDT((fdt_property_string(fdt, "status", "okay"))); 359 _FDT((fdt_property(fdt, "64-bit", NULL, 0))); 360 361 /* Build interrupt servers and gservers properties */ 362 for (i = 0; i < smp_threads; i++) { 363 servers_prop[i] = cpu_to_be32(index + i); 364 /* Hack, direct the group queues back to cpu 0 */ 365 gservers_prop[i*2] = cpu_to_be32(index + i); 366 gservers_prop[i*2 + 1] = 0; 367 } 368 _FDT((fdt_property(fdt, "ibm,ppc-interrupt-server#s", 369 servers_prop, sizeof(servers_prop)))); 370 _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s", 371 gservers_prop, sizeof(gservers_prop)))); 372 373 if (env->mmu_model & POWERPC_MMU_1TSEG) { 374 _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", 375 segs, sizeof(segs)))); 376 } 377 378 /* Advertise VMX/VSX (vector extensions) if available 379 * 0 / no property == no vector extensions 380 * 1 == VMX / Altivec available 381 * 2 == VSX available */ 382 if (env->insns_flags & PPC_ALTIVEC) { 383 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 384 385 _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx))); 386 } 387 388 /* Advertise DFP (Decimal Floating Point) if available 389 * 0 / no property == no DFP 390 * 1 == DFP available */ 391 if (env->insns_flags2 & PPC2_DFP) { 392 _FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); 393 } 394 395 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 396 sizeof(page_sizes_prop)); 397 if (page_sizes_prop_size) { 398 _FDT((fdt_property(fdt, "ibm,segment-page-sizes", 399 page_sizes_prop, page_sizes_prop_size))); 400 } 401 402 _FDT((fdt_end_node(fdt))); 403 } 404 405 g_free(modelname); 406 407 _FDT((fdt_end_node(fdt))); 408 409 /* RTAS */ 410 _FDT((fdt_begin_node(fdt, "rtas"))); 411 412 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop, 413 sizeof(hypertas_prop)))); 414 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas_prop, 415 sizeof(qemu_hypertas_prop)))); 416 417 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 418 refpoints, sizeof(refpoints)))); 419 420 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 421 422 _FDT((fdt_end_node(fdt))); 423 424 /* interrupt controller */ 425 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 426 427 _FDT((fdt_property_string(fdt, "device_type", 428 "PowerPC-External-Interrupt-Presentation"))); 429 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 430 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 431 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 432 interrupt_server_ranges_prop, 433 sizeof(interrupt_server_ranges_prop)))); 434 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 435 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 436 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 437 438 _FDT((fdt_end_node(fdt))); 439 440 /* vdevice */ 441 _FDT((fdt_begin_node(fdt, "vdevice"))); 442 443 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 444 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 445 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 446 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 447 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 448 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 449 450 _FDT((fdt_end_node(fdt))); 451 452 /* event-sources */ 453 spapr_events_fdt_skel(fdt, epow_irq); 454 455 _FDT((fdt_end_node(fdt))); /* close root node */ 456 _FDT((fdt_finish(fdt))); 457 458 return fdt; 459 } 460 461 static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt) 462 { 463 uint32_t associativity[] = {cpu_to_be32(0x4), cpu_to_be32(0x0), 464 cpu_to_be32(0x0), cpu_to_be32(0x0), 465 cpu_to_be32(0x0)}; 466 char mem_name[32]; 467 hwaddr node0_size, mem_start; 468 uint64_t mem_reg_property[2]; 469 int i, off; 470 471 /* memory node(s) */ 472 node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size; 473 if (spapr->rma_size > node0_size) { 474 spapr->rma_size = node0_size; 475 } 476 477 /* RMA */ 478 mem_reg_property[0] = 0; 479 mem_reg_property[1] = cpu_to_be64(spapr->rma_size); 480 off = fdt_add_subnode(fdt, 0, "memory@0"); 481 _FDT(off); 482 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 483 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 484 sizeof(mem_reg_property)))); 485 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 486 sizeof(associativity)))); 487 488 /* RAM: Node 0 */ 489 if (node0_size > spapr->rma_size) { 490 mem_reg_property[0] = cpu_to_be64(spapr->rma_size); 491 mem_reg_property[1] = cpu_to_be64(node0_size - spapr->rma_size); 492 493 sprintf(mem_name, "memory@" TARGET_FMT_lx, spapr->rma_size); 494 off = fdt_add_subnode(fdt, 0, mem_name); 495 _FDT(off); 496 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 497 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 498 sizeof(mem_reg_property)))); 499 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 500 sizeof(associativity)))); 501 } 502 503 /* RAM: Node 1 and beyond */ 504 mem_start = node0_size; 505 for (i = 1; i < nb_numa_nodes; i++) { 506 mem_reg_property[0] = cpu_to_be64(mem_start); 507 mem_reg_property[1] = cpu_to_be64(node_mem[i]); 508 associativity[3] = associativity[4] = cpu_to_be32(i); 509 sprintf(mem_name, "memory@" TARGET_FMT_lx, mem_start); 510 off = fdt_add_subnode(fdt, 0, mem_name); 511 _FDT(off); 512 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 513 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 514 sizeof(mem_reg_property)))); 515 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 516 sizeof(associativity)))); 517 mem_start += node_mem[i]; 518 } 519 520 return 0; 521 } 522 523 static void spapr_finalize_fdt(sPAPREnvironment *spapr, 524 hwaddr fdt_addr, 525 hwaddr rtas_addr, 526 hwaddr rtas_size) 527 { 528 int ret; 529 void *fdt; 530 sPAPRPHBState *phb; 531 532 fdt = g_malloc(FDT_MAX_SIZE); 533 534 /* open out the base tree into a temp buffer for the final tweaks */ 535 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 536 537 ret = spapr_populate_memory(spapr, fdt); 538 if (ret < 0) { 539 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 540 exit(1); 541 } 542 543 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 544 if (ret < 0) { 545 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 546 exit(1); 547 } 548 549 QLIST_FOREACH(phb, &spapr->phbs, list) { 550 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 551 } 552 553 if (ret < 0) { 554 fprintf(stderr, "couldn't setup PCI devices in fdt\n"); 555 exit(1); 556 } 557 558 /* RTAS */ 559 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 560 if (ret < 0) { 561 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 562 } 563 564 /* Advertise NUMA via ibm,associativity */ 565 ret = spapr_fixup_cpu_dt(fdt, spapr); 566 if (ret < 0) { 567 fprintf(stderr, "Couldn't finalize CPU device tree properties\n"); 568 } 569 570 if (!spapr->has_graphics) { 571 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 572 } 573 574 _FDT((fdt_pack(fdt))); 575 576 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 577 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n", 578 fdt_totalsize(fdt), FDT_MAX_SIZE); 579 exit(1); 580 } 581 582 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 583 584 g_free(fdt); 585 } 586 587 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 588 { 589 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 590 } 591 592 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 593 { 594 CPUPPCState *env = &cpu->env; 595 596 if (msr_pr) { 597 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 598 env->gpr[3] = H_PRIVILEGE; 599 } else { 600 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 601 } 602 } 603 604 static void spapr_reset_htab(sPAPREnvironment *spapr) 605 { 606 long shift; 607 608 /* allocate hash page table. For now we always make this 16mb, 609 * later we should probably make it scale to the size of guest 610 * RAM */ 611 612 shift = kvmppc_reset_htab(spapr->htab_shift); 613 614 if (shift > 0) { 615 /* Kernel handles htab, we don't need to allocate one */ 616 spapr->htab_shift = shift; 617 } else { 618 if (!spapr->htab) { 619 /* Allocate an htab if we don't yet have one */ 620 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); 621 } 622 623 /* And clear it */ 624 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 625 } 626 627 /* Update the RMA size if necessary */ 628 if (spapr->vrma_adjust) { 629 spapr->rma_size = kvmppc_rma_size(ram_size, spapr->htab_shift); 630 } 631 } 632 633 static void ppc_spapr_reset(void) 634 { 635 PowerPCCPU *first_ppc_cpu; 636 637 /* Reset the hash table & recalc the RMA */ 638 spapr_reset_htab(spapr); 639 640 qemu_devices_reset(); 641 642 /* Load the fdt */ 643 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 644 spapr->rtas_size); 645 646 /* Set up the entry state */ 647 first_ppc_cpu = POWERPC_CPU(first_cpu); 648 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 649 first_ppc_cpu->env.gpr[5] = 0; 650 first_cpu->halted = 0; 651 first_ppc_cpu->env.nip = spapr->entry_point; 652 653 } 654 655 static void spapr_cpu_reset(void *opaque) 656 { 657 PowerPCCPU *cpu = opaque; 658 CPUState *cs = CPU(cpu); 659 CPUPPCState *env = &cpu->env; 660 661 cpu_reset(cs); 662 663 /* All CPUs start halted. CPU0 is unhalted from the machine level 664 * reset code and the rest are explicitly started up by the guest 665 * using an RTAS call */ 666 cs->halted = 1; 667 668 env->spr[SPR_HIOR] = 0; 669 670 env->external_htab = (uint8_t *)spapr->htab; 671 env->htab_base = -1; 672 env->htab_mask = HTAB_SIZE(spapr) - 1; 673 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | 674 (spapr->htab_shift - 18); 675 } 676 677 static void spapr_create_nvram(sPAPREnvironment *spapr) 678 { 679 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 680 const char *drivename = qemu_opt_get(qemu_get_machine_opts(), "nvram"); 681 682 if (drivename) { 683 BlockDriverState *bs; 684 685 bs = bdrv_find(drivename); 686 if (!bs) { 687 fprintf(stderr, "No such block device \"%s\" for nvram\n", 688 drivename); 689 exit(1); 690 } 691 qdev_prop_set_drive_nofail(dev, "drive", bs); 692 } 693 694 qdev_init_nofail(dev); 695 696 spapr->nvram = (struct sPAPRNVRAM *)dev; 697 } 698 699 /* Returns whether we want to use VGA or not */ 700 static int spapr_vga_init(PCIBus *pci_bus) 701 { 702 switch (vga_interface_type) { 703 case VGA_NONE: 704 case VGA_STD: 705 return pci_vga_init(pci_bus) != NULL; 706 default: 707 fprintf(stderr, "This vga model is not supported," 708 "currently it only supports -vga std\n"); 709 exit(0); 710 break; 711 } 712 } 713 714 static const VMStateDescription vmstate_spapr = { 715 .name = "spapr", 716 .version_id = 1, 717 .minimum_version_id = 1, 718 .minimum_version_id_old = 1, 719 .fields = (VMStateField []) { 720 VMSTATE_UINT32(next_irq, sPAPREnvironment), 721 722 /* RTC offset */ 723 VMSTATE_UINT64(rtc_offset, sPAPREnvironment), 724 725 VMSTATE_END_OF_LIST() 726 }, 727 }; 728 729 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 730 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 731 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 732 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 733 734 static int htab_save_setup(QEMUFile *f, void *opaque) 735 { 736 sPAPREnvironment *spapr = opaque; 737 738 spapr->htab_save_index = 0; 739 spapr->htab_first_pass = true; 740 741 /* "Iteration" header */ 742 qemu_put_be32(f, spapr->htab_shift); 743 744 return 0; 745 } 746 747 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 748 749 static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr, 750 int64_t max_ns) 751 { 752 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 753 int index = spapr->htab_save_index; 754 int64_t starttime = qemu_get_clock_ns(rt_clock); 755 756 assert(spapr->htab_first_pass); 757 758 do { 759 int chunkstart; 760 761 /* Consume invalid HPTEs */ 762 while ((index < htabslots) 763 && !HPTE_VALID(HPTE(spapr->htab, index))) { 764 index++; 765 CLEAN_HPTE(HPTE(spapr->htab, index)); 766 } 767 768 /* Consume valid HPTEs */ 769 chunkstart = index; 770 while ((index < htabslots) 771 && HPTE_VALID(HPTE(spapr->htab, index))) { 772 index++; 773 CLEAN_HPTE(HPTE(spapr->htab, index)); 774 } 775 776 if (index > chunkstart) { 777 int n_valid = index - chunkstart; 778 779 qemu_put_be32(f, chunkstart); 780 qemu_put_be16(f, n_valid); 781 qemu_put_be16(f, 0); 782 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 783 HASH_PTE_SIZE_64 * n_valid); 784 785 if ((qemu_get_clock_ns(rt_clock) - starttime) > max_ns) { 786 break; 787 } 788 } 789 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 790 791 if (index >= htabslots) { 792 assert(index == htabslots); 793 index = 0; 794 spapr->htab_first_pass = false; 795 } 796 spapr->htab_save_index = index; 797 } 798 799 static bool htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, 800 int64_t max_ns) 801 { 802 bool final = max_ns < 0; 803 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 804 int examined = 0, sent = 0; 805 int index = spapr->htab_save_index; 806 int64_t starttime = qemu_get_clock_ns(rt_clock); 807 808 assert(!spapr->htab_first_pass); 809 810 do { 811 int chunkstart, invalidstart; 812 813 /* Consume non-dirty HPTEs */ 814 while ((index < htabslots) 815 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 816 index++; 817 examined++; 818 } 819 820 chunkstart = index; 821 /* Consume valid dirty HPTEs */ 822 while ((index < htabslots) 823 && HPTE_DIRTY(HPTE(spapr->htab, index)) 824 && HPTE_VALID(HPTE(spapr->htab, index))) { 825 CLEAN_HPTE(HPTE(spapr->htab, index)); 826 index++; 827 examined++; 828 } 829 830 invalidstart = index; 831 /* Consume invalid dirty HPTEs */ 832 while ((index < htabslots) 833 && HPTE_DIRTY(HPTE(spapr->htab, index)) 834 && !HPTE_VALID(HPTE(spapr->htab, index))) { 835 CLEAN_HPTE(HPTE(spapr->htab, index)); 836 index++; 837 examined++; 838 } 839 840 if (index > chunkstart) { 841 int n_valid = invalidstart - chunkstart; 842 int n_invalid = index - invalidstart; 843 844 qemu_put_be32(f, chunkstart); 845 qemu_put_be16(f, n_valid); 846 qemu_put_be16(f, n_invalid); 847 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 848 HASH_PTE_SIZE_64 * n_valid); 849 sent += index - chunkstart; 850 851 if (!final && (qemu_get_clock_ns(rt_clock) - starttime) > max_ns) { 852 break; 853 } 854 } 855 856 if (examined >= htabslots) { 857 break; 858 } 859 860 if (index >= htabslots) { 861 assert(index == htabslots); 862 index = 0; 863 } 864 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 865 866 if (index >= htabslots) { 867 assert(index == htabslots); 868 index = 0; 869 } 870 871 spapr->htab_save_index = index; 872 873 return (examined >= htabslots) && (sent == 0); 874 } 875 876 static int htab_save_iterate(QEMUFile *f, void *opaque) 877 { 878 sPAPREnvironment *spapr = opaque; 879 bool nothingleft = false;; 880 881 /* Iteration header */ 882 qemu_put_be32(f, 0); 883 884 if (spapr->htab_first_pass) { 885 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 886 } else { 887 nothingleft = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 888 } 889 890 /* End marker */ 891 qemu_put_be32(f, 0); 892 qemu_put_be16(f, 0); 893 qemu_put_be16(f, 0); 894 895 return nothingleft ? 1 : 0; 896 } 897 898 static int htab_save_complete(QEMUFile *f, void *opaque) 899 { 900 sPAPREnvironment *spapr = opaque; 901 902 /* Iteration header */ 903 qemu_put_be32(f, 0); 904 905 htab_save_later_pass(f, spapr, -1); 906 907 /* End marker */ 908 qemu_put_be32(f, 0); 909 qemu_put_be16(f, 0); 910 qemu_put_be16(f, 0); 911 912 return 0; 913 } 914 915 static int htab_load(QEMUFile *f, void *opaque, int version_id) 916 { 917 sPAPREnvironment *spapr = opaque; 918 uint32_t section_hdr; 919 920 if (version_id < 1 || version_id > 1) { 921 fprintf(stderr, "htab_load() bad version\n"); 922 return -EINVAL; 923 } 924 925 section_hdr = qemu_get_be32(f); 926 927 if (section_hdr) { 928 /* First section, just the hash shift */ 929 if (spapr->htab_shift != section_hdr) { 930 return -EINVAL; 931 } 932 return 0; 933 } 934 935 while (true) { 936 uint32_t index; 937 uint16_t n_valid, n_invalid; 938 939 index = qemu_get_be32(f); 940 n_valid = qemu_get_be16(f); 941 n_invalid = qemu_get_be16(f); 942 943 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 944 /* End of Stream */ 945 break; 946 } 947 948 if ((index + n_valid + n_invalid) >= 949 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 950 /* Bad index in stream */ 951 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " 952 "in htab stream\n", index, n_valid, n_invalid); 953 return -EINVAL; 954 } 955 956 if (n_valid) { 957 qemu_get_buffer(f, HPTE(spapr->htab, index), 958 HASH_PTE_SIZE_64 * n_valid); 959 } 960 if (n_invalid) { 961 memset(HPTE(spapr->htab, index + n_valid), 0, 962 HASH_PTE_SIZE_64 * n_invalid); 963 } 964 } 965 966 return 0; 967 } 968 969 static SaveVMHandlers savevm_htab_handlers = { 970 .save_live_setup = htab_save_setup, 971 .save_live_iterate = htab_save_iterate, 972 .save_live_complete = htab_save_complete, 973 .load_state = htab_load, 974 }; 975 976 /* pSeries LPAR / sPAPR hardware init */ 977 static void ppc_spapr_init(QEMUMachineInitArgs *args) 978 { 979 ram_addr_t ram_size = args->ram_size; 980 const char *cpu_model = args->cpu_model; 981 const char *kernel_filename = args->kernel_filename; 982 const char *kernel_cmdline = args->kernel_cmdline; 983 const char *initrd_filename = args->initrd_filename; 984 const char *boot_device = args->boot_device; 985 PowerPCCPU *cpu; 986 CPUPPCState *env; 987 PCIHostState *phb; 988 int i; 989 MemoryRegion *sysmem = get_system_memory(); 990 MemoryRegion *ram = g_new(MemoryRegion, 1); 991 hwaddr rma_alloc_size; 992 uint32_t initrd_base = 0; 993 long kernel_size = 0, initrd_size = 0; 994 long load_limit, rtas_limit, fw_size; 995 char *filename; 996 997 msi_supported = true; 998 999 spapr = g_malloc0(sizeof(*spapr)); 1000 QLIST_INIT(&spapr->phbs); 1001 1002 cpu_ppc_hypercall = emulate_spapr_hypercall; 1003 1004 /* Allocate RMA if necessary */ 1005 rma_alloc_size = kvmppc_alloc_rma("ppc_spapr.rma", sysmem); 1006 1007 if (rma_alloc_size == -1) { 1008 hw_error("qemu: Unable to create RMA\n"); 1009 exit(1); 1010 } 1011 1012 if (rma_alloc_size && (rma_alloc_size < ram_size)) { 1013 spapr->rma_size = rma_alloc_size; 1014 } else { 1015 spapr->rma_size = ram_size; 1016 1017 /* With KVM, we don't actually know whether KVM supports an 1018 * unbounded RMA (PR KVM) or is limited by the hash table size 1019 * (HV KVM using VRMA), so we always assume the latter 1020 * 1021 * In that case, we also limit the initial allocations for RTAS 1022 * etc... to 256M since we have no way to know what the VRMA size 1023 * is going to be as it depends on the size of the hash table 1024 * isn't determined yet. 1025 */ 1026 if (kvm_enabled()) { 1027 spapr->vrma_adjust = 1; 1028 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1029 } 1030 } 1031 1032 /* We place the device tree and RTAS just below either the top of the RMA, 1033 * or just below 2GB, whichever is lowere, so that it can be 1034 * processed with 32-bit real mode code if necessary */ 1035 rtas_limit = MIN(spapr->rma_size, 0x80000000); 1036 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1037 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 1038 load_limit = spapr->fdt_addr - FW_OVERHEAD; 1039 1040 /* We aim for a hash table of size 1/128 the size of RAM. The 1041 * normal rule of thumb is 1/64 the size of RAM, but that's much 1042 * more than needed for the Linux guests we support. */ 1043 spapr->htab_shift = 18; /* Minimum architected size */ 1044 while (spapr->htab_shift <= 46) { 1045 if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) { 1046 break; 1047 } 1048 spapr->htab_shift++; 1049 } 1050 1051 /* Set up Interrupt Controller before we create the VCPUs */ 1052 spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads, 1053 XICS_IRQS); 1054 spapr->next_irq = XICS_IRQ_BASE; 1055 1056 /* init CPUs */ 1057 if (cpu_model == NULL) { 1058 cpu_model = kvm_enabled() ? "host" : "POWER7"; 1059 } 1060 for (i = 0; i < smp_cpus; i++) { 1061 cpu = cpu_ppc_init(cpu_model); 1062 if (cpu == NULL) { 1063 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 1064 exit(1); 1065 } 1066 env = &cpu->env; 1067 1068 xics_cpu_setup(spapr->icp, cpu); 1069 1070 /* Set time-base frequency to 512 MHz */ 1071 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 1072 1073 /* PAPR always has exception vectors in RAM not ROM. To ensure this, 1074 * MSR[IP] should never be set. 1075 */ 1076 env->msr_mask &= ~(1 << 6); 1077 1078 /* Tell KVM that we're in PAPR mode */ 1079 if (kvm_enabled()) { 1080 kvmppc_set_papr(cpu); 1081 } 1082 1083 qemu_register_reset(spapr_cpu_reset, cpu); 1084 } 1085 1086 /* allocate RAM */ 1087 spapr->ram_limit = ram_size; 1088 if (spapr->ram_limit > rma_alloc_size) { 1089 ram_addr_t nonrma_base = rma_alloc_size; 1090 ram_addr_t nonrma_size = spapr->ram_limit - rma_alloc_size; 1091 1092 memory_region_init_ram(ram, NULL, "ppc_spapr.ram", nonrma_size); 1093 vmstate_register_ram_global(ram); 1094 memory_region_add_subregion(sysmem, nonrma_base, ram); 1095 } 1096 1097 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1098 spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr, 1099 rtas_limit - spapr->rtas_addr); 1100 if (spapr->rtas_size < 0) { 1101 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1102 exit(1); 1103 } 1104 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1105 hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n", 1106 spapr->rtas_size, RTAS_MAX_SIZE); 1107 exit(1); 1108 } 1109 g_free(filename); 1110 1111 /* Set up EPOW events infrastructure */ 1112 spapr_events_init(spapr); 1113 1114 /* Set up VIO bus */ 1115 spapr->vio_bus = spapr_vio_bus_init(); 1116 1117 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1118 if (serial_hds[i]) { 1119 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1120 } 1121 } 1122 1123 /* We always have at least the nvram device on VIO */ 1124 spapr_create_nvram(spapr); 1125 1126 /* Set up PCI */ 1127 spapr_pci_rtas_init(); 1128 1129 phb = spapr_create_phb(spapr, 0); 1130 1131 for (i = 0; i < nb_nics; i++) { 1132 NICInfo *nd = &nd_table[i]; 1133 1134 if (!nd->model) { 1135 nd->model = g_strdup("ibmveth"); 1136 } 1137 1138 if (strcmp(nd->model, "ibmveth") == 0) { 1139 spapr_vlan_create(spapr->vio_bus, nd); 1140 } else { 1141 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1142 } 1143 } 1144 1145 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1146 spapr_vscsi_create(spapr->vio_bus); 1147 } 1148 1149 /* Graphics */ 1150 if (spapr_vga_init(phb->bus)) { 1151 spapr->has_graphics = true; 1152 } 1153 1154 if (usb_enabled(spapr->has_graphics)) { 1155 pci_create_simple(phb->bus, -1, "pci-ohci"); 1156 if (spapr->has_graphics) { 1157 usbdevice_create("keyboard"); 1158 usbdevice_create("mouse"); 1159 } 1160 } 1161 1162 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1163 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " 1164 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); 1165 exit(1); 1166 } 1167 1168 if (kernel_filename) { 1169 uint64_t lowaddr = 0; 1170 1171 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1172 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); 1173 if (kernel_size < 0) { 1174 kernel_size = load_image_targphys(kernel_filename, 1175 KERNEL_LOAD_ADDR, 1176 load_limit - KERNEL_LOAD_ADDR); 1177 } 1178 if (kernel_size < 0) { 1179 fprintf(stderr, "qemu: could not load kernel '%s'\n", 1180 kernel_filename); 1181 exit(1); 1182 } 1183 1184 /* load initrd */ 1185 if (initrd_filename) { 1186 /* Try to locate the initrd in the gap between the kernel 1187 * and the firmware. Add a bit of space just in case 1188 */ 1189 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1190 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1191 load_limit - initrd_base); 1192 if (initrd_size < 0) { 1193 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 1194 initrd_filename); 1195 exit(1); 1196 } 1197 } else { 1198 initrd_base = 0; 1199 initrd_size = 0; 1200 } 1201 } 1202 1203 if (bios_name == NULL) { 1204 bios_name = FW_FILE_NAME; 1205 } 1206 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1207 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 1208 if (fw_size < 0) { 1209 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1210 exit(1); 1211 } 1212 g_free(filename); 1213 1214 spapr->entry_point = 0x100; 1215 1216 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 1217 register_savevm_live(NULL, "spapr/htab", -1, 1, 1218 &savevm_htab_handlers, spapr); 1219 1220 /* Prepare the device tree */ 1221 spapr->fdt_skel = spapr_create_fdt_skel(cpu_model, 1222 initrd_base, initrd_size, 1223 kernel_size, 1224 boot_device, kernel_cmdline, 1225 spapr->epow_irq); 1226 assert(spapr->fdt_skel != NULL); 1227 } 1228 1229 static QEMUMachine spapr_machine = { 1230 .name = "pseries", 1231 .desc = "pSeries Logical Partition (PAPR compliant)", 1232 .is_default = 1, 1233 .init = ppc_spapr_init, 1234 .reset = ppc_spapr_reset, 1235 .block_default_type = IF_SCSI, 1236 .max_cpus = MAX_CPUS, 1237 .no_parallel = 1, 1238 .boot_order = NULL, 1239 }; 1240 1241 static void spapr_machine_init(void) 1242 { 1243 qemu_register_machine(&spapr_machine); 1244 } 1245 1246 machine_init(spapr_machine_init); 1247