1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qapi/error.h" 30 #include "qapi/visitor.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/hostmem.h" 33 #include "sysemu/numa.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/runstate.h" 37 #include "qemu/log.h" 38 #include "hw/fw-path-provider.h" 39 #include "elf.h" 40 #include "net/net.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/cpus.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_ppc.h" 45 #include "migration/misc.h" 46 #include "migration/qemu-file-types.h" 47 #include "migration/global_state.h" 48 #include "migration/register.h" 49 #include "migration/blocker.h" 50 #include "mmu-hash64.h" 51 #include "mmu-book3s-v3.h" 52 #include "cpu-models.h" 53 #include "hw/core/cpu.h" 54 55 #include "hw/boards.h" 56 #include "hw/ppc/ppc.h" 57 #include "hw/loader.h" 58 59 #include "hw/ppc/fdt.h" 60 #include "hw/ppc/spapr.h" 61 #include "hw/ppc/spapr_vio.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/pci-host/spapr.h" 64 #include "hw/pci/msi.h" 65 66 #include "hw/pci/pci.h" 67 #include "hw/scsi/scsi.h" 68 #include "hw/virtio/virtio-scsi.h" 69 #include "hw/virtio/vhost-scsi-common.h" 70 71 #include "exec/address-spaces.h" 72 #include "exec/ram_addr.h" 73 #include "hw/usb.h" 74 #include "qemu/config-file.h" 75 #include "qemu/error-report.h" 76 #include "trace.h" 77 #include "hw/nmi.h" 78 #include "hw/intc/intc.h" 79 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 #include "hw/ppc/spapr_nvdimm.h" 84 85 #include "monitor/monitor.h" 86 87 #include <libfdt.h> 88 89 /* SLOF memory layout: 90 * 91 * SLOF raw image loaded at 0, copies its romfs right below the flat 92 * device-tree, then position SLOF itself 31M below that 93 * 94 * So we set FW_OVERHEAD to 40MB which should account for all of that 95 * and more 96 * 97 * We load our kernel at 4M, leaving space for SLOF initial image 98 */ 99 #define FDT_MAX_SIZE 0x100000 100 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 101 #define FW_MAX_SIZE 0x400000 102 #define FW_FILE_NAME "slof.bin" 103 #define FW_OVERHEAD 0x2800000 104 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 105 106 #define MIN_RMA_SLOF (128 * MiB) 107 108 #define PHANDLE_INTC 0x00001111 109 110 /* These two functions implement the VCPU id numbering: one to compute them 111 * all and one to identify thread 0 of a VCORE. Any change to the first one 112 * is likely to have an impact on the second one, so let's keep them close. 113 */ 114 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 115 { 116 MachineState *ms = MACHINE(spapr); 117 unsigned int smp_threads = ms->smp.threads; 118 119 assert(spapr->vsmt); 120 return 121 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 122 } 123 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 124 PowerPCCPU *cpu) 125 { 126 assert(spapr->vsmt); 127 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 128 } 129 130 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 131 { 132 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 133 * and newer QEMUs don't even have them. In both cases, we don't want 134 * to send anything on the wire. 135 */ 136 return false; 137 } 138 139 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 140 .name = "icp/server", 141 .version_id = 1, 142 .minimum_version_id = 1, 143 .needed = pre_2_10_vmstate_dummy_icp_needed, 144 .fields = (VMStateField[]) { 145 VMSTATE_UNUSED(4), /* uint32_t xirr */ 146 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 147 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 148 VMSTATE_END_OF_LIST() 149 }, 150 }; 151 152 static void pre_2_10_vmstate_register_dummy_icp(int i) 153 { 154 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 155 (void *)(uintptr_t) i); 156 } 157 158 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 159 { 160 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 161 (void *)(uintptr_t) i); 162 } 163 164 int spapr_max_server_number(SpaprMachineState *spapr) 165 { 166 MachineState *ms = MACHINE(spapr); 167 168 assert(spapr->vsmt); 169 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 170 } 171 172 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 173 int smt_threads) 174 { 175 int i, ret = 0; 176 uint32_t servers_prop[smt_threads]; 177 uint32_t gservers_prop[smt_threads * 2]; 178 int index = spapr_get_vcpu_id(cpu); 179 180 if (cpu->compat_pvr) { 181 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 182 if (ret < 0) { 183 return ret; 184 } 185 } 186 187 /* Build interrupt servers and gservers properties */ 188 for (i = 0; i < smt_threads; i++) { 189 servers_prop[i] = cpu_to_be32(index + i); 190 /* Hack, direct the group queues back to cpu 0 */ 191 gservers_prop[i*2] = cpu_to_be32(index + i); 192 gservers_prop[i*2 + 1] = 0; 193 } 194 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 195 servers_prop, sizeof(servers_prop)); 196 if (ret < 0) { 197 return ret; 198 } 199 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 200 gservers_prop, sizeof(gservers_prop)); 201 202 return ret; 203 } 204 205 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 206 { 207 int index = spapr_get_vcpu_id(cpu); 208 uint32_t associativity[] = {cpu_to_be32(0x5), 209 cpu_to_be32(0x0), 210 cpu_to_be32(0x0), 211 cpu_to_be32(0x0), 212 cpu_to_be32(cpu->node_id), 213 cpu_to_be32(index)}; 214 215 /* Advertise NUMA via ibm,associativity */ 216 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 217 sizeof(associativity)); 218 } 219 220 /* Populate the "ibm,pa-features" property */ 221 static void spapr_populate_pa_features(SpaprMachineState *spapr, 222 PowerPCCPU *cpu, 223 void *fdt, int offset) 224 { 225 uint8_t pa_features_206[] = { 6, 0, 226 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 227 uint8_t pa_features_207[] = { 24, 0, 228 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 229 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 230 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 231 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 232 uint8_t pa_features_300[] = { 66, 0, 233 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 234 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 235 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 236 /* 6: DS207 */ 237 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 238 /* 16: Vector */ 239 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 240 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 241 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 242 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 243 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 244 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 245 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 246 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 247 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 248 /* 42: PM, 44: PC RA, 46: SC vec'd */ 249 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 250 /* 48: SIMD, 50: QP BFP, 52: String */ 251 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 252 /* 54: DecFP, 56: DecI, 58: SHA */ 253 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 254 /* 60: NM atomic, 62: RNG */ 255 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 256 }; 257 uint8_t *pa_features = NULL; 258 size_t pa_size; 259 260 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 261 pa_features = pa_features_206; 262 pa_size = sizeof(pa_features_206); 263 } 264 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 265 pa_features = pa_features_207; 266 pa_size = sizeof(pa_features_207); 267 } 268 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 269 pa_features = pa_features_300; 270 pa_size = sizeof(pa_features_300); 271 } 272 if (!pa_features) { 273 return; 274 } 275 276 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 277 /* 278 * Note: we keep CI large pages off by default because a 64K capable 279 * guest provisioned with large pages might otherwise try to map a qemu 280 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 281 * even if that qemu runs on a 4k host. 282 * We dd this bit back here if we are confident this is not an issue 283 */ 284 pa_features[3] |= 0x20; 285 } 286 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 287 pa_features[24] |= 0x80; /* Transactional memory support */ 288 } 289 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 290 /* Workaround for broken kernels that attempt (guest) radix 291 * mode when they can't handle it, if they see the radix bit set 292 * in pa-features. So hide it from them. */ 293 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 294 } 295 296 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 297 } 298 299 static hwaddr spapr_node0_size(MachineState *machine) 300 { 301 if (machine->numa_state->num_nodes) { 302 int i; 303 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 304 if (machine->numa_state->nodes[i].node_mem) { 305 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 306 machine->ram_size); 307 } 308 } 309 } 310 return machine->ram_size; 311 } 312 313 static void add_str(GString *s, const gchar *s1) 314 { 315 g_string_append_len(s, s1, strlen(s1) + 1); 316 } 317 318 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 319 hwaddr size) 320 { 321 uint32_t associativity[] = { 322 cpu_to_be32(0x4), /* length */ 323 cpu_to_be32(0x0), cpu_to_be32(0x0), 324 cpu_to_be32(0x0), cpu_to_be32(nodeid) 325 }; 326 char mem_name[32]; 327 uint64_t mem_reg_property[2]; 328 int off; 329 330 mem_reg_property[0] = cpu_to_be64(start); 331 mem_reg_property[1] = cpu_to_be64(size); 332 333 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 334 off = fdt_add_subnode(fdt, 0, mem_name); 335 _FDT(off); 336 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 337 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 338 sizeof(mem_reg_property)))); 339 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 340 sizeof(associativity)))); 341 return off; 342 } 343 344 static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt) 345 { 346 MachineState *machine = MACHINE(spapr); 347 hwaddr mem_start, node_size; 348 int i, nb_nodes = machine->numa_state->num_nodes; 349 NodeInfo *nodes = machine->numa_state->nodes; 350 351 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 352 if (!nodes[i].node_mem) { 353 continue; 354 } 355 if (mem_start >= machine->ram_size) { 356 node_size = 0; 357 } else { 358 node_size = nodes[i].node_mem; 359 if (node_size > machine->ram_size - mem_start) { 360 node_size = machine->ram_size - mem_start; 361 } 362 } 363 if (!mem_start) { 364 /* spapr_machine_init() checks for rma_size <= node0_size 365 * already */ 366 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 367 mem_start += spapr->rma_size; 368 node_size -= spapr->rma_size; 369 } 370 for ( ; node_size; ) { 371 hwaddr sizetmp = pow2floor(node_size); 372 373 /* mem_start != 0 here */ 374 if (ctzl(mem_start) < ctzl(sizetmp)) { 375 sizetmp = 1ULL << ctzl(mem_start); 376 } 377 378 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 379 node_size -= sizetmp; 380 mem_start += sizetmp; 381 } 382 } 383 384 return 0; 385 } 386 387 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 388 SpaprMachineState *spapr) 389 { 390 MachineState *ms = MACHINE(spapr); 391 PowerPCCPU *cpu = POWERPC_CPU(cs); 392 CPUPPCState *env = &cpu->env; 393 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 394 int index = spapr_get_vcpu_id(cpu); 395 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 396 0xffffffff, 0xffffffff}; 397 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 398 : SPAPR_TIMEBASE_FREQ; 399 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 400 uint32_t page_sizes_prop[64]; 401 size_t page_sizes_prop_size; 402 unsigned int smp_threads = ms->smp.threads; 403 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 404 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 405 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 406 SpaprDrc *drc; 407 int drc_index; 408 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 409 int i; 410 411 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 412 if (drc) { 413 drc_index = spapr_drc_index(drc); 414 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 415 } 416 417 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 418 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 419 420 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 421 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 422 env->dcache_line_size))); 423 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 424 env->dcache_line_size))); 425 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 426 env->icache_line_size))); 427 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 428 env->icache_line_size))); 429 430 if (pcc->l1_dcache_size) { 431 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 432 pcc->l1_dcache_size))); 433 } else { 434 warn_report("Unknown L1 dcache size for cpu"); 435 } 436 if (pcc->l1_icache_size) { 437 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 438 pcc->l1_icache_size))); 439 } else { 440 warn_report("Unknown L1 icache size for cpu"); 441 } 442 443 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 444 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 445 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 446 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 447 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 448 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 449 450 if (env->spr_cb[SPR_PURR].oea_read) { 451 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 452 } 453 if (env->spr_cb[SPR_SPURR].oea_read) { 454 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 455 } 456 457 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 458 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 459 segs, sizeof(segs)))); 460 } 461 462 /* Advertise VSX (vector extensions) if available 463 * 1 == VMX / Altivec available 464 * 2 == VSX available 465 * 466 * Only CPUs for which we create core types in spapr_cpu_core.c 467 * are possible, and all of those have VMX */ 468 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 469 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 470 } else { 471 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 472 } 473 474 /* Advertise DFP (Decimal Floating Point) if available 475 * 0 / no property == no DFP 476 * 1 == DFP available */ 477 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 478 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 479 } 480 481 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 482 sizeof(page_sizes_prop)); 483 if (page_sizes_prop_size) { 484 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 485 page_sizes_prop, page_sizes_prop_size))); 486 } 487 488 spapr_populate_pa_features(spapr, cpu, fdt, offset); 489 490 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 491 cs->cpu_index / vcpus_per_socket))); 492 493 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 494 pft_size_prop, sizeof(pft_size_prop)))); 495 496 if (ms->numa_state->num_nodes > 1) { 497 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 498 } 499 500 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 501 502 if (pcc->radix_page_info) { 503 for (i = 0; i < pcc->radix_page_info->count; i++) { 504 radix_AP_encodings[i] = 505 cpu_to_be32(pcc->radix_page_info->entries[i]); 506 } 507 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 508 radix_AP_encodings, 509 pcc->radix_page_info->count * 510 sizeof(radix_AP_encodings[0])))); 511 } 512 513 /* 514 * We set this property to let the guest know that it can use the large 515 * decrementer and its width in bits. 516 */ 517 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 518 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 519 pcc->lrg_decr_bits))); 520 } 521 522 static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spapr) 523 { 524 CPUState **rev; 525 CPUState *cs; 526 int n_cpus; 527 int cpus_offset; 528 char *nodename; 529 int i; 530 531 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 532 _FDT(cpus_offset); 533 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 534 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 535 536 /* 537 * We walk the CPUs in reverse order to ensure that CPU DT nodes 538 * created by fdt_add_subnode() end up in the right order in FDT 539 * for the guest kernel the enumerate the CPUs correctly. 540 * 541 * The CPU list cannot be traversed in reverse order, so we need 542 * to do extra work. 543 */ 544 n_cpus = 0; 545 rev = NULL; 546 CPU_FOREACH(cs) { 547 rev = g_renew(CPUState *, rev, n_cpus + 1); 548 rev[n_cpus++] = cs; 549 } 550 551 for (i = n_cpus - 1; i >= 0; i--) { 552 CPUState *cs = rev[i]; 553 PowerPCCPU *cpu = POWERPC_CPU(cs); 554 int index = spapr_get_vcpu_id(cpu); 555 DeviceClass *dc = DEVICE_GET_CLASS(cs); 556 int offset; 557 558 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 559 continue; 560 } 561 562 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 563 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 564 g_free(nodename); 565 _FDT(offset); 566 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 567 } 568 569 g_free(rev); 570 } 571 572 static int spapr_rng_populate_dt(void *fdt) 573 { 574 int node; 575 int ret; 576 577 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 578 if (node <= 0) { 579 return -1; 580 } 581 ret = fdt_setprop_string(fdt, node, "device_type", 582 "ibm,platform-facilities"); 583 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 584 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 585 586 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 587 if (node <= 0) { 588 return -1; 589 } 590 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 591 592 return ret ? -1 : 0; 593 } 594 595 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 596 { 597 MemoryDeviceInfoList *info; 598 599 for (info = list; info; info = info->next) { 600 MemoryDeviceInfo *value = info->value; 601 602 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 603 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 604 605 if (addr >= pcdimm_info->addr && 606 addr < (pcdimm_info->addr + pcdimm_info->size)) { 607 return pcdimm_info->node; 608 } 609 } 610 } 611 612 return -1; 613 } 614 615 struct sPAPRDrconfCellV2 { 616 uint32_t seq_lmbs; 617 uint64_t base_addr; 618 uint32_t drc_index; 619 uint32_t aa_index; 620 uint32_t flags; 621 } QEMU_PACKED; 622 623 typedef struct DrconfCellQueue { 624 struct sPAPRDrconfCellV2 cell; 625 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 626 } DrconfCellQueue; 627 628 static DrconfCellQueue * 629 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 630 uint32_t drc_index, uint32_t aa_index, 631 uint32_t flags) 632 { 633 DrconfCellQueue *elem; 634 635 elem = g_malloc0(sizeof(*elem)); 636 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 637 elem->cell.base_addr = cpu_to_be64(base_addr); 638 elem->cell.drc_index = cpu_to_be32(drc_index); 639 elem->cell.aa_index = cpu_to_be32(aa_index); 640 elem->cell.flags = cpu_to_be32(flags); 641 642 return elem; 643 } 644 645 /* ibm,dynamic-memory-v2 */ 646 static int spapr_populate_drmem_v2(SpaprMachineState *spapr, void *fdt, 647 int offset, MemoryDeviceInfoList *dimms) 648 { 649 MachineState *machine = MACHINE(spapr); 650 uint8_t *int_buf, *cur_index; 651 int ret; 652 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 653 uint64_t addr, cur_addr, size; 654 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 655 uint64_t mem_end = machine->device_memory->base + 656 memory_region_size(&machine->device_memory->mr); 657 uint32_t node, buf_len, nr_entries = 0; 658 SpaprDrc *drc; 659 DrconfCellQueue *elem, *next; 660 MemoryDeviceInfoList *info; 661 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 662 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 663 664 /* Entry to cover RAM and the gap area */ 665 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 666 SPAPR_LMB_FLAGS_RESERVED | 667 SPAPR_LMB_FLAGS_DRC_INVALID); 668 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 669 nr_entries++; 670 671 cur_addr = machine->device_memory->base; 672 for (info = dimms; info; info = info->next) { 673 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 674 675 addr = di->addr; 676 size = di->size; 677 node = di->node; 678 679 /* 680 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 681 * area is marked hotpluggable in the next iteration for the bigger 682 * chunk including the NVDIMM occupied area. 683 */ 684 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 685 continue; 686 687 /* Entry for hot-pluggable area */ 688 if (cur_addr < addr) { 689 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 690 g_assert(drc); 691 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 692 cur_addr, spapr_drc_index(drc), -1, 0); 693 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 694 nr_entries++; 695 } 696 697 /* Entry for DIMM */ 698 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 699 g_assert(drc); 700 elem = spapr_get_drconf_cell(size / lmb_size, addr, 701 spapr_drc_index(drc), node, 702 SPAPR_LMB_FLAGS_ASSIGNED); 703 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 704 nr_entries++; 705 cur_addr = addr + size; 706 } 707 708 /* Entry for remaining hotpluggable area */ 709 if (cur_addr < mem_end) { 710 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 711 g_assert(drc); 712 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 713 cur_addr, spapr_drc_index(drc), -1, 0); 714 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 715 nr_entries++; 716 } 717 718 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 719 int_buf = cur_index = g_malloc0(buf_len); 720 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 721 cur_index += sizeof(nr_entries); 722 723 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 724 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 725 cur_index += sizeof(elem->cell); 726 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 727 g_free(elem); 728 } 729 730 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 731 g_free(int_buf); 732 if (ret < 0) { 733 return -1; 734 } 735 return 0; 736 } 737 738 /* ibm,dynamic-memory */ 739 static int spapr_populate_drmem_v1(SpaprMachineState *spapr, void *fdt, 740 int offset, MemoryDeviceInfoList *dimms) 741 { 742 MachineState *machine = MACHINE(spapr); 743 int i, ret; 744 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 745 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 746 uint32_t nr_lmbs = (machine->device_memory->base + 747 memory_region_size(&machine->device_memory->mr)) / 748 lmb_size; 749 uint32_t *int_buf, *cur_index, buf_len; 750 751 /* 752 * Allocate enough buffer size to fit in ibm,dynamic-memory 753 */ 754 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 755 cur_index = int_buf = g_malloc0(buf_len); 756 int_buf[0] = cpu_to_be32(nr_lmbs); 757 cur_index++; 758 for (i = 0; i < nr_lmbs; i++) { 759 uint64_t addr = i * lmb_size; 760 uint32_t *dynamic_memory = cur_index; 761 762 if (i >= device_lmb_start) { 763 SpaprDrc *drc; 764 765 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 766 g_assert(drc); 767 768 dynamic_memory[0] = cpu_to_be32(addr >> 32); 769 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 770 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 771 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 772 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 773 if (memory_region_present(get_system_memory(), addr)) { 774 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 775 } else { 776 dynamic_memory[5] = cpu_to_be32(0); 777 } 778 } else { 779 /* 780 * LMB information for RMA, boot time RAM and gap b/n RAM and 781 * device memory region -- all these are marked as reserved 782 * and as having no valid DRC. 783 */ 784 dynamic_memory[0] = cpu_to_be32(addr >> 32); 785 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 786 dynamic_memory[2] = cpu_to_be32(0); 787 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 788 dynamic_memory[4] = cpu_to_be32(-1); 789 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 790 SPAPR_LMB_FLAGS_DRC_INVALID); 791 } 792 793 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 794 } 795 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 796 g_free(int_buf); 797 if (ret < 0) { 798 return -1; 799 } 800 return 0; 801 } 802 803 /* 804 * Adds ibm,dynamic-reconfiguration-memory node. 805 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 806 * of this device tree node. 807 */ 808 static int spapr_populate_drconf_memory(SpaprMachineState *spapr, void *fdt) 809 { 810 MachineState *machine = MACHINE(spapr); 811 int nb_numa_nodes = machine->numa_state->num_nodes; 812 int ret, i, offset; 813 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 814 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 815 uint32_t *int_buf, *cur_index, buf_len; 816 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 817 MemoryDeviceInfoList *dimms = NULL; 818 819 /* 820 * Don't create the node if there is no device memory 821 */ 822 if (machine->ram_size == machine->maxram_size) { 823 return 0; 824 } 825 826 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 827 828 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 829 sizeof(prop_lmb_size)); 830 if (ret < 0) { 831 return ret; 832 } 833 834 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 835 if (ret < 0) { 836 return ret; 837 } 838 839 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 840 if (ret < 0) { 841 return ret; 842 } 843 844 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 845 dimms = qmp_memory_device_list(); 846 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 847 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 848 } else { 849 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 850 } 851 qapi_free_MemoryDeviceInfoList(dimms); 852 853 if (ret < 0) { 854 return ret; 855 } 856 857 /* ibm,associativity-lookup-arrays */ 858 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 859 cur_index = int_buf = g_malloc0(buf_len); 860 int_buf[0] = cpu_to_be32(nr_nodes); 861 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 862 cur_index += 2; 863 for (i = 0; i < nr_nodes; i++) { 864 uint32_t associativity[] = { 865 cpu_to_be32(0x0), 866 cpu_to_be32(0x0), 867 cpu_to_be32(0x0), 868 cpu_to_be32(i) 869 }; 870 memcpy(cur_index, associativity, sizeof(associativity)); 871 cur_index += 4; 872 } 873 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 874 (cur_index - int_buf) * sizeof(uint32_t)); 875 g_free(int_buf); 876 877 return ret; 878 } 879 880 static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt, 881 SpaprOptionVector *ov5_updates) 882 { 883 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 884 int ret = 0, offset; 885 886 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 887 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 888 g_assert(smc->dr_lmb_enabled); 889 ret = spapr_populate_drconf_memory(spapr, fdt); 890 if (ret) { 891 return ret; 892 } 893 } 894 895 offset = fdt_path_offset(fdt, "/chosen"); 896 if (offset < 0) { 897 offset = fdt_add_subnode(fdt, 0, "chosen"); 898 if (offset < 0) { 899 return offset; 900 } 901 } 902 return spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 903 "ibm,architecture-vec-5"); 904 } 905 906 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 907 { 908 MachineState *ms = MACHINE(spapr); 909 int rtas; 910 GString *hypertas = g_string_sized_new(256); 911 GString *qemu_hypertas = g_string_sized_new(256); 912 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 913 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 914 memory_region_size(&MACHINE(spapr)->device_memory->mr); 915 uint32_t lrdr_capacity[] = { 916 cpu_to_be32(max_device_addr >> 32), 917 cpu_to_be32(max_device_addr & 0xffffffff), 918 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 919 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 920 }; 921 uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0); 922 uint32_t maxdomains[] = { 923 cpu_to_be32(4), 924 maxdomain, 925 maxdomain, 926 maxdomain, 927 cpu_to_be32(spapr->gpu_numa_id), 928 }; 929 930 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 931 932 /* hypertas */ 933 add_str(hypertas, "hcall-pft"); 934 add_str(hypertas, "hcall-term"); 935 add_str(hypertas, "hcall-dabr"); 936 add_str(hypertas, "hcall-interrupt"); 937 add_str(hypertas, "hcall-tce"); 938 add_str(hypertas, "hcall-vio"); 939 add_str(hypertas, "hcall-splpar"); 940 add_str(hypertas, "hcall-join"); 941 add_str(hypertas, "hcall-bulk"); 942 add_str(hypertas, "hcall-set-mode"); 943 add_str(hypertas, "hcall-sprg0"); 944 add_str(hypertas, "hcall-copy"); 945 add_str(hypertas, "hcall-debug"); 946 add_str(hypertas, "hcall-vphn"); 947 add_str(qemu_hypertas, "hcall-memop1"); 948 949 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 950 add_str(hypertas, "hcall-multi-tce"); 951 } 952 953 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 954 add_str(hypertas, "hcall-hpt-resize"); 955 } 956 957 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 958 hypertas->str, hypertas->len)); 959 g_string_free(hypertas, TRUE); 960 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 961 qemu_hypertas->str, qemu_hypertas->len)); 962 g_string_free(qemu_hypertas, TRUE); 963 964 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 965 refpoints, sizeof(refpoints))); 966 967 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 968 maxdomains, sizeof(maxdomains))); 969 970 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 971 RTAS_ERROR_LOG_MAX)); 972 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 973 RTAS_EVENT_SCAN_RATE)); 974 975 g_assert(msi_nonbroken); 976 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 977 978 /* 979 * According to PAPR, rtas ibm,os-term does not guarantee a return 980 * back to the guest cpu. 981 * 982 * While an additional ibm,extended-os-term property indicates 983 * that rtas call return will always occur. Set this property. 984 */ 985 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 986 987 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 988 lrdr_capacity, sizeof(lrdr_capacity))); 989 990 spapr_dt_rtas_tokens(fdt, rtas); 991 } 992 993 /* 994 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 995 * and the XIVE features that the guest may request and thus the valid 996 * values for bytes 23..26 of option vector 5: 997 */ 998 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 999 int chosen) 1000 { 1001 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1002 1003 char val[2 * 4] = { 1004 23, 0x00, /* XICS / XIVE mode */ 1005 24, 0x00, /* Hash/Radix, filled in below. */ 1006 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1007 26, 0x40, /* Radix options: GTSE == yes. */ 1008 }; 1009 1010 if (spapr->irq->xics && spapr->irq->xive) { 1011 val[1] = SPAPR_OV5_XIVE_BOTH; 1012 } else if (spapr->irq->xive) { 1013 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1014 } else { 1015 assert(spapr->irq->xics); 1016 val[1] = SPAPR_OV5_XIVE_LEGACY; 1017 } 1018 1019 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1020 first_ppc_cpu->compat_pvr)) { 1021 /* 1022 * If we're in a pre POWER9 compat mode then the guest should 1023 * do hash and use the legacy interrupt mode 1024 */ 1025 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1026 val[3] = 0x00; /* Hash */ 1027 } else if (kvm_enabled()) { 1028 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1029 val[3] = 0x80; /* OV5_MMU_BOTH */ 1030 } else if (kvmppc_has_cap_mmu_radix()) { 1031 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1032 } else { 1033 val[3] = 0x00; /* Hash */ 1034 } 1035 } else { 1036 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1037 val[3] = 0xC0; 1038 } 1039 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1040 val, sizeof(val))); 1041 } 1042 1043 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt) 1044 { 1045 MachineState *machine = MACHINE(spapr); 1046 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1047 int chosen; 1048 const char *boot_device = machine->boot_order; 1049 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1050 size_t cb = 0; 1051 char *bootlist = get_boot_devices_list(&cb); 1052 1053 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1054 1055 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1056 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1057 machine->kernel_cmdline)); 1058 } 1059 if (spapr->initrd_size) { 1060 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1061 spapr->initrd_base)); 1062 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1063 spapr->initrd_base + spapr->initrd_size)); 1064 } 1065 1066 if (spapr->kernel_size) { 1067 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1068 cpu_to_be64(spapr->kernel_size) }; 1069 1070 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1071 &kprop, sizeof(kprop))); 1072 if (spapr->kernel_le) { 1073 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1074 } 1075 } 1076 if (boot_menu) { 1077 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1078 } 1079 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1080 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1081 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1082 1083 if (cb && bootlist) { 1084 int i; 1085 1086 for (i = 0; i < cb; i++) { 1087 if (bootlist[i] == '\n') { 1088 bootlist[i] = ' '; 1089 } 1090 } 1091 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1092 } 1093 1094 if (boot_device && strlen(boot_device)) { 1095 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1096 } 1097 1098 if (!spapr->has_graphics && stdout_path) { 1099 /* 1100 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1101 * kernel. New platforms should only use the "stdout-path" property. Set 1102 * the new property and continue using older property to remain 1103 * compatible with the existing firmware. 1104 */ 1105 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1106 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1107 } 1108 1109 /* We can deal with BAR reallocation just fine, advertise it to the guest */ 1110 if (smc->linux_pci_probe) { 1111 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1112 } 1113 1114 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1115 1116 g_free(stdout_path); 1117 g_free(bootlist); 1118 } 1119 1120 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1121 { 1122 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1123 * KVM to work under pHyp with some guest co-operation */ 1124 int hypervisor; 1125 uint8_t hypercall[16]; 1126 1127 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1128 /* indicate KVM hypercall interface */ 1129 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1130 if (kvmppc_has_cap_fixup_hcalls()) { 1131 /* 1132 * Older KVM versions with older guest kernels were broken 1133 * with the magic page, don't allow the guest to map it. 1134 */ 1135 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1136 sizeof(hypercall))) { 1137 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1138 hypercall, sizeof(hypercall))); 1139 } 1140 } 1141 } 1142 1143 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1144 { 1145 MachineState *machine = MACHINE(spapr); 1146 MachineClass *mc = MACHINE_GET_CLASS(machine); 1147 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1148 int ret; 1149 void *fdt; 1150 SpaprPhbState *phb; 1151 char *buf; 1152 1153 fdt = g_malloc0(space); 1154 _FDT((fdt_create_empty_tree(fdt, space))); 1155 1156 /* Root node */ 1157 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1158 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1159 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1160 1161 /* Guest UUID & Name*/ 1162 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1163 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1164 if (qemu_uuid_set) { 1165 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1166 } 1167 g_free(buf); 1168 1169 if (qemu_get_vm_name()) { 1170 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1171 qemu_get_vm_name())); 1172 } 1173 1174 /* Host Model & Serial Number */ 1175 if (spapr->host_model) { 1176 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1177 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1178 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1179 g_free(buf); 1180 } 1181 1182 if (spapr->host_serial) { 1183 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1184 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1185 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1186 g_free(buf); 1187 } 1188 1189 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1190 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1191 1192 /* /interrupt controller */ 1193 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1194 1195 ret = spapr_populate_memory(spapr, fdt); 1196 if (ret < 0) { 1197 error_report("couldn't setup memory nodes in fdt"); 1198 exit(1); 1199 } 1200 1201 /* /vdevice */ 1202 spapr_dt_vdevice(spapr->vio_bus, fdt); 1203 1204 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1205 ret = spapr_rng_populate_dt(fdt); 1206 if (ret < 0) { 1207 error_report("could not set up rng device in the fdt"); 1208 exit(1); 1209 } 1210 } 1211 1212 QLIST_FOREACH(phb, &spapr->phbs, list) { 1213 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1214 if (ret < 0) { 1215 error_report("couldn't setup PCI devices in fdt"); 1216 exit(1); 1217 } 1218 } 1219 1220 /* cpus */ 1221 spapr_populate_cpus_dt_node(fdt, spapr); 1222 1223 if (smc->dr_lmb_enabled) { 1224 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1225 } 1226 1227 if (mc->has_hotpluggable_cpus) { 1228 int offset = fdt_path_offset(fdt, "/cpus"); 1229 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1230 if (ret < 0) { 1231 error_report("Couldn't set up CPU DR device tree properties"); 1232 exit(1); 1233 } 1234 } 1235 1236 /* /event-sources */ 1237 spapr_dt_events(spapr, fdt); 1238 1239 /* /rtas */ 1240 spapr_dt_rtas(spapr, fdt); 1241 1242 /* /chosen */ 1243 if (reset) { 1244 spapr_dt_chosen(spapr, fdt); 1245 } 1246 1247 /* /hypervisor */ 1248 if (kvm_enabled()) { 1249 spapr_dt_hypervisor(spapr, fdt); 1250 } 1251 1252 /* Build memory reserve map */ 1253 if (reset) { 1254 if (spapr->kernel_size) { 1255 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1256 spapr->kernel_size))); 1257 } 1258 if (spapr->initrd_size) { 1259 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1260 spapr->initrd_size))); 1261 } 1262 } 1263 1264 /* ibm,client-architecture-support updates */ 1265 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1266 if (ret < 0) { 1267 error_report("couldn't setup CAS properties fdt"); 1268 exit(1); 1269 } 1270 1271 if (smc->dr_phb_enabled) { 1272 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); 1273 if (ret < 0) { 1274 error_report("Couldn't set up PHB DR device tree properties"); 1275 exit(1); 1276 } 1277 } 1278 1279 /* NVDIMM devices */ 1280 if (mc->nvdimm_supported) { 1281 spapr_dt_persistent_memory(fdt); 1282 } 1283 1284 return fdt; 1285 } 1286 1287 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1288 { 1289 SpaprMachineState *spapr = opaque; 1290 1291 return (addr & 0x0fffffff) + spapr->kernel_addr; 1292 } 1293 1294 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1295 PowerPCCPU *cpu) 1296 { 1297 CPUPPCState *env = &cpu->env; 1298 1299 /* The TCG path should also be holding the BQL at this point */ 1300 g_assert(qemu_mutex_iothread_locked()); 1301 1302 if (msr_pr) { 1303 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1304 env->gpr[3] = H_PRIVILEGE; 1305 } else { 1306 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1307 } 1308 } 1309 1310 struct LPCRSyncState { 1311 target_ulong value; 1312 target_ulong mask; 1313 }; 1314 1315 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1316 { 1317 struct LPCRSyncState *s = arg.host_ptr; 1318 PowerPCCPU *cpu = POWERPC_CPU(cs); 1319 CPUPPCState *env = &cpu->env; 1320 target_ulong lpcr; 1321 1322 cpu_synchronize_state(cs); 1323 lpcr = env->spr[SPR_LPCR]; 1324 lpcr &= ~s->mask; 1325 lpcr |= s->value; 1326 ppc_store_lpcr(cpu, lpcr); 1327 } 1328 1329 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1330 { 1331 CPUState *cs; 1332 struct LPCRSyncState s = { 1333 .value = value, 1334 .mask = mask 1335 }; 1336 CPU_FOREACH(cs) { 1337 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1338 } 1339 } 1340 1341 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1342 { 1343 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1344 1345 /* Copy PATE1:GR into PATE0:HR */ 1346 entry->dw0 = spapr->patb_entry & PATE0_HR; 1347 entry->dw1 = spapr->patb_entry; 1348 } 1349 1350 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1351 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1352 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1353 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1354 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1355 1356 /* 1357 * Get the fd to access the kernel htab, re-opening it if necessary 1358 */ 1359 static int get_htab_fd(SpaprMachineState *spapr) 1360 { 1361 Error *local_err = NULL; 1362 1363 if (spapr->htab_fd >= 0) { 1364 return spapr->htab_fd; 1365 } 1366 1367 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1368 if (spapr->htab_fd < 0) { 1369 error_report_err(local_err); 1370 } 1371 1372 return spapr->htab_fd; 1373 } 1374 1375 void close_htab_fd(SpaprMachineState *spapr) 1376 { 1377 if (spapr->htab_fd >= 0) { 1378 close(spapr->htab_fd); 1379 } 1380 spapr->htab_fd = -1; 1381 } 1382 1383 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1384 { 1385 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1386 1387 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1388 } 1389 1390 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1391 { 1392 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1393 1394 assert(kvm_enabled()); 1395 1396 if (!spapr->htab) { 1397 return 0; 1398 } 1399 1400 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1401 } 1402 1403 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1404 hwaddr ptex, int n) 1405 { 1406 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1407 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1408 1409 if (!spapr->htab) { 1410 /* 1411 * HTAB is controlled by KVM. Fetch into temporary buffer 1412 */ 1413 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1414 kvmppc_read_hptes(hptes, ptex, n); 1415 return hptes; 1416 } 1417 1418 /* 1419 * HTAB is controlled by QEMU. Just point to the internally 1420 * accessible PTEG. 1421 */ 1422 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1423 } 1424 1425 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1426 const ppc_hash_pte64_t *hptes, 1427 hwaddr ptex, int n) 1428 { 1429 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1430 1431 if (!spapr->htab) { 1432 g_free((void *)hptes); 1433 } 1434 1435 /* Nothing to do for qemu managed HPT */ 1436 } 1437 1438 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1439 uint64_t pte0, uint64_t pte1) 1440 { 1441 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1442 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1443 1444 if (!spapr->htab) { 1445 kvmppc_write_hpte(ptex, pte0, pte1); 1446 } else { 1447 if (pte0 & HPTE64_V_VALID) { 1448 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1449 /* 1450 * When setting valid, we write PTE1 first. This ensures 1451 * proper synchronization with the reading code in 1452 * ppc_hash64_pteg_search() 1453 */ 1454 smp_wmb(); 1455 stq_p(spapr->htab + offset, pte0); 1456 } else { 1457 stq_p(spapr->htab + offset, pte0); 1458 /* 1459 * When clearing it we set PTE0 first. This ensures proper 1460 * synchronization with the reading code in 1461 * ppc_hash64_pteg_search() 1462 */ 1463 smp_wmb(); 1464 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1465 } 1466 } 1467 } 1468 1469 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1470 uint64_t pte1) 1471 { 1472 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1473 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1474 1475 if (!spapr->htab) { 1476 /* There should always be a hash table when this is called */ 1477 error_report("spapr_hpte_set_c called with no hash table !"); 1478 return; 1479 } 1480 1481 /* The HW performs a non-atomic byte update */ 1482 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1483 } 1484 1485 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1486 uint64_t pte1) 1487 { 1488 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1489 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1490 1491 if (!spapr->htab) { 1492 /* There should always be a hash table when this is called */ 1493 error_report("spapr_hpte_set_r called with no hash table !"); 1494 return; 1495 } 1496 1497 /* The HW performs a non-atomic byte update */ 1498 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1499 } 1500 1501 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1502 { 1503 int shift; 1504 1505 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1506 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1507 * that's much more than is needed for Linux guests */ 1508 shift = ctz64(pow2ceil(ramsize)) - 7; 1509 shift = MAX(shift, 18); /* Minimum architected size */ 1510 shift = MIN(shift, 46); /* Maximum architected size */ 1511 return shift; 1512 } 1513 1514 void spapr_free_hpt(SpaprMachineState *spapr) 1515 { 1516 g_free(spapr->htab); 1517 spapr->htab = NULL; 1518 spapr->htab_shift = 0; 1519 close_htab_fd(spapr); 1520 } 1521 1522 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 1523 Error **errp) 1524 { 1525 long rc; 1526 1527 /* Clean up any HPT info from a previous boot */ 1528 spapr_free_hpt(spapr); 1529 1530 rc = kvmppc_reset_htab(shift); 1531 if (rc < 0) { 1532 /* kernel-side HPT needed, but couldn't allocate one */ 1533 error_setg_errno(errp, errno, 1534 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1535 shift); 1536 /* This is almost certainly fatal, but if the caller really 1537 * wants to carry on with shift == 0, it's welcome to try */ 1538 } else if (rc > 0) { 1539 /* kernel-side HPT allocated */ 1540 if (rc != shift) { 1541 error_setg(errp, 1542 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1543 shift, rc); 1544 } 1545 1546 spapr->htab_shift = shift; 1547 spapr->htab = NULL; 1548 } else { 1549 /* kernel-side HPT not needed, allocate in userspace instead */ 1550 size_t size = 1ULL << shift; 1551 int i; 1552 1553 spapr->htab = qemu_memalign(size, size); 1554 if (!spapr->htab) { 1555 error_setg_errno(errp, errno, 1556 "Could not allocate HPT of order %d", shift); 1557 return; 1558 } 1559 1560 memset(spapr->htab, 0, size); 1561 spapr->htab_shift = shift; 1562 1563 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1564 DIRTY_HPTE(HPTE(spapr->htab, i)); 1565 } 1566 } 1567 /* We're setting up a hash table, so that means we're not radix */ 1568 spapr->patb_entry = 0; 1569 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1570 } 1571 1572 void spapr_setup_hpt(SpaprMachineState *spapr) 1573 { 1574 int hpt_shift; 1575 1576 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1577 || (spapr->cas_reboot 1578 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1579 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1580 } else { 1581 uint64_t current_ram_size; 1582 1583 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1584 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1585 } 1586 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1587 1588 if (kvm_enabled()) { 1589 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1590 1591 /* Check our RMA fits in the possible VRMA */ 1592 if (vrma_limit < spapr->rma_size) { 1593 error_report("Unable to create %" HWADDR_PRIu 1594 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1595 spapr->rma_size / MiB, vrma_limit / MiB); 1596 exit(EXIT_FAILURE); 1597 } 1598 } 1599 } 1600 1601 static int spapr_reset_drcs(Object *child, void *opaque) 1602 { 1603 SpaprDrc *drc = 1604 (SpaprDrc *) object_dynamic_cast(child, 1605 TYPE_SPAPR_DR_CONNECTOR); 1606 1607 if (drc) { 1608 spapr_drc_reset(drc); 1609 } 1610 1611 return 0; 1612 } 1613 1614 static void spapr_machine_reset(MachineState *machine) 1615 { 1616 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1617 PowerPCCPU *first_ppc_cpu; 1618 hwaddr fdt_addr; 1619 void *fdt; 1620 int rc; 1621 1622 kvmppc_svm_off(&error_fatal); 1623 spapr_caps_apply(spapr); 1624 1625 first_ppc_cpu = POWERPC_CPU(first_cpu); 1626 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1627 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1628 spapr->max_compat_pvr)) { 1629 /* 1630 * If using KVM with radix mode available, VCPUs can be started 1631 * without a HPT because KVM will start them in radix mode. 1632 * Set the GR bit in PATE so that we know there is no HPT. 1633 */ 1634 spapr->patb_entry = PATE1_GR; 1635 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1636 } else { 1637 spapr_setup_hpt(spapr); 1638 } 1639 1640 qemu_devices_reset(); 1641 1642 /* 1643 * If this reset wasn't generated by CAS, we should reset our 1644 * negotiated options and start from scratch 1645 */ 1646 if (!spapr->cas_reboot) { 1647 spapr_ovec_cleanup(spapr->ov5_cas); 1648 spapr->ov5_cas = spapr_ovec_new(); 1649 1650 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1651 } 1652 1653 /* 1654 * This is fixing some of the default configuration of the XIVE 1655 * devices. To be called after the reset of the machine devices. 1656 */ 1657 spapr_irq_reset(spapr, &error_fatal); 1658 1659 /* 1660 * There is no CAS under qtest. Simulate one to please the code that 1661 * depends on spapr->ov5_cas. This is especially needed to test device 1662 * unplug, so we do that before resetting the DRCs. 1663 */ 1664 if (qtest_enabled()) { 1665 spapr_ovec_cleanup(spapr->ov5_cas); 1666 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1667 } 1668 1669 /* DRC reset may cause a device to be unplugged. This will cause troubles 1670 * if this device is used by another device (eg, a running vhost backend 1671 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1672 * situations, we reset DRCs after all devices have been reset. 1673 */ 1674 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1675 1676 spapr_clear_pending_events(spapr); 1677 1678 /* 1679 * We place the device tree and RTAS just below either the top of the RMA, 1680 * or just below 2GB, whichever is lower, so that it can be 1681 * processed with 32-bit real mode code if necessary 1682 */ 1683 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1684 1685 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1686 1687 rc = fdt_pack(fdt); 1688 1689 /* Should only fail if we've built a corrupted tree */ 1690 assert(rc == 0); 1691 1692 /* Load the fdt */ 1693 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1694 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1695 g_free(spapr->fdt_blob); 1696 spapr->fdt_size = fdt_totalsize(fdt); 1697 spapr->fdt_initial_size = spapr->fdt_size; 1698 spapr->fdt_blob = fdt; 1699 1700 /* Set up the entry state */ 1701 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); 1702 first_ppc_cpu->env.gpr[5] = 0; 1703 1704 spapr->cas_reboot = false; 1705 1706 spapr->mc_status = -1; 1707 spapr->guest_machine_check_addr = -1; 1708 1709 /* Signal all vCPUs waiting on this condition */ 1710 qemu_cond_broadcast(&spapr->mc_delivery_cond); 1711 1712 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1713 } 1714 1715 static void spapr_create_nvram(SpaprMachineState *spapr) 1716 { 1717 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1718 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1719 1720 if (dinfo) { 1721 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1722 &error_fatal); 1723 } 1724 1725 qdev_init_nofail(dev); 1726 1727 spapr->nvram = (struct SpaprNvram *)dev; 1728 } 1729 1730 static void spapr_rtc_create(SpaprMachineState *spapr) 1731 { 1732 object_initialize_child(OBJECT(spapr), "rtc", 1733 &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1734 &error_fatal, NULL); 1735 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1736 &error_fatal); 1737 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1738 "date", &error_fatal); 1739 } 1740 1741 /* Returns whether we want to use VGA or not */ 1742 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1743 { 1744 switch (vga_interface_type) { 1745 case VGA_NONE: 1746 return false; 1747 case VGA_DEVICE: 1748 return true; 1749 case VGA_STD: 1750 case VGA_VIRTIO: 1751 case VGA_CIRRUS: 1752 return pci_vga_init(pci_bus) != NULL; 1753 default: 1754 error_setg(errp, 1755 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1756 return false; 1757 } 1758 } 1759 1760 static int spapr_pre_load(void *opaque) 1761 { 1762 int rc; 1763 1764 rc = spapr_caps_pre_load(opaque); 1765 if (rc) { 1766 return rc; 1767 } 1768 1769 return 0; 1770 } 1771 1772 static int spapr_post_load(void *opaque, int version_id) 1773 { 1774 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1775 int err = 0; 1776 1777 err = spapr_caps_post_migration(spapr); 1778 if (err) { 1779 return err; 1780 } 1781 1782 /* 1783 * In earlier versions, there was no separate qdev for the PAPR 1784 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1785 * So when migrating from those versions, poke the incoming offset 1786 * value into the RTC device 1787 */ 1788 if (version_id < 3) { 1789 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1790 if (err) { 1791 return err; 1792 } 1793 } 1794 1795 if (kvm_enabled() && spapr->patb_entry) { 1796 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1797 bool radix = !!(spapr->patb_entry & PATE1_GR); 1798 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1799 1800 /* 1801 * Update LPCR:HR and UPRT as they may not be set properly in 1802 * the stream 1803 */ 1804 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1805 LPCR_HR | LPCR_UPRT); 1806 1807 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1808 if (err) { 1809 error_report("Process table config unsupported by the host"); 1810 return -EINVAL; 1811 } 1812 } 1813 1814 err = spapr_irq_post_load(spapr, version_id); 1815 if (err) { 1816 return err; 1817 } 1818 1819 return err; 1820 } 1821 1822 static int spapr_pre_save(void *opaque) 1823 { 1824 int rc; 1825 1826 rc = spapr_caps_pre_save(opaque); 1827 if (rc) { 1828 return rc; 1829 } 1830 1831 return 0; 1832 } 1833 1834 static bool version_before_3(void *opaque, int version_id) 1835 { 1836 return version_id < 3; 1837 } 1838 1839 static bool spapr_pending_events_needed(void *opaque) 1840 { 1841 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1842 return !QTAILQ_EMPTY(&spapr->pending_events); 1843 } 1844 1845 static const VMStateDescription vmstate_spapr_event_entry = { 1846 .name = "spapr_event_log_entry", 1847 .version_id = 1, 1848 .minimum_version_id = 1, 1849 .fields = (VMStateField[]) { 1850 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1851 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1852 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1853 NULL, extended_length), 1854 VMSTATE_END_OF_LIST() 1855 }, 1856 }; 1857 1858 static const VMStateDescription vmstate_spapr_pending_events = { 1859 .name = "spapr_pending_events", 1860 .version_id = 1, 1861 .minimum_version_id = 1, 1862 .needed = spapr_pending_events_needed, 1863 .fields = (VMStateField[]) { 1864 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1865 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1866 VMSTATE_END_OF_LIST() 1867 }, 1868 }; 1869 1870 static bool spapr_ov5_cas_needed(void *opaque) 1871 { 1872 SpaprMachineState *spapr = opaque; 1873 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1874 bool cas_needed; 1875 1876 /* Prior to the introduction of SpaprOptionVector, we had two option 1877 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1878 * Both of these options encode machine topology into the device-tree 1879 * in such a way that the now-booted OS should still be able to interact 1880 * appropriately with QEMU regardless of what options were actually 1881 * negotiatied on the source side. 1882 * 1883 * As such, we can avoid migrating the CAS-negotiated options if these 1884 * are the only options available on the current machine/platform. 1885 * Since these are the only options available for pseries-2.7 and 1886 * earlier, this allows us to maintain old->new/new->old migration 1887 * compatibility. 1888 * 1889 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1890 * via default pseries-2.8 machines and explicit command-line parameters. 1891 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1892 * of the actual CAS-negotiated values to continue working properly. For 1893 * example, availability of memory unplug depends on knowing whether 1894 * OV5_HP_EVT was negotiated via CAS. 1895 * 1896 * Thus, for any cases where the set of available CAS-negotiatable 1897 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1898 * include the CAS-negotiated options in the migration stream, unless 1899 * if they affect boot time behaviour only. 1900 */ 1901 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1902 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1903 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1904 1905 /* We need extra information if we have any bits outside the mask 1906 * defined above */ 1907 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1908 1909 spapr_ovec_cleanup(ov5_mask); 1910 1911 return cas_needed; 1912 } 1913 1914 static const VMStateDescription vmstate_spapr_ov5_cas = { 1915 .name = "spapr_option_vector_ov5_cas", 1916 .version_id = 1, 1917 .minimum_version_id = 1, 1918 .needed = spapr_ov5_cas_needed, 1919 .fields = (VMStateField[]) { 1920 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1921 vmstate_spapr_ovec, SpaprOptionVector), 1922 VMSTATE_END_OF_LIST() 1923 }, 1924 }; 1925 1926 static bool spapr_patb_entry_needed(void *opaque) 1927 { 1928 SpaprMachineState *spapr = opaque; 1929 1930 return !!spapr->patb_entry; 1931 } 1932 1933 static const VMStateDescription vmstate_spapr_patb_entry = { 1934 .name = "spapr_patb_entry", 1935 .version_id = 1, 1936 .minimum_version_id = 1, 1937 .needed = spapr_patb_entry_needed, 1938 .fields = (VMStateField[]) { 1939 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1940 VMSTATE_END_OF_LIST() 1941 }, 1942 }; 1943 1944 static bool spapr_irq_map_needed(void *opaque) 1945 { 1946 SpaprMachineState *spapr = opaque; 1947 1948 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1949 } 1950 1951 static const VMStateDescription vmstate_spapr_irq_map = { 1952 .name = "spapr_irq_map", 1953 .version_id = 1, 1954 .minimum_version_id = 1, 1955 .needed = spapr_irq_map_needed, 1956 .fields = (VMStateField[]) { 1957 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1958 VMSTATE_END_OF_LIST() 1959 }, 1960 }; 1961 1962 static bool spapr_dtb_needed(void *opaque) 1963 { 1964 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1965 1966 return smc->update_dt_enabled; 1967 } 1968 1969 static int spapr_dtb_pre_load(void *opaque) 1970 { 1971 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1972 1973 g_free(spapr->fdt_blob); 1974 spapr->fdt_blob = NULL; 1975 spapr->fdt_size = 0; 1976 1977 return 0; 1978 } 1979 1980 static const VMStateDescription vmstate_spapr_dtb = { 1981 .name = "spapr_dtb", 1982 .version_id = 1, 1983 .minimum_version_id = 1, 1984 .needed = spapr_dtb_needed, 1985 .pre_load = spapr_dtb_pre_load, 1986 .fields = (VMStateField[]) { 1987 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1988 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1989 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1990 fdt_size), 1991 VMSTATE_END_OF_LIST() 1992 }, 1993 }; 1994 1995 static bool spapr_fwnmi_needed(void *opaque) 1996 { 1997 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1998 1999 return spapr->guest_machine_check_addr != -1; 2000 } 2001 2002 static int spapr_fwnmi_pre_save(void *opaque) 2003 { 2004 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2005 2006 /* 2007 * Check if machine check handling is in progress and print a 2008 * warning message. 2009 */ 2010 if (spapr->mc_status != -1) { 2011 warn_report("A machine check is being handled during migration. The" 2012 "handler may run and log hardware error on the destination"); 2013 } 2014 2015 return 0; 2016 } 2017 2018 static const VMStateDescription vmstate_spapr_machine_check = { 2019 .name = "spapr_machine_check", 2020 .version_id = 1, 2021 .minimum_version_id = 1, 2022 .needed = spapr_fwnmi_needed, 2023 .pre_save = spapr_fwnmi_pre_save, 2024 .fields = (VMStateField[]) { 2025 VMSTATE_UINT64(guest_machine_check_addr, SpaprMachineState), 2026 VMSTATE_INT32(mc_status, SpaprMachineState), 2027 VMSTATE_END_OF_LIST() 2028 }, 2029 }; 2030 2031 static const VMStateDescription vmstate_spapr = { 2032 .name = "spapr", 2033 .version_id = 3, 2034 .minimum_version_id = 1, 2035 .pre_load = spapr_pre_load, 2036 .post_load = spapr_post_load, 2037 .pre_save = spapr_pre_save, 2038 .fields = (VMStateField[]) { 2039 /* used to be @next_irq */ 2040 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2041 2042 /* RTC offset */ 2043 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2044 2045 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2046 VMSTATE_END_OF_LIST() 2047 }, 2048 .subsections = (const VMStateDescription*[]) { 2049 &vmstate_spapr_ov5_cas, 2050 &vmstate_spapr_patb_entry, 2051 &vmstate_spapr_pending_events, 2052 &vmstate_spapr_cap_htm, 2053 &vmstate_spapr_cap_vsx, 2054 &vmstate_spapr_cap_dfp, 2055 &vmstate_spapr_cap_cfpc, 2056 &vmstate_spapr_cap_sbbc, 2057 &vmstate_spapr_cap_ibs, 2058 &vmstate_spapr_cap_hpt_maxpagesize, 2059 &vmstate_spapr_irq_map, 2060 &vmstate_spapr_cap_nested_kvm_hv, 2061 &vmstate_spapr_dtb, 2062 &vmstate_spapr_cap_large_decr, 2063 &vmstate_spapr_cap_ccf_assist, 2064 &vmstate_spapr_cap_fwnmi, 2065 &vmstate_spapr_machine_check, 2066 NULL 2067 } 2068 }; 2069 2070 static int htab_save_setup(QEMUFile *f, void *opaque) 2071 { 2072 SpaprMachineState *spapr = opaque; 2073 2074 /* "Iteration" header */ 2075 if (!spapr->htab_shift) { 2076 qemu_put_be32(f, -1); 2077 } else { 2078 qemu_put_be32(f, spapr->htab_shift); 2079 } 2080 2081 if (spapr->htab) { 2082 spapr->htab_save_index = 0; 2083 spapr->htab_first_pass = true; 2084 } else { 2085 if (spapr->htab_shift) { 2086 assert(kvm_enabled()); 2087 } 2088 } 2089 2090 2091 return 0; 2092 } 2093 2094 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2095 int chunkstart, int n_valid, int n_invalid) 2096 { 2097 qemu_put_be32(f, chunkstart); 2098 qemu_put_be16(f, n_valid); 2099 qemu_put_be16(f, n_invalid); 2100 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2101 HASH_PTE_SIZE_64 * n_valid); 2102 } 2103 2104 static void htab_save_end_marker(QEMUFile *f) 2105 { 2106 qemu_put_be32(f, 0); 2107 qemu_put_be16(f, 0); 2108 qemu_put_be16(f, 0); 2109 } 2110 2111 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2112 int64_t max_ns) 2113 { 2114 bool has_timeout = max_ns != -1; 2115 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2116 int index = spapr->htab_save_index; 2117 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2118 2119 assert(spapr->htab_first_pass); 2120 2121 do { 2122 int chunkstart; 2123 2124 /* Consume invalid HPTEs */ 2125 while ((index < htabslots) 2126 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2127 CLEAN_HPTE(HPTE(spapr->htab, index)); 2128 index++; 2129 } 2130 2131 /* Consume valid HPTEs */ 2132 chunkstart = index; 2133 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2134 && HPTE_VALID(HPTE(spapr->htab, index))) { 2135 CLEAN_HPTE(HPTE(spapr->htab, index)); 2136 index++; 2137 } 2138 2139 if (index > chunkstart) { 2140 int n_valid = index - chunkstart; 2141 2142 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2143 2144 if (has_timeout && 2145 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2146 break; 2147 } 2148 } 2149 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2150 2151 if (index >= htabslots) { 2152 assert(index == htabslots); 2153 index = 0; 2154 spapr->htab_first_pass = false; 2155 } 2156 spapr->htab_save_index = index; 2157 } 2158 2159 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2160 int64_t max_ns) 2161 { 2162 bool final = max_ns < 0; 2163 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2164 int examined = 0, sent = 0; 2165 int index = spapr->htab_save_index; 2166 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2167 2168 assert(!spapr->htab_first_pass); 2169 2170 do { 2171 int chunkstart, invalidstart; 2172 2173 /* Consume non-dirty HPTEs */ 2174 while ((index < htabslots) 2175 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2176 index++; 2177 examined++; 2178 } 2179 2180 chunkstart = index; 2181 /* Consume valid dirty HPTEs */ 2182 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2183 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2184 && HPTE_VALID(HPTE(spapr->htab, index))) { 2185 CLEAN_HPTE(HPTE(spapr->htab, index)); 2186 index++; 2187 examined++; 2188 } 2189 2190 invalidstart = index; 2191 /* Consume invalid dirty HPTEs */ 2192 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2193 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2194 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2195 CLEAN_HPTE(HPTE(spapr->htab, index)); 2196 index++; 2197 examined++; 2198 } 2199 2200 if (index > chunkstart) { 2201 int n_valid = invalidstart - chunkstart; 2202 int n_invalid = index - invalidstart; 2203 2204 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2205 sent += index - chunkstart; 2206 2207 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2208 break; 2209 } 2210 } 2211 2212 if (examined >= htabslots) { 2213 break; 2214 } 2215 2216 if (index >= htabslots) { 2217 assert(index == htabslots); 2218 index = 0; 2219 } 2220 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2221 2222 if (index >= htabslots) { 2223 assert(index == htabslots); 2224 index = 0; 2225 } 2226 2227 spapr->htab_save_index = index; 2228 2229 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2230 } 2231 2232 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2233 #define MAX_KVM_BUF_SIZE 2048 2234 2235 static int htab_save_iterate(QEMUFile *f, void *opaque) 2236 { 2237 SpaprMachineState *spapr = opaque; 2238 int fd; 2239 int rc = 0; 2240 2241 /* Iteration header */ 2242 if (!spapr->htab_shift) { 2243 qemu_put_be32(f, -1); 2244 return 1; 2245 } else { 2246 qemu_put_be32(f, 0); 2247 } 2248 2249 if (!spapr->htab) { 2250 assert(kvm_enabled()); 2251 2252 fd = get_htab_fd(spapr); 2253 if (fd < 0) { 2254 return fd; 2255 } 2256 2257 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2258 if (rc < 0) { 2259 return rc; 2260 } 2261 } else if (spapr->htab_first_pass) { 2262 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2263 } else { 2264 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2265 } 2266 2267 htab_save_end_marker(f); 2268 2269 return rc; 2270 } 2271 2272 static int htab_save_complete(QEMUFile *f, void *opaque) 2273 { 2274 SpaprMachineState *spapr = opaque; 2275 int fd; 2276 2277 /* Iteration header */ 2278 if (!spapr->htab_shift) { 2279 qemu_put_be32(f, -1); 2280 return 0; 2281 } else { 2282 qemu_put_be32(f, 0); 2283 } 2284 2285 if (!spapr->htab) { 2286 int rc; 2287 2288 assert(kvm_enabled()); 2289 2290 fd = get_htab_fd(spapr); 2291 if (fd < 0) { 2292 return fd; 2293 } 2294 2295 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2296 if (rc < 0) { 2297 return rc; 2298 } 2299 } else { 2300 if (spapr->htab_first_pass) { 2301 htab_save_first_pass(f, spapr, -1); 2302 } 2303 htab_save_later_pass(f, spapr, -1); 2304 } 2305 2306 /* End marker */ 2307 htab_save_end_marker(f); 2308 2309 return 0; 2310 } 2311 2312 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2313 { 2314 SpaprMachineState *spapr = opaque; 2315 uint32_t section_hdr; 2316 int fd = -1; 2317 Error *local_err = NULL; 2318 2319 if (version_id < 1 || version_id > 1) { 2320 error_report("htab_load() bad version"); 2321 return -EINVAL; 2322 } 2323 2324 section_hdr = qemu_get_be32(f); 2325 2326 if (section_hdr == -1) { 2327 spapr_free_hpt(spapr); 2328 return 0; 2329 } 2330 2331 if (section_hdr) { 2332 /* First section gives the htab size */ 2333 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2334 if (local_err) { 2335 error_report_err(local_err); 2336 return -EINVAL; 2337 } 2338 return 0; 2339 } 2340 2341 if (!spapr->htab) { 2342 assert(kvm_enabled()); 2343 2344 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2345 if (fd < 0) { 2346 error_report_err(local_err); 2347 return fd; 2348 } 2349 } 2350 2351 while (true) { 2352 uint32_t index; 2353 uint16_t n_valid, n_invalid; 2354 2355 index = qemu_get_be32(f); 2356 n_valid = qemu_get_be16(f); 2357 n_invalid = qemu_get_be16(f); 2358 2359 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2360 /* End of Stream */ 2361 break; 2362 } 2363 2364 if ((index + n_valid + n_invalid) > 2365 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2366 /* Bad index in stream */ 2367 error_report( 2368 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2369 index, n_valid, n_invalid, spapr->htab_shift); 2370 return -EINVAL; 2371 } 2372 2373 if (spapr->htab) { 2374 if (n_valid) { 2375 qemu_get_buffer(f, HPTE(spapr->htab, index), 2376 HASH_PTE_SIZE_64 * n_valid); 2377 } 2378 if (n_invalid) { 2379 memset(HPTE(spapr->htab, index + n_valid), 0, 2380 HASH_PTE_SIZE_64 * n_invalid); 2381 } 2382 } else { 2383 int rc; 2384 2385 assert(fd >= 0); 2386 2387 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2388 if (rc < 0) { 2389 return rc; 2390 } 2391 } 2392 } 2393 2394 if (!spapr->htab) { 2395 assert(fd >= 0); 2396 close(fd); 2397 } 2398 2399 return 0; 2400 } 2401 2402 static void htab_save_cleanup(void *opaque) 2403 { 2404 SpaprMachineState *spapr = opaque; 2405 2406 close_htab_fd(spapr); 2407 } 2408 2409 static SaveVMHandlers savevm_htab_handlers = { 2410 .save_setup = htab_save_setup, 2411 .save_live_iterate = htab_save_iterate, 2412 .save_live_complete_precopy = htab_save_complete, 2413 .save_cleanup = htab_save_cleanup, 2414 .load_state = htab_load, 2415 }; 2416 2417 static void spapr_boot_set(void *opaque, const char *boot_device, 2418 Error **errp) 2419 { 2420 MachineState *machine = MACHINE(opaque); 2421 machine->boot_order = g_strdup(boot_device); 2422 } 2423 2424 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2425 { 2426 MachineState *machine = MACHINE(spapr); 2427 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2428 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2429 int i; 2430 2431 for (i = 0; i < nr_lmbs; i++) { 2432 uint64_t addr; 2433 2434 addr = i * lmb_size + machine->device_memory->base; 2435 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2436 addr / lmb_size); 2437 } 2438 } 2439 2440 /* 2441 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2442 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2443 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2444 */ 2445 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2446 { 2447 int i; 2448 2449 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2450 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2451 " is not aligned to %" PRIu64 " MiB", 2452 machine->ram_size, 2453 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2454 return; 2455 } 2456 2457 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2458 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2459 " is not aligned to %" PRIu64 " MiB", 2460 machine->ram_size, 2461 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2462 return; 2463 } 2464 2465 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2466 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2467 error_setg(errp, 2468 "Node %d memory size 0x%" PRIx64 2469 " is not aligned to %" PRIu64 " MiB", 2470 i, machine->numa_state->nodes[i].node_mem, 2471 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2472 return; 2473 } 2474 } 2475 } 2476 2477 /* find cpu slot in machine->possible_cpus by core_id */ 2478 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2479 { 2480 int index = id / ms->smp.threads; 2481 2482 if (index >= ms->possible_cpus->len) { 2483 return NULL; 2484 } 2485 if (idx) { 2486 *idx = index; 2487 } 2488 return &ms->possible_cpus->cpus[index]; 2489 } 2490 2491 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2492 { 2493 MachineState *ms = MACHINE(spapr); 2494 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2495 Error *local_err = NULL; 2496 bool vsmt_user = !!spapr->vsmt; 2497 int kvm_smt = kvmppc_smt_threads(); 2498 int ret; 2499 unsigned int smp_threads = ms->smp.threads; 2500 2501 if (!kvm_enabled() && (smp_threads > 1)) { 2502 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2503 "on a pseries machine"); 2504 goto out; 2505 } 2506 if (!is_power_of_2(smp_threads)) { 2507 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2508 "machine because it must be a power of 2", smp_threads); 2509 goto out; 2510 } 2511 2512 /* Detemine the VSMT mode to use: */ 2513 if (vsmt_user) { 2514 if (spapr->vsmt < smp_threads) { 2515 error_setg(&local_err, "Cannot support VSMT mode %d" 2516 " because it must be >= threads/core (%d)", 2517 spapr->vsmt, smp_threads); 2518 goto out; 2519 } 2520 /* In this case, spapr->vsmt has been set by the command line */ 2521 } else if (!smc->smp_threads_vsmt) { 2522 /* 2523 * Default VSMT value is tricky, because we need it to be as 2524 * consistent as possible (for migration), but this requires 2525 * changing it for at least some existing cases. We pick 8 as 2526 * the value that we'd get with KVM on POWER8, the 2527 * overwhelmingly common case in production systems. 2528 */ 2529 spapr->vsmt = MAX(8, smp_threads); 2530 } else { 2531 spapr->vsmt = smp_threads; 2532 } 2533 2534 /* KVM: If necessary, set the SMT mode: */ 2535 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2536 ret = kvmppc_set_smt_threads(spapr->vsmt); 2537 if (ret) { 2538 /* Looks like KVM isn't able to change VSMT mode */ 2539 error_setg(&local_err, 2540 "Failed to set KVM's VSMT mode to %d (errno %d)", 2541 spapr->vsmt, ret); 2542 /* We can live with that if the default one is big enough 2543 * for the number of threads, and a submultiple of the one 2544 * we want. In this case we'll waste some vcpu ids, but 2545 * behaviour will be correct */ 2546 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2547 warn_report_err(local_err); 2548 local_err = NULL; 2549 goto out; 2550 } else { 2551 if (!vsmt_user) { 2552 error_append_hint(&local_err, 2553 "On PPC, a VM with %d threads/core" 2554 " on a host with %d threads/core" 2555 " requires the use of VSMT mode %d.\n", 2556 smp_threads, kvm_smt, spapr->vsmt); 2557 } 2558 kvmppc_error_append_smt_possible_hint(&local_err); 2559 goto out; 2560 } 2561 } 2562 } 2563 /* else TCG: nothing to do currently */ 2564 out: 2565 error_propagate(errp, local_err); 2566 } 2567 2568 static void spapr_init_cpus(SpaprMachineState *spapr) 2569 { 2570 MachineState *machine = MACHINE(spapr); 2571 MachineClass *mc = MACHINE_GET_CLASS(machine); 2572 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2573 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2574 const CPUArchIdList *possible_cpus; 2575 unsigned int smp_cpus = machine->smp.cpus; 2576 unsigned int smp_threads = machine->smp.threads; 2577 unsigned int max_cpus = machine->smp.max_cpus; 2578 int boot_cores_nr = smp_cpus / smp_threads; 2579 int i; 2580 2581 possible_cpus = mc->possible_cpu_arch_ids(machine); 2582 if (mc->has_hotpluggable_cpus) { 2583 if (smp_cpus % smp_threads) { 2584 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2585 smp_cpus, smp_threads); 2586 exit(1); 2587 } 2588 if (max_cpus % smp_threads) { 2589 error_report("max_cpus (%u) must be multiple of threads (%u)", 2590 max_cpus, smp_threads); 2591 exit(1); 2592 } 2593 } else { 2594 if (max_cpus != smp_cpus) { 2595 error_report("This machine version does not support CPU hotplug"); 2596 exit(1); 2597 } 2598 boot_cores_nr = possible_cpus->len; 2599 } 2600 2601 if (smc->pre_2_10_has_unused_icps) { 2602 int i; 2603 2604 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2605 /* Dummy entries get deregistered when real ICPState objects 2606 * are registered during CPU core hotplug. 2607 */ 2608 pre_2_10_vmstate_register_dummy_icp(i); 2609 } 2610 } 2611 2612 for (i = 0; i < possible_cpus->len; i++) { 2613 int core_id = i * smp_threads; 2614 2615 if (mc->has_hotpluggable_cpus) { 2616 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2617 spapr_vcpu_id(spapr, core_id)); 2618 } 2619 2620 if (i < boot_cores_nr) { 2621 Object *core = object_new(type); 2622 int nr_threads = smp_threads; 2623 2624 /* Handle the partially filled core for older machine types */ 2625 if ((i + 1) * smp_threads >= smp_cpus) { 2626 nr_threads = smp_cpus - i * smp_threads; 2627 } 2628 2629 object_property_set_int(core, nr_threads, "nr-threads", 2630 &error_fatal); 2631 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2632 &error_fatal); 2633 object_property_set_bool(core, true, "realized", &error_fatal); 2634 2635 object_unref(core); 2636 } 2637 } 2638 } 2639 2640 static PCIHostState *spapr_create_default_phb(void) 2641 { 2642 DeviceState *dev; 2643 2644 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 2645 qdev_prop_set_uint32(dev, "index", 0); 2646 qdev_init_nofail(dev); 2647 2648 return PCI_HOST_BRIDGE(dev); 2649 } 2650 2651 /* pSeries LPAR / sPAPR hardware init */ 2652 static void spapr_machine_init(MachineState *machine) 2653 { 2654 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2655 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2656 MachineClass *mc = MACHINE_GET_CLASS(machine); 2657 const char *kernel_filename = machine->kernel_filename; 2658 const char *initrd_filename = machine->initrd_filename; 2659 PCIHostState *phb; 2660 int i; 2661 MemoryRegion *sysmem = get_system_memory(); 2662 hwaddr node0_size = spapr_node0_size(machine); 2663 long load_limit, fw_size; 2664 char *filename; 2665 Error *resize_hpt_err = NULL; 2666 2667 msi_nonbroken = true; 2668 2669 QLIST_INIT(&spapr->phbs); 2670 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2671 2672 /* Determine capabilities to run with */ 2673 spapr_caps_init(spapr); 2674 2675 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2676 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2677 /* 2678 * If the user explicitly requested a mode we should either 2679 * supply it, or fail completely (which we do below). But if 2680 * it's not set explicitly, we reset our mode to something 2681 * that works 2682 */ 2683 if (resize_hpt_err) { 2684 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2685 error_free(resize_hpt_err); 2686 resize_hpt_err = NULL; 2687 } else { 2688 spapr->resize_hpt = smc->resize_hpt_default; 2689 } 2690 } 2691 2692 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2693 2694 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2695 /* 2696 * User requested HPT resize, but this host can't supply it. Bail out 2697 */ 2698 error_report_err(resize_hpt_err); 2699 exit(1); 2700 } 2701 2702 spapr->rma_size = node0_size; 2703 2704 /* 2705 * Clamp the RMA size based on machine type. This is for 2706 * migration compatibility with older qemu versions, which limited 2707 * the RMA size for complicated and mostly bad reasons. 2708 */ 2709 if (smc->rma_limit) { 2710 spapr->rma_size = MIN(spapr->rma_size, smc->rma_limit); 2711 } 2712 2713 if (spapr->rma_size > node0_size) { 2714 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2715 spapr->rma_size); 2716 exit(1); 2717 } 2718 2719 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2720 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2721 2722 /* 2723 * VSMT must be set in order to be able to compute VCPU ids, ie to 2724 * call spapr_max_server_number() or spapr_vcpu_id(). 2725 */ 2726 spapr_set_vsmt_mode(spapr, &error_fatal); 2727 2728 /* Set up Interrupt Controller before we create the VCPUs */ 2729 spapr_irq_init(spapr, &error_fatal); 2730 2731 /* Set up containers for ibm,client-architecture-support negotiated options 2732 */ 2733 spapr->ov5 = spapr_ovec_new(); 2734 spapr->ov5_cas = spapr_ovec_new(); 2735 2736 if (smc->dr_lmb_enabled) { 2737 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2738 spapr_validate_node_memory(machine, &error_fatal); 2739 } 2740 2741 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2742 2743 /* advertise support for dedicated HP event source to guests */ 2744 if (spapr->use_hotplug_event_source) { 2745 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2746 } 2747 2748 /* advertise support for HPT resizing */ 2749 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2750 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2751 } 2752 2753 /* advertise support for ibm,dyamic-memory-v2 */ 2754 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2755 2756 /* advertise XIVE on POWER9 machines */ 2757 if (spapr->irq->xive) { 2758 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2759 } 2760 2761 /* init CPUs */ 2762 spapr_init_cpus(spapr); 2763 2764 /* 2765 * check we don't have a memory-less/cpu-less NUMA node 2766 * Firmware relies on the existing memory/cpu topology to provide the 2767 * NUMA topology to the kernel. 2768 * And the linux kernel needs to know the NUMA topology at start 2769 * to be able to hotplug CPUs later. 2770 */ 2771 if (machine->numa_state->num_nodes) { 2772 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2773 /* check for memory-less node */ 2774 if (machine->numa_state->nodes[i].node_mem == 0) { 2775 CPUState *cs; 2776 int found = 0; 2777 /* check for cpu-less node */ 2778 CPU_FOREACH(cs) { 2779 PowerPCCPU *cpu = POWERPC_CPU(cs); 2780 if (cpu->node_id == i) { 2781 found = 1; 2782 break; 2783 } 2784 } 2785 /* memory-less and cpu-less node */ 2786 if (!found) { 2787 error_report( 2788 "Memory-less/cpu-less nodes are not supported (node %d)", 2789 i); 2790 exit(1); 2791 } 2792 } 2793 } 2794 2795 } 2796 2797 /* 2798 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2799 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2800 * called from vPHB reset handler so we initialize the counter here. 2801 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2802 * must be equally distant from any other node. 2803 * The final value of spapr->gpu_numa_id is going to be written to 2804 * max-associativity-domains in spapr_build_fdt(). 2805 */ 2806 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2807 2808 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2809 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2810 spapr->max_compat_pvr)) { 2811 /* KVM and TCG always allow GTSE with radix... */ 2812 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2813 } 2814 /* ... but not with hash (currently). */ 2815 2816 if (kvm_enabled()) { 2817 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2818 kvmppc_enable_logical_ci_hcalls(); 2819 kvmppc_enable_set_mode_hcall(); 2820 2821 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2822 kvmppc_enable_clear_ref_mod_hcalls(); 2823 2824 /* Enable H_PAGE_INIT */ 2825 kvmppc_enable_h_page_init(); 2826 } 2827 2828 /* map RAM */ 2829 memory_region_add_subregion(sysmem, 0, machine->ram); 2830 2831 /* always allocate the device memory information */ 2832 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2833 2834 /* initialize hotplug memory address space */ 2835 if (machine->ram_size < machine->maxram_size) { 2836 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2837 /* 2838 * Limit the number of hotpluggable memory slots to half the number 2839 * slots that KVM supports, leaving the other half for PCI and other 2840 * devices. However ensure that number of slots doesn't drop below 32. 2841 */ 2842 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2843 SPAPR_MAX_RAM_SLOTS; 2844 2845 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2846 max_memslots = SPAPR_MAX_RAM_SLOTS; 2847 } 2848 if (machine->ram_slots > max_memslots) { 2849 error_report("Specified number of memory slots %" 2850 PRIu64" exceeds max supported %d", 2851 machine->ram_slots, max_memslots); 2852 exit(1); 2853 } 2854 2855 machine->device_memory->base = ROUND_UP(machine->ram_size, 2856 SPAPR_DEVICE_MEM_ALIGN); 2857 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2858 "device-memory", device_mem_size); 2859 memory_region_add_subregion(sysmem, machine->device_memory->base, 2860 &machine->device_memory->mr); 2861 } 2862 2863 if (smc->dr_lmb_enabled) { 2864 spapr_create_lmb_dr_connectors(spapr); 2865 } 2866 2867 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI_MCE) == SPAPR_CAP_ON) { 2868 /* Create the error string for live migration blocker */ 2869 error_setg(&spapr->fwnmi_migration_blocker, 2870 "A machine check is being handled during migration. The handler" 2871 "may run and log hardware error on the destination"); 2872 } 2873 2874 if (mc->nvdimm_supported) { 2875 spapr_create_nvdimm_dr_connectors(spapr); 2876 } 2877 2878 /* Set up RTAS event infrastructure */ 2879 spapr_events_init(spapr); 2880 2881 /* Set up the RTC RTAS interfaces */ 2882 spapr_rtc_create(spapr); 2883 2884 /* Set up VIO bus */ 2885 spapr->vio_bus = spapr_vio_bus_init(); 2886 2887 for (i = 0; i < serial_max_hds(); i++) { 2888 if (serial_hd(i)) { 2889 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2890 } 2891 } 2892 2893 /* We always have at least the nvram device on VIO */ 2894 spapr_create_nvram(spapr); 2895 2896 /* 2897 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2898 * connectors (described in root DT node's "ibm,drc-types" property) 2899 * are pre-initialized here. additional child connectors (such as 2900 * connectors for a PHBs PCI slots) are added as needed during their 2901 * parent's realization. 2902 */ 2903 if (smc->dr_phb_enabled) { 2904 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2905 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2906 } 2907 } 2908 2909 /* Set up PCI */ 2910 spapr_pci_rtas_init(); 2911 2912 phb = spapr_create_default_phb(); 2913 2914 for (i = 0; i < nb_nics; i++) { 2915 NICInfo *nd = &nd_table[i]; 2916 2917 if (!nd->model) { 2918 nd->model = g_strdup("spapr-vlan"); 2919 } 2920 2921 if (g_str_equal(nd->model, "spapr-vlan") || 2922 g_str_equal(nd->model, "ibmveth")) { 2923 spapr_vlan_create(spapr->vio_bus, nd); 2924 } else { 2925 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2926 } 2927 } 2928 2929 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2930 spapr_vscsi_create(spapr->vio_bus); 2931 } 2932 2933 /* Graphics */ 2934 if (spapr_vga_init(phb->bus, &error_fatal)) { 2935 spapr->has_graphics = true; 2936 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2937 } 2938 2939 if (machine->usb) { 2940 if (smc->use_ohci_by_default) { 2941 pci_create_simple(phb->bus, -1, "pci-ohci"); 2942 } else { 2943 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2944 } 2945 2946 if (spapr->has_graphics) { 2947 USBBus *usb_bus = usb_bus_find(-1); 2948 2949 usb_create_simple(usb_bus, "usb-kbd"); 2950 usb_create_simple(usb_bus, "usb-mouse"); 2951 } 2952 } 2953 2954 if (spapr->rma_size < MIN_RMA_SLOF) { 2955 error_report( 2956 "pSeries SLOF firmware requires >= %ldMiB guest RMA (Real Mode Area memory)", 2957 MIN_RMA_SLOF / MiB); 2958 exit(1); 2959 } 2960 2961 if (kernel_filename) { 2962 uint64_t lowaddr = 0; 2963 2964 spapr->kernel_size = load_elf(kernel_filename, NULL, 2965 translate_kernel_address, spapr, 2966 NULL, &lowaddr, NULL, NULL, 1, 2967 PPC_ELF_MACHINE, 0, 0); 2968 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2969 spapr->kernel_size = load_elf(kernel_filename, NULL, 2970 translate_kernel_address, spapr, NULL, 2971 &lowaddr, NULL, NULL, 0, 2972 PPC_ELF_MACHINE, 2973 0, 0); 2974 spapr->kernel_le = spapr->kernel_size > 0; 2975 } 2976 if (spapr->kernel_size < 0) { 2977 error_report("error loading %s: %s", kernel_filename, 2978 load_elf_strerror(spapr->kernel_size)); 2979 exit(1); 2980 } 2981 2982 /* load initrd */ 2983 if (initrd_filename) { 2984 /* Try to locate the initrd in the gap between the kernel 2985 * and the firmware. Add a bit of space just in case 2986 */ 2987 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2988 + 0x1ffff) & ~0xffff; 2989 spapr->initrd_size = load_image_targphys(initrd_filename, 2990 spapr->initrd_base, 2991 load_limit 2992 - spapr->initrd_base); 2993 if (spapr->initrd_size < 0) { 2994 error_report("could not load initial ram disk '%s'", 2995 initrd_filename); 2996 exit(1); 2997 } 2998 } 2999 } 3000 3001 if (bios_name == NULL) { 3002 bios_name = FW_FILE_NAME; 3003 } 3004 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 3005 if (!filename) { 3006 error_report("Could not find LPAR firmware '%s'", bios_name); 3007 exit(1); 3008 } 3009 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 3010 if (fw_size <= 0) { 3011 error_report("Could not load LPAR firmware '%s'", filename); 3012 exit(1); 3013 } 3014 g_free(filename); 3015 3016 /* FIXME: Should register things through the MachineState's qdev 3017 * interface, this is a legacy from the sPAPREnvironment structure 3018 * which predated MachineState but had a similar function */ 3019 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3020 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3021 &savevm_htab_handlers, spapr); 3022 3023 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine), 3024 &error_fatal); 3025 3026 qemu_register_boot_set(spapr_boot_set, spapr); 3027 3028 /* 3029 * Nothing needs to be done to resume a suspended guest because 3030 * suspending does not change the machine state, so no need for 3031 * a ->wakeup method. 3032 */ 3033 qemu_register_wakeup_support(); 3034 3035 if (kvm_enabled()) { 3036 /* to stop and start vmclock */ 3037 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3038 &spapr->tb); 3039 3040 kvmppc_spapr_enable_inkernel_multitce(); 3041 } 3042 3043 qemu_cond_init(&spapr->mc_delivery_cond); 3044 } 3045 3046 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3047 { 3048 if (!vm_type) { 3049 return 0; 3050 } 3051 3052 if (!strcmp(vm_type, "HV")) { 3053 return 1; 3054 } 3055 3056 if (!strcmp(vm_type, "PR")) { 3057 return 2; 3058 } 3059 3060 error_report("Unknown kvm-type specified '%s'", vm_type); 3061 exit(1); 3062 } 3063 3064 /* 3065 * Implementation of an interface to adjust firmware path 3066 * for the bootindex property handling. 3067 */ 3068 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3069 DeviceState *dev) 3070 { 3071 #define CAST(type, obj, name) \ 3072 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3073 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3074 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3075 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3076 3077 if (d) { 3078 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3079 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3080 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3081 3082 if (spapr) { 3083 /* 3084 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3085 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3086 * 0x8000 | (target << 8) | (bus << 5) | lun 3087 * (see the "Logical unit addressing format" table in SAM5) 3088 */ 3089 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3090 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3091 (uint64_t)id << 48); 3092 } else if (virtio) { 3093 /* 3094 * We use SRP luns of the form 01000000 | (target << 8) | lun 3095 * in the top 32 bits of the 64-bit LUN 3096 * Note: the quote above is from SLOF and it is wrong, 3097 * the actual binding is: 3098 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3099 */ 3100 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3101 if (d->lun >= 256) { 3102 /* Use the LUN "flat space addressing method" */ 3103 id |= 0x4000; 3104 } 3105 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3106 (uint64_t)id << 32); 3107 } else if (usb) { 3108 /* 3109 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3110 * in the top 32 bits of the 64-bit LUN 3111 */ 3112 unsigned usb_port = atoi(usb->port->path); 3113 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3114 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3115 (uint64_t)id << 32); 3116 } 3117 } 3118 3119 /* 3120 * SLOF probes the USB devices, and if it recognizes that the device is a 3121 * storage device, it changes its name to "storage" instead of "usb-host", 3122 * and additionally adds a child node for the SCSI LUN, so the correct 3123 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3124 */ 3125 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3126 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3127 if (usb_host_dev_is_scsi_storage(usbdev)) { 3128 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3129 } 3130 } 3131 3132 if (phb) { 3133 /* Replace "pci" with "pci@800000020000000" */ 3134 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3135 } 3136 3137 if (vsc) { 3138 /* Same logic as virtio above */ 3139 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3140 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3141 } 3142 3143 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3144 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3145 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3146 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3147 } 3148 3149 return NULL; 3150 } 3151 3152 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3153 { 3154 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3155 3156 return g_strdup(spapr->kvm_type); 3157 } 3158 3159 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3160 { 3161 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3162 3163 g_free(spapr->kvm_type); 3164 spapr->kvm_type = g_strdup(value); 3165 } 3166 3167 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3168 { 3169 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3170 3171 return spapr->use_hotplug_event_source; 3172 } 3173 3174 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3175 Error **errp) 3176 { 3177 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3178 3179 spapr->use_hotplug_event_source = value; 3180 } 3181 3182 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3183 { 3184 return true; 3185 } 3186 3187 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3188 { 3189 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3190 3191 switch (spapr->resize_hpt) { 3192 case SPAPR_RESIZE_HPT_DEFAULT: 3193 return g_strdup("default"); 3194 case SPAPR_RESIZE_HPT_DISABLED: 3195 return g_strdup("disabled"); 3196 case SPAPR_RESIZE_HPT_ENABLED: 3197 return g_strdup("enabled"); 3198 case SPAPR_RESIZE_HPT_REQUIRED: 3199 return g_strdup("required"); 3200 } 3201 g_assert_not_reached(); 3202 } 3203 3204 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3205 { 3206 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3207 3208 if (strcmp(value, "default") == 0) { 3209 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3210 } else if (strcmp(value, "disabled") == 0) { 3211 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3212 } else if (strcmp(value, "enabled") == 0) { 3213 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3214 } else if (strcmp(value, "required") == 0) { 3215 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3216 } else { 3217 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3218 } 3219 } 3220 3221 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3222 void *opaque, Error **errp) 3223 { 3224 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3225 } 3226 3227 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3228 void *opaque, Error **errp) 3229 { 3230 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3231 } 3232 3233 static void spapr_get_kernel_addr(Object *obj, Visitor *v, const char *name, 3234 void *opaque, Error **errp) 3235 { 3236 visit_type_uint64(v, name, (uint64_t *)opaque, errp); 3237 } 3238 3239 static void spapr_set_kernel_addr(Object *obj, Visitor *v, const char *name, 3240 void *opaque, Error **errp) 3241 { 3242 visit_type_uint64(v, name, (uint64_t *)opaque, errp); 3243 } 3244 3245 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3246 { 3247 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3248 3249 if (spapr->irq == &spapr_irq_xics_legacy) { 3250 return g_strdup("legacy"); 3251 } else if (spapr->irq == &spapr_irq_xics) { 3252 return g_strdup("xics"); 3253 } else if (spapr->irq == &spapr_irq_xive) { 3254 return g_strdup("xive"); 3255 } else if (spapr->irq == &spapr_irq_dual) { 3256 return g_strdup("dual"); 3257 } 3258 g_assert_not_reached(); 3259 } 3260 3261 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3262 { 3263 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3264 3265 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3266 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3267 return; 3268 } 3269 3270 /* The legacy IRQ backend can not be set */ 3271 if (strcmp(value, "xics") == 0) { 3272 spapr->irq = &spapr_irq_xics; 3273 } else if (strcmp(value, "xive") == 0) { 3274 spapr->irq = &spapr_irq_xive; 3275 } else if (strcmp(value, "dual") == 0) { 3276 spapr->irq = &spapr_irq_dual; 3277 } else { 3278 error_setg(errp, "Bad value for \"ic-mode\" property"); 3279 } 3280 } 3281 3282 static char *spapr_get_host_model(Object *obj, Error **errp) 3283 { 3284 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3285 3286 return g_strdup(spapr->host_model); 3287 } 3288 3289 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3290 { 3291 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3292 3293 g_free(spapr->host_model); 3294 spapr->host_model = g_strdup(value); 3295 } 3296 3297 static char *spapr_get_host_serial(Object *obj, Error **errp) 3298 { 3299 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3300 3301 return g_strdup(spapr->host_serial); 3302 } 3303 3304 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3305 { 3306 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3307 3308 g_free(spapr->host_serial); 3309 spapr->host_serial = g_strdup(value); 3310 } 3311 3312 static void spapr_instance_init(Object *obj) 3313 { 3314 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3315 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3316 3317 spapr->htab_fd = -1; 3318 spapr->use_hotplug_event_source = true; 3319 object_property_add_str(obj, "kvm-type", 3320 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3321 object_property_set_description(obj, "kvm-type", 3322 "Specifies the KVM virtualization mode (HV, PR)", 3323 NULL); 3324 object_property_add_bool(obj, "modern-hotplug-events", 3325 spapr_get_modern_hotplug_events, 3326 spapr_set_modern_hotplug_events, 3327 NULL); 3328 object_property_set_description(obj, "modern-hotplug-events", 3329 "Use dedicated hotplug event mechanism in" 3330 " place of standard EPOW events when possible" 3331 " (required for memory hot-unplug support)", 3332 NULL); 3333 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3334 "Maximum permitted CPU compatibility mode", 3335 &error_fatal); 3336 3337 object_property_add_str(obj, "resize-hpt", 3338 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3339 object_property_set_description(obj, "resize-hpt", 3340 "Resizing of the Hash Page Table (enabled, disabled, required)", 3341 NULL); 3342 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3343 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3344 object_property_set_description(obj, "vsmt", 3345 "Virtual SMT: KVM behaves as if this were" 3346 " the host's SMT mode", &error_abort); 3347 object_property_add_bool(obj, "vfio-no-msix-emulation", 3348 spapr_get_msix_emulation, NULL, NULL); 3349 3350 object_property_add(obj, "kernel-addr", "uint64", spapr_get_kernel_addr, 3351 spapr_set_kernel_addr, NULL, &spapr->kernel_addr, 3352 &error_abort); 3353 object_property_set_description(obj, "kernel-addr", 3354 stringify(KERNEL_LOAD_ADDR) 3355 " for -kernel is the default", 3356 NULL); 3357 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3358 /* The machine class defines the default interrupt controller mode */ 3359 spapr->irq = smc->irq; 3360 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3361 spapr_set_ic_mode, NULL); 3362 object_property_set_description(obj, "ic-mode", 3363 "Specifies the interrupt controller mode (xics, xive, dual)", 3364 NULL); 3365 3366 object_property_add_str(obj, "host-model", 3367 spapr_get_host_model, spapr_set_host_model, 3368 &error_abort); 3369 object_property_set_description(obj, "host-model", 3370 "Host model to advertise in guest device tree", &error_abort); 3371 object_property_add_str(obj, "host-serial", 3372 spapr_get_host_serial, spapr_set_host_serial, 3373 &error_abort); 3374 object_property_set_description(obj, "host-serial", 3375 "Host serial number to advertise in guest device tree", &error_abort); 3376 } 3377 3378 static void spapr_machine_finalizefn(Object *obj) 3379 { 3380 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3381 3382 g_free(spapr->kvm_type); 3383 } 3384 3385 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3386 { 3387 cpu_synchronize_state(cs); 3388 ppc_cpu_do_system_reset(cs); 3389 } 3390 3391 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3392 { 3393 CPUState *cs; 3394 3395 CPU_FOREACH(cs) { 3396 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3397 } 3398 } 3399 3400 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3401 void *fdt, int *fdt_start_offset, Error **errp) 3402 { 3403 uint64_t addr; 3404 uint32_t node; 3405 3406 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3407 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3408 &error_abort); 3409 *fdt_start_offset = spapr_populate_memory_node(fdt, node, addr, 3410 SPAPR_MEMORY_BLOCK_SIZE); 3411 return 0; 3412 } 3413 3414 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3415 bool dedicated_hp_event_source, Error **errp) 3416 { 3417 SpaprDrc *drc; 3418 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3419 int i; 3420 uint64_t addr = addr_start; 3421 bool hotplugged = spapr_drc_hotplugged(dev); 3422 Error *local_err = NULL; 3423 3424 for (i = 0; i < nr_lmbs; i++) { 3425 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3426 addr / SPAPR_MEMORY_BLOCK_SIZE); 3427 g_assert(drc); 3428 3429 spapr_drc_attach(drc, dev, &local_err); 3430 if (local_err) { 3431 while (addr > addr_start) { 3432 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3433 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3434 addr / SPAPR_MEMORY_BLOCK_SIZE); 3435 spapr_drc_detach(drc); 3436 } 3437 error_propagate(errp, local_err); 3438 return; 3439 } 3440 if (!hotplugged) { 3441 spapr_drc_reset(drc); 3442 } 3443 addr += SPAPR_MEMORY_BLOCK_SIZE; 3444 } 3445 /* send hotplug notification to the 3446 * guest only in case of hotplugged memory 3447 */ 3448 if (hotplugged) { 3449 if (dedicated_hp_event_source) { 3450 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3451 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3452 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3453 nr_lmbs, 3454 spapr_drc_index(drc)); 3455 } else { 3456 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3457 nr_lmbs); 3458 } 3459 } 3460 } 3461 3462 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3463 Error **errp) 3464 { 3465 Error *local_err = NULL; 3466 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3467 PCDIMMDevice *dimm = PC_DIMM(dev); 3468 uint64_t size, addr, slot; 3469 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3470 3471 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3472 3473 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3474 if (local_err) { 3475 goto out; 3476 } 3477 3478 if (!is_nvdimm) { 3479 addr = object_property_get_uint(OBJECT(dimm), 3480 PC_DIMM_ADDR_PROP, &local_err); 3481 if (local_err) { 3482 goto out_unplug; 3483 } 3484 spapr_add_lmbs(dev, addr, size, 3485 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3486 &local_err); 3487 } else { 3488 slot = object_property_get_uint(OBJECT(dimm), 3489 PC_DIMM_SLOT_PROP, &local_err); 3490 if (local_err) { 3491 goto out_unplug; 3492 } 3493 spapr_add_nvdimm(dev, slot, &local_err); 3494 } 3495 3496 if (local_err) { 3497 goto out_unplug; 3498 } 3499 3500 return; 3501 3502 out_unplug: 3503 pc_dimm_unplug(dimm, MACHINE(ms)); 3504 out: 3505 error_propagate(errp, local_err); 3506 } 3507 3508 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3509 Error **errp) 3510 { 3511 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3512 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3513 const MachineClass *mc = MACHINE_CLASS(smc); 3514 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3515 PCDIMMDevice *dimm = PC_DIMM(dev); 3516 Error *local_err = NULL; 3517 uint64_t size; 3518 Object *memdev; 3519 hwaddr pagesize; 3520 3521 if (!smc->dr_lmb_enabled) { 3522 error_setg(errp, "Memory hotplug not supported for this machine"); 3523 return; 3524 } 3525 3526 if (is_nvdimm && !mc->nvdimm_supported) { 3527 error_setg(errp, "NVDIMM hotplug not supported for this machine"); 3528 return; 3529 } 3530 3531 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3532 if (local_err) { 3533 error_propagate(errp, local_err); 3534 return; 3535 } 3536 3537 if (!is_nvdimm && size % SPAPR_MEMORY_BLOCK_SIZE) { 3538 error_setg(errp, "Hotplugged memory size must be a multiple of " 3539 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3540 return; 3541 } else if (is_nvdimm) { 3542 spapr_nvdimm_validate_opts(NVDIMM(dev), size, &local_err); 3543 if (local_err) { 3544 error_propagate(errp, local_err); 3545 return; 3546 } 3547 } 3548 3549 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3550 &error_abort); 3551 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3552 spapr_check_pagesize(spapr, pagesize, &local_err); 3553 if (local_err) { 3554 error_propagate(errp, local_err); 3555 return; 3556 } 3557 3558 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3559 } 3560 3561 struct SpaprDimmState { 3562 PCDIMMDevice *dimm; 3563 uint32_t nr_lmbs; 3564 QTAILQ_ENTRY(SpaprDimmState) next; 3565 }; 3566 3567 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3568 PCDIMMDevice *dimm) 3569 { 3570 SpaprDimmState *dimm_state = NULL; 3571 3572 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3573 if (dimm_state->dimm == dimm) { 3574 break; 3575 } 3576 } 3577 return dimm_state; 3578 } 3579 3580 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3581 uint32_t nr_lmbs, 3582 PCDIMMDevice *dimm) 3583 { 3584 SpaprDimmState *ds = NULL; 3585 3586 /* 3587 * If this request is for a DIMM whose removal had failed earlier 3588 * (due to guest's refusal to remove the LMBs), we would have this 3589 * dimm already in the pending_dimm_unplugs list. In that 3590 * case don't add again. 3591 */ 3592 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3593 if (!ds) { 3594 ds = g_malloc0(sizeof(SpaprDimmState)); 3595 ds->nr_lmbs = nr_lmbs; 3596 ds->dimm = dimm; 3597 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3598 } 3599 return ds; 3600 } 3601 3602 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3603 SpaprDimmState *dimm_state) 3604 { 3605 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3606 g_free(dimm_state); 3607 } 3608 3609 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3610 PCDIMMDevice *dimm) 3611 { 3612 SpaprDrc *drc; 3613 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3614 &error_abort); 3615 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3616 uint32_t avail_lmbs = 0; 3617 uint64_t addr_start, addr; 3618 int i; 3619 3620 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3621 &error_abort); 3622 3623 addr = addr_start; 3624 for (i = 0; i < nr_lmbs; i++) { 3625 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3626 addr / SPAPR_MEMORY_BLOCK_SIZE); 3627 g_assert(drc); 3628 if (drc->dev) { 3629 avail_lmbs++; 3630 } 3631 addr += SPAPR_MEMORY_BLOCK_SIZE; 3632 } 3633 3634 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3635 } 3636 3637 /* Callback to be called during DRC release. */ 3638 void spapr_lmb_release(DeviceState *dev) 3639 { 3640 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3641 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3642 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3643 3644 /* This information will get lost if a migration occurs 3645 * during the unplug process. In this case recover it. */ 3646 if (ds == NULL) { 3647 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3648 g_assert(ds); 3649 /* The DRC being examined by the caller at least must be counted */ 3650 g_assert(ds->nr_lmbs); 3651 } 3652 3653 if (--ds->nr_lmbs) { 3654 return; 3655 } 3656 3657 /* 3658 * Now that all the LMBs have been removed by the guest, call the 3659 * unplug handler chain. This can never fail. 3660 */ 3661 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3662 object_unparent(OBJECT(dev)); 3663 } 3664 3665 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3666 { 3667 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3668 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3669 3670 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3671 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3672 spapr_pending_dimm_unplugs_remove(spapr, ds); 3673 } 3674 3675 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3676 DeviceState *dev, Error **errp) 3677 { 3678 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3679 Error *local_err = NULL; 3680 PCDIMMDevice *dimm = PC_DIMM(dev); 3681 uint32_t nr_lmbs; 3682 uint64_t size, addr_start, addr; 3683 int i; 3684 SpaprDrc *drc; 3685 3686 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3687 error_setg(&local_err, 3688 "nvdimm device hot unplug is not supported yet."); 3689 goto out; 3690 } 3691 3692 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3693 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3694 3695 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3696 &local_err); 3697 if (local_err) { 3698 goto out; 3699 } 3700 3701 /* 3702 * An existing pending dimm state for this DIMM means that there is an 3703 * unplug operation in progress, waiting for the spapr_lmb_release 3704 * callback to complete the job (BQL can't cover that far). In this case, 3705 * bail out to avoid detaching DRCs that were already released. 3706 */ 3707 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3708 error_setg(&local_err, 3709 "Memory unplug already in progress for device %s", 3710 dev->id); 3711 goto out; 3712 } 3713 3714 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3715 3716 addr = addr_start; 3717 for (i = 0; i < nr_lmbs; i++) { 3718 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3719 addr / SPAPR_MEMORY_BLOCK_SIZE); 3720 g_assert(drc); 3721 3722 spapr_drc_detach(drc); 3723 addr += SPAPR_MEMORY_BLOCK_SIZE; 3724 } 3725 3726 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3727 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3728 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3729 nr_lmbs, spapr_drc_index(drc)); 3730 out: 3731 error_propagate(errp, local_err); 3732 } 3733 3734 /* Callback to be called during DRC release. */ 3735 void spapr_core_release(DeviceState *dev) 3736 { 3737 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3738 3739 /* Call the unplug handler chain. This can never fail. */ 3740 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3741 object_unparent(OBJECT(dev)); 3742 } 3743 3744 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3745 { 3746 MachineState *ms = MACHINE(hotplug_dev); 3747 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3748 CPUCore *cc = CPU_CORE(dev); 3749 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3750 3751 if (smc->pre_2_10_has_unused_icps) { 3752 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3753 int i; 3754 3755 for (i = 0; i < cc->nr_threads; i++) { 3756 CPUState *cs = CPU(sc->threads[i]); 3757 3758 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3759 } 3760 } 3761 3762 assert(core_slot); 3763 core_slot->cpu = NULL; 3764 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3765 } 3766 3767 static 3768 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3769 Error **errp) 3770 { 3771 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3772 int index; 3773 SpaprDrc *drc; 3774 CPUCore *cc = CPU_CORE(dev); 3775 3776 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3777 error_setg(errp, "Unable to find CPU core with core-id: %d", 3778 cc->core_id); 3779 return; 3780 } 3781 if (index == 0) { 3782 error_setg(errp, "Boot CPU core may not be unplugged"); 3783 return; 3784 } 3785 3786 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3787 spapr_vcpu_id(spapr, cc->core_id)); 3788 g_assert(drc); 3789 3790 if (!spapr_drc_unplug_requested(drc)) { 3791 spapr_drc_detach(drc); 3792 spapr_hotplug_req_remove_by_index(drc); 3793 } 3794 } 3795 3796 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3797 void *fdt, int *fdt_start_offset, Error **errp) 3798 { 3799 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3800 CPUState *cs = CPU(core->threads[0]); 3801 PowerPCCPU *cpu = POWERPC_CPU(cs); 3802 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3803 int id = spapr_get_vcpu_id(cpu); 3804 char *nodename; 3805 int offset; 3806 3807 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3808 offset = fdt_add_subnode(fdt, 0, nodename); 3809 g_free(nodename); 3810 3811 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3812 3813 *fdt_start_offset = offset; 3814 return 0; 3815 } 3816 3817 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3818 Error **errp) 3819 { 3820 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3821 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3822 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3823 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3824 CPUCore *cc = CPU_CORE(dev); 3825 CPUState *cs; 3826 SpaprDrc *drc; 3827 Error *local_err = NULL; 3828 CPUArchId *core_slot; 3829 int index; 3830 bool hotplugged = spapr_drc_hotplugged(dev); 3831 int i; 3832 3833 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3834 if (!core_slot) { 3835 error_setg(errp, "Unable to find CPU core with core-id: %d", 3836 cc->core_id); 3837 return; 3838 } 3839 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3840 spapr_vcpu_id(spapr, cc->core_id)); 3841 3842 g_assert(drc || !mc->has_hotpluggable_cpus); 3843 3844 if (drc) { 3845 spapr_drc_attach(drc, dev, &local_err); 3846 if (local_err) { 3847 error_propagate(errp, local_err); 3848 return; 3849 } 3850 3851 if (hotplugged) { 3852 /* 3853 * Send hotplug notification interrupt to the guest only 3854 * in case of hotplugged CPUs. 3855 */ 3856 spapr_hotplug_req_add_by_index(drc); 3857 } else { 3858 spapr_drc_reset(drc); 3859 } 3860 } 3861 3862 core_slot->cpu = OBJECT(dev); 3863 3864 if (smc->pre_2_10_has_unused_icps) { 3865 for (i = 0; i < cc->nr_threads; i++) { 3866 cs = CPU(core->threads[i]); 3867 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3868 } 3869 } 3870 3871 /* 3872 * Set compatibility mode to match the boot CPU, which was either set 3873 * by the machine reset code or by CAS. 3874 */ 3875 if (hotplugged) { 3876 for (i = 0; i < cc->nr_threads; i++) { 3877 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3878 &local_err); 3879 if (local_err) { 3880 error_propagate(errp, local_err); 3881 return; 3882 } 3883 } 3884 } 3885 } 3886 3887 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3888 Error **errp) 3889 { 3890 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3891 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3892 Error *local_err = NULL; 3893 CPUCore *cc = CPU_CORE(dev); 3894 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3895 const char *type = object_get_typename(OBJECT(dev)); 3896 CPUArchId *core_slot; 3897 int index; 3898 unsigned int smp_threads = machine->smp.threads; 3899 3900 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3901 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3902 goto out; 3903 } 3904 3905 if (strcmp(base_core_type, type)) { 3906 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3907 goto out; 3908 } 3909 3910 if (cc->core_id % smp_threads) { 3911 error_setg(&local_err, "invalid core id %d", cc->core_id); 3912 goto out; 3913 } 3914 3915 /* 3916 * In general we should have homogeneous threads-per-core, but old 3917 * (pre hotplug support) machine types allow the last core to have 3918 * reduced threads as a compatibility hack for when we allowed 3919 * total vcpus not a multiple of threads-per-core. 3920 */ 3921 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3922 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3923 cc->nr_threads, smp_threads); 3924 goto out; 3925 } 3926 3927 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3928 if (!core_slot) { 3929 error_setg(&local_err, "core id %d out of range", cc->core_id); 3930 goto out; 3931 } 3932 3933 if (core_slot->cpu) { 3934 error_setg(&local_err, "core %d already populated", cc->core_id); 3935 goto out; 3936 } 3937 3938 numa_cpu_pre_plug(core_slot, dev, &local_err); 3939 3940 out: 3941 error_propagate(errp, local_err); 3942 } 3943 3944 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3945 void *fdt, int *fdt_start_offset, Error **errp) 3946 { 3947 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3948 int intc_phandle; 3949 3950 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3951 if (intc_phandle <= 0) { 3952 return -1; 3953 } 3954 3955 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3956 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3957 return -1; 3958 } 3959 3960 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3961 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3962 3963 return 0; 3964 } 3965 3966 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3967 Error **errp) 3968 { 3969 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3970 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3971 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3972 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3973 3974 if (dev->hotplugged && !smc->dr_phb_enabled) { 3975 error_setg(errp, "PHB hotplug not supported for this machine"); 3976 return; 3977 } 3978 3979 if (sphb->index == (uint32_t)-1) { 3980 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3981 return; 3982 } 3983 3984 /* 3985 * This will check that sphb->index doesn't exceed the maximum number of 3986 * PHBs for the current machine type. 3987 */ 3988 smc->phb_placement(spapr, sphb->index, 3989 &sphb->buid, &sphb->io_win_addr, 3990 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3991 windows_supported, sphb->dma_liobn, 3992 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3993 errp); 3994 } 3995 3996 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3997 Error **errp) 3998 { 3999 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4000 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4001 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4002 SpaprDrc *drc; 4003 bool hotplugged = spapr_drc_hotplugged(dev); 4004 Error *local_err = NULL; 4005 4006 if (!smc->dr_phb_enabled) { 4007 return; 4008 } 4009 4010 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4011 /* hotplug hooks should check it's enabled before getting this far */ 4012 assert(drc); 4013 4014 spapr_drc_attach(drc, DEVICE(dev), &local_err); 4015 if (local_err) { 4016 error_propagate(errp, local_err); 4017 return; 4018 } 4019 4020 if (hotplugged) { 4021 spapr_hotplug_req_add_by_index(drc); 4022 } else { 4023 spapr_drc_reset(drc); 4024 } 4025 } 4026 4027 void spapr_phb_release(DeviceState *dev) 4028 { 4029 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4030 4031 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4032 object_unparent(OBJECT(dev)); 4033 } 4034 4035 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4036 { 4037 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 4038 } 4039 4040 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4041 DeviceState *dev, Error **errp) 4042 { 4043 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4044 SpaprDrc *drc; 4045 4046 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4047 assert(drc); 4048 4049 if (!spapr_drc_unplug_requested(drc)) { 4050 spapr_drc_detach(drc); 4051 spapr_hotplug_req_remove_by_index(drc); 4052 } 4053 } 4054 4055 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4056 Error **errp) 4057 { 4058 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4059 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4060 4061 if (spapr->tpm_proxy != NULL) { 4062 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4063 return; 4064 } 4065 4066 spapr->tpm_proxy = tpm_proxy; 4067 } 4068 4069 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4070 { 4071 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4072 4073 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 4074 object_unparent(OBJECT(dev)); 4075 spapr->tpm_proxy = NULL; 4076 } 4077 4078 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4079 DeviceState *dev, Error **errp) 4080 { 4081 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4082 spapr_memory_plug(hotplug_dev, dev, errp); 4083 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4084 spapr_core_plug(hotplug_dev, dev, errp); 4085 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4086 spapr_phb_plug(hotplug_dev, dev, errp); 4087 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4088 spapr_tpm_proxy_plug(hotplug_dev, dev, errp); 4089 } 4090 } 4091 4092 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4093 DeviceState *dev, Error **errp) 4094 { 4095 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4096 spapr_memory_unplug(hotplug_dev, dev); 4097 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4098 spapr_core_unplug(hotplug_dev, dev); 4099 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4100 spapr_phb_unplug(hotplug_dev, dev); 4101 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4102 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4103 } 4104 } 4105 4106 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4107 DeviceState *dev, Error **errp) 4108 { 4109 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4110 MachineClass *mc = MACHINE_GET_CLASS(sms); 4111 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4112 4113 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4114 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 4115 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4116 } else { 4117 /* NOTE: this means there is a window after guest reset, prior to 4118 * CAS negotiation, where unplug requests will fail due to the 4119 * capability not being detected yet. This is a bit different than 4120 * the case with PCI unplug, where the events will be queued and 4121 * eventually handled by the guest after boot 4122 */ 4123 error_setg(errp, "Memory hot unplug not supported for this guest"); 4124 } 4125 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4126 if (!mc->has_hotpluggable_cpus) { 4127 error_setg(errp, "CPU hot unplug not supported on this machine"); 4128 return; 4129 } 4130 spapr_core_unplug_request(hotplug_dev, dev, errp); 4131 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4132 if (!smc->dr_phb_enabled) { 4133 error_setg(errp, "PHB hot unplug not supported on this machine"); 4134 return; 4135 } 4136 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4137 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4138 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4139 } 4140 } 4141 4142 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4143 DeviceState *dev, Error **errp) 4144 { 4145 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4146 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4147 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4148 spapr_core_pre_plug(hotplug_dev, dev, errp); 4149 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4150 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4151 } 4152 } 4153 4154 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4155 DeviceState *dev) 4156 { 4157 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4158 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4159 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4160 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4161 return HOTPLUG_HANDLER(machine); 4162 } 4163 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4164 PCIDevice *pcidev = PCI_DEVICE(dev); 4165 PCIBus *root = pci_device_root_bus(pcidev); 4166 SpaprPhbState *phb = 4167 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4168 TYPE_SPAPR_PCI_HOST_BRIDGE); 4169 4170 if (phb) { 4171 return HOTPLUG_HANDLER(phb); 4172 } 4173 } 4174 return NULL; 4175 } 4176 4177 static CpuInstanceProperties 4178 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4179 { 4180 CPUArchId *core_slot; 4181 MachineClass *mc = MACHINE_GET_CLASS(machine); 4182 4183 /* make sure possible_cpu are intialized */ 4184 mc->possible_cpu_arch_ids(machine); 4185 /* get CPU core slot containing thread that matches cpu_index */ 4186 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4187 assert(core_slot); 4188 return core_slot->props; 4189 } 4190 4191 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4192 { 4193 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4194 } 4195 4196 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4197 { 4198 int i; 4199 unsigned int smp_threads = machine->smp.threads; 4200 unsigned int smp_cpus = machine->smp.cpus; 4201 const char *core_type; 4202 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4203 MachineClass *mc = MACHINE_GET_CLASS(machine); 4204 4205 if (!mc->has_hotpluggable_cpus) { 4206 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4207 } 4208 if (machine->possible_cpus) { 4209 assert(machine->possible_cpus->len == spapr_max_cores); 4210 return machine->possible_cpus; 4211 } 4212 4213 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4214 if (!core_type) { 4215 error_report("Unable to find sPAPR CPU Core definition"); 4216 exit(1); 4217 } 4218 4219 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4220 sizeof(CPUArchId) * spapr_max_cores); 4221 machine->possible_cpus->len = spapr_max_cores; 4222 for (i = 0; i < machine->possible_cpus->len; i++) { 4223 int core_id = i * smp_threads; 4224 4225 machine->possible_cpus->cpus[i].type = core_type; 4226 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4227 machine->possible_cpus->cpus[i].arch_id = core_id; 4228 machine->possible_cpus->cpus[i].props.has_core_id = true; 4229 machine->possible_cpus->cpus[i].props.core_id = core_id; 4230 } 4231 return machine->possible_cpus; 4232 } 4233 4234 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4235 uint64_t *buid, hwaddr *pio, 4236 hwaddr *mmio32, hwaddr *mmio64, 4237 unsigned n_dma, uint32_t *liobns, 4238 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4239 { 4240 /* 4241 * New-style PHB window placement. 4242 * 4243 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4244 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4245 * windows. 4246 * 4247 * Some guest kernels can't work with MMIO windows above 1<<46 4248 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4249 * 4250 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4251 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4252 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4253 * 1TiB 64-bit MMIO windows for each PHB. 4254 */ 4255 const uint64_t base_buid = 0x800000020000000ULL; 4256 int i; 4257 4258 /* Sanity check natural alignments */ 4259 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4260 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4261 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4262 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4263 /* Sanity check bounds */ 4264 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4265 SPAPR_PCI_MEM32_WIN_SIZE); 4266 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4267 SPAPR_PCI_MEM64_WIN_SIZE); 4268 4269 if (index >= SPAPR_MAX_PHBS) { 4270 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4271 SPAPR_MAX_PHBS - 1); 4272 return; 4273 } 4274 4275 *buid = base_buid + index; 4276 for (i = 0; i < n_dma; ++i) { 4277 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4278 } 4279 4280 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4281 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4282 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4283 4284 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4285 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4286 } 4287 4288 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4289 { 4290 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4291 4292 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4293 } 4294 4295 static void spapr_ics_resend(XICSFabric *dev) 4296 { 4297 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4298 4299 ics_resend(spapr->ics); 4300 } 4301 4302 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4303 { 4304 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4305 4306 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4307 } 4308 4309 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4310 Monitor *mon) 4311 { 4312 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4313 4314 spapr_irq_print_info(spapr, mon); 4315 monitor_printf(mon, "irqchip: %s\n", 4316 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4317 } 4318 4319 /* 4320 * This is a XIVE only operation 4321 */ 4322 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4323 uint8_t nvt_blk, uint32_t nvt_idx, 4324 bool cam_ignore, uint8_t priority, 4325 uint32_t logic_serv, XiveTCTXMatch *match) 4326 { 4327 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4328 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4329 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4330 int count; 4331 4332 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4333 priority, logic_serv, match); 4334 if (count < 0) { 4335 return count; 4336 } 4337 4338 /* 4339 * When we implement the save and restore of the thread interrupt 4340 * contexts in the enter/exit CPU handlers of the machine and the 4341 * escalations in QEMU, we should be able to handle non dispatched 4342 * vCPUs. 4343 * 4344 * Until this is done, the sPAPR machine should find at least one 4345 * matching context always. 4346 */ 4347 if (count == 0) { 4348 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4349 nvt_blk, nvt_idx); 4350 } 4351 4352 return count; 4353 } 4354 4355 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4356 { 4357 return cpu->vcpu_id; 4358 } 4359 4360 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4361 { 4362 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4363 MachineState *ms = MACHINE(spapr); 4364 int vcpu_id; 4365 4366 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4367 4368 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4369 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4370 error_append_hint(errp, "Adjust the number of cpus to %d " 4371 "or try to raise the number of threads per core\n", 4372 vcpu_id * ms->smp.threads / spapr->vsmt); 4373 return; 4374 } 4375 4376 cpu->vcpu_id = vcpu_id; 4377 } 4378 4379 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4380 { 4381 CPUState *cs; 4382 4383 CPU_FOREACH(cs) { 4384 PowerPCCPU *cpu = POWERPC_CPU(cs); 4385 4386 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4387 return cpu; 4388 } 4389 } 4390 4391 return NULL; 4392 } 4393 4394 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4395 { 4396 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4397 4398 /* These are only called by TCG, KVM maintains dispatch state */ 4399 4400 spapr_cpu->prod = false; 4401 if (spapr_cpu->vpa_addr) { 4402 CPUState *cs = CPU(cpu); 4403 uint32_t dispatch; 4404 4405 dispatch = ldl_be_phys(cs->as, 4406 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4407 dispatch++; 4408 if ((dispatch & 1) != 0) { 4409 qemu_log_mask(LOG_GUEST_ERROR, 4410 "VPA: incorrect dispatch counter value for " 4411 "dispatched partition %u, correcting.\n", dispatch); 4412 dispatch++; 4413 } 4414 stl_be_phys(cs->as, 4415 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4416 } 4417 } 4418 4419 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4420 { 4421 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4422 4423 if (spapr_cpu->vpa_addr) { 4424 CPUState *cs = CPU(cpu); 4425 uint32_t dispatch; 4426 4427 dispatch = ldl_be_phys(cs->as, 4428 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4429 dispatch++; 4430 if ((dispatch & 1) != 1) { 4431 qemu_log_mask(LOG_GUEST_ERROR, 4432 "VPA: incorrect dispatch counter value for " 4433 "preempted partition %u, correcting.\n", dispatch); 4434 dispatch++; 4435 } 4436 stl_be_phys(cs->as, 4437 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4438 } 4439 } 4440 4441 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4442 { 4443 MachineClass *mc = MACHINE_CLASS(oc); 4444 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4445 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4446 NMIClass *nc = NMI_CLASS(oc); 4447 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4448 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4449 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4450 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4451 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4452 4453 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4454 mc->ignore_boot_device_suffixes = true; 4455 4456 /* 4457 * We set up the default / latest behaviour here. The class_init 4458 * functions for the specific versioned machine types can override 4459 * these details for backwards compatibility 4460 */ 4461 mc->init = spapr_machine_init; 4462 mc->reset = spapr_machine_reset; 4463 mc->block_default_type = IF_SCSI; 4464 mc->max_cpus = 1024; 4465 mc->no_parallel = 1; 4466 mc->default_boot_order = ""; 4467 mc->default_ram_size = 512 * MiB; 4468 mc->default_ram_id = "ppc_spapr.ram"; 4469 mc->default_display = "std"; 4470 mc->kvm_type = spapr_kvm_type; 4471 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4472 mc->pci_allow_0_address = true; 4473 assert(!mc->get_hotplug_handler); 4474 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4475 hc->pre_plug = spapr_machine_device_pre_plug; 4476 hc->plug = spapr_machine_device_plug; 4477 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4478 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4479 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4480 hc->unplug_request = spapr_machine_device_unplug_request; 4481 hc->unplug = spapr_machine_device_unplug; 4482 4483 smc->dr_lmb_enabled = true; 4484 smc->update_dt_enabled = true; 4485 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4486 mc->has_hotpluggable_cpus = true; 4487 mc->nvdimm_supported = true; 4488 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4489 fwc->get_dev_path = spapr_get_fw_dev_path; 4490 nc->nmi_monitor_handler = spapr_nmi; 4491 smc->phb_placement = spapr_phb_placement; 4492 vhc->hypercall = emulate_spapr_hypercall; 4493 vhc->hpt_mask = spapr_hpt_mask; 4494 vhc->map_hptes = spapr_map_hptes; 4495 vhc->unmap_hptes = spapr_unmap_hptes; 4496 vhc->hpte_set_c = spapr_hpte_set_c; 4497 vhc->hpte_set_r = spapr_hpte_set_r; 4498 vhc->get_pate = spapr_get_pate; 4499 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4500 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4501 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4502 xic->ics_get = spapr_ics_get; 4503 xic->ics_resend = spapr_ics_resend; 4504 xic->icp_get = spapr_icp_get; 4505 ispc->print_info = spapr_pic_print_info; 4506 /* Force NUMA node memory size to be a multiple of 4507 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4508 * in which LMBs are represented and hot-added 4509 */ 4510 mc->numa_mem_align_shift = 28; 4511 mc->numa_mem_supported = true; 4512 mc->auto_enable_numa = true; 4513 4514 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4515 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4516 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4517 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4518 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4519 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4520 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4521 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4522 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4523 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4524 smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] = SPAPR_CAP_ON; 4525 spapr_caps_add_properties(smc, &error_abort); 4526 smc->irq = &spapr_irq_dual; 4527 smc->dr_phb_enabled = true; 4528 smc->linux_pci_probe = true; 4529 smc->smp_threads_vsmt = true; 4530 smc->nr_xirqs = SPAPR_NR_XIRQS; 4531 xfc->match_nvt = spapr_match_nvt; 4532 } 4533 4534 static const TypeInfo spapr_machine_info = { 4535 .name = TYPE_SPAPR_MACHINE, 4536 .parent = TYPE_MACHINE, 4537 .abstract = true, 4538 .instance_size = sizeof(SpaprMachineState), 4539 .instance_init = spapr_instance_init, 4540 .instance_finalize = spapr_machine_finalizefn, 4541 .class_size = sizeof(SpaprMachineClass), 4542 .class_init = spapr_machine_class_init, 4543 .interfaces = (InterfaceInfo[]) { 4544 { TYPE_FW_PATH_PROVIDER }, 4545 { TYPE_NMI }, 4546 { TYPE_HOTPLUG_HANDLER }, 4547 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4548 { TYPE_XICS_FABRIC }, 4549 { TYPE_INTERRUPT_STATS_PROVIDER }, 4550 { TYPE_XIVE_FABRIC }, 4551 { } 4552 }, 4553 }; 4554 4555 static void spapr_machine_latest_class_options(MachineClass *mc) 4556 { 4557 mc->alias = "pseries"; 4558 mc->is_default = true; 4559 } 4560 4561 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4562 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4563 void *data) \ 4564 { \ 4565 MachineClass *mc = MACHINE_CLASS(oc); \ 4566 spapr_machine_##suffix##_class_options(mc); \ 4567 if (latest) { \ 4568 spapr_machine_latest_class_options(mc); \ 4569 } \ 4570 } \ 4571 static const TypeInfo spapr_machine_##suffix##_info = { \ 4572 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4573 .parent = TYPE_SPAPR_MACHINE, \ 4574 .class_init = spapr_machine_##suffix##_class_init, \ 4575 }; \ 4576 static void spapr_machine_register_##suffix(void) \ 4577 { \ 4578 type_register(&spapr_machine_##suffix##_info); \ 4579 } \ 4580 type_init(spapr_machine_register_##suffix) 4581 4582 /* 4583 * pseries-5.0 4584 */ 4585 static void spapr_machine_5_0_class_options(MachineClass *mc) 4586 { 4587 /* Defaults for the latest behaviour inherited from the base class */ 4588 } 4589 4590 DEFINE_SPAPR_MACHINE(5_0, "5.0", true); 4591 4592 /* 4593 * pseries-4.2 4594 */ 4595 static void spapr_machine_4_2_class_options(MachineClass *mc) 4596 { 4597 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4598 4599 spapr_machine_5_0_class_options(mc); 4600 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4601 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4602 smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] = SPAPR_CAP_OFF; 4603 smc->rma_limit = 16 * GiB; 4604 mc->nvdimm_supported = false; 4605 } 4606 4607 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4608 4609 /* 4610 * pseries-4.1 4611 */ 4612 static void spapr_machine_4_1_class_options(MachineClass *mc) 4613 { 4614 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4615 static GlobalProperty compat[] = { 4616 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4617 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4618 }; 4619 4620 spapr_machine_4_2_class_options(mc); 4621 smc->linux_pci_probe = false; 4622 smc->smp_threads_vsmt = false; 4623 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4624 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4625 } 4626 4627 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4628 4629 /* 4630 * pseries-4.0 4631 */ 4632 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4633 uint64_t *buid, hwaddr *pio, 4634 hwaddr *mmio32, hwaddr *mmio64, 4635 unsigned n_dma, uint32_t *liobns, 4636 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4637 { 4638 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, 4639 nv2gpa, nv2atsd, errp); 4640 *nv2gpa = 0; 4641 *nv2atsd = 0; 4642 } 4643 4644 static void spapr_machine_4_0_class_options(MachineClass *mc) 4645 { 4646 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4647 4648 spapr_machine_4_1_class_options(mc); 4649 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4650 smc->phb_placement = phb_placement_4_0; 4651 smc->irq = &spapr_irq_xics; 4652 smc->pre_4_1_migration = true; 4653 } 4654 4655 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4656 4657 /* 4658 * pseries-3.1 4659 */ 4660 static void spapr_machine_3_1_class_options(MachineClass *mc) 4661 { 4662 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4663 4664 spapr_machine_4_0_class_options(mc); 4665 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4666 4667 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4668 smc->update_dt_enabled = false; 4669 smc->dr_phb_enabled = false; 4670 smc->broken_host_serial_model = true; 4671 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4672 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4673 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4674 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4675 } 4676 4677 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4678 4679 /* 4680 * pseries-3.0 4681 */ 4682 4683 static void spapr_machine_3_0_class_options(MachineClass *mc) 4684 { 4685 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4686 4687 spapr_machine_3_1_class_options(mc); 4688 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4689 4690 smc->legacy_irq_allocation = true; 4691 smc->nr_xirqs = 0x400; 4692 smc->irq = &spapr_irq_xics_legacy; 4693 } 4694 4695 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4696 4697 /* 4698 * pseries-2.12 4699 */ 4700 static void spapr_machine_2_12_class_options(MachineClass *mc) 4701 { 4702 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4703 static GlobalProperty compat[] = { 4704 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4705 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4706 }; 4707 4708 spapr_machine_3_0_class_options(mc); 4709 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4710 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4711 4712 /* We depend on kvm_enabled() to choose a default value for the 4713 * hpt-max-page-size capability. Of course we can't do it here 4714 * because this is too early and the HW accelerator isn't initialzed 4715 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4716 */ 4717 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4718 } 4719 4720 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4721 4722 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4723 { 4724 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4725 4726 spapr_machine_2_12_class_options(mc); 4727 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4728 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4729 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4730 } 4731 4732 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4733 4734 /* 4735 * pseries-2.11 4736 */ 4737 4738 static void spapr_machine_2_11_class_options(MachineClass *mc) 4739 { 4740 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4741 4742 spapr_machine_2_12_class_options(mc); 4743 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4744 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4745 } 4746 4747 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4748 4749 /* 4750 * pseries-2.10 4751 */ 4752 4753 static void spapr_machine_2_10_class_options(MachineClass *mc) 4754 { 4755 spapr_machine_2_11_class_options(mc); 4756 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4757 } 4758 4759 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4760 4761 /* 4762 * pseries-2.9 4763 */ 4764 4765 static void spapr_machine_2_9_class_options(MachineClass *mc) 4766 { 4767 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4768 static GlobalProperty compat[] = { 4769 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4770 }; 4771 4772 spapr_machine_2_10_class_options(mc); 4773 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4774 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4775 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4776 smc->pre_2_10_has_unused_icps = true; 4777 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4778 } 4779 4780 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4781 4782 /* 4783 * pseries-2.8 4784 */ 4785 4786 static void spapr_machine_2_8_class_options(MachineClass *mc) 4787 { 4788 static GlobalProperty compat[] = { 4789 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4790 }; 4791 4792 spapr_machine_2_9_class_options(mc); 4793 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4794 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4795 mc->numa_mem_align_shift = 23; 4796 } 4797 4798 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4799 4800 /* 4801 * pseries-2.7 4802 */ 4803 4804 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4805 uint64_t *buid, hwaddr *pio, 4806 hwaddr *mmio32, hwaddr *mmio64, 4807 unsigned n_dma, uint32_t *liobns, 4808 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4809 { 4810 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4811 const uint64_t base_buid = 0x800000020000000ULL; 4812 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4813 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4814 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4815 const uint32_t max_index = 255; 4816 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4817 4818 uint64_t ram_top = MACHINE(spapr)->ram_size; 4819 hwaddr phb0_base, phb_base; 4820 int i; 4821 4822 /* Do we have device memory? */ 4823 if (MACHINE(spapr)->maxram_size > ram_top) { 4824 /* Can't just use maxram_size, because there may be an 4825 * alignment gap between normal and device memory regions 4826 */ 4827 ram_top = MACHINE(spapr)->device_memory->base + 4828 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4829 } 4830 4831 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4832 4833 if (index > max_index) { 4834 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4835 max_index); 4836 return; 4837 } 4838 4839 *buid = base_buid + index; 4840 for (i = 0; i < n_dma; ++i) { 4841 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4842 } 4843 4844 phb_base = phb0_base + index * phb_spacing; 4845 *pio = phb_base + pio_offset; 4846 *mmio32 = phb_base + mmio_offset; 4847 /* 4848 * We don't set the 64-bit MMIO window, relying on the PHB's 4849 * fallback behaviour of automatically splitting a large "32-bit" 4850 * window into contiguous 32-bit and 64-bit windows 4851 */ 4852 4853 *nv2gpa = 0; 4854 *nv2atsd = 0; 4855 } 4856 4857 static void spapr_machine_2_7_class_options(MachineClass *mc) 4858 { 4859 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4860 static GlobalProperty compat[] = { 4861 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4862 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4863 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4864 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4865 }; 4866 4867 spapr_machine_2_8_class_options(mc); 4868 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4869 mc->default_machine_opts = "modern-hotplug-events=off"; 4870 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4871 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4872 smc->phb_placement = phb_placement_2_7; 4873 } 4874 4875 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4876 4877 /* 4878 * pseries-2.6 4879 */ 4880 4881 static void spapr_machine_2_6_class_options(MachineClass *mc) 4882 { 4883 static GlobalProperty compat[] = { 4884 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4885 }; 4886 4887 spapr_machine_2_7_class_options(mc); 4888 mc->has_hotpluggable_cpus = false; 4889 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4890 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4891 } 4892 4893 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4894 4895 /* 4896 * pseries-2.5 4897 */ 4898 4899 static void spapr_machine_2_5_class_options(MachineClass *mc) 4900 { 4901 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4902 static GlobalProperty compat[] = { 4903 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4904 }; 4905 4906 spapr_machine_2_6_class_options(mc); 4907 smc->use_ohci_by_default = true; 4908 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4909 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4910 } 4911 4912 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4913 4914 /* 4915 * pseries-2.4 4916 */ 4917 4918 static void spapr_machine_2_4_class_options(MachineClass *mc) 4919 { 4920 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4921 4922 spapr_machine_2_5_class_options(mc); 4923 smc->dr_lmb_enabled = false; 4924 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4925 } 4926 4927 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4928 4929 /* 4930 * pseries-2.3 4931 */ 4932 4933 static void spapr_machine_2_3_class_options(MachineClass *mc) 4934 { 4935 static GlobalProperty compat[] = { 4936 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4937 }; 4938 spapr_machine_2_4_class_options(mc); 4939 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4940 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4941 } 4942 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4943 4944 /* 4945 * pseries-2.2 4946 */ 4947 4948 static void spapr_machine_2_2_class_options(MachineClass *mc) 4949 { 4950 static GlobalProperty compat[] = { 4951 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4952 }; 4953 4954 spapr_machine_2_3_class_options(mc); 4955 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4956 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4957 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4958 } 4959 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4960 4961 /* 4962 * pseries-2.1 4963 */ 4964 4965 static void spapr_machine_2_1_class_options(MachineClass *mc) 4966 { 4967 spapr_machine_2_2_class_options(mc); 4968 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4969 } 4970 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4971 4972 static void spapr_machine_register_types(void) 4973 { 4974 type_register_static(&spapr_machine_info); 4975 } 4976 4977 type_init(spapr_machine_register_types) 4978