1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "sysemu/sysemu.h" 28 #include "sysemu/numa.h" 29 #include "hw/hw.h" 30 #include "hw/fw-path-provider.h" 31 #include "elf.h" 32 #include "net/net.h" 33 #include "sysemu/block-backend.h" 34 #include "sysemu/cpus.h" 35 #include "sysemu/kvm.h" 36 #include "kvm_ppc.h" 37 #include "mmu-hash64.h" 38 #include "qom/cpu.h" 39 40 #include "hw/boards.h" 41 #include "hw/ppc/ppc.h" 42 #include "hw/loader.h" 43 44 #include "hw/ppc/spapr.h" 45 #include "hw/ppc/spapr_vio.h" 46 #include "hw/pci-host/spapr.h" 47 #include "hw/ppc/xics.h" 48 #include "hw/pci/msi.h" 49 50 #include "hw/pci/pci.h" 51 #include "hw/scsi/scsi.h" 52 #include "hw/virtio/virtio-scsi.h" 53 54 #include "exec/address-spaces.h" 55 #include "hw/usb.h" 56 #include "qemu/config-file.h" 57 #include "qemu/error-report.h" 58 #include "trace.h" 59 #include "hw/nmi.h" 60 61 #include "hw/compat.h" 62 63 #include <libfdt.h> 64 65 /* SLOF memory layout: 66 * 67 * SLOF raw image loaded at 0, copies its romfs right below the flat 68 * device-tree, then position SLOF itself 31M below that 69 * 70 * So we set FW_OVERHEAD to 40MB which should account for all of that 71 * and more 72 * 73 * We load our kernel at 4M, leaving space for SLOF initial image 74 */ 75 #define FDT_MAX_SIZE 0x40000 76 #define RTAS_MAX_SIZE 0x10000 77 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 78 #define FW_MAX_SIZE 0x400000 79 #define FW_FILE_NAME "slof.bin" 80 #define FW_OVERHEAD 0x2800000 81 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 82 83 #define MIN_RMA_SLOF 128UL 84 85 #define TIMEBASE_FREQ 512000000ULL 86 87 #define MAX_CPUS 255 88 89 #define PHANDLE_XICP 0x00001111 90 91 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 92 93 typedef struct sPAPRMachineState sPAPRMachineState; 94 95 #define TYPE_SPAPR_MACHINE "spapr-machine" 96 #define SPAPR_MACHINE(obj) \ 97 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 98 99 /** 100 * sPAPRMachineState: 101 */ 102 struct sPAPRMachineState { 103 /*< private >*/ 104 MachineState parent_obj; 105 106 /*< public >*/ 107 char *kvm_type; 108 }; 109 110 sPAPREnvironment *spapr; 111 112 static XICSState *try_create_xics(const char *type, int nr_servers, 113 int nr_irqs, Error **errp) 114 { 115 Error *err = NULL; 116 DeviceState *dev; 117 118 dev = qdev_create(NULL, type); 119 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 120 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 121 object_property_set_bool(OBJECT(dev), true, "realized", &err); 122 if (err) { 123 error_propagate(errp, err); 124 object_unparent(OBJECT(dev)); 125 return NULL; 126 } 127 return XICS_COMMON(dev); 128 } 129 130 static XICSState *xics_system_init(MachineState *machine, 131 int nr_servers, int nr_irqs) 132 { 133 XICSState *icp = NULL; 134 135 if (kvm_enabled()) { 136 Error *err = NULL; 137 138 if (machine_kernel_irqchip_allowed(machine)) { 139 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err); 140 } 141 if (machine_kernel_irqchip_required(machine) && !icp) { 142 error_report("kernel_irqchip requested but unavailable: %s", 143 error_get_pretty(err)); 144 } 145 } 146 147 if (!icp) { 148 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, &error_abort); 149 } 150 151 return icp; 152 } 153 154 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 155 int smt_threads) 156 { 157 int i, ret = 0; 158 uint32_t servers_prop[smt_threads]; 159 uint32_t gservers_prop[smt_threads * 2]; 160 int index = ppc_get_vcpu_dt_id(cpu); 161 162 if (cpu->cpu_version) { 163 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); 164 if (ret < 0) { 165 return ret; 166 } 167 } 168 169 /* Build interrupt servers and gservers properties */ 170 for (i = 0; i < smt_threads; i++) { 171 servers_prop[i] = cpu_to_be32(index + i); 172 /* Hack, direct the group queues back to cpu 0 */ 173 gservers_prop[i*2] = cpu_to_be32(index + i); 174 gservers_prop[i*2 + 1] = 0; 175 } 176 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 177 servers_prop, sizeof(servers_prop)); 178 if (ret < 0) { 179 return ret; 180 } 181 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 182 gservers_prop, sizeof(gservers_prop)); 183 184 return ret; 185 } 186 187 static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) 188 { 189 int ret = 0, offset, cpus_offset; 190 CPUState *cs; 191 char cpu_model[32]; 192 int smt = kvmppc_smt_threads(); 193 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 194 195 CPU_FOREACH(cs) { 196 PowerPCCPU *cpu = POWERPC_CPU(cs); 197 DeviceClass *dc = DEVICE_GET_CLASS(cs); 198 int index = ppc_get_vcpu_dt_id(cpu); 199 uint32_t associativity[] = {cpu_to_be32(0x5), 200 cpu_to_be32(0x0), 201 cpu_to_be32(0x0), 202 cpu_to_be32(0x0), 203 cpu_to_be32(cs->numa_node), 204 cpu_to_be32(index)}; 205 206 if ((index % smt) != 0) { 207 continue; 208 } 209 210 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 211 212 cpus_offset = fdt_path_offset(fdt, "/cpus"); 213 if (cpus_offset < 0) { 214 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 215 "cpus"); 216 if (cpus_offset < 0) { 217 return cpus_offset; 218 } 219 } 220 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 221 if (offset < 0) { 222 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 223 if (offset < 0) { 224 return offset; 225 } 226 } 227 228 if (nb_numa_nodes > 1) { 229 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 230 sizeof(associativity)); 231 if (ret < 0) { 232 return ret; 233 } 234 } 235 236 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 237 pft_size_prop, sizeof(pft_size_prop)); 238 if (ret < 0) { 239 return ret; 240 } 241 242 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 243 ppc_get_compat_smt_threads(cpu)); 244 if (ret < 0) { 245 return ret; 246 } 247 } 248 return ret; 249 } 250 251 252 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 253 size_t maxsize) 254 { 255 size_t maxcells = maxsize / sizeof(uint32_t); 256 int i, j, count; 257 uint32_t *p = prop; 258 259 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 260 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 261 262 if (!sps->page_shift) { 263 break; 264 } 265 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 266 if (sps->enc[count].page_shift == 0) { 267 break; 268 } 269 } 270 if ((p - prop) >= (maxcells - 3 - count * 2)) { 271 break; 272 } 273 *(p++) = cpu_to_be32(sps->page_shift); 274 *(p++) = cpu_to_be32(sps->slb_enc); 275 *(p++) = cpu_to_be32(count); 276 for (j = 0; j < count; j++) { 277 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 278 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 279 } 280 } 281 282 return (p - prop) * sizeof(uint32_t); 283 } 284 285 static hwaddr spapr_node0_size(void) 286 { 287 if (nb_numa_nodes) { 288 int i; 289 for (i = 0; i < nb_numa_nodes; ++i) { 290 if (numa_info[i].node_mem) { 291 return MIN(pow2floor(numa_info[i].node_mem), ram_size); 292 } 293 } 294 } 295 return ram_size; 296 } 297 298 #define _FDT(exp) \ 299 do { \ 300 int ret = (exp); \ 301 if (ret < 0) { \ 302 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 303 #exp, fdt_strerror(ret)); \ 304 exit(1); \ 305 } \ 306 } while (0) 307 308 static void add_str(GString *s, const gchar *s1) 309 { 310 g_string_append_len(s, s1, strlen(s1) + 1); 311 } 312 313 static void *spapr_create_fdt_skel(hwaddr initrd_base, 314 hwaddr initrd_size, 315 hwaddr kernel_size, 316 bool little_endian, 317 const char *kernel_cmdline, 318 uint32_t epow_irq) 319 { 320 void *fdt; 321 CPUState *cs; 322 uint32_t start_prop = cpu_to_be32(initrd_base); 323 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 324 GString *hypertas = g_string_sized_new(256); 325 GString *qemu_hypertas = g_string_sized_new(256); 326 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 327 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; 328 int smt = kvmppc_smt_threads(); 329 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 330 QemuOpts *opts = qemu_opts_find(qemu_find_opts("smp-opts"), NULL); 331 unsigned sockets = opts ? qemu_opt_get_number(opts, "sockets", 0) : 0; 332 uint32_t cpus_per_socket = sockets ? (smp_cpus / sockets) : 1; 333 char *buf; 334 335 add_str(hypertas, "hcall-pft"); 336 add_str(hypertas, "hcall-term"); 337 add_str(hypertas, "hcall-dabr"); 338 add_str(hypertas, "hcall-interrupt"); 339 add_str(hypertas, "hcall-tce"); 340 add_str(hypertas, "hcall-vio"); 341 add_str(hypertas, "hcall-splpar"); 342 add_str(hypertas, "hcall-bulk"); 343 add_str(hypertas, "hcall-set-mode"); 344 add_str(qemu_hypertas, "hcall-memop1"); 345 346 fdt = g_malloc0(FDT_MAX_SIZE); 347 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 348 349 if (kernel_size) { 350 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 351 } 352 if (initrd_size) { 353 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 354 } 355 _FDT((fdt_finish_reservemap(fdt))); 356 357 /* Root node */ 358 _FDT((fdt_begin_node(fdt, ""))); 359 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 360 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 361 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 362 363 /* 364 * Add info to guest to indentify which host is it being run on 365 * and what is the uuid of the guest 366 */ 367 if (kvmppc_get_host_model(&buf)) { 368 _FDT((fdt_property_string(fdt, "host-model", buf))); 369 g_free(buf); 370 } 371 if (kvmppc_get_host_serial(&buf)) { 372 _FDT((fdt_property_string(fdt, "host-serial", buf))); 373 g_free(buf); 374 } 375 376 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1], 377 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4], 378 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7], 379 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10], 380 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13], 381 qemu_uuid[14], qemu_uuid[15]); 382 383 _FDT((fdt_property_string(fdt, "vm,uuid", buf))); 384 g_free(buf); 385 386 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 387 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 388 389 /* /chosen */ 390 _FDT((fdt_begin_node(fdt, "chosen"))); 391 392 /* Set Form1_affinity */ 393 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 394 395 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 396 _FDT((fdt_property(fdt, "linux,initrd-start", 397 &start_prop, sizeof(start_prop)))); 398 _FDT((fdt_property(fdt, "linux,initrd-end", 399 &end_prop, sizeof(end_prop)))); 400 if (kernel_size) { 401 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 402 cpu_to_be64(kernel_size) }; 403 404 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 405 if (little_endian) { 406 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 407 } 408 } 409 if (boot_menu) { 410 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); 411 } 412 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 413 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 414 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 415 416 _FDT((fdt_end_node(fdt))); 417 418 /* cpus */ 419 _FDT((fdt_begin_node(fdt, "cpus"))); 420 421 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 422 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 423 424 CPU_FOREACH(cs) { 425 PowerPCCPU *cpu = POWERPC_CPU(cs); 426 CPUPPCState *env = &cpu->env; 427 DeviceClass *dc = DEVICE_GET_CLASS(cs); 428 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 429 int index = ppc_get_vcpu_dt_id(cpu); 430 char *nodename; 431 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 432 0xffffffff, 0xffffffff}; 433 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 434 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 435 uint32_t page_sizes_prop[64]; 436 size_t page_sizes_prop_size; 437 438 if ((index % smt) != 0) { 439 continue; 440 } 441 442 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 443 444 _FDT((fdt_begin_node(fdt, nodename))); 445 446 g_free(nodename); 447 448 _FDT((fdt_property_cell(fdt, "reg", index))); 449 _FDT((fdt_property_string(fdt, "device_type", "cpu"))); 450 451 _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); 452 _FDT((fdt_property_cell(fdt, "d-cache-block-size", 453 env->dcache_line_size))); 454 _FDT((fdt_property_cell(fdt, "d-cache-line-size", 455 env->dcache_line_size))); 456 _FDT((fdt_property_cell(fdt, "i-cache-block-size", 457 env->icache_line_size))); 458 _FDT((fdt_property_cell(fdt, "i-cache-line-size", 459 env->icache_line_size))); 460 461 if (pcc->l1_dcache_size) { 462 _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size))); 463 } else { 464 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 465 } 466 if (pcc->l1_icache_size) { 467 _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size))); 468 } else { 469 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 470 } 471 472 _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq))); 473 _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq))); 474 _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); 475 _FDT((fdt_property_string(fdt, "status", "okay"))); 476 _FDT((fdt_property(fdt, "64-bit", NULL, 0))); 477 478 if (env->spr_cb[SPR_PURR].oea_read) { 479 _FDT((fdt_property(fdt, "ibm,purr", NULL, 0))); 480 } 481 482 if (env->mmu_model & POWERPC_MMU_1TSEG) { 483 _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", 484 segs, sizeof(segs)))); 485 } 486 487 /* Advertise VMX/VSX (vector extensions) if available 488 * 0 / no property == no vector extensions 489 * 1 == VMX / Altivec available 490 * 2 == VSX available */ 491 if (env->insns_flags & PPC_ALTIVEC) { 492 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 493 494 _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx))); 495 } 496 497 /* Advertise DFP (Decimal Floating Point) if available 498 * 0 / no property == no DFP 499 * 1 == DFP available */ 500 if (env->insns_flags2 & PPC2_DFP) { 501 _FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); 502 } 503 504 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 505 sizeof(page_sizes_prop)); 506 if (page_sizes_prop_size) { 507 _FDT((fdt_property(fdt, "ibm,segment-page-sizes", 508 page_sizes_prop, page_sizes_prop_size))); 509 } 510 511 _FDT((fdt_property_cell(fdt, "ibm,chip-id", 512 cs->cpu_index / cpus_per_socket))); 513 514 _FDT((fdt_end_node(fdt))); 515 } 516 517 _FDT((fdt_end_node(fdt))); 518 519 /* RTAS */ 520 _FDT((fdt_begin_node(fdt, "rtas"))); 521 522 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 523 add_str(hypertas, "hcall-multi-tce"); 524 } 525 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, 526 hypertas->len))); 527 g_string_free(hypertas, TRUE); 528 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, 529 qemu_hypertas->len))); 530 g_string_free(qemu_hypertas, TRUE); 531 532 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 533 refpoints, sizeof(refpoints)))); 534 535 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 536 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate", 537 RTAS_EVENT_SCAN_RATE))); 538 539 /* 540 * According to PAPR, rtas ibm,os-term does not guarantee a return 541 * back to the guest cpu. 542 * 543 * While an additional ibm,extended-os-term property indicates that 544 * rtas call return will always occur. Set this property. 545 */ 546 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0))); 547 548 _FDT((fdt_end_node(fdt))); 549 550 /* interrupt controller */ 551 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 552 553 _FDT((fdt_property_string(fdt, "device_type", 554 "PowerPC-External-Interrupt-Presentation"))); 555 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 556 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 557 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 558 interrupt_server_ranges_prop, 559 sizeof(interrupt_server_ranges_prop)))); 560 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 561 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 562 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 563 564 _FDT((fdt_end_node(fdt))); 565 566 /* vdevice */ 567 _FDT((fdt_begin_node(fdt, "vdevice"))); 568 569 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 570 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 571 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 572 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 573 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 574 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 575 576 _FDT((fdt_end_node(fdt))); 577 578 /* event-sources */ 579 spapr_events_fdt_skel(fdt, epow_irq); 580 581 /* /hypervisor node */ 582 if (kvm_enabled()) { 583 uint8_t hypercall[16]; 584 585 /* indicate KVM hypercall interface */ 586 _FDT((fdt_begin_node(fdt, "hypervisor"))); 587 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); 588 if (kvmppc_has_cap_fixup_hcalls()) { 589 /* 590 * Older KVM versions with older guest kernels were broken with the 591 * magic page, don't allow the guest to map it. 592 */ 593 kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 594 sizeof(hypercall)); 595 _FDT((fdt_property(fdt, "hcall-instructions", hypercall, 596 sizeof(hypercall)))); 597 } 598 _FDT((fdt_end_node(fdt))); 599 } 600 601 _FDT((fdt_end_node(fdt))); /* close root node */ 602 _FDT((fdt_finish(fdt))); 603 604 return fdt; 605 } 606 607 int spapr_h_cas_compose_response(target_ulong addr, target_ulong size) 608 { 609 void *fdt, *fdt_skel; 610 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 611 612 size -= sizeof(hdr); 613 614 /* Create sceleton */ 615 fdt_skel = g_malloc0(size); 616 _FDT((fdt_create(fdt_skel, size))); 617 _FDT((fdt_begin_node(fdt_skel, ""))); 618 _FDT((fdt_end_node(fdt_skel))); 619 _FDT((fdt_finish(fdt_skel))); 620 fdt = g_malloc0(size); 621 _FDT((fdt_open_into(fdt_skel, fdt, size))); 622 g_free(fdt_skel); 623 624 /* Fix skeleton up */ 625 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 626 627 /* Pack resulting tree */ 628 _FDT((fdt_pack(fdt))); 629 630 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 631 trace_spapr_cas_failed(size); 632 return -1; 633 } 634 635 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 636 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 637 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 638 g_free(fdt); 639 640 return 0; 641 } 642 643 static void spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 644 hwaddr size) 645 { 646 uint32_t associativity[] = { 647 cpu_to_be32(0x4), /* length */ 648 cpu_to_be32(0x0), cpu_to_be32(0x0), 649 cpu_to_be32(0x0), cpu_to_be32(nodeid) 650 }; 651 char mem_name[32]; 652 uint64_t mem_reg_property[2]; 653 int off; 654 655 mem_reg_property[0] = cpu_to_be64(start); 656 mem_reg_property[1] = cpu_to_be64(size); 657 658 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 659 off = fdt_add_subnode(fdt, 0, mem_name); 660 _FDT(off); 661 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 662 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 663 sizeof(mem_reg_property)))); 664 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 665 sizeof(associativity)))); 666 } 667 668 static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt) 669 { 670 hwaddr mem_start, node_size; 671 int i, nb_nodes = nb_numa_nodes; 672 NodeInfo *nodes = numa_info; 673 NodeInfo ramnode; 674 675 /* No NUMA nodes, assume there is just one node with whole RAM */ 676 if (!nb_numa_nodes) { 677 nb_nodes = 1; 678 ramnode.node_mem = ram_size; 679 nodes = &ramnode; 680 } 681 682 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 683 if (!nodes[i].node_mem) { 684 continue; 685 } 686 if (mem_start >= ram_size) { 687 node_size = 0; 688 } else { 689 node_size = nodes[i].node_mem; 690 if (node_size > ram_size - mem_start) { 691 node_size = ram_size - mem_start; 692 } 693 } 694 if (!mem_start) { 695 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 696 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 697 mem_start += spapr->rma_size; 698 node_size -= spapr->rma_size; 699 } 700 for ( ; node_size; ) { 701 hwaddr sizetmp = pow2floor(node_size); 702 703 /* mem_start != 0 here */ 704 if (ctzl(mem_start) < ctzl(sizetmp)) { 705 sizetmp = 1ULL << ctzl(mem_start); 706 } 707 708 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 709 node_size -= sizetmp; 710 mem_start += sizetmp; 711 } 712 } 713 714 return 0; 715 } 716 717 static void spapr_finalize_fdt(sPAPREnvironment *spapr, 718 hwaddr fdt_addr, 719 hwaddr rtas_addr, 720 hwaddr rtas_size) 721 { 722 MachineState *machine = MACHINE(qdev_get_machine()); 723 const char *boot_device = machine->boot_order; 724 int ret, i; 725 size_t cb = 0; 726 char *bootlist; 727 void *fdt; 728 sPAPRPHBState *phb; 729 730 fdt = g_malloc(FDT_MAX_SIZE); 731 732 /* open out the base tree into a temp buffer for the final tweaks */ 733 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 734 735 ret = spapr_populate_memory(spapr, fdt); 736 if (ret < 0) { 737 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 738 exit(1); 739 } 740 741 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 742 if (ret < 0) { 743 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 744 exit(1); 745 } 746 747 QLIST_FOREACH(phb, &spapr->phbs, list) { 748 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 749 } 750 751 if (ret < 0) { 752 fprintf(stderr, "couldn't setup PCI devices in fdt\n"); 753 exit(1); 754 } 755 756 /* RTAS */ 757 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 758 if (ret < 0) { 759 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 760 } 761 762 /* Advertise NUMA via ibm,associativity */ 763 ret = spapr_fixup_cpu_dt(fdt, spapr); 764 if (ret < 0) { 765 fprintf(stderr, "Couldn't finalize CPU device tree properties\n"); 766 } 767 768 bootlist = get_boot_devices_list(&cb, true); 769 if (cb && bootlist) { 770 int offset = fdt_path_offset(fdt, "/chosen"); 771 if (offset < 0) { 772 exit(1); 773 } 774 for (i = 0; i < cb; i++) { 775 if (bootlist[i] == '\n') { 776 bootlist[i] = ' '; 777 } 778 779 } 780 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); 781 } 782 783 if (boot_device && strlen(boot_device)) { 784 int offset = fdt_path_offset(fdt, "/chosen"); 785 786 if (offset < 0) { 787 exit(1); 788 } 789 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device); 790 } 791 792 if (!spapr->has_graphics) { 793 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 794 } 795 796 _FDT((fdt_pack(fdt))); 797 798 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 799 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 800 fdt_totalsize(fdt), FDT_MAX_SIZE); 801 exit(1); 802 } 803 804 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 805 806 g_free(bootlist); 807 g_free(fdt); 808 } 809 810 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 811 { 812 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 813 } 814 815 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 816 { 817 CPUPPCState *env = &cpu->env; 818 819 if (msr_pr) { 820 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 821 env->gpr[3] = H_PRIVILEGE; 822 } else { 823 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 824 } 825 } 826 827 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 828 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 829 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 830 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 831 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 832 833 static void spapr_reset_htab(sPAPREnvironment *spapr) 834 { 835 long shift; 836 int index; 837 838 /* allocate hash page table. For now we always make this 16mb, 839 * later we should probably make it scale to the size of guest 840 * RAM */ 841 842 shift = kvmppc_reset_htab(spapr->htab_shift); 843 844 if (shift > 0) { 845 /* Kernel handles htab, we don't need to allocate one */ 846 spapr->htab_shift = shift; 847 kvmppc_kern_htab = true; 848 849 /* Tell readers to update their file descriptor */ 850 if (spapr->htab_fd >= 0) { 851 spapr->htab_fd_stale = true; 852 } 853 } else { 854 if (!spapr->htab) { 855 /* Allocate an htab if we don't yet have one */ 856 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); 857 } 858 859 /* And clear it */ 860 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 861 862 for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) { 863 DIRTY_HPTE(HPTE(spapr->htab, index)); 864 } 865 } 866 867 /* Update the RMA size if necessary */ 868 if (spapr->vrma_adjust) { 869 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 870 spapr->htab_shift); 871 } 872 } 873 874 static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 875 { 876 bool matched = false; 877 878 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 879 matched = true; 880 } 881 882 if (!matched) { 883 error_report("Device %s is not supported by this machine yet.", 884 qdev_fw_name(DEVICE(sbdev))); 885 exit(1); 886 } 887 888 return 0; 889 } 890 891 /* 892 * A guest reset will cause spapr->htab_fd to become stale if being used. 893 * Reopen the file descriptor to make sure the whole HTAB is properly read. 894 */ 895 static int spapr_check_htab_fd(sPAPREnvironment *spapr) 896 { 897 int rc = 0; 898 899 if (spapr->htab_fd_stale) { 900 close(spapr->htab_fd); 901 spapr->htab_fd = kvmppc_get_htab_fd(false); 902 if (spapr->htab_fd < 0) { 903 error_report("Unable to open fd for reading hash table from KVM: " 904 "%s", strerror(errno)); 905 rc = -1; 906 } 907 spapr->htab_fd_stale = false; 908 } 909 910 return rc; 911 } 912 913 static void ppc_spapr_reset(void) 914 { 915 PowerPCCPU *first_ppc_cpu; 916 uint32_t rtas_limit; 917 918 /* Check for unknown sysbus devices */ 919 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 920 921 /* Reset the hash table & recalc the RMA */ 922 spapr_reset_htab(spapr); 923 924 qemu_devices_reset(); 925 926 /* 927 * We place the device tree and RTAS just below either the top of the RMA, 928 * or just below 2GB, whichever is lowere, so that it can be 929 * processed with 32-bit real mode code if necessary 930 */ 931 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 932 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 933 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 934 935 /* Load the fdt */ 936 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 937 spapr->rtas_size); 938 939 /* Copy RTAS over */ 940 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob, 941 spapr->rtas_size); 942 943 /* Set up the entry state */ 944 first_ppc_cpu = POWERPC_CPU(first_cpu); 945 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 946 first_ppc_cpu->env.gpr[5] = 0; 947 first_cpu->halted = 0; 948 first_ppc_cpu->env.nip = spapr->entry_point; 949 950 } 951 952 static void spapr_cpu_reset(void *opaque) 953 { 954 PowerPCCPU *cpu = opaque; 955 CPUState *cs = CPU(cpu); 956 CPUPPCState *env = &cpu->env; 957 958 cpu_reset(cs); 959 960 /* All CPUs start halted. CPU0 is unhalted from the machine level 961 * reset code and the rest are explicitly started up by the guest 962 * using an RTAS call */ 963 cs->halted = 1; 964 965 env->spr[SPR_HIOR] = 0; 966 967 env->external_htab = (uint8_t *)spapr->htab; 968 if (kvm_enabled() && !env->external_htab) { 969 /* 970 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte* 971 * functions do the right thing. 972 */ 973 env->external_htab = (void *)1; 974 } 975 env->htab_base = -1; 976 /* 977 * htab_mask is the mask used to normalize hash value to PTEG index. 978 * htab_shift is log2 of hash table size. 979 * We have 8 hpte per group, and each hpte is 16 bytes. 980 * ie have 128 bytes per hpte entry. 981 */ 982 env->htab_mask = (1ULL << ((spapr)->htab_shift - 7)) - 1; 983 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | 984 (spapr->htab_shift - 18); 985 } 986 987 static void spapr_create_nvram(sPAPREnvironment *spapr) 988 { 989 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 990 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 991 992 if (dinfo) { 993 qdev_prop_set_drive_nofail(dev, "drive", blk_by_legacy_dinfo(dinfo)); 994 } 995 996 qdev_init_nofail(dev); 997 998 spapr->nvram = (struct sPAPRNVRAM *)dev; 999 } 1000 1001 static void spapr_rtc_create(sPAPREnvironment *spapr) 1002 { 1003 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); 1004 1005 qdev_init_nofail(dev); 1006 spapr->rtc = dev; 1007 1008 object_property_add_alias(qdev_get_machine(), "rtc-time", 1009 OBJECT(spapr->rtc), "date", NULL); 1010 } 1011 1012 /* Returns whether we want to use VGA or not */ 1013 static int spapr_vga_init(PCIBus *pci_bus) 1014 { 1015 switch (vga_interface_type) { 1016 case VGA_NONE: 1017 return false; 1018 case VGA_DEVICE: 1019 return true; 1020 case VGA_STD: 1021 return pci_vga_init(pci_bus) != NULL; 1022 default: 1023 fprintf(stderr, "This vga model is not supported," 1024 "currently it only supports -vga std\n"); 1025 exit(0); 1026 } 1027 } 1028 1029 static int spapr_post_load(void *opaque, int version_id) 1030 { 1031 sPAPREnvironment *spapr = (sPAPREnvironment *)opaque; 1032 int err = 0; 1033 1034 /* In earlier versions, there was no separate qdev for the PAPR 1035 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1036 * So when migrating from those versions, poke the incoming offset 1037 * value into the RTC device */ 1038 if (version_id < 3) { 1039 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); 1040 } 1041 1042 return err; 1043 } 1044 1045 static bool version_before_3(void *opaque, int version_id) 1046 { 1047 return version_id < 3; 1048 } 1049 1050 static const VMStateDescription vmstate_spapr = { 1051 .name = "spapr", 1052 .version_id = 3, 1053 .minimum_version_id = 1, 1054 .post_load = spapr_post_load, 1055 .fields = (VMStateField[]) { 1056 /* used to be @next_irq */ 1057 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1058 1059 /* RTC offset */ 1060 VMSTATE_UINT64_TEST(rtc_offset, sPAPREnvironment, version_before_3), 1061 1062 VMSTATE_PPC_TIMEBASE_V(tb, sPAPREnvironment, 2), 1063 VMSTATE_END_OF_LIST() 1064 }, 1065 }; 1066 1067 static int htab_save_setup(QEMUFile *f, void *opaque) 1068 { 1069 sPAPREnvironment *spapr = opaque; 1070 1071 /* "Iteration" header */ 1072 qemu_put_be32(f, spapr->htab_shift); 1073 1074 if (spapr->htab) { 1075 spapr->htab_save_index = 0; 1076 spapr->htab_first_pass = true; 1077 } else { 1078 assert(kvm_enabled()); 1079 1080 spapr->htab_fd = kvmppc_get_htab_fd(false); 1081 spapr->htab_fd_stale = false; 1082 if (spapr->htab_fd < 0) { 1083 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", 1084 strerror(errno)); 1085 return -1; 1086 } 1087 } 1088 1089 1090 return 0; 1091 } 1092 1093 static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr, 1094 int64_t max_ns) 1095 { 1096 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1097 int index = spapr->htab_save_index; 1098 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1099 1100 assert(spapr->htab_first_pass); 1101 1102 do { 1103 int chunkstart; 1104 1105 /* Consume invalid HPTEs */ 1106 while ((index < htabslots) 1107 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1108 index++; 1109 CLEAN_HPTE(HPTE(spapr->htab, index)); 1110 } 1111 1112 /* Consume valid HPTEs */ 1113 chunkstart = index; 1114 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1115 && HPTE_VALID(HPTE(spapr->htab, index))) { 1116 index++; 1117 CLEAN_HPTE(HPTE(spapr->htab, index)); 1118 } 1119 1120 if (index > chunkstart) { 1121 int n_valid = index - chunkstart; 1122 1123 qemu_put_be32(f, chunkstart); 1124 qemu_put_be16(f, n_valid); 1125 qemu_put_be16(f, 0); 1126 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1127 HASH_PTE_SIZE_64 * n_valid); 1128 1129 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1130 break; 1131 } 1132 } 1133 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1134 1135 if (index >= htabslots) { 1136 assert(index == htabslots); 1137 index = 0; 1138 spapr->htab_first_pass = false; 1139 } 1140 spapr->htab_save_index = index; 1141 } 1142 1143 static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, 1144 int64_t max_ns) 1145 { 1146 bool final = max_ns < 0; 1147 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1148 int examined = 0, sent = 0; 1149 int index = spapr->htab_save_index; 1150 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1151 1152 assert(!spapr->htab_first_pass); 1153 1154 do { 1155 int chunkstart, invalidstart; 1156 1157 /* Consume non-dirty HPTEs */ 1158 while ((index < htabslots) 1159 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1160 index++; 1161 examined++; 1162 } 1163 1164 chunkstart = index; 1165 /* Consume valid dirty HPTEs */ 1166 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1167 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1168 && HPTE_VALID(HPTE(spapr->htab, index))) { 1169 CLEAN_HPTE(HPTE(spapr->htab, index)); 1170 index++; 1171 examined++; 1172 } 1173 1174 invalidstart = index; 1175 /* Consume invalid dirty HPTEs */ 1176 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1177 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1178 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1179 CLEAN_HPTE(HPTE(spapr->htab, index)); 1180 index++; 1181 examined++; 1182 } 1183 1184 if (index > chunkstart) { 1185 int n_valid = invalidstart - chunkstart; 1186 int n_invalid = index - invalidstart; 1187 1188 qemu_put_be32(f, chunkstart); 1189 qemu_put_be16(f, n_valid); 1190 qemu_put_be16(f, n_invalid); 1191 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1192 HASH_PTE_SIZE_64 * n_valid); 1193 sent += index - chunkstart; 1194 1195 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1196 break; 1197 } 1198 } 1199 1200 if (examined >= htabslots) { 1201 break; 1202 } 1203 1204 if (index >= htabslots) { 1205 assert(index == htabslots); 1206 index = 0; 1207 } 1208 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1209 1210 if (index >= htabslots) { 1211 assert(index == htabslots); 1212 index = 0; 1213 } 1214 1215 spapr->htab_save_index = index; 1216 1217 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1218 } 1219 1220 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1221 #define MAX_KVM_BUF_SIZE 2048 1222 1223 static int htab_save_iterate(QEMUFile *f, void *opaque) 1224 { 1225 sPAPREnvironment *spapr = opaque; 1226 int rc = 0; 1227 1228 /* Iteration header */ 1229 qemu_put_be32(f, 0); 1230 1231 if (!spapr->htab) { 1232 assert(kvm_enabled()); 1233 1234 rc = spapr_check_htab_fd(spapr); 1235 if (rc < 0) { 1236 return rc; 1237 } 1238 1239 rc = kvmppc_save_htab(f, spapr->htab_fd, 1240 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1241 if (rc < 0) { 1242 return rc; 1243 } 1244 } else if (spapr->htab_first_pass) { 1245 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1246 } else { 1247 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1248 } 1249 1250 /* End marker */ 1251 qemu_put_be32(f, 0); 1252 qemu_put_be16(f, 0); 1253 qemu_put_be16(f, 0); 1254 1255 return rc; 1256 } 1257 1258 static int htab_save_complete(QEMUFile *f, void *opaque) 1259 { 1260 sPAPREnvironment *spapr = opaque; 1261 1262 /* Iteration header */ 1263 qemu_put_be32(f, 0); 1264 1265 if (!spapr->htab) { 1266 int rc; 1267 1268 assert(kvm_enabled()); 1269 1270 rc = spapr_check_htab_fd(spapr); 1271 if (rc < 0) { 1272 return rc; 1273 } 1274 1275 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); 1276 if (rc < 0) { 1277 return rc; 1278 } 1279 close(spapr->htab_fd); 1280 spapr->htab_fd = -1; 1281 } else { 1282 htab_save_later_pass(f, spapr, -1); 1283 } 1284 1285 /* End marker */ 1286 qemu_put_be32(f, 0); 1287 qemu_put_be16(f, 0); 1288 qemu_put_be16(f, 0); 1289 1290 return 0; 1291 } 1292 1293 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1294 { 1295 sPAPREnvironment *spapr = opaque; 1296 uint32_t section_hdr; 1297 int fd = -1; 1298 1299 if (version_id < 1 || version_id > 1) { 1300 fprintf(stderr, "htab_load() bad version\n"); 1301 return -EINVAL; 1302 } 1303 1304 section_hdr = qemu_get_be32(f); 1305 1306 if (section_hdr) { 1307 /* First section, just the hash shift */ 1308 if (spapr->htab_shift != section_hdr) { 1309 return -EINVAL; 1310 } 1311 return 0; 1312 } 1313 1314 if (!spapr->htab) { 1315 assert(kvm_enabled()); 1316 1317 fd = kvmppc_get_htab_fd(true); 1318 if (fd < 0) { 1319 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", 1320 strerror(errno)); 1321 } 1322 } 1323 1324 while (true) { 1325 uint32_t index; 1326 uint16_t n_valid, n_invalid; 1327 1328 index = qemu_get_be32(f); 1329 n_valid = qemu_get_be16(f); 1330 n_invalid = qemu_get_be16(f); 1331 1332 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1333 /* End of Stream */ 1334 break; 1335 } 1336 1337 if ((index + n_valid + n_invalid) > 1338 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1339 /* Bad index in stream */ 1340 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " 1341 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, 1342 spapr->htab_shift); 1343 return -EINVAL; 1344 } 1345 1346 if (spapr->htab) { 1347 if (n_valid) { 1348 qemu_get_buffer(f, HPTE(spapr->htab, index), 1349 HASH_PTE_SIZE_64 * n_valid); 1350 } 1351 if (n_invalid) { 1352 memset(HPTE(spapr->htab, index + n_valid), 0, 1353 HASH_PTE_SIZE_64 * n_invalid); 1354 } 1355 } else { 1356 int rc; 1357 1358 assert(fd >= 0); 1359 1360 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1361 if (rc < 0) { 1362 return rc; 1363 } 1364 } 1365 } 1366 1367 if (!spapr->htab) { 1368 assert(fd >= 0); 1369 close(fd); 1370 } 1371 1372 return 0; 1373 } 1374 1375 static SaveVMHandlers savevm_htab_handlers = { 1376 .save_live_setup = htab_save_setup, 1377 .save_live_iterate = htab_save_iterate, 1378 .save_live_complete = htab_save_complete, 1379 .load_state = htab_load, 1380 }; 1381 1382 static void spapr_boot_set(void *opaque, const char *boot_device, 1383 Error **errp) 1384 { 1385 MachineState *machine = MACHINE(qdev_get_machine()); 1386 machine->boot_order = g_strdup(boot_device); 1387 } 1388 1389 /* pSeries LPAR / sPAPR hardware init */ 1390 static void ppc_spapr_init(MachineState *machine) 1391 { 1392 ram_addr_t ram_size = machine->ram_size; 1393 const char *cpu_model = machine->cpu_model; 1394 const char *kernel_filename = machine->kernel_filename; 1395 const char *kernel_cmdline = machine->kernel_cmdline; 1396 const char *initrd_filename = machine->initrd_filename; 1397 PowerPCCPU *cpu; 1398 CPUPPCState *env; 1399 PCIHostState *phb; 1400 int i; 1401 MemoryRegion *sysmem = get_system_memory(); 1402 MemoryRegion *ram = g_new(MemoryRegion, 1); 1403 MemoryRegion *rma_region; 1404 void *rma = NULL; 1405 hwaddr rma_alloc_size; 1406 hwaddr node0_size = spapr_node0_size(); 1407 uint32_t initrd_base = 0; 1408 long kernel_size = 0, initrd_size = 0; 1409 long load_limit, fw_size; 1410 bool kernel_le = false; 1411 char *filename; 1412 1413 msi_supported = true; 1414 1415 spapr = g_malloc0(sizeof(*spapr)); 1416 QLIST_INIT(&spapr->phbs); 1417 1418 cpu_ppc_hypercall = emulate_spapr_hypercall; 1419 1420 /* Allocate RMA if necessary */ 1421 rma_alloc_size = kvmppc_alloc_rma(&rma); 1422 1423 if (rma_alloc_size == -1) { 1424 error_report("Unable to create RMA"); 1425 exit(1); 1426 } 1427 1428 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1429 spapr->rma_size = rma_alloc_size; 1430 } else { 1431 spapr->rma_size = node0_size; 1432 1433 /* With KVM, we don't actually know whether KVM supports an 1434 * unbounded RMA (PR KVM) or is limited by the hash table size 1435 * (HV KVM using VRMA), so we always assume the latter 1436 * 1437 * In that case, we also limit the initial allocations for RTAS 1438 * etc... to 256M since we have no way to know what the VRMA size 1439 * is going to be as it depends on the size of the hash table 1440 * isn't determined yet. 1441 */ 1442 if (kvm_enabled()) { 1443 spapr->vrma_adjust = 1; 1444 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1445 } 1446 } 1447 1448 if (spapr->rma_size > node0_size) { 1449 fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n", 1450 spapr->rma_size); 1451 exit(1); 1452 } 1453 1454 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 1455 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 1456 1457 /* We aim for a hash table of size 1/128 the size of RAM. The 1458 * normal rule of thumb is 1/64 the size of RAM, but that's much 1459 * more than needed for the Linux guests we support. */ 1460 spapr->htab_shift = 18; /* Minimum architected size */ 1461 while (spapr->htab_shift <= 46) { 1462 if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) { 1463 break; 1464 } 1465 spapr->htab_shift++; 1466 } 1467 1468 /* Set up Interrupt Controller before we create the VCPUs */ 1469 spapr->icp = xics_system_init(machine, 1470 smp_cpus * kvmppc_smt_threads() / smp_threads, 1471 XICS_IRQS); 1472 1473 /* init CPUs */ 1474 if (cpu_model == NULL) { 1475 cpu_model = kvm_enabled() ? "host" : "POWER7"; 1476 } 1477 for (i = 0; i < smp_cpus; i++) { 1478 cpu = cpu_ppc_init(cpu_model); 1479 if (cpu == NULL) { 1480 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 1481 exit(1); 1482 } 1483 env = &cpu->env; 1484 1485 /* Set time-base frequency to 512 MHz */ 1486 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 1487 1488 /* PAPR always has exception vectors in RAM not ROM. To ensure this, 1489 * MSR[IP] should never be set. 1490 */ 1491 env->msr_mask &= ~(1 << 6); 1492 1493 /* Tell KVM that we're in PAPR mode */ 1494 if (kvm_enabled()) { 1495 kvmppc_set_papr(cpu); 1496 } 1497 1498 if (cpu->max_compat) { 1499 if (ppc_set_compat(cpu, cpu->max_compat) < 0) { 1500 exit(1); 1501 } 1502 } 1503 1504 xics_cpu_setup(spapr->icp, cpu); 1505 1506 qemu_register_reset(spapr_cpu_reset, cpu); 1507 } 1508 1509 if (kvm_enabled()) { 1510 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 1511 kvmppc_enable_logical_ci_hcalls(); 1512 } 1513 1514 /* allocate RAM */ 1515 spapr->ram_limit = ram_size; 1516 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 1517 spapr->ram_limit); 1518 memory_region_add_subregion(sysmem, 0, ram); 1519 1520 if (rma_alloc_size && rma) { 1521 rma_region = g_new(MemoryRegion, 1); 1522 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 1523 rma_alloc_size, rma); 1524 vmstate_register_ram_global(rma_region); 1525 memory_region_add_subregion(sysmem, 0, rma_region); 1526 } 1527 1528 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1529 if (!filename) { 1530 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 1531 exit(1); 1532 } 1533 spapr->rtas_size = get_image_size(filename); 1534 spapr->rtas_blob = g_malloc(spapr->rtas_size); 1535 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 1536 error_report("Could not load LPAR rtas '%s'", filename); 1537 exit(1); 1538 } 1539 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1540 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 1541 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 1542 exit(1); 1543 } 1544 g_free(filename); 1545 1546 /* Set up EPOW events infrastructure */ 1547 spapr_events_init(spapr); 1548 1549 /* Set up the RTC RTAS interfaces */ 1550 spapr_rtc_create(spapr); 1551 1552 /* Set up VIO bus */ 1553 spapr->vio_bus = spapr_vio_bus_init(); 1554 1555 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1556 if (serial_hds[i]) { 1557 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1558 } 1559 } 1560 1561 /* We always have at least the nvram device on VIO */ 1562 spapr_create_nvram(spapr); 1563 1564 /* Set up PCI */ 1565 spapr_pci_rtas_init(); 1566 1567 phb = spapr_create_phb(spapr, 0); 1568 1569 for (i = 0; i < nb_nics; i++) { 1570 NICInfo *nd = &nd_table[i]; 1571 1572 if (!nd->model) { 1573 nd->model = g_strdup("ibmveth"); 1574 } 1575 1576 if (strcmp(nd->model, "ibmveth") == 0) { 1577 spapr_vlan_create(spapr->vio_bus, nd); 1578 } else { 1579 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1580 } 1581 } 1582 1583 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1584 spapr_vscsi_create(spapr->vio_bus); 1585 } 1586 1587 /* Graphics */ 1588 if (spapr_vga_init(phb->bus)) { 1589 spapr->has_graphics = true; 1590 machine->usb |= defaults_enabled() && !machine->usb_disabled; 1591 } 1592 1593 if (machine->usb) { 1594 pci_create_simple(phb->bus, -1, "pci-ohci"); 1595 1596 if (spapr->has_graphics) { 1597 USBBus *usb_bus = usb_bus_find(-1); 1598 1599 usb_create_simple(usb_bus, "usb-kbd"); 1600 usb_create_simple(usb_bus, "usb-mouse"); 1601 } 1602 } 1603 1604 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1605 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " 1606 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); 1607 exit(1); 1608 } 1609 1610 if (kernel_filename) { 1611 uint64_t lowaddr = 0; 1612 1613 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1614 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); 1615 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { 1616 kernel_size = load_elf(kernel_filename, 1617 translate_kernel_address, NULL, 1618 NULL, &lowaddr, NULL, 0, ELF_MACHINE, 0); 1619 kernel_le = kernel_size > 0; 1620 } 1621 if (kernel_size < 0) { 1622 fprintf(stderr, "qemu: error loading %s: %s\n", 1623 kernel_filename, load_elf_strerror(kernel_size)); 1624 exit(1); 1625 } 1626 1627 /* load initrd */ 1628 if (initrd_filename) { 1629 /* Try to locate the initrd in the gap between the kernel 1630 * and the firmware. Add a bit of space just in case 1631 */ 1632 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1633 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1634 load_limit - initrd_base); 1635 if (initrd_size < 0) { 1636 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 1637 initrd_filename); 1638 exit(1); 1639 } 1640 } else { 1641 initrd_base = 0; 1642 initrd_size = 0; 1643 } 1644 } 1645 1646 if (bios_name == NULL) { 1647 bios_name = FW_FILE_NAME; 1648 } 1649 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1650 if (!filename) { 1651 error_report("Could not find LPAR firmware '%s'", bios_name); 1652 exit(1); 1653 } 1654 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 1655 if (fw_size <= 0) { 1656 error_report("Could not load LPAR firmware '%s'", filename); 1657 exit(1); 1658 } 1659 g_free(filename); 1660 1661 spapr->entry_point = 0x100; 1662 1663 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 1664 register_savevm_live(NULL, "spapr/htab", -1, 1, 1665 &savevm_htab_handlers, spapr); 1666 1667 /* Prepare the device tree */ 1668 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 1669 kernel_size, kernel_le, 1670 kernel_cmdline, 1671 spapr->check_exception_irq); 1672 assert(spapr->fdt_skel != NULL); 1673 1674 /* used by RTAS */ 1675 QTAILQ_INIT(&spapr->ccs_list); 1676 qemu_register_reset(spapr_ccs_reset_hook, spapr); 1677 1678 qemu_register_boot_set(spapr_boot_set, spapr); 1679 } 1680 1681 static int spapr_kvm_type(const char *vm_type) 1682 { 1683 if (!vm_type) { 1684 return 0; 1685 } 1686 1687 if (!strcmp(vm_type, "HV")) { 1688 return 1; 1689 } 1690 1691 if (!strcmp(vm_type, "PR")) { 1692 return 2; 1693 } 1694 1695 error_report("Unknown kvm-type specified '%s'", vm_type); 1696 exit(1); 1697 } 1698 1699 /* 1700 * Implementation of an interface to adjust firmware path 1701 * for the bootindex property handling. 1702 */ 1703 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 1704 DeviceState *dev) 1705 { 1706 #define CAST(type, obj, name) \ 1707 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 1708 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 1709 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 1710 1711 if (d) { 1712 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 1713 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 1714 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 1715 1716 if (spapr) { 1717 /* 1718 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 1719 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 1720 * in the top 16 bits of the 64-bit LUN 1721 */ 1722 unsigned id = 0x8000 | (d->id << 8) | d->lun; 1723 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1724 (uint64_t)id << 48); 1725 } else if (virtio) { 1726 /* 1727 * We use SRP luns of the form 01000000 | (target << 8) | lun 1728 * in the top 32 bits of the 64-bit LUN 1729 * Note: the quote above is from SLOF and it is wrong, 1730 * the actual binding is: 1731 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 1732 */ 1733 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 1734 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1735 (uint64_t)id << 32); 1736 } else if (usb) { 1737 /* 1738 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 1739 * in the top 32 bits of the 64-bit LUN 1740 */ 1741 unsigned usb_port = atoi(usb->port->path); 1742 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 1743 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1744 (uint64_t)id << 32); 1745 } 1746 } 1747 1748 if (phb) { 1749 /* Replace "pci" with "pci@800000020000000" */ 1750 return g_strdup_printf("pci@%"PRIX64, phb->buid); 1751 } 1752 1753 return NULL; 1754 } 1755 1756 static char *spapr_get_kvm_type(Object *obj, Error **errp) 1757 { 1758 sPAPRMachineState *sm = SPAPR_MACHINE(obj); 1759 1760 return g_strdup(sm->kvm_type); 1761 } 1762 1763 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 1764 { 1765 sPAPRMachineState *sm = SPAPR_MACHINE(obj); 1766 1767 g_free(sm->kvm_type); 1768 sm->kvm_type = g_strdup(value); 1769 } 1770 1771 static void spapr_machine_initfn(Object *obj) 1772 { 1773 object_property_add_str(obj, "kvm-type", 1774 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 1775 object_property_set_description(obj, "kvm-type", 1776 "Specifies the KVM virtualization mode (HV, PR)", 1777 NULL); 1778 } 1779 1780 static void ppc_cpu_do_nmi_on_cpu(void *arg) 1781 { 1782 CPUState *cs = arg; 1783 1784 cpu_synchronize_state(cs); 1785 ppc_cpu_do_system_reset(cs); 1786 } 1787 1788 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 1789 { 1790 CPUState *cs; 1791 1792 CPU_FOREACH(cs) { 1793 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs); 1794 } 1795 } 1796 1797 static void spapr_machine_class_init(ObjectClass *oc, void *data) 1798 { 1799 MachineClass *mc = MACHINE_CLASS(oc); 1800 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 1801 NMIClass *nc = NMI_CLASS(oc); 1802 1803 mc->init = ppc_spapr_init; 1804 mc->reset = ppc_spapr_reset; 1805 mc->block_default_type = IF_SCSI; 1806 mc->max_cpus = MAX_CPUS; 1807 mc->no_parallel = 1; 1808 mc->default_boot_order = ""; 1809 mc->default_ram_size = 512 * M_BYTE; 1810 mc->kvm_type = spapr_kvm_type; 1811 mc->has_dynamic_sysbus = true; 1812 1813 fwc->get_dev_path = spapr_get_fw_dev_path; 1814 nc->nmi_monitor_handler = spapr_nmi; 1815 } 1816 1817 static const TypeInfo spapr_machine_info = { 1818 .name = TYPE_SPAPR_MACHINE, 1819 .parent = TYPE_MACHINE, 1820 .abstract = true, 1821 .instance_size = sizeof(sPAPRMachineState), 1822 .instance_init = spapr_machine_initfn, 1823 .class_init = spapr_machine_class_init, 1824 .interfaces = (InterfaceInfo[]) { 1825 { TYPE_FW_PATH_PROVIDER }, 1826 { TYPE_NMI }, 1827 { } 1828 }, 1829 }; 1830 1831 #define SPAPR_COMPAT_2_3 \ 1832 HW_COMPAT_2_3 \ 1833 {\ 1834 .driver = "spapr-pci-host-bridge",\ 1835 .property = "dynamic-reconfiguration",\ 1836 .value = "off",\ 1837 }, 1838 1839 #define SPAPR_COMPAT_2_2 \ 1840 SPAPR_COMPAT_2_3 \ 1841 HW_COMPAT_2_2 \ 1842 {\ 1843 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 1844 .property = "mem_win_size",\ 1845 .value = "0x20000000",\ 1846 }, 1847 1848 #define SPAPR_COMPAT_2_1 \ 1849 SPAPR_COMPAT_2_2 \ 1850 HW_COMPAT_2_1 1851 1852 static void spapr_compat_2_3(Object *obj) 1853 { 1854 } 1855 1856 static void spapr_compat_2_2(Object *obj) 1857 { 1858 spapr_compat_2_3(obj); 1859 } 1860 1861 static void spapr_compat_2_1(Object *obj) 1862 { 1863 spapr_compat_2_2(obj); 1864 } 1865 1866 static void spapr_machine_2_3_instance_init(Object *obj) 1867 { 1868 spapr_compat_2_3(obj); 1869 spapr_machine_initfn(obj); 1870 } 1871 1872 static void spapr_machine_2_2_instance_init(Object *obj) 1873 { 1874 spapr_compat_2_2(obj); 1875 spapr_machine_initfn(obj); 1876 } 1877 1878 static void spapr_machine_2_1_instance_init(Object *obj) 1879 { 1880 spapr_compat_2_1(obj); 1881 spapr_machine_initfn(obj); 1882 } 1883 1884 static void spapr_machine_2_1_class_init(ObjectClass *oc, void *data) 1885 { 1886 MachineClass *mc = MACHINE_CLASS(oc); 1887 static GlobalProperty compat_props[] = { 1888 SPAPR_COMPAT_2_1 1889 { /* end of list */ } 1890 }; 1891 1892 mc->name = "pseries-2.1"; 1893 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.1"; 1894 mc->compat_props = compat_props; 1895 } 1896 1897 static const TypeInfo spapr_machine_2_1_info = { 1898 .name = TYPE_SPAPR_MACHINE "2.1", 1899 .parent = TYPE_SPAPR_MACHINE, 1900 .class_init = spapr_machine_2_1_class_init, 1901 .instance_init = spapr_machine_2_1_instance_init, 1902 }; 1903 1904 static void spapr_machine_2_2_class_init(ObjectClass *oc, void *data) 1905 { 1906 static GlobalProperty compat_props[] = { 1907 SPAPR_COMPAT_2_2 1908 { /* end of list */ } 1909 }; 1910 MachineClass *mc = MACHINE_CLASS(oc); 1911 1912 mc->name = "pseries-2.2"; 1913 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.2"; 1914 mc->compat_props = compat_props; 1915 } 1916 1917 static const TypeInfo spapr_machine_2_2_info = { 1918 .name = TYPE_SPAPR_MACHINE "2.2", 1919 .parent = TYPE_SPAPR_MACHINE, 1920 .class_init = spapr_machine_2_2_class_init, 1921 .instance_init = spapr_machine_2_2_instance_init, 1922 }; 1923 1924 static void spapr_machine_2_3_class_init(ObjectClass *oc, void *data) 1925 { 1926 static GlobalProperty compat_props[] = { 1927 SPAPR_COMPAT_2_3 1928 { /* end of list */ } 1929 }; 1930 MachineClass *mc = MACHINE_CLASS(oc); 1931 1932 mc->name = "pseries-2.3"; 1933 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.3"; 1934 mc->compat_props = compat_props; 1935 } 1936 1937 static const TypeInfo spapr_machine_2_3_info = { 1938 .name = TYPE_SPAPR_MACHINE "2.3", 1939 .parent = TYPE_SPAPR_MACHINE, 1940 .class_init = spapr_machine_2_3_class_init, 1941 .instance_init = spapr_machine_2_3_instance_init, 1942 }; 1943 1944 static void spapr_machine_2_4_class_init(ObjectClass *oc, void *data) 1945 { 1946 MachineClass *mc = MACHINE_CLASS(oc); 1947 1948 mc->name = "pseries-2.4"; 1949 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.4"; 1950 mc->alias = "pseries"; 1951 mc->is_default = 1; 1952 } 1953 1954 static const TypeInfo spapr_machine_2_4_info = { 1955 .name = TYPE_SPAPR_MACHINE "2.4", 1956 .parent = TYPE_SPAPR_MACHINE, 1957 .class_init = spapr_machine_2_4_class_init, 1958 }; 1959 1960 static void spapr_machine_register_types(void) 1961 { 1962 type_register_static(&spapr_machine_info); 1963 type_register_static(&spapr_machine_2_1_info); 1964 type_register_static(&spapr_machine_2_2_info); 1965 type_register_static(&spapr_machine_2_3_info); 1966 type_register_static(&spapr_machine_2_4_info); 1967 } 1968 1969 type_init(spapr_machine_register_types) 1970