1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/numa.h" 32 #include "hw/hw.h" 33 #include "qemu/log.h" 34 #include "hw/fw-path-provider.h" 35 #include "elf.h" 36 #include "net/net.h" 37 #include "sysemu/device_tree.h" 38 #include "sysemu/block-backend.h" 39 #include "sysemu/cpus.h" 40 #include "sysemu/hw_accel.h" 41 #include "kvm_ppc.h" 42 #include "migration/misc.h" 43 #include "migration/global_state.h" 44 #include "migration/register.h" 45 #include "mmu-hash64.h" 46 #include "mmu-book3s-v3.h" 47 #include "cpu-models.h" 48 #include "qom/cpu.h" 49 50 #include "hw/boards.h" 51 #include "hw/ppc/ppc.h" 52 #include "hw/loader.h" 53 54 #include "hw/ppc/fdt.h" 55 #include "hw/ppc/spapr.h" 56 #include "hw/ppc/spapr_vio.h" 57 #include "hw/pci-host/spapr.h" 58 #include "hw/ppc/xics.h" 59 #include "hw/pci/msi.h" 60 61 #include "hw/pci/pci.h" 62 #include "hw/scsi/scsi.h" 63 #include "hw/virtio/virtio-scsi.h" 64 #include "hw/virtio/vhost-scsi-common.h" 65 66 #include "exec/address-spaces.h" 67 #include "hw/usb.h" 68 #include "qemu/config-file.h" 69 #include "qemu/error-report.h" 70 #include "trace.h" 71 #include "hw/nmi.h" 72 #include "hw/intc/intc.h" 73 74 #include "hw/compat.h" 75 #include "qemu/cutils.h" 76 #include "hw/ppc/spapr_cpu_core.h" 77 78 #include <libfdt.h> 79 80 /* SLOF memory layout: 81 * 82 * SLOF raw image loaded at 0, copies its romfs right below the flat 83 * device-tree, then position SLOF itself 31M below that 84 * 85 * So we set FW_OVERHEAD to 40MB which should account for all of that 86 * and more 87 * 88 * We load our kernel at 4M, leaving space for SLOF initial image 89 */ 90 #define FDT_MAX_SIZE 0x100000 91 #define RTAS_MAX_SIZE 0x10000 92 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 93 #define FW_MAX_SIZE 0x400000 94 #define FW_FILE_NAME "slof.bin" 95 #define FW_OVERHEAD 0x2800000 96 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 97 98 #define MIN_RMA_SLOF 128UL 99 100 #define PHANDLE_XICP 0x00001111 101 102 /* These two functions implement the VCPU id numbering: one to compute them 103 * all and one to identify thread 0 of a VCORE. Any change to the first one 104 * is likely to have an impact on the second one, so let's keep them close. 105 */ 106 static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index) 107 { 108 assert(spapr->vsmt); 109 return 110 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 111 } 112 static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr, 113 PowerPCCPU *cpu) 114 { 115 assert(spapr->vsmt); 116 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 117 } 118 119 static ICSState *spapr_ics_create(sPAPRMachineState *spapr, 120 const char *type_ics, 121 int nr_irqs, Error **errp) 122 { 123 Error *local_err = NULL; 124 Object *obj; 125 126 obj = object_new(type_ics); 127 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); 128 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), 129 &error_abort); 130 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); 131 if (local_err) { 132 goto error; 133 } 134 object_property_set_bool(obj, true, "realized", &local_err); 135 if (local_err) { 136 goto error; 137 } 138 139 return ICS_SIMPLE(obj); 140 141 error: 142 error_propagate(errp, local_err); 143 return NULL; 144 } 145 146 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 147 { 148 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 149 * and newer QEMUs don't even have them. In both cases, we don't want 150 * to send anything on the wire. 151 */ 152 return false; 153 } 154 155 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 156 .name = "icp/server", 157 .version_id = 1, 158 .minimum_version_id = 1, 159 .needed = pre_2_10_vmstate_dummy_icp_needed, 160 .fields = (VMStateField[]) { 161 VMSTATE_UNUSED(4), /* uint32_t xirr */ 162 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 163 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 164 VMSTATE_END_OF_LIST() 165 }, 166 }; 167 168 static void pre_2_10_vmstate_register_dummy_icp(int i) 169 { 170 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 171 (void *)(uintptr_t) i); 172 } 173 174 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 175 { 176 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 177 (void *)(uintptr_t) i); 178 } 179 180 static int xics_max_server_number(sPAPRMachineState *spapr) 181 { 182 assert(spapr->vsmt); 183 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads); 184 } 185 186 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) 187 { 188 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 189 190 if (kvm_enabled()) { 191 if (machine_kernel_irqchip_allowed(machine) && 192 !xics_kvm_init(spapr, errp)) { 193 spapr->icp_type = TYPE_KVM_ICP; 194 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp); 195 } 196 if (machine_kernel_irqchip_required(machine) && !spapr->ics) { 197 error_prepend(errp, "kernel_irqchip requested but unavailable: "); 198 return; 199 } 200 } 201 202 if (!spapr->ics) { 203 xics_spapr_init(spapr); 204 spapr->icp_type = TYPE_ICP; 205 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp); 206 if (!spapr->ics) { 207 return; 208 } 209 } 210 } 211 212 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 213 int smt_threads) 214 { 215 int i, ret = 0; 216 uint32_t servers_prop[smt_threads]; 217 uint32_t gservers_prop[smt_threads * 2]; 218 int index = spapr_get_vcpu_id(cpu); 219 220 if (cpu->compat_pvr) { 221 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 222 if (ret < 0) { 223 return ret; 224 } 225 } 226 227 /* Build interrupt servers and gservers properties */ 228 for (i = 0; i < smt_threads; i++) { 229 servers_prop[i] = cpu_to_be32(index + i); 230 /* Hack, direct the group queues back to cpu 0 */ 231 gservers_prop[i*2] = cpu_to_be32(index + i); 232 gservers_prop[i*2 + 1] = 0; 233 } 234 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 235 servers_prop, sizeof(servers_prop)); 236 if (ret < 0) { 237 return ret; 238 } 239 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 240 gservers_prop, sizeof(gservers_prop)); 241 242 return ret; 243 } 244 245 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 246 { 247 int index = spapr_get_vcpu_id(cpu); 248 uint32_t associativity[] = {cpu_to_be32(0x5), 249 cpu_to_be32(0x0), 250 cpu_to_be32(0x0), 251 cpu_to_be32(0x0), 252 cpu_to_be32(cpu->node_id), 253 cpu_to_be32(index)}; 254 255 /* Advertise NUMA via ibm,associativity */ 256 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 257 sizeof(associativity)); 258 } 259 260 /* Populate the "ibm,pa-features" property */ 261 static void spapr_populate_pa_features(sPAPRMachineState *spapr, 262 PowerPCCPU *cpu, 263 void *fdt, int offset, 264 bool legacy_guest) 265 { 266 uint8_t pa_features_206[] = { 6, 0, 267 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 268 uint8_t pa_features_207[] = { 24, 0, 269 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 270 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 271 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 272 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 273 uint8_t pa_features_300[] = { 66, 0, 274 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 275 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 276 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 277 /* 6: DS207 */ 278 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 279 /* 16: Vector */ 280 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 281 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 282 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 283 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 284 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 285 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 286 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 287 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 288 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 289 /* 42: PM, 44: PC RA, 46: SC vec'd */ 290 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 291 /* 48: SIMD, 50: QP BFP, 52: String */ 292 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 293 /* 54: DecFP, 56: DecI, 58: SHA */ 294 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 295 /* 60: NM atomic, 62: RNG */ 296 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 297 }; 298 uint8_t *pa_features = NULL; 299 size_t pa_size; 300 301 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 302 pa_features = pa_features_206; 303 pa_size = sizeof(pa_features_206); 304 } 305 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 306 pa_features = pa_features_207; 307 pa_size = sizeof(pa_features_207); 308 } 309 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 310 pa_features = pa_features_300; 311 pa_size = sizeof(pa_features_300); 312 } 313 if (!pa_features) { 314 return; 315 } 316 317 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 318 /* 319 * Note: we keep CI large pages off by default because a 64K capable 320 * guest provisioned with large pages might otherwise try to map a qemu 321 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 322 * even if that qemu runs on a 4k host. 323 * We dd this bit back here if we are confident this is not an issue 324 */ 325 pa_features[3] |= 0x20; 326 } 327 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 328 pa_features[24] |= 0x80; /* Transactional memory support */ 329 } 330 if (legacy_guest && pa_size > 40) { 331 /* Workaround for broken kernels that attempt (guest) radix 332 * mode when they can't handle it, if they see the radix bit set 333 * in pa-features. So hide it from them. */ 334 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 335 } 336 337 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 338 } 339 340 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 341 { 342 int ret = 0, offset, cpus_offset; 343 CPUState *cs; 344 char cpu_model[32]; 345 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 346 347 CPU_FOREACH(cs) { 348 PowerPCCPU *cpu = POWERPC_CPU(cs); 349 DeviceClass *dc = DEVICE_GET_CLASS(cs); 350 int index = spapr_get_vcpu_id(cpu); 351 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 352 353 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 354 continue; 355 } 356 357 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 358 359 cpus_offset = fdt_path_offset(fdt, "/cpus"); 360 if (cpus_offset < 0) { 361 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 362 if (cpus_offset < 0) { 363 return cpus_offset; 364 } 365 } 366 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 367 if (offset < 0) { 368 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 369 if (offset < 0) { 370 return offset; 371 } 372 } 373 374 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 375 pft_size_prop, sizeof(pft_size_prop)); 376 if (ret < 0) { 377 return ret; 378 } 379 380 if (nb_numa_nodes > 1) { 381 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 382 if (ret < 0) { 383 return ret; 384 } 385 } 386 387 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 388 if (ret < 0) { 389 return ret; 390 } 391 392 spapr_populate_pa_features(spapr, cpu, fdt, offset, 393 spapr->cas_legacy_guest_workaround); 394 } 395 return ret; 396 } 397 398 static hwaddr spapr_node0_size(MachineState *machine) 399 { 400 if (nb_numa_nodes) { 401 int i; 402 for (i = 0; i < nb_numa_nodes; ++i) { 403 if (numa_info[i].node_mem) { 404 return MIN(pow2floor(numa_info[i].node_mem), 405 machine->ram_size); 406 } 407 } 408 } 409 return machine->ram_size; 410 } 411 412 static void add_str(GString *s, const gchar *s1) 413 { 414 g_string_append_len(s, s1, strlen(s1) + 1); 415 } 416 417 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 418 hwaddr size) 419 { 420 uint32_t associativity[] = { 421 cpu_to_be32(0x4), /* length */ 422 cpu_to_be32(0x0), cpu_to_be32(0x0), 423 cpu_to_be32(0x0), cpu_to_be32(nodeid) 424 }; 425 char mem_name[32]; 426 uint64_t mem_reg_property[2]; 427 int off; 428 429 mem_reg_property[0] = cpu_to_be64(start); 430 mem_reg_property[1] = cpu_to_be64(size); 431 432 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 433 off = fdt_add_subnode(fdt, 0, mem_name); 434 _FDT(off); 435 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 436 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 437 sizeof(mem_reg_property)))); 438 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 439 sizeof(associativity)))); 440 return off; 441 } 442 443 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 444 { 445 MachineState *machine = MACHINE(spapr); 446 hwaddr mem_start, node_size; 447 int i, nb_nodes = nb_numa_nodes; 448 NodeInfo *nodes = numa_info; 449 NodeInfo ramnode; 450 451 /* No NUMA nodes, assume there is just one node with whole RAM */ 452 if (!nb_numa_nodes) { 453 nb_nodes = 1; 454 ramnode.node_mem = machine->ram_size; 455 nodes = &ramnode; 456 } 457 458 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 459 if (!nodes[i].node_mem) { 460 continue; 461 } 462 if (mem_start >= machine->ram_size) { 463 node_size = 0; 464 } else { 465 node_size = nodes[i].node_mem; 466 if (node_size > machine->ram_size - mem_start) { 467 node_size = machine->ram_size - mem_start; 468 } 469 } 470 if (!mem_start) { 471 /* spapr_machine_init() checks for rma_size <= node0_size 472 * already */ 473 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 474 mem_start += spapr->rma_size; 475 node_size -= spapr->rma_size; 476 } 477 for ( ; node_size; ) { 478 hwaddr sizetmp = pow2floor(node_size); 479 480 /* mem_start != 0 here */ 481 if (ctzl(mem_start) < ctzl(sizetmp)) { 482 sizetmp = 1ULL << ctzl(mem_start); 483 } 484 485 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 486 node_size -= sizetmp; 487 mem_start += sizetmp; 488 } 489 } 490 491 return 0; 492 } 493 494 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 495 sPAPRMachineState *spapr) 496 { 497 PowerPCCPU *cpu = POWERPC_CPU(cs); 498 CPUPPCState *env = &cpu->env; 499 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 500 int index = spapr_get_vcpu_id(cpu); 501 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 502 0xffffffff, 0xffffffff}; 503 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 504 : SPAPR_TIMEBASE_FREQ; 505 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 506 uint32_t page_sizes_prop[64]; 507 size_t page_sizes_prop_size; 508 uint32_t vcpus_per_socket = smp_threads * smp_cores; 509 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 510 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 511 sPAPRDRConnector *drc; 512 int drc_index; 513 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 514 int i; 515 516 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 517 if (drc) { 518 drc_index = spapr_drc_index(drc); 519 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 520 } 521 522 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 523 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 524 525 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 526 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 527 env->dcache_line_size))); 528 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 529 env->dcache_line_size))); 530 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 531 env->icache_line_size))); 532 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 533 env->icache_line_size))); 534 535 if (pcc->l1_dcache_size) { 536 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 537 pcc->l1_dcache_size))); 538 } else { 539 warn_report("Unknown L1 dcache size for cpu"); 540 } 541 if (pcc->l1_icache_size) { 542 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 543 pcc->l1_icache_size))); 544 } else { 545 warn_report("Unknown L1 icache size for cpu"); 546 } 547 548 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 549 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 550 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 551 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 552 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 553 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 554 555 if (env->spr_cb[SPR_PURR].oea_read) { 556 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 557 } 558 559 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 560 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 561 segs, sizeof(segs)))); 562 } 563 564 /* Advertise VSX (vector extensions) if available 565 * 1 == VMX / Altivec available 566 * 2 == VSX available 567 * 568 * Only CPUs for which we create core types in spapr_cpu_core.c 569 * are possible, and all of those have VMX */ 570 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 571 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 572 } else { 573 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 574 } 575 576 /* Advertise DFP (Decimal Floating Point) if available 577 * 0 / no property == no DFP 578 * 1 == DFP available */ 579 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 580 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 581 } 582 583 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 584 sizeof(page_sizes_prop)); 585 if (page_sizes_prop_size) { 586 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 587 page_sizes_prop, page_sizes_prop_size))); 588 } 589 590 spapr_populate_pa_features(spapr, cpu, fdt, offset, false); 591 592 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 593 cs->cpu_index / vcpus_per_socket))); 594 595 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 596 pft_size_prop, sizeof(pft_size_prop)))); 597 598 if (nb_numa_nodes > 1) { 599 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 600 } 601 602 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 603 604 if (pcc->radix_page_info) { 605 for (i = 0; i < pcc->radix_page_info->count; i++) { 606 radix_AP_encodings[i] = 607 cpu_to_be32(pcc->radix_page_info->entries[i]); 608 } 609 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 610 radix_AP_encodings, 611 pcc->radix_page_info->count * 612 sizeof(radix_AP_encodings[0])))); 613 } 614 } 615 616 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 617 { 618 CPUState *cs; 619 int cpus_offset; 620 char *nodename; 621 622 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 623 _FDT(cpus_offset); 624 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 625 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 626 627 /* 628 * We walk the CPUs in reverse order to ensure that CPU DT nodes 629 * created by fdt_add_subnode() end up in the right order in FDT 630 * for the guest kernel the enumerate the CPUs correctly. 631 */ 632 CPU_FOREACH_REVERSE(cs) { 633 PowerPCCPU *cpu = POWERPC_CPU(cs); 634 int index = spapr_get_vcpu_id(cpu); 635 DeviceClass *dc = DEVICE_GET_CLASS(cs); 636 int offset; 637 638 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 639 continue; 640 } 641 642 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 643 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 644 g_free(nodename); 645 _FDT(offset); 646 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 647 } 648 649 } 650 651 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 652 { 653 MemoryDeviceInfoList *info; 654 655 for (info = list; info; info = info->next) { 656 MemoryDeviceInfo *value = info->value; 657 658 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 659 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 660 661 if (pcdimm_info->addr >= addr && 662 addr < (pcdimm_info->addr + pcdimm_info->size)) { 663 return pcdimm_info->node; 664 } 665 } 666 } 667 668 return -1; 669 } 670 671 struct sPAPRDrconfCellV2 { 672 uint32_t seq_lmbs; 673 uint64_t base_addr; 674 uint32_t drc_index; 675 uint32_t aa_index; 676 uint32_t flags; 677 } QEMU_PACKED; 678 679 typedef struct DrconfCellQueue { 680 struct sPAPRDrconfCellV2 cell; 681 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 682 } DrconfCellQueue; 683 684 static DrconfCellQueue * 685 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 686 uint32_t drc_index, uint32_t aa_index, 687 uint32_t flags) 688 { 689 DrconfCellQueue *elem; 690 691 elem = g_malloc0(sizeof(*elem)); 692 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 693 elem->cell.base_addr = cpu_to_be64(base_addr); 694 elem->cell.drc_index = cpu_to_be32(drc_index); 695 elem->cell.aa_index = cpu_to_be32(aa_index); 696 elem->cell.flags = cpu_to_be32(flags); 697 698 return elem; 699 } 700 701 /* ibm,dynamic-memory-v2 */ 702 static int spapr_populate_drmem_v2(sPAPRMachineState *spapr, void *fdt, 703 int offset, MemoryDeviceInfoList *dimms) 704 { 705 uint8_t *int_buf, *cur_index, buf_len; 706 int ret; 707 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 708 uint64_t addr, cur_addr, size; 709 uint32_t nr_boot_lmbs = (spapr->hotplug_memory.base / lmb_size); 710 uint64_t mem_end = spapr->hotplug_memory.base + 711 memory_region_size(&spapr->hotplug_memory.mr); 712 uint32_t node, nr_entries = 0; 713 sPAPRDRConnector *drc; 714 DrconfCellQueue *elem, *next; 715 MemoryDeviceInfoList *info; 716 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 717 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 718 719 /* Entry to cover RAM and the gap area */ 720 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 721 SPAPR_LMB_FLAGS_RESERVED | 722 SPAPR_LMB_FLAGS_DRC_INVALID); 723 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 724 nr_entries++; 725 726 cur_addr = spapr->hotplug_memory.base; 727 for (info = dimms; info; info = info->next) { 728 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 729 730 addr = di->addr; 731 size = di->size; 732 node = di->node; 733 734 /* Entry for hot-pluggable area */ 735 if (cur_addr < addr) { 736 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 737 g_assert(drc); 738 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 739 cur_addr, spapr_drc_index(drc), -1, 0); 740 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 741 nr_entries++; 742 } 743 744 /* Entry for DIMM */ 745 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 746 g_assert(drc); 747 elem = spapr_get_drconf_cell(size / lmb_size, addr, 748 spapr_drc_index(drc), node, 749 SPAPR_LMB_FLAGS_ASSIGNED); 750 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 751 nr_entries++; 752 cur_addr = addr + size; 753 } 754 755 /* Entry for remaining hotpluggable area */ 756 if (cur_addr < mem_end) { 757 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 758 g_assert(drc); 759 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 760 cur_addr, spapr_drc_index(drc), -1, 0); 761 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 762 nr_entries++; 763 } 764 765 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 766 int_buf = cur_index = g_malloc0(buf_len); 767 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 768 cur_index += sizeof(nr_entries); 769 770 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 771 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 772 cur_index += sizeof(elem->cell); 773 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 774 g_free(elem); 775 } 776 777 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 778 g_free(int_buf); 779 if (ret < 0) { 780 return -1; 781 } 782 return 0; 783 } 784 785 /* ibm,dynamic-memory */ 786 static int spapr_populate_drmem_v1(sPAPRMachineState *spapr, void *fdt, 787 int offset, MemoryDeviceInfoList *dimms) 788 { 789 int i, ret; 790 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 791 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 792 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 793 memory_region_size(&spapr->hotplug_memory.mr)) / 794 lmb_size; 795 uint32_t *int_buf, *cur_index, buf_len; 796 797 /* 798 * Allocate enough buffer size to fit in ibm,dynamic-memory 799 */ 800 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 801 cur_index = int_buf = g_malloc0(buf_len); 802 int_buf[0] = cpu_to_be32(nr_lmbs); 803 cur_index++; 804 for (i = 0; i < nr_lmbs; i++) { 805 uint64_t addr = i * lmb_size; 806 uint32_t *dynamic_memory = cur_index; 807 808 if (i >= hotplug_lmb_start) { 809 sPAPRDRConnector *drc; 810 811 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 812 g_assert(drc); 813 814 dynamic_memory[0] = cpu_to_be32(addr >> 32); 815 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 816 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 817 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 818 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 819 if (memory_region_present(get_system_memory(), addr)) { 820 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 821 } else { 822 dynamic_memory[5] = cpu_to_be32(0); 823 } 824 } else { 825 /* 826 * LMB information for RMA, boot time RAM and gap b/n RAM and 827 * hotplug memory region -- all these are marked as reserved 828 * and as having no valid DRC. 829 */ 830 dynamic_memory[0] = cpu_to_be32(addr >> 32); 831 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 832 dynamic_memory[2] = cpu_to_be32(0); 833 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 834 dynamic_memory[4] = cpu_to_be32(-1); 835 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 836 SPAPR_LMB_FLAGS_DRC_INVALID); 837 } 838 839 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 840 } 841 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 842 g_free(int_buf); 843 if (ret < 0) { 844 return -1; 845 } 846 return 0; 847 } 848 849 /* 850 * Adds ibm,dynamic-reconfiguration-memory node. 851 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 852 * of this device tree node. 853 */ 854 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 855 { 856 MachineState *machine = MACHINE(spapr); 857 int ret, i, offset; 858 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 859 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 860 uint32_t *int_buf, *cur_index, buf_len; 861 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 862 MemoryDeviceInfoList *dimms = NULL; 863 864 /* 865 * Don't create the node if there is no hotpluggable memory 866 */ 867 if (machine->ram_size == machine->maxram_size) { 868 return 0; 869 } 870 871 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 872 873 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 874 sizeof(prop_lmb_size)); 875 if (ret < 0) { 876 return ret; 877 } 878 879 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 880 if (ret < 0) { 881 return ret; 882 } 883 884 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 885 if (ret < 0) { 886 return ret; 887 } 888 889 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 890 dimms = qmp_pc_dimm_device_list(); 891 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 892 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 893 } else { 894 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 895 } 896 qapi_free_MemoryDeviceInfoList(dimms); 897 898 if (ret < 0) { 899 return ret; 900 } 901 902 /* ibm,associativity-lookup-arrays */ 903 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 904 cur_index = int_buf = g_malloc0(buf_len); 905 906 cur_index = int_buf; 907 int_buf[0] = cpu_to_be32(nr_nodes); 908 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 909 cur_index += 2; 910 for (i = 0; i < nr_nodes; i++) { 911 uint32_t associativity[] = { 912 cpu_to_be32(0x0), 913 cpu_to_be32(0x0), 914 cpu_to_be32(0x0), 915 cpu_to_be32(i) 916 }; 917 memcpy(cur_index, associativity, sizeof(associativity)); 918 cur_index += 4; 919 } 920 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 921 (cur_index - int_buf) * sizeof(uint32_t)); 922 g_free(int_buf); 923 924 return ret; 925 } 926 927 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 928 sPAPROptionVector *ov5_updates) 929 { 930 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 931 int ret = 0, offset; 932 933 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 934 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 935 g_assert(smc->dr_lmb_enabled); 936 ret = spapr_populate_drconf_memory(spapr, fdt); 937 if (ret) { 938 goto out; 939 } 940 } 941 942 offset = fdt_path_offset(fdt, "/chosen"); 943 if (offset < 0) { 944 offset = fdt_add_subnode(fdt, 0, "chosen"); 945 if (offset < 0) { 946 return offset; 947 } 948 } 949 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 950 "ibm,architecture-vec-5"); 951 952 out: 953 return ret; 954 } 955 956 static bool spapr_hotplugged_dev_before_cas(void) 957 { 958 Object *drc_container, *obj; 959 ObjectProperty *prop; 960 ObjectPropertyIterator iter; 961 962 drc_container = container_get(object_get_root(), "/dr-connector"); 963 object_property_iter_init(&iter, drc_container); 964 while ((prop = object_property_iter_next(&iter))) { 965 if (!strstart(prop->type, "link<", NULL)) { 966 continue; 967 } 968 obj = object_property_get_link(drc_container, prop->name, NULL); 969 if (spapr_drc_needed(obj)) { 970 return true; 971 } 972 } 973 return false; 974 } 975 976 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 977 target_ulong addr, target_ulong size, 978 sPAPROptionVector *ov5_updates) 979 { 980 void *fdt, *fdt_skel; 981 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 982 983 if (spapr_hotplugged_dev_before_cas()) { 984 return 1; 985 } 986 987 if (size < sizeof(hdr) || size > FW_MAX_SIZE) { 988 error_report("SLOF provided an unexpected CAS buffer size " 989 TARGET_FMT_lu " (min: %zu, max: %u)", 990 size, sizeof(hdr), FW_MAX_SIZE); 991 exit(EXIT_FAILURE); 992 } 993 994 size -= sizeof(hdr); 995 996 /* Create skeleton */ 997 fdt_skel = g_malloc0(size); 998 _FDT((fdt_create(fdt_skel, size))); 999 _FDT((fdt_finish_reservemap(fdt_skel))); 1000 _FDT((fdt_begin_node(fdt_skel, ""))); 1001 _FDT((fdt_end_node(fdt_skel))); 1002 _FDT((fdt_finish(fdt_skel))); 1003 fdt = g_malloc0(size); 1004 _FDT((fdt_open_into(fdt_skel, fdt, size))); 1005 g_free(fdt_skel); 1006 1007 /* Fixup cpu nodes */ 1008 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 1009 1010 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 1011 return -1; 1012 } 1013 1014 /* Pack resulting tree */ 1015 _FDT((fdt_pack(fdt))); 1016 1017 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 1018 trace_spapr_cas_failed(size); 1019 return -1; 1020 } 1021 1022 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 1023 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 1024 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 1025 g_free(fdt); 1026 1027 return 0; 1028 } 1029 1030 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 1031 { 1032 int rtas; 1033 GString *hypertas = g_string_sized_new(256); 1034 GString *qemu_hypertas = g_string_sized_new(256); 1035 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 1036 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 1037 memory_region_size(&spapr->hotplug_memory.mr); 1038 uint32_t lrdr_capacity[] = { 1039 cpu_to_be32(max_hotplug_addr >> 32), 1040 cpu_to_be32(max_hotplug_addr & 0xffffffff), 1041 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 1042 cpu_to_be32(max_cpus / smp_threads), 1043 }; 1044 uint32_t maxdomains[] = { 1045 cpu_to_be32(4), 1046 cpu_to_be32(0), 1047 cpu_to_be32(0), 1048 cpu_to_be32(0), 1049 cpu_to_be32(nb_numa_nodes ? nb_numa_nodes - 1 : 0), 1050 }; 1051 1052 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 1053 1054 /* hypertas */ 1055 add_str(hypertas, "hcall-pft"); 1056 add_str(hypertas, "hcall-term"); 1057 add_str(hypertas, "hcall-dabr"); 1058 add_str(hypertas, "hcall-interrupt"); 1059 add_str(hypertas, "hcall-tce"); 1060 add_str(hypertas, "hcall-vio"); 1061 add_str(hypertas, "hcall-splpar"); 1062 add_str(hypertas, "hcall-bulk"); 1063 add_str(hypertas, "hcall-set-mode"); 1064 add_str(hypertas, "hcall-sprg0"); 1065 add_str(hypertas, "hcall-copy"); 1066 add_str(hypertas, "hcall-debug"); 1067 add_str(qemu_hypertas, "hcall-memop1"); 1068 1069 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 1070 add_str(hypertas, "hcall-multi-tce"); 1071 } 1072 1073 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 1074 add_str(hypertas, "hcall-hpt-resize"); 1075 } 1076 1077 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 1078 hypertas->str, hypertas->len)); 1079 g_string_free(hypertas, TRUE); 1080 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 1081 qemu_hypertas->str, qemu_hypertas->len)); 1082 g_string_free(qemu_hypertas, TRUE); 1083 1084 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 1085 refpoints, sizeof(refpoints))); 1086 1087 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 1088 maxdomains, sizeof(maxdomains))); 1089 1090 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 1091 RTAS_ERROR_LOG_MAX)); 1092 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 1093 RTAS_EVENT_SCAN_RATE)); 1094 1095 g_assert(msi_nonbroken); 1096 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 1097 1098 /* 1099 * According to PAPR, rtas ibm,os-term does not guarantee a return 1100 * back to the guest cpu. 1101 * 1102 * While an additional ibm,extended-os-term property indicates 1103 * that rtas call return will always occur. Set this property. 1104 */ 1105 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1106 1107 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1108 lrdr_capacity, sizeof(lrdr_capacity))); 1109 1110 spapr_dt_rtas_tokens(fdt, rtas); 1111 } 1112 1113 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features 1114 * that the guest may request and thus the valid values for bytes 24..26 of 1115 * option vector 5: */ 1116 static void spapr_dt_ov5_platform_support(void *fdt, int chosen) 1117 { 1118 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1119 1120 char val[2 * 4] = { 1121 23, 0x00, /* Xive mode, filled in below. */ 1122 24, 0x00, /* Hash/Radix, filled in below. */ 1123 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1124 26, 0x40, /* Radix options: GTSE == yes. */ 1125 }; 1126 1127 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1128 first_ppc_cpu->compat_pvr)) { 1129 /* If we're in a pre POWER9 compat mode then the guest should do hash */ 1130 val[3] = 0x00; /* Hash */ 1131 } else if (kvm_enabled()) { 1132 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1133 val[3] = 0x80; /* OV5_MMU_BOTH */ 1134 } else if (kvmppc_has_cap_mmu_radix()) { 1135 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1136 } else { 1137 val[3] = 0x00; /* Hash */ 1138 } 1139 } else { 1140 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1141 val[3] = 0xC0; 1142 } 1143 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1144 val, sizeof(val))); 1145 } 1146 1147 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 1148 { 1149 MachineState *machine = MACHINE(spapr); 1150 int chosen; 1151 const char *boot_device = machine->boot_order; 1152 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1153 size_t cb = 0; 1154 char *bootlist = get_boot_devices_list(&cb, true); 1155 1156 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1157 1158 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 1159 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1160 spapr->initrd_base)); 1161 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1162 spapr->initrd_base + spapr->initrd_size)); 1163 1164 if (spapr->kernel_size) { 1165 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1166 cpu_to_be64(spapr->kernel_size) }; 1167 1168 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1169 &kprop, sizeof(kprop))); 1170 if (spapr->kernel_le) { 1171 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1172 } 1173 } 1174 if (boot_menu) { 1175 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1176 } 1177 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1178 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1179 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1180 1181 if (cb && bootlist) { 1182 int i; 1183 1184 for (i = 0; i < cb; i++) { 1185 if (bootlist[i] == '\n') { 1186 bootlist[i] = ' '; 1187 } 1188 } 1189 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1190 } 1191 1192 if (boot_device && strlen(boot_device)) { 1193 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1194 } 1195 1196 if (!spapr->has_graphics && stdout_path) { 1197 /* 1198 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1199 * kernel. New platforms should only use the "stdout-path" property. Set 1200 * the new property and continue using older property to remain 1201 * compatible with the existing firmware. 1202 */ 1203 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1204 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1205 } 1206 1207 spapr_dt_ov5_platform_support(fdt, chosen); 1208 1209 g_free(stdout_path); 1210 g_free(bootlist); 1211 } 1212 1213 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 1214 { 1215 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1216 * KVM to work under pHyp with some guest co-operation */ 1217 int hypervisor; 1218 uint8_t hypercall[16]; 1219 1220 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1221 /* indicate KVM hypercall interface */ 1222 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1223 if (kvmppc_has_cap_fixup_hcalls()) { 1224 /* 1225 * Older KVM versions with older guest kernels were broken 1226 * with the magic page, don't allow the guest to map it. 1227 */ 1228 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1229 sizeof(hypercall))) { 1230 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1231 hypercall, sizeof(hypercall))); 1232 } 1233 } 1234 } 1235 1236 static void *spapr_build_fdt(sPAPRMachineState *spapr, 1237 hwaddr rtas_addr, 1238 hwaddr rtas_size) 1239 { 1240 MachineState *machine = MACHINE(spapr); 1241 MachineClass *mc = MACHINE_GET_CLASS(machine); 1242 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1243 int ret; 1244 void *fdt; 1245 sPAPRPHBState *phb; 1246 char *buf; 1247 1248 fdt = g_malloc0(FDT_MAX_SIZE); 1249 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1250 1251 /* Root node */ 1252 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1253 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1254 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1255 1256 /* 1257 * Add info to guest to indentify which host is it being run on 1258 * and what is the uuid of the guest 1259 */ 1260 if (kvmppc_get_host_model(&buf)) { 1261 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1262 g_free(buf); 1263 } 1264 if (kvmppc_get_host_serial(&buf)) { 1265 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1266 g_free(buf); 1267 } 1268 1269 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1270 1271 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1272 if (qemu_uuid_set) { 1273 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1274 } 1275 g_free(buf); 1276 1277 if (qemu_get_vm_name()) { 1278 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1279 qemu_get_vm_name())); 1280 } 1281 1282 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1283 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1284 1285 /* /interrupt controller */ 1286 spapr_dt_xics(xics_max_server_number(spapr), fdt, PHANDLE_XICP); 1287 1288 ret = spapr_populate_memory(spapr, fdt); 1289 if (ret < 0) { 1290 error_report("couldn't setup memory nodes in fdt"); 1291 exit(1); 1292 } 1293 1294 /* /vdevice */ 1295 spapr_dt_vdevice(spapr->vio_bus, fdt); 1296 1297 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1298 ret = spapr_rng_populate_dt(fdt); 1299 if (ret < 0) { 1300 error_report("could not set up rng device in the fdt"); 1301 exit(1); 1302 } 1303 } 1304 1305 QLIST_FOREACH(phb, &spapr->phbs, list) { 1306 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 1307 if (ret < 0) { 1308 error_report("couldn't setup PCI devices in fdt"); 1309 exit(1); 1310 } 1311 } 1312 1313 /* cpus */ 1314 spapr_populate_cpus_dt_node(fdt, spapr); 1315 1316 if (smc->dr_lmb_enabled) { 1317 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1318 } 1319 1320 if (mc->has_hotpluggable_cpus) { 1321 int offset = fdt_path_offset(fdt, "/cpus"); 1322 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1323 SPAPR_DR_CONNECTOR_TYPE_CPU); 1324 if (ret < 0) { 1325 error_report("Couldn't set up CPU DR device tree properties"); 1326 exit(1); 1327 } 1328 } 1329 1330 /* /event-sources */ 1331 spapr_dt_events(spapr, fdt); 1332 1333 /* /rtas */ 1334 spapr_dt_rtas(spapr, fdt); 1335 1336 /* /chosen */ 1337 spapr_dt_chosen(spapr, fdt); 1338 1339 /* /hypervisor */ 1340 if (kvm_enabled()) { 1341 spapr_dt_hypervisor(spapr, fdt); 1342 } 1343 1344 /* Build memory reserve map */ 1345 if (spapr->kernel_size) { 1346 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1347 } 1348 if (spapr->initrd_size) { 1349 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1350 } 1351 1352 /* ibm,client-architecture-support updates */ 1353 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1354 if (ret < 0) { 1355 error_report("couldn't setup CAS properties fdt"); 1356 exit(1); 1357 } 1358 1359 return fdt; 1360 } 1361 1362 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1363 { 1364 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1365 } 1366 1367 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1368 PowerPCCPU *cpu) 1369 { 1370 CPUPPCState *env = &cpu->env; 1371 1372 /* The TCG path should also be holding the BQL at this point */ 1373 g_assert(qemu_mutex_iothread_locked()); 1374 1375 if (msr_pr) { 1376 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1377 env->gpr[3] = H_PRIVILEGE; 1378 } else { 1379 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1380 } 1381 } 1382 1383 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1384 { 1385 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1386 1387 return spapr->patb_entry; 1388 } 1389 1390 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1391 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1392 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1393 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1394 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1395 1396 /* 1397 * Get the fd to access the kernel htab, re-opening it if necessary 1398 */ 1399 static int get_htab_fd(sPAPRMachineState *spapr) 1400 { 1401 Error *local_err = NULL; 1402 1403 if (spapr->htab_fd >= 0) { 1404 return spapr->htab_fd; 1405 } 1406 1407 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1408 if (spapr->htab_fd < 0) { 1409 error_report_err(local_err); 1410 } 1411 1412 return spapr->htab_fd; 1413 } 1414 1415 void close_htab_fd(sPAPRMachineState *spapr) 1416 { 1417 if (spapr->htab_fd >= 0) { 1418 close(spapr->htab_fd); 1419 } 1420 spapr->htab_fd = -1; 1421 } 1422 1423 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1424 { 1425 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1426 1427 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1428 } 1429 1430 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1431 { 1432 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1433 1434 assert(kvm_enabled()); 1435 1436 if (!spapr->htab) { 1437 return 0; 1438 } 1439 1440 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1441 } 1442 1443 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1444 hwaddr ptex, int n) 1445 { 1446 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1447 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1448 1449 if (!spapr->htab) { 1450 /* 1451 * HTAB is controlled by KVM. Fetch into temporary buffer 1452 */ 1453 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1454 kvmppc_read_hptes(hptes, ptex, n); 1455 return hptes; 1456 } 1457 1458 /* 1459 * HTAB is controlled by QEMU. Just point to the internally 1460 * accessible PTEG. 1461 */ 1462 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1463 } 1464 1465 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1466 const ppc_hash_pte64_t *hptes, 1467 hwaddr ptex, int n) 1468 { 1469 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1470 1471 if (!spapr->htab) { 1472 g_free((void *)hptes); 1473 } 1474 1475 /* Nothing to do for qemu managed HPT */ 1476 } 1477 1478 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1479 uint64_t pte0, uint64_t pte1) 1480 { 1481 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1482 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1483 1484 if (!spapr->htab) { 1485 kvmppc_write_hpte(ptex, pte0, pte1); 1486 } else { 1487 stq_p(spapr->htab + offset, pte0); 1488 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1489 } 1490 } 1491 1492 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1493 { 1494 int shift; 1495 1496 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1497 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1498 * that's much more than is needed for Linux guests */ 1499 shift = ctz64(pow2ceil(ramsize)) - 7; 1500 shift = MAX(shift, 18); /* Minimum architected size */ 1501 shift = MIN(shift, 46); /* Maximum architected size */ 1502 return shift; 1503 } 1504 1505 void spapr_free_hpt(sPAPRMachineState *spapr) 1506 { 1507 g_free(spapr->htab); 1508 spapr->htab = NULL; 1509 spapr->htab_shift = 0; 1510 close_htab_fd(spapr); 1511 } 1512 1513 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1514 Error **errp) 1515 { 1516 long rc; 1517 1518 /* Clean up any HPT info from a previous boot */ 1519 spapr_free_hpt(spapr); 1520 1521 rc = kvmppc_reset_htab(shift); 1522 if (rc < 0) { 1523 /* kernel-side HPT needed, but couldn't allocate one */ 1524 error_setg_errno(errp, errno, 1525 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1526 shift); 1527 /* This is almost certainly fatal, but if the caller really 1528 * wants to carry on with shift == 0, it's welcome to try */ 1529 } else if (rc > 0) { 1530 /* kernel-side HPT allocated */ 1531 if (rc != shift) { 1532 error_setg(errp, 1533 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1534 shift, rc); 1535 } 1536 1537 spapr->htab_shift = shift; 1538 spapr->htab = NULL; 1539 } else { 1540 /* kernel-side HPT not needed, allocate in userspace instead */ 1541 size_t size = 1ULL << shift; 1542 int i; 1543 1544 spapr->htab = qemu_memalign(size, size); 1545 if (!spapr->htab) { 1546 error_setg_errno(errp, errno, 1547 "Could not allocate HPT of order %d", shift); 1548 return; 1549 } 1550 1551 memset(spapr->htab, 0, size); 1552 spapr->htab_shift = shift; 1553 1554 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1555 DIRTY_HPTE(HPTE(spapr->htab, i)); 1556 } 1557 } 1558 /* We're setting up a hash table, so that means we're not radix */ 1559 spapr->patb_entry = 0; 1560 } 1561 1562 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1563 { 1564 int hpt_shift; 1565 1566 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1567 || (spapr->cas_reboot 1568 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1569 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1570 } else { 1571 uint64_t current_ram_size; 1572 1573 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1574 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1575 } 1576 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1577 1578 if (spapr->vrma_adjust) { 1579 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1580 spapr->htab_shift); 1581 } 1582 } 1583 1584 static int spapr_reset_drcs(Object *child, void *opaque) 1585 { 1586 sPAPRDRConnector *drc = 1587 (sPAPRDRConnector *) object_dynamic_cast(child, 1588 TYPE_SPAPR_DR_CONNECTOR); 1589 1590 if (drc) { 1591 spapr_drc_reset(drc); 1592 } 1593 1594 return 0; 1595 } 1596 1597 static void spapr_machine_reset(void) 1598 { 1599 MachineState *machine = MACHINE(qdev_get_machine()); 1600 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1601 PowerPCCPU *first_ppc_cpu; 1602 uint32_t rtas_limit; 1603 hwaddr rtas_addr, fdt_addr; 1604 void *fdt; 1605 int rc; 1606 1607 spapr_caps_reset(spapr); 1608 1609 first_ppc_cpu = POWERPC_CPU(first_cpu); 1610 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1611 ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1612 spapr->max_compat_pvr)) { 1613 /* If using KVM with radix mode available, VCPUs can be started 1614 * without a HPT because KVM will start them in radix mode. 1615 * Set the GR bit in PATB so that we know there is no HPT. */ 1616 spapr->patb_entry = PATBE1_GR; 1617 } else { 1618 spapr_setup_hpt_and_vrma(spapr); 1619 } 1620 1621 /* if this reset wasn't generated by CAS, we should reset our 1622 * negotiated options and start from scratch */ 1623 if (!spapr->cas_reboot) { 1624 spapr_ovec_cleanup(spapr->ov5_cas); 1625 spapr->ov5_cas = spapr_ovec_new(); 1626 1627 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); 1628 } 1629 1630 qemu_devices_reset(); 1631 1632 /* DRC reset may cause a device to be unplugged. This will cause troubles 1633 * if this device is used by another device (eg, a running vhost backend 1634 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1635 * situations, we reset DRCs after all devices have been reset. 1636 */ 1637 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1638 1639 spapr_clear_pending_events(spapr); 1640 1641 /* 1642 * We place the device tree and RTAS just below either the top of the RMA, 1643 * or just below 2GB, whichever is lowere, so that it can be 1644 * processed with 32-bit real mode code if necessary 1645 */ 1646 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1647 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1648 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1649 1650 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1651 1652 spapr_load_rtas(spapr, fdt, rtas_addr); 1653 1654 rc = fdt_pack(fdt); 1655 1656 /* Should only fail if we've built a corrupted tree */ 1657 assert(rc == 0); 1658 1659 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1660 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1661 fdt_totalsize(fdt), FDT_MAX_SIZE); 1662 exit(1); 1663 } 1664 1665 /* Load the fdt */ 1666 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1667 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1668 g_free(fdt); 1669 1670 /* Set up the entry state */ 1671 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); 1672 first_ppc_cpu->env.gpr[5] = 0; 1673 1674 spapr->cas_reboot = false; 1675 } 1676 1677 static void spapr_create_nvram(sPAPRMachineState *spapr) 1678 { 1679 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1680 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1681 1682 if (dinfo) { 1683 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1684 &error_fatal); 1685 } 1686 1687 qdev_init_nofail(dev); 1688 1689 spapr->nvram = (struct sPAPRNVRAM *)dev; 1690 } 1691 1692 static void spapr_rtc_create(sPAPRMachineState *spapr) 1693 { 1694 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1695 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1696 &error_fatal); 1697 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1698 &error_fatal); 1699 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1700 "date", &error_fatal); 1701 } 1702 1703 /* Returns whether we want to use VGA or not */ 1704 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1705 { 1706 switch (vga_interface_type) { 1707 case VGA_NONE: 1708 return false; 1709 case VGA_DEVICE: 1710 return true; 1711 case VGA_STD: 1712 case VGA_VIRTIO: 1713 return pci_vga_init(pci_bus) != NULL; 1714 default: 1715 error_setg(errp, 1716 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1717 return false; 1718 } 1719 } 1720 1721 static int spapr_pre_load(void *opaque) 1722 { 1723 int rc; 1724 1725 rc = spapr_caps_pre_load(opaque); 1726 if (rc) { 1727 return rc; 1728 } 1729 1730 return 0; 1731 } 1732 1733 static int spapr_post_load(void *opaque, int version_id) 1734 { 1735 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1736 int err = 0; 1737 1738 err = spapr_caps_post_migration(spapr); 1739 if (err) { 1740 return err; 1741 } 1742 1743 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1744 CPUState *cs; 1745 CPU_FOREACH(cs) { 1746 PowerPCCPU *cpu = POWERPC_CPU(cs); 1747 icp_resend(ICP(cpu->intc)); 1748 } 1749 } 1750 1751 /* In earlier versions, there was no separate qdev for the PAPR 1752 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1753 * So when migrating from those versions, poke the incoming offset 1754 * value into the RTC device */ 1755 if (version_id < 3) { 1756 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1757 } 1758 1759 if (kvm_enabled() && spapr->patb_entry) { 1760 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1761 bool radix = !!(spapr->patb_entry & PATBE1_GR); 1762 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1763 1764 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1765 if (err) { 1766 error_report("Process table config unsupported by the host"); 1767 return -EINVAL; 1768 } 1769 } 1770 1771 return err; 1772 } 1773 1774 static int spapr_pre_save(void *opaque) 1775 { 1776 int rc; 1777 1778 rc = spapr_caps_pre_save(opaque); 1779 if (rc) { 1780 return rc; 1781 } 1782 1783 return 0; 1784 } 1785 1786 static bool version_before_3(void *opaque, int version_id) 1787 { 1788 return version_id < 3; 1789 } 1790 1791 static bool spapr_pending_events_needed(void *opaque) 1792 { 1793 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1794 return !QTAILQ_EMPTY(&spapr->pending_events); 1795 } 1796 1797 static const VMStateDescription vmstate_spapr_event_entry = { 1798 .name = "spapr_event_log_entry", 1799 .version_id = 1, 1800 .minimum_version_id = 1, 1801 .fields = (VMStateField[]) { 1802 VMSTATE_UINT32(summary, sPAPREventLogEntry), 1803 VMSTATE_UINT32(extended_length, sPAPREventLogEntry), 1804 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, 1805 NULL, extended_length), 1806 VMSTATE_END_OF_LIST() 1807 }, 1808 }; 1809 1810 static const VMStateDescription vmstate_spapr_pending_events = { 1811 .name = "spapr_pending_events", 1812 .version_id = 1, 1813 .minimum_version_id = 1, 1814 .needed = spapr_pending_events_needed, 1815 .fields = (VMStateField[]) { 1816 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, 1817 vmstate_spapr_event_entry, sPAPREventLogEntry, next), 1818 VMSTATE_END_OF_LIST() 1819 }, 1820 }; 1821 1822 static bool spapr_ov5_cas_needed(void *opaque) 1823 { 1824 sPAPRMachineState *spapr = opaque; 1825 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1826 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1827 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1828 bool cas_needed; 1829 1830 /* Prior to the introduction of sPAPROptionVector, we had two option 1831 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1832 * Both of these options encode machine topology into the device-tree 1833 * in such a way that the now-booted OS should still be able to interact 1834 * appropriately with QEMU regardless of what options were actually 1835 * negotiatied on the source side. 1836 * 1837 * As such, we can avoid migrating the CAS-negotiated options if these 1838 * are the only options available on the current machine/platform. 1839 * Since these are the only options available for pseries-2.7 and 1840 * earlier, this allows us to maintain old->new/new->old migration 1841 * compatibility. 1842 * 1843 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1844 * via default pseries-2.8 machines and explicit command-line parameters. 1845 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1846 * of the actual CAS-negotiated values to continue working properly. For 1847 * example, availability of memory unplug depends on knowing whether 1848 * OV5_HP_EVT was negotiated via CAS. 1849 * 1850 * Thus, for any cases where the set of available CAS-negotiatable 1851 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1852 * include the CAS-negotiated options in the migration stream. 1853 */ 1854 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1855 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1856 1857 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1858 * the mask itself since in the future it's possible "legacy" bits may be 1859 * removed via machine options, which could generate a false positive 1860 * that breaks migration. 1861 */ 1862 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1863 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1864 1865 spapr_ovec_cleanup(ov5_mask); 1866 spapr_ovec_cleanup(ov5_legacy); 1867 spapr_ovec_cleanup(ov5_removed); 1868 1869 return cas_needed; 1870 } 1871 1872 static const VMStateDescription vmstate_spapr_ov5_cas = { 1873 .name = "spapr_option_vector_ov5_cas", 1874 .version_id = 1, 1875 .minimum_version_id = 1, 1876 .needed = spapr_ov5_cas_needed, 1877 .fields = (VMStateField[]) { 1878 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1879 vmstate_spapr_ovec, sPAPROptionVector), 1880 VMSTATE_END_OF_LIST() 1881 }, 1882 }; 1883 1884 static bool spapr_patb_entry_needed(void *opaque) 1885 { 1886 sPAPRMachineState *spapr = opaque; 1887 1888 return !!spapr->patb_entry; 1889 } 1890 1891 static const VMStateDescription vmstate_spapr_patb_entry = { 1892 .name = "spapr_patb_entry", 1893 .version_id = 1, 1894 .minimum_version_id = 1, 1895 .needed = spapr_patb_entry_needed, 1896 .fields = (VMStateField[]) { 1897 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1898 VMSTATE_END_OF_LIST() 1899 }, 1900 }; 1901 1902 static const VMStateDescription vmstate_spapr = { 1903 .name = "spapr", 1904 .version_id = 3, 1905 .minimum_version_id = 1, 1906 .pre_load = spapr_pre_load, 1907 .post_load = spapr_post_load, 1908 .pre_save = spapr_pre_save, 1909 .fields = (VMStateField[]) { 1910 /* used to be @next_irq */ 1911 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1912 1913 /* RTC offset */ 1914 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1915 1916 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1917 VMSTATE_END_OF_LIST() 1918 }, 1919 .subsections = (const VMStateDescription*[]) { 1920 &vmstate_spapr_ov5_cas, 1921 &vmstate_spapr_patb_entry, 1922 &vmstate_spapr_pending_events, 1923 &vmstate_spapr_cap_htm, 1924 &vmstate_spapr_cap_vsx, 1925 &vmstate_spapr_cap_dfp, 1926 &vmstate_spapr_cap_cfpc, 1927 &vmstate_spapr_cap_sbbc, 1928 &vmstate_spapr_cap_ibs, 1929 NULL 1930 } 1931 }; 1932 1933 static int htab_save_setup(QEMUFile *f, void *opaque) 1934 { 1935 sPAPRMachineState *spapr = opaque; 1936 1937 /* "Iteration" header */ 1938 if (!spapr->htab_shift) { 1939 qemu_put_be32(f, -1); 1940 } else { 1941 qemu_put_be32(f, spapr->htab_shift); 1942 } 1943 1944 if (spapr->htab) { 1945 spapr->htab_save_index = 0; 1946 spapr->htab_first_pass = true; 1947 } else { 1948 if (spapr->htab_shift) { 1949 assert(kvm_enabled()); 1950 } 1951 } 1952 1953 1954 return 0; 1955 } 1956 1957 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr, 1958 int chunkstart, int n_valid, int n_invalid) 1959 { 1960 qemu_put_be32(f, chunkstart); 1961 qemu_put_be16(f, n_valid); 1962 qemu_put_be16(f, n_invalid); 1963 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1964 HASH_PTE_SIZE_64 * n_valid); 1965 } 1966 1967 static void htab_save_end_marker(QEMUFile *f) 1968 { 1969 qemu_put_be32(f, 0); 1970 qemu_put_be16(f, 0); 1971 qemu_put_be16(f, 0); 1972 } 1973 1974 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1975 int64_t max_ns) 1976 { 1977 bool has_timeout = max_ns != -1; 1978 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1979 int index = spapr->htab_save_index; 1980 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1981 1982 assert(spapr->htab_first_pass); 1983 1984 do { 1985 int chunkstart; 1986 1987 /* Consume invalid HPTEs */ 1988 while ((index < htabslots) 1989 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1990 CLEAN_HPTE(HPTE(spapr->htab, index)); 1991 index++; 1992 } 1993 1994 /* Consume valid HPTEs */ 1995 chunkstart = index; 1996 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1997 && HPTE_VALID(HPTE(spapr->htab, index))) { 1998 CLEAN_HPTE(HPTE(spapr->htab, index)); 1999 index++; 2000 } 2001 2002 if (index > chunkstart) { 2003 int n_valid = index - chunkstart; 2004 2005 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2006 2007 if (has_timeout && 2008 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2009 break; 2010 } 2011 } 2012 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2013 2014 if (index >= htabslots) { 2015 assert(index == htabslots); 2016 index = 0; 2017 spapr->htab_first_pass = false; 2018 } 2019 spapr->htab_save_index = index; 2020 } 2021 2022 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 2023 int64_t max_ns) 2024 { 2025 bool final = max_ns < 0; 2026 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2027 int examined = 0, sent = 0; 2028 int index = spapr->htab_save_index; 2029 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2030 2031 assert(!spapr->htab_first_pass); 2032 2033 do { 2034 int chunkstart, invalidstart; 2035 2036 /* Consume non-dirty HPTEs */ 2037 while ((index < htabslots) 2038 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2039 index++; 2040 examined++; 2041 } 2042 2043 chunkstart = index; 2044 /* Consume valid dirty HPTEs */ 2045 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2046 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2047 && HPTE_VALID(HPTE(spapr->htab, index))) { 2048 CLEAN_HPTE(HPTE(spapr->htab, index)); 2049 index++; 2050 examined++; 2051 } 2052 2053 invalidstart = index; 2054 /* Consume invalid dirty HPTEs */ 2055 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2056 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2057 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2058 CLEAN_HPTE(HPTE(spapr->htab, index)); 2059 index++; 2060 examined++; 2061 } 2062 2063 if (index > chunkstart) { 2064 int n_valid = invalidstart - chunkstart; 2065 int n_invalid = index - invalidstart; 2066 2067 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2068 sent += index - chunkstart; 2069 2070 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2071 break; 2072 } 2073 } 2074 2075 if (examined >= htabslots) { 2076 break; 2077 } 2078 2079 if (index >= htabslots) { 2080 assert(index == htabslots); 2081 index = 0; 2082 } 2083 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2084 2085 if (index >= htabslots) { 2086 assert(index == htabslots); 2087 index = 0; 2088 } 2089 2090 spapr->htab_save_index = index; 2091 2092 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2093 } 2094 2095 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2096 #define MAX_KVM_BUF_SIZE 2048 2097 2098 static int htab_save_iterate(QEMUFile *f, void *opaque) 2099 { 2100 sPAPRMachineState *spapr = opaque; 2101 int fd; 2102 int rc = 0; 2103 2104 /* Iteration header */ 2105 if (!spapr->htab_shift) { 2106 qemu_put_be32(f, -1); 2107 return 1; 2108 } else { 2109 qemu_put_be32(f, 0); 2110 } 2111 2112 if (!spapr->htab) { 2113 assert(kvm_enabled()); 2114 2115 fd = get_htab_fd(spapr); 2116 if (fd < 0) { 2117 return fd; 2118 } 2119 2120 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2121 if (rc < 0) { 2122 return rc; 2123 } 2124 } else if (spapr->htab_first_pass) { 2125 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2126 } else { 2127 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2128 } 2129 2130 htab_save_end_marker(f); 2131 2132 return rc; 2133 } 2134 2135 static int htab_save_complete(QEMUFile *f, void *opaque) 2136 { 2137 sPAPRMachineState *spapr = opaque; 2138 int fd; 2139 2140 /* Iteration header */ 2141 if (!spapr->htab_shift) { 2142 qemu_put_be32(f, -1); 2143 return 0; 2144 } else { 2145 qemu_put_be32(f, 0); 2146 } 2147 2148 if (!spapr->htab) { 2149 int rc; 2150 2151 assert(kvm_enabled()); 2152 2153 fd = get_htab_fd(spapr); 2154 if (fd < 0) { 2155 return fd; 2156 } 2157 2158 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2159 if (rc < 0) { 2160 return rc; 2161 } 2162 } else { 2163 if (spapr->htab_first_pass) { 2164 htab_save_first_pass(f, spapr, -1); 2165 } 2166 htab_save_later_pass(f, spapr, -1); 2167 } 2168 2169 /* End marker */ 2170 htab_save_end_marker(f); 2171 2172 return 0; 2173 } 2174 2175 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2176 { 2177 sPAPRMachineState *spapr = opaque; 2178 uint32_t section_hdr; 2179 int fd = -1; 2180 Error *local_err = NULL; 2181 2182 if (version_id < 1 || version_id > 1) { 2183 error_report("htab_load() bad version"); 2184 return -EINVAL; 2185 } 2186 2187 section_hdr = qemu_get_be32(f); 2188 2189 if (section_hdr == -1) { 2190 spapr_free_hpt(spapr); 2191 return 0; 2192 } 2193 2194 if (section_hdr) { 2195 /* First section gives the htab size */ 2196 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2197 if (local_err) { 2198 error_report_err(local_err); 2199 return -EINVAL; 2200 } 2201 return 0; 2202 } 2203 2204 if (!spapr->htab) { 2205 assert(kvm_enabled()); 2206 2207 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2208 if (fd < 0) { 2209 error_report_err(local_err); 2210 return fd; 2211 } 2212 } 2213 2214 while (true) { 2215 uint32_t index; 2216 uint16_t n_valid, n_invalid; 2217 2218 index = qemu_get_be32(f); 2219 n_valid = qemu_get_be16(f); 2220 n_invalid = qemu_get_be16(f); 2221 2222 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2223 /* End of Stream */ 2224 break; 2225 } 2226 2227 if ((index + n_valid + n_invalid) > 2228 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2229 /* Bad index in stream */ 2230 error_report( 2231 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2232 index, n_valid, n_invalid, spapr->htab_shift); 2233 return -EINVAL; 2234 } 2235 2236 if (spapr->htab) { 2237 if (n_valid) { 2238 qemu_get_buffer(f, HPTE(spapr->htab, index), 2239 HASH_PTE_SIZE_64 * n_valid); 2240 } 2241 if (n_invalid) { 2242 memset(HPTE(spapr->htab, index + n_valid), 0, 2243 HASH_PTE_SIZE_64 * n_invalid); 2244 } 2245 } else { 2246 int rc; 2247 2248 assert(fd >= 0); 2249 2250 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2251 if (rc < 0) { 2252 return rc; 2253 } 2254 } 2255 } 2256 2257 if (!spapr->htab) { 2258 assert(fd >= 0); 2259 close(fd); 2260 } 2261 2262 return 0; 2263 } 2264 2265 static void htab_save_cleanup(void *opaque) 2266 { 2267 sPAPRMachineState *spapr = opaque; 2268 2269 close_htab_fd(spapr); 2270 } 2271 2272 static SaveVMHandlers savevm_htab_handlers = { 2273 .save_setup = htab_save_setup, 2274 .save_live_iterate = htab_save_iterate, 2275 .save_live_complete_precopy = htab_save_complete, 2276 .save_cleanup = htab_save_cleanup, 2277 .load_state = htab_load, 2278 }; 2279 2280 static void spapr_boot_set(void *opaque, const char *boot_device, 2281 Error **errp) 2282 { 2283 MachineState *machine = MACHINE(opaque); 2284 machine->boot_order = g_strdup(boot_device); 2285 } 2286 2287 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 2288 { 2289 MachineState *machine = MACHINE(spapr); 2290 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2291 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2292 int i; 2293 2294 for (i = 0; i < nr_lmbs; i++) { 2295 uint64_t addr; 2296 2297 addr = i * lmb_size + spapr->hotplug_memory.base; 2298 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2299 addr / lmb_size); 2300 } 2301 } 2302 2303 /* 2304 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2305 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2306 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2307 */ 2308 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2309 { 2310 int i; 2311 2312 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2313 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2314 " is not aligned to %llu MiB", 2315 machine->ram_size, 2316 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2317 return; 2318 } 2319 2320 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2321 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2322 " is not aligned to %llu MiB", 2323 machine->ram_size, 2324 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2325 return; 2326 } 2327 2328 for (i = 0; i < nb_numa_nodes; i++) { 2329 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2330 error_setg(errp, 2331 "Node %d memory size 0x%" PRIx64 2332 " is not aligned to %llu MiB", 2333 i, numa_info[i].node_mem, 2334 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2335 return; 2336 } 2337 } 2338 } 2339 2340 /* find cpu slot in machine->possible_cpus by core_id */ 2341 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2342 { 2343 int index = id / smp_threads; 2344 2345 if (index >= ms->possible_cpus->len) { 2346 return NULL; 2347 } 2348 if (idx) { 2349 *idx = index; 2350 } 2351 return &ms->possible_cpus->cpus[index]; 2352 } 2353 2354 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) 2355 { 2356 Error *local_err = NULL; 2357 bool vsmt_user = !!spapr->vsmt; 2358 int kvm_smt = kvmppc_smt_threads(); 2359 int ret; 2360 2361 if (!kvm_enabled() && (smp_threads > 1)) { 2362 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2363 "on a pseries machine"); 2364 goto out; 2365 } 2366 if (!is_power_of_2(smp_threads)) { 2367 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2368 "machine because it must be a power of 2", smp_threads); 2369 goto out; 2370 } 2371 2372 /* Detemine the VSMT mode to use: */ 2373 if (vsmt_user) { 2374 if (spapr->vsmt < smp_threads) { 2375 error_setg(&local_err, "Cannot support VSMT mode %d" 2376 " because it must be >= threads/core (%d)", 2377 spapr->vsmt, smp_threads); 2378 goto out; 2379 } 2380 /* In this case, spapr->vsmt has been set by the command line */ 2381 } else { 2382 /* 2383 * Default VSMT value is tricky, because we need it to be as 2384 * consistent as possible (for migration), but this requires 2385 * changing it for at least some existing cases. We pick 8 as 2386 * the value that we'd get with KVM on POWER8, the 2387 * overwhelmingly common case in production systems. 2388 */ 2389 spapr->vsmt = MAX(8, smp_threads); 2390 } 2391 2392 /* KVM: If necessary, set the SMT mode: */ 2393 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2394 ret = kvmppc_set_smt_threads(spapr->vsmt); 2395 if (ret) { 2396 /* Looks like KVM isn't able to change VSMT mode */ 2397 error_setg(&local_err, 2398 "Failed to set KVM's VSMT mode to %d (errno %d)", 2399 spapr->vsmt, ret); 2400 /* We can live with that if the default one is big enough 2401 * for the number of threads, and a submultiple of the one 2402 * we want. In this case we'll waste some vcpu ids, but 2403 * behaviour will be correct */ 2404 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2405 warn_report_err(local_err); 2406 local_err = NULL; 2407 goto out; 2408 } else { 2409 if (!vsmt_user) { 2410 error_append_hint(&local_err, 2411 "On PPC, a VM with %d threads/core" 2412 " on a host with %d threads/core" 2413 " requires the use of VSMT mode %d.\n", 2414 smp_threads, kvm_smt, spapr->vsmt); 2415 } 2416 kvmppc_hint_smt_possible(&local_err); 2417 goto out; 2418 } 2419 } 2420 } 2421 /* else TCG: nothing to do currently */ 2422 out: 2423 error_propagate(errp, local_err); 2424 } 2425 2426 static void spapr_init_cpus(sPAPRMachineState *spapr) 2427 { 2428 MachineState *machine = MACHINE(spapr); 2429 MachineClass *mc = MACHINE_GET_CLASS(machine); 2430 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2431 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2432 const CPUArchIdList *possible_cpus; 2433 int boot_cores_nr = smp_cpus / smp_threads; 2434 int i; 2435 2436 possible_cpus = mc->possible_cpu_arch_ids(machine); 2437 if (mc->has_hotpluggable_cpus) { 2438 if (smp_cpus % smp_threads) { 2439 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2440 smp_cpus, smp_threads); 2441 exit(1); 2442 } 2443 if (max_cpus % smp_threads) { 2444 error_report("max_cpus (%u) must be multiple of threads (%u)", 2445 max_cpus, smp_threads); 2446 exit(1); 2447 } 2448 } else { 2449 if (max_cpus != smp_cpus) { 2450 error_report("This machine version does not support CPU hotplug"); 2451 exit(1); 2452 } 2453 boot_cores_nr = possible_cpus->len; 2454 } 2455 2456 /* VSMT must be set in order to be able to compute VCPU ids, ie to 2457 * call xics_max_server_number() or spapr_vcpu_id(). 2458 */ 2459 spapr_set_vsmt_mode(spapr, &error_fatal); 2460 2461 if (smc->pre_2_10_has_unused_icps) { 2462 int i; 2463 2464 for (i = 0; i < xics_max_server_number(spapr); i++) { 2465 /* Dummy entries get deregistered when real ICPState objects 2466 * are registered during CPU core hotplug. 2467 */ 2468 pre_2_10_vmstate_register_dummy_icp(i); 2469 } 2470 } 2471 2472 for (i = 0; i < possible_cpus->len; i++) { 2473 int core_id = i * smp_threads; 2474 2475 if (mc->has_hotpluggable_cpus) { 2476 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2477 spapr_vcpu_id(spapr, core_id)); 2478 } 2479 2480 if (i < boot_cores_nr) { 2481 Object *core = object_new(type); 2482 int nr_threads = smp_threads; 2483 2484 /* Handle the partially filled core for older machine types */ 2485 if ((i + 1) * smp_threads >= smp_cpus) { 2486 nr_threads = smp_cpus - i * smp_threads; 2487 } 2488 2489 object_property_set_int(core, nr_threads, "nr-threads", 2490 &error_fatal); 2491 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2492 &error_fatal); 2493 object_property_set_bool(core, true, "realized", &error_fatal); 2494 } 2495 } 2496 } 2497 2498 /* pSeries LPAR / sPAPR hardware init */ 2499 static void spapr_machine_init(MachineState *machine) 2500 { 2501 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2502 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2503 const char *kernel_filename = machine->kernel_filename; 2504 const char *initrd_filename = machine->initrd_filename; 2505 PCIHostState *phb; 2506 int i; 2507 MemoryRegion *sysmem = get_system_memory(); 2508 MemoryRegion *ram = g_new(MemoryRegion, 1); 2509 hwaddr node0_size = spapr_node0_size(machine); 2510 long load_limit, fw_size; 2511 char *filename; 2512 Error *resize_hpt_err = NULL; 2513 2514 msi_nonbroken = true; 2515 2516 QLIST_INIT(&spapr->phbs); 2517 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2518 2519 /* Check HPT resizing availability */ 2520 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2521 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2522 /* 2523 * If the user explicitly requested a mode we should either 2524 * supply it, or fail completely (which we do below). But if 2525 * it's not set explicitly, we reset our mode to something 2526 * that works 2527 */ 2528 if (resize_hpt_err) { 2529 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2530 error_free(resize_hpt_err); 2531 resize_hpt_err = NULL; 2532 } else { 2533 spapr->resize_hpt = smc->resize_hpt_default; 2534 } 2535 } 2536 2537 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2538 2539 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2540 /* 2541 * User requested HPT resize, but this host can't supply it. Bail out 2542 */ 2543 error_report_err(resize_hpt_err); 2544 exit(1); 2545 } 2546 2547 spapr->rma_size = node0_size; 2548 2549 /* With KVM, we don't actually know whether KVM supports an 2550 * unbounded RMA (PR KVM) or is limited by the hash table size 2551 * (HV KVM using VRMA), so we always assume the latter 2552 * 2553 * In that case, we also limit the initial allocations for RTAS 2554 * etc... to 256M since we have no way to know what the VRMA size 2555 * is going to be as it depends on the size of the hash table 2556 * which isn't determined yet. 2557 */ 2558 if (kvm_enabled()) { 2559 spapr->vrma_adjust = 1; 2560 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2561 } 2562 2563 /* Actually we don't support unbounded RMA anymore since we added 2564 * proper emulation of HV mode. The max we can get is 16G which 2565 * also happens to be what we configure for PAPR mode so make sure 2566 * we don't do anything bigger than that 2567 */ 2568 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2569 2570 if (spapr->rma_size > node0_size) { 2571 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2572 spapr->rma_size); 2573 exit(1); 2574 } 2575 2576 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2577 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2578 2579 /* Set up Interrupt Controller before we create the VCPUs */ 2580 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); 2581 2582 /* Set up containers for ibm,client-architecture-support negotiated options 2583 */ 2584 spapr->ov5 = spapr_ovec_new(); 2585 spapr->ov5_cas = spapr_ovec_new(); 2586 2587 if (smc->dr_lmb_enabled) { 2588 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2589 spapr_validate_node_memory(machine, &error_fatal); 2590 } 2591 2592 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2593 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) { 2594 /* KVM and TCG always allow GTSE with radix... */ 2595 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2596 } 2597 /* ... but not with hash (currently). */ 2598 2599 /* advertise support for dedicated HP event source to guests */ 2600 if (spapr->use_hotplug_event_source) { 2601 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2602 } 2603 2604 /* advertise support for HPT resizing */ 2605 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2606 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2607 } 2608 2609 /* advertise support for ibm,dyamic-memory-v2 */ 2610 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2611 2612 /* init CPUs */ 2613 spapr_init_cpus(spapr); 2614 2615 if (kvm_enabled()) { 2616 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2617 kvmppc_enable_logical_ci_hcalls(); 2618 kvmppc_enable_set_mode_hcall(); 2619 2620 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2621 kvmppc_enable_clear_ref_mod_hcalls(); 2622 } 2623 2624 /* allocate RAM */ 2625 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2626 machine->ram_size); 2627 memory_region_add_subregion(sysmem, 0, ram); 2628 2629 /* initialize hotplug memory address space */ 2630 if (machine->ram_size < machine->maxram_size) { 2631 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2632 /* 2633 * Limit the number of hotpluggable memory slots to half the number 2634 * slots that KVM supports, leaving the other half for PCI and other 2635 * devices. However ensure that number of slots doesn't drop below 32. 2636 */ 2637 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2638 SPAPR_MAX_RAM_SLOTS; 2639 2640 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2641 max_memslots = SPAPR_MAX_RAM_SLOTS; 2642 } 2643 if (machine->ram_slots > max_memslots) { 2644 error_report("Specified number of memory slots %" 2645 PRIu64" exceeds max supported %d", 2646 machine->ram_slots, max_memslots); 2647 exit(1); 2648 } 2649 2650 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2651 SPAPR_HOTPLUG_MEM_ALIGN); 2652 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2653 "hotplug-memory", hotplug_mem_size); 2654 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2655 &spapr->hotplug_memory.mr); 2656 } 2657 2658 if (smc->dr_lmb_enabled) { 2659 spapr_create_lmb_dr_connectors(spapr); 2660 } 2661 2662 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2663 if (!filename) { 2664 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2665 exit(1); 2666 } 2667 spapr->rtas_size = get_image_size(filename); 2668 if (spapr->rtas_size < 0) { 2669 error_report("Could not get size of LPAR rtas '%s'", filename); 2670 exit(1); 2671 } 2672 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2673 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2674 error_report("Could not load LPAR rtas '%s'", filename); 2675 exit(1); 2676 } 2677 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2678 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2679 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2680 exit(1); 2681 } 2682 g_free(filename); 2683 2684 /* Set up RTAS event infrastructure */ 2685 spapr_events_init(spapr); 2686 2687 /* Set up the RTC RTAS interfaces */ 2688 spapr_rtc_create(spapr); 2689 2690 /* Set up VIO bus */ 2691 spapr->vio_bus = spapr_vio_bus_init(); 2692 2693 for (i = 0; i < serial_max_hds(); i++) { 2694 if (serial_hd(i)) { 2695 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2696 } 2697 } 2698 2699 /* We always have at least the nvram device on VIO */ 2700 spapr_create_nvram(spapr); 2701 2702 /* Set up PCI */ 2703 spapr_pci_rtas_init(); 2704 2705 phb = spapr_create_phb(spapr, 0); 2706 2707 for (i = 0; i < nb_nics; i++) { 2708 NICInfo *nd = &nd_table[i]; 2709 2710 if (!nd->model) { 2711 nd->model = g_strdup("spapr-vlan"); 2712 } 2713 2714 if (g_str_equal(nd->model, "spapr-vlan") || 2715 g_str_equal(nd->model, "ibmveth")) { 2716 spapr_vlan_create(spapr->vio_bus, nd); 2717 } else { 2718 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2719 } 2720 } 2721 2722 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2723 spapr_vscsi_create(spapr->vio_bus); 2724 } 2725 2726 /* Graphics */ 2727 if (spapr_vga_init(phb->bus, &error_fatal)) { 2728 spapr->has_graphics = true; 2729 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2730 } 2731 2732 if (machine->usb) { 2733 if (smc->use_ohci_by_default) { 2734 pci_create_simple(phb->bus, -1, "pci-ohci"); 2735 } else { 2736 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2737 } 2738 2739 if (spapr->has_graphics) { 2740 USBBus *usb_bus = usb_bus_find(-1); 2741 2742 usb_create_simple(usb_bus, "usb-kbd"); 2743 usb_create_simple(usb_bus, "usb-mouse"); 2744 } 2745 } 2746 2747 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2748 error_report( 2749 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2750 MIN_RMA_SLOF); 2751 exit(1); 2752 } 2753 2754 if (kernel_filename) { 2755 uint64_t lowaddr = 0; 2756 2757 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2758 NULL, NULL, &lowaddr, NULL, 1, 2759 PPC_ELF_MACHINE, 0, 0); 2760 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2761 spapr->kernel_size = load_elf(kernel_filename, 2762 translate_kernel_address, NULL, NULL, 2763 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2764 0, 0); 2765 spapr->kernel_le = spapr->kernel_size > 0; 2766 } 2767 if (spapr->kernel_size < 0) { 2768 error_report("error loading %s: %s", kernel_filename, 2769 load_elf_strerror(spapr->kernel_size)); 2770 exit(1); 2771 } 2772 2773 /* load initrd */ 2774 if (initrd_filename) { 2775 /* Try to locate the initrd in the gap between the kernel 2776 * and the firmware. Add a bit of space just in case 2777 */ 2778 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2779 + 0x1ffff) & ~0xffff; 2780 spapr->initrd_size = load_image_targphys(initrd_filename, 2781 spapr->initrd_base, 2782 load_limit 2783 - spapr->initrd_base); 2784 if (spapr->initrd_size < 0) { 2785 error_report("could not load initial ram disk '%s'", 2786 initrd_filename); 2787 exit(1); 2788 } 2789 } 2790 } 2791 2792 if (bios_name == NULL) { 2793 bios_name = FW_FILE_NAME; 2794 } 2795 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2796 if (!filename) { 2797 error_report("Could not find LPAR firmware '%s'", bios_name); 2798 exit(1); 2799 } 2800 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2801 if (fw_size <= 0) { 2802 error_report("Could not load LPAR firmware '%s'", filename); 2803 exit(1); 2804 } 2805 g_free(filename); 2806 2807 /* FIXME: Should register things through the MachineState's qdev 2808 * interface, this is a legacy from the sPAPREnvironment structure 2809 * which predated MachineState but had a similar function */ 2810 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2811 register_savevm_live(NULL, "spapr/htab", -1, 1, 2812 &savevm_htab_handlers, spapr); 2813 2814 qemu_register_boot_set(spapr_boot_set, spapr); 2815 2816 if (kvm_enabled()) { 2817 /* to stop and start vmclock */ 2818 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2819 &spapr->tb); 2820 2821 kvmppc_spapr_enable_inkernel_multitce(); 2822 } 2823 } 2824 2825 static int spapr_kvm_type(const char *vm_type) 2826 { 2827 if (!vm_type) { 2828 return 0; 2829 } 2830 2831 if (!strcmp(vm_type, "HV")) { 2832 return 1; 2833 } 2834 2835 if (!strcmp(vm_type, "PR")) { 2836 return 2; 2837 } 2838 2839 error_report("Unknown kvm-type specified '%s'", vm_type); 2840 exit(1); 2841 } 2842 2843 /* 2844 * Implementation of an interface to adjust firmware path 2845 * for the bootindex property handling. 2846 */ 2847 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2848 DeviceState *dev) 2849 { 2850 #define CAST(type, obj, name) \ 2851 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2852 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2853 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2854 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 2855 2856 if (d) { 2857 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2858 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2859 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2860 2861 if (spapr) { 2862 /* 2863 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2864 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2865 * in the top 16 bits of the 64-bit LUN 2866 */ 2867 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2868 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2869 (uint64_t)id << 48); 2870 } else if (virtio) { 2871 /* 2872 * We use SRP luns of the form 01000000 | (target << 8) | lun 2873 * in the top 32 bits of the 64-bit LUN 2874 * Note: the quote above is from SLOF and it is wrong, 2875 * the actual binding is: 2876 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2877 */ 2878 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2879 if (d->lun >= 256) { 2880 /* Use the LUN "flat space addressing method" */ 2881 id |= 0x4000; 2882 } 2883 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2884 (uint64_t)id << 32); 2885 } else if (usb) { 2886 /* 2887 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2888 * in the top 32 bits of the 64-bit LUN 2889 */ 2890 unsigned usb_port = atoi(usb->port->path); 2891 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2892 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2893 (uint64_t)id << 32); 2894 } 2895 } 2896 2897 /* 2898 * SLOF probes the USB devices, and if it recognizes that the device is a 2899 * storage device, it changes its name to "storage" instead of "usb-host", 2900 * and additionally adds a child node for the SCSI LUN, so the correct 2901 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2902 */ 2903 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2904 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2905 if (usb_host_dev_is_scsi_storage(usbdev)) { 2906 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2907 } 2908 } 2909 2910 if (phb) { 2911 /* Replace "pci" with "pci@800000020000000" */ 2912 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2913 } 2914 2915 if (vsc) { 2916 /* Same logic as virtio above */ 2917 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 2918 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 2919 } 2920 2921 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 2922 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 2923 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 2924 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 2925 } 2926 2927 return NULL; 2928 } 2929 2930 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2931 { 2932 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2933 2934 return g_strdup(spapr->kvm_type); 2935 } 2936 2937 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2938 { 2939 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2940 2941 g_free(spapr->kvm_type); 2942 spapr->kvm_type = g_strdup(value); 2943 } 2944 2945 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2946 { 2947 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2948 2949 return spapr->use_hotplug_event_source; 2950 } 2951 2952 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2953 Error **errp) 2954 { 2955 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2956 2957 spapr->use_hotplug_event_source = value; 2958 } 2959 2960 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 2961 { 2962 return true; 2963 } 2964 2965 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 2966 { 2967 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2968 2969 switch (spapr->resize_hpt) { 2970 case SPAPR_RESIZE_HPT_DEFAULT: 2971 return g_strdup("default"); 2972 case SPAPR_RESIZE_HPT_DISABLED: 2973 return g_strdup("disabled"); 2974 case SPAPR_RESIZE_HPT_ENABLED: 2975 return g_strdup("enabled"); 2976 case SPAPR_RESIZE_HPT_REQUIRED: 2977 return g_strdup("required"); 2978 } 2979 g_assert_not_reached(); 2980 } 2981 2982 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 2983 { 2984 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2985 2986 if (strcmp(value, "default") == 0) { 2987 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 2988 } else if (strcmp(value, "disabled") == 0) { 2989 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2990 } else if (strcmp(value, "enabled") == 0) { 2991 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 2992 } else if (strcmp(value, "required") == 0) { 2993 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 2994 } else { 2995 error_setg(errp, "Bad value for \"resize-hpt\" property"); 2996 } 2997 } 2998 2999 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3000 void *opaque, Error **errp) 3001 { 3002 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3003 } 3004 3005 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3006 void *opaque, Error **errp) 3007 { 3008 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3009 } 3010 3011 static void spapr_instance_init(Object *obj) 3012 { 3013 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3014 3015 spapr->htab_fd = -1; 3016 spapr->use_hotplug_event_source = true; 3017 object_property_add_str(obj, "kvm-type", 3018 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3019 object_property_set_description(obj, "kvm-type", 3020 "Specifies the KVM virtualization mode (HV, PR)", 3021 NULL); 3022 object_property_add_bool(obj, "modern-hotplug-events", 3023 spapr_get_modern_hotplug_events, 3024 spapr_set_modern_hotplug_events, 3025 NULL); 3026 object_property_set_description(obj, "modern-hotplug-events", 3027 "Use dedicated hotplug event mechanism in" 3028 " place of standard EPOW events when possible" 3029 " (required for memory hot-unplug support)", 3030 NULL); 3031 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3032 "Maximum permitted CPU compatibility mode", 3033 &error_fatal); 3034 3035 object_property_add_str(obj, "resize-hpt", 3036 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3037 object_property_set_description(obj, "resize-hpt", 3038 "Resizing of the Hash Page Table (enabled, disabled, required)", 3039 NULL); 3040 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3041 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3042 object_property_set_description(obj, "vsmt", 3043 "Virtual SMT: KVM behaves as if this were" 3044 " the host's SMT mode", &error_abort); 3045 object_property_add_bool(obj, "vfio-no-msix-emulation", 3046 spapr_get_msix_emulation, NULL, NULL); 3047 } 3048 3049 static void spapr_machine_finalizefn(Object *obj) 3050 { 3051 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3052 3053 g_free(spapr->kvm_type); 3054 } 3055 3056 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3057 { 3058 cpu_synchronize_state(cs); 3059 ppc_cpu_do_system_reset(cs); 3060 } 3061 3062 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3063 { 3064 CPUState *cs; 3065 3066 CPU_FOREACH(cs) { 3067 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3068 } 3069 } 3070 3071 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3072 uint32_t node, bool dedicated_hp_event_source, 3073 Error **errp) 3074 { 3075 sPAPRDRConnector *drc; 3076 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3077 int i, fdt_offset, fdt_size; 3078 void *fdt; 3079 uint64_t addr = addr_start; 3080 bool hotplugged = spapr_drc_hotplugged(dev); 3081 Error *local_err = NULL; 3082 3083 for (i = 0; i < nr_lmbs; i++) { 3084 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3085 addr / SPAPR_MEMORY_BLOCK_SIZE); 3086 g_assert(drc); 3087 3088 fdt = create_device_tree(&fdt_size); 3089 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 3090 SPAPR_MEMORY_BLOCK_SIZE); 3091 3092 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3093 if (local_err) { 3094 while (addr > addr_start) { 3095 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3096 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3097 addr / SPAPR_MEMORY_BLOCK_SIZE); 3098 spapr_drc_detach(drc); 3099 } 3100 g_free(fdt); 3101 error_propagate(errp, local_err); 3102 return; 3103 } 3104 if (!hotplugged) { 3105 spapr_drc_reset(drc); 3106 } 3107 addr += SPAPR_MEMORY_BLOCK_SIZE; 3108 } 3109 /* send hotplug notification to the 3110 * guest only in case of hotplugged memory 3111 */ 3112 if (hotplugged) { 3113 if (dedicated_hp_event_source) { 3114 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3115 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3116 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3117 nr_lmbs, 3118 spapr_drc_index(drc)); 3119 } else { 3120 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3121 nr_lmbs); 3122 } 3123 } 3124 } 3125 3126 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3127 uint32_t node, Error **errp) 3128 { 3129 Error *local_err = NULL; 3130 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3131 PCDIMMDevice *dimm = PC_DIMM(dev); 3132 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3133 MemoryRegion *mr; 3134 uint64_t align, size, addr; 3135 3136 mr = ddc->get_memory_region(dimm, &local_err); 3137 if (local_err) { 3138 goto out; 3139 } 3140 align = memory_region_get_alignment(mr); 3141 size = memory_region_size(mr); 3142 3143 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 3144 if (local_err) { 3145 goto out; 3146 } 3147 3148 addr = object_property_get_uint(OBJECT(dimm), 3149 PC_DIMM_ADDR_PROP, &local_err); 3150 if (local_err) { 3151 goto out_unplug; 3152 } 3153 3154 spapr_add_lmbs(dev, addr, size, node, 3155 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3156 &local_err); 3157 if (local_err) { 3158 goto out_unplug; 3159 } 3160 3161 return; 3162 3163 out_unplug: 3164 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 3165 out: 3166 error_propagate(errp, local_err); 3167 } 3168 3169 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3170 Error **errp) 3171 { 3172 PCDIMMDevice *dimm = PC_DIMM(dev); 3173 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3174 MemoryRegion *mr; 3175 uint64_t size; 3176 char *mem_dev; 3177 3178 mr = ddc->get_memory_region(dimm, errp); 3179 if (!mr) { 3180 return; 3181 } 3182 size = memory_region_size(mr); 3183 3184 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3185 error_setg(errp, "Hotplugged memory size must be a multiple of " 3186 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 3187 return; 3188 } 3189 3190 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 3191 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 3192 error_setg(errp, "Memory backend has bad page size. " 3193 "Use 'memory-backend-file' with correct mem-path."); 3194 goto out; 3195 } 3196 3197 out: 3198 g_free(mem_dev); 3199 } 3200 3201 struct sPAPRDIMMState { 3202 PCDIMMDevice *dimm; 3203 uint32_t nr_lmbs; 3204 QTAILQ_ENTRY(sPAPRDIMMState) next; 3205 }; 3206 3207 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 3208 PCDIMMDevice *dimm) 3209 { 3210 sPAPRDIMMState *dimm_state = NULL; 3211 3212 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3213 if (dimm_state->dimm == dimm) { 3214 break; 3215 } 3216 } 3217 return dimm_state; 3218 } 3219 3220 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 3221 uint32_t nr_lmbs, 3222 PCDIMMDevice *dimm) 3223 { 3224 sPAPRDIMMState *ds = NULL; 3225 3226 /* 3227 * If this request is for a DIMM whose removal had failed earlier 3228 * (due to guest's refusal to remove the LMBs), we would have this 3229 * dimm already in the pending_dimm_unplugs list. In that 3230 * case don't add again. 3231 */ 3232 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3233 if (!ds) { 3234 ds = g_malloc0(sizeof(sPAPRDIMMState)); 3235 ds->nr_lmbs = nr_lmbs; 3236 ds->dimm = dimm; 3237 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3238 } 3239 return ds; 3240 } 3241 3242 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 3243 sPAPRDIMMState *dimm_state) 3244 { 3245 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3246 g_free(dimm_state); 3247 } 3248 3249 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 3250 PCDIMMDevice *dimm) 3251 { 3252 sPAPRDRConnector *drc; 3253 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3254 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3255 uint64_t size = memory_region_size(mr); 3256 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3257 uint32_t avail_lmbs = 0; 3258 uint64_t addr_start, addr; 3259 int i; 3260 3261 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3262 &error_abort); 3263 3264 addr = addr_start; 3265 for (i = 0; i < nr_lmbs; i++) { 3266 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3267 addr / SPAPR_MEMORY_BLOCK_SIZE); 3268 g_assert(drc); 3269 if (drc->dev) { 3270 avail_lmbs++; 3271 } 3272 addr += SPAPR_MEMORY_BLOCK_SIZE; 3273 } 3274 3275 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3276 } 3277 3278 /* Callback to be called during DRC release. */ 3279 void spapr_lmb_release(DeviceState *dev) 3280 { 3281 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_hotplug_handler(dev)); 3282 PCDIMMDevice *dimm = PC_DIMM(dev); 3283 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3284 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3285 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3286 3287 /* This information will get lost if a migration occurs 3288 * during the unplug process. In this case recover it. */ 3289 if (ds == NULL) { 3290 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3291 g_assert(ds); 3292 /* The DRC being examined by the caller at least must be counted */ 3293 g_assert(ds->nr_lmbs); 3294 } 3295 3296 if (--ds->nr_lmbs) { 3297 return; 3298 } 3299 3300 /* 3301 * Now that all the LMBs have been removed by the guest, call the 3302 * pc-dimm unplug handler to cleanup up the pc-dimm device. 3303 */ 3304 pc_dimm_memory_unplug(dev, &spapr->hotplug_memory, mr); 3305 object_unparent(OBJECT(dev)); 3306 spapr_pending_dimm_unplugs_remove(spapr, ds); 3307 } 3308 3309 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3310 DeviceState *dev, Error **errp) 3311 { 3312 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3313 Error *local_err = NULL; 3314 PCDIMMDevice *dimm = PC_DIMM(dev); 3315 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3316 MemoryRegion *mr; 3317 uint32_t nr_lmbs; 3318 uint64_t size, addr_start, addr; 3319 int i; 3320 sPAPRDRConnector *drc; 3321 3322 mr = ddc->get_memory_region(dimm, &local_err); 3323 if (local_err) { 3324 goto out; 3325 } 3326 size = memory_region_size(mr); 3327 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3328 3329 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3330 &local_err); 3331 if (local_err) { 3332 goto out; 3333 } 3334 3335 /* 3336 * An existing pending dimm state for this DIMM means that there is an 3337 * unplug operation in progress, waiting for the spapr_lmb_release 3338 * callback to complete the job (BQL can't cover that far). In this case, 3339 * bail out to avoid detaching DRCs that were already released. 3340 */ 3341 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3342 error_setg(&local_err, 3343 "Memory unplug already in progress for device %s", 3344 dev->id); 3345 goto out; 3346 } 3347 3348 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3349 3350 addr = addr_start; 3351 for (i = 0; i < nr_lmbs; i++) { 3352 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3353 addr / SPAPR_MEMORY_BLOCK_SIZE); 3354 g_assert(drc); 3355 3356 spapr_drc_detach(drc); 3357 addr += SPAPR_MEMORY_BLOCK_SIZE; 3358 } 3359 3360 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3361 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3362 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3363 nr_lmbs, spapr_drc_index(drc)); 3364 out: 3365 error_propagate(errp, local_err); 3366 } 3367 3368 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 3369 sPAPRMachineState *spapr) 3370 { 3371 PowerPCCPU *cpu = POWERPC_CPU(cs); 3372 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3373 int id = spapr_get_vcpu_id(cpu); 3374 void *fdt; 3375 int offset, fdt_size; 3376 char *nodename; 3377 3378 fdt = create_device_tree(&fdt_size); 3379 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3380 offset = fdt_add_subnode(fdt, 0, nodename); 3381 3382 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3383 g_free(nodename); 3384 3385 *fdt_offset = offset; 3386 return fdt; 3387 } 3388 3389 /* Callback to be called during DRC release. */ 3390 void spapr_core_release(DeviceState *dev) 3391 { 3392 MachineState *ms = MACHINE(qdev_get_hotplug_handler(dev)); 3393 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3394 CPUCore *cc = CPU_CORE(dev); 3395 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3396 3397 if (smc->pre_2_10_has_unused_icps) { 3398 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3399 int i; 3400 3401 for (i = 0; i < cc->nr_threads; i++) { 3402 CPUState *cs = CPU(sc->threads[i]); 3403 3404 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3405 } 3406 } 3407 3408 assert(core_slot); 3409 core_slot->cpu = NULL; 3410 object_unparent(OBJECT(dev)); 3411 } 3412 3413 static 3414 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3415 Error **errp) 3416 { 3417 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3418 int index; 3419 sPAPRDRConnector *drc; 3420 CPUCore *cc = CPU_CORE(dev); 3421 3422 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3423 error_setg(errp, "Unable to find CPU core with core-id: %d", 3424 cc->core_id); 3425 return; 3426 } 3427 if (index == 0) { 3428 error_setg(errp, "Boot CPU core may not be unplugged"); 3429 return; 3430 } 3431 3432 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3433 spapr_vcpu_id(spapr, cc->core_id)); 3434 g_assert(drc); 3435 3436 spapr_drc_detach(drc); 3437 3438 spapr_hotplug_req_remove_by_index(drc); 3439 } 3440 3441 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3442 Error **errp) 3443 { 3444 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3445 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3446 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3447 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3448 CPUCore *cc = CPU_CORE(dev); 3449 CPUState *cs = CPU(core->threads[0]); 3450 sPAPRDRConnector *drc; 3451 Error *local_err = NULL; 3452 CPUArchId *core_slot; 3453 int index; 3454 bool hotplugged = spapr_drc_hotplugged(dev); 3455 3456 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3457 if (!core_slot) { 3458 error_setg(errp, "Unable to find CPU core with core-id: %d", 3459 cc->core_id); 3460 return; 3461 } 3462 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3463 spapr_vcpu_id(spapr, cc->core_id)); 3464 3465 g_assert(drc || !mc->has_hotpluggable_cpus); 3466 3467 if (drc) { 3468 void *fdt; 3469 int fdt_offset; 3470 3471 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 3472 3473 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3474 if (local_err) { 3475 g_free(fdt); 3476 error_propagate(errp, local_err); 3477 return; 3478 } 3479 3480 if (hotplugged) { 3481 /* 3482 * Send hotplug notification interrupt to the guest only 3483 * in case of hotplugged CPUs. 3484 */ 3485 spapr_hotplug_req_add_by_index(drc); 3486 } else { 3487 spapr_drc_reset(drc); 3488 } 3489 } 3490 3491 core_slot->cpu = OBJECT(dev); 3492 3493 if (smc->pre_2_10_has_unused_icps) { 3494 int i; 3495 3496 for (i = 0; i < cc->nr_threads; i++) { 3497 cs = CPU(core->threads[i]); 3498 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3499 } 3500 } 3501 } 3502 3503 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3504 Error **errp) 3505 { 3506 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3507 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3508 Error *local_err = NULL; 3509 CPUCore *cc = CPU_CORE(dev); 3510 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3511 const char *type = object_get_typename(OBJECT(dev)); 3512 CPUArchId *core_slot; 3513 int index; 3514 3515 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3516 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3517 goto out; 3518 } 3519 3520 if (strcmp(base_core_type, type)) { 3521 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3522 goto out; 3523 } 3524 3525 if (cc->core_id % smp_threads) { 3526 error_setg(&local_err, "invalid core id %d", cc->core_id); 3527 goto out; 3528 } 3529 3530 /* 3531 * In general we should have homogeneous threads-per-core, but old 3532 * (pre hotplug support) machine types allow the last core to have 3533 * reduced threads as a compatibility hack for when we allowed 3534 * total vcpus not a multiple of threads-per-core. 3535 */ 3536 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3537 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3538 cc->nr_threads, smp_threads); 3539 goto out; 3540 } 3541 3542 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3543 if (!core_slot) { 3544 error_setg(&local_err, "core id %d out of range", cc->core_id); 3545 goto out; 3546 } 3547 3548 if (core_slot->cpu) { 3549 error_setg(&local_err, "core %d already populated", cc->core_id); 3550 goto out; 3551 } 3552 3553 numa_cpu_pre_plug(core_slot, dev, &local_err); 3554 3555 out: 3556 error_propagate(errp, local_err); 3557 } 3558 3559 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3560 DeviceState *dev, Error **errp) 3561 { 3562 MachineState *ms = MACHINE(hotplug_dev); 3563 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3564 3565 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3566 int node; 3567 3568 if (!smc->dr_lmb_enabled) { 3569 error_setg(errp, "Memory hotplug not supported for this machine"); 3570 return; 3571 } 3572 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 3573 if (*errp) { 3574 return; 3575 } 3576 if (node < 0 || node >= MAX_NODES) { 3577 error_setg(errp, "Invaild node %d", node); 3578 return; 3579 } 3580 3581 spapr_memory_plug(hotplug_dev, dev, node, errp); 3582 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3583 spapr_core_plug(hotplug_dev, dev, errp); 3584 } 3585 } 3586 3587 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3588 DeviceState *dev, Error **errp) 3589 { 3590 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3591 MachineClass *mc = MACHINE_GET_CLASS(sms); 3592 3593 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3594 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3595 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3596 } else { 3597 /* NOTE: this means there is a window after guest reset, prior to 3598 * CAS negotiation, where unplug requests will fail due to the 3599 * capability not being detected yet. This is a bit different than 3600 * the case with PCI unplug, where the events will be queued and 3601 * eventually handled by the guest after boot 3602 */ 3603 error_setg(errp, "Memory hot unplug not supported for this guest"); 3604 } 3605 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3606 if (!mc->has_hotpluggable_cpus) { 3607 error_setg(errp, "CPU hot unplug not supported on this machine"); 3608 return; 3609 } 3610 spapr_core_unplug_request(hotplug_dev, dev, errp); 3611 } 3612 } 3613 3614 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3615 DeviceState *dev, Error **errp) 3616 { 3617 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3618 spapr_memory_pre_plug(hotplug_dev, dev, errp); 3619 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3620 spapr_core_pre_plug(hotplug_dev, dev, errp); 3621 } 3622 } 3623 3624 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3625 DeviceState *dev) 3626 { 3627 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3628 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3629 return HOTPLUG_HANDLER(machine); 3630 } 3631 return NULL; 3632 } 3633 3634 static CpuInstanceProperties 3635 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3636 { 3637 CPUArchId *core_slot; 3638 MachineClass *mc = MACHINE_GET_CLASS(machine); 3639 3640 /* make sure possible_cpu are intialized */ 3641 mc->possible_cpu_arch_ids(machine); 3642 /* get CPU core slot containing thread that matches cpu_index */ 3643 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3644 assert(core_slot); 3645 return core_slot->props; 3646 } 3647 3648 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 3649 { 3650 return idx / smp_cores % nb_numa_nodes; 3651 } 3652 3653 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3654 { 3655 int i; 3656 const char *core_type; 3657 int spapr_max_cores = max_cpus / smp_threads; 3658 MachineClass *mc = MACHINE_GET_CLASS(machine); 3659 3660 if (!mc->has_hotpluggable_cpus) { 3661 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3662 } 3663 if (machine->possible_cpus) { 3664 assert(machine->possible_cpus->len == spapr_max_cores); 3665 return machine->possible_cpus; 3666 } 3667 3668 core_type = spapr_get_cpu_core_type(machine->cpu_type); 3669 if (!core_type) { 3670 error_report("Unable to find sPAPR CPU Core definition"); 3671 exit(1); 3672 } 3673 3674 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3675 sizeof(CPUArchId) * spapr_max_cores); 3676 machine->possible_cpus->len = spapr_max_cores; 3677 for (i = 0; i < machine->possible_cpus->len; i++) { 3678 int core_id = i * smp_threads; 3679 3680 machine->possible_cpus->cpus[i].type = core_type; 3681 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3682 machine->possible_cpus->cpus[i].arch_id = core_id; 3683 machine->possible_cpus->cpus[i].props.has_core_id = true; 3684 machine->possible_cpus->cpus[i].props.core_id = core_id; 3685 } 3686 return machine->possible_cpus; 3687 } 3688 3689 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3690 uint64_t *buid, hwaddr *pio, 3691 hwaddr *mmio32, hwaddr *mmio64, 3692 unsigned n_dma, uint32_t *liobns, Error **errp) 3693 { 3694 /* 3695 * New-style PHB window placement. 3696 * 3697 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3698 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3699 * windows. 3700 * 3701 * Some guest kernels can't work with MMIO windows above 1<<46 3702 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3703 * 3704 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3705 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3706 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3707 * 1TiB 64-bit MMIO windows for each PHB. 3708 */ 3709 const uint64_t base_buid = 0x800000020000000ULL; 3710 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3711 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3712 int i; 3713 3714 /* Sanity check natural alignments */ 3715 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3716 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3717 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3718 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3719 /* Sanity check bounds */ 3720 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3721 SPAPR_PCI_MEM32_WIN_SIZE); 3722 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3723 SPAPR_PCI_MEM64_WIN_SIZE); 3724 3725 if (index >= SPAPR_MAX_PHBS) { 3726 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3727 SPAPR_MAX_PHBS - 1); 3728 return; 3729 } 3730 3731 *buid = base_buid + index; 3732 for (i = 0; i < n_dma; ++i) { 3733 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3734 } 3735 3736 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3737 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3738 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3739 } 3740 3741 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3742 { 3743 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3744 3745 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3746 } 3747 3748 static void spapr_ics_resend(XICSFabric *dev) 3749 { 3750 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3751 3752 ics_resend(spapr->ics); 3753 } 3754 3755 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 3756 { 3757 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 3758 3759 return cpu ? ICP(cpu->intc) : NULL; 3760 } 3761 3762 #define ICS_IRQ_FREE(ics, srcno) \ 3763 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) 3764 3765 static int ics_find_free_block(ICSState *ics, int num, int alignnum) 3766 { 3767 int first, i; 3768 3769 for (first = 0; first < ics->nr_irqs; first += alignnum) { 3770 if (num > (ics->nr_irqs - first)) { 3771 return -1; 3772 } 3773 for (i = first; i < first + num; ++i) { 3774 if (!ICS_IRQ_FREE(ics, i)) { 3775 break; 3776 } 3777 } 3778 if (i == (first + num)) { 3779 return first; 3780 } 3781 } 3782 3783 return -1; 3784 } 3785 3786 /* 3787 * Allocate the IRQ number and set the IRQ type, LSI or MSI 3788 */ 3789 static void spapr_irq_set_lsi(sPAPRMachineState *spapr, int irq, bool lsi) 3790 { 3791 ics_set_irq_type(spapr->ics, irq - spapr->ics->offset, lsi); 3792 } 3793 3794 int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi, 3795 Error **errp) 3796 { 3797 ICSState *ics = spapr->ics; 3798 int irq; 3799 3800 assert(ics); 3801 3802 if (irq_hint) { 3803 if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) { 3804 error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint); 3805 return -1; 3806 } 3807 irq = irq_hint; 3808 } else { 3809 irq = ics_find_free_block(ics, 1, 1); 3810 if (irq < 0) { 3811 error_setg(errp, "can't allocate IRQ: no IRQ left"); 3812 return -1; 3813 } 3814 irq += ics->offset; 3815 } 3816 3817 spapr_irq_set_lsi(spapr, irq, lsi); 3818 trace_spapr_irq_alloc(irq); 3819 3820 return irq; 3821 } 3822 3823 /* 3824 * Allocate block of consecutive IRQs, and return the number of the first IRQ in 3825 * the block. If align==true, aligns the first IRQ number to num. 3826 */ 3827 int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi, 3828 bool align, Error **errp) 3829 { 3830 ICSState *ics = spapr->ics; 3831 int i, first = -1; 3832 3833 assert(ics); 3834 3835 /* 3836 * MSIMesage::data is used for storing VIRQ so 3837 * it has to be aligned to num to support multiple 3838 * MSI vectors. MSI-X is not affected by this. 3839 * The hint is used for the first IRQ, the rest should 3840 * be allocated continuously. 3841 */ 3842 if (align) { 3843 assert((num == 1) || (num == 2) || (num == 4) || 3844 (num == 8) || (num == 16) || (num == 32)); 3845 first = ics_find_free_block(ics, num, num); 3846 } else { 3847 first = ics_find_free_block(ics, num, 1); 3848 } 3849 if (first < 0) { 3850 error_setg(errp, "can't find a free %d-IRQ block", num); 3851 return -1; 3852 } 3853 3854 first += ics->offset; 3855 for (i = first; i < first + num; ++i) { 3856 spapr_irq_set_lsi(spapr, i, lsi); 3857 } 3858 3859 trace_spapr_irq_alloc_block(first, num, lsi, align); 3860 3861 return first; 3862 } 3863 3864 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num) 3865 { 3866 ICSState *ics = spapr->ics; 3867 int srcno = irq - ics->offset; 3868 int i; 3869 3870 if (ics_valid_irq(ics, irq)) { 3871 trace_spapr_irq_free(0, irq, num); 3872 for (i = srcno; i < srcno + num; ++i) { 3873 if (ICS_IRQ_FREE(ics, i)) { 3874 trace_spapr_irq_free_warn(0, i + ics->offset); 3875 } 3876 memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); 3877 } 3878 } 3879 } 3880 3881 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq) 3882 { 3883 ICSState *ics = spapr->ics; 3884 3885 if (ics_valid_irq(ics, irq)) { 3886 return ics->qirqs[irq - ics->offset]; 3887 } 3888 3889 return NULL; 3890 } 3891 3892 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3893 Monitor *mon) 3894 { 3895 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3896 CPUState *cs; 3897 3898 CPU_FOREACH(cs) { 3899 PowerPCCPU *cpu = POWERPC_CPU(cs); 3900 3901 icp_pic_print_info(ICP(cpu->intc), mon); 3902 } 3903 3904 ics_pic_print_info(spapr->ics, mon); 3905 } 3906 3907 int spapr_get_vcpu_id(PowerPCCPU *cpu) 3908 { 3909 return cpu->vcpu_id; 3910 } 3911 3912 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 3913 { 3914 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3915 int vcpu_id; 3916 3917 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 3918 3919 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 3920 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 3921 error_append_hint(errp, "Adjust the number of cpus to %d " 3922 "or try to raise the number of threads per core\n", 3923 vcpu_id * smp_threads / spapr->vsmt); 3924 return; 3925 } 3926 3927 cpu->vcpu_id = vcpu_id; 3928 } 3929 3930 PowerPCCPU *spapr_find_cpu(int vcpu_id) 3931 { 3932 CPUState *cs; 3933 3934 CPU_FOREACH(cs) { 3935 PowerPCCPU *cpu = POWERPC_CPU(cs); 3936 3937 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 3938 return cpu; 3939 } 3940 } 3941 3942 return NULL; 3943 } 3944 3945 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3946 { 3947 MachineClass *mc = MACHINE_CLASS(oc); 3948 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3949 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3950 NMIClass *nc = NMI_CLASS(oc); 3951 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3952 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3953 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3954 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3955 3956 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3957 3958 /* 3959 * We set up the default / latest behaviour here. The class_init 3960 * functions for the specific versioned machine types can override 3961 * these details for backwards compatibility 3962 */ 3963 mc->init = spapr_machine_init; 3964 mc->reset = spapr_machine_reset; 3965 mc->block_default_type = IF_SCSI; 3966 mc->max_cpus = 1024; 3967 mc->no_parallel = 1; 3968 mc->default_boot_order = ""; 3969 mc->default_ram_size = 512 * M_BYTE; 3970 mc->kvm_type = spapr_kvm_type; 3971 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 3972 mc->pci_allow_0_address = true; 3973 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3974 hc->pre_plug = spapr_machine_device_pre_plug; 3975 hc->plug = spapr_machine_device_plug; 3976 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 3977 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 3978 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3979 hc->unplug_request = spapr_machine_device_unplug_request; 3980 3981 smc->dr_lmb_enabled = true; 3982 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 3983 mc->has_hotpluggable_cpus = true; 3984 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 3985 fwc->get_dev_path = spapr_get_fw_dev_path; 3986 nc->nmi_monitor_handler = spapr_nmi; 3987 smc->phb_placement = spapr_phb_placement; 3988 vhc->hypercall = emulate_spapr_hypercall; 3989 vhc->hpt_mask = spapr_hpt_mask; 3990 vhc->map_hptes = spapr_map_hptes; 3991 vhc->unmap_hptes = spapr_unmap_hptes; 3992 vhc->store_hpte = spapr_store_hpte; 3993 vhc->get_patbe = spapr_get_patbe; 3994 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 3995 xic->ics_get = spapr_ics_get; 3996 xic->ics_resend = spapr_ics_resend; 3997 xic->icp_get = spapr_icp_get; 3998 ispc->print_info = spapr_pic_print_info; 3999 /* Force NUMA node memory size to be a multiple of 4000 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4001 * in which LMBs are represented and hot-added 4002 */ 4003 mc->numa_mem_align_shift = 28; 4004 4005 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4006 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4007 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4008 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4009 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4010 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4011 spapr_caps_add_properties(smc, &error_abort); 4012 } 4013 4014 static const TypeInfo spapr_machine_info = { 4015 .name = TYPE_SPAPR_MACHINE, 4016 .parent = TYPE_MACHINE, 4017 .abstract = true, 4018 .instance_size = sizeof(sPAPRMachineState), 4019 .instance_init = spapr_instance_init, 4020 .instance_finalize = spapr_machine_finalizefn, 4021 .class_size = sizeof(sPAPRMachineClass), 4022 .class_init = spapr_machine_class_init, 4023 .interfaces = (InterfaceInfo[]) { 4024 { TYPE_FW_PATH_PROVIDER }, 4025 { TYPE_NMI }, 4026 { TYPE_HOTPLUG_HANDLER }, 4027 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4028 { TYPE_XICS_FABRIC }, 4029 { TYPE_INTERRUPT_STATS_PROVIDER }, 4030 { } 4031 }, 4032 }; 4033 4034 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4035 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4036 void *data) \ 4037 { \ 4038 MachineClass *mc = MACHINE_CLASS(oc); \ 4039 spapr_machine_##suffix##_class_options(mc); \ 4040 if (latest) { \ 4041 mc->alias = "pseries"; \ 4042 mc->is_default = 1; \ 4043 } \ 4044 } \ 4045 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 4046 { \ 4047 MachineState *machine = MACHINE(obj); \ 4048 spapr_machine_##suffix##_instance_options(machine); \ 4049 } \ 4050 static const TypeInfo spapr_machine_##suffix##_info = { \ 4051 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4052 .parent = TYPE_SPAPR_MACHINE, \ 4053 .class_init = spapr_machine_##suffix##_class_init, \ 4054 .instance_init = spapr_machine_##suffix##_instance_init, \ 4055 }; \ 4056 static void spapr_machine_register_##suffix(void) \ 4057 { \ 4058 type_register(&spapr_machine_##suffix##_info); \ 4059 } \ 4060 type_init(spapr_machine_register_##suffix) 4061 4062 /* 4063 * pseries-2.13 4064 */ 4065 static void spapr_machine_2_13_instance_options(MachineState *machine) 4066 { 4067 } 4068 4069 static void spapr_machine_2_13_class_options(MachineClass *mc) 4070 { 4071 /* Defaults for the latest behaviour inherited from the base class */ 4072 } 4073 4074 DEFINE_SPAPR_MACHINE(2_13, "2.13", true); 4075 4076 /* 4077 * pseries-2.12 4078 */ 4079 #define SPAPR_COMPAT_2_12 \ 4080 HW_COMPAT_2_12 \ 4081 { \ 4082 .driver = TYPE_POWERPC_CPU, \ 4083 .property = "pre-2.13-migration", \ 4084 .value = "on", \ 4085 }, 4086 4087 static void spapr_machine_2_12_instance_options(MachineState *machine) 4088 { 4089 spapr_machine_2_13_instance_options(machine); 4090 } 4091 4092 static void spapr_machine_2_12_class_options(MachineClass *mc) 4093 { 4094 spapr_machine_2_13_class_options(mc); 4095 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_12); 4096 } 4097 4098 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4099 4100 static void spapr_machine_2_12_sxxm_instance_options(MachineState *machine) 4101 { 4102 spapr_machine_2_12_instance_options(machine); 4103 } 4104 4105 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4106 { 4107 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4108 4109 spapr_machine_2_12_class_options(mc); 4110 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4111 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4112 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4113 } 4114 4115 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4116 4117 /* 4118 * pseries-2.11 4119 */ 4120 #define SPAPR_COMPAT_2_11 \ 4121 HW_COMPAT_2_11 4122 4123 static void spapr_machine_2_11_instance_options(MachineState *machine) 4124 { 4125 spapr_machine_2_12_instance_options(machine); 4126 } 4127 4128 static void spapr_machine_2_11_class_options(MachineClass *mc) 4129 { 4130 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4131 4132 spapr_machine_2_12_class_options(mc); 4133 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4134 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11); 4135 } 4136 4137 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4138 4139 /* 4140 * pseries-2.10 4141 */ 4142 #define SPAPR_COMPAT_2_10 \ 4143 HW_COMPAT_2_10 4144 4145 static void spapr_machine_2_10_instance_options(MachineState *machine) 4146 { 4147 spapr_machine_2_11_instance_options(machine); 4148 } 4149 4150 static void spapr_machine_2_10_class_options(MachineClass *mc) 4151 { 4152 spapr_machine_2_11_class_options(mc); 4153 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10); 4154 } 4155 4156 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4157 4158 /* 4159 * pseries-2.9 4160 */ 4161 #define SPAPR_COMPAT_2_9 \ 4162 HW_COMPAT_2_9 \ 4163 { \ 4164 .driver = TYPE_POWERPC_CPU, \ 4165 .property = "pre-2.10-migration", \ 4166 .value = "on", \ 4167 }, \ 4168 4169 static void spapr_machine_2_9_instance_options(MachineState *machine) 4170 { 4171 spapr_machine_2_10_instance_options(machine); 4172 } 4173 4174 static void spapr_machine_2_9_class_options(MachineClass *mc) 4175 { 4176 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4177 4178 spapr_machine_2_10_class_options(mc); 4179 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); 4180 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4181 smc->pre_2_10_has_unused_icps = true; 4182 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4183 } 4184 4185 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4186 4187 /* 4188 * pseries-2.8 4189 */ 4190 #define SPAPR_COMPAT_2_8 \ 4191 HW_COMPAT_2_8 \ 4192 { \ 4193 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4194 .property = "pcie-extended-configuration-space", \ 4195 .value = "off", \ 4196 }, 4197 4198 static void spapr_machine_2_8_instance_options(MachineState *machine) 4199 { 4200 spapr_machine_2_9_instance_options(machine); 4201 } 4202 4203 static void spapr_machine_2_8_class_options(MachineClass *mc) 4204 { 4205 spapr_machine_2_9_class_options(mc); 4206 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 4207 mc->numa_mem_align_shift = 23; 4208 } 4209 4210 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4211 4212 /* 4213 * pseries-2.7 4214 */ 4215 #define SPAPR_COMPAT_2_7 \ 4216 HW_COMPAT_2_7 \ 4217 { \ 4218 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4219 .property = "mem_win_size", \ 4220 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 4221 }, \ 4222 { \ 4223 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4224 .property = "mem64_win_size", \ 4225 .value = "0", \ 4226 }, \ 4227 { \ 4228 .driver = TYPE_POWERPC_CPU, \ 4229 .property = "pre-2.8-migration", \ 4230 .value = "on", \ 4231 }, \ 4232 { \ 4233 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4234 .property = "pre-2.8-migration", \ 4235 .value = "on", \ 4236 }, 4237 4238 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 4239 uint64_t *buid, hwaddr *pio, 4240 hwaddr *mmio32, hwaddr *mmio64, 4241 unsigned n_dma, uint32_t *liobns, Error **errp) 4242 { 4243 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4244 const uint64_t base_buid = 0x800000020000000ULL; 4245 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4246 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4247 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4248 const uint32_t max_index = 255; 4249 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4250 4251 uint64_t ram_top = MACHINE(spapr)->ram_size; 4252 hwaddr phb0_base, phb_base; 4253 int i; 4254 4255 /* Do we have hotpluggable memory? */ 4256 if (MACHINE(spapr)->maxram_size > ram_top) { 4257 /* Can't just use maxram_size, because there may be an 4258 * alignment gap between normal and hotpluggable memory 4259 * regions */ 4260 ram_top = spapr->hotplug_memory.base + 4261 memory_region_size(&spapr->hotplug_memory.mr); 4262 } 4263 4264 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4265 4266 if (index > max_index) { 4267 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4268 max_index); 4269 return; 4270 } 4271 4272 *buid = base_buid + index; 4273 for (i = 0; i < n_dma; ++i) { 4274 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4275 } 4276 4277 phb_base = phb0_base + index * phb_spacing; 4278 *pio = phb_base + pio_offset; 4279 *mmio32 = phb_base + mmio_offset; 4280 /* 4281 * We don't set the 64-bit MMIO window, relying on the PHB's 4282 * fallback behaviour of automatically splitting a large "32-bit" 4283 * window into contiguous 32-bit and 64-bit windows 4284 */ 4285 } 4286 4287 static void spapr_machine_2_7_instance_options(MachineState *machine) 4288 { 4289 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 4290 4291 spapr_machine_2_8_instance_options(machine); 4292 spapr->use_hotplug_event_source = false; 4293 } 4294 4295 static void spapr_machine_2_7_class_options(MachineClass *mc) 4296 { 4297 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4298 4299 spapr_machine_2_8_class_options(mc); 4300 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4301 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 4302 smc->phb_placement = phb_placement_2_7; 4303 } 4304 4305 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4306 4307 /* 4308 * pseries-2.6 4309 */ 4310 #define SPAPR_COMPAT_2_6 \ 4311 HW_COMPAT_2_6 \ 4312 { \ 4313 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 4314 .property = "ddw",\ 4315 .value = stringify(off),\ 4316 }, 4317 4318 static void spapr_machine_2_6_instance_options(MachineState *machine) 4319 { 4320 spapr_machine_2_7_instance_options(machine); 4321 } 4322 4323 static void spapr_machine_2_6_class_options(MachineClass *mc) 4324 { 4325 spapr_machine_2_7_class_options(mc); 4326 mc->has_hotpluggable_cpus = false; 4327 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 4328 } 4329 4330 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4331 4332 /* 4333 * pseries-2.5 4334 */ 4335 #define SPAPR_COMPAT_2_5 \ 4336 HW_COMPAT_2_5 \ 4337 { \ 4338 .driver = "spapr-vlan", \ 4339 .property = "use-rx-buffer-pools", \ 4340 .value = "off", \ 4341 }, 4342 4343 static void spapr_machine_2_5_instance_options(MachineState *machine) 4344 { 4345 spapr_machine_2_6_instance_options(machine); 4346 } 4347 4348 static void spapr_machine_2_5_class_options(MachineClass *mc) 4349 { 4350 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4351 4352 spapr_machine_2_6_class_options(mc); 4353 smc->use_ohci_by_default = true; 4354 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 4355 } 4356 4357 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4358 4359 /* 4360 * pseries-2.4 4361 */ 4362 #define SPAPR_COMPAT_2_4 \ 4363 HW_COMPAT_2_4 4364 4365 static void spapr_machine_2_4_instance_options(MachineState *machine) 4366 { 4367 spapr_machine_2_5_instance_options(machine); 4368 } 4369 4370 static void spapr_machine_2_4_class_options(MachineClass *mc) 4371 { 4372 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4373 4374 spapr_machine_2_5_class_options(mc); 4375 smc->dr_lmb_enabled = false; 4376 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 4377 } 4378 4379 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4380 4381 /* 4382 * pseries-2.3 4383 */ 4384 #define SPAPR_COMPAT_2_3 \ 4385 HW_COMPAT_2_3 \ 4386 {\ 4387 .driver = "spapr-pci-host-bridge",\ 4388 .property = "dynamic-reconfiguration",\ 4389 .value = "off",\ 4390 }, 4391 4392 static void spapr_machine_2_3_instance_options(MachineState *machine) 4393 { 4394 spapr_machine_2_4_instance_options(machine); 4395 } 4396 4397 static void spapr_machine_2_3_class_options(MachineClass *mc) 4398 { 4399 spapr_machine_2_4_class_options(mc); 4400 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 4401 } 4402 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4403 4404 /* 4405 * pseries-2.2 4406 */ 4407 4408 #define SPAPR_COMPAT_2_2 \ 4409 HW_COMPAT_2_2 \ 4410 {\ 4411 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 4412 .property = "mem_win_size",\ 4413 .value = "0x20000000",\ 4414 }, 4415 4416 static void spapr_machine_2_2_instance_options(MachineState *machine) 4417 { 4418 spapr_machine_2_3_instance_options(machine); 4419 machine->suppress_vmdesc = true; 4420 } 4421 4422 static void spapr_machine_2_2_class_options(MachineClass *mc) 4423 { 4424 spapr_machine_2_3_class_options(mc); 4425 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 4426 } 4427 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4428 4429 /* 4430 * pseries-2.1 4431 */ 4432 #define SPAPR_COMPAT_2_1 \ 4433 HW_COMPAT_2_1 4434 4435 static void spapr_machine_2_1_instance_options(MachineState *machine) 4436 { 4437 spapr_machine_2_2_instance_options(machine); 4438 } 4439 4440 static void spapr_machine_2_1_class_options(MachineClass *mc) 4441 { 4442 spapr_machine_2_2_class_options(mc); 4443 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 4444 } 4445 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4446 4447 static void spapr_machine_register_types(void) 4448 { 4449 type_register_static(&spapr_machine_info); 4450 } 4451 4452 type_init(spapr_machine_register_types) 4453