1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "sysemu/sysemu.h" 28 #include "sysemu/numa.h" 29 #include "hw/hw.h" 30 #include "hw/fw-path-provider.h" 31 #include "elf.h" 32 #include "net/net.h" 33 #include "sysemu/device_tree.h" 34 #include "sysemu/block-backend.h" 35 #include "sysemu/cpus.h" 36 #include "sysemu/kvm.h" 37 #include "sysemu/device_tree.h" 38 #include "kvm_ppc.h" 39 #include "migration/migration.h" 40 #include "mmu-hash64.h" 41 #include "qom/cpu.h" 42 43 #include "hw/boards.h" 44 #include "hw/ppc/ppc.h" 45 #include "hw/loader.h" 46 47 #include "hw/ppc/spapr.h" 48 #include "hw/ppc/spapr_vio.h" 49 #include "hw/pci-host/spapr.h" 50 #include "hw/ppc/xics.h" 51 #include "hw/pci/msi.h" 52 53 #include "hw/pci/pci.h" 54 #include "hw/scsi/scsi.h" 55 #include "hw/virtio/virtio-scsi.h" 56 57 #include "exec/address-spaces.h" 58 #include "hw/usb.h" 59 #include "qemu/config-file.h" 60 #include "qemu/error-report.h" 61 #include "trace.h" 62 #include "hw/nmi.h" 63 64 #include "hw/compat.h" 65 #include "qemu-common.h" 66 67 #include <libfdt.h> 68 69 /* SLOF memory layout: 70 * 71 * SLOF raw image loaded at 0, copies its romfs right below the flat 72 * device-tree, then position SLOF itself 31M below that 73 * 74 * So we set FW_OVERHEAD to 40MB which should account for all of that 75 * and more 76 * 77 * We load our kernel at 4M, leaving space for SLOF initial image 78 */ 79 #define FDT_MAX_SIZE 0x100000 80 #define RTAS_MAX_SIZE 0x10000 81 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 82 #define FW_MAX_SIZE 0x400000 83 #define FW_FILE_NAME "slof.bin" 84 #define FW_OVERHEAD 0x2800000 85 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 86 87 #define MIN_RMA_SLOF 128UL 88 89 #define TIMEBASE_FREQ 512000000ULL 90 91 #define PHANDLE_XICP 0x00001111 92 93 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 94 95 static XICSState *try_create_xics(const char *type, int nr_servers, 96 int nr_irqs, Error **errp) 97 { 98 Error *err = NULL; 99 DeviceState *dev; 100 101 dev = qdev_create(NULL, type); 102 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 103 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 104 object_property_set_bool(OBJECT(dev), true, "realized", &err); 105 if (err) { 106 error_propagate(errp, err); 107 object_unparent(OBJECT(dev)); 108 return NULL; 109 } 110 return XICS_COMMON(dev); 111 } 112 113 static XICSState *xics_system_init(MachineState *machine, 114 int nr_servers, int nr_irqs) 115 { 116 XICSState *icp = NULL; 117 118 if (kvm_enabled()) { 119 Error *err = NULL; 120 121 if (machine_kernel_irqchip_allowed(machine)) { 122 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err); 123 } 124 if (machine_kernel_irqchip_required(machine) && !icp) { 125 error_report("kernel_irqchip requested but unavailable: %s", 126 error_get_pretty(err)); 127 } 128 error_free(err); 129 } 130 131 if (!icp) { 132 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, &error_abort); 133 } 134 135 return icp; 136 } 137 138 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 139 int smt_threads) 140 { 141 int i, ret = 0; 142 uint32_t servers_prop[smt_threads]; 143 uint32_t gservers_prop[smt_threads * 2]; 144 int index = ppc_get_vcpu_dt_id(cpu); 145 146 if (cpu->cpu_version) { 147 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); 148 if (ret < 0) { 149 return ret; 150 } 151 } 152 153 /* Build interrupt servers and gservers properties */ 154 for (i = 0; i < smt_threads; i++) { 155 servers_prop[i] = cpu_to_be32(index + i); 156 /* Hack, direct the group queues back to cpu 0 */ 157 gservers_prop[i*2] = cpu_to_be32(index + i); 158 gservers_prop[i*2 + 1] = 0; 159 } 160 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 161 servers_prop, sizeof(servers_prop)); 162 if (ret < 0) { 163 return ret; 164 } 165 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 166 gservers_prop, sizeof(gservers_prop)); 167 168 return ret; 169 } 170 171 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) 172 { 173 int ret = 0; 174 PowerPCCPU *cpu = POWERPC_CPU(cs); 175 int index = ppc_get_vcpu_dt_id(cpu); 176 uint32_t associativity[] = {cpu_to_be32(0x5), 177 cpu_to_be32(0x0), 178 cpu_to_be32(0x0), 179 cpu_to_be32(0x0), 180 cpu_to_be32(cs->numa_node), 181 cpu_to_be32(index)}; 182 183 /* Advertise NUMA via ibm,associativity */ 184 if (nb_numa_nodes > 1) { 185 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 186 sizeof(associativity)); 187 } 188 189 return ret; 190 } 191 192 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 193 { 194 int ret = 0, offset, cpus_offset; 195 CPUState *cs; 196 char cpu_model[32]; 197 int smt = kvmppc_smt_threads(); 198 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 199 200 CPU_FOREACH(cs) { 201 PowerPCCPU *cpu = POWERPC_CPU(cs); 202 DeviceClass *dc = DEVICE_GET_CLASS(cs); 203 int index = ppc_get_vcpu_dt_id(cpu); 204 205 if ((index % smt) != 0) { 206 continue; 207 } 208 209 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 210 211 cpus_offset = fdt_path_offset(fdt, "/cpus"); 212 if (cpus_offset < 0) { 213 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 214 "cpus"); 215 if (cpus_offset < 0) { 216 return cpus_offset; 217 } 218 } 219 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 220 if (offset < 0) { 221 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 222 if (offset < 0) { 223 return offset; 224 } 225 } 226 227 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 228 pft_size_prop, sizeof(pft_size_prop)); 229 if (ret < 0) { 230 return ret; 231 } 232 233 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); 234 if (ret < 0) { 235 return ret; 236 } 237 238 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 239 ppc_get_compat_smt_threads(cpu)); 240 if (ret < 0) { 241 return ret; 242 } 243 } 244 return ret; 245 } 246 247 248 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 249 size_t maxsize) 250 { 251 size_t maxcells = maxsize / sizeof(uint32_t); 252 int i, j, count; 253 uint32_t *p = prop; 254 255 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 256 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 257 258 if (!sps->page_shift) { 259 break; 260 } 261 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 262 if (sps->enc[count].page_shift == 0) { 263 break; 264 } 265 } 266 if ((p - prop) >= (maxcells - 3 - count * 2)) { 267 break; 268 } 269 *(p++) = cpu_to_be32(sps->page_shift); 270 *(p++) = cpu_to_be32(sps->slb_enc); 271 *(p++) = cpu_to_be32(count); 272 for (j = 0; j < count; j++) { 273 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 274 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 275 } 276 } 277 278 return (p - prop) * sizeof(uint32_t); 279 } 280 281 static hwaddr spapr_node0_size(void) 282 { 283 MachineState *machine = MACHINE(qdev_get_machine()); 284 285 if (nb_numa_nodes) { 286 int i; 287 for (i = 0; i < nb_numa_nodes; ++i) { 288 if (numa_info[i].node_mem) { 289 return MIN(pow2floor(numa_info[i].node_mem), 290 machine->ram_size); 291 } 292 } 293 } 294 return machine->ram_size; 295 } 296 297 #define _FDT(exp) \ 298 do { \ 299 int ret = (exp); \ 300 if (ret < 0) { \ 301 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 302 #exp, fdt_strerror(ret)); \ 303 exit(1); \ 304 } \ 305 } while (0) 306 307 static void add_str(GString *s, const gchar *s1) 308 { 309 g_string_append_len(s, s1, strlen(s1) + 1); 310 } 311 312 static void *spapr_create_fdt_skel(hwaddr initrd_base, 313 hwaddr initrd_size, 314 hwaddr kernel_size, 315 bool little_endian, 316 const char *kernel_cmdline, 317 uint32_t epow_irq) 318 { 319 void *fdt; 320 uint32_t start_prop = cpu_to_be32(initrd_base); 321 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 322 GString *hypertas = g_string_sized_new(256); 323 GString *qemu_hypertas = g_string_sized_new(256); 324 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 325 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)}; 326 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 327 char *buf; 328 329 add_str(hypertas, "hcall-pft"); 330 add_str(hypertas, "hcall-term"); 331 add_str(hypertas, "hcall-dabr"); 332 add_str(hypertas, "hcall-interrupt"); 333 add_str(hypertas, "hcall-tce"); 334 add_str(hypertas, "hcall-vio"); 335 add_str(hypertas, "hcall-splpar"); 336 add_str(hypertas, "hcall-bulk"); 337 add_str(hypertas, "hcall-set-mode"); 338 add_str(qemu_hypertas, "hcall-memop1"); 339 340 fdt = g_malloc0(FDT_MAX_SIZE); 341 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 342 343 if (kernel_size) { 344 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 345 } 346 if (initrd_size) { 347 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 348 } 349 _FDT((fdt_finish_reservemap(fdt))); 350 351 /* Root node */ 352 _FDT((fdt_begin_node(fdt, ""))); 353 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 354 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 355 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 356 357 /* 358 * Add info to guest to indentify which host is it being run on 359 * and what is the uuid of the guest 360 */ 361 if (kvmppc_get_host_model(&buf)) { 362 _FDT((fdt_property_string(fdt, "host-model", buf))); 363 g_free(buf); 364 } 365 if (kvmppc_get_host_serial(&buf)) { 366 _FDT((fdt_property_string(fdt, "host-serial", buf))); 367 g_free(buf); 368 } 369 370 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1], 371 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4], 372 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7], 373 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10], 374 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13], 375 qemu_uuid[14], qemu_uuid[15]); 376 377 _FDT((fdt_property_string(fdt, "vm,uuid", buf))); 378 g_free(buf); 379 380 if (qemu_get_vm_name()) { 381 _FDT((fdt_property_string(fdt, "ibm,partition-name", 382 qemu_get_vm_name()))); 383 } 384 385 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 386 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 387 388 /* /chosen */ 389 _FDT((fdt_begin_node(fdt, "chosen"))); 390 391 /* Set Form1_affinity */ 392 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 393 394 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 395 _FDT((fdt_property(fdt, "linux,initrd-start", 396 &start_prop, sizeof(start_prop)))); 397 _FDT((fdt_property(fdt, "linux,initrd-end", 398 &end_prop, sizeof(end_prop)))); 399 if (kernel_size) { 400 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 401 cpu_to_be64(kernel_size) }; 402 403 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 404 if (little_endian) { 405 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 406 } 407 } 408 if (boot_menu) { 409 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); 410 } 411 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 412 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 413 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 414 415 _FDT((fdt_end_node(fdt))); 416 417 /* RTAS */ 418 _FDT((fdt_begin_node(fdt, "rtas"))); 419 420 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 421 add_str(hypertas, "hcall-multi-tce"); 422 } 423 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, 424 hypertas->len))); 425 g_string_free(hypertas, TRUE); 426 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, 427 qemu_hypertas->len))); 428 g_string_free(qemu_hypertas, TRUE); 429 430 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 431 refpoints, sizeof(refpoints)))); 432 433 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 434 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate", 435 RTAS_EVENT_SCAN_RATE))); 436 437 if (msi_supported) { 438 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0))); 439 } 440 441 /* 442 * According to PAPR, rtas ibm,os-term does not guarantee a return 443 * back to the guest cpu. 444 * 445 * While an additional ibm,extended-os-term property indicates that 446 * rtas call return will always occur. Set this property. 447 */ 448 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0))); 449 450 _FDT((fdt_end_node(fdt))); 451 452 /* interrupt controller */ 453 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 454 455 _FDT((fdt_property_string(fdt, "device_type", 456 "PowerPC-External-Interrupt-Presentation"))); 457 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 458 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 459 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 460 interrupt_server_ranges_prop, 461 sizeof(interrupt_server_ranges_prop)))); 462 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 463 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 464 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 465 466 _FDT((fdt_end_node(fdt))); 467 468 /* vdevice */ 469 _FDT((fdt_begin_node(fdt, "vdevice"))); 470 471 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 472 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 473 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 474 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 475 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 476 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 477 478 _FDT((fdt_end_node(fdt))); 479 480 /* event-sources */ 481 spapr_events_fdt_skel(fdt, epow_irq); 482 483 /* /hypervisor node */ 484 if (kvm_enabled()) { 485 uint8_t hypercall[16]; 486 487 /* indicate KVM hypercall interface */ 488 _FDT((fdt_begin_node(fdt, "hypervisor"))); 489 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); 490 if (kvmppc_has_cap_fixup_hcalls()) { 491 /* 492 * Older KVM versions with older guest kernels were broken with the 493 * magic page, don't allow the guest to map it. 494 */ 495 kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 496 sizeof(hypercall)); 497 _FDT((fdt_property(fdt, "hcall-instructions", hypercall, 498 sizeof(hypercall)))); 499 } 500 _FDT((fdt_end_node(fdt))); 501 } 502 503 _FDT((fdt_end_node(fdt))); /* close root node */ 504 _FDT((fdt_finish(fdt))); 505 506 return fdt; 507 } 508 509 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 510 hwaddr size) 511 { 512 uint32_t associativity[] = { 513 cpu_to_be32(0x4), /* length */ 514 cpu_to_be32(0x0), cpu_to_be32(0x0), 515 cpu_to_be32(0x0), cpu_to_be32(nodeid) 516 }; 517 char mem_name[32]; 518 uint64_t mem_reg_property[2]; 519 int off; 520 521 mem_reg_property[0] = cpu_to_be64(start); 522 mem_reg_property[1] = cpu_to_be64(size); 523 524 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 525 off = fdt_add_subnode(fdt, 0, mem_name); 526 _FDT(off); 527 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 528 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 529 sizeof(mem_reg_property)))); 530 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 531 sizeof(associativity)))); 532 return off; 533 } 534 535 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 536 { 537 MachineState *machine = MACHINE(spapr); 538 hwaddr mem_start, node_size; 539 int i, nb_nodes = nb_numa_nodes; 540 NodeInfo *nodes = numa_info; 541 NodeInfo ramnode; 542 543 /* No NUMA nodes, assume there is just one node with whole RAM */ 544 if (!nb_numa_nodes) { 545 nb_nodes = 1; 546 ramnode.node_mem = machine->ram_size; 547 nodes = &ramnode; 548 } 549 550 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 551 if (!nodes[i].node_mem) { 552 continue; 553 } 554 if (mem_start >= machine->ram_size) { 555 node_size = 0; 556 } else { 557 node_size = nodes[i].node_mem; 558 if (node_size > machine->ram_size - mem_start) { 559 node_size = machine->ram_size - mem_start; 560 } 561 } 562 if (!mem_start) { 563 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 564 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 565 mem_start += spapr->rma_size; 566 node_size -= spapr->rma_size; 567 } 568 for ( ; node_size; ) { 569 hwaddr sizetmp = pow2floor(node_size); 570 571 /* mem_start != 0 here */ 572 if (ctzl(mem_start) < ctzl(sizetmp)) { 573 sizetmp = 1ULL << ctzl(mem_start); 574 } 575 576 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 577 node_size -= sizetmp; 578 mem_start += sizetmp; 579 } 580 } 581 582 return 0; 583 } 584 585 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 586 sPAPRMachineState *spapr) 587 { 588 PowerPCCPU *cpu = POWERPC_CPU(cs); 589 CPUPPCState *env = &cpu->env; 590 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 591 int index = ppc_get_vcpu_dt_id(cpu); 592 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 593 0xffffffff, 0xffffffff}; 594 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 595 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 596 uint32_t page_sizes_prop[64]; 597 size_t page_sizes_prop_size; 598 uint32_t vcpus_per_socket = smp_threads * smp_cores; 599 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 600 601 /* Note: we keep CI large pages off for now because a 64K capable guest 602 * provisioned with large pages might otherwise try to map a qemu 603 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 604 * even if that qemu runs on a 4k host. 605 * 606 * We can later add this bit back when we are confident this is not 607 * an issue (!HV KVM or 64K host) 608 */ 609 uint8_t pa_features_206[] = { 6, 0, 610 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 611 uint8_t pa_features_207[] = { 24, 0, 612 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 613 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 614 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 615 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 616 uint8_t *pa_features; 617 size_t pa_size; 618 619 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 620 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 621 622 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 623 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 624 env->dcache_line_size))); 625 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 626 env->dcache_line_size))); 627 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 628 env->icache_line_size))); 629 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 630 env->icache_line_size))); 631 632 if (pcc->l1_dcache_size) { 633 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 634 pcc->l1_dcache_size))); 635 } else { 636 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 637 } 638 if (pcc->l1_icache_size) { 639 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 640 pcc->l1_icache_size))); 641 } else { 642 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 643 } 644 645 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 646 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 647 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 648 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 649 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 650 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 651 652 if (env->spr_cb[SPR_PURR].oea_read) { 653 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 654 } 655 656 if (env->mmu_model & POWERPC_MMU_1TSEG) { 657 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 658 segs, sizeof(segs)))); 659 } 660 661 /* Advertise VMX/VSX (vector extensions) if available 662 * 0 / no property == no vector extensions 663 * 1 == VMX / Altivec available 664 * 2 == VSX available */ 665 if (env->insns_flags & PPC_ALTIVEC) { 666 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 667 668 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 669 } 670 671 /* Advertise DFP (Decimal Floating Point) if available 672 * 0 / no property == no DFP 673 * 1 == DFP available */ 674 if (env->insns_flags2 & PPC2_DFP) { 675 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 676 } 677 678 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 679 sizeof(page_sizes_prop)); 680 if (page_sizes_prop_size) { 681 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 682 page_sizes_prop, page_sizes_prop_size))); 683 } 684 685 /* Do the ibm,pa-features property, adjust it for ci-large-pages */ 686 if (env->mmu_model == POWERPC_MMU_2_06) { 687 pa_features = pa_features_206; 688 pa_size = sizeof(pa_features_206); 689 } else /* env->mmu_model == POWERPC_MMU_2_07 */ { 690 pa_features = pa_features_207; 691 pa_size = sizeof(pa_features_207); 692 } 693 if (env->ci_large_pages) { 694 pa_features[3] |= 0x20; 695 } 696 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 697 698 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 699 cs->cpu_index / vcpus_per_socket))); 700 701 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 702 pft_size_prop, sizeof(pft_size_prop)))); 703 704 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); 705 706 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 707 ppc_get_compat_smt_threads(cpu))); 708 } 709 710 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 711 { 712 CPUState *cs; 713 int cpus_offset; 714 char *nodename; 715 int smt = kvmppc_smt_threads(); 716 717 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 718 _FDT(cpus_offset); 719 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 720 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 721 722 /* 723 * We walk the CPUs in reverse order to ensure that CPU DT nodes 724 * created by fdt_add_subnode() end up in the right order in FDT 725 * for the guest kernel the enumerate the CPUs correctly. 726 */ 727 CPU_FOREACH_REVERSE(cs) { 728 PowerPCCPU *cpu = POWERPC_CPU(cs); 729 int index = ppc_get_vcpu_dt_id(cpu); 730 DeviceClass *dc = DEVICE_GET_CLASS(cs); 731 int offset; 732 733 if ((index % smt) != 0) { 734 continue; 735 } 736 737 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 738 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 739 g_free(nodename); 740 _FDT(offset); 741 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 742 } 743 744 } 745 746 /* 747 * Adds ibm,dynamic-reconfiguration-memory node. 748 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 749 * of this device tree node. 750 */ 751 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 752 { 753 MachineState *machine = MACHINE(spapr); 754 int ret, i, offset; 755 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 756 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 757 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 758 uint32_t *int_buf, *cur_index, buf_len; 759 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 760 761 /* 762 * Allocate enough buffer size to fit in ibm,dynamic-memory 763 * or ibm,associativity-lookup-arrays 764 */ 765 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 766 * sizeof(uint32_t); 767 cur_index = int_buf = g_malloc0(buf_len); 768 769 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 770 771 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 772 sizeof(prop_lmb_size)); 773 if (ret < 0) { 774 goto out; 775 } 776 777 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 778 if (ret < 0) { 779 goto out; 780 } 781 782 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 783 if (ret < 0) { 784 goto out; 785 } 786 787 /* ibm,dynamic-memory */ 788 int_buf[0] = cpu_to_be32(nr_lmbs); 789 cur_index++; 790 for (i = 0; i < nr_lmbs; i++) { 791 sPAPRDRConnector *drc; 792 sPAPRDRConnectorClass *drck; 793 uint64_t addr = i * lmb_size + spapr->hotplug_memory.base;; 794 uint32_t *dynamic_memory = cur_index; 795 796 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 797 addr/lmb_size); 798 g_assert(drc); 799 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 800 801 dynamic_memory[0] = cpu_to_be32(addr >> 32); 802 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 803 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); 804 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 805 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 806 if (addr < machine->ram_size || 807 memory_region_present(get_system_memory(), addr)) { 808 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 809 } else { 810 dynamic_memory[5] = cpu_to_be32(0); 811 } 812 813 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 814 } 815 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 816 if (ret < 0) { 817 goto out; 818 } 819 820 /* ibm,associativity-lookup-arrays */ 821 cur_index = int_buf; 822 int_buf[0] = cpu_to_be32(nr_nodes); 823 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 824 cur_index += 2; 825 for (i = 0; i < nr_nodes; i++) { 826 uint32_t associativity[] = { 827 cpu_to_be32(0x0), 828 cpu_to_be32(0x0), 829 cpu_to_be32(0x0), 830 cpu_to_be32(i) 831 }; 832 memcpy(cur_index, associativity, sizeof(associativity)); 833 cur_index += 4; 834 } 835 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 836 (cur_index - int_buf) * sizeof(uint32_t)); 837 out: 838 g_free(int_buf); 839 return ret; 840 } 841 842 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 843 target_ulong addr, target_ulong size, 844 bool cpu_update, bool memory_update) 845 { 846 void *fdt, *fdt_skel; 847 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 848 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 849 850 size -= sizeof(hdr); 851 852 /* Create sceleton */ 853 fdt_skel = g_malloc0(size); 854 _FDT((fdt_create(fdt_skel, size))); 855 _FDT((fdt_begin_node(fdt_skel, ""))); 856 _FDT((fdt_end_node(fdt_skel))); 857 _FDT((fdt_finish(fdt_skel))); 858 fdt = g_malloc0(size); 859 _FDT((fdt_open_into(fdt_skel, fdt, size))); 860 g_free(fdt_skel); 861 862 /* Fixup cpu nodes */ 863 if (cpu_update) { 864 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 865 } 866 867 /* Generate memory nodes or ibm,dynamic-reconfiguration-memory node */ 868 if (memory_update && smc->dr_lmb_enabled) { 869 _FDT((spapr_populate_drconf_memory(spapr, fdt))); 870 } 871 872 /* Pack resulting tree */ 873 _FDT((fdt_pack(fdt))); 874 875 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 876 trace_spapr_cas_failed(size); 877 return -1; 878 } 879 880 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 881 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 882 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 883 g_free(fdt); 884 885 return 0; 886 } 887 888 static void spapr_finalize_fdt(sPAPRMachineState *spapr, 889 hwaddr fdt_addr, 890 hwaddr rtas_addr, 891 hwaddr rtas_size) 892 { 893 MachineState *machine = MACHINE(qdev_get_machine()); 894 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 895 const char *boot_device = machine->boot_order; 896 int ret, i; 897 size_t cb = 0; 898 char *bootlist; 899 void *fdt; 900 sPAPRPHBState *phb; 901 902 fdt = g_malloc(FDT_MAX_SIZE); 903 904 /* open out the base tree into a temp buffer for the final tweaks */ 905 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 906 907 ret = spapr_populate_memory(spapr, fdt); 908 if (ret < 0) { 909 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 910 exit(1); 911 } 912 913 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 914 if (ret < 0) { 915 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 916 exit(1); 917 } 918 919 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 920 ret = spapr_rng_populate_dt(fdt); 921 if (ret < 0) { 922 fprintf(stderr, "could not set up rng device in the fdt\n"); 923 exit(1); 924 } 925 } 926 927 QLIST_FOREACH(phb, &spapr->phbs, list) { 928 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 929 } 930 931 if (ret < 0) { 932 fprintf(stderr, "couldn't setup PCI devices in fdt\n"); 933 exit(1); 934 } 935 936 /* RTAS */ 937 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 938 if (ret < 0) { 939 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 940 } 941 942 /* cpus */ 943 spapr_populate_cpus_dt_node(fdt, spapr); 944 945 bootlist = get_boot_devices_list(&cb, true); 946 if (cb && bootlist) { 947 int offset = fdt_path_offset(fdt, "/chosen"); 948 if (offset < 0) { 949 exit(1); 950 } 951 for (i = 0; i < cb; i++) { 952 if (bootlist[i] == '\n') { 953 bootlist[i] = ' '; 954 } 955 956 } 957 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); 958 } 959 960 if (boot_device && strlen(boot_device)) { 961 int offset = fdt_path_offset(fdt, "/chosen"); 962 963 if (offset < 0) { 964 exit(1); 965 } 966 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device); 967 } 968 969 if (!spapr->has_graphics) { 970 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 971 } 972 973 if (smc->dr_lmb_enabled) { 974 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 975 } 976 977 _FDT((fdt_pack(fdt))); 978 979 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 980 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 981 fdt_totalsize(fdt), FDT_MAX_SIZE); 982 exit(1); 983 } 984 985 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 986 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 987 988 g_free(bootlist); 989 g_free(fdt); 990 } 991 992 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 993 { 994 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 995 } 996 997 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 998 { 999 CPUPPCState *env = &cpu->env; 1000 1001 if (msr_pr) { 1002 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1003 env->gpr[3] = H_PRIVILEGE; 1004 } else { 1005 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1006 } 1007 } 1008 1009 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1010 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1011 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1012 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1013 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1014 1015 static void spapr_alloc_htab(sPAPRMachineState *spapr) 1016 { 1017 long shift; 1018 int index; 1019 1020 /* allocate hash page table. For now we always make this 16mb, 1021 * later we should probably make it scale to the size of guest 1022 * RAM */ 1023 1024 shift = kvmppc_reset_htab(spapr->htab_shift); 1025 if (shift < 0) { 1026 /* 1027 * For HV KVM, host kernel will return -ENOMEM when requested 1028 * HTAB size can't be allocated. 1029 */ 1030 error_setg(&error_abort, "Failed to allocate HTAB of requested size, try with smaller maxmem"); 1031 } else if (shift > 0) { 1032 /* 1033 * Kernel handles htab, we don't need to allocate one 1034 * 1035 * Older kernels can fall back to lower HTAB shift values, 1036 * but we don't allow booting of such guests. 1037 */ 1038 if (shift != spapr->htab_shift) { 1039 error_setg(&error_abort, "Failed to allocate HTAB of requested size, try with smaller maxmem"); 1040 } 1041 1042 spapr->htab_shift = shift; 1043 kvmppc_kern_htab = true; 1044 } else { 1045 /* Allocate htab */ 1046 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); 1047 1048 /* And clear it */ 1049 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 1050 1051 for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) { 1052 DIRTY_HPTE(HPTE(spapr->htab, index)); 1053 } 1054 } 1055 } 1056 1057 /* 1058 * Clear HTAB entries during reset. 1059 * 1060 * If host kernel has allocated HTAB, KVM_PPC_ALLOCATE_HTAB ioctl is 1061 * used to clear HTAB. Otherwise QEMU-allocated HTAB is cleared manually. 1062 */ 1063 static void spapr_reset_htab(sPAPRMachineState *spapr) 1064 { 1065 long shift; 1066 int index; 1067 1068 shift = kvmppc_reset_htab(spapr->htab_shift); 1069 if (shift < 0) { 1070 error_setg(&error_abort, "Failed to reset HTAB"); 1071 } else if (shift > 0) { 1072 if (shift != spapr->htab_shift) { 1073 error_setg(&error_abort, "Requested HTAB allocation failed during reset"); 1074 } 1075 1076 /* Tell readers to update their file descriptor */ 1077 if (spapr->htab_fd >= 0) { 1078 spapr->htab_fd_stale = true; 1079 } 1080 } else { 1081 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 1082 1083 for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) { 1084 DIRTY_HPTE(HPTE(spapr->htab, index)); 1085 } 1086 } 1087 1088 /* Update the RMA size if necessary */ 1089 if (spapr->vrma_adjust) { 1090 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1091 spapr->htab_shift); 1092 } 1093 } 1094 1095 static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1096 { 1097 bool matched = false; 1098 1099 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1100 matched = true; 1101 } 1102 1103 if (!matched) { 1104 error_report("Device %s is not supported by this machine yet.", 1105 qdev_fw_name(DEVICE(sbdev))); 1106 exit(1); 1107 } 1108 1109 return 0; 1110 } 1111 1112 /* 1113 * A guest reset will cause spapr->htab_fd to become stale if being used. 1114 * Reopen the file descriptor to make sure the whole HTAB is properly read. 1115 */ 1116 static int spapr_check_htab_fd(sPAPRMachineState *spapr) 1117 { 1118 int rc = 0; 1119 1120 if (spapr->htab_fd_stale) { 1121 close(spapr->htab_fd); 1122 spapr->htab_fd = kvmppc_get_htab_fd(false); 1123 if (spapr->htab_fd < 0) { 1124 error_report("Unable to open fd for reading hash table from KVM: " 1125 "%s", strerror(errno)); 1126 rc = -1; 1127 } 1128 spapr->htab_fd_stale = false; 1129 } 1130 1131 return rc; 1132 } 1133 1134 static void ppc_spapr_reset(void) 1135 { 1136 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1137 PowerPCCPU *first_ppc_cpu; 1138 uint32_t rtas_limit; 1139 1140 /* Check for unknown sysbus devices */ 1141 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1142 1143 /* Reset the hash table & recalc the RMA */ 1144 spapr_reset_htab(spapr); 1145 1146 qemu_devices_reset(); 1147 1148 /* 1149 * We place the device tree and RTAS just below either the top of the RMA, 1150 * or just below 2GB, whichever is lowere, so that it can be 1151 * processed with 32-bit real mode code if necessary 1152 */ 1153 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1154 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1155 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 1156 1157 /* Load the fdt */ 1158 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 1159 spapr->rtas_size); 1160 1161 /* Copy RTAS over */ 1162 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob, 1163 spapr->rtas_size); 1164 1165 /* Set up the entry state */ 1166 first_ppc_cpu = POWERPC_CPU(first_cpu); 1167 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 1168 first_ppc_cpu->env.gpr[5] = 0; 1169 first_cpu->halted = 0; 1170 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1171 1172 } 1173 1174 static void spapr_cpu_reset(void *opaque) 1175 { 1176 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1177 PowerPCCPU *cpu = opaque; 1178 CPUState *cs = CPU(cpu); 1179 CPUPPCState *env = &cpu->env; 1180 1181 cpu_reset(cs); 1182 1183 /* All CPUs start halted. CPU0 is unhalted from the machine level 1184 * reset code and the rest are explicitly started up by the guest 1185 * using an RTAS call */ 1186 cs->halted = 1; 1187 1188 env->spr[SPR_HIOR] = 0; 1189 1190 env->external_htab = (uint8_t *)spapr->htab; 1191 if (kvm_enabled() && !env->external_htab) { 1192 /* 1193 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte* 1194 * functions do the right thing. 1195 */ 1196 env->external_htab = (void *)1; 1197 } 1198 env->htab_base = -1; 1199 /* 1200 * htab_mask is the mask used to normalize hash value to PTEG index. 1201 * htab_shift is log2 of hash table size. 1202 * We have 8 hpte per group, and each hpte is 16 bytes. 1203 * ie have 128 bytes per hpte entry. 1204 */ 1205 env->htab_mask = (1ULL << (spapr->htab_shift - 7)) - 1; 1206 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | 1207 (spapr->htab_shift - 18); 1208 } 1209 1210 static void spapr_create_nvram(sPAPRMachineState *spapr) 1211 { 1212 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1213 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1214 1215 if (dinfo) { 1216 qdev_prop_set_drive_nofail(dev, "drive", blk_by_legacy_dinfo(dinfo)); 1217 } 1218 1219 qdev_init_nofail(dev); 1220 1221 spapr->nvram = (struct sPAPRNVRAM *)dev; 1222 } 1223 1224 static void spapr_rtc_create(sPAPRMachineState *spapr) 1225 { 1226 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); 1227 1228 qdev_init_nofail(dev); 1229 spapr->rtc = dev; 1230 1231 object_property_add_alias(qdev_get_machine(), "rtc-time", 1232 OBJECT(spapr->rtc), "date", NULL); 1233 } 1234 1235 /* Returns whether we want to use VGA or not */ 1236 static int spapr_vga_init(PCIBus *pci_bus) 1237 { 1238 switch (vga_interface_type) { 1239 case VGA_NONE: 1240 return false; 1241 case VGA_DEVICE: 1242 return true; 1243 case VGA_STD: 1244 case VGA_VIRTIO: 1245 return pci_vga_init(pci_bus) != NULL; 1246 default: 1247 fprintf(stderr, "This vga model is not supported," 1248 "currently it only supports -vga std\n"); 1249 exit(0); 1250 } 1251 } 1252 1253 static int spapr_post_load(void *opaque, int version_id) 1254 { 1255 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1256 int err = 0; 1257 1258 /* In earlier versions, there was no separate qdev for the PAPR 1259 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1260 * So when migrating from those versions, poke the incoming offset 1261 * value into the RTC device */ 1262 if (version_id < 3) { 1263 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); 1264 } 1265 1266 return err; 1267 } 1268 1269 static bool version_before_3(void *opaque, int version_id) 1270 { 1271 return version_id < 3; 1272 } 1273 1274 static const VMStateDescription vmstate_spapr = { 1275 .name = "spapr", 1276 .version_id = 3, 1277 .minimum_version_id = 1, 1278 .post_load = spapr_post_load, 1279 .fields = (VMStateField[]) { 1280 /* used to be @next_irq */ 1281 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1282 1283 /* RTC offset */ 1284 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1285 1286 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1287 VMSTATE_END_OF_LIST() 1288 }, 1289 }; 1290 1291 static int htab_save_setup(QEMUFile *f, void *opaque) 1292 { 1293 sPAPRMachineState *spapr = opaque; 1294 1295 /* "Iteration" header */ 1296 qemu_put_be32(f, spapr->htab_shift); 1297 1298 if (spapr->htab) { 1299 spapr->htab_save_index = 0; 1300 spapr->htab_first_pass = true; 1301 } else { 1302 assert(kvm_enabled()); 1303 1304 spapr->htab_fd = kvmppc_get_htab_fd(false); 1305 spapr->htab_fd_stale = false; 1306 if (spapr->htab_fd < 0) { 1307 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", 1308 strerror(errno)); 1309 return -1; 1310 } 1311 } 1312 1313 1314 return 0; 1315 } 1316 1317 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1318 int64_t max_ns) 1319 { 1320 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1321 int index = spapr->htab_save_index; 1322 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1323 1324 assert(spapr->htab_first_pass); 1325 1326 do { 1327 int chunkstart; 1328 1329 /* Consume invalid HPTEs */ 1330 while ((index < htabslots) 1331 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1332 index++; 1333 CLEAN_HPTE(HPTE(spapr->htab, index)); 1334 } 1335 1336 /* Consume valid HPTEs */ 1337 chunkstart = index; 1338 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1339 && HPTE_VALID(HPTE(spapr->htab, index))) { 1340 index++; 1341 CLEAN_HPTE(HPTE(spapr->htab, index)); 1342 } 1343 1344 if (index > chunkstart) { 1345 int n_valid = index - chunkstart; 1346 1347 qemu_put_be32(f, chunkstart); 1348 qemu_put_be16(f, n_valid); 1349 qemu_put_be16(f, 0); 1350 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1351 HASH_PTE_SIZE_64 * n_valid); 1352 1353 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1354 break; 1355 } 1356 } 1357 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1358 1359 if (index >= htabslots) { 1360 assert(index == htabslots); 1361 index = 0; 1362 spapr->htab_first_pass = false; 1363 } 1364 spapr->htab_save_index = index; 1365 } 1366 1367 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1368 int64_t max_ns) 1369 { 1370 bool final = max_ns < 0; 1371 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1372 int examined = 0, sent = 0; 1373 int index = spapr->htab_save_index; 1374 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1375 1376 assert(!spapr->htab_first_pass); 1377 1378 do { 1379 int chunkstart, invalidstart; 1380 1381 /* Consume non-dirty HPTEs */ 1382 while ((index < htabslots) 1383 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1384 index++; 1385 examined++; 1386 } 1387 1388 chunkstart = index; 1389 /* Consume valid dirty HPTEs */ 1390 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1391 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1392 && HPTE_VALID(HPTE(spapr->htab, index))) { 1393 CLEAN_HPTE(HPTE(spapr->htab, index)); 1394 index++; 1395 examined++; 1396 } 1397 1398 invalidstart = index; 1399 /* Consume invalid dirty HPTEs */ 1400 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1401 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1402 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1403 CLEAN_HPTE(HPTE(spapr->htab, index)); 1404 index++; 1405 examined++; 1406 } 1407 1408 if (index > chunkstart) { 1409 int n_valid = invalidstart - chunkstart; 1410 int n_invalid = index - invalidstart; 1411 1412 qemu_put_be32(f, chunkstart); 1413 qemu_put_be16(f, n_valid); 1414 qemu_put_be16(f, n_invalid); 1415 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1416 HASH_PTE_SIZE_64 * n_valid); 1417 sent += index - chunkstart; 1418 1419 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1420 break; 1421 } 1422 } 1423 1424 if (examined >= htabslots) { 1425 break; 1426 } 1427 1428 if (index >= htabslots) { 1429 assert(index == htabslots); 1430 index = 0; 1431 } 1432 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1433 1434 if (index >= htabslots) { 1435 assert(index == htabslots); 1436 index = 0; 1437 } 1438 1439 spapr->htab_save_index = index; 1440 1441 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1442 } 1443 1444 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1445 #define MAX_KVM_BUF_SIZE 2048 1446 1447 static int htab_save_iterate(QEMUFile *f, void *opaque) 1448 { 1449 sPAPRMachineState *spapr = opaque; 1450 int rc = 0; 1451 1452 /* Iteration header */ 1453 qemu_put_be32(f, 0); 1454 1455 if (!spapr->htab) { 1456 assert(kvm_enabled()); 1457 1458 rc = spapr_check_htab_fd(spapr); 1459 if (rc < 0) { 1460 return rc; 1461 } 1462 1463 rc = kvmppc_save_htab(f, spapr->htab_fd, 1464 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1465 if (rc < 0) { 1466 return rc; 1467 } 1468 } else if (spapr->htab_first_pass) { 1469 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1470 } else { 1471 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1472 } 1473 1474 /* End marker */ 1475 qemu_put_be32(f, 0); 1476 qemu_put_be16(f, 0); 1477 qemu_put_be16(f, 0); 1478 1479 return rc; 1480 } 1481 1482 static int htab_save_complete(QEMUFile *f, void *opaque) 1483 { 1484 sPAPRMachineState *spapr = opaque; 1485 1486 /* Iteration header */ 1487 qemu_put_be32(f, 0); 1488 1489 if (!spapr->htab) { 1490 int rc; 1491 1492 assert(kvm_enabled()); 1493 1494 rc = spapr_check_htab_fd(spapr); 1495 if (rc < 0) { 1496 return rc; 1497 } 1498 1499 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); 1500 if (rc < 0) { 1501 return rc; 1502 } 1503 close(spapr->htab_fd); 1504 spapr->htab_fd = -1; 1505 } else { 1506 htab_save_later_pass(f, spapr, -1); 1507 } 1508 1509 /* End marker */ 1510 qemu_put_be32(f, 0); 1511 qemu_put_be16(f, 0); 1512 qemu_put_be16(f, 0); 1513 1514 return 0; 1515 } 1516 1517 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1518 { 1519 sPAPRMachineState *spapr = opaque; 1520 uint32_t section_hdr; 1521 int fd = -1; 1522 1523 if (version_id < 1 || version_id > 1) { 1524 fprintf(stderr, "htab_load() bad version\n"); 1525 return -EINVAL; 1526 } 1527 1528 section_hdr = qemu_get_be32(f); 1529 1530 if (section_hdr) { 1531 /* First section, just the hash shift */ 1532 if (spapr->htab_shift != section_hdr) { 1533 error_report("htab_shift mismatch: source %d target %d", 1534 section_hdr, spapr->htab_shift); 1535 return -EINVAL; 1536 } 1537 return 0; 1538 } 1539 1540 if (!spapr->htab) { 1541 assert(kvm_enabled()); 1542 1543 fd = kvmppc_get_htab_fd(true); 1544 if (fd < 0) { 1545 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", 1546 strerror(errno)); 1547 } 1548 } 1549 1550 while (true) { 1551 uint32_t index; 1552 uint16_t n_valid, n_invalid; 1553 1554 index = qemu_get_be32(f); 1555 n_valid = qemu_get_be16(f); 1556 n_invalid = qemu_get_be16(f); 1557 1558 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1559 /* End of Stream */ 1560 break; 1561 } 1562 1563 if ((index + n_valid + n_invalid) > 1564 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1565 /* Bad index in stream */ 1566 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " 1567 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, 1568 spapr->htab_shift); 1569 return -EINVAL; 1570 } 1571 1572 if (spapr->htab) { 1573 if (n_valid) { 1574 qemu_get_buffer(f, HPTE(spapr->htab, index), 1575 HASH_PTE_SIZE_64 * n_valid); 1576 } 1577 if (n_invalid) { 1578 memset(HPTE(spapr->htab, index + n_valid), 0, 1579 HASH_PTE_SIZE_64 * n_invalid); 1580 } 1581 } else { 1582 int rc; 1583 1584 assert(fd >= 0); 1585 1586 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1587 if (rc < 0) { 1588 return rc; 1589 } 1590 } 1591 } 1592 1593 if (!spapr->htab) { 1594 assert(fd >= 0); 1595 close(fd); 1596 } 1597 1598 return 0; 1599 } 1600 1601 static SaveVMHandlers savevm_htab_handlers = { 1602 .save_live_setup = htab_save_setup, 1603 .save_live_iterate = htab_save_iterate, 1604 .save_live_complete_precopy = htab_save_complete, 1605 .load_state = htab_load, 1606 }; 1607 1608 static void spapr_boot_set(void *opaque, const char *boot_device, 1609 Error **errp) 1610 { 1611 MachineState *machine = MACHINE(qdev_get_machine()); 1612 machine->boot_order = g_strdup(boot_device); 1613 } 1614 1615 static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu) 1616 { 1617 CPUPPCState *env = &cpu->env; 1618 1619 /* Set time-base frequency to 512 MHz */ 1620 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 1621 1622 /* PAPR always has exception vectors in RAM not ROM. To ensure this, 1623 * MSR[IP] should never be set. 1624 */ 1625 env->msr_mask &= ~(1 << 6); 1626 1627 /* Tell KVM that we're in PAPR mode */ 1628 if (kvm_enabled()) { 1629 kvmppc_set_papr(cpu); 1630 } 1631 1632 if (cpu->max_compat) { 1633 if (ppc_set_compat(cpu, cpu->max_compat) < 0) { 1634 exit(1); 1635 } 1636 } 1637 1638 xics_cpu_setup(spapr->icp, cpu); 1639 1640 qemu_register_reset(spapr_cpu_reset, cpu); 1641 } 1642 1643 /* 1644 * Reset routine for LMB DR devices. 1645 * 1646 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1647 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1648 * when it walks all its children devices. LMB devices reset occurs 1649 * as part of spapr_ppc_reset(). 1650 */ 1651 static void spapr_drc_reset(void *opaque) 1652 { 1653 sPAPRDRConnector *drc = opaque; 1654 DeviceState *d = DEVICE(drc); 1655 1656 if (d) { 1657 device_reset(d); 1658 } 1659 } 1660 1661 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1662 { 1663 MachineState *machine = MACHINE(spapr); 1664 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1665 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1666 int i; 1667 1668 for (i = 0; i < nr_lmbs; i++) { 1669 sPAPRDRConnector *drc; 1670 uint64_t addr; 1671 1672 addr = i * lmb_size + spapr->hotplug_memory.base; 1673 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, 1674 addr/lmb_size); 1675 qemu_register_reset(spapr_drc_reset, drc); 1676 } 1677 } 1678 1679 /* 1680 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1681 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1682 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1683 */ 1684 static void spapr_validate_node_memory(MachineState *machine) 1685 { 1686 int i; 1687 1688 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE || 1689 machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1690 error_report("Can't support memory configuration where RAM size " 1691 "0x" RAM_ADDR_FMT " or maxmem size " 1692 "0x" RAM_ADDR_FMT " isn't aligned to %llu MB", 1693 machine->ram_size, machine->maxram_size, 1694 SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 1695 exit(EXIT_FAILURE); 1696 } 1697 1698 for (i = 0; i < nb_numa_nodes; i++) { 1699 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 1700 error_report("Can't support memory configuration where memory size" 1701 " %" PRIx64 " of node %d isn't aligned to %llu MB", 1702 numa_info[i].node_mem, i, 1703 SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 1704 exit(EXIT_FAILURE); 1705 } 1706 } 1707 } 1708 1709 /* pSeries LPAR / sPAPR hardware init */ 1710 static void ppc_spapr_init(MachineState *machine) 1711 { 1712 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1713 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1714 const char *kernel_filename = machine->kernel_filename; 1715 const char *kernel_cmdline = machine->kernel_cmdline; 1716 const char *initrd_filename = machine->initrd_filename; 1717 PowerPCCPU *cpu; 1718 PCIHostState *phb; 1719 int i; 1720 MemoryRegion *sysmem = get_system_memory(); 1721 MemoryRegion *ram = g_new(MemoryRegion, 1); 1722 MemoryRegion *rma_region; 1723 void *rma = NULL; 1724 hwaddr rma_alloc_size; 1725 hwaddr node0_size = spapr_node0_size(); 1726 uint32_t initrd_base = 0; 1727 long kernel_size = 0, initrd_size = 0; 1728 long load_limit, fw_size; 1729 bool kernel_le = false; 1730 char *filename; 1731 1732 msi_supported = true; 1733 1734 QLIST_INIT(&spapr->phbs); 1735 1736 cpu_ppc_hypercall = emulate_spapr_hypercall; 1737 1738 /* Allocate RMA if necessary */ 1739 rma_alloc_size = kvmppc_alloc_rma(&rma); 1740 1741 if (rma_alloc_size == -1) { 1742 error_report("Unable to create RMA"); 1743 exit(1); 1744 } 1745 1746 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1747 spapr->rma_size = rma_alloc_size; 1748 } else { 1749 spapr->rma_size = node0_size; 1750 1751 /* With KVM, we don't actually know whether KVM supports an 1752 * unbounded RMA (PR KVM) or is limited by the hash table size 1753 * (HV KVM using VRMA), so we always assume the latter 1754 * 1755 * In that case, we also limit the initial allocations for RTAS 1756 * etc... to 256M since we have no way to know what the VRMA size 1757 * is going to be as it depends on the size of the hash table 1758 * isn't determined yet. 1759 */ 1760 if (kvm_enabled()) { 1761 spapr->vrma_adjust = 1; 1762 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1763 } 1764 } 1765 1766 if (spapr->rma_size > node0_size) { 1767 fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n", 1768 spapr->rma_size); 1769 exit(1); 1770 } 1771 1772 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 1773 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 1774 1775 /* We aim for a hash table of size 1/128 the size of RAM. The 1776 * normal rule of thumb is 1/64 the size of RAM, but that's much 1777 * more than needed for the Linux guests we support. */ 1778 spapr->htab_shift = 18; /* Minimum architected size */ 1779 while (spapr->htab_shift <= 46) { 1780 if ((1ULL << (spapr->htab_shift + 7)) >= machine->maxram_size) { 1781 break; 1782 } 1783 spapr->htab_shift++; 1784 } 1785 spapr_alloc_htab(spapr); 1786 1787 /* Set up Interrupt Controller before we create the VCPUs */ 1788 spapr->icp = xics_system_init(machine, 1789 DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), 1790 smp_threads), 1791 XICS_IRQS); 1792 1793 if (smc->dr_lmb_enabled) { 1794 spapr_validate_node_memory(machine); 1795 } 1796 1797 /* init CPUs */ 1798 if (machine->cpu_model == NULL) { 1799 machine->cpu_model = kvm_enabled() ? "host" : "POWER7"; 1800 } 1801 for (i = 0; i < smp_cpus; i++) { 1802 cpu = cpu_ppc_init(machine->cpu_model); 1803 if (cpu == NULL) { 1804 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 1805 exit(1); 1806 } 1807 spapr_cpu_init(spapr, cpu); 1808 } 1809 1810 if (kvm_enabled()) { 1811 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 1812 kvmppc_enable_logical_ci_hcalls(); 1813 kvmppc_enable_set_mode_hcall(); 1814 } 1815 1816 /* allocate RAM */ 1817 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 1818 machine->ram_size); 1819 memory_region_add_subregion(sysmem, 0, ram); 1820 1821 if (rma_alloc_size && rma) { 1822 rma_region = g_new(MemoryRegion, 1); 1823 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 1824 rma_alloc_size, rma); 1825 vmstate_register_ram_global(rma_region); 1826 memory_region_add_subregion(sysmem, 0, rma_region); 1827 } 1828 1829 /* initialize hotplug memory address space */ 1830 if (machine->ram_size < machine->maxram_size) { 1831 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 1832 1833 if (machine->ram_slots > SPAPR_MAX_RAM_SLOTS) { 1834 error_report("Specified number of memory slots %"PRIu64" exceeds max supported %d\n", 1835 machine->ram_slots, SPAPR_MAX_RAM_SLOTS); 1836 exit(EXIT_FAILURE); 1837 } 1838 1839 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 1840 SPAPR_HOTPLUG_MEM_ALIGN); 1841 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 1842 "hotplug-memory", hotplug_mem_size); 1843 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 1844 &spapr->hotplug_memory.mr); 1845 } 1846 1847 if (smc->dr_lmb_enabled) { 1848 spapr_create_lmb_dr_connectors(spapr); 1849 } 1850 1851 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1852 if (!filename) { 1853 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 1854 exit(1); 1855 } 1856 spapr->rtas_size = get_image_size(filename); 1857 spapr->rtas_blob = g_malloc(spapr->rtas_size); 1858 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 1859 error_report("Could not load LPAR rtas '%s'", filename); 1860 exit(1); 1861 } 1862 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1863 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 1864 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 1865 exit(1); 1866 } 1867 g_free(filename); 1868 1869 /* Set up EPOW events infrastructure */ 1870 spapr_events_init(spapr); 1871 1872 /* Set up the RTC RTAS interfaces */ 1873 spapr_rtc_create(spapr); 1874 1875 /* Set up VIO bus */ 1876 spapr->vio_bus = spapr_vio_bus_init(); 1877 1878 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1879 if (serial_hds[i]) { 1880 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1881 } 1882 } 1883 1884 /* We always have at least the nvram device on VIO */ 1885 spapr_create_nvram(spapr); 1886 1887 /* Set up PCI */ 1888 spapr_pci_rtas_init(); 1889 1890 phb = spapr_create_phb(spapr, 0); 1891 1892 for (i = 0; i < nb_nics; i++) { 1893 NICInfo *nd = &nd_table[i]; 1894 1895 if (!nd->model) { 1896 nd->model = g_strdup("ibmveth"); 1897 } 1898 1899 if (strcmp(nd->model, "ibmveth") == 0) { 1900 spapr_vlan_create(spapr->vio_bus, nd); 1901 } else { 1902 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1903 } 1904 } 1905 1906 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1907 spapr_vscsi_create(spapr->vio_bus); 1908 } 1909 1910 /* Graphics */ 1911 if (spapr_vga_init(phb->bus)) { 1912 spapr->has_graphics = true; 1913 machine->usb |= defaults_enabled() && !machine->usb_disabled; 1914 } 1915 1916 if (machine->usb) { 1917 pci_create_simple(phb->bus, -1, "pci-ohci"); 1918 1919 if (spapr->has_graphics) { 1920 USBBus *usb_bus = usb_bus_find(-1); 1921 1922 usb_create_simple(usb_bus, "usb-kbd"); 1923 usb_create_simple(usb_bus, "usb-mouse"); 1924 } 1925 } 1926 1927 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1928 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " 1929 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); 1930 exit(1); 1931 } 1932 1933 if (kernel_filename) { 1934 uint64_t lowaddr = 0; 1935 1936 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1937 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 0); 1938 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { 1939 kernel_size = load_elf(kernel_filename, 1940 translate_kernel_address, NULL, 1941 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE, 0); 1942 kernel_le = kernel_size > 0; 1943 } 1944 if (kernel_size < 0) { 1945 fprintf(stderr, "qemu: error loading %s: %s\n", 1946 kernel_filename, load_elf_strerror(kernel_size)); 1947 exit(1); 1948 } 1949 1950 /* load initrd */ 1951 if (initrd_filename) { 1952 /* Try to locate the initrd in the gap between the kernel 1953 * and the firmware. Add a bit of space just in case 1954 */ 1955 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1956 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1957 load_limit - initrd_base); 1958 if (initrd_size < 0) { 1959 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 1960 initrd_filename); 1961 exit(1); 1962 } 1963 } else { 1964 initrd_base = 0; 1965 initrd_size = 0; 1966 } 1967 } 1968 1969 if (bios_name == NULL) { 1970 bios_name = FW_FILE_NAME; 1971 } 1972 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1973 if (!filename) { 1974 error_report("Could not find LPAR firmware '%s'", bios_name); 1975 exit(1); 1976 } 1977 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 1978 if (fw_size <= 0) { 1979 error_report("Could not load LPAR firmware '%s'", filename); 1980 exit(1); 1981 } 1982 g_free(filename); 1983 1984 /* FIXME: Should register things through the MachineState's qdev 1985 * interface, this is a legacy from the sPAPREnvironment structure 1986 * which predated MachineState but had a similar function */ 1987 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 1988 register_savevm_live(NULL, "spapr/htab", -1, 1, 1989 &savevm_htab_handlers, spapr); 1990 1991 /* Prepare the device tree */ 1992 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 1993 kernel_size, kernel_le, 1994 kernel_cmdline, 1995 spapr->check_exception_irq); 1996 assert(spapr->fdt_skel != NULL); 1997 1998 /* used by RTAS */ 1999 QTAILQ_INIT(&spapr->ccs_list); 2000 qemu_register_reset(spapr_ccs_reset_hook, spapr); 2001 2002 qemu_register_boot_set(spapr_boot_set, spapr); 2003 } 2004 2005 static int spapr_kvm_type(const char *vm_type) 2006 { 2007 if (!vm_type) { 2008 return 0; 2009 } 2010 2011 if (!strcmp(vm_type, "HV")) { 2012 return 1; 2013 } 2014 2015 if (!strcmp(vm_type, "PR")) { 2016 return 2; 2017 } 2018 2019 error_report("Unknown kvm-type specified '%s'", vm_type); 2020 exit(1); 2021 } 2022 2023 /* 2024 * Implementation of an interface to adjust firmware path 2025 * for the bootindex property handling. 2026 */ 2027 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2028 DeviceState *dev) 2029 { 2030 #define CAST(type, obj, name) \ 2031 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2032 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2033 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2034 2035 if (d) { 2036 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2037 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2038 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2039 2040 if (spapr) { 2041 /* 2042 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2043 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2044 * in the top 16 bits of the 64-bit LUN 2045 */ 2046 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2047 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2048 (uint64_t)id << 48); 2049 } else if (virtio) { 2050 /* 2051 * We use SRP luns of the form 01000000 | (target << 8) | lun 2052 * in the top 32 bits of the 64-bit LUN 2053 * Note: the quote above is from SLOF and it is wrong, 2054 * the actual binding is: 2055 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2056 */ 2057 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2058 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2059 (uint64_t)id << 32); 2060 } else if (usb) { 2061 /* 2062 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2063 * in the top 32 bits of the 64-bit LUN 2064 */ 2065 unsigned usb_port = atoi(usb->port->path); 2066 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2067 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2068 (uint64_t)id << 32); 2069 } 2070 } 2071 2072 if (phb) { 2073 /* Replace "pci" with "pci@800000020000000" */ 2074 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2075 } 2076 2077 return NULL; 2078 } 2079 2080 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2081 { 2082 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2083 2084 return g_strdup(spapr->kvm_type); 2085 } 2086 2087 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2088 { 2089 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2090 2091 g_free(spapr->kvm_type); 2092 spapr->kvm_type = g_strdup(value); 2093 } 2094 2095 static void spapr_machine_initfn(Object *obj) 2096 { 2097 object_property_add_str(obj, "kvm-type", 2098 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2099 object_property_set_description(obj, "kvm-type", 2100 "Specifies the KVM virtualization mode (HV, PR)", 2101 NULL); 2102 } 2103 2104 static void ppc_cpu_do_nmi_on_cpu(void *arg) 2105 { 2106 CPUState *cs = arg; 2107 2108 cpu_synchronize_state(cs); 2109 ppc_cpu_do_system_reset(cs); 2110 } 2111 2112 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2113 { 2114 CPUState *cs; 2115 2116 CPU_FOREACH(cs) { 2117 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs); 2118 } 2119 } 2120 2121 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size, 2122 uint32_t node, Error **errp) 2123 { 2124 sPAPRDRConnector *drc; 2125 sPAPRDRConnectorClass *drck; 2126 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2127 int i, fdt_offset, fdt_size; 2128 void *fdt; 2129 2130 /* 2131 * Check for DRC connectors and send hotplug notification to the 2132 * guest only in case of hotplugged memory. This allows cold plugged 2133 * memory to be specified at boot time. 2134 */ 2135 if (!dev->hotplugged) { 2136 return; 2137 } 2138 2139 for (i = 0; i < nr_lmbs; i++) { 2140 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2141 addr/SPAPR_MEMORY_BLOCK_SIZE); 2142 g_assert(drc); 2143 2144 fdt = create_device_tree(&fdt_size); 2145 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2146 SPAPR_MEMORY_BLOCK_SIZE); 2147 2148 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2149 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2150 addr += SPAPR_MEMORY_BLOCK_SIZE; 2151 } 2152 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs); 2153 } 2154 2155 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2156 uint32_t node, Error **errp) 2157 { 2158 Error *local_err = NULL; 2159 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2160 PCDIMMDevice *dimm = PC_DIMM(dev); 2161 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2162 MemoryRegion *mr = ddc->get_memory_region(dimm); 2163 uint64_t align = memory_region_get_alignment(mr); 2164 uint64_t size = memory_region_size(mr); 2165 uint64_t addr; 2166 2167 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2168 error_setg(&local_err, "Hotplugged memory size must be a multiple of " 2169 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 2170 goto out; 2171 } 2172 2173 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2174 if (local_err) { 2175 goto out; 2176 } 2177 2178 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2179 if (local_err) { 2180 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2181 goto out; 2182 } 2183 2184 spapr_add_lmbs(dev, addr, size, node, &error_abort); 2185 2186 out: 2187 error_propagate(errp, local_err); 2188 } 2189 2190 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 2191 DeviceState *dev, Error **errp) 2192 { 2193 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2194 2195 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2196 int node; 2197 2198 if (!smc->dr_lmb_enabled) { 2199 error_setg(errp, "Memory hotplug not supported for this machine"); 2200 return; 2201 } 2202 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 2203 if (*errp) { 2204 return; 2205 } 2206 2207 /* 2208 * Currently PowerPC kernel doesn't allow hot-adding memory to 2209 * memory-less node, but instead will silently add the memory 2210 * to the first node that has some memory. This causes two 2211 * unexpected behaviours for the user. 2212 * 2213 * - Memory gets hotplugged to a different node than what the user 2214 * specified. 2215 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 2216 * to memory-less node, a reboot will set things accordingly 2217 * and the previously hotplugged memory now ends in the right node. 2218 * This appears as if some memory moved from one node to another. 2219 * 2220 * So until kernel starts supporting memory hotplug to memory-less 2221 * nodes, just prevent such attempts upfront in QEMU. 2222 */ 2223 if (nb_numa_nodes && !numa_info[node].node_mem) { 2224 error_setg(errp, "Can't hotplug memory to memory-less node %d", 2225 node); 2226 return; 2227 } 2228 2229 spapr_memory_plug(hotplug_dev, dev, node, errp); 2230 } 2231 } 2232 2233 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 2234 DeviceState *dev, Error **errp) 2235 { 2236 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2237 error_setg(errp, "Memory hot unplug not supported by sPAPR"); 2238 } 2239 } 2240 2241 static HotplugHandler *spapr_get_hotpug_handler(MachineState *machine, 2242 DeviceState *dev) 2243 { 2244 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2245 return HOTPLUG_HANDLER(machine); 2246 } 2247 return NULL; 2248 } 2249 2250 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index) 2251 { 2252 /* Allocate to NUMA nodes on a "socket" basis (not that concept of 2253 * socket means much for the paravirtualized PAPR platform) */ 2254 return cpu_index / smp_threads / smp_cores; 2255 } 2256 2257 static void spapr_machine_class_init(ObjectClass *oc, void *data) 2258 { 2259 MachineClass *mc = MACHINE_CLASS(oc); 2260 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 2261 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 2262 NMIClass *nc = NMI_CLASS(oc); 2263 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2264 2265 mc->init = ppc_spapr_init; 2266 mc->reset = ppc_spapr_reset; 2267 mc->block_default_type = IF_SCSI; 2268 mc->max_cpus = MAX_CPUMASK_BITS; 2269 mc->no_parallel = 1; 2270 mc->default_boot_order = ""; 2271 mc->default_ram_size = 512 * M_BYTE; 2272 mc->kvm_type = spapr_kvm_type; 2273 mc->has_dynamic_sysbus = true; 2274 mc->pci_allow_0_address = true; 2275 mc->get_hotplug_handler = spapr_get_hotpug_handler; 2276 hc->plug = spapr_machine_device_plug; 2277 hc->unplug = spapr_machine_device_unplug; 2278 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; 2279 2280 smc->dr_lmb_enabled = false; 2281 fwc->get_dev_path = spapr_get_fw_dev_path; 2282 nc->nmi_monitor_handler = spapr_nmi; 2283 } 2284 2285 static const TypeInfo spapr_machine_info = { 2286 .name = TYPE_SPAPR_MACHINE, 2287 .parent = TYPE_MACHINE, 2288 .abstract = true, 2289 .instance_size = sizeof(sPAPRMachineState), 2290 .instance_init = spapr_machine_initfn, 2291 .class_size = sizeof(sPAPRMachineClass), 2292 .class_init = spapr_machine_class_init, 2293 .interfaces = (InterfaceInfo[]) { 2294 { TYPE_FW_PATH_PROVIDER }, 2295 { TYPE_NMI }, 2296 { TYPE_HOTPLUG_HANDLER }, 2297 { } 2298 }, 2299 }; 2300 2301 #define SPAPR_COMPAT_2_4 \ 2302 HW_COMPAT_2_4 2303 2304 #define SPAPR_COMPAT_2_3 \ 2305 SPAPR_COMPAT_2_4 \ 2306 HW_COMPAT_2_3 \ 2307 {\ 2308 .driver = "spapr-pci-host-bridge",\ 2309 .property = "dynamic-reconfiguration",\ 2310 .value = "off",\ 2311 }, 2312 2313 #define SPAPR_COMPAT_2_2 \ 2314 SPAPR_COMPAT_2_3 \ 2315 HW_COMPAT_2_2 \ 2316 {\ 2317 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 2318 .property = "mem_win_size",\ 2319 .value = "0x20000000",\ 2320 }, 2321 2322 #define SPAPR_COMPAT_2_1 \ 2323 SPAPR_COMPAT_2_2 \ 2324 HW_COMPAT_2_1 2325 2326 static void spapr_compat_2_3(Object *obj) 2327 { 2328 savevm_skip_section_footers(); 2329 global_state_set_optional(); 2330 } 2331 2332 static void spapr_compat_2_2(Object *obj) 2333 { 2334 spapr_compat_2_3(obj); 2335 } 2336 2337 static void spapr_compat_2_1(Object *obj) 2338 { 2339 spapr_compat_2_2(obj); 2340 } 2341 2342 static void spapr_machine_2_3_instance_init(Object *obj) 2343 { 2344 spapr_compat_2_3(obj); 2345 spapr_machine_initfn(obj); 2346 } 2347 2348 static void spapr_machine_2_2_instance_init(Object *obj) 2349 { 2350 spapr_compat_2_2(obj); 2351 spapr_machine_initfn(obj); 2352 } 2353 2354 static void spapr_machine_2_1_instance_init(Object *obj) 2355 { 2356 spapr_compat_2_1(obj); 2357 spapr_machine_initfn(obj); 2358 } 2359 2360 static void spapr_machine_2_1_class_init(ObjectClass *oc, void *data) 2361 { 2362 MachineClass *mc = MACHINE_CLASS(oc); 2363 static GlobalProperty compat_props[] = { 2364 SPAPR_COMPAT_2_1 2365 { /* end of list */ } 2366 }; 2367 2368 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.1"; 2369 mc->compat_props = compat_props; 2370 } 2371 2372 static const TypeInfo spapr_machine_2_1_info = { 2373 .name = MACHINE_TYPE_NAME("pseries-2.1"), 2374 .parent = TYPE_SPAPR_MACHINE, 2375 .class_init = spapr_machine_2_1_class_init, 2376 .instance_init = spapr_machine_2_1_instance_init, 2377 }; 2378 2379 static void spapr_machine_2_2_class_init(ObjectClass *oc, void *data) 2380 { 2381 static GlobalProperty compat_props[] = { 2382 SPAPR_COMPAT_2_2 2383 { /* end of list */ } 2384 }; 2385 MachineClass *mc = MACHINE_CLASS(oc); 2386 2387 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.2"; 2388 mc->compat_props = compat_props; 2389 } 2390 2391 static const TypeInfo spapr_machine_2_2_info = { 2392 .name = MACHINE_TYPE_NAME("pseries-2.2"), 2393 .parent = TYPE_SPAPR_MACHINE, 2394 .class_init = spapr_machine_2_2_class_init, 2395 .instance_init = spapr_machine_2_2_instance_init, 2396 }; 2397 2398 static void spapr_machine_2_3_class_init(ObjectClass *oc, void *data) 2399 { 2400 static GlobalProperty compat_props[] = { 2401 SPAPR_COMPAT_2_3 2402 { /* end of list */ } 2403 }; 2404 MachineClass *mc = MACHINE_CLASS(oc); 2405 2406 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.3"; 2407 mc->compat_props = compat_props; 2408 } 2409 2410 static const TypeInfo spapr_machine_2_3_info = { 2411 .name = MACHINE_TYPE_NAME("pseries-2.3"), 2412 .parent = TYPE_SPAPR_MACHINE, 2413 .class_init = spapr_machine_2_3_class_init, 2414 .instance_init = spapr_machine_2_3_instance_init, 2415 }; 2416 2417 static void spapr_machine_2_4_class_init(ObjectClass *oc, void *data) 2418 { 2419 static GlobalProperty compat_props[] = { 2420 SPAPR_COMPAT_2_4 2421 { /* end of list */ } 2422 }; 2423 MachineClass *mc = MACHINE_CLASS(oc); 2424 2425 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.4"; 2426 mc->compat_props = compat_props; 2427 } 2428 2429 static const TypeInfo spapr_machine_2_4_info = { 2430 .name = MACHINE_TYPE_NAME("pseries-2.4"), 2431 .parent = TYPE_SPAPR_MACHINE, 2432 .class_init = spapr_machine_2_4_class_init, 2433 }; 2434 2435 static void spapr_machine_2_5_class_init(ObjectClass *oc, void *data) 2436 { 2437 MachineClass *mc = MACHINE_CLASS(oc); 2438 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 2439 2440 mc->name = "pseries-2.5"; 2441 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.5"; 2442 mc->alias = "pseries"; 2443 mc->is_default = 1; 2444 smc->dr_lmb_enabled = true; 2445 } 2446 2447 static const TypeInfo spapr_machine_2_5_info = { 2448 .name = MACHINE_TYPE_NAME("pseries-2.5"), 2449 .parent = TYPE_SPAPR_MACHINE, 2450 .class_init = spapr_machine_2_5_class_init, 2451 }; 2452 2453 static void spapr_machine_register_types(void) 2454 { 2455 type_register_static(&spapr_machine_info); 2456 type_register_static(&spapr_machine_2_1_info); 2457 type_register_static(&spapr_machine_2_2_info); 2458 type_register_static(&spapr_machine_2_3_info); 2459 type_register_static(&spapr_machine_2_4_info); 2460 type_register_static(&spapr_machine_2_5_info); 2461 } 2462 2463 type_init(spapr_machine_register_types) 2464