1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/numa.h" 32 #include "hw/hw.h" 33 #include "qemu/log.h" 34 #include "hw/fw-path-provider.h" 35 #include "elf.h" 36 #include "net/net.h" 37 #include "sysemu/device_tree.h" 38 #include "sysemu/block-backend.h" 39 #include "sysemu/cpus.h" 40 #include "sysemu/hw_accel.h" 41 #include "kvm_ppc.h" 42 #include "migration/misc.h" 43 #include "migration/global_state.h" 44 #include "migration/register.h" 45 #include "mmu-hash64.h" 46 #include "mmu-book3s-v3.h" 47 #include "cpu-models.h" 48 #include "qom/cpu.h" 49 50 #include "hw/boards.h" 51 #include "hw/ppc/ppc.h" 52 #include "hw/loader.h" 53 54 #include "hw/ppc/fdt.h" 55 #include "hw/ppc/spapr.h" 56 #include "hw/ppc/spapr_vio.h" 57 #include "hw/pci-host/spapr.h" 58 #include "hw/ppc/xics.h" 59 #include "hw/pci/msi.h" 60 61 #include "hw/pci/pci.h" 62 #include "hw/scsi/scsi.h" 63 #include "hw/virtio/virtio-scsi.h" 64 #include "hw/virtio/vhost-scsi-common.h" 65 66 #include "exec/address-spaces.h" 67 #include "hw/usb.h" 68 #include "qemu/config-file.h" 69 #include "qemu/error-report.h" 70 #include "trace.h" 71 #include "hw/nmi.h" 72 #include "hw/intc/intc.h" 73 74 #include "hw/compat.h" 75 #include "qemu/cutils.h" 76 #include "hw/ppc/spapr_cpu_core.h" 77 78 #include <libfdt.h> 79 80 /* SLOF memory layout: 81 * 82 * SLOF raw image loaded at 0, copies its romfs right below the flat 83 * device-tree, then position SLOF itself 31M below that 84 * 85 * So we set FW_OVERHEAD to 40MB which should account for all of that 86 * and more 87 * 88 * We load our kernel at 4M, leaving space for SLOF initial image 89 */ 90 #define FDT_MAX_SIZE 0x100000 91 #define RTAS_MAX_SIZE 0x10000 92 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 93 #define FW_MAX_SIZE 0x400000 94 #define FW_FILE_NAME "slof.bin" 95 #define FW_OVERHEAD 0x2800000 96 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 97 98 #define MIN_RMA_SLOF 128UL 99 100 #define PHANDLE_XICP 0x00001111 101 102 /* These two functions implement the VCPU id numbering: one to compute them 103 * all and one to identify thread 0 of a VCORE. Any change to the first one 104 * is likely to have an impact on the second one, so let's keep them close. 105 */ 106 static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index) 107 { 108 assert(spapr->vsmt); 109 return 110 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 111 } 112 static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr, 113 PowerPCCPU *cpu) 114 { 115 assert(spapr->vsmt); 116 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 117 } 118 119 static ICSState *spapr_ics_create(sPAPRMachineState *spapr, 120 const char *type_ics, 121 int nr_irqs, Error **errp) 122 { 123 Error *local_err = NULL; 124 Object *obj; 125 126 obj = object_new(type_ics); 127 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); 128 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), 129 &error_abort); 130 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); 131 if (local_err) { 132 goto error; 133 } 134 object_property_set_bool(obj, true, "realized", &local_err); 135 if (local_err) { 136 goto error; 137 } 138 139 return ICS_SIMPLE(obj); 140 141 error: 142 error_propagate(errp, local_err); 143 return NULL; 144 } 145 146 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 147 { 148 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 149 * and newer QEMUs don't even have them. In both cases, we don't want 150 * to send anything on the wire. 151 */ 152 return false; 153 } 154 155 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 156 .name = "icp/server", 157 .version_id = 1, 158 .minimum_version_id = 1, 159 .needed = pre_2_10_vmstate_dummy_icp_needed, 160 .fields = (VMStateField[]) { 161 VMSTATE_UNUSED(4), /* uint32_t xirr */ 162 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 163 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 164 VMSTATE_END_OF_LIST() 165 }, 166 }; 167 168 static void pre_2_10_vmstate_register_dummy_icp(int i) 169 { 170 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 171 (void *)(uintptr_t) i); 172 } 173 174 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 175 { 176 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 177 (void *)(uintptr_t) i); 178 } 179 180 static int xics_max_server_number(sPAPRMachineState *spapr) 181 { 182 assert(spapr->vsmt); 183 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads); 184 } 185 186 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) 187 { 188 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 189 190 if (kvm_enabled()) { 191 if (machine_kernel_irqchip_allowed(machine) && 192 !xics_kvm_init(spapr, errp)) { 193 spapr->icp_type = TYPE_KVM_ICP; 194 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp); 195 } 196 if (machine_kernel_irqchip_required(machine) && !spapr->ics) { 197 error_prepend(errp, "kernel_irqchip requested but unavailable: "); 198 return; 199 } 200 } 201 202 if (!spapr->ics) { 203 xics_spapr_init(spapr); 204 spapr->icp_type = TYPE_ICP; 205 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp); 206 if (!spapr->ics) { 207 return; 208 } 209 } 210 } 211 212 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 213 int smt_threads) 214 { 215 int i, ret = 0; 216 uint32_t servers_prop[smt_threads]; 217 uint32_t gservers_prop[smt_threads * 2]; 218 int index = spapr_get_vcpu_id(cpu); 219 220 if (cpu->compat_pvr) { 221 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 222 if (ret < 0) { 223 return ret; 224 } 225 } 226 227 /* Build interrupt servers and gservers properties */ 228 for (i = 0; i < smt_threads; i++) { 229 servers_prop[i] = cpu_to_be32(index + i); 230 /* Hack, direct the group queues back to cpu 0 */ 231 gservers_prop[i*2] = cpu_to_be32(index + i); 232 gservers_prop[i*2 + 1] = 0; 233 } 234 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 235 servers_prop, sizeof(servers_prop)); 236 if (ret < 0) { 237 return ret; 238 } 239 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 240 gservers_prop, sizeof(gservers_prop)); 241 242 return ret; 243 } 244 245 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 246 { 247 int index = spapr_get_vcpu_id(cpu); 248 uint32_t associativity[] = {cpu_to_be32(0x5), 249 cpu_to_be32(0x0), 250 cpu_to_be32(0x0), 251 cpu_to_be32(0x0), 252 cpu_to_be32(cpu->node_id), 253 cpu_to_be32(index)}; 254 255 /* Advertise NUMA via ibm,associativity */ 256 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 257 sizeof(associativity)); 258 } 259 260 /* Populate the "ibm,pa-features" property */ 261 static void spapr_populate_pa_features(sPAPRMachineState *spapr, 262 PowerPCCPU *cpu, 263 void *fdt, int offset, 264 bool legacy_guest) 265 { 266 CPUPPCState *env = &cpu->env; 267 uint8_t pa_features_206[] = { 6, 0, 268 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 269 uint8_t pa_features_207[] = { 24, 0, 270 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 271 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 272 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 273 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 274 uint8_t pa_features_300[] = { 66, 0, 275 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 276 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 277 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 278 /* 6: DS207 */ 279 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 280 /* 16: Vector */ 281 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 282 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 283 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 284 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 285 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 286 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 287 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 288 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 289 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 290 /* 42: PM, 44: PC RA, 46: SC vec'd */ 291 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 292 /* 48: SIMD, 50: QP BFP, 52: String */ 293 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 294 /* 54: DecFP, 56: DecI, 58: SHA */ 295 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 296 /* 60: NM atomic, 62: RNG */ 297 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 298 }; 299 uint8_t *pa_features = NULL; 300 size_t pa_size; 301 302 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 303 pa_features = pa_features_206; 304 pa_size = sizeof(pa_features_206); 305 } 306 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 307 pa_features = pa_features_207; 308 pa_size = sizeof(pa_features_207); 309 } 310 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 311 pa_features = pa_features_300; 312 pa_size = sizeof(pa_features_300); 313 } 314 if (!pa_features) { 315 return; 316 } 317 318 if (env->ci_large_pages) { 319 /* 320 * Note: we keep CI large pages off by default because a 64K capable 321 * guest provisioned with large pages might otherwise try to map a qemu 322 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 323 * even if that qemu runs on a 4k host. 324 * We dd this bit back here if we are confident this is not an issue 325 */ 326 pa_features[3] |= 0x20; 327 } 328 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 329 pa_features[24] |= 0x80; /* Transactional memory support */ 330 } 331 if (legacy_guest && pa_size > 40) { 332 /* Workaround for broken kernels that attempt (guest) radix 333 * mode when they can't handle it, if they see the radix bit set 334 * in pa-features. So hide it from them. */ 335 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 336 } 337 338 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 339 } 340 341 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 342 { 343 int ret = 0, offset, cpus_offset; 344 CPUState *cs; 345 char cpu_model[32]; 346 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 347 348 CPU_FOREACH(cs) { 349 PowerPCCPU *cpu = POWERPC_CPU(cs); 350 DeviceClass *dc = DEVICE_GET_CLASS(cs); 351 int index = spapr_get_vcpu_id(cpu); 352 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 353 354 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 355 continue; 356 } 357 358 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 359 360 cpus_offset = fdt_path_offset(fdt, "/cpus"); 361 if (cpus_offset < 0) { 362 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 363 if (cpus_offset < 0) { 364 return cpus_offset; 365 } 366 } 367 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 368 if (offset < 0) { 369 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 370 if (offset < 0) { 371 return offset; 372 } 373 } 374 375 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 376 pft_size_prop, sizeof(pft_size_prop)); 377 if (ret < 0) { 378 return ret; 379 } 380 381 if (nb_numa_nodes > 1) { 382 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 383 if (ret < 0) { 384 return ret; 385 } 386 } 387 388 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 389 if (ret < 0) { 390 return ret; 391 } 392 393 spapr_populate_pa_features(spapr, cpu, fdt, offset, 394 spapr->cas_legacy_guest_workaround); 395 } 396 return ret; 397 } 398 399 static hwaddr spapr_node0_size(MachineState *machine) 400 { 401 if (nb_numa_nodes) { 402 int i; 403 for (i = 0; i < nb_numa_nodes; ++i) { 404 if (numa_info[i].node_mem) { 405 return MIN(pow2floor(numa_info[i].node_mem), 406 machine->ram_size); 407 } 408 } 409 } 410 return machine->ram_size; 411 } 412 413 static void add_str(GString *s, const gchar *s1) 414 { 415 g_string_append_len(s, s1, strlen(s1) + 1); 416 } 417 418 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 419 hwaddr size) 420 { 421 uint32_t associativity[] = { 422 cpu_to_be32(0x4), /* length */ 423 cpu_to_be32(0x0), cpu_to_be32(0x0), 424 cpu_to_be32(0x0), cpu_to_be32(nodeid) 425 }; 426 char mem_name[32]; 427 uint64_t mem_reg_property[2]; 428 int off; 429 430 mem_reg_property[0] = cpu_to_be64(start); 431 mem_reg_property[1] = cpu_to_be64(size); 432 433 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 434 off = fdt_add_subnode(fdt, 0, mem_name); 435 _FDT(off); 436 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 437 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 438 sizeof(mem_reg_property)))); 439 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 440 sizeof(associativity)))); 441 return off; 442 } 443 444 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 445 { 446 MachineState *machine = MACHINE(spapr); 447 hwaddr mem_start, node_size; 448 int i, nb_nodes = nb_numa_nodes; 449 NodeInfo *nodes = numa_info; 450 NodeInfo ramnode; 451 452 /* No NUMA nodes, assume there is just one node with whole RAM */ 453 if (!nb_numa_nodes) { 454 nb_nodes = 1; 455 ramnode.node_mem = machine->ram_size; 456 nodes = &ramnode; 457 } 458 459 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 460 if (!nodes[i].node_mem) { 461 continue; 462 } 463 if (mem_start >= machine->ram_size) { 464 node_size = 0; 465 } else { 466 node_size = nodes[i].node_mem; 467 if (node_size > machine->ram_size - mem_start) { 468 node_size = machine->ram_size - mem_start; 469 } 470 } 471 if (!mem_start) { 472 /* spapr_machine_init() checks for rma_size <= node0_size 473 * already */ 474 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 475 mem_start += spapr->rma_size; 476 node_size -= spapr->rma_size; 477 } 478 for ( ; node_size; ) { 479 hwaddr sizetmp = pow2floor(node_size); 480 481 /* mem_start != 0 here */ 482 if (ctzl(mem_start) < ctzl(sizetmp)) { 483 sizetmp = 1ULL << ctzl(mem_start); 484 } 485 486 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 487 node_size -= sizetmp; 488 mem_start += sizetmp; 489 } 490 } 491 492 return 0; 493 } 494 495 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 496 sPAPRMachineState *spapr) 497 { 498 PowerPCCPU *cpu = POWERPC_CPU(cs); 499 CPUPPCState *env = &cpu->env; 500 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 501 int index = spapr_get_vcpu_id(cpu); 502 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 503 0xffffffff, 0xffffffff}; 504 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 505 : SPAPR_TIMEBASE_FREQ; 506 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 507 uint32_t page_sizes_prop[64]; 508 size_t page_sizes_prop_size; 509 uint32_t vcpus_per_socket = smp_threads * smp_cores; 510 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 511 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 512 sPAPRDRConnector *drc; 513 int drc_index; 514 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 515 int i; 516 517 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 518 if (drc) { 519 drc_index = spapr_drc_index(drc); 520 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 521 } 522 523 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 524 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 525 526 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 527 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 528 env->dcache_line_size))); 529 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 530 env->dcache_line_size))); 531 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 532 env->icache_line_size))); 533 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 534 env->icache_line_size))); 535 536 if (pcc->l1_dcache_size) { 537 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 538 pcc->l1_dcache_size))); 539 } else { 540 warn_report("Unknown L1 dcache size for cpu"); 541 } 542 if (pcc->l1_icache_size) { 543 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 544 pcc->l1_icache_size))); 545 } else { 546 warn_report("Unknown L1 icache size for cpu"); 547 } 548 549 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 550 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 551 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 552 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 553 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 554 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 555 556 if (env->spr_cb[SPR_PURR].oea_read) { 557 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 558 } 559 560 if (env->mmu_model & POWERPC_MMU_1TSEG) { 561 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 562 segs, sizeof(segs)))); 563 } 564 565 /* Advertise VSX (vector extensions) if available 566 * 1 == VMX / Altivec available 567 * 2 == VSX available 568 * 569 * Only CPUs for which we create core types in spapr_cpu_core.c 570 * are possible, and all of those have VMX */ 571 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 572 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 573 } else { 574 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 575 } 576 577 /* Advertise DFP (Decimal Floating Point) if available 578 * 0 / no property == no DFP 579 * 1 == DFP available */ 580 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 581 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 582 } 583 584 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 585 sizeof(page_sizes_prop)); 586 if (page_sizes_prop_size) { 587 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 588 page_sizes_prop, page_sizes_prop_size))); 589 } 590 591 spapr_populate_pa_features(spapr, cpu, fdt, offset, false); 592 593 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 594 cs->cpu_index / vcpus_per_socket))); 595 596 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 597 pft_size_prop, sizeof(pft_size_prop)))); 598 599 if (nb_numa_nodes > 1) { 600 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 601 } 602 603 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 604 605 if (pcc->radix_page_info) { 606 for (i = 0; i < pcc->radix_page_info->count; i++) { 607 radix_AP_encodings[i] = 608 cpu_to_be32(pcc->radix_page_info->entries[i]); 609 } 610 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 611 radix_AP_encodings, 612 pcc->radix_page_info->count * 613 sizeof(radix_AP_encodings[0])))); 614 } 615 } 616 617 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 618 { 619 CPUState *cs; 620 int cpus_offset; 621 char *nodename; 622 623 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 624 _FDT(cpus_offset); 625 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 626 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 627 628 /* 629 * We walk the CPUs in reverse order to ensure that CPU DT nodes 630 * created by fdt_add_subnode() end up in the right order in FDT 631 * for the guest kernel the enumerate the CPUs correctly. 632 */ 633 CPU_FOREACH_REVERSE(cs) { 634 PowerPCCPU *cpu = POWERPC_CPU(cs); 635 int index = spapr_get_vcpu_id(cpu); 636 DeviceClass *dc = DEVICE_GET_CLASS(cs); 637 int offset; 638 639 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 640 continue; 641 } 642 643 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 644 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 645 g_free(nodename); 646 _FDT(offset); 647 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 648 } 649 650 } 651 652 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 653 { 654 MemoryDeviceInfoList *info; 655 656 for (info = list; info; info = info->next) { 657 MemoryDeviceInfo *value = info->value; 658 659 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 660 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 661 662 if (pcdimm_info->addr >= addr && 663 addr < (pcdimm_info->addr + pcdimm_info->size)) { 664 return pcdimm_info->node; 665 } 666 } 667 } 668 669 return -1; 670 } 671 672 /* 673 * Adds ibm,dynamic-reconfiguration-memory node. 674 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 675 * of this device tree node. 676 */ 677 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 678 { 679 MachineState *machine = MACHINE(spapr); 680 int ret, i, offset; 681 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 682 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 683 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 684 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 685 memory_region_size(&spapr->hotplug_memory.mr)) / 686 lmb_size; 687 uint32_t *int_buf, *cur_index, buf_len; 688 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 689 MemoryDeviceInfoList *dimms = NULL; 690 691 /* 692 * Don't create the node if there is no hotpluggable memory 693 */ 694 if (machine->ram_size == machine->maxram_size) { 695 return 0; 696 } 697 698 /* 699 * Allocate enough buffer size to fit in ibm,dynamic-memory 700 * or ibm,associativity-lookup-arrays 701 */ 702 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 703 * sizeof(uint32_t); 704 cur_index = int_buf = g_malloc0(buf_len); 705 706 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 707 708 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 709 sizeof(prop_lmb_size)); 710 if (ret < 0) { 711 goto out; 712 } 713 714 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 715 if (ret < 0) { 716 goto out; 717 } 718 719 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 720 if (ret < 0) { 721 goto out; 722 } 723 724 if (hotplug_lmb_start) { 725 MemoryDeviceInfoList **prev = &dimms; 726 qmp_pc_dimm_device_list(qdev_get_machine(), &prev); 727 } 728 729 /* ibm,dynamic-memory */ 730 int_buf[0] = cpu_to_be32(nr_lmbs); 731 cur_index++; 732 for (i = 0; i < nr_lmbs; i++) { 733 uint64_t addr = i * lmb_size; 734 uint32_t *dynamic_memory = cur_index; 735 736 if (i >= hotplug_lmb_start) { 737 sPAPRDRConnector *drc; 738 739 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 740 g_assert(drc); 741 742 dynamic_memory[0] = cpu_to_be32(addr >> 32); 743 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 744 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 745 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 746 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 747 if (memory_region_present(get_system_memory(), addr)) { 748 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 749 } else { 750 dynamic_memory[5] = cpu_to_be32(0); 751 } 752 } else { 753 /* 754 * LMB information for RMA, boot time RAM and gap b/n RAM and 755 * hotplug memory region -- all these are marked as reserved 756 * and as having no valid DRC. 757 */ 758 dynamic_memory[0] = cpu_to_be32(addr >> 32); 759 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 760 dynamic_memory[2] = cpu_to_be32(0); 761 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 762 dynamic_memory[4] = cpu_to_be32(-1); 763 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 764 SPAPR_LMB_FLAGS_DRC_INVALID); 765 } 766 767 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 768 } 769 qapi_free_MemoryDeviceInfoList(dimms); 770 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 771 if (ret < 0) { 772 goto out; 773 } 774 775 /* ibm,associativity-lookup-arrays */ 776 cur_index = int_buf; 777 int_buf[0] = cpu_to_be32(nr_nodes); 778 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 779 cur_index += 2; 780 for (i = 0; i < nr_nodes; i++) { 781 uint32_t associativity[] = { 782 cpu_to_be32(0x0), 783 cpu_to_be32(0x0), 784 cpu_to_be32(0x0), 785 cpu_to_be32(i) 786 }; 787 memcpy(cur_index, associativity, sizeof(associativity)); 788 cur_index += 4; 789 } 790 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 791 (cur_index - int_buf) * sizeof(uint32_t)); 792 out: 793 g_free(int_buf); 794 return ret; 795 } 796 797 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 798 sPAPROptionVector *ov5_updates) 799 { 800 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 801 int ret = 0, offset; 802 803 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 804 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 805 g_assert(smc->dr_lmb_enabled); 806 ret = spapr_populate_drconf_memory(spapr, fdt); 807 if (ret) { 808 goto out; 809 } 810 } 811 812 offset = fdt_path_offset(fdt, "/chosen"); 813 if (offset < 0) { 814 offset = fdt_add_subnode(fdt, 0, "chosen"); 815 if (offset < 0) { 816 return offset; 817 } 818 } 819 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 820 "ibm,architecture-vec-5"); 821 822 out: 823 return ret; 824 } 825 826 static bool spapr_hotplugged_dev_before_cas(void) 827 { 828 Object *drc_container, *obj; 829 ObjectProperty *prop; 830 ObjectPropertyIterator iter; 831 832 drc_container = container_get(object_get_root(), "/dr-connector"); 833 object_property_iter_init(&iter, drc_container); 834 while ((prop = object_property_iter_next(&iter))) { 835 if (!strstart(prop->type, "link<", NULL)) { 836 continue; 837 } 838 obj = object_property_get_link(drc_container, prop->name, NULL); 839 if (spapr_drc_needed(obj)) { 840 return true; 841 } 842 } 843 return false; 844 } 845 846 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 847 target_ulong addr, target_ulong size, 848 sPAPROptionVector *ov5_updates) 849 { 850 void *fdt, *fdt_skel; 851 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 852 853 if (spapr_hotplugged_dev_before_cas()) { 854 return 1; 855 } 856 857 if (size < sizeof(hdr) || size > FW_MAX_SIZE) { 858 error_report("SLOF provided an unexpected CAS buffer size " 859 TARGET_FMT_lu " (min: %zu, max: %u)", 860 size, sizeof(hdr), FW_MAX_SIZE); 861 exit(EXIT_FAILURE); 862 } 863 864 size -= sizeof(hdr); 865 866 /* Create skeleton */ 867 fdt_skel = g_malloc0(size); 868 _FDT((fdt_create(fdt_skel, size))); 869 _FDT((fdt_begin_node(fdt_skel, ""))); 870 _FDT((fdt_end_node(fdt_skel))); 871 _FDT((fdt_finish(fdt_skel))); 872 fdt = g_malloc0(size); 873 _FDT((fdt_open_into(fdt_skel, fdt, size))); 874 g_free(fdt_skel); 875 876 /* Fixup cpu nodes */ 877 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 878 879 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 880 return -1; 881 } 882 883 /* Pack resulting tree */ 884 _FDT((fdt_pack(fdt))); 885 886 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 887 trace_spapr_cas_failed(size); 888 return -1; 889 } 890 891 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 892 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 893 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 894 g_free(fdt); 895 896 return 0; 897 } 898 899 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 900 { 901 int rtas; 902 GString *hypertas = g_string_sized_new(256); 903 GString *qemu_hypertas = g_string_sized_new(256); 904 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 905 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 906 memory_region_size(&spapr->hotplug_memory.mr); 907 uint32_t lrdr_capacity[] = { 908 cpu_to_be32(max_hotplug_addr >> 32), 909 cpu_to_be32(max_hotplug_addr & 0xffffffff), 910 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 911 cpu_to_be32(max_cpus / smp_threads), 912 }; 913 914 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 915 916 /* hypertas */ 917 add_str(hypertas, "hcall-pft"); 918 add_str(hypertas, "hcall-term"); 919 add_str(hypertas, "hcall-dabr"); 920 add_str(hypertas, "hcall-interrupt"); 921 add_str(hypertas, "hcall-tce"); 922 add_str(hypertas, "hcall-vio"); 923 add_str(hypertas, "hcall-splpar"); 924 add_str(hypertas, "hcall-bulk"); 925 add_str(hypertas, "hcall-set-mode"); 926 add_str(hypertas, "hcall-sprg0"); 927 add_str(hypertas, "hcall-copy"); 928 add_str(hypertas, "hcall-debug"); 929 add_str(qemu_hypertas, "hcall-memop1"); 930 931 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 932 add_str(hypertas, "hcall-multi-tce"); 933 } 934 935 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 936 add_str(hypertas, "hcall-hpt-resize"); 937 } 938 939 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 940 hypertas->str, hypertas->len)); 941 g_string_free(hypertas, TRUE); 942 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 943 qemu_hypertas->str, qemu_hypertas->len)); 944 g_string_free(qemu_hypertas, TRUE); 945 946 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 947 refpoints, sizeof(refpoints))); 948 949 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 950 RTAS_ERROR_LOG_MAX)); 951 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 952 RTAS_EVENT_SCAN_RATE)); 953 954 g_assert(msi_nonbroken); 955 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 956 957 /* 958 * According to PAPR, rtas ibm,os-term does not guarantee a return 959 * back to the guest cpu. 960 * 961 * While an additional ibm,extended-os-term property indicates 962 * that rtas call return will always occur. Set this property. 963 */ 964 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 965 966 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 967 lrdr_capacity, sizeof(lrdr_capacity))); 968 969 spapr_dt_rtas_tokens(fdt, rtas); 970 } 971 972 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features 973 * that the guest may request and thus the valid values for bytes 24..26 of 974 * option vector 5: */ 975 static void spapr_dt_ov5_platform_support(void *fdt, int chosen) 976 { 977 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 978 979 char val[2 * 4] = { 980 23, 0x00, /* Xive mode, filled in below. */ 981 24, 0x00, /* Hash/Radix, filled in below. */ 982 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 983 26, 0x40, /* Radix options: GTSE == yes. */ 984 }; 985 986 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 987 first_ppc_cpu->compat_pvr)) { 988 /* If we're in a pre POWER9 compat mode then the guest should do hash */ 989 val[3] = 0x00; /* Hash */ 990 } else if (kvm_enabled()) { 991 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 992 val[3] = 0x80; /* OV5_MMU_BOTH */ 993 } else if (kvmppc_has_cap_mmu_radix()) { 994 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 995 } else { 996 val[3] = 0x00; /* Hash */ 997 } 998 } else { 999 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1000 val[3] = 0xC0; 1001 } 1002 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1003 val, sizeof(val))); 1004 } 1005 1006 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 1007 { 1008 MachineState *machine = MACHINE(spapr); 1009 int chosen; 1010 const char *boot_device = machine->boot_order; 1011 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1012 size_t cb = 0; 1013 char *bootlist = get_boot_devices_list(&cb, true); 1014 1015 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1016 1017 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 1018 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1019 spapr->initrd_base)); 1020 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1021 spapr->initrd_base + spapr->initrd_size)); 1022 1023 if (spapr->kernel_size) { 1024 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1025 cpu_to_be64(spapr->kernel_size) }; 1026 1027 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1028 &kprop, sizeof(kprop))); 1029 if (spapr->kernel_le) { 1030 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1031 } 1032 } 1033 if (boot_menu) { 1034 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1035 } 1036 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1037 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1038 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1039 1040 if (cb && bootlist) { 1041 int i; 1042 1043 for (i = 0; i < cb; i++) { 1044 if (bootlist[i] == '\n') { 1045 bootlist[i] = ' '; 1046 } 1047 } 1048 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1049 } 1050 1051 if (boot_device && strlen(boot_device)) { 1052 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1053 } 1054 1055 if (!spapr->has_graphics && stdout_path) { 1056 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1057 } 1058 1059 spapr_dt_ov5_platform_support(fdt, chosen); 1060 1061 g_free(stdout_path); 1062 g_free(bootlist); 1063 } 1064 1065 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 1066 { 1067 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1068 * KVM to work under pHyp with some guest co-operation */ 1069 int hypervisor; 1070 uint8_t hypercall[16]; 1071 1072 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1073 /* indicate KVM hypercall interface */ 1074 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1075 if (kvmppc_has_cap_fixup_hcalls()) { 1076 /* 1077 * Older KVM versions with older guest kernels were broken 1078 * with the magic page, don't allow the guest to map it. 1079 */ 1080 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1081 sizeof(hypercall))) { 1082 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1083 hypercall, sizeof(hypercall))); 1084 } 1085 } 1086 } 1087 1088 static void *spapr_build_fdt(sPAPRMachineState *spapr, 1089 hwaddr rtas_addr, 1090 hwaddr rtas_size) 1091 { 1092 MachineState *machine = MACHINE(spapr); 1093 MachineClass *mc = MACHINE_GET_CLASS(machine); 1094 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1095 int ret; 1096 void *fdt; 1097 sPAPRPHBState *phb; 1098 char *buf; 1099 1100 fdt = g_malloc0(FDT_MAX_SIZE); 1101 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1102 1103 /* Root node */ 1104 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1105 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1106 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1107 1108 /* 1109 * Add info to guest to indentify which host is it being run on 1110 * and what is the uuid of the guest 1111 */ 1112 if (kvmppc_get_host_model(&buf)) { 1113 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1114 g_free(buf); 1115 } 1116 if (kvmppc_get_host_serial(&buf)) { 1117 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1118 g_free(buf); 1119 } 1120 1121 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1122 1123 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1124 if (qemu_uuid_set) { 1125 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1126 } 1127 g_free(buf); 1128 1129 if (qemu_get_vm_name()) { 1130 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1131 qemu_get_vm_name())); 1132 } 1133 1134 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1135 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1136 1137 /* /interrupt controller */ 1138 spapr_dt_xics(xics_max_server_number(spapr), fdt, PHANDLE_XICP); 1139 1140 ret = spapr_populate_memory(spapr, fdt); 1141 if (ret < 0) { 1142 error_report("couldn't setup memory nodes in fdt"); 1143 exit(1); 1144 } 1145 1146 /* /vdevice */ 1147 spapr_dt_vdevice(spapr->vio_bus, fdt); 1148 1149 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1150 ret = spapr_rng_populate_dt(fdt); 1151 if (ret < 0) { 1152 error_report("could not set up rng device in the fdt"); 1153 exit(1); 1154 } 1155 } 1156 1157 QLIST_FOREACH(phb, &spapr->phbs, list) { 1158 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 1159 if (ret < 0) { 1160 error_report("couldn't setup PCI devices in fdt"); 1161 exit(1); 1162 } 1163 } 1164 1165 /* cpus */ 1166 spapr_populate_cpus_dt_node(fdt, spapr); 1167 1168 if (smc->dr_lmb_enabled) { 1169 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1170 } 1171 1172 if (mc->has_hotpluggable_cpus) { 1173 int offset = fdt_path_offset(fdt, "/cpus"); 1174 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1175 SPAPR_DR_CONNECTOR_TYPE_CPU); 1176 if (ret < 0) { 1177 error_report("Couldn't set up CPU DR device tree properties"); 1178 exit(1); 1179 } 1180 } 1181 1182 /* /event-sources */ 1183 spapr_dt_events(spapr, fdt); 1184 1185 /* /rtas */ 1186 spapr_dt_rtas(spapr, fdt); 1187 1188 /* /chosen */ 1189 spapr_dt_chosen(spapr, fdt); 1190 1191 /* /hypervisor */ 1192 if (kvm_enabled()) { 1193 spapr_dt_hypervisor(spapr, fdt); 1194 } 1195 1196 /* Build memory reserve map */ 1197 if (spapr->kernel_size) { 1198 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1199 } 1200 if (spapr->initrd_size) { 1201 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1202 } 1203 1204 /* ibm,client-architecture-support updates */ 1205 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1206 if (ret < 0) { 1207 error_report("couldn't setup CAS properties fdt"); 1208 exit(1); 1209 } 1210 1211 return fdt; 1212 } 1213 1214 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1215 { 1216 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1217 } 1218 1219 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1220 PowerPCCPU *cpu) 1221 { 1222 CPUPPCState *env = &cpu->env; 1223 1224 /* The TCG path should also be holding the BQL at this point */ 1225 g_assert(qemu_mutex_iothread_locked()); 1226 1227 if (msr_pr) { 1228 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1229 env->gpr[3] = H_PRIVILEGE; 1230 } else { 1231 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1232 } 1233 } 1234 1235 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1236 { 1237 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1238 1239 return spapr->patb_entry; 1240 } 1241 1242 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1243 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1244 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1245 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1246 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1247 1248 /* 1249 * Get the fd to access the kernel htab, re-opening it if necessary 1250 */ 1251 static int get_htab_fd(sPAPRMachineState *spapr) 1252 { 1253 Error *local_err = NULL; 1254 1255 if (spapr->htab_fd >= 0) { 1256 return spapr->htab_fd; 1257 } 1258 1259 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1260 if (spapr->htab_fd < 0) { 1261 error_report_err(local_err); 1262 } 1263 1264 return spapr->htab_fd; 1265 } 1266 1267 void close_htab_fd(sPAPRMachineState *spapr) 1268 { 1269 if (spapr->htab_fd >= 0) { 1270 close(spapr->htab_fd); 1271 } 1272 spapr->htab_fd = -1; 1273 } 1274 1275 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1276 { 1277 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1278 1279 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1280 } 1281 1282 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1283 { 1284 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1285 1286 assert(kvm_enabled()); 1287 1288 if (!spapr->htab) { 1289 return 0; 1290 } 1291 1292 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1293 } 1294 1295 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1296 hwaddr ptex, int n) 1297 { 1298 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1299 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1300 1301 if (!spapr->htab) { 1302 /* 1303 * HTAB is controlled by KVM. Fetch into temporary buffer 1304 */ 1305 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1306 kvmppc_read_hptes(hptes, ptex, n); 1307 return hptes; 1308 } 1309 1310 /* 1311 * HTAB is controlled by QEMU. Just point to the internally 1312 * accessible PTEG. 1313 */ 1314 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1315 } 1316 1317 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1318 const ppc_hash_pte64_t *hptes, 1319 hwaddr ptex, int n) 1320 { 1321 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1322 1323 if (!spapr->htab) { 1324 g_free((void *)hptes); 1325 } 1326 1327 /* Nothing to do for qemu managed HPT */ 1328 } 1329 1330 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1331 uint64_t pte0, uint64_t pte1) 1332 { 1333 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1334 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1335 1336 if (!spapr->htab) { 1337 kvmppc_write_hpte(ptex, pte0, pte1); 1338 } else { 1339 stq_p(spapr->htab + offset, pte0); 1340 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1341 } 1342 } 1343 1344 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1345 { 1346 int shift; 1347 1348 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1349 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1350 * that's much more than is needed for Linux guests */ 1351 shift = ctz64(pow2ceil(ramsize)) - 7; 1352 shift = MAX(shift, 18); /* Minimum architected size */ 1353 shift = MIN(shift, 46); /* Maximum architected size */ 1354 return shift; 1355 } 1356 1357 void spapr_free_hpt(sPAPRMachineState *spapr) 1358 { 1359 g_free(spapr->htab); 1360 spapr->htab = NULL; 1361 spapr->htab_shift = 0; 1362 close_htab_fd(spapr); 1363 } 1364 1365 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1366 Error **errp) 1367 { 1368 long rc; 1369 1370 /* Clean up any HPT info from a previous boot */ 1371 spapr_free_hpt(spapr); 1372 1373 rc = kvmppc_reset_htab(shift); 1374 if (rc < 0) { 1375 /* kernel-side HPT needed, but couldn't allocate one */ 1376 error_setg_errno(errp, errno, 1377 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1378 shift); 1379 /* This is almost certainly fatal, but if the caller really 1380 * wants to carry on with shift == 0, it's welcome to try */ 1381 } else if (rc > 0) { 1382 /* kernel-side HPT allocated */ 1383 if (rc != shift) { 1384 error_setg(errp, 1385 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1386 shift, rc); 1387 } 1388 1389 spapr->htab_shift = shift; 1390 spapr->htab = NULL; 1391 } else { 1392 /* kernel-side HPT not needed, allocate in userspace instead */ 1393 size_t size = 1ULL << shift; 1394 int i; 1395 1396 spapr->htab = qemu_memalign(size, size); 1397 if (!spapr->htab) { 1398 error_setg_errno(errp, errno, 1399 "Could not allocate HPT of order %d", shift); 1400 return; 1401 } 1402 1403 memset(spapr->htab, 0, size); 1404 spapr->htab_shift = shift; 1405 1406 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1407 DIRTY_HPTE(HPTE(spapr->htab, i)); 1408 } 1409 } 1410 /* We're setting up a hash table, so that means we're not radix */ 1411 spapr->patb_entry = 0; 1412 } 1413 1414 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1415 { 1416 int hpt_shift; 1417 1418 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1419 || (spapr->cas_reboot 1420 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1421 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1422 } else { 1423 uint64_t current_ram_size; 1424 1425 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1426 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1427 } 1428 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1429 1430 if (spapr->vrma_adjust) { 1431 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1432 spapr->htab_shift); 1433 } 1434 } 1435 1436 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1437 { 1438 bool matched = false; 1439 1440 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1441 matched = true; 1442 } 1443 1444 if (!matched) { 1445 error_report("Device %s is not supported by this machine yet.", 1446 qdev_fw_name(DEVICE(sbdev))); 1447 exit(1); 1448 } 1449 } 1450 1451 static int spapr_reset_drcs(Object *child, void *opaque) 1452 { 1453 sPAPRDRConnector *drc = 1454 (sPAPRDRConnector *) object_dynamic_cast(child, 1455 TYPE_SPAPR_DR_CONNECTOR); 1456 1457 if (drc) { 1458 spapr_drc_reset(drc); 1459 } 1460 1461 return 0; 1462 } 1463 1464 static void spapr_machine_reset(void) 1465 { 1466 MachineState *machine = MACHINE(qdev_get_machine()); 1467 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1468 PowerPCCPU *first_ppc_cpu; 1469 uint32_t rtas_limit; 1470 hwaddr rtas_addr, fdt_addr; 1471 void *fdt; 1472 int rc; 1473 1474 /* Check for unknown sysbus devices */ 1475 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1476 1477 spapr_caps_reset(spapr); 1478 1479 first_ppc_cpu = POWERPC_CPU(first_cpu); 1480 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1481 ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1482 spapr->max_compat_pvr)) { 1483 /* If using KVM with radix mode available, VCPUs can be started 1484 * without a HPT because KVM will start them in radix mode. 1485 * Set the GR bit in PATB so that we know there is no HPT. */ 1486 spapr->patb_entry = PATBE1_GR; 1487 } else { 1488 spapr_setup_hpt_and_vrma(spapr); 1489 } 1490 1491 /* if this reset wasn't generated by CAS, we should reset our 1492 * negotiated options and start from scratch */ 1493 if (!spapr->cas_reboot) { 1494 spapr_ovec_cleanup(spapr->ov5_cas); 1495 spapr->ov5_cas = spapr_ovec_new(); 1496 1497 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); 1498 } 1499 1500 qemu_devices_reset(); 1501 1502 /* DRC reset may cause a device to be unplugged. This will cause troubles 1503 * if this device is used by another device (eg, a running vhost backend 1504 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1505 * situations, we reset DRCs after all devices have been reset. 1506 */ 1507 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1508 1509 spapr_clear_pending_events(spapr); 1510 1511 /* 1512 * We place the device tree and RTAS just below either the top of the RMA, 1513 * or just below 2GB, whichever is lowere, so that it can be 1514 * processed with 32-bit real mode code if necessary 1515 */ 1516 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1517 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1518 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1519 1520 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1521 1522 spapr_load_rtas(spapr, fdt, rtas_addr); 1523 1524 rc = fdt_pack(fdt); 1525 1526 /* Should only fail if we've built a corrupted tree */ 1527 assert(rc == 0); 1528 1529 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1530 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1531 fdt_totalsize(fdt), FDT_MAX_SIZE); 1532 exit(1); 1533 } 1534 1535 /* Load the fdt */ 1536 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1537 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1538 g_free(fdt); 1539 1540 /* Set up the entry state */ 1541 first_ppc_cpu->env.gpr[3] = fdt_addr; 1542 first_ppc_cpu->env.gpr[5] = 0; 1543 first_cpu->halted = 0; 1544 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1545 1546 spapr->cas_reboot = false; 1547 } 1548 1549 static void spapr_create_nvram(sPAPRMachineState *spapr) 1550 { 1551 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1552 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1553 1554 if (dinfo) { 1555 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1556 &error_fatal); 1557 } 1558 1559 qdev_init_nofail(dev); 1560 1561 spapr->nvram = (struct sPAPRNVRAM *)dev; 1562 } 1563 1564 static void spapr_rtc_create(sPAPRMachineState *spapr) 1565 { 1566 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1567 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1568 &error_fatal); 1569 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1570 &error_fatal); 1571 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1572 "date", &error_fatal); 1573 } 1574 1575 /* Returns whether we want to use VGA or not */ 1576 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1577 { 1578 switch (vga_interface_type) { 1579 case VGA_NONE: 1580 return false; 1581 case VGA_DEVICE: 1582 return true; 1583 case VGA_STD: 1584 case VGA_VIRTIO: 1585 return pci_vga_init(pci_bus) != NULL; 1586 default: 1587 error_setg(errp, 1588 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1589 return false; 1590 } 1591 } 1592 1593 static int spapr_pre_load(void *opaque) 1594 { 1595 int rc; 1596 1597 rc = spapr_caps_pre_load(opaque); 1598 if (rc) { 1599 return rc; 1600 } 1601 1602 return 0; 1603 } 1604 1605 static int spapr_post_load(void *opaque, int version_id) 1606 { 1607 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1608 int err = 0; 1609 1610 err = spapr_caps_post_migration(spapr); 1611 if (err) { 1612 return err; 1613 } 1614 1615 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1616 CPUState *cs; 1617 CPU_FOREACH(cs) { 1618 PowerPCCPU *cpu = POWERPC_CPU(cs); 1619 icp_resend(ICP(cpu->intc)); 1620 } 1621 } 1622 1623 /* In earlier versions, there was no separate qdev for the PAPR 1624 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1625 * So when migrating from those versions, poke the incoming offset 1626 * value into the RTC device */ 1627 if (version_id < 3) { 1628 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1629 } 1630 1631 if (kvm_enabled() && spapr->patb_entry) { 1632 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1633 bool radix = !!(spapr->patb_entry & PATBE1_GR); 1634 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1635 1636 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1637 if (err) { 1638 error_report("Process table config unsupported by the host"); 1639 return -EINVAL; 1640 } 1641 } 1642 1643 return err; 1644 } 1645 1646 static int spapr_pre_save(void *opaque) 1647 { 1648 int rc; 1649 1650 rc = spapr_caps_pre_save(opaque); 1651 if (rc) { 1652 return rc; 1653 } 1654 1655 return 0; 1656 } 1657 1658 static bool version_before_3(void *opaque, int version_id) 1659 { 1660 return version_id < 3; 1661 } 1662 1663 static bool spapr_pending_events_needed(void *opaque) 1664 { 1665 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1666 return !QTAILQ_EMPTY(&spapr->pending_events); 1667 } 1668 1669 static const VMStateDescription vmstate_spapr_event_entry = { 1670 .name = "spapr_event_log_entry", 1671 .version_id = 1, 1672 .minimum_version_id = 1, 1673 .fields = (VMStateField[]) { 1674 VMSTATE_UINT32(summary, sPAPREventLogEntry), 1675 VMSTATE_UINT32(extended_length, sPAPREventLogEntry), 1676 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, 1677 NULL, extended_length), 1678 VMSTATE_END_OF_LIST() 1679 }, 1680 }; 1681 1682 static const VMStateDescription vmstate_spapr_pending_events = { 1683 .name = "spapr_pending_events", 1684 .version_id = 1, 1685 .minimum_version_id = 1, 1686 .needed = spapr_pending_events_needed, 1687 .fields = (VMStateField[]) { 1688 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, 1689 vmstate_spapr_event_entry, sPAPREventLogEntry, next), 1690 VMSTATE_END_OF_LIST() 1691 }, 1692 }; 1693 1694 static bool spapr_ov5_cas_needed(void *opaque) 1695 { 1696 sPAPRMachineState *spapr = opaque; 1697 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1698 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1699 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1700 bool cas_needed; 1701 1702 /* Prior to the introduction of sPAPROptionVector, we had two option 1703 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1704 * Both of these options encode machine topology into the device-tree 1705 * in such a way that the now-booted OS should still be able to interact 1706 * appropriately with QEMU regardless of what options were actually 1707 * negotiatied on the source side. 1708 * 1709 * As such, we can avoid migrating the CAS-negotiated options if these 1710 * are the only options available on the current machine/platform. 1711 * Since these are the only options available for pseries-2.7 and 1712 * earlier, this allows us to maintain old->new/new->old migration 1713 * compatibility. 1714 * 1715 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1716 * via default pseries-2.8 machines and explicit command-line parameters. 1717 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1718 * of the actual CAS-negotiated values to continue working properly. For 1719 * example, availability of memory unplug depends on knowing whether 1720 * OV5_HP_EVT was negotiated via CAS. 1721 * 1722 * Thus, for any cases where the set of available CAS-negotiatable 1723 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1724 * include the CAS-negotiated options in the migration stream. 1725 */ 1726 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1727 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1728 1729 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1730 * the mask itself since in the future it's possible "legacy" bits may be 1731 * removed via machine options, which could generate a false positive 1732 * that breaks migration. 1733 */ 1734 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1735 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1736 1737 spapr_ovec_cleanup(ov5_mask); 1738 spapr_ovec_cleanup(ov5_legacy); 1739 spapr_ovec_cleanup(ov5_removed); 1740 1741 return cas_needed; 1742 } 1743 1744 static const VMStateDescription vmstate_spapr_ov5_cas = { 1745 .name = "spapr_option_vector_ov5_cas", 1746 .version_id = 1, 1747 .minimum_version_id = 1, 1748 .needed = spapr_ov5_cas_needed, 1749 .fields = (VMStateField[]) { 1750 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1751 vmstate_spapr_ovec, sPAPROptionVector), 1752 VMSTATE_END_OF_LIST() 1753 }, 1754 }; 1755 1756 static bool spapr_patb_entry_needed(void *opaque) 1757 { 1758 sPAPRMachineState *spapr = opaque; 1759 1760 return !!spapr->patb_entry; 1761 } 1762 1763 static const VMStateDescription vmstate_spapr_patb_entry = { 1764 .name = "spapr_patb_entry", 1765 .version_id = 1, 1766 .minimum_version_id = 1, 1767 .needed = spapr_patb_entry_needed, 1768 .fields = (VMStateField[]) { 1769 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1770 VMSTATE_END_OF_LIST() 1771 }, 1772 }; 1773 1774 static const VMStateDescription vmstate_spapr = { 1775 .name = "spapr", 1776 .version_id = 3, 1777 .minimum_version_id = 1, 1778 .pre_load = spapr_pre_load, 1779 .post_load = spapr_post_load, 1780 .pre_save = spapr_pre_save, 1781 .fields = (VMStateField[]) { 1782 /* used to be @next_irq */ 1783 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1784 1785 /* RTC offset */ 1786 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1787 1788 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1789 VMSTATE_END_OF_LIST() 1790 }, 1791 .subsections = (const VMStateDescription*[]) { 1792 &vmstate_spapr_ov5_cas, 1793 &vmstate_spapr_patb_entry, 1794 &vmstate_spapr_pending_events, 1795 &vmstate_spapr_cap_htm, 1796 &vmstate_spapr_cap_vsx, 1797 &vmstate_spapr_cap_dfp, 1798 &vmstate_spapr_cap_cfpc, 1799 &vmstate_spapr_cap_sbbc, 1800 &vmstate_spapr_cap_ibs, 1801 NULL 1802 } 1803 }; 1804 1805 static int htab_save_setup(QEMUFile *f, void *opaque) 1806 { 1807 sPAPRMachineState *spapr = opaque; 1808 1809 /* "Iteration" header */ 1810 if (!spapr->htab_shift) { 1811 qemu_put_be32(f, -1); 1812 } else { 1813 qemu_put_be32(f, spapr->htab_shift); 1814 } 1815 1816 if (spapr->htab) { 1817 spapr->htab_save_index = 0; 1818 spapr->htab_first_pass = true; 1819 } else { 1820 if (spapr->htab_shift) { 1821 assert(kvm_enabled()); 1822 } 1823 } 1824 1825 1826 return 0; 1827 } 1828 1829 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr, 1830 int chunkstart, int n_valid, int n_invalid) 1831 { 1832 qemu_put_be32(f, chunkstart); 1833 qemu_put_be16(f, n_valid); 1834 qemu_put_be16(f, n_invalid); 1835 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1836 HASH_PTE_SIZE_64 * n_valid); 1837 } 1838 1839 static void htab_save_end_marker(QEMUFile *f) 1840 { 1841 qemu_put_be32(f, 0); 1842 qemu_put_be16(f, 0); 1843 qemu_put_be16(f, 0); 1844 } 1845 1846 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1847 int64_t max_ns) 1848 { 1849 bool has_timeout = max_ns != -1; 1850 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1851 int index = spapr->htab_save_index; 1852 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1853 1854 assert(spapr->htab_first_pass); 1855 1856 do { 1857 int chunkstart; 1858 1859 /* Consume invalid HPTEs */ 1860 while ((index < htabslots) 1861 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1862 CLEAN_HPTE(HPTE(spapr->htab, index)); 1863 index++; 1864 } 1865 1866 /* Consume valid HPTEs */ 1867 chunkstart = index; 1868 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1869 && HPTE_VALID(HPTE(spapr->htab, index))) { 1870 CLEAN_HPTE(HPTE(spapr->htab, index)); 1871 index++; 1872 } 1873 1874 if (index > chunkstart) { 1875 int n_valid = index - chunkstart; 1876 1877 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 1878 1879 if (has_timeout && 1880 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1881 break; 1882 } 1883 } 1884 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1885 1886 if (index >= htabslots) { 1887 assert(index == htabslots); 1888 index = 0; 1889 spapr->htab_first_pass = false; 1890 } 1891 spapr->htab_save_index = index; 1892 } 1893 1894 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1895 int64_t max_ns) 1896 { 1897 bool final = max_ns < 0; 1898 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1899 int examined = 0, sent = 0; 1900 int index = spapr->htab_save_index; 1901 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1902 1903 assert(!spapr->htab_first_pass); 1904 1905 do { 1906 int chunkstart, invalidstart; 1907 1908 /* Consume non-dirty HPTEs */ 1909 while ((index < htabslots) 1910 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1911 index++; 1912 examined++; 1913 } 1914 1915 chunkstart = index; 1916 /* Consume valid dirty HPTEs */ 1917 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1918 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1919 && HPTE_VALID(HPTE(spapr->htab, index))) { 1920 CLEAN_HPTE(HPTE(spapr->htab, index)); 1921 index++; 1922 examined++; 1923 } 1924 1925 invalidstart = index; 1926 /* Consume invalid dirty HPTEs */ 1927 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1928 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1929 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1930 CLEAN_HPTE(HPTE(spapr->htab, index)); 1931 index++; 1932 examined++; 1933 } 1934 1935 if (index > chunkstart) { 1936 int n_valid = invalidstart - chunkstart; 1937 int n_invalid = index - invalidstart; 1938 1939 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 1940 sent += index - chunkstart; 1941 1942 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1943 break; 1944 } 1945 } 1946 1947 if (examined >= htabslots) { 1948 break; 1949 } 1950 1951 if (index >= htabslots) { 1952 assert(index == htabslots); 1953 index = 0; 1954 } 1955 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1956 1957 if (index >= htabslots) { 1958 assert(index == htabslots); 1959 index = 0; 1960 } 1961 1962 spapr->htab_save_index = index; 1963 1964 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1965 } 1966 1967 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1968 #define MAX_KVM_BUF_SIZE 2048 1969 1970 static int htab_save_iterate(QEMUFile *f, void *opaque) 1971 { 1972 sPAPRMachineState *spapr = opaque; 1973 int fd; 1974 int rc = 0; 1975 1976 /* Iteration header */ 1977 if (!spapr->htab_shift) { 1978 qemu_put_be32(f, -1); 1979 return 1; 1980 } else { 1981 qemu_put_be32(f, 0); 1982 } 1983 1984 if (!spapr->htab) { 1985 assert(kvm_enabled()); 1986 1987 fd = get_htab_fd(spapr); 1988 if (fd < 0) { 1989 return fd; 1990 } 1991 1992 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1993 if (rc < 0) { 1994 return rc; 1995 } 1996 } else if (spapr->htab_first_pass) { 1997 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1998 } else { 1999 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2000 } 2001 2002 htab_save_end_marker(f); 2003 2004 return rc; 2005 } 2006 2007 static int htab_save_complete(QEMUFile *f, void *opaque) 2008 { 2009 sPAPRMachineState *spapr = opaque; 2010 int fd; 2011 2012 /* Iteration header */ 2013 if (!spapr->htab_shift) { 2014 qemu_put_be32(f, -1); 2015 return 0; 2016 } else { 2017 qemu_put_be32(f, 0); 2018 } 2019 2020 if (!spapr->htab) { 2021 int rc; 2022 2023 assert(kvm_enabled()); 2024 2025 fd = get_htab_fd(spapr); 2026 if (fd < 0) { 2027 return fd; 2028 } 2029 2030 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2031 if (rc < 0) { 2032 return rc; 2033 } 2034 } else { 2035 if (spapr->htab_first_pass) { 2036 htab_save_first_pass(f, spapr, -1); 2037 } 2038 htab_save_later_pass(f, spapr, -1); 2039 } 2040 2041 /* End marker */ 2042 htab_save_end_marker(f); 2043 2044 return 0; 2045 } 2046 2047 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2048 { 2049 sPAPRMachineState *spapr = opaque; 2050 uint32_t section_hdr; 2051 int fd = -1; 2052 Error *local_err = NULL; 2053 2054 if (version_id < 1 || version_id > 1) { 2055 error_report("htab_load() bad version"); 2056 return -EINVAL; 2057 } 2058 2059 section_hdr = qemu_get_be32(f); 2060 2061 if (section_hdr == -1) { 2062 spapr_free_hpt(spapr); 2063 return 0; 2064 } 2065 2066 if (section_hdr) { 2067 /* First section gives the htab size */ 2068 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2069 if (local_err) { 2070 error_report_err(local_err); 2071 return -EINVAL; 2072 } 2073 return 0; 2074 } 2075 2076 if (!spapr->htab) { 2077 assert(kvm_enabled()); 2078 2079 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2080 if (fd < 0) { 2081 error_report_err(local_err); 2082 return fd; 2083 } 2084 } 2085 2086 while (true) { 2087 uint32_t index; 2088 uint16_t n_valid, n_invalid; 2089 2090 index = qemu_get_be32(f); 2091 n_valid = qemu_get_be16(f); 2092 n_invalid = qemu_get_be16(f); 2093 2094 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2095 /* End of Stream */ 2096 break; 2097 } 2098 2099 if ((index + n_valid + n_invalid) > 2100 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2101 /* Bad index in stream */ 2102 error_report( 2103 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2104 index, n_valid, n_invalid, spapr->htab_shift); 2105 return -EINVAL; 2106 } 2107 2108 if (spapr->htab) { 2109 if (n_valid) { 2110 qemu_get_buffer(f, HPTE(spapr->htab, index), 2111 HASH_PTE_SIZE_64 * n_valid); 2112 } 2113 if (n_invalid) { 2114 memset(HPTE(spapr->htab, index + n_valid), 0, 2115 HASH_PTE_SIZE_64 * n_invalid); 2116 } 2117 } else { 2118 int rc; 2119 2120 assert(fd >= 0); 2121 2122 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2123 if (rc < 0) { 2124 return rc; 2125 } 2126 } 2127 } 2128 2129 if (!spapr->htab) { 2130 assert(fd >= 0); 2131 close(fd); 2132 } 2133 2134 return 0; 2135 } 2136 2137 static void htab_save_cleanup(void *opaque) 2138 { 2139 sPAPRMachineState *spapr = opaque; 2140 2141 close_htab_fd(spapr); 2142 } 2143 2144 static SaveVMHandlers savevm_htab_handlers = { 2145 .save_setup = htab_save_setup, 2146 .save_live_iterate = htab_save_iterate, 2147 .save_live_complete_precopy = htab_save_complete, 2148 .save_cleanup = htab_save_cleanup, 2149 .load_state = htab_load, 2150 }; 2151 2152 static void spapr_boot_set(void *opaque, const char *boot_device, 2153 Error **errp) 2154 { 2155 MachineState *machine = MACHINE(opaque); 2156 machine->boot_order = g_strdup(boot_device); 2157 } 2158 2159 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 2160 { 2161 MachineState *machine = MACHINE(spapr); 2162 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2163 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2164 int i; 2165 2166 for (i = 0; i < nr_lmbs; i++) { 2167 uint64_t addr; 2168 2169 addr = i * lmb_size + spapr->hotplug_memory.base; 2170 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2171 addr / lmb_size); 2172 } 2173 } 2174 2175 /* 2176 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2177 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2178 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2179 */ 2180 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2181 { 2182 int i; 2183 2184 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2185 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2186 " is not aligned to %llu MiB", 2187 machine->ram_size, 2188 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2189 return; 2190 } 2191 2192 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2193 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2194 " is not aligned to %llu MiB", 2195 machine->ram_size, 2196 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2197 return; 2198 } 2199 2200 for (i = 0; i < nb_numa_nodes; i++) { 2201 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2202 error_setg(errp, 2203 "Node %d memory size 0x%" PRIx64 2204 " is not aligned to %llu MiB", 2205 i, numa_info[i].node_mem, 2206 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2207 return; 2208 } 2209 } 2210 } 2211 2212 /* find cpu slot in machine->possible_cpus by core_id */ 2213 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2214 { 2215 int index = id / smp_threads; 2216 2217 if (index >= ms->possible_cpus->len) { 2218 return NULL; 2219 } 2220 if (idx) { 2221 *idx = index; 2222 } 2223 return &ms->possible_cpus->cpus[index]; 2224 } 2225 2226 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) 2227 { 2228 Error *local_err = NULL; 2229 bool vsmt_user = !!spapr->vsmt; 2230 int kvm_smt = kvmppc_smt_threads(); 2231 int ret; 2232 2233 if (!kvm_enabled() && (smp_threads > 1)) { 2234 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2235 "on a pseries machine"); 2236 goto out; 2237 } 2238 if (!is_power_of_2(smp_threads)) { 2239 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2240 "machine because it must be a power of 2", smp_threads); 2241 goto out; 2242 } 2243 2244 /* Detemine the VSMT mode to use: */ 2245 if (vsmt_user) { 2246 if (spapr->vsmt < smp_threads) { 2247 error_setg(&local_err, "Cannot support VSMT mode %d" 2248 " because it must be >= threads/core (%d)", 2249 spapr->vsmt, smp_threads); 2250 goto out; 2251 } 2252 /* In this case, spapr->vsmt has been set by the command line */ 2253 } else { 2254 /* 2255 * Default VSMT value is tricky, because we need it to be as 2256 * consistent as possible (for migration), but this requires 2257 * changing it for at least some existing cases. We pick 8 as 2258 * the value that we'd get with KVM on POWER8, the 2259 * overwhelmingly common case in production systems. 2260 */ 2261 spapr->vsmt = MAX(8, smp_threads); 2262 } 2263 2264 /* KVM: If necessary, set the SMT mode: */ 2265 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2266 ret = kvmppc_set_smt_threads(spapr->vsmt); 2267 if (ret) { 2268 /* Looks like KVM isn't able to change VSMT mode */ 2269 error_setg(&local_err, 2270 "Failed to set KVM's VSMT mode to %d (errno %d)", 2271 spapr->vsmt, ret); 2272 /* We can live with that if the default one is big enough 2273 * for the number of threads, and a submultiple of the one 2274 * we want. In this case we'll waste some vcpu ids, but 2275 * behaviour will be correct */ 2276 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2277 warn_report_err(local_err); 2278 local_err = NULL; 2279 goto out; 2280 } else { 2281 if (!vsmt_user) { 2282 error_append_hint(&local_err, 2283 "On PPC, a VM with %d threads/core" 2284 " on a host with %d threads/core" 2285 " requires the use of VSMT mode %d.\n", 2286 smp_threads, kvm_smt, spapr->vsmt); 2287 } 2288 kvmppc_hint_smt_possible(&local_err); 2289 goto out; 2290 } 2291 } 2292 } 2293 /* else TCG: nothing to do currently */ 2294 out: 2295 error_propagate(errp, local_err); 2296 } 2297 2298 static void spapr_init_cpus(sPAPRMachineState *spapr) 2299 { 2300 MachineState *machine = MACHINE(spapr); 2301 MachineClass *mc = MACHINE_GET_CLASS(machine); 2302 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2303 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2304 const CPUArchIdList *possible_cpus; 2305 int boot_cores_nr = smp_cpus / smp_threads; 2306 int i; 2307 2308 possible_cpus = mc->possible_cpu_arch_ids(machine); 2309 if (mc->has_hotpluggable_cpus) { 2310 if (smp_cpus % smp_threads) { 2311 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2312 smp_cpus, smp_threads); 2313 exit(1); 2314 } 2315 if (max_cpus % smp_threads) { 2316 error_report("max_cpus (%u) must be multiple of threads (%u)", 2317 max_cpus, smp_threads); 2318 exit(1); 2319 } 2320 } else { 2321 if (max_cpus != smp_cpus) { 2322 error_report("This machine version does not support CPU hotplug"); 2323 exit(1); 2324 } 2325 boot_cores_nr = possible_cpus->len; 2326 } 2327 2328 /* VSMT must be set in order to be able to compute VCPU ids, ie to 2329 * call xics_max_server_number() or spapr_vcpu_id(). 2330 */ 2331 spapr_set_vsmt_mode(spapr, &error_fatal); 2332 2333 if (smc->pre_2_10_has_unused_icps) { 2334 int i; 2335 2336 for (i = 0; i < xics_max_server_number(spapr); i++) { 2337 /* Dummy entries get deregistered when real ICPState objects 2338 * are registered during CPU core hotplug. 2339 */ 2340 pre_2_10_vmstate_register_dummy_icp(i); 2341 } 2342 } 2343 2344 for (i = 0; i < possible_cpus->len; i++) { 2345 int core_id = i * smp_threads; 2346 2347 if (mc->has_hotpluggable_cpus) { 2348 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2349 spapr_vcpu_id(spapr, core_id)); 2350 } 2351 2352 if (i < boot_cores_nr) { 2353 Object *core = object_new(type); 2354 int nr_threads = smp_threads; 2355 2356 /* Handle the partially filled core for older machine types */ 2357 if ((i + 1) * smp_threads >= smp_cpus) { 2358 nr_threads = smp_cpus - i * smp_threads; 2359 } 2360 2361 object_property_set_int(core, nr_threads, "nr-threads", 2362 &error_fatal); 2363 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2364 &error_fatal); 2365 object_property_set_bool(core, true, "realized", &error_fatal); 2366 } 2367 } 2368 } 2369 2370 /* pSeries LPAR / sPAPR hardware init */ 2371 static void spapr_machine_init(MachineState *machine) 2372 { 2373 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2374 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2375 const char *kernel_filename = machine->kernel_filename; 2376 const char *initrd_filename = machine->initrd_filename; 2377 PCIHostState *phb; 2378 int i; 2379 MemoryRegion *sysmem = get_system_memory(); 2380 MemoryRegion *ram = g_new(MemoryRegion, 1); 2381 MemoryRegion *rma_region; 2382 void *rma = NULL; 2383 hwaddr rma_alloc_size; 2384 hwaddr node0_size = spapr_node0_size(machine); 2385 long load_limit, fw_size; 2386 char *filename; 2387 Error *resize_hpt_err = NULL; 2388 2389 msi_nonbroken = true; 2390 2391 QLIST_INIT(&spapr->phbs); 2392 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2393 2394 /* Check HPT resizing availability */ 2395 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2396 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2397 /* 2398 * If the user explicitly requested a mode we should either 2399 * supply it, or fail completely (which we do below). But if 2400 * it's not set explicitly, we reset our mode to something 2401 * that works 2402 */ 2403 if (resize_hpt_err) { 2404 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2405 error_free(resize_hpt_err); 2406 resize_hpt_err = NULL; 2407 } else { 2408 spapr->resize_hpt = smc->resize_hpt_default; 2409 } 2410 } 2411 2412 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2413 2414 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2415 /* 2416 * User requested HPT resize, but this host can't supply it. Bail out 2417 */ 2418 error_report_err(resize_hpt_err); 2419 exit(1); 2420 } 2421 2422 /* Allocate RMA if necessary */ 2423 rma_alloc_size = kvmppc_alloc_rma(&rma); 2424 2425 if (rma_alloc_size == -1) { 2426 error_report("Unable to create RMA"); 2427 exit(1); 2428 } 2429 2430 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 2431 spapr->rma_size = rma_alloc_size; 2432 } else { 2433 spapr->rma_size = node0_size; 2434 2435 /* With KVM, we don't actually know whether KVM supports an 2436 * unbounded RMA (PR KVM) or is limited by the hash table size 2437 * (HV KVM using VRMA), so we always assume the latter 2438 * 2439 * In that case, we also limit the initial allocations for RTAS 2440 * etc... to 256M since we have no way to know what the VRMA size 2441 * is going to be as it depends on the size of the hash table 2442 * isn't determined yet. 2443 */ 2444 if (kvm_enabled()) { 2445 spapr->vrma_adjust = 1; 2446 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2447 } 2448 2449 /* Actually we don't support unbounded RMA anymore since we 2450 * added proper emulation of HV mode. The max we can get is 2451 * 16G which also happens to be what we configure for PAPR 2452 * mode so make sure we don't do anything bigger than that 2453 */ 2454 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2455 } 2456 2457 if (spapr->rma_size > node0_size) { 2458 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2459 spapr->rma_size); 2460 exit(1); 2461 } 2462 2463 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2464 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2465 2466 /* Set up Interrupt Controller before we create the VCPUs */ 2467 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); 2468 2469 /* Set up containers for ibm,client-architecture-support negotiated options 2470 */ 2471 spapr->ov5 = spapr_ovec_new(); 2472 spapr->ov5_cas = spapr_ovec_new(); 2473 2474 if (smc->dr_lmb_enabled) { 2475 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2476 spapr_validate_node_memory(machine, &error_fatal); 2477 } 2478 2479 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2480 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) { 2481 /* KVM and TCG always allow GTSE with radix... */ 2482 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2483 } 2484 /* ... but not with hash (currently). */ 2485 2486 /* advertise support for dedicated HP event source to guests */ 2487 if (spapr->use_hotplug_event_source) { 2488 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2489 } 2490 2491 /* advertise support for HPT resizing */ 2492 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2493 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2494 } 2495 2496 /* init CPUs */ 2497 spapr_init_cpus(spapr); 2498 2499 if (kvm_enabled()) { 2500 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2501 kvmppc_enable_logical_ci_hcalls(); 2502 kvmppc_enable_set_mode_hcall(); 2503 2504 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2505 kvmppc_enable_clear_ref_mod_hcalls(); 2506 } 2507 2508 /* allocate RAM */ 2509 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2510 machine->ram_size); 2511 memory_region_add_subregion(sysmem, 0, ram); 2512 2513 if (rma_alloc_size && rma) { 2514 rma_region = g_new(MemoryRegion, 1); 2515 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 2516 rma_alloc_size, rma); 2517 vmstate_register_ram_global(rma_region); 2518 memory_region_add_subregion(sysmem, 0, rma_region); 2519 } 2520 2521 /* initialize hotplug memory address space */ 2522 if (machine->ram_size < machine->maxram_size) { 2523 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2524 /* 2525 * Limit the number of hotpluggable memory slots to half the number 2526 * slots that KVM supports, leaving the other half for PCI and other 2527 * devices. However ensure that number of slots doesn't drop below 32. 2528 */ 2529 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2530 SPAPR_MAX_RAM_SLOTS; 2531 2532 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2533 max_memslots = SPAPR_MAX_RAM_SLOTS; 2534 } 2535 if (machine->ram_slots > max_memslots) { 2536 error_report("Specified number of memory slots %" 2537 PRIu64" exceeds max supported %d", 2538 machine->ram_slots, max_memslots); 2539 exit(1); 2540 } 2541 2542 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2543 SPAPR_HOTPLUG_MEM_ALIGN); 2544 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2545 "hotplug-memory", hotplug_mem_size); 2546 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2547 &spapr->hotplug_memory.mr); 2548 } 2549 2550 if (smc->dr_lmb_enabled) { 2551 spapr_create_lmb_dr_connectors(spapr); 2552 } 2553 2554 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2555 if (!filename) { 2556 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2557 exit(1); 2558 } 2559 spapr->rtas_size = get_image_size(filename); 2560 if (spapr->rtas_size < 0) { 2561 error_report("Could not get size of LPAR rtas '%s'", filename); 2562 exit(1); 2563 } 2564 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2565 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2566 error_report("Could not load LPAR rtas '%s'", filename); 2567 exit(1); 2568 } 2569 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2570 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2571 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2572 exit(1); 2573 } 2574 g_free(filename); 2575 2576 /* Set up RTAS event infrastructure */ 2577 spapr_events_init(spapr); 2578 2579 /* Set up the RTC RTAS interfaces */ 2580 spapr_rtc_create(spapr); 2581 2582 /* Set up VIO bus */ 2583 spapr->vio_bus = spapr_vio_bus_init(); 2584 2585 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 2586 if (serial_hds[i]) { 2587 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 2588 } 2589 } 2590 2591 /* We always have at least the nvram device on VIO */ 2592 spapr_create_nvram(spapr); 2593 2594 /* Set up PCI */ 2595 spapr_pci_rtas_init(); 2596 2597 phb = spapr_create_phb(spapr, 0); 2598 2599 for (i = 0; i < nb_nics; i++) { 2600 NICInfo *nd = &nd_table[i]; 2601 2602 if (!nd->model) { 2603 nd->model = g_strdup("ibmveth"); 2604 } 2605 2606 if (strcmp(nd->model, "ibmveth") == 0) { 2607 spapr_vlan_create(spapr->vio_bus, nd); 2608 } else { 2609 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2610 } 2611 } 2612 2613 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2614 spapr_vscsi_create(spapr->vio_bus); 2615 } 2616 2617 /* Graphics */ 2618 if (spapr_vga_init(phb->bus, &error_fatal)) { 2619 spapr->has_graphics = true; 2620 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2621 } 2622 2623 if (machine->usb) { 2624 if (smc->use_ohci_by_default) { 2625 pci_create_simple(phb->bus, -1, "pci-ohci"); 2626 } else { 2627 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2628 } 2629 2630 if (spapr->has_graphics) { 2631 USBBus *usb_bus = usb_bus_find(-1); 2632 2633 usb_create_simple(usb_bus, "usb-kbd"); 2634 usb_create_simple(usb_bus, "usb-mouse"); 2635 } 2636 } 2637 2638 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2639 error_report( 2640 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2641 MIN_RMA_SLOF); 2642 exit(1); 2643 } 2644 2645 if (kernel_filename) { 2646 uint64_t lowaddr = 0; 2647 2648 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2649 NULL, NULL, &lowaddr, NULL, 1, 2650 PPC_ELF_MACHINE, 0, 0); 2651 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2652 spapr->kernel_size = load_elf(kernel_filename, 2653 translate_kernel_address, NULL, NULL, 2654 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2655 0, 0); 2656 spapr->kernel_le = spapr->kernel_size > 0; 2657 } 2658 if (spapr->kernel_size < 0) { 2659 error_report("error loading %s: %s", kernel_filename, 2660 load_elf_strerror(spapr->kernel_size)); 2661 exit(1); 2662 } 2663 2664 /* load initrd */ 2665 if (initrd_filename) { 2666 /* Try to locate the initrd in the gap between the kernel 2667 * and the firmware. Add a bit of space just in case 2668 */ 2669 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2670 + 0x1ffff) & ~0xffff; 2671 spapr->initrd_size = load_image_targphys(initrd_filename, 2672 spapr->initrd_base, 2673 load_limit 2674 - spapr->initrd_base); 2675 if (spapr->initrd_size < 0) { 2676 error_report("could not load initial ram disk '%s'", 2677 initrd_filename); 2678 exit(1); 2679 } 2680 } 2681 } 2682 2683 if (bios_name == NULL) { 2684 bios_name = FW_FILE_NAME; 2685 } 2686 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2687 if (!filename) { 2688 error_report("Could not find LPAR firmware '%s'", bios_name); 2689 exit(1); 2690 } 2691 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2692 if (fw_size <= 0) { 2693 error_report("Could not load LPAR firmware '%s'", filename); 2694 exit(1); 2695 } 2696 g_free(filename); 2697 2698 /* FIXME: Should register things through the MachineState's qdev 2699 * interface, this is a legacy from the sPAPREnvironment structure 2700 * which predated MachineState but had a similar function */ 2701 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2702 register_savevm_live(NULL, "spapr/htab", -1, 1, 2703 &savevm_htab_handlers, spapr); 2704 2705 qemu_register_boot_set(spapr_boot_set, spapr); 2706 2707 if (kvm_enabled()) { 2708 /* to stop and start vmclock */ 2709 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2710 &spapr->tb); 2711 2712 kvmppc_spapr_enable_inkernel_multitce(); 2713 } 2714 } 2715 2716 static int spapr_kvm_type(const char *vm_type) 2717 { 2718 if (!vm_type) { 2719 return 0; 2720 } 2721 2722 if (!strcmp(vm_type, "HV")) { 2723 return 1; 2724 } 2725 2726 if (!strcmp(vm_type, "PR")) { 2727 return 2; 2728 } 2729 2730 error_report("Unknown kvm-type specified '%s'", vm_type); 2731 exit(1); 2732 } 2733 2734 /* 2735 * Implementation of an interface to adjust firmware path 2736 * for the bootindex property handling. 2737 */ 2738 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2739 DeviceState *dev) 2740 { 2741 #define CAST(type, obj, name) \ 2742 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2743 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2744 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2745 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 2746 2747 if (d) { 2748 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2749 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2750 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2751 2752 if (spapr) { 2753 /* 2754 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2755 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2756 * in the top 16 bits of the 64-bit LUN 2757 */ 2758 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2759 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2760 (uint64_t)id << 48); 2761 } else if (virtio) { 2762 /* 2763 * We use SRP luns of the form 01000000 | (target << 8) | lun 2764 * in the top 32 bits of the 64-bit LUN 2765 * Note: the quote above is from SLOF and it is wrong, 2766 * the actual binding is: 2767 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2768 */ 2769 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2770 if (d->lun >= 256) { 2771 /* Use the LUN "flat space addressing method" */ 2772 id |= 0x4000; 2773 } 2774 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2775 (uint64_t)id << 32); 2776 } else if (usb) { 2777 /* 2778 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2779 * in the top 32 bits of the 64-bit LUN 2780 */ 2781 unsigned usb_port = atoi(usb->port->path); 2782 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2783 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2784 (uint64_t)id << 32); 2785 } 2786 } 2787 2788 /* 2789 * SLOF probes the USB devices, and if it recognizes that the device is a 2790 * storage device, it changes its name to "storage" instead of "usb-host", 2791 * and additionally adds a child node for the SCSI LUN, so the correct 2792 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2793 */ 2794 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2795 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2796 if (usb_host_dev_is_scsi_storage(usbdev)) { 2797 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2798 } 2799 } 2800 2801 if (phb) { 2802 /* Replace "pci" with "pci@800000020000000" */ 2803 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2804 } 2805 2806 if (vsc) { 2807 /* Same logic as virtio above */ 2808 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 2809 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 2810 } 2811 2812 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 2813 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 2814 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 2815 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 2816 } 2817 2818 return NULL; 2819 } 2820 2821 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2822 { 2823 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2824 2825 return g_strdup(spapr->kvm_type); 2826 } 2827 2828 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2829 { 2830 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2831 2832 g_free(spapr->kvm_type); 2833 spapr->kvm_type = g_strdup(value); 2834 } 2835 2836 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2837 { 2838 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2839 2840 return spapr->use_hotplug_event_source; 2841 } 2842 2843 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2844 Error **errp) 2845 { 2846 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2847 2848 spapr->use_hotplug_event_source = value; 2849 } 2850 2851 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 2852 { 2853 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2854 2855 switch (spapr->resize_hpt) { 2856 case SPAPR_RESIZE_HPT_DEFAULT: 2857 return g_strdup("default"); 2858 case SPAPR_RESIZE_HPT_DISABLED: 2859 return g_strdup("disabled"); 2860 case SPAPR_RESIZE_HPT_ENABLED: 2861 return g_strdup("enabled"); 2862 case SPAPR_RESIZE_HPT_REQUIRED: 2863 return g_strdup("required"); 2864 } 2865 g_assert_not_reached(); 2866 } 2867 2868 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 2869 { 2870 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2871 2872 if (strcmp(value, "default") == 0) { 2873 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 2874 } else if (strcmp(value, "disabled") == 0) { 2875 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2876 } else if (strcmp(value, "enabled") == 0) { 2877 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 2878 } else if (strcmp(value, "required") == 0) { 2879 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 2880 } else { 2881 error_setg(errp, "Bad value for \"resize-hpt\" property"); 2882 } 2883 } 2884 2885 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 2886 void *opaque, Error **errp) 2887 { 2888 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 2889 } 2890 2891 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 2892 void *opaque, Error **errp) 2893 { 2894 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 2895 } 2896 2897 static void spapr_instance_init(Object *obj) 2898 { 2899 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2900 2901 spapr->htab_fd = -1; 2902 spapr->use_hotplug_event_source = true; 2903 object_property_add_str(obj, "kvm-type", 2904 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2905 object_property_set_description(obj, "kvm-type", 2906 "Specifies the KVM virtualization mode (HV, PR)", 2907 NULL); 2908 object_property_add_bool(obj, "modern-hotplug-events", 2909 spapr_get_modern_hotplug_events, 2910 spapr_set_modern_hotplug_events, 2911 NULL); 2912 object_property_set_description(obj, "modern-hotplug-events", 2913 "Use dedicated hotplug event mechanism in" 2914 " place of standard EPOW events when possible" 2915 " (required for memory hot-unplug support)", 2916 NULL); 2917 2918 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 2919 "Maximum permitted CPU compatibility mode", 2920 &error_fatal); 2921 2922 object_property_add_str(obj, "resize-hpt", 2923 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 2924 object_property_set_description(obj, "resize-hpt", 2925 "Resizing of the Hash Page Table (enabled, disabled, required)", 2926 NULL); 2927 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 2928 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 2929 object_property_set_description(obj, "vsmt", 2930 "Virtual SMT: KVM behaves as if this were" 2931 " the host's SMT mode", &error_abort); 2932 } 2933 2934 static void spapr_machine_finalizefn(Object *obj) 2935 { 2936 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2937 2938 g_free(spapr->kvm_type); 2939 } 2940 2941 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 2942 { 2943 cpu_synchronize_state(cs); 2944 ppc_cpu_do_system_reset(cs); 2945 } 2946 2947 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2948 { 2949 CPUState *cs; 2950 2951 CPU_FOREACH(cs) { 2952 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 2953 } 2954 } 2955 2956 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2957 uint32_t node, bool dedicated_hp_event_source, 2958 Error **errp) 2959 { 2960 sPAPRDRConnector *drc; 2961 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2962 int i, fdt_offset, fdt_size; 2963 void *fdt; 2964 uint64_t addr = addr_start; 2965 bool hotplugged = spapr_drc_hotplugged(dev); 2966 Error *local_err = NULL; 2967 2968 for (i = 0; i < nr_lmbs; i++) { 2969 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2970 addr / SPAPR_MEMORY_BLOCK_SIZE); 2971 g_assert(drc); 2972 2973 fdt = create_device_tree(&fdt_size); 2974 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2975 SPAPR_MEMORY_BLOCK_SIZE); 2976 2977 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 2978 if (local_err) { 2979 while (addr > addr_start) { 2980 addr -= SPAPR_MEMORY_BLOCK_SIZE; 2981 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2982 addr / SPAPR_MEMORY_BLOCK_SIZE); 2983 spapr_drc_detach(drc); 2984 } 2985 g_free(fdt); 2986 error_propagate(errp, local_err); 2987 return; 2988 } 2989 if (!hotplugged) { 2990 spapr_drc_reset(drc); 2991 } 2992 addr += SPAPR_MEMORY_BLOCK_SIZE; 2993 } 2994 /* send hotplug notification to the 2995 * guest only in case of hotplugged memory 2996 */ 2997 if (hotplugged) { 2998 if (dedicated_hp_event_source) { 2999 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3000 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3001 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3002 nr_lmbs, 3003 spapr_drc_index(drc)); 3004 } else { 3005 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3006 nr_lmbs); 3007 } 3008 } 3009 } 3010 3011 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3012 uint32_t node, Error **errp) 3013 { 3014 Error *local_err = NULL; 3015 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3016 PCDIMMDevice *dimm = PC_DIMM(dev); 3017 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3018 MemoryRegion *mr; 3019 uint64_t align, size, addr; 3020 3021 mr = ddc->get_memory_region(dimm, &local_err); 3022 if (local_err) { 3023 goto out; 3024 } 3025 align = memory_region_get_alignment(mr); 3026 size = memory_region_size(mr); 3027 3028 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 3029 if (local_err) { 3030 goto out; 3031 } 3032 3033 addr = object_property_get_uint(OBJECT(dimm), 3034 PC_DIMM_ADDR_PROP, &local_err); 3035 if (local_err) { 3036 goto out_unplug; 3037 } 3038 3039 spapr_add_lmbs(dev, addr, size, node, 3040 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3041 &local_err); 3042 if (local_err) { 3043 goto out_unplug; 3044 } 3045 3046 return; 3047 3048 out_unplug: 3049 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 3050 out: 3051 error_propagate(errp, local_err); 3052 } 3053 3054 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3055 Error **errp) 3056 { 3057 PCDIMMDevice *dimm = PC_DIMM(dev); 3058 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3059 MemoryRegion *mr; 3060 uint64_t size; 3061 char *mem_dev; 3062 3063 mr = ddc->get_memory_region(dimm, errp); 3064 if (!mr) { 3065 return; 3066 } 3067 size = memory_region_size(mr); 3068 3069 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3070 error_setg(errp, "Hotplugged memory size must be a multiple of " 3071 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 3072 return; 3073 } 3074 3075 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 3076 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 3077 error_setg(errp, "Memory backend has bad page size. " 3078 "Use 'memory-backend-file' with correct mem-path."); 3079 goto out; 3080 } 3081 3082 out: 3083 g_free(mem_dev); 3084 } 3085 3086 struct sPAPRDIMMState { 3087 PCDIMMDevice *dimm; 3088 uint32_t nr_lmbs; 3089 QTAILQ_ENTRY(sPAPRDIMMState) next; 3090 }; 3091 3092 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 3093 PCDIMMDevice *dimm) 3094 { 3095 sPAPRDIMMState *dimm_state = NULL; 3096 3097 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3098 if (dimm_state->dimm == dimm) { 3099 break; 3100 } 3101 } 3102 return dimm_state; 3103 } 3104 3105 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 3106 uint32_t nr_lmbs, 3107 PCDIMMDevice *dimm) 3108 { 3109 sPAPRDIMMState *ds = NULL; 3110 3111 /* 3112 * If this request is for a DIMM whose removal had failed earlier 3113 * (due to guest's refusal to remove the LMBs), we would have this 3114 * dimm already in the pending_dimm_unplugs list. In that 3115 * case don't add again. 3116 */ 3117 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3118 if (!ds) { 3119 ds = g_malloc0(sizeof(sPAPRDIMMState)); 3120 ds->nr_lmbs = nr_lmbs; 3121 ds->dimm = dimm; 3122 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3123 } 3124 return ds; 3125 } 3126 3127 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 3128 sPAPRDIMMState *dimm_state) 3129 { 3130 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3131 g_free(dimm_state); 3132 } 3133 3134 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 3135 PCDIMMDevice *dimm) 3136 { 3137 sPAPRDRConnector *drc; 3138 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3139 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3140 uint64_t size = memory_region_size(mr); 3141 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3142 uint32_t avail_lmbs = 0; 3143 uint64_t addr_start, addr; 3144 int i; 3145 3146 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3147 &error_abort); 3148 3149 addr = addr_start; 3150 for (i = 0; i < nr_lmbs; i++) { 3151 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3152 addr / SPAPR_MEMORY_BLOCK_SIZE); 3153 g_assert(drc); 3154 if (drc->dev) { 3155 avail_lmbs++; 3156 } 3157 addr += SPAPR_MEMORY_BLOCK_SIZE; 3158 } 3159 3160 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3161 } 3162 3163 /* Callback to be called during DRC release. */ 3164 void spapr_lmb_release(DeviceState *dev) 3165 { 3166 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_hotplug_handler(dev)); 3167 PCDIMMDevice *dimm = PC_DIMM(dev); 3168 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3169 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3170 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3171 3172 /* This information will get lost if a migration occurs 3173 * during the unplug process. In this case recover it. */ 3174 if (ds == NULL) { 3175 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3176 g_assert(ds); 3177 /* The DRC being examined by the caller at least must be counted */ 3178 g_assert(ds->nr_lmbs); 3179 } 3180 3181 if (--ds->nr_lmbs) { 3182 return; 3183 } 3184 3185 /* 3186 * Now that all the LMBs have been removed by the guest, call the 3187 * pc-dimm unplug handler to cleanup up the pc-dimm device. 3188 */ 3189 pc_dimm_memory_unplug(dev, &spapr->hotplug_memory, mr); 3190 object_unparent(OBJECT(dev)); 3191 spapr_pending_dimm_unplugs_remove(spapr, ds); 3192 } 3193 3194 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3195 DeviceState *dev, Error **errp) 3196 { 3197 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3198 Error *local_err = NULL; 3199 PCDIMMDevice *dimm = PC_DIMM(dev); 3200 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3201 MemoryRegion *mr; 3202 uint32_t nr_lmbs; 3203 uint64_t size, addr_start, addr; 3204 int i; 3205 sPAPRDRConnector *drc; 3206 3207 mr = ddc->get_memory_region(dimm, &local_err); 3208 if (local_err) { 3209 goto out; 3210 } 3211 size = memory_region_size(mr); 3212 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3213 3214 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3215 &local_err); 3216 if (local_err) { 3217 goto out; 3218 } 3219 3220 /* 3221 * An existing pending dimm state for this DIMM means that there is an 3222 * unplug operation in progress, waiting for the spapr_lmb_release 3223 * callback to complete the job (BQL can't cover that far). In this case, 3224 * bail out to avoid detaching DRCs that were already released. 3225 */ 3226 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3227 error_setg(&local_err, 3228 "Memory unplug already in progress for device %s", 3229 dev->id); 3230 goto out; 3231 } 3232 3233 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3234 3235 addr = addr_start; 3236 for (i = 0; i < nr_lmbs; i++) { 3237 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3238 addr / SPAPR_MEMORY_BLOCK_SIZE); 3239 g_assert(drc); 3240 3241 spapr_drc_detach(drc); 3242 addr += SPAPR_MEMORY_BLOCK_SIZE; 3243 } 3244 3245 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3246 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3247 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3248 nr_lmbs, spapr_drc_index(drc)); 3249 out: 3250 error_propagate(errp, local_err); 3251 } 3252 3253 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 3254 sPAPRMachineState *spapr) 3255 { 3256 PowerPCCPU *cpu = POWERPC_CPU(cs); 3257 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3258 int id = spapr_get_vcpu_id(cpu); 3259 void *fdt; 3260 int offset, fdt_size; 3261 char *nodename; 3262 3263 fdt = create_device_tree(&fdt_size); 3264 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3265 offset = fdt_add_subnode(fdt, 0, nodename); 3266 3267 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3268 g_free(nodename); 3269 3270 *fdt_offset = offset; 3271 return fdt; 3272 } 3273 3274 /* Callback to be called during DRC release. */ 3275 void spapr_core_release(DeviceState *dev) 3276 { 3277 MachineState *ms = MACHINE(qdev_get_hotplug_handler(dev)); 3278 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3279 CPUCore *cc = CPU_CORE(dev); 3280 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3281 3282 if (smc->pre_2_10_has_unused_icps) { 3283 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3284 int i; 3285 3286 for (i = 0; i < cc->nr_threads; i++) { 3287 CPUState *cs = CPU(sc->threads[i]); 3288 3289 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3290 } 3291 } 3292 3293 assert(core_slot); 3294 core_slot->cpu = NULL; 3295 object_unparent(OBJECT(dev)); 3296 } 3297 3298 static 3299 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3300 Error **errp) 3301 { 3302 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3303 int index; 3304 sPAPRDRConnector *drc; 3305 CPUCore *cc = CPU_CORE(dev); 3306 3307 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3308 error_setg(errp, "Unable to find CPU core with core-id: %d", 3309 cc->core_id); 3310 return; 3311 } 3312 if (index == 0) { 3313 error_setg(errp, "Boot CPU core may not be unplugged"); 3314 return; 3315 } 3316 3317 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3318 spapr_vcpu_id(spapr, cc->core_id)); 3319 g_assert(drc); 3320 3321 spapr_drc_detach(drc); 3322 3323 spapr_hotplug_req_remove_by_index(drc); 3324 } 3325 3326 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3327 Error **errp) 3328 { 3329 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3330 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3331 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3332 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3333 CPUCore *cc = CPU_CORE(dev); 3334 CPUState *cs = CPU(core->threads[0]); 3335 sPAPRDRConnector *drc; 3336 Error *local_err = NULL; 3337 CPUArchId *core_slot; 3338 int index; 3339 bool hotplugged = spapr_drc_hotplugged(dev); 3340 3341 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3342 if (!core_slot) { 3343 error_setg(errp, "Unable to find CPU core with core-id: %d", 3344 cc->core_id); 3345 return; 3346 } 3347 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3348 spapr_vcpu_id(spapr, cc->core_id)); 3349 3350 g_assert(drc || !mc->has_hotpluggable_cpus); 3351 3352 if (drc) { 3353 void *fdt; 3354 int fdt_offset; 3355 3356 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 3357 3358 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3359 if (local_err) { 3360 g_free(fdt); 3361 error_propagate(errp, local_err); 3362 return; 3363 } 3364 3365 if (hotplugged) { 3366 /* 3367 * Send hotplug notification interrupt to the guest only 3368 * in case of hotplugged CPUs. 3369 */ 3370 spapr_hotplug_req_add_by_index(drc); 3371 } else { 3372 spapr_drc_reset(drc); 3373 } 3374 } 3375 3376 core_slot->cpu = OBJECT(dev); 3377 3378 if (smc->pre_2_10_has_unused_icps) { 3379 int i; 3380 3381 for (i = 0; i < cc->nr_threads; i++) { 3382 cs = CPU(core->threads[i]); 3383 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3384 } 3385 } 3386 } 3387 3388 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3389 Error **errp) 3390 { 3391 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3392 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3393 Error *local_err = NULL; 3394 CPUCore *cc = CPU_CORE(dev); 3395 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3396 const char *type = object_get_typename(OBJECT(dev)); 3397 CPUArchId *core_slot; 3398 int index; 3399 3400 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3401 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3402 goto out; 3403 } 3404 3405 if (strcmp(base_core_type, type)) { 3406 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3407 goto out; 3408 } 3409 3410 if (cc->core_id % smp_threads) { 3411 error_setg(&local_err, "invalid core id %d", cc->core_id); 3412 goto out; 3413 } 3414 3415 /* 3416 * In general we should have homogeneous threads-per-core, but old 3417 * (pre hotplug support) machine types allow the last core to have 3418 * reduced threads as a compatibility hack for when we allowed 3419 * total vcpus not a multiple of threads-per-core. 3420 */ 3421 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3422 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3423 cc->nr_threads, smp_threads); 3424 goto out; 3425 } 3426 3427 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3428 if (!core_slot) { 3429 error_setg(&local_err, "core id %d out of range", cc->core_id); 3430 goto out; 3431 } 3432 3433 if (core_slot->cpu) { 3434 error_setg(&local_err, "core %d already populated", cc->core_id); 3435 goto out; 3436 } 3437 3438 numa_cpu_pre_plug(core_slot, dev, &local_err); 3439 3440 out: 3441 error_propagate(errp, local_err); 3442 } 3443 3444 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3445 DeviceState *dev, Error **errp) 3446 { 3447 MachineState *ms = MACHINE(hotplug_dev); 3448 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3449 3450 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3451 int node; 3452 3453 if (!smc->dr_lmb_enabled) { 3454 error_setg(errp, "Memory hotplug not supported for this machine"); 3455 return; 3456 } 3457 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 3458 if (*errp) { 3459 return; 3460 } 3461 if (node < 0 || node >= MAX_NODES) { 3462 error_setg(errp, "Invaild node %d", node); 3463 return; 3464 } 3465 3466 /* 3467 * Currently PowerPC kernel doesn't allow hot-adding memory to 3468 * memory-less node, but instead will silently add the memory 3469 * to the first node that has some memory. This causes two 3470 * unexpected behaviours for the user. 3471 * 3472 * - Memory gets hotplugged to a different node than what the user 3473 * specified. 3474 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 3475 * to memory-less node, a reboot will set things accordingly 3476 * and the previously hotplugged memory now ends in the right node. 3477 * This appears as if some memory moved from one node to another. 3478 * 3479 * So until kernel starts supporting memory hotplug to memory-less 3480 * nodes, just prevent such attempts upfront in QEMU. 3481 */ 3482 if (nb_numa_nodes && !numa_info[node].node_mem) { 3483 error_setg(errp, "Can't hotplug memory to memory-less node %d", 3484 node); 3485 return; 3486 } 3487 3488 spapr_memory_plug(hotplug_dev, dev, node, errp); 3489 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3490 spapr_core_plug(hotplug_dev, dev, errp); 3491 } 3492 } 3493 3494 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3495 DeviceState *dev, Error **errp) 3496 { 3497 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3498 MachineClass *mc = MACHINE_GET_CLASS(sms); 3499 3500 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3501 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3502 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3503 } else { 3504 /* NOTE: this means there is a window after guest reset, prior to 3505 * CAS negotiation, where unplug requests will fail due to the 3506 * capability not being detected yet. This is a bit different than 3507 * the case with PCI unplug, where the events will be queued and 3508 * eventually handled by the guest after boot 3509 */ 3510 error_setg(errp, "Memory hot unplug not supported for this guest"); 3511 } 3512 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3513 if (!mc->has_hotpluggable_cpus) { 3514 error_setg(errp, "CPU hot unplug not supported on this machine"); 3515 return; 3516 } 3517 spapr_core_unplug_request(hotplug_dev, dev, errp); 3518 } 3519 } 3520 3521 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3522 DeviceState *dev, Error **errp) 3523 { 3524 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3525 spapr_memory_pre_plug(hotplug_dev, dev, errp); 3526 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3527 spapr_core_pre_plug(hotplug_dev, dev, errp); 3528 } 3529 } 3530 3531 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3532 DeviceState *dev) 3533 { 3534 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3535 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3536 return HOTPLUG_HANDLER(machine); 3537 } 3538 return NULL; 3539 } 3540 3541 static CpuInstanceProperties 3542 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3543 { 3544 CPUArchId *core_slot; 3545 MachineClass *mc = MACHINE_GET_CLASS(machine); 3546 3547 /* make sure possible_cpu are intialized */ 3548 mc->possible_cpu_arch_ids(machine); 3549 /* get CPU core slot containing thread that matches cpu_index */ 3550 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3551 assert(core_slot); 3552 return core_slot->props; 3553 } 3554 3555 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 3556 { 3557 return idx / smp_cores % nb_numa_nodes; 3558 } 3559 3560 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3561 { 3562 int i; 3563 const char *core_type; 3564 int spapr_max_cores = max_cpus / smp_threads; 3565 MachineClass *mc = MACHINE_GET_CLASS(machine); 3566 3567 if (!mc->has_hotpluggable_cpus) { 3568 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3569 } 3570 if (machine->possible_cpus) { 3571 assert(machine->possible_cpus->len == spapr_max_cores); 3572 return machine->possible_cpus; 3573 } 3574 3575 core_type = spapr_get_cpu_core_type(machine->cpu_type); 3576 if (!core_type) { 3577 error_report("Unable to find sPAPR CPU Core definition"); 3578 exit(1); 3579 } 3580 3581 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3582 sizeof(CPUArchId) * spapr_max_cores); 3583 machine->possible_cpus->len = spapr_max_cores; 3584 for (i = 0; i < machine->possible_cpus->len; i++) { 3585 int core_id = i * smp_threads; 3586 3587 machine->possible_cpus->cpus[i].type = core_type; 3588 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3589 machine->possible_cpus->cpus[i].arch_id = core_id; 3590 machine->possible_cpus->cpus[i].props.has_core_id = true; 3591 machine->possible_cpus->cpus[i].props.core_id = core_id; 3592 } 3593 return machine->possible_cpus; 3594 } 3595 3596 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3597 uint64_t *buid, hwaddr *pio, 3598 hwaddr *mmio32, hwaddr *mmio64, 3599 unsigned n_dma, uint32_t *liobns, Error **errp) 3600 { 3601 /* 3602 * New-style PHB window placement. 3603 * 3604 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3605 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3606 * windows. 3607 * 3608 * Some guest kernels can't work with MMIO windows above 1<<46 3609 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3610 * 3611 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3612 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3613 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3614 * 1TiB 64-bit MMIO windows for each PHB. 3615 */ 3616 const uint64_t base_buid = 0x800000020000000ULL; 3617 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3618 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3619 int i; 3620 3621 /* Sanity check natural alignments */ 3622 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3623 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3624 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3625 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3626 /* Sanity check bounds */ 3627 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3628 SPAPR_PCI_MEM32_WIN_SIZE); 3629 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3630 SPAPR_PCI_MEM64_WIN_SIZE); 3631 3632 if (index >= SPAPR_MAX_PHBS) { 3633 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3634 SPAPR_MAX_PHBS - 1); 3635 return; 3636 } 3637 3638 *buid = base_buid + index; 3639 for (i = 0; i < n_dma; ++i) { 3640 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3641 } 3642 3643 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3644 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3645 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3646 } 3647 3648 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3649 { 3650 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3651 3652 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3653 } 3654 3655 static void spapr_ics_resend(XICSFabric *dev) 3656 { 3657 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3658 3659 ics_resend(spapr->ics); 3660 } 3661 3662 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 3663 { 3664 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 3665 3666 return cpu ? ICP(cpu->intc) : NULL; 3667 } 3668 3669 #define ICS_IRQ_FREE(ics, srcno) \ 3670 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) 3671 3672 static int ics_find_free_block(ICSState *ics, int num, int alignnum) 3673 { 3674 int first, i; 3675 3676 for (first = 0; first < ics->nr_irqs; first += alignnum) { 3677 if (num > (ics->nr_irqs - first)) { 3678 return -1; 3679 } 3680 for (i = first; i < first + num; ++i) { 3681 if (!ICS_IRQ_FREE(ics, i)) { 3682 break; 3683 } 3684 } 3685 if (i == (first + num)) { 3686 return first; 3687 } 3688 } 3689 3690 return -1; 3691 } 3692 3693 /* 3694 * Allocate the IRQ number and set the IRQ type, LSI or MSI 3695 */ 3696 static void spapr_irq_set_lsi(sPAPRMachineState *spapr, int irq, bool lsi) 3697 { 3698 ics_set_irq_type(spapr->ics, irq - spapr->ics->offset, lsi); 3699 } 3700 3701 int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi, 3702 Error **errp) 3703 { 3704 ICSState *ics = spapr->ics; 3705 int irq; 3706 3707 if (!ics) { 3708 return -1; 3709 } 3710 if (irq_hint) { 3711 if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) { 3712 error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint); 3713 return -1; 3714 } 3715 irq = irq_hint; 3716 } else { 3717 irq = ics_find_free_block(ics, 1, 1); 3718 if (irq < 0) { 3719 error_setg(errp, "can't allocate IRQ: no IRQ left"); 3720 return -1; 3721 } 3722 irq += ics->offset; 3723 } 3724 3725 spapr_irq_set_lsi(spapr, irq, lsi); 3726 trace_spapr_irq_alloc(irq); 3727 3728 return irq; 3729 } 3730 3731 /* 3732 * Allocate block of consecutive IRQs, and return the number of the first IRQ in 3733 * the block. If align==true, aligns the first IRQ number to num. 3734 */ 3735 int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi, 3736 bool align, Error **errp) 3737 { 3738 ICSState *ics = spapr->ics; 3739 int i, first = -1; 3740 3741 if (!ics) { 3742 return -1; 3743 } 3744 3745 /* 3746 * MSIMesage::data is used for storing VIRQ so 3747 * it has to be aligned to num to support multiple 3748 * MSI vectors. MSI-X is not affected by this. 3749 * The hint is used for the first IRQ, the rest should 3750 * be allocated continuously. 3751 */ 3752 if (align) { 3753 assert((num == 1) || (num == 2) || (num == 4) || 3754 (num == 8) || (num == 16) || (num == 32)); 3755 first = ics_find_free_block(ics, num, num); 3756 } else { 3757 first = ics_find_free_block(ics, num, 1); 3758 } 3759 if (first < 0) { 3760 error_setg(errp, "can't find a free %d-IRQ block", num); 3761 return -1; 3762 } 3763 3764 first += ics->offset; 3765 for (i = first; i < first + num; ++i) { 3766 spapr_irq_set_lsi(spapr, i, lsi); 3767 } 3768 3769 trace_spapr_irq_alloc_block(first, num, lsi, align); 3770 3771 return first; 3772 } 3773 3774 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num) 3775 { 3776 ICSState *ics = spapr->ics; 3777 int srcno = irq - ics->offset; 3778 int i; 3779 3780 if (ics_valid_irq(ics, irq)) { 3781 trace_spapr_irq_free(0, irq, num); 3782 for (i = srcno; i < srcno + num; ++i) { 3783 if (ICS_IRQ_FREE(ics, i)) { 3784 trace_spapr_irq_free_warn(0, i + ics->offset); 3785 } 3786 memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); 3787 } 3788 } 3789 } 3790 3791 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq) 3792 { 3793 ICSState *ics = spapr->ics; 3794 3795 if (ics_valid_irq(ics, irq)) { 3796 return ics->qirqs[irq - ics->offset]; 3797 } 3798 3799 return NULL; 3800 } 3801 3802 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3803 Monitor *mon) 3804 { 3805 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3806 CPUState *cs; 3807 3808 CPU_FOREACH(cs) { 3809 PowerPCCPU *cpu = POWERPC_CPU(cs); 3810 3811 icp_pic_print_info(ICP(cpu->intc), mon); 3812 } 3813 3814 ics_pic_print_info(spapr->ics, mon); 3815 } 3816 3817 int spapr_get_vcpu_id(PowerPCCPU *cpu) 3818 { 3819 return cpu->vcpu_id; 3820 } 3821 3822 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 3823 { 3824 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3825 int vcpu_id; 3826 3827 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 3828 3829 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 3830 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 3831 error_append_hint(errp, "Adjust the number of cpus to %d " 3832 "or try to raise the number of threads per core\n", 3833 vcpu_id * smp_threads / spapr->vsmt); 3834 return; 3835 } 3836 3837 cpu->vcpu_id = vcpu_id; 3838 } 3839 3840 PowerPCCPU *spapr_find_cpu(int vcpu_id) 3841 { 3842 CPUState *cs; 3843 3844 CPU_FOREACH(cs) { 3845 PowerPCCPU *cpu = POWERPC_CPU(cs); 3846 3847 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 3848 return cpu; 3849 } 3850 } 3851 3852 return NULL; 3853 } 3854 3855 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3856 { 3857 MachineClass *mc = MACHINE_CLASS(oc); 3858 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3859 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3860 NMIClass *nc = NMI_CLASS(oc); 3861 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3862 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3863 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3864 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3865 3866 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3867 3868 /* 3869 * We set up the default / latest behaviour here. The class_init 3870 * functions for the specific versioned machine types can override 3871 * these details for backwards compatibility 3872 */ 3873 mc->init = spapr_machine_init; 3874 mc->reset = spapr_machine_reset; 3875 mc->block_default_type = IF_SCSI; 3876 mc->max_cpus = 1024; 3877 mc->no_parallel = 1; 3878 mc->default_boot_order = ""; 3879 mc->default_ram_size = 512 * M_BYTE; 3880 mc->kvm_type = spapr_kvm_type; 3881 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 3882 mc->pci_allow_0_address = true; 3883 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3884 hc->pre_plug = spapr_machine_device_pre_plug; 3885 hc->plug = spapr_machine_device_plug; 3886 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 3887 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 3888 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3889 hc->unplug_request = spapr_machine_device_unplug_request; 3890 3891 smc->dr_lmb_enabled = true; 3892 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 3893 mc->has_hotpluggable_cpus = true; 3894 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 3895 fwc->get_dev_path = spapr_get_fw_dev_path; 3896 nc->nmi_monitor_handler = spapr_nmi; 3897 smc->phb_placement = spapr_phb_placement; 3898 vhc->hypercall = emulate_spapr_hypercall; 3899 vhc->hpt_mask = spapr_hpt_mask; 3900 vhc->map_hptes = spapr_map_hptes; 3901 vhc->unmap_hptes = spapr_unmap_hptes; 3902 vhc->store_hpte = spapr_store_hpte; 3903 vhc->get_patbe = spapr_get_patbe; 3904 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 3905 xic->ics_get = spapr_ics_get; 3906 xic->ics_resend = spapr_ics_resend; 3907 xic->icp_get = spapr_icp_get; 3908 ispc->print_info = spapr_pic_print_info; 3909 /* Force NUMA node memory size to be a multiple of 3910 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 3911 * in which LMBs are represented and hot-added 3912 */ 3913 mc->numa_mem_align_shift = 28; 3914 3915 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 3916 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 3917 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 3918 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 3919 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 3920 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 3921 spapr_caps_add_properties(smc, &error_abort); 3922 } 3923 3924 static const TypeInfo spapr_machine_info = { 3925 .name = TYPE_SPAPR_MACHINE, 3926 .parent = TYPE_MACHINE, 3927 .abstract = true, 3928 .instance_size = sizeof(sPAPRMachineState), 3929 .instance_init = spapr_instance_init, 3930 .instance_finalize = spapr_machine_finalizefn, 3931 .class_size = sizeof(sPAPRMachineClass), 3932 .class_init = spapr_machine_class_init, 3933 .interfaces = (InterfaceInfo[]) { 3934 { TYPE_FW_PATH_PROVIDER }, 3935 { TYPE_NMI }, 3936 { TYPE_HOTPLUG_HANDLER }, 3937 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3938 { TYPE_XICS_FABRIC }, 3939 { TYPE_INTERRUPT_STATS_PROVIDER }, 3940 { } 3941 }, 3942 }; 3943 3944 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3945 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3946 void *data) \ 3947 { \ 3948 MachineClass *mc = MACHINE_CLASS(oc); \ 3949 spapr_machine_##suffix##_class_options(mc); \ 3950 if (latest) { \ 3951 mc->alias = "pseries"; \ 3952 mc->is_default = 1; \ 3953 } \ 3954 } \ 3955 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3956 { \ 3957 MachineState *machine = MACHINE(obj); \ 3958 spapr_machine_##suffix##_instance_options(machine); \ 3959 } \ 3960 static const TypeInfo spapr_machine_##suffix##_info = { \ 3961 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3962 .parent = TYPE_SPAPR_MACHINE, \ 3963 .class_init = spapr_machine_##suffix##_class_init, \ 3964 .instance_init = spapr_machine_##suffix##_instance_init, \ 3965 }; \ 3966 static void spapr_machine_register_##suffix(void) \ 3967 { \ 3968 type_register(&spapr_machine_##suffix##_info); \ 3969 } \ 3970 type_init(spapr_machine_register_##suffix) 3971 3972 /* 3973 * pseries-2.12 3974 */ 3975 static void spapr_machine_2_12_instance_options(MachineState *machine) 3976 { 3977 } 3978 3979 static void spapr_machine_2_12_class_options(MachineClass *mc) 3980 { 3981 /* Defaults for the latest behaviour inherited from the base class */ 3982 } 3983 3984 DEFINE_SPAPR_MACHINE(2_12, "2.12", true); 3985 3986 /* 3987 * pseries-2.11 3988 */ 3989 #define SPAPR_COMPAT_2_11 \ 3990 HW_COMPAT_2_11 3991 3992 static void spapr_machine_2_11_instance_options(MachineState *machine) 3993 { 3994 spapr_machine_2_12_instance_options(machine); 3995 } 3996 3997 static void spapr_machine_2_11_class_options(MachineClass *mc) 3998 { 3999 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4000 4001 spapr_machine_2_12_class_options(mc); 4002 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4003 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11); 4004 } 4005 4006 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4007 4008 /* 4009 * pseries-2.10 4010 */ 4011 #define SPAPR_COMPAT_2_10 \ 4012 HW_COMPAT_2_10 4013 4014 static void spapr_machine_2_10_instance_options(MachineState *machine) 4015 { 4016 spapr_machine_2_11_instance_options(machine); 4017 } 4018 4019 static void spapr_machine_2_10_class_options(MachineClass *mc) 4020 { 4021 spapr_machine_2_11_class_options(mc); 4022 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10); 4023 } 4024 4025 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4026 4027 /* 4028 * pseries-2.9 4029 */ 4030 #define SPAPR_COMPAT_2_9 \ 4031 HW_COMPAT_2_9 \ 4032 { \ 4033 .driver = TYPE_POWERPC_CPU, \ 4034 .property = "pre-2.10-migration", \ 4035 .value = "on", \ 4036 }, \ 4037 4038 static void spapr_machine_2_9_instance_options(MachineState *machine) 4039 { 4040 spapr_machine_2_10_instance_options(machine); 4041 } 4042 4043 static void spapr_machine_2_9_class_options(MachineClass *mc) 4044 { 4045 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4046 4047 spapr_machine_2_10_class_options(mc); 4048 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); 4049 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4050 smc->pre_2_10_has_unused_icps = true; 4051 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4052 } 4053 4054 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4055 4056 /* 4057 * pseries-2.8 4058 */ 4059 #define SPAPR_COMPAT_2_8 \ 4060 HW_COMPAT_2_8 \ 4061 { \ 4062 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4063 .property = "pcie-extended-configuration-space", \ 4064 .value = "off", \ 4065 }, 4066 4067 static void spapr_machine_2_8_instance_options(MachineState *machine) 4068 { 4069 spapr_machine_2_9_instance_options(machine); 4070 } 4071 4072 static void spapr_machine_2_8_class_options(MachineClass *mc) 4073 { 4074 spapr_machine_2_9_class_options(mc); 4075 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 4076 mc->numa_mem_align_shift = 23; 4077 } 4078 4079 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4080 4081 /* 4082 * pseries-2.7 4083 */ 4084 #define SPAPR_COMPAT_2_7 \ 4085 HW_COMPAT_2_7 \ 4086 { \ 4087 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4088 .property = "mem_win_size", \ 4089 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 4090 }, \ 4091 { \ 4092 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4093 .property = "mem64_win_size", \ 4094 .value = "0", \ 4095 }, \ 4096 { \ 4097 .driver = TYPE_POWERPC_CPU, \ 4098 .property = "pre-2.8-migration", \ 4099 .value = "on", \ 4100 }, \ 4101 { \ 4102 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4103 .property = "pre-2.8-migration", \ 4104 .value = "on", \ 4105 }, 4106 4107 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 4108 uint64_t *buid, hwaddr *pio, 4109 hwaddr *mmio32, hwaddr *mmio64, 4110 unsigned n_dma, uint32_t *liobns, Error **errp) 4111 { 4112 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4113 const uint64_t base_buid = 0x800000020000000ULL; 4114 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4115 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4116 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4117 const uint32_t max_index = 255; 4118 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4119 4120 uint64_t ram_top = MACHINE(spapr)->ram_size; 4121 hwaddr phb0_base, phb_base; 4122 int i; 4123 4124 /* Do we have hotpluggable memory? */ 4125 if (MACHINE(spapr)->maxram_size > ram_top) { 4126 /* Can't just use maxram_size, because there may be an 4127 * alignment gap between normal and hotpluggable memory 4128 * regions */ 4129 ram_top = spapr->hotplug_memory.base + 4130 memory_region_size(&spapr->hotplug_memory.mr); 4131 } 4132 4133 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4134 4135 if (index > max_index) { 4136 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4137 max_index); 4138 return; 4139 } 4140 4141 *buid = base_buid + index; 4142 for (i = 0; i < n_dma; ++i) { 4143 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4144 } 4145 4146 phb_base = phb0_base + index * phb_spacing; 4147 *pio = phb_base + pio_offset; 4148 *mmio32 = phb_base + mmio_offset; 4149 /* 4150 * We don't set the 64-bit MMIO window, relying on the PHB's 4151 * fallback behaviour of automatically splitting a large "32-bit" 4152 * window into contiguous 32-bit and 64-bit windows 4153 */ 4154 } 4155 4156 static void spapr_machine_2_7_instance_options(MachineState *machine) 4157 { 4158 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 4159 4160 spapr_machine_2_8_instance_options(machine); 4161 spapr->use_hotplug_event_source = false; 4162 } 4163 4164 static void spapr_machine_2_7_class_options(MachineClass *mc) 4165 { 4166 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4167 4168 spapr_machine_2_8_class_options(mc); 4169 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4170 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 4171 smc->phb_placement = phb_placement_2_7; 4172 } 4173 4174 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4175 4176 /* 4177 * pseries-2.6 4178 */ 4179 #define SPAPR_COMPAT_2_6 \ 4180 HW_COMPAT_2_6 \ 4181 { \ 4182 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 4183 .property = "ddw",\ 4184 .value = stringify(off),\ 4185 }, 4186 4187 static void spapr_machine_2_6_instance_options(MachineState *machine) 4188 { 4189 spapr_machine_2_7_instance_options(machine); 4190 } 4191 4192 static void spapr_machine_2_6_class_options(MachineClass *mc) 4193 { 4194 spapr_machine_2_7_class_options(mc); 4195 mc->has_hotpluggable_cpus = false; 4196 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 4197 } 4198 4199 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4200 4201 /* 4202 * pseries-2.5 4203 */ 4204 #define SPAPR_COMPAT_2_5 \ 4205 HW_COMPAT_2_5 \ 4206 { \ 4207 .driver = "spapr-vlan", \ 4208 .property = "use-rx-buffer-pools", \ 4209 .value = "off", \ 4210 }, 4211 4212 static void spapr_machine_2_5_instance_options(MachineState *machine) 4213 { 4214 spapr_machine_2_6_instance_options(machine); 4215 } 4216 4217 static void spapr_machine_2_5_class_options(MachineClass *mc) 4218 { 4219 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4220 4221 spapr_machine_2_6_class_options(mc); 4222 smc->use_ohci_by_default = true; 4223 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 4224 } 4225 4226 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4227 4228 /* 4229 * pseries-2.4 4230 */ 4231 #define SPAPR_COMPAT_2_4 \ 4232 HW_COMPAT_2_4 4233 4234 static void spapr_machine_2_4_instance_options(MachineState *machine) 4235 { 4236 spapr_machine_2_5_instance_options(machine); 4237 } 4238 4239 static void spapr_machine_2_4_class_options(MachineClass *mc) 4240 { 4241 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4242 4243 spapr_machine_2_5_class_options(mc); 4244 smc->dr_lmb_enabled = false; 4245 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 4246 } 4247 4248 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4249 4250 /* 4251 * pseries-2.3 4252 */ 4253 #define SPAPR_COMPAT_2_3 \ 4254 HW_COMPAT_2_3 \ 4255 {\ 4256 .driver = "spapr-pci-host-bridge",\ 4257 .property = "dynamic-reconfiguration",\ 4258 .value = "off",\ 4259 }, 4260 4261 static void spapr_machine_2_3_instance_options(MachineState *machine) 4262 { 4263 spapr_machine_2_4_instance_options(machine); 4264 } 4265 4266 static void spapr_machine_2_3_class_options(MachineClass *mc) 4267 { 4268 spapr_machine_2_4_class_options(mc); 4269 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 4270 } 4271 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4272 4273 /* 4274 * pseries-2.2 4275 */ 4276 4277 #define SPAPR_COMPAT_2_2 \ 4278 HW_COMPAT_2_2 \ 4279 {\ 4280 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 4281 .property = "mem_win_size",\ 4282 .value = "0x20000000",\ 4283 }, 4284 4285 static void spapr_machine_2_2_instance_options(MachineState *machine) 4286 { 4287 spapr_machine_2_3_instance_options(machine); 4288 machine->suppress_vmdesc = true; 4289 } 4290 4291 static void spapr_machine_2_2_class_options(MachineClass *mc) 4292 { 4293 spapr_machine_2_3_class_options(mc); 4294 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 4295 } 4296 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4297 4298 /* 4299 * pseries-2.1 4300 */ 4301 #define SPAPR_COMPAT_2_1 \ 4302 HW_COMPAT_2_1 4303 4304 static void spapr_machine_2_1_instance_options(MachineState *machine) 4305 { 4306 spapr_machine_2_2_instance_options(machine); 4307 } 4308 4309 static void spapr_machine_2_1_class_options(MachineClass *mc) 4310 { 4311 spapr_machine_2_2_class_options(mc); 4312 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 4313 } 4314 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4315 4316 static void spapr_machine_register_types(void) 4317 { 4318 type_register_static(&spapr_machine_info); 4319 } 4320 4321 type_init(spapr_machine_register_types) 4322