1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/datadir.h" 30 #include "qapi/error.h" 31 #include "qapi/qapi-events-machine.h" 32 #include "qapi/visitor.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/hostmem.h" 35 #include "sysemu/numa.h" 36 #include "sysemu/qtest.h" 37 #include "sysemu/reset.h" 38 #include "sysemu/runstate.h" 39 #include "qemu/log.h" 40 #include "hw/fw-path-provider.h" 41 #include "elf.h" 42 #include "net/net.h" 43 #include "sysemu/device_tree.h" 44 #include "sysemu/cpus.h" 45 #include "sysemu/hw_accel.h" 46 #include "kvm_ppc.h" 47 #include "migration/misc.h" 48 #include "migration/qemu-file-types.h" 49 #include "migration/global_state.h" 50 #include "migration/register.h" 51 #include "migration/blocker.h" 52 #include "mmu-hash64.h" 53 #include "mmu-book3s-v3.h" 54 #include "cpu-models.h" 55 #include "hw/core/cpu.h" 56 57 #include "hw/ppc/ppc.h" 58 #include "hw/loader.h" 59 60 #include "hw/ppc/fdt.h" 61 #include "hw/ppc/spapr.h" 62 #include "hw/ppc/spapr_vio.h" 63 #include "hw/qdev-properties.h" 64 #include "hw/pci-host/spapr.h" 65 #include "hw/pci/msi.h" 66 67 #include "hw/pci/pci.h" 68 #include "hw/scsi/scsi.h" 69 #include "hw/virtio/virtio-scsi.h" 70 #include "hw/virtio/vhost-scsi-common.h" 71 72 #include "exec/ram_addr.h" 73 #include "hw/usb.h" 74 #include "qemu/config-file.h" 75 #include "qemu/error-report.h" 76 #include "trace.h" 77 #include "hw/nmi.h" 78 #include "hw/intc/intc.h" 79 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 #include "hw/ppc/spapr_nvdimm.h" 84 #include "hw/ppc/spapr_numa.h" 85 #include "hw/ppc/pef.h" 86 87 #include "monitor/monitor.h" 88 89 #include <libfdt.h> 90 91 /* SLOF memory layout: 92 * 93 * SLOF raw image loaded at 0, copies its romfs right below the flat 94 * device-tree, then position SLOF itself 31M below that 95 * 96 * So we set FW_OVERHEAD to 40MB which should account for all of that 97 * and more 98 * 99 * We load our kernel at 4M, leaving space for SLOF initial image 100 */ 101 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */ 102 #define FW_MAX_SIZE 0x400000 103 #define FW_FILE_NAME "slof.bin" 104 #define FW_OVERHEAD 0x2800000 105 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 106 107 #define MIN_RMA_SLOF (128 * MiB) 108 109 #define PHANDLE_INTC 0x00001111 110 111 /* These two functions implement the VCPU id numbering: one to compute them 112 * all and one to identify thread 0 of a VCORE. Any change to the first one 113 * is likely to have an impact on the second one, so let's keep them close. 114 */ 115 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 116 { 117 MachineState *ms = MACHINE(spapr); 118 unsigned int smp_threads = ms->smp.threads; 119 120 assert(spapr->vsmt); 121 return 122 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 123 } 124 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 125 PowerPCCPU *cpu) 126 { 127 assert(spapr->vsmt); 128 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 129 } 130 131 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 132 { 133 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 134 * and newer QEMUs don't even have them. In both cases, we don't want 135 * to send anything on the wire. 136 */ 137 return false; 138 } 139 140 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 141 .name = "icp/server", 142 .version_id = 1, 143 .minimum_version_id = 1, 144 .needed = pre_2_10_vmstate_dummy_icp_needed, 145 .fields = (VMStateField[]) { 146 VMSTATE_UNUSED(4), /* uint32_t xirr */ 147 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 148 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 149 VMSTATE_END_OF_LIST() 150 }, 151 }; 152 153 static void pre_2_10_vmstate_register_dummy_icp(int i) 154 { 155 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 156 (void *)(uintptr_t) i); 157 } 158 159 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 160 { 161 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 162 (void *)(uintptr_t) i); 163 } 164 165 int spapr_max_server_number(SpaprMachineState *spapr) 166 { 167 MachineState *ms = MACHINE(spapr); 168 169 assert(spapr->vsmt); 170 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 171 } 172 173 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 174 int smt_threads) 175 { 176 int i, ret = 0; 177 uint32_t servers_prop[smt_threads]; 178 uint32_t gservers_prop[smt_threads * 2]; 179 int index = spapr_get_vcpu_id(cpu); 180 181 if (cpu->compat_pvr) { 182 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 183 if (ret < 0) { 184 return ret; 185 } 186 } 187 188 /* Build interrupt servers and gservers properties */ 189 for (i = 0; i < smt_threads; i++) { 190 servers_prop[i] = cpu_to_be32(index + i); 191 /* Hack, direct the group queues back to cpu 0 */ 192 gservers_prop[i*2] = cpu_to_be32(index + i); 193 gservers_prop[i*2 + 1] = 0; 194 } 195 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 196 servers_prop, sizeof(servers_prop)); 197 if (ret < 0) { 198 return ret; 199 } 200 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 201 gservers_prop, sizeof(gservers_prop)); 202 203 return ret; 204 } 205 206 static void spapr_dt_pa_features(SpaprMachineState *spapr, 207 PowerPCCPU *cpu, 208 void *fdt, int offset) 209 { 210 uint8_t pa_features_206[] = { 6, 0, 211 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 212 uint8_t pa_features_207[] = { 24, 0, 213 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 214 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 215 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 216 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 217 uint8_t pa_features_300[] = { 66, 0, 218 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 219 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 220 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 221 /* 6: DS207 */ 222 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 223 /* 16: Vector */ 224 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 225 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 226 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 227 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 228 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 229 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 230 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 231 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 232 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 233 /* 42: PM, 44: PC RA, 46: SC vec'd */ 234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 235 /* 48: SIMD, 50: QP BFP, 52: String */ 236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 237 /* 54: DecFP, 56: DecI, 58: SHA */ 238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 239 /* 60: NM atomic, 62: RNG */ 240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 241 }; 242 uint8_t *pa_features = NULL; 243 size_t pa_size; 244 245 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 246 pa_features = pa_features_206; 247 pa_size = sizeof(pa_features_206); 248 } 249 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 250 pa_features = pa_features_207; 251 pa_size = sizeof(pa_features_207); 252 } 253 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 254 pa_features = pa_features_300; 255 pa_size = sizeof(pa_features_300); 256 } 257 if (!pa_features) { 258 return; 259 } 260 261 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 262 /* 263 * Note: we keep CI large pages off by default because a 64K capable 264 * guest provisioned with large pages might otherwise try to map a qemu 265 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 266 * even if that qemu runs on a 4k host. 267 * We dd this bit back here if we are confident this is not an issue 268 */ 269 pa_features[3] |= 0x20; 270 } 271 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 272 pa_features[24] |= 0x80; /* Transactional memory support */ 273 } 274 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 275 /* Workaround for broken kernels that attempt (guest) radix 276 * mode when they can't handle it, if they see the radix bit set 277 * in pa-features. So hide it from them. */ 278 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 279 } 280 281 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 282 } 283 284 static hwaddr spapr_node0_size(MachineState *machine) 285 { 286 if (machine->numa_state->num_nodes) { 287 int i; 288 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 289 if (machine->numa_state->nodes[i].node_mem) { 290 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 291 machine->ram_size); 292 } 293 } 294 } 295 return machine->ram_size; 296 } 297 298 static void add_str(GString *s, const gchar *s1) 299 { 300 g_string_append_len(s, s1, strlen(s1) + 1); 301 } 302 303 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 304 hwaddr start, hwaddr size) 305 { 306 char mem_name[32]; 307 uint64_t mem_reg_property[2]; 308 int off; 309 310 mem_reg_property[0] = cpu_to_be64(start); 311 mem_reg_property[1] = cpu_to_be64(size); 312 313 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 314 off = fdt_add_subnode(fdt, 0, mem_name); 315 _FDT(off); 316 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 317 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 318 sizeof(mem_reg_property)))); 319 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 320 return off; 321 } 322 323 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 324 { 325 MemoryDeviceInfoList *info; 326 327 for (info = list; info; info = info->next) { 328 MemoryDeviceInfo *value = info->value; 329 330 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 331 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 332 333 if (addr >= pcdimm_info->addr && 334 addr < (pcdimm_info->addr + pcdimm_info->size)) { 335 return pcdimm_info->node; 336 } 337 } 338 } 339 340 return -1; 341 } 342 343 struct sPAPRDrconfCellV2 { 344 uint32_t seq_lmbs; 345 uint64_t base_addr; 346 uint32_t drc_index; 347 uint32_t aa_index; 348 uint32_t flags; 349 } QEMU_PACKED; 350 351 typedef struct DrconfCellQueue { 352 struct sPAPRDrconfCellV2 cell; 353 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 354 } DrconfCellQueue; 355 356 static DrconfCellQueue * 357 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 358 uint32_t drc_index, uint32_t aa_index, 359 uint32_t flags) 360 { 361 DrconfCellQueue *elem; 362 363 elem = g_malloc0(sizeof(*elem)); 364 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 365 elem->cell.base_addr = cpu_to_be64(base_addr); 366 elem->cell.drc_index = cpu_to_be32(drc_index); 367 elem->cell.aa_index = cpu_to_be32(aa_index); 368 elem->cell.flags = cpu_to_be32(flags); 369 370 return elem; 371 } 372 373 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 374 int offset, MemoryDeviceInfoList *dimms) 375 { 376 MachineState *machine = MACHINE(spapr); 377 uint8_t *int_buf, *cur_index; 378 int ret; 379 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 380 uint64_t addr, cur_addr, size; 381 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 382 uint64_t mem_end = machine->device_memory->base + 383 memory_region_size(&machine->device_memory->mr); 384 uint32_t node, buf_len, nr_entries = 0; 385 SpaprDrc *drc; 386 DrconfCellQueue *elem, *next; 387 MemoryDeviceInfoList *info; 388 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 389 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 390 391 /* Entry to cover RAM and the gap area */ 392 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 393 SPAPR_LMB_FLAGS_RESERVED | 394 SPAPR_LMB_FLAGS_DRC_INVALID); 395 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 396 nr_entries++; 397 398 cur_addr = machine->device_memory->base; 399 for (info = dimms; info; info = info->next) { 400 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 401 402 addr = di->addr; 403 size = di->size; 404 node = di->node; 405 406 /* 407 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 408 * area is marked hotpluggable in the next iteration for the bigger 409 * chunk including the NVDIMM occupied area. 410 */ 411 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 412 continue; 413 414 /* Entry for hot-pluggable area */ 415 if (cur_addr < addr) { 416 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 417 g_assert(drc); 418 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 419 cur_addr, spapr_drc_index(drc), -1, 0); 420 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 421 nr_entries++; 422 } 423 424 /* Entry for DIMM */ 425 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 426 g_assert(drc); 427 elem = spapr_get_drconf_cell(size / lmb_size, addr, 428 spapr_drc_index(drc), node, 429 (SPAPR_LMB_FLAGS_ASSIGNED | 430 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 431 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 432 nr_entries++; 433 cur_addr = addr + size; 434 } 435 436 /* Entry for remaining hotpluggable area */ 437 if (cur_addr < mem_end) { 438 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 439 g_assert(drc); 440 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 441 cur_addr, spapr_drc_index(drc), -1, 0); 442 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 443 nr_entries++; 444 } 445 446 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 447 int_buf = cur_index = g_malloc0(buf_len); 448 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 449 cur_index += sizeof(nr_entries); 450 451 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 452 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 453 cur_index += sizeof(elem->cell); 454 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 455 g_free(elem); 456 } 457 458 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 459 g_free(int_buf); 460 if (ret < 0) { 461 return -1; 462 } 463 return 0; 464 } 465 466 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 467 int offset, MemoryDeviceInfoList *dimms) 468 { 469 MachineState *machine = MACHINE(spapr); 470 int i, ret; 471 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 472 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 473 uint32_t nr_lmbs = (machine->device_memory->base + 474 memory_region_size(&machine->device_memory->mr)) / 475 lmb_size; 476 uint32_t *int_buf, *cur_index, buf_len; 477 478 /* 479 * Allocate enough buffer size to fit in ibm,dynamic-memory 480 */ 481 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 482 cur_index = int_buf = g_malloc0(buf_len); 483 int_buf[0] = cpu_to_be32(nr_lmbs); 484 cur_index++; 485 for (i = 0; i < nr_lmbs; i++) { 486 uint64_t addr = i * lmb_size; 487 uint32_t *dynamic_memory = cur_index; 488 489 if (i >= device_lmb_start) { 490 SpaprDrc *drc; 491 492 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 493 g_assert(drc); 494 495 dynamic_memory[0] = cpu_to_be32(addr >> 32); 496 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 497 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 498 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 499 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 500 if (memory_region_present(get_system_memory(), addr)) { 501 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 502 } else { 503 dynamic_memory[5] = cpu_to_be32(0); 504 } 505 } else { 506 /* 507 * LMB information for RMA, boot time RAM and gap b/n RAM and 508 * device memory region -- all these are marked as reserved 509 * and as having no valid DRC. 510 */ 511 dynamic_memory[0] = cpu_to_be32(addr >> 32); 512 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 513 dynamic_memory[2] = cpu_to_be32(0); 514 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 515 dynamic_memory[4] = cpu_to_be32(-1); 516 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 517 SPAPR_LMB_FLAGS_DRC_INVALID); 518 } 519 520 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 521 } 522 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 523 g_free(int_buf); 524 if (ret < 0) { 525 return -1; 526 } 527 return 0; 528 } 529 530 /* 531 * Adds ibm,dynamic-reconfiguration-memory node. 532 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 533 * of this device tree node. 534 */ 535 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 536 void *fdt) 537 { 538 MachineState *machine = MACHINE(spapr); 539 int ret, offset; 540 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 541 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 542 cpu_to_be32(lmb_size & 0xffffffff)}; 543 MemoryDeviceInfoList *dimms = NULL; 544 545 /* 546 * Don't create the node if there is no device memory 547 */ 548 if (machine->ram_size == machine->maxram_size) { 549 return 0; 550 } 551 552 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 553 554 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 555 sizeof(prop_lmb_size)); 556 if (ret < 0) { 557 return ret; 558 } 559 560 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 561 if (ret < 0) { 562 return ret; 563 } 564 565 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 566 if (ret < 0) { 567 return ret; 568 } 569 570 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 571 dimms = qmp_memory_device_list(); 572 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 573 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 574 } else { 575 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 576 } 577 qapi_free_MemoryDeviceInfoList(dimms); 578 579 if (ret < 0) { 580 return ret; 581 } 582 583 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 584 585 return ret; 586 } 587 588 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 589 { 590 MachineState *machine = MACHINE(spapr); 591 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 592 hwaddr mem_start, node_size; 593 int i, nb_nodes = machine->numa_state->num_nodes; 594 NodeInfo *nodes = machine->numa_state->nodes; 595 596 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 597 if (!nodes[i].node_mem) { 598 continue; 599 } 600 if (mem_start >= machine->ram_size) { 601 node_size = 0; 602 } else { 603 node_size = nodes[i].node_mem; 604 if (node_size > machine->ram_size - mem_start) { 605 node_size = machine->ram_size - mem_start; 606 } 607 } 608 if (!mem_start) { 609 /* spapr_machine_init() checks for rma_size <= node0_size 610 * already */ 611 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 612 mem_start += spapr->rma_size; 613 node_size -= spapr->rma_size; 614 } 615 for ( ; node_size; ) { 616 hwaddr sizetmp = pow2floor(node_size); 617 618 /* mem_start != 0 here */ 619 if (ctzl(mem_start) < ctzl(sizetmp)) { 620 sizetmp = 1ULL << ctzl(mem_start); 621 } 622 623 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 624 node_size -= sizetmp; 625 mem_start += sizetmp; 626 } 627 } 628 629 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 630 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 631 int ret; 632 633 g_assert(smc->dr_lmb_enabled); 634 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 635 if (ret) { 636 return ret; 637 } 638 } 639 640 return 0; 641 } 642 643 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 644 SpaprMachineState *spapr) 645 { 646 MachineState *ms = MACHINE(spapr); 647 PowerPCCPU *cpu = POWERPC_CPU(cs); 648 CPUPPCState *env = &cpu->env; 649 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 650 int index = spapr_get_vcpu_id(cpu); 651 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 652 0xffffffff, 0xffffffff}; 653 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 654 : SPAPR_TIMEBASE_FREQ; 655 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 656 uint32_t page_sizes_prop[64]; 657 size_t page_sizes_prop_size; 658 unsigned int smp_threads = ms->smp.threads; 659 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 660 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 661 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 662 SpaprDrc *drc; 663 int drc_index; 664 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 665 int i; 666 667 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 668 if (drc) { 669 drc_index = spapr_drc_index(drc); 670 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 671 } 672 673 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 674 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 675 676 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 677 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 678 env->dcache_line_size))); 679 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 680 env->dcache_line_size))); 681 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 682 env->icache_line_size))); 683 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 684 env->icache_line_size))); 685 686 if (pcc->l1_dcache_size) { 687 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 688 pcc->l1_dcache_size))); 689 } else { 690 warn_report("Unknown L1 dcache size for cpu"); 691 } 692 if (pcc->l1_icache_size) { 693 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 694 pcc->l1_icache_size))); 695 } else { 696 warn_report("Unknown L1 icache size for cpu"); 697 } 698 699 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 700 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 701 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 702 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 703 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 704 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 705 706 if (env->spr_cb[SPR_PURR].oea_read) { 707 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 708 } 709 if (env->spr_cb[SPR_SPURR].oea_read) { 710 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 711 } 712 713 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 714 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 715 segs, sizeof(segs)))); 716 } 717 718 /* Advertise VSX (vector extensions) if available 719 * 1 == VMX / Altivec available 720 * 2 == VSX available 721 * 722 * Only CPUs for which we create core types in spapr_cpu_core.c 723 * are possible, and all of those have VMX */ 724 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 725 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 726 } else { 727 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 728 } 729 730 /* Advertise DFP (Decimal Floating Point) if available 731 * 0 / no property == no DFP 732 * 1 == DFP available */ 733 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 734 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 735 } 736 737 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 738 sizeof(page_sizes_prop)); 739 if (page_sizes_prop_size) { 740 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 741 page_sizes_prop, page_sizes_prop_size))); 742 } 743 744 spapr_dt_pa_features(spapr, cpu, fdt, offset); 745 746 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 747 cs->cpu_index / vcpus_per_socket))); 748 749 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 750 pft_size_prop, sizeof(pft_size_prop)))); 751 752 if (ms->numa_state->num_nodes > 1) { 753 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 754 } 755 756 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 757 758 if (pcc->radix_page_info) { 759 for (i = 0; i < pcc->radix_page_info->count; i++) { 760 radix_AP_encodings[i] = 761 cpu_to_be32(pcc->radix_page_info->entries[i]); 762 } 763 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 764 radix_AP_encodings, 765 pcc->radix_page_info->count * 766 sizeof(radix_AP_encodings[0])))); 767 } 768 769 /* 770 * We set this property to let the guest know that it can use the large 771 * decrementer and its width in bits. 772 */ 773 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 774 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 775 pcc->lrg_decr_bits))); 776 } 777 778 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 779 { 780 CPUState **rev; 781 CPUState *cs; 782 int n_cpus; 783 int cpus_offset; 784 int i; 785 786 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 787 _FDT(cpus_offset); 788 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 789 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 790 791 /* 792 * We walk the CPUs in reverse order to ensure that CPU DT nodes 793 * created by fdt_add_subnode() end up in the right order in FDT 794 * for the guest kernel the enumerate the CPUs correctly. 795 * 796 * The CPU list cannot be traversed in reverse order, so we need 797 * to do extra work. 798 */ 799 n_cpus = 0; 800 rev = NULL; 801 CPU_FOREACH(cs) { 802 rev = g_renew(CPUState *, rev, n_cpus + 1); 803 rev[n_cpus++] = cs; 804 } 805 806 for (i = n_cpus - 1; i >= 0; i--) { 807 CPUState *cs = rev[i]; 808 PowerPCCPU *cpu = POWERPC_CPU(cs); 809 int index = spapr_get_vcpu_id(cpu); 810 DeviceClass *dc = DEVICE_GET_CLASS(cs); 811 g_autofree char *nodename = NULL; 812 int offset; 813 814 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 815 continue; 816 } 817 818 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 819 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 820 _FDT(offset); 821 spapr_dt_cpu(cs, fdt, offset, spapr); 822 } 823 824 g_free(rev); 825 } 826 827 static int spapr_dt_rng(void *fdt) 828 { 829 int node; 830 int ret; 831 832 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 833 if (node <= 0) { 834 return -1; 835 } 836 ret = fdt_setprop_string(fdt, node, "device_type", 837 "ibm,platform-facilities"); 838 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 839 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 840 841 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 842 if (node <= 0) { 843 return -1; 844 } 845 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 846 847 return ret ? -1 : 0; 848 } 849 850 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 851 { 852 MachineState *ms = MACHINE(spapr); 853 int rtas; 854 GString *hypertas = g_string_sized_new(256); 855 GString *qemu_hypertas = g_string_sized_new(256); 856 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 857 memory_region_size(&MACHINE(spapr)->device_memory->mr); 858 uint32_t lrdr_capacity[] = { 859 cpu_to_be32(max_device_addr >> 32), 860 cpu_to_be32(max_device_addr & 0xffffffff), 861 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 862 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 863 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 864 }; 865 866 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 867 868 /* hypertas */ 869 add_str(hypertas, "hcall-pft"); 870 add_str(hypertas, "hcall-term"); 871 add_str(hypertas, "hcall-dabr"); 872 add_str(hypertas, "hcall-interrupt"); 873 add_str(hypertas, "hcall-tce"); 874 add_str(hypertas, "hcall-vio"); 875 add_str(hypertas, "hcall-splpar"); 876 add_str(hypertas, "hcall-join"); 877 add_str(hypertas, "hcall-bulk"); 878 add_str(hypertas, "hcall-set-mode"); 879 add_str(hypertas, "hcall-sprg0"); 880 add_str(hypertas, "hcall-copy"); 881 add_str(hypertas, "hcall-debug"); 882 add_str(hypertas, "hcall-vphn"); 883 add_str(qemu_hypertas, "hcall-memop1"); 884 885 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 886 add_str(hypertas, "hcall-multi-tce"); 887 } 888 889 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 890 add_str(hypertas, "hcall-hpt-resize"); 891 } 892 893 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 894 hypertas->str, hypertas->len)); 895 g_string_free(hypertas, TRUE); 896 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 897 qemu_hypertas->str, qemu_hypertas->len)); 898 g_string_free(qemu_hypertas, TRUE); 899 900 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 901 902 /* 903 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 904 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 905 * 906 * The system reset requirements are driven by existing Linux and PowerVM 907 * implementation which (contrary to PAPR) saves r3 in the error log 908 * structure like machine check, so Linux expects to find the saved r3 909 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 910 * does not look at the error value). 911 * 912 * System reset interrupts are not subject to interlock like machine 913 * check, so this memory area could be corrupted if the sreset is 914 * interrupted by a machine check (or vice versa) if it was shared. To 915 * prevent this, system reset uses per-CPU areas for the sreset save 916 * area. A system reset that interrupts a system reset handler could 917 * still overwrite this area, but Linux doesn't try to recover in that 918 * case anyway. 919 * 920 * The extra 8 bytes is required because Linux's FWNMI error log check 921 * is off-by-one. 922 */ 923 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX + 924 ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t))); 925 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 926 RTAS_ERROR_LOG_MAX)); 927 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 928 RTAS_EVENT_SCAN_RATE)); 929 930 g_assert(msi_nonbroken); 931 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 932 933 /* 934 * According to PAPR, rtas ibm,os-term does not guarantee a return 935 * back to the guest cpu. 936 * 937 * While an additional ibm,extended-os-term property indicates 938 * that rtas call return will always occur. Set this property. 939 */ 940 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 941 942 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 943 lrdr_capacity, sizeof(lrdr_capacity))); 944 945 spapr_dt_rtas_tokens(fdt, rtas); 946 } 947 948 /* 949 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 950 * and the XIVE features that the guest may request and thus the valid 951 * values for bytes 23..26 of option vector 5: 952 */ 953 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 954 int chosen) 955 { 956 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 957 958 char val[2 * 4] = { 959 23, 0x00, /* XICS / XIVE mode */ 960 24, 0x00, /* Hash/Radix, filled in below. */ 961 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 962 26, 0x40, /* Radix options: GTSE == yes. */ 963 }; 964 965 if (spapr->irq->xics && spapr->irq->xive) { 966 val[1] = SPAPR_OV5_XIVE_BOTH; 967 } else if (spapr->irq->xive) { 968 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 969 } else { 970 assert(spapr->irq->xics); 971 val[1] = SPAPR_OV5_XIVE_LEGACY; 972 } 973 974 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 975 first_ppc_cpu->compat_pvr)) { 976 /* 977 * If we're in a pre POWER9 compat mode then the guest should 978 * do hash and use the legacy interrupt mode 979 */ 980 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 981 val[3] = 0x00; /* Hash */ 982 } else if (kvm_enabled()) { 983 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 984 val[3] = 0x80; /* OV5_MMU_BOTH */ 985 } else if (kvmppc_has_cap_mmu_radix()) { 986 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 987 } else { 988 val[3] = 0x00; /* Hash */ 989 } 990 } else { 991 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 992 val[3] = 0xC0; 993 } 994 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 995 val, sizeof(val))); 996 } 997 998 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 999 { 1000 MachineState *machine = MACHINE(spapr); 1001 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1002 int chosen; 1003 1004 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1005 1006 if (reset) { 1007 const char *boot_device = machine->boot_order; 1008 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1009 size_t cb = 0; 1010 char *bootlist = get_boot_devices_list(&cb); 1011 1012 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1013 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1014 machine->kernel_cmdline)); 1015 } 1016 1017 if (spapr->initrd_size) { 1018 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1019 spapr->initrd_base)); 1020 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1021 spapr->initrd_base + spapr->initrd_size)); 1022 } 1023 1024 if (spapr->kernel_size) { 1025 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1026 cpu_to_be64(spapr->kernel_size) }; 1027 1028 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1029 &kprop, sizeof(kprop))); 1030 if (spapr->kernel_le) { 1031 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1032 } 1033 } 1034 if (boot_menu) { 1035 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1036 } 1037 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1038 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1039 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1040 1041 if (cb && bootlist) { 1042 int i; 1043 1044 for (i = 0; i < cb; i++) { 1045 if (bootlist[i] == '\n') { 1046 bootlist[i] = ' '; 1047 } 1048 } 1049 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1050 } 1051 1052 if (boot_device && strlen(boot_device)) { 1053 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1054 } 1055 1056 if (!spapr->has_graphics && stdout_path) { 1057 /* 1058 * "linux,stdout-path" and "stdout" properties are 1059 * deprecated by linux kernel. New platforms should only 1060 * use the "stdout-path" property. Set the new property 1061 * and continue using older property to remain compatible 1062 * with the existing firmware. 1063 */ 1064 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1065 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1066 } 1067 1068 /* 1069 * We can deal with BAR reallocation just fine, advertise it 1070 * to the guest 1071 */ 1072 if (smc->linux_pci_probe) { 1073 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1074 } 1075 1076 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1077 1078 g_free(stdout_path); 1079 g_free(bootlist); 1080 } 1081 1082 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1083 } 1084 1085 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1086 { 1087 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1088 * KVM to work under pHyp with some guest co-operation */ 1089 int hypervisor; 1090 uint8_t hypercall[16]; 1091 1092 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1093 /* indicate KVM hypercall interface */ 1094 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1095 if (kvmppc_has_cap_fixup_hcalls()) { 1096 /* 1097 * Older KVM versions with older guest kernels were broken 1098 * with the magic page, don't allow the guest to map it. 1099 */ 1100 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1101 sizeof(hypercall))) { 1102 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1103 hypercall, sizeof(hypercall))); 1104 } 1105 } 1106 } 1107 1108 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1109 { 1110 MachineState *machine = MACHINE(spapr); 1111 MachineClass *mc = MACHINE_GET_CLASS(machine); 1112 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1113 uint32_t root_drc_type_mask = 0; 1114 int ret; 1115 void *fdt; 1116 SpaprPhbState *phb; 1117 char *buf; 1118 1119 fdt = g_malloc0(space); 1120 _FDT((fdt_create_empty_tree(fdt, space))); 1121 1122 /* Root node */ 1123 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1124 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1125 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1126 1127 /* Guest UUID & Name*/ 1128 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1129 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1130 if (qemu_uuid_set) { 1131 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1132 } 1133 g_free(buf); 1134 1135 if (qemu_get_vm_name()) { 1136 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1137 qemu_get_vm_name())); 1138 } 1139 1140 /* Host Model & Serial Number */ 1141 if (spapr->host_model) { 1142 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1143 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1144 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1145 g_free(buf); 1146 } 1147 1148 if (spapr->host_serial) { 1149 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1150 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1151 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1152 g_free(buf); 1153 } 1154 1155 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1156 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1157 1158 /* /interrupt controller */ 1159 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1160 1161 ret = spapr_dt_memory(spapr, fdt); 1162 if (ret < 0) { 1163 error_report("couldn't setup memory nodes in fdt"); 1164 exit(1); 1165 } 1166 1167 /* /vdevice */ 1168 spapr_dt_vdevice(spapr->vio_bus, fdt); 1169 1170 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1171 ret = spapr_dt_rng(fdt); 1172 if (ret < 0) { 1173 error_report("could not set up rng device in the fdt"); 1174 exit(1); 1175 } 1176 } 1177 1178 QLIST_FOREACH(phb, &spapr->phbs, list) { 1179 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1180 if (ret < 0) { 1181 error_report("couldn't setup PCI devices in fdt"); 1182 exit(1); 1183 } 1184 } 1185 1186 spapr_dt_cpus(fdt, spapr); 1187 1188 /* ibm,drc-indexes and friends */ 1189 if (smc->dr_lmb_enabled) { 1190 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1191 } 1192 if (smc->dr_phb_enabled) { 1193 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1194 } 1195 if (mc->nvdimm_supported) { 1196 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1197 } 1198 if (root_drc_type_mask) { 1199 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1200 } 1201 1202 if (mc->has_hotpluggable_cpus) { 1203 int offset = fdt_path_offset(fdt, "/cpus"); 1204 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1205 if (ret < 0) { 1206 error_report("Couldn't set up CPU DR device tree properties"); 1207 exit(1); 1208 } 1209 } 1210 1211 /* /event-sources */ 1212 spapr_dt_events(spapr, fdt); 1213 1214 /* /rtas */ 1215 spapr_dt_rtas(spapr, fdt); 1216 1217 /* /chosen */ 1218 spapr_dt_chosen(spapr, fdt, reset); 1219 1220 /* /hypervisor */ 1221 if (kvm_enabled()) { 1222 spapr_dt_hypervisor(spapr, fdt); 1223 } 1224 1225 /* Build memory reserve map */ 1226 if (reset) { 1227 if (spapr->kernel_size) { 1228 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1229 spapr->kernel_size))); 1230 } 1231 if (spapr->initrd_size) { 1232 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1233 spapr->initrd_size))); 1234 } 1235 } 1236 1237 /* NVDIMM devices */ 1238 if (mc->nvdimm_supported) { 1239 spapr_dt_persistent_memory(spapr, fdt); 1240 } 1241 1242 return fdt; 1243 } 1244 1245 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1246 { 1247 SpaprMachineState *spapr = opaque; 1248 1249 return (addr & 0x0fffffff) + spapr->kernel_addr; 1250 } 1251 1252 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1253 PowerPCCPU *cpu) 1254 { 1255 CPUPPCState *env = &cpu->env; 1256 1257 /* The TCG path should also be holding the BQL at this point */ 1258 g_assert(qemu_mutex_iothread_locked()); 1259 1260 if (msr_pr) { 1261 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1262 env->gpr[3] = H_PRIVILEGE; 1263 } else { 1264 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1265 } 1266 } 1267 1268 struct LPCRSyncState { 1269 target_ulong value; 1270 target_ulong mask; 1271 }; 1272 1273 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1274 { 1275 struct LPCRSyncState *s = arg.host_ptr; 1276 PowerPCCPU *cpu = POWERPC_CPU(cs); 1277 CPUPPCState *env = &cpu->env; 1278 target_ulong lpcr; 1279 1280 cpu_synchronize_state(cs); 1281 lpcr = env->spr[SPR_LPCR]; 1282 lpcr &= ~s->mask; 1283 lpcr |= s->value; 1284 ppc_store_lpcr(cpu, lpcr); 1285 } 1286 1287 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1288 { 1289 CPUState *cs; 1290 struct LPCRSyncState s = { 1291 .value = value, 1292 .mask = mask 1293 }; 1294 CPU_FOREACH(cs) { 1295 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1296 } 1297 } 1298 1299 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1300 { 1301 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1302 1303 /* Copy PATE1:GR into PATE0:HR */ 1304 entry->dw0 = spapr->patb_entry & PATE0_HR; 1305 entry->dw1 = spapr->patb_entry; 1306 } 1307 1308 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1309 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1310 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1311 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1312 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1313 1314 /* 1315 * Get the fd to access the kernel htab, re-opening it if necessary 1316 */ 1317 static int get_htab_fd(SpaprMachineState *spapr) 1318 { 1319 Error *local_err = NULL; 1320 1321 if (spapr->htab_fd >= 0) { 1322 return spapr->htab_fd; 1323 } 1324 1325 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1326 if (spapr->htab_fd < 0) { 1327 error_report_err(local_err); 1328 } 1329 1330 return spapr->htab_fd; 1331 } 1332 1333 void close_htab_fd(SpaprMachineState *spapr) 1334 { 1335 if (spapr->htab_fd >= 0) { 1336 close(spapr->htab_fd); 1337 } 1338 spapr->htab_fd = -1; 1339 } 1340 1341 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1342 { 1343 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1344 1345 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1346 } 1347 1348 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1349 { 1350 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1351 1352 assert(kvm_enabled()); 1353 1354 if (!spapr->htab) { 1355 return 0; 1356 } 1357 1358 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1359 } 1360 1361 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1362 hwaddr ptex, int n) 1363 { 1364 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1365 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1366 1367 if (!spapr->htab) { 1368 /* 1369 * HTAB is controlled by KVM. Fetch into temporary buffer 1370 */ 1371 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1372 kvmppc_read_hptes(hptes, ptex, n); 1373 return hptes; 1374 } 1375 1376 /* 1377 * HTAB is controlled by QEMU. Just point to the internally 1378 * accessible PTEG. 1379 */ 1380 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1381 } 1382 1383 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1384 const ppc_hash_pte64_t *hptes, 1385 hwaddr ptex, int n) 1386 { 1387 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1388 1389 if (!spapr->htab) { 1390 g_free((void *)hptes); 1391 } 1392 1393 /* Nothing to do for qemu managed HPT */ 1394 } 1395 1396 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1397 uint64_t pte0, uint64_t pte1) 1398 { 1399 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1400 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1401 1402 if (!spapr->htab) { 1403 kvmppc_write_hpte(ptex, pte0, pte1); 1404 } else { 1405 if (pte0 & HPTE64_V_VALID) { 1406 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1407 /* 1408 * When setting valid, we write PTE1 first. This ensures 1409 * proper synchronization with the reading code in 1410 * ppc_hash64_pteg_search() 1411 */ 1412 smp_wmb(); 1413 stq_p(spapr->htab + offset, pte0); 1414 } else { 1415 stq_p(spapr->htab + offset, pte0); 1416 /* 1417 * When clearing it we set PTE0 first. This ensures proper 1418 * synchronization with the reading code in 1419 * ppc_hash64_pteg_search() 1420 */ 1421 smp_wmb(); 1422 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1423 } 1424 } 1425 } 1426 1427 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1428 uint64_t pte1) 1429 { 1430 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1431 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1432 1433 if (!spapr->htab) { 1434 /* There should always be a hash table when this is called */ 1435 error_report("spapr_hpte_set_c called with no hash table !"); 1436 return; 1437 } 1438 1439 /* The HW performs a non-atomic byte update */ 1440 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1441 } 1442 1443 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1444 uint64_t pte1) 1445 { 1446 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1447 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1448 1449 if (!spapr->htab) { 1450 /* There should always be a hash table when this is called */ 1451 error_report("spapr_hpte_set_r called with no hash table !"); 1452 return; 1453 } 1454 1455 /* The HW performs a non-atomic byte update */ 1456 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1457 } 1458 1459 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1460 { 1461 int shift; 1462 1463 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1464 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1465 * that's much more than is needed for Linux guests */ 1466 shift = ctz64(pow2ceil(ramsize)) - 7; 1467 shift = MAX(shift, 18); /* Minimum architected size */ 1468 shift = MIN(shift, 46); /* Maximum architected size */ 1469 return shift; 1470 } 1471 1472 void spapr_free_hpt(SpaprMachineState *spapr) 1473 { 1474 g_free(spapr->htab); 1475 spapr->htab = NULL; 1476 spapr->htab_shift = 0; 1477 close_htab_fd(spapr); 1478 } 1479 1480 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1481 { 1482 ERRP_GUARD(); 1483 long rc; 1484 1485 /* Clean up any HPT info from a previous boot */ 1486 spapr_free_hpt(spapr); 1487 1488 rc = kvmppc_reset_htab(shift); 1489 1490 if (rc == -EOPNOTSUPP) { 1491 error_setg(errp, "HPT not supported in nested guests"); 1492 return -EOPNOTSUPP; 1493 } 1494 1495 if (rc < 0) { 1496 /* kernel-side HPT needed, but couldn't allocate one */ 1497 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1498 shift); 1499 error_append_hint(errp, "Try smaller maxmem?\n"); 1500 return -errno; 1501 } else if (rc > 0) { 1502 /* kernel-side HPT allocated */ 1503 if (rc != shift) { 1504 error_setg(errp, 1505 "Requested order %d HPT, but kernel allocated order %ld", 1506 shift, rc); 1507 error_append_hint(errp, "Try smaller maxmem?\n"); 1508 return -ENOSPC; 1509 } 1510 1511 spapr->htab_shift = shift; 1512 spapr->htab = NULL; 1513 } else { 1514 /* kernel-side HPT not needed, allocate in userspace instead */ 1515 size_t size = 1ULL << shift; 1516 int i; 1517 1518 spapr->htab = qemu_memalign(size, size); 1519 memset(spapr->htab, 0, size); 1520 spapr->htab_shift = shift; 1521 1522 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1523 DIRTY_HPTE(HPTE(spapr->htab, i)); 1524 } 1525 } 1526 /* We're setting up a hash table, so that means we're not radix */ 1527 spapr->patb_entry = 0; 1528 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1529 return 0; 1530 } 1531 1532 void spapr_setup_hpt(SpaprMachineState *spapr) 1533 { 1534 int hpt_shift; 1535 1536 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1537 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1538 } else { 1539 uint64_t current_ram_size; 1540 1541 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1542 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1543 } 1544 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1545 1546 if (kvm_enabled()) { 1547 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1548 1549 /* Check our RMA fits in the possible VRMA */ 1550 if (vrma_limit < spapr->rma_size) { 1551 error_report("Unable to create %" HWADDR_PRIu 1552 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1553 spapr->rma_size / MiB, vrma_limit / MiB); 1554 exit(EXIT_FAILURE); 1555 } 1556 } 1557 } 1558 1559 void spapr_check_mmu_mode(bool guest_radix) 1560 { 1561 if (guest_radix) { 1562 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1563 error_report("Guest requested unavailable MMU mode (radix)."); 1564 exit(EXIT_FAILURE); 1565 } 1566 } else { 1567 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1568 && !kvmppc_has_cap_mmu_hash_v3()) { 1569 error_report("Guest requested unavailable MMU mode (hash)."); 1570 exit(EXIT_FAILURE); 1571 } 1572 } 1573 } 1574 1575 static void spapr_machine_reset(MachineState *machine) 1576 { 1577 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1578 PowerPCCPU *first_ppc_cpu; 1579 hwaddr fdt_addr; 1580 void *fdt; 1581 int rc; 1582 1583 pef_kvm_reset(machine->cgs, &error_fatal); 1584 spapr_caps_apply(spapr); 1585 1586 first_ppc_cpu = POWERPC_CPU(first_cpu); 1587 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1588 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1589 spapr->max_compat_pvr)) { 1590 /* 1591 * If using KVM with radix mode available, VCPUs can be started 1592 * without a HPT because KVM will start them in radix mode. 1593 * Set the GR bit in PATE so that we know there is no HPT. 1594 */ 1595 spapr->patb_entry = PATE1_GR; 1596 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1597 } else { 1598 spapr_setup_hpt(spapr); 1599 } 1600 1601 qemu_devices_reset(); 1602 1603 spapr_ovec_cleanup(spapr->ov5_cas); 1604 spapr->ov5_cas = spapr_ovec_new(); 1605 1606 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1607 1608 /* 1609 * This is fixing some of the default configuration of the XIVE 1610 * devices. To be called after the reset of the machine devices. 1611 */ 1612 spapr_irq_reset(spapr, &error_fatal); 1613 1614 /* 1615 * There is no CAS under qtest. Simulate one to please the code that 1616 * depends on spapr->ov5_cas. This is especially needed to test device 1617 * unplug, so we do that before resetting the DRCs. 1618 */ 1619 if (qtest_enabled()) { 1620 spapr_ovec_cleanup(spapr->ov5_cas); 1621 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1622 } 1623 1624 /* DRC reset may cause a device to be unplugged. This will cause troubles 1625 * if this device is used by another device (eg, a running vhost backend 1626 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1627 * situations, we reset DRCs after all devices have been reset. 1628 */ 1629 spapr_drc_reset_all(spapr); 1630 1631 spapr_clear_pending_events(spapr); 1632 1633 /* 1634 * We place the device tree just below either the top of the RMA, 1635 * or just below 2GB, whichever is lower, so that it can be 1636 * processed with 32-bit real mode code if necessary 1637 */ 1638 fdt_addr = MIN(spapr->rma_size, FDT_MAX_ADDR) - FDT_MAX_SIZE; 1639 1640 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1641 1642 rc = fdt_pack(fdt); 1643 1644 /* Should only fail if we've built a corrupted tree */ 1645 assert(rc == 0); 1646 1647 /* Load the fdt */ 1648 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1649 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1650 g_free(spapr->fdt_blob); 1651 spapr->fdt_size = fdt_totalsize(fdt); 1652 spapr->fdt_initial_size = spapr->fdt_size; 1653 spapr->fdt_blob = fdt; 1654 1655 /* Set up the entry state */ 1656 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); 1657 first_ppc_cpu->env.gpr[5] = 0; 1658 1659 spapr->fwnmi_system_reset_addr = -1; 1660 spapr->fwnmi_machine_check_addr = -1; 1661 spapr->fwnmi_machine_check_interlock = -1; 1662 1663 /* Signal all vCPUs waiting on this condition */ 1664 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1665 1666 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1667 } 1668 1669 static void spapr_create_nvram(SpaprMachineState *spapr) 1670 { 1671 DeviceState *dev = qdev_new("spapr-nvram"); 1672 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1673 1674 if (dinfo) { 1675 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1676 &error_fatal); 1677 } 1678 1679 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1680 1681 spapr->nvram = (struct SpaprNvram *)dev; 1682 } 1683 1684 static void spapr_rtc_create(SpaprMachineState *spapr) 1685 { 1686 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1687 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1688 &error_fatal, NULL); 1689 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1690 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1691 "date"); 1692 } 1693 1694 /* Returns whether we want to use VGA or not */ 1695 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1696 { 1697 switch (vga_interface_type) { 1698 case VGA_NONE: 1699 return false; 1700 case VGA_DEVICE: 1701 return true; 1702 case VGA_STD: 1703 case VGA_VIRTIO: 1704 case VGA_CIRRUS: 1705 return pci_vga_init(pci_bus) != NULL; 1706 default: 1707 error_setg(errp, 1708 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1709 return false; 1710 } 1711 } 1712 1713 static int spapr_pre_load(void *opaque) 1714 { 1715 int rc; 1716 1717 rc = spapr_caps_pre_load(opaque); 1718 if (rc) { 1719 return rc; 1720 } 1721 1722 return 0; 1723 } 1724 1725 static int spapr_post_load(void *opaque, int version_id) 1726 { 1727 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1728 int err = 0; 1729 1730 err = spapr_caps_post_migration(spapr); 1731 if (err) { 1732 return err; 1733 } 1734 1735 /* 1736 * In earlier versions, there was no separate qdev for the PAPR 1737 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1738 * So when migrating from those versions, poke the incoming offset 1739 * value into the RTC device 1740 */ 1741 if (version_id < 3) { 1742 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1743 if (err) { 1744 return err; 1745 } 1746 } 1747 1748 if (kvm_enabled() && spapr->patb_entry) { 1749 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1750 bool radix = !!(spapr->patb_entry & PATE1_GR); 1751 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1752 1753 /* 1754 * Update LPCR:HR and UPRT as they may not be set properly in 1755 * the stream 1756 */ 1757 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1758 LPCR_HR | LPCR_UPRT); 1759 1760 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1761 if (err) { 1762 error_report("Process table config unsupported by the host"); 1763 return -EINVAL; 1764 } 1765 } 1766 1767 err = spapr_irq_post_load(spapr, version_id); 1768 if (err) { 1769 return err; 1770 } 1771 1772 return err; 1773 } 1774 1775 static int spapr_pre_save(void *opaque) 1776 { 1777 int rc; 1778 1779 rc = spapr_caps_pre_save(opaque); 1780 if (rc) { 1781 return rc; 1782 } 1783 1784 return 0; 1785 } 1786 1787 static bool version_before_3(void *opaque, int version_id) 1788 { 1789 return version_id < 3; 1790 } 1791 1792 static bool spapr_pending_events_needed(void *opaque) 1793 { 1794 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1795 return !QTAILQ_EMPTY(&spapr->pending_events); 1796 } 1797 1798 static const VMStateDescription vmstate_spapr_event_entry = { 1799 .name = "spapr_event_log_entry", 1800 .version_id = 1, 1801 .minimum_version_id = 1, 1802 .fields = (VMStateField[]) { 1803 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1804 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1805 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1806 NULL, extended_length), 1807 VMSTATE_END_OF_LIST() 1808 }, 1809 }; 1810 1811 static const VMStateDescription vmstate_spapr_pending_events = { 1812 .name = "spapr_pending_events", 1813 .version_id = 1, 1814 .minimum_version_id = 1, 1815 .needed = spapr_pending_events_needed, 1816 .fields = (VMStateField[]) { 1817 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1818 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1819 VMSTATE_END_OF_LIST() 1820 }, 1821 }; 1822 1823 static bool spapr_ov5_cas_needed(void *opaque) 1824 { 1825 SpaprMachineState *spapr = opaque; 1826 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1827 bool cas_needed; 1828 1829 /* Prior to the introduction of SpaprOptionVector, we had two option 1830 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1831 * Both of these options encode machine topology into the device-tree 1832 * in such a way that the now-booted OS should still be able to interact 1833 * appropriately with QEMU regardless of what options were actually 1834 * negotiatied on the source side. 1835 * 1836 * As such, we can avoid migrating the CAS-negotiated options if these 1837 * are the only options available on the current machine/platform. 1838 * Since these are the only options available for pseries-2.7 and 1839 * earlier, this allows us to maintain old->new/new->old migration 1840 * compatibility. 1841 * 1842 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1843 * via default pseries-2.8 machines and explicit command-line parameters. 1844 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1845 * of the actual CAS-negotiated values to continue working properly. For 1846 * example, availability of memory unplug depends on knowing whether 1847 * OV5_HP_EVT was negotiated via CAS. 1848 * 1849 * Thus, for any cases where the set of available CAS-negotiatable 1850 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1851 * include the CAS-negotiated options in the migration stream, unless 1852 * if they affect boot time behaviour only. 1853 */ 1854 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1855 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1856 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1857 1858 /* We need extra information if we have any bits outside the mask 1859 * defined above */ 1860 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1861 1862 spapr_ovec_cleanup(ov5_mask); 1863 1864 return cas_needed; 1865 } 1866 1867 static const VMStateDescription vmstate_spapr_ov5_cas = { 1868 .name = "spapr_option_vector_ov5_cas", 1869 .version_id = 1, 1870 .minimum_version_id = 1, 1871 .needed = spapr_ov5_cas_needed, 1872 .fields = (VMStateField[]) { 1873 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1874 vmstate_spapr_ovec, SpaprOptionVector), 1875 VMSTATE_END_OF_LIST() 1876 }, 1877 }; 1878 1879 static bool spapr_patb_entry_needed(void *opaque) 1880 { 1881 SpaprMachineState *spapr = opaque; 1882 1883 return !!spapr->patb_entry; 1884 } 1885 1886 static const VMStateDescription vmstate_spapr_patb_entry = { 1887 .name = "spapr_patb_entry", 1888 .version_id = 1, 1889 .minimum_version_id = 1, 1890 .needed = spapr_patb_entry_needed, 1891 .fields = (VMStateField[]) { 1892 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1893 VMSTATE_END_OF_LIST() 1894 }, 1895 }; 1896 1897 static bool spapr_irq_map_needed(void *opaque) 1898 { 1899 SpaprMachineState *spapr = opaque; 1900 1901 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1902 } 1903 1904 static const VMStateDescription vmstate_spapr_irq_map = { 1905 .name = "spapr_irq_map", 1906 .version_id = 1, 1907 .minimum_version_id = 1, 1908 .needed = spapr_irq_map_needed, 1909 .fields = (VMStateField[]) { 1910 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1911 VMSTATE_END_OF_LIST() 1912 }, 1913 }; 1914 1915 static bool spapr_dtb_needed(void *opaque) 1916 { 1917 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1918 1919 return smc->update_dt_enabled; 1920 } 1921 1922 static int spapr_dtb_pre_load(void *opaque) 1923 { 1924 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1925 1926 g_free(spapr->fdt_blob); 1927 spapr->fdt_blob = NULL; 1928 spapr->fdt_size = 0; 1929 1930 return 0; 1931 } 1932 1933 static const VMStateDescription vmstate_spapr_dtb = { 1934 .name = "spapr_dtb", 1935 .version_id = 1, 1936 .minimum_version_id = 1, 1937 .needed = spapr_dtb_needed, 1938 .pre_load = spapr_dtb_pre_load, 1939 .fields = (VMStateField[]) { 1940 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1941 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1942 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1943 fdt_size), 1944 VMSTATE_END_OF_LIST() 1945 }, 1946 }; 1947 1948 static bool spapr_fwnmi_needed(void *opaque) 1949 { 1950 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1951 1952 return spapr->fwnmi_machine_check_addr != -1; 1953 } 1954 1955 static int spapr_fwnmi_pre_save(void *opaque) 1956 { 1957 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1958 1959 /* 1960 * Check if machine check handling is in progress and print a 1961 * warning message. 1962 */ 1963 if (spapr->fwnmi_machine_check_interlock != -1) { 1964 warn_report("A machine check is being handled during migration. The" 1965 "handler may run and log hardware error on the destination"); 1966 } 1967 1968 return 0; 1969 } 1970 1971 static const VMStateDescription vmstate_spapr_fwnmi = { 1972 .name = "spapr_fwnmi", 1973 .version_id = 1, 1974 .minimum_version_id = 1, 1975 .needed = spapr_fwnmi_needed, 1976 .pre_save = spapr_fwnmi_pre_save, 1977 .fields = (VMStateField[]) { 1978 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 1979 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 1980 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 1981 VMSTATE_END_OF_LIST() 1982 }, 1983 }; 1984 1985 static const VMStateDescription vmstate_spapr = { 1986 .name = "spapr", 1987 .version_id = 3, 1988 .minimum_version_id = 1, 1989 .pre_load = spapr_pre_load, 1990 .post_load = spapr_post_load, 1991 .pre_save = spapr_pre_save, 1992 .fields = (VMStateField[]) { 1993 /* used to be @next_irq */ 1994 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1995 1996 /* RTC offset */ 1997 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 1998 1999 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2000 VMSTATE_END_OF_LIST() 2001 }, 2002 .subsections = (const VMStateDescription*[]) { 2003 &vmstate_spapr_ov5_cas, 2004 &vmstate_spapr_patb_entry, 2005 &vmstate_spapr_pending_events, 2006 &vmstate_spapr_cap_htm, 2007 &vmstate_spapr_cap_vsx, 2008 &vmstate_spapr_cap_dfp, 2009 &vmstate_spapr_cap_cfpc, 2010 &vmstate_spapr_cap_sbbc, 2011 &vmstate_spapr_cap_ibs, 2012 &vmstate_spapr_cap_hpt_maxpagesize, 2013 &vmstate_spapr_irq_map, 2014 &vmstate_spapr_cap_nested_kvm_hv, 2015 &vmstate_spapr_dtb, 2016 &vmstate_spapr_cap_large_decr, 2017 &vmstate_spapr_cap_ccf_assist, 2018 &vmstate_spapr_cap_fwnmi, 2019 &vmstate_spapr_fwnmi, 2020 NULL 2021 } 2022 }; 2023 2024 static int htab_save_setup(QEMUFile *f, void *opaque) 2025 { 2026 SpaprMachineState *spapr = opaque; 2027 2028 /* "Iteration" header */ 2029 if (!spapr->htab_shift) { 2030 qemu_put_be32(f, -1); 2031 } else { 2032 qemu_put_be32(f, spapr->htab_shift); 2033 } 2034 2035 if (spapr->htab) { 2036 spapr->htab_save_index = 0; 2037 spapr->htab_first_pass = true; 2038 } else { 2039 if (spapr->htab_shift) { 2040 assert(kvm_enabled()); 2041 } 2042 } 2043 2044 2045 return 0; 2046 } 2047 2048 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2049 int chunkstart, int n_valid, int n_invalid) 2050 { 2051 qemu_put_be32(f, chunkstart); 2052 qemu_put_be16(f, n_valid); 2053 qemu_put_be16(f, n_invalid); 2054 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2055 HASH_PTE_SIZE_64 * n_valid); 2056 } 2057 2058 static void htab_save_end_marker(QEMUFile *f) 2059 { 2060 qemu_put_be32(f, 0); 2061 qemu_put_be16(f, 0); 2062 qemu_put_be16(f, 0); 2063 } 2064 2065 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2066 int64_t max_ns) 2067 { 2068 bool has_timeout = max_ns != -1; 2069 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2070 int index = spapr->htab_save_index; 2071 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2072 2073 assert(spapr->htab_first_pass); 2074 2075 do { 2076 int chunkstart; 2077 2078 /* Consume invalid HPTEs */ 2079 while ((index < htabslots) 2080 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2081 CLEAN_HPTE(HPTE(spapr->htab, index)); 2082 index++; 2083 } 2084 2085 /* Consume valid HPTEs */ 2086 chunkstart = index; 2087 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2088 && HPTE_VALID(HPTE(spapr->htab, index))) { 2089 CLEAN_HPTE(HPTE(spapr->htab, index)); 2090 index++; 2091 } 2092 2093 if (index > chunkstart) { 2094 int n_valid = index - chunkstart; 2095 2096 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2097 2098 if (has_timeout && 2099 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2100 break; 2101 } 2102 } 2103 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2104 2105 if (index >= htabslots) { 2106 assert(index == htabslots); 2107 index = 0; 2108 spapr->htab_first_pass = false; 2109 } 2110 spapr->htab_save_index = index; 2111 } 2112 2113 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2114 int64_t max_ns) 2115 { 2116 bool final = max_ns < 0; 2117 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2118 int examined = 0, sent = 0; 2119 int index = spapr->htab_save_index; 2120 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2121 2122 assert(!spapr->htab_first_pass); 2123 2124 do { 2125 int chunkstart, invalidstart; 2126 2127 /* Consume non-dirty HPTEs */ 2128 while ((index < htabslots) 2129 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2130 index++; 2131 examined++; 2132 } 2133 2134 chunkstart = index; 2135 /* Consume valid dirty HPTEs */ 2136 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2137 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2138 && HPTE_VALID(HPTE(spapr->htab, index))) { 2139 CLEAN_HPTE(HPTE(spapr->htab, index)); 2140 index++; 2141 examined++; 2142 } 2143 2144 invalidstart = index; 2145 /* Consume invalid dirty HPTEs */ 2146 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2147 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2148 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2149 CLEAN_HPTE(HPTE(spapr->htab, index)); 2150 index++; 2151 examined++; 2152 } 2153 2154 if (index > chunkstart) { 2155 int n_valid = invalidstart - chunkstart; 2156 int n_invalid = index - invalidstart; 2157 2158 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2159 sent += index - chunkstart; 2160 2161 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2162 break; 2163 } 2164 } 2165 2166 if (examined >= htabslots) { 2167 break; 2168 } 2169 2170 if (index >= htabslots) { 2171 assert(index == htabslots); 2172 index = 0; 2173 } 2174 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2175 2176 if (index >= htabslots) { 2177 assert(index == htabslots); 2178 index = 0; 2179 } 2180 2181 spapr->htab_save_index = index; 2182 2183 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2184 } 2185 2186 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2187 #define MAX_KVM_BUF_SIZE 2048 2188 2189 static int htab_save_iterate(QEMUFile *f, void *opaque) 2190 { 2191 SpaprMachineState *spapr = opaque; 2192 int fd; 2193 int rc = 0; 2194 2195 /* Iteration header */ 2196 if (!spapr->htab_shift) { 2197 qemu_put_be32(f, -1); 2198 return 1; 2199 } else { 2200 qemu_put_be32(f, 0); 2201 } 2202 2203 if (!spapr->htab) { 2204 assert(kvm_enabled()); 2205 2206 fd = get_htab_fd(spapr); 2207 if (fd < 0) { 2208 return fd; 2209 } 2210 2211 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2212 if (rc < 0) { 2213 return rc; 2214 } 2215 } else if (spapr->htab_first_pass) { 2216 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2217 } else { 2218 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2219 } 2220 2221 htab_save_end_marker(f); 2222 2223 return rc; 2224 } 2225 2226 static int htab_save_complete(QEMUFile *f, void *opaque) 2227 { 2228 SpaprMachineState *spapr = opaque; 2229 int fd; 2230 2231 /* Iteration header */ 2232 if (!spapr->htab_shift) { 2233 qemu_put_be32(f, -1); 2234 return 0; 2235 } else { 2236 qemu_put_be32(f, 0); 2237 } 2238 2239 if (!spapr->htab) { 2240 int rc; 2241 2242 assert(kvm_enabled()); 2243 2244 fd = get_htab_fd(spapr); 2245 if (fd < 0) { 2246 return fd; 2247 } 2248 2249 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2250 if (rc < 0) { 2251 return rc; 2252 } 2253 } else { 2254 if (spapr->htab_first_pass) { 2255 htab_save_first_pass(f, spapr, -1); 2256 } 2257 htab_save_later_pass(f, spapr, -1); 2258 } 2259 2260 /* End marker */ 2261 htab_save_end_marker(f); 2262 2263 return 0; 2264 } 2265 2266 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2267 { 2268 SpaprMachineState *spapr = opaque; 2269 uint32_t section_hdr; 2270 int fd = -1; 2271 Error *local_err = NULL; 2272 2273 if (version_id < 1 || version_id > 1) { 2274 error_report("htab_load() bad version"); 2275 return -EINVAL; 2276 } 2277 2278 section_hdr = qemu_get_be32(f); 2279 2280 if (section_hdr == -1) { 2281 spapr_free_hpt(spapr); 2282 return 0; 2283 } 2284 2285 if (section_hdr) { 2286 int ret; 2287 2288 /* First section gives the htab size */ 2289 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2290 if (ret < 0) { 2291 error_report_err(local_err); 2292 return ret; 2293 } 2294 return 0; 2295 } 2296 2297 if (!spapr->htab) { 2298 assert(kvm_enabled()); 2299 2300 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2301 if (fd < 0) { 2302 error_report_err(local_err); 2303 return fd; 2304 } 2305 } 2306 2307 while (true) { 2308 uint32_t index; 2309 uint16_t n_valid, n_invalid; 2310 2311 index = qemu_get_be32(f); 2312 n_valid = qemu_get_be16(f); 2313 n_invalid = qemu_get_be16(f); 2314 2315 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2316 /* End of Stream */ 2317 break; 2318 } 2319 2320 if ((index + n_valid + n_invalid) > 2321 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2322 /* Bad index in stream */ 2323 error_report( 2324 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2325 index, n_valid, n_invalid, spapr->htab_shift); 2326 return -EINVAL; 2327 } 2328 2329 if (spapr->htab) { 2330 if (n_valid) { 2331 qemu_get_buffer(f, HPTE(spapr->htab, index), 2332 HASH_PTE_SIZE_64 * n_valid); 2333 } 2334 if (n_invalid) { 2335 memset(HPTE(spapr->htab, index + n_valid), 0, 2336 HASH_PTE_SIZE_64 * n_invalid); 2337 } 2338 } else { 2339 int rc; 2340 2341 assert(fd >= 0); 2342 2343 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2344 &local_err); 2345 if (rc < 0) { 2346 error_report_err(local_err); 2347 return rc; 2348 } 2349 } 2350 } 2351 2352 if (!spapr->htab) { 2353 assert(fd >= 0); 2354 close(fd); 2355 } 2356 2357 return 0; 2358 } 2359 2360 static void htab_save_cleanup(void *opaque) 2361 { 2362 SpaprMachineState *spapr = opaque; 2363 2364 close_htab_fd(spapr); 2365 } 2366 2367 static SaveVMHandlers savevm_htab_handlers = { 2368 .save_setup = htab_save_setup, 2369 .save_live_iterate = htab_save_iterate, 2370 .save_live_complete_precopy = htab_save_complete, 2371 .save_cleanup = htab_save_cleanup, 2372 .load_state = htab_load, 2373 }; 2374 2375 static void spapr_boot_set(void *opaque, const char *boot_device, 2376 Error **errp) 2377 { 2378 MachineState *machine = MACHINE(opaque); 2379 machine->boot_order = g_strdup(boot_device); 2380 } 2381 2382 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2383 { 2384 MachineState *machine = MACHINE(spapr); 2385 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2386 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2387 int i; 2388 2389 for (i = 0; i < nr_lmbs; i++) { 2390 uint64_t addr; 2391 2392 addr = i * lmb_size + machine->device_memory->base; 2393 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2394 addr / lmb_size); 2395 } 2396 } 2397 2398 /* 2399 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2400 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2401 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2402 */ 2403 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2404 { 2405 int i; 2406 2407 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2408 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2409 " is not aligned to %" PRIu64 " MiB", 2410 machine->ram_size, 2411 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2412 return; 2413 } 2414 2415 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2416 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2417 " is not aligned to %" PRIu64 " MiB", 2418 machine->ram_size, 2419 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2420 return; 2421 } 2422 2423 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2424 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2425 error_setg(errp, 2426 "Node %d memory size 0x%" PRIx64 2427 " is not aligned to %" PRIu64 " MiB", 2428 i, machine->numa_state->nodes[i].node_mem, 2429 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2430 return; 2431 } 2432 } 2433 } 2434 2435 /* find cpu slot in machine->possible_cpus by core_id */ 2436 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2437 { 2438 int index = id / ms->smp.threads; 2439 2440 if (index >= ms->possible_cpus->len) { 2441 return NULL; 2442 } 2443 if (idx) { 2444 *idx = index; 2445 } 2446 return &ms->possible_cpus->cpus[index]; 2447 } 2448 2449 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2450 { 2451 MachineState *ms = MACHINE(spapr); 2452 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2453 Error *local_err = NULL; 2454 bool vsmt_user = !!spapr->vsmt; 2455 int kvm_smt = kvmppc_smt_threads(); 2456 int ret; 2457 unsigned int smp_threads = ms->smp.threads; 2458 2459 if (!kvm_enabled() && (smp_threads > 1)) { 2460 error_setg(errp, "TCG cannot support more than 1 thread/core " 2461 "on a pseries machine"); 2462 return; 2463 } 2464 if (!is_power_of_2(smp_threads)) { 2465 error_setg(errp, "Cannot support %d threads/core on a pseries " 2466 "machine because it must be a power of 2", smp_threads); 2467 return; 2468 } 2469 2470 /* Detemine the VSMT mode to use: */ 2471 if (vsmt_user) { 2472 if (spapr->vsmt < smp_threads) { 2473 error_setg(errp, "Cannot support VSMT mode %d" 2474 " because it must be >= threads/core (%d)", 2475 spapr->vsmt, smp_threads); 2476 return; 2477 } 2478 /* In this case, spapr->vsmt has been set by the command line */ 2479 } else if (!smc->smp_threads_vsmt) { 2480 /* 2481 * Default VSMT value is tricky, because we need it to be as 2482 * consistent as possible (for migration), but this requires 2483 * changing it for at least some existing cases. We pick 8 as 2484 * the value that we'd get with KVM on POWER8, the 2485 * overwhelmingly common case in production systems. 2486 */ 2487 spapr->vsmt = MAX(8, smp_threads); 2488 } else { 2489 spapr->vsmt = smp_threads; 2490 } 2491 2492 /* KVM: If necessary, set the SMT mode: */ 2493 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2494 ret = kvmppc_set_smt_threads(spapr->vsmt); 2495 if (ret) { 2496 /* Looks like KVM isn't able to change VSMT mode */ 2497 error_setg(&local_err, 2498 "Failed to set KVM's VSMT mode to %d (errno %d)", 2499 spapr->vsmt, ret); 2500 /* We can live with that if the default one is big enough 2501 * for the number of threads, and a submultiple of the one 2502 * we want. In this case we'll waste some vcpu ids, but 2503 * behaviour will be correct */ 2504 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2505 warn_report_err(local_err); 2506 } else { 2507 if (!vsmt_user) { 2508 error_append_hint(&local_err, 2509 "On PPC, a VM with %d threads/core" 2510 " on a host with %d threads/core" 2511 " requires the use of VSMT mode %d.\n", 2512 smp_threads, kvm_smt, spapr->vsmt); 2513 } 2514 kvmppc_error_append_smt_possible_hint(&local_err); 2515 error_propagate(errp, local_err); 2516 } 2517 } 2518 } 2519 /* else TCG: nothing to do currently */ 2520 } 2521 2522 static void spapr_init_cpus(SpaprMachineState *spapr) 2523 { 2524 MachineState *machine = MACHINE(spapr); 2525 MachineClass *mc = MACHINE_GET_CLASS(machine); 2526 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2527 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2528 const CPUArchIdList *possible_cpus; 2529 unsigned int smp_cpus = machine->smp.cpus; 2530 unsigned int smp_threads = machine->smp.threads; 2531 unsigned int max_cpus = machine->smp.max_cpus; 2532 int boot_cores_nr = smp_cpus / smp_threads; 2533 int i; 2534 2535 possible_cpus = mc->possible_cpu_arch_ids(machine); 2536 if (mc->has_hotpluggable_cpus) { 2537 if (smp_cpus % smp_threads) { 2538 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2539 smp_cpus, smp_threads); 2540 exit(1); 2541 } 2542 if (max_cpus % smp_threads) { 2543 error_report("max_cpus (%u) must be multiple of threads (%u)", 2544 max_cpus, smp_threads); 2545 exit(1); 2546 } 2547 } else { 2548 if (max_cpus != smp_cpus) { 2549 error_report("This machine version does not support CPU hotplug"); 2550 exit(1); 2551 } 2552 boot_cores_nr = possible_cpus->len; 2553 } 2554 2555 if (smc->pre_2_10_has_unused_icps) { 2556 int i; 2557 2558 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2559 /* Dummy entries get deregistered when real ICPState objects 2560 * are registered during CPU core hotplug. 2561 */ 2562 pre_2_10_vmstate_register_dummy_icp(i); 2563 } 2564 } 2565 2566 for (i = 0; i < possible_cpus->len; i++) { 2567 int core_id = i * smp_threads; 2568 2569 if (mc->has_hotpluggable_cpus) { 2570 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2571 spapr_vcpu_id(spapr, core_id)); 2572 } 2573 2574 if (i < boot_cores_nr) { 2575 Object *core = object_new(type); 2576 int nr_threads = smp_threads; 2577 2578 /* Handle the partially filled core for older machine types */ 2579 if ((i + 1) * smp_threads >= smp_cpus) { 2580 nr_threads = smp_cpus - i * smp_threads; 2581 } 2582 2583 object_property_set_int(core, "nr-threads", nr_threads, 2584 &error_fatal); 2585 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2586 &error_fatal); 2587 qdev_realize(DEVICE(core), NULL, &error_fatal); 2588 2589 object_unref(core); 2590 } 2591 } 2592 } 2593 2594 static PCIHostState *spapr_create_default_phb(void) 2595 { 2596 DeviceState *dev; 2597 2598 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2599 qdev_prop_set_uint32(dev, "index", 0); 2600 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2601 2602 return PCI_HOST_BRIDGE(dev); 2603 } 2604 2605 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2606 { 2607 MachineState *machine = MACHINE(spapr); 2608 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2609 hwaddr rma_size = machine->ram_size; 2610 hwaddr node0_size = spapr_node0_size(machine); 2611 2612 /* RMA has to fit in the first NUMA node */ 2613 rma_size = MIN(rma_size, node0_size); 2614 2615 /* 2616 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2617 * never exceed that 2618 */ 2619 rma_size = MIN(rma_size, 1 * TiB); 2620 2621 /* 2622 * Clamp the RMA size based on machine type. This is for 2623 * migration compatibility with older qemu versions, which limited 2624 * the RMA size for complicated and mostly bad reasons. 2625 */ 2626 if (smc->rma_limit) { 2627 rma_size = MIN(rma_size, smc->rma_limit); 2628 } 2629 2630 if (rma_size < MIN_RMA_SLOF) { 2631 error_setg(errp, 2632 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2633 "ldMiB guest RMA (Real Mode Area memory)", 2634 MIN_RMA_SLOF / MiB); 2635 return 0; 2636 } 2637 2638 return rma_size; 2639 } 2640 2641 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2642 { 2643 MachineState *machine = MACHINE(spapr); 2644 int i; 2645 2646 for (i = 0; i < machine->ram_slots; i++) { 2647 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2648 } 2649 } 2650 2651 /* pSeries LPAR / sPAPR hardware init */ 2652 static void spapr_machine_init(MachineState *machine) 2653 { 2654 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2655 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2656 MachineClass *mc = MACHINE_GET_CLASS(machine); 2657 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 2658 const char *kernel_filename = machine->kernel_filename; 2659 const char *initrd_filename = machine->initrd_filename; 2660 PCIHostState *phb; 2661 int i; 2662 MemoryRegion *sysmem = get_system_memory(); 2663 long load_limit, fw_size; 2664 char *filename; 2665 Error *resize_hpt_err = NULL; 2666 2667 /* 2668 * if Secure VM (PEF) support is configured, then initialize it 2669 */ 2670 pef_kvm_init(machine->cgs, &error_fatal); 2671 2672 msi_nonbroken = true; 2673 2674 QLIST_INIT(&spapr->phbs); 2675 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2676 2677 /* Determine capabilities to run with */ 2678 spapr_caps_init(spapr); 2679 2680 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2681 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2682 /* 2683 * If the user explicitly requested a mode we should either 2684 * supply it, or fail completely (which we do below). But if 2685 * it's not set explicitly, we reset our mode to something 2686 * that works 2687 */ 2688 if (resize_hpt_err) { 2689 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2690 error_free(resize_hpt_err); 2691 resize_hpt_err = NULL; 2692 } else { 2693 spapr->resize_hpt = smc->resize_hpt_default; 2694 } 2695 } 2696 2697 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2698 2699 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2700 /* 2701 * User requested HPT resize, but this host can't supply it. Bail out 2702 */ 2703 error_report_err(resize_hpt_err); 2704 exit(1); 2705 } 2706 error_free(resize_hpt_err); 2707 2708 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2709 2710 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2711 load_limit = MIN(spapr->rma_size, FDT_MAX_ADDR) - FW_OVERHEAD; 2712 2713 /* 2714 * VSMT must be set in order to be able to compute VCPU ids, ie to 2715 * call spapr_max_server_number() or spapr_vcpu_id(). 2716 */ 2717 spapr_set_vsmt_mode(spapr, &error_fatal); 2718 2719 /* Set up Interrupt Controller before we create the VCPUs */ 2720 spapr_irq_init(spapr, &error_fatal); 2721 2722 /* Set up containers for ibm,client-architecture-support negotiated options 2723 */ 2724 spapr->ov5 = spapr_ovec_new(); 2725 spapr->ov5_cas = spapr_ovec_new(); 2726 2727 if (smc->dr_lmb_enabled) { 2728 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2729 spapr_validate_node_memory(machine, &error_fatal); 2730 } 2731 2732 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2733 2734 /* advertise support for dedicated HP event source to guests */ 2735 if (spapr->use_hotplug_event_source) { 2736 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2737 } 2738 2739 /* advertise support for HPT resizing */ 2740 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2741 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2742 } 2743 2744 /* advertise support for ibm,dyamic-memory-v2 */ 2745 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2746 2747 /* advertise XIVE on POWER9 machines */ 2748 if (spapr->irq->xive) { 2749 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2750 } 2751 2752 /* init CPUs */ 2753 spapr_init_cpus(spapr); 2754 2755 /* 2756 * check we don't have a memory-less/cpu-less NUMA node 2757 * Firmware relies on the existing memory/cpu topology to provide the 2758 * NUMA topology to the kernel. 2759 * And the linux kernel needs to know the NUMA topology at start 2760 * to be able to hotplug CPUs later. 2761 */ 2762 if (machine->numa_state->num_nodes) { 2763 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2764 /* check for memory-less node */ 2765 if (machine->numa_state->nodes[i].node_mem == 0) { 2766 CPUState *cs; 2767 int found = 0; 2768 /* check for cpu-less node */ 2769 CPU_FOREACH(cs) { 2770 PowerPCCPU *cpu = POWERPC_CPU(cs); 2771 if (cpu->node_id == i) { 2772 found = 1; 2773 break; 2774 } 2775 } 2776 /* memory-less and cpu-less node */ 2777 if (!found) { 2778 error_report( 2779 "Memory-less/cpu-less nodes are not supported (node %d)", 2780 i); 2781 exit(1); 2782 } 2783 } 2784 } 2785 2786 } 2787 2788 spapr->gpu_numa_id = spapr_numa_initial_nvgpu_numa_id(machine); 2789 2790 /* Init numa_assoc_array */ 2791 spapr_numa_associativity_init(spapr, machine); 2792 2793 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2794 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2795 spapr->max_compat_pvr)) { 2796 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2797 /* KVM and TCG always allow GTSE with radix... */ 2798 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2799 } 2800 /* ... but not with hash (currently). */ 2801 2802 if (kvm_enabled()) { 2803 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2804 kvmppc_enable_logical_ci_hcalls(); 2805 kvmppc_enable_set_mode_hcall(); 2806 2807 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2808 kvmppc_enable_clear_ref_mod_hcalls(); 2809 2810 /* Enable H_PAGE_INIT */ 2811 kvmppc_enable_h_page_init(); 2812 } 2813 2814 /* map RAM */ 2815 memory_region_add_subregion(sysmem, 0, machine->ram); 2816 2817 /* always allocate the device memory information */ 2818 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2819 2820 /* initialize hotplug memory address space */ 2821 if (machine->ram_size < machine->maxram_size) { 2822 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2823 /* 2824 * Limit the number of hotpluggable memory slots to half the number 2825 * slots that KVM supports, leaving the other half for PCI and other 2826 * devices. However ensure that number of slots doesn't drop below 32. 2827 */ 2828 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2829 SPAPR_MAX_RAM_SLOTS; 2830 2831 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2832 max_memslots = SPAPR_MAX_RAM_SLOTS; 2833 } 2834 if (machine->ram_slots > max_memslots) { 2835 error_report("Specified number of memory slots %" 2836 PRIu64" exceeds max supported %d", 2837 machine->ram_slots, max_memslots); 2838 exit(1); 2839 } 2840 2841 machine->device_memory->base = ROUND_UP(machine->ram_size, 2842 SPAPR_DEVICE_MEM_ALIGN); 2843 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2844 "device-memory", device_mem_size); 2845 memory_region_add_subregion(sysmem, machine->device_memory->base, 2846 &machine->device_memory->mr); 2847 } 2848 2849 if (smc->dr_lmb_enabled) { 2850 spapr_create_lmb_dr_connectors(spapr); 2851 } 2852 2853 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2854 /* Create the error string for live migration blocker */ 2855 error_setg(&spapr->fwnmi_migration_blocker, 2856 "A machine check is being handled during migration. The handler" 2857 "may run and log hardware error on the destination"); 2858 } 2859 2860 if (mc->nvdimm_supported) { 2861 spapr_create_nvdimm_dr_connectors(spapr); 2862 } 2863 2864 /* Set up RTAS event infrastructure */ 2865 spapr_events_init(spapr); 2866 2867 /* Set up the RTC RTAS interfaces */ 2868 spapr_rtc_create(spapr); 2869 2870 /* Set up VIO bus */ 2871 spapr->vio_bus = spapr_vio_bus_init(); 2872 2873 for (i = 0; serial_hd(i); i++) { 2874 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2875 } 2876 2877 /* We always have at least the nvram device on VIO */ 2878 spapr_create_nvram(spapr); 2879 2880 /* 2881 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2882 * connectors (described in root DT node's "ibm,drc-types" property) 2883 * are pre-initialized here. additional child connectors (such as 2884 * connectors for a PHBs PCI slots) are added as needed during their 2885 * parent's realization. 2886 */ 2887 if (smc->dr_phb_enabled) { 2888 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2889 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2890 } 2891 } 2892 2893 /* Set up PCI */ 2894 spapr_pci_rtas_init(); 2895 2896 phb = spapr_create_default_phb(); 2897 2898 for (i = 0; i < nb_nics; i++) { 2899 NICInfo *nd = &nd_table[i]; 2900 2901 if (!nd->model) { 2902 nd->model = g_strdup("spapr-vlan"); 2903 } 2904 2905 if (g_str_equal(nd->model, "spapr-vlan") || 2906 g_str_equal(nd->model, "ibmveth")) { 2907 spapr_vlan_create(spapr->vio_bus, nd); 2908 } else { 2909 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2910 } 2911 } 2912 2913 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2914 spapr_vscsi_create(spapr->vio_bus); 2915 } 2916 2917 /* Graphics */ 2918 if (spapr_vga_init(phb->bus, &error_fatal)) { 2919 spapr->has_graphics = true; 2920 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2921 } 2922 2923 if (machine->usb) { 2924 if (smc->use_ohci_by_default) { 2925 pci_create_simple(phb->bus, -1, "pci-ohci"); 2926 } else { 2927 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2928 } 2929 2930 if (spapr->has_graphics) { 2931 USBBus *usb_bus = usb_bus_find(-1); 2932 2933 usb_create_simple(usb_bus, "usb-kbd"); 2934 usb_create_simple(usb_bus, "usb-mouse"); 2935 } 2936 } 2937 2938 if (kernel_filename) { 2939 spapr->kernel_size = load_elf(kernel_filename, NULL, 2940 translate_kernel_address, spapr, 2941 NULL, NULL, NULL, NULL, 1, 2942 PPC_ELF_MACHINE, 0, 0); 2943 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2944 spapr->kernel_size = load_elf(kernel_filename, NULL, 2945 translate_kernel_address, spapr, 2946 NULL, NULL, NULL, NULL, 0, 2947 PPC_ELF_MACHINE, 0, 0); 2948 spapr->kernel_le = spapr->kernel_size > 0; 2949 } 2950 if (spapr->kernel_size < 0) { 2951 error_report("error loading %s: %s", kernel_filename, 2952 load_elf_strerror(spapr->kernel_size)); 2953 exit(1); 2954 } 2955 2956 /* load initrd */ 2957 if (initrd_filename) { 2958 /* Try to locate the initrd in the gap between the kernel 2959 * and the firmware. Add a bit of space just in case 2960 */ 2961 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2962 + 0x1ffff) & ~0xffff; 2963 spapr->initrd_size = load_image_targphys(initrd_filename, 2964 spapr->initrd_base, 2965 load_limit 2966 - spapr->initrd_base); 2967 if (spapr->initrd_size < 0) { 2968 error_report("could not load initial ram disk '%s'", 2969 initrd_filename); 2970 exit(1); 2971 } 2972 } 2973 } 2974 2975 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2976 if (!filename) { 2977 error_report("Could not find LPAR firmware '%s'", bios_name); 2978 exit(1); 2979 } 2980 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2981 if (fw_size <= 0) { 2982 error_report("Could not load LPAR firmware '%s'", filename); 2983 exit(1); 2984 } 2985 g_free(filename); 2986 2987 /* FIXME: Should register things through the MachineState's qdev 2988 * interface, this is a legacy from the sPAPREnvironment structure 2989 * which predated MachineState but had a similar function */ 2990 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2991 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 2992 &savevm_htab_handlers, spapr); 2993 2994 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 2995 2996 qemu_register_boot_set(spapr_boot_set, spapr); 2997 2998 /* 2999 * Nothing needs to be done to resume a suspended guest because 3000 * suspending does not change the machine state, so no need for 3001 * a ->wakeup method. 3002 */ 3003 qemu_register_wakeup_support(); 3004 3005 if (kvm_enabled()) { 3006 /* to stop and start vmclock */ 3007 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3008 &spapr->tb); 3009 3010 kvmppc_spapr_enable_inkernel_multitce(); 3011 } 3012 3013 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3014 } 3015 3016 #define DEFAULT_KVM_TYPE "auto" 3017 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3018 { 3019 /* 3020 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3021 * accomodate the 'HV' and 'PV' formats that exists in the 3022 * wild. The 'auto' mode is being introduced already as 3023 * lower-case, thus we don't need to bother checking for 3024 * "AUTO". 3025 */ 3026 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3027 return 0; 3028 } 3029 3030 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3031 return 1; 3032 } 3033 3034 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3035 return 2; 3036 } 3037 3038 error_report("Unknown kvm-type specified '%s'", vm_type); 3039 exit(1); 3040 } 3041 3042 /* 3043 * Implementation of an interface to adjust firmware path 3044 * for the bootindex property handling. 3045 */ 3046 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3047 DeviceState *dev) 3048 { 3049 #define CAST(type, obj, name) \ 3050 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3051 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3052 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3053 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3054 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3055 3056 if (d) { 3057 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3058 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3059 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3060 3061 if (spapr) { 3062 /* 3063 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3064 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3065 * 0x8000 | (target << 8) | (bus << 5) | lun 3066 * (see the "Logical unit addressing format" table in SAM5) 3067 */ 3068 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3069 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3070 (uint64_t)id << 48); 3071 } else if (virtio) { 3072 /* 3073 * We use SRP luns of the form 01000000 | (target << 8) | lun 3074 * in the top 32 bits of the 64-bit LUN 3075 * Note: the quote above is from SLOF and it is wrong, 3076 * the actual binding is: 3077 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3078 */ 3079 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3080 if (d->lun >= 256) { 3081 /* Use the LUN "flat space addressing method" */ 3082 id |= 0x4000; 3083 } 3084 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3085 (uint64_t)id << 32); 3086 } else if (usb) { 3087 /* 3088 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3089 * in the top 32 bits of the 64-bit LUN 3090 */ 3091 unsigned usb_port = atoi(usb->port->path); 3092 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3093 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3094 (uint64_t)id << 32); 3095 } 3096 } 3097 3098 /* 3099 * SLOF probes the USB devices, and if it recognizes that the device is a 3100 * storage device, it changes its name to "storage" instead of "usb-host", 3101 * and additionally adds a child node for the SCSI LUN, so the correct 3102 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3103 */ 3104 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3105 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3106 if (usb_host_dev_is_scsi_storage(usbdev)) { 3107 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3108 } 3109 } 3110 3111 if (phb) { 3112 /* Replace "pci" with "pci@800000020000000" */ 3113 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3114 } 3115 3116 if (vsc) { 3117 /* Same logic as virtio above */ 3118 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3119 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3120 } 3121 3122 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3123 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3124 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3125 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3126 } 3127 3128 if (pcidev) { 3129 return spapr_pci_fw_dev_name(pcidev); 3130 } 3131 3132 return NULL; 3133 } 3134 3135 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3136 { 3137 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3138 3139 return g_strdup(spapr->kvm_type); 3140 } 3141 3142 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3143 { 3144 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3145 3146 g_free(spapr->kvm_type); 3147 spapr->kvm_type = g_strdup(value); 3148 } 3149 3150 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3151 { 3152 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3153 3154 return spapr->use_hotplug_event_source; 3155 } 3156 3157 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3158 Error **errp) 3159 { 3160 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3161 3162 spapr->use_hotplug_event_source = value; 3163 } 3164 3165 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3166 { 3167 return true; 3168 } 3169 3170 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3171 { 3172 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3173 3174 switch (spapr->resize_hpt) { 3175 case SPAPR_RESIZE_HPT_DEFAULT: 3176 return g_strdup("default"); 3177 case SPAPR_RESIZE_HPT_DISABLED: 3178 return g_strdup("disabled"); 3179 case SPAPR_RESIZE_HPT_ENABLED: 3180 return g_strdup("enabled"); 3181 case SPAPR_RESIZE_HPT_REQUIRED: 3182 return g_strdup("required"); 3183 } 3184 g_assert_not_reached(); 3185 } 3186 3187 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3188 { 3189 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3190 3191 if (strcmp(value, "default") == 0) { 3192 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3193 } else if (strcmp(value, "disabled") == 0) { 3194 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3195 } else if (strcmp(value, "enabled") == 0) { 3196 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3197 } else if (strcmp(value, "required") == 0) { 3198 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3199 } else { 3200 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3201 } 3202 } 3203 3204 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3205 { 3206 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3207 3208 if (spapr->irq == &spapr_irq_xics_legacy) { 3209 return g_strdup("legacy"); 3210 } else if (spapr->irq == &spapr_irq_xics) { 3211 return g_strdup("xics"); 3212 } else if (spapr->irq == &spapr_irq_xive) { 3213 return g_strdup("xive"); 3214 } else if (spapr->irq == &spapr_irq_dual) { 3215 return g_strdup("dual"); 3216 } 3217 g_assert_not_reached(); 3218 } 3219 3220 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3221 { 3222 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3223 3224 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3225 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3226 return; 3227 } 3228 3229 /* The legacy IRQ backend can not be set */ 3230 if (strcmp(value, "xics") == 0) { 3231 spapr->irq = &spapr_irq_xics; 3232 } else if (strcmp(value, "xive") == 0) { 3233 spapr->irq = &spapr_irq_xive; 3234 } else if (strcmp(value, "dual") == 0) { 3235 spapr->irq = &spapr_irq_dual; 3236 } else { 3237 error_setg(errp, "Bad value for \"ic-mode\" property"); 3238 } 3239 } 3240 3241 static char *spapr_get_host_model(Object *obj, Error **errp) 3242 { 3243 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3244 3245 return g_strdup(spapr->host_model); 3246 } 3247 3248 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3249 { 3250 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3251 3252 g_free(spapr->host_model); 3253 spapr->host_model = g_strdup(value); 3254 } 3255 3256 static char *spapr_get_host_serial(Object *obj, Error **errp) 3257 { 3258 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3259 3260 return g_strdup(spapr->host_serial); 3261 } 3262 3263 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3264 { 3265 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3266 3267 g_free(spapr->host_serial); 3268 spapr->host_serial = g_strdup(value); 3269 } 3270 3271 static void spapr_instance_init(Object *obj) 3272 { 3273 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3274 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3275 MachineState *ms = MACHINE(spapr); 3276 MachineClass *mc = MACHINE_GET_CLASS(ms); 3277 3278 /* 3279 * NVDIMM support went live in 5.1 without considering that, in 3280 * other archs, the user needs to enable NVDIMM support with the 3281 * 'nvdimm' machine option and the default behavior is NVDIMM 3282 * support disabled. It is too late to roll back to the standard 3283 * behavior without breaking 5.1 guests. 3284 */ 3285 if (mc->nvdimm_supported) { 3286 ms->nvdimms_state->is_enabled = true; 3287 } 3288 3289 spapr->htab_fd = -1; 3290 spapr->use_hotplug_event_source = true; 3291 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3292 object_property_add_str(obj, "kvm-type", 3293 spapr_get_kvm_type, spapr_set_kvm_type); 3294 object_property_set_description(obj, "kvm-type", 3295 "Specifies the KVM virtualization mode (auto," 3296 " hv, pr). Defaults to 'auto'. This mode will use" 3297 " any available KVM module loaded in the host," 3298 " where kvm_hv takes precedence if both kvm_hv and" 3299 " kvm_pr are loaded."); 3300 object_property_add_bool(obj, "modern-hotplug-events", 3301 spapr_get_modern_hotplug_events, 3302 spapr_set_modern_hotplug_events); 3303 object_property_set_description(obj, "modern-hotplug-events", 3304 "Use dedicated hotplug event mechanism in" 3305 " place of standard EPOW events when possible" 3306 " (required for memory hot-unplug support)"); 3307 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3308 "Maximum permitted CPU compatibility mode"); 3309 3310 object_property_add_str(obj, "resize-hpt", 3311 spapr_get_resize_hpt, spapr_set_resize_hpt); 3312 object_property_set_description(obj, "resize-hpt", 3313 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3314 object_property_add_uint32_ptr(obj, "vsmt", 3315 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3316 object_property_set_description(obj, "vsmt", 3317 "Virtual SMT: KVM behaves as if this were" 3318 " the host's SMT mode"); 3319 3320 object_property_add_bool(obj, "vfio-no-msix-emulation", 3321 spapr_get_msix_emulation, NULL); 3322 3323 object_property_add_uint64_ptr(obj, "kernel-addr", 3324 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3325 object_property_set_description(obj, "kernel-addr", 3326 stringify(KERNEL_LOAD_ADDR) 3327 " for -kernel is the default"); 3328 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3329 /* The machine class defines the default interrupt controller mode */ 3330 spapr->irq = smc->irq; 3331 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3332 spapr_set_ic_mode); 3333 object_property_set_description(obj, "ic-mode", 3334 "Specifies the interrupt controller mode (xics, xive, dual)"); 3335 3336 object_property_add_str(obj, "host-model", 3337 spapr_get_host_model, spapr_set_host_model); 3338 object_property_set_description(obj, "host-model", 3339 "Host model to advertise in guest device tree"); 3340 object_property_add_str(obj, "host-serial", 3341 spapr_get_host_serial, spapr_set_host_serial); 3342 object_property_set_description(obj, "host-serial", 3343 "Host serial number to advertise in guest device tree"); 3344 } 3345 3346 static void spapr_machine_finalizefn(Object *obj) 3347 { 3348 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3349 3350 g_free(spapr->kvm_type); 3351 } 3352 3353 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3354 { 3355 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3356 PowerPCCPU *cpu = POWERPC_CPU(cs); 3357 CPUPPCState *env = &cpu->env; 3358 3359 cpu_synchronize_state(cs); 3360 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3361 if (spapr->fwnmi_system_reset_addr != -1) { 3362 uint64_t rtas_addr, addr; 3363 3364 /* get rtas addr from fdt */ 3365 rtas_addr = spapr_get_rtas_addr(); 3366 if (!rtas_addr) { 3367 qemu_system_guest_panicked(NULL); 3368 return; 3369 } 3370 3371 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3372 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3373 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3374 env->gpr[3] = addr; 3375 } 3376 ppc_cpu_do_system_reset(cs); 3377 if (spapr->fwnmi_system_reset_addr != -1) { 3378 env->nip = spapr->fwnmi_system_reset_addr; 3379 } 3380 } 3381 3382 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3383 { 3384 CPUState *cs; 3385 3386 CPU_FOREACH(cs) { 3387 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3388 } 3389 } 3390 3391 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3392 void *fdt, int *fdt_start_offset, Error **errp) 3393 { 3394 uint64_t addr; 3395 uint32_t node; 3396 3397 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3398 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3399 &error_abort); 3400 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3401 SPAPR_MEMORY_BLOCK_SIZE); 3402 return 0; 3403 } 3404 3405 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3406 bool dedicated_hp_event_source) 3407 { 3408 SpaprDrc *drc; 3409 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3410 int i; 3411 uint64_t addr = addr_start; 3412 bool hotplugged = spapr_drc_hotplugged(dev); 3413 3414 for (i = 0; i < nr_lmbs; i++) { 3415 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3416 addr / SPAPR_MEMORY_BLOCK_SIZE); 3417 g_assert(drc); 3418 3419 /* 3420 * memory_device_get_free_addr() provided a range of free addresses 3421 * that doesn't overlap with any existing mapping at pre-plug. The 3422 * corresponding LMB DRCs are thus assumed to be all attachable. 3423 */ 3424 spapr_drc_attach(drc, dev); 3425 if (!hotplugged) { 3426 spapr_drc_reset(drc); 3427 } 3428 addr += SPAPR_MEMORY_BLOCK_SIZE; 3429 } 3430 /* send hotplug notification to the 3431 * guest only in case of hotplugged memory 3432 */ 3433 if (hotplugged) { 3434 if (dedicated_hp_event_source) { 3435 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3436 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3437 g_assert(drc); 3438 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3439 nr_lmbs, 3440 spapr_drc_index(drc)); 3441 } else { 3442 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3443 nr_lmbs); 3444 } 3445 } 3446 } 3447 3448 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3449 { 3450 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3451 PCDIMMDevice *dimm = PC_DIMM(dev); 3452 uint64_t size, addr; 3453 int64_t slot; 3454 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3455 3456 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3457 3458 pc_dimm_plug(dimm, MACHINE(ms)); 3459 3460 if (!is_nvdimm) { 3461 addr = object_property_get_uint(OBJECT(dimm), 3462 PC_DIMM_ADDR_PROP, &error_abort); 3463 spapr_add_lmbs(dev, addr, size, 3464 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3465 } else { 3466 slot = object_property_get_int(OBJECT(dimm), 3467 PC_DIMM_SLOT_PROP, &error_abort); 3468 /* We should have valid slot number at this point */ 3469 g_assert(slot >= 0); 3470 spapr_add_nvdimm(dev, slot); 3471 } 3472 } 3473 3474 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3475 Error **errp) 3476 { 3477 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3478 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3479 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3480 PCDIMMDevice *dimm = PC_DIMM(dev); 3481 Error *local_err = NULL; 3482 uint64_t size; 3483 Object *memdev; 3484 hwaddr pagesize; 3485 3486 if (!smc->dr_lmb_enabled) { 3487 error_setg(errp, "Memory hotplug not supported for this machine"); 3488 return; 3489 } 3490 3491 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3492 if (local_err) { 3493 error_propagate(errp, local_err); 3494 return; 3495 } 3496 3497 if (is_nvdimm) { 3498 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3499 return; 3500 } 3501 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3502 error_setg(errp, "Hotplugged memory size must be a multiple of " 3503 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3504 return; 3505 } 3506 3507 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3508 &error_abort); 3509 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3510 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3511 return; 3512 } 3513 3514 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3515 } 3516 3517 struct SpaprDimmState { 3518 PCDIMMDevice *dimm; 3519 uint32_t nr_lmbs; 3520 QTAILQ_ENTRY(SpaprDimmState) next; 3521 }; 3522 3523 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3524 PCDIMMDevice *dimm) 3525 { 3526 SpaprDimmState *dimm_state = NULL; 3527 3528 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3529 if (dimm_state->dimm == dimm) { 3530 break; 3531 } 3532 } 3533 return dimm_state; 3534 } 3535 3536 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3537 uint32_t nr_lmbs, 3538 PCDIMMDevice *dimm) 3539 { 3540 SpaprDimmState *ds = NULL; 3541 3542 /* 3543 * If this request is for a DIMM whose removal had failed earlier 3544 * (due to guest's refusal to remove the LMBs), we would have this 3545 * dimm already in the pending_dimm_unplugs list. In that 3546 * case don't add again. 3547 */ 3548 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3549 if (!ds) { 3550 ds = g_malloc0(sizeof(SpaprDimmState)); 3551 ds->nr_lmbs = nr_lmbs; 3552 ds->dimm = dimm; 3553 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3554 } 3555 return ds; 3556 } 3557 3558 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3559 SpaprDimmState *dimm_state) 3560 { 3561 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3562 g_free(dimm_state); 3563 } 3564 3565 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3566 PCDIMMDevice *dimm) 3567 { 3568 SpaprDrc *drc; 3569 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3570 &error_abort); 3571 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3572 uint32_t avail_lmbs = 0; 3573 uint64_t addr_start, addr; 3574 int i; 3575 3576 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3577 &error_abort); 3578 3579 addr = addr_start; 3580 for (i = 0; i < nr_lmbs; i++) { 3581 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3582 addr / SPAPR_MEMORY_BLOCK_SIZE); 3583 g_assert(drc); 3584 if (drc->dev) { 3585 avail_lmbs++; 3586 } 3587 addr += SPAPR_MEMORY_BLOCK_SIZE; 3588 } 3589 3590 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3591 } 3592 3593 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev) 3594 { 3595 SpaprDimmState *ds; 3596 PCDIMMDevice *dimm; 3597 SpaprDrc *drc; 3598 uint32_t nr_lmbs; 3599 uint64_t size, addr_start, addr; 3600 g_autofree char *qapi_error = NULL; 3601 int i; 3602 3603 if (!dev) { 3604 return; 3605 } 3606 3607 dimm = PC_DIMM(dev); 3608 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3609 3610 /* 3611 * 'ds == NULL' would mean that the DIMM doesn't have a pending 3612 * unplug state, but one of its DRC is marked as unplug_requested. 3613 * This is bad and weird enough to g_assert() out. 3614 */ 3615 g_assert(ds); 3616 3617 spapr_pending_dimm_unplugs_remove(spapr, ds); 3618 3619 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3620 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3621 3622 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3623 &error_abort); 3624 3625 addr = addr_start; 3626 for (i = 0; i < nr_lmbs; i++) { 3627 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3628 addr / SPAPR_MEMORY_BLOCK_SIZE); 3629 g_assert(drc); 3630 3631 drc->unplug_requested = false; 3632 addr += SPAPR_MEMORY_BLOCK_SIZE; 3633 } 3634 3635 /* 3636 * Tell QAPI that something happened and the memory 3637 * hotunplug wasn't successful. 3638 */ 3639 qapi_error = g_strdup_printf("Memory hotunplug rejected by the guest " 3640 "for device %s", dev->id); 3641 qapi_event_send_mem_unplug_error(dev->id, qapi_error); 3642 } 3643 3644 /* Callback to be called during DRC release. */ 3645 void spapr_lmb_release(DeviceState *dev) 3646 { 3647 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3648 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3649 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3650 3651 /* This information will get lost if a migration occurs 3652 * during the unplug process. In this case recover it. */ 3653 if (ds == NULL) { 3654 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3655 g_assert(ds); 3656 /* The DRC being examined by the caller at least must be counted */ 3657 g_assert(ds->nr_lmbs); 3658 } 3659 3660 if (--ds->nr_lmbs) { 3661 return; 3662 } 3663 3664 /* 3665 * Now that all the LMBs have been removed by the guest, call the 3666 * unplug handler chain. This can never fail. 3667 */ 3668 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3669 object_unparent(OBJECT(dev)); 3670 } 3671 3672 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3673 { 3674 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3675 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3676 3677 /* We really shouldn't get this far without anything to unplug */ 3678 g_assert(ds); 3679 3680 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3681 qdev_unrealize(dev); 3682 spapr_pending_dimm_unplugs_remove(spapr, ds); 3683 } 3684 3685 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3686 DeviceState *dev, Error **errp) 3687 { 3688 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3689 PCDIMMDevice *dimm = PC_DIMM(dev); 3690 uint32_t nr_lmbs; 3691 uint64_t size, addr_start, addr; 3692 int i; 3693 SpaprDrc *drc; 3694 3695 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3696 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3697 return; 3698 } 3699 3700 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3701 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3702 3703 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3704 &error_abort); 3705 3706 /* 3707 * An existing pending dimm state for this DIMM means that there is an 3708 * unplug operation in progress, waiting for the spapr_lmb_release 3709 * callback to complete the job (BQL can't cover that far). In this case, 3710 * bail out to avoid detaching DRCs that were already released. 3711 */ 3712 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3713 error_setg(errp, "Memory unplug already in progress for device %s", 3714 dev->id); 3715 return; 3716 } 3717 3718 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3719 3720 addr = addr_start; 3721 for (i = 0; i < nr_lmbs; i++) { 3722 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3723 addr / SPAPR_MEMORY_BLOCK_SIZE); 3724 g_assert(drc); 3725 3726 spapr_drc_unplug_request(drc); 3727 addr += SPAPR_MEMORY_BLOCK_SIZE; 3728 } 3729 3730 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3731 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3732 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3733 nr_lmbs, spapr_drc_index(drc)); 3734 } 3735 3736 /* Callback to be called during DRC release. */ 3737 void spapr_core_release(DeviceState *dev) 3738 { 3739 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3740 3741 /* Call the unplug handler chain. This can never fail. */ 3742 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3743 object_unparent(OBJECT(dev)); 3744 } 3745 3746 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3747 { 3748 MachineState *ms = MACHINE(hotplug_dev); 3749 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3750 CPUCore *cc = CPU_CORE(dev); 3751 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3752 3753 if (smc->pre_2_10_has_unused_icps) { 3754 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3755 int i; 3756 3757 for (i = 0; i < cc->nr_threads; i++) { 3758 CPUState *cs = CPU(sc->threads[i]); 3759 3760 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3761 } 3762 } 3763 3764 assert(core_slot); 3765 core_slot->cpu = NULL; 3766 qdev_unrealize(dev); 3767 } 3768 3769 static 3770 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3771 Error **errp) 3772 { 3773 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3774 int index; 3775 SpaprDrc *drc; 3776 CPUCore *cc = CPU_CORE(dev); 3777 3778 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3779 error_setg(errp, "Unable to find CPU core with core-id: %d", 3780 cc->core_id); 3781 return; 3782 } 3783 if (index == 0) { 3784 error_setg(errp, "Boot CPU core may not be unplugged"); 3785 return; 3786 } 3787 3788 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3789 spapr_vcpu_id(spapr, cc->core_id)); 3790 g_assert(drc); 3791 3792 if (!spapr_drc_unplug_requested(drc)) { 3793 spapr_drc_unplug_request(drc); 3794 } 3795 3796 /* 3797 * spapr_hotplug_req_remove_by_index is left unguarded, out of the 3798 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ 3799 * pulses removing the same CPU. Otherwise, in an failed hotunplug 3800 * attempt (e.g. the kernel will refuse to remove the last online 3801 * CPU), we will never attempt it again because unplug_requested 3802 * will still be 'true' in that case. 3803 */ 3804 spapr_hotplug_req_remove_by_index(drc); 3805 } 3806 3807 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3808 void *fdt, int *fdt_start_offset, Error **errp) 3809 { 3810 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3811 CPUState *cs = CPU(core->threads[0]); 3812 PowerPCCPU *cpu = POWERPC_CPU(cs); 3813 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3814 int id = spapr_get_vcpu_id(cpu); 3815 g_autofree char *nodename = NULL; 3816 int offset; 3817 3818 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3819 offset = fdt_add_subnode(fdt, 0, nodename); 3820 3821 spapr_dt_cpu(cs, fdt, offset, spapr); 3822 3823 /* 3824 * spapr_dt_cpu() does not fill the 'name' property in the 3825 * CPU node. The function is called during boot process, before 3826 * and after CAS, and overwriting the 'name' property written 3827 * by SLOF is not allowed. 3828 * 3829 * Write it manually after spapr_dt_cpu(). This makes the hotplug 3830 * CPUs more compatible with the coldplugged ones, which have 3831 * the 'name' property. Linux Kernel also relies on this 3832 * property to identify CPU nodes. 3833 */ 3834 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 3835 3836 *fdt_start_offset = offset; 3837 return 0; 3838 } 3839 3840 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3841 { 3842 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3843 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3844 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3845 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3846 CPUCore *cc = CPU_CORE(dev); 3847 CPUState *cs; 3848 SpaprDrc *drc; 3849 CPUArchId *core_slot; 3850 int index; 3851 bool hotplugged = spapr_drc_hotplugged(dev); 3852 int i; 3853 3854 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3855 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 3856 3857 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3858 spapr_vcpu_id(spapr, cc->core_id)); 3859 3860 g_assert(drc || !mc->has_hotpluggable_cpus); 3861 3862 if (drc) { 3863 /* 3864 * spapr_core_pre_plug() already buys us this is a brand new 3865 * core being plugged into a free slot. Nothing should already 3866 * be attached to the corresponding DRC. 3867 */ 3868 spapr_drc_attach(drc, dev); 3869 3870 if (hotplugged) { 3871 /* 3872 * Send hotplug notification interrupt to the guest only 3873 * in case of hotplugged CPUs. 3874 */ 3875 spapr_hotplug_req_add_by_index(drc); 3876 } else { 3877 spapr_drc_reset(drc); 3878 } 3879 } 3880 3881 core_slot->cpu = OBJECT(dev); 3882 3883 /* 3884 * Set compatibility mode to match the boot CPU, which was either set 3885 * by the machine reset code or by CAS. This really shouldn't fail at 3886 * this point. 3887 */ 3888 if (hotplugged) { 3889 for (i = 0; i < cc->nr_threads; i++) { 3890 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3891 &error_abort); 3892 } 3893 } 3894 3895 if (smc->pre_2_10_has_unused_icps) { 3896 for (i = 0; i < cc->nr_threads; i++) { 3897 cs = CPU(core->threads[i]); 3898 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3899 } 3900 } 3901 } 3902 3903 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3904 Error **errp) 3905 { 3906 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3907 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3908 CPUCore *cc = CPU_CORE(dev); 3909 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3910 const char *type = object_get_typename(OBJECT(dev)); 3911 CPUArchId *core_slot; 3912 int index; 3913 unsigned int smp_threads = machine->smp.threads; 3914 3915 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3916 error_setg(errp, "CPU hotplug not supported for this machine"); 3917 return; 3918 } 3919 3920 if (strcmp(base_core_type, type)) { 3921 error_setg(errp, "CPU core type should be %s", base_core_type); 3922 return; 3923 } 3924 3925 if (cc->core_id % smp_threads) { 3926 error_setg(errp, "invalid core id %d", cc->core_id); 3927 return; 3928 } 3929 3930 /* 3931 * In general we should have homogeneous threads-per-core, but old 3932 * (pre hotplug support) machine types allow the last core to have 3933 * reduced threads as a compatibility hack for when we allowed 3934 * total vcpus not a multiple of threads-per-core. 3935 */ 3936 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3937 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 3938 smp_threads); 3939 return; 3940 } 3941 3942 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3943 if (!core_slot) { 3944 error_setg(errp, "core id %d out of range", cc->core_id); 3945 return; 3946 } 3947 3948 if (core_slot->cpu) { 3949 error_setg(errp, "core %d already populated", cc->core_id); 3950 return; 3951 } 3952 3953 numa_cpu_pre_plug(core_slot, dev, errp); 3954 } 3955 3956 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3957 void *fdt, int *fdt_start_offset, Error **errp) 3958 { 3959 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3960 int intc_phandle; 3961 3962 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3963 if (intc_phandle <= 0) { 3964 return -1; 3965 } 3966 3967 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3968 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3969 return -1; 3970 } 3971 3972 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3973 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3974 3975 return 0; 3976 } 3977 3978 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3979 Error **errp) 3980 { 3981 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3982 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3983 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3984 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3985 SpaprDrc *drc; 3986 3987 if (dev->hotplugged && !smc->dr_phb_enabled) { 3988 error_setg(errp, "PHB hotplug not supported for this machine"); 3989 return false; 3990 } 3991 3992 if (sphb->index == (uint32_t)-1) { 3993 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3994 return false; 3995 } 3996 3997 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3998 if (drc && drc->dev) { 3999 error_setg(errp, "PHB %d already attached", sphb->index); 4000 return false; 4001 } 4002 4003 /* 4004 * This will check that sphb->index doesn't exceed the maximum number of 4005 * PHBs for the current machine type. 4006 */ 4007 return 4008 smc->phb_placement(spapr, sphb->index, 4009 &sphb->buid, &sphb->io_win_addr, 4010 &sphb->mem_win_addr, &sphb->mem64_win_addr, 4011 windows_supported, sphb->dma_liobn, 4012 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 4013 errp); 4014 } 4015 4016 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4017 { 4018 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4019 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4020 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4021 SpaprDrc *drc; 4022 bool hotplugged = spapr_drc_hotplugged(dev); 4023 4024 if (!smc->dr_phb_enabled) { 4025 return; 4026 } 4027 4028 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4029 /* hotplug hooks should check it's enabled before getting this far */ 4030 assert(drc); 4031 4032 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 4033 spapr_drc_attach(drc, dev); 4034 4035 if (hotplugged) { 4036 spapr_hotplug_req_add_by_index(drc); 4037 } else { 4038 spapr_drc_reset(drc); 4039 } 4040 } 4041 4042 void spapr_phb_release(DeviceState *dev) 4043 { 4044 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4045 4046 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4047 object_unparent(OBJECT(dev)); 4048 } 4049 4050 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4051 { 4052 qdev_unrealize(dev); 4053 } 4054 4055 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4056 DeviceState *dev, Error **errp) 4057 { 4058 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4059 SpaprDrc *drc; 4060 4061 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4062 assert(drc); 4063 4064 if (!spapr_drc_unplug_requested(drc)) { 4065 spapr_drc_unplug_request(drc); 4066 spapr_hotplug_req_remove_by_index(drc); 4067 } else { 4068 error_setg(errp, 4069 "PCI Host Bridge unplug already in progress for device %s", 4070 dev->id); 4071 } 4072 } 4073 4074 static 4075 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4076 Error **errp) 4077 { 4078 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4079 4080 if (spapr->tpm_proxy != NULL) { 4081 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4082 return false; 4083 } 4084 4085 return true; 4086 } 4087 4088 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4089 { 4090 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4091 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4092 4093 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4094 g_assert(spapr->tpm_proxy == NULL); 4095 4096 spapr->tpm_proxy = tpm_proxy; 4097 } 4098 4099 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4100 { 4101 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4102 4103 qdev_unrealize(dev); 4104 object_unparent(OBJECT(dev)); 4105 spapr->tpm_proxy = NULL; 4106 } 4107 4108 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4109 DeviceState *dev, Error **errp) 4110 { 4111 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4112 spapr_memory_plug(hotplug_dev, dev); 4113 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4114 spapr_core_plug(hotplug_dev, dev); 4115 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4116 spapr_phb_plug(hotplug_dev, dev); 4117 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4118 spapr_tpm_proxy_plug(hotplug_dev, dev); 4119 } 4120 } 4121 4122 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4123 DeviceState *dev, Error **errp) 4124 { 4125 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4126 spapr_memory_unplug(hotplug_dev, dev); 4127 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4128 spapr_core_unplug(hotplug_dev, dev); 4129 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4130 spapr_phb_unplug(hotplug_dev, dev); 4131 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4132 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4133 } 4134 } 4135 4136 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4137 { 4138 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4139 /* 4140 * CAS will process all pending unplug requests. 4141 * 4142 * HACK: a guest could theoretically have cleared all bits in OV5, 4143 * but none of the guests we care for do. 4144 */ 4145 spapr_ovec_empty(spapr->ov5_cas); 4146 } 4147 4148 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4149 DeviceState *dev, Error **errp) 4150 { 4151 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4152 MachineClass *mc = MACHINE_GET_CLASS(sms); 4153 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4154 4155 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4156 if (spapr_memory_hot_unplug_supported(sms)) { 4157 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4158 } else { 4159 error_setg(errp, "Memory hot unplug not supported for this guest"); 4160 } 4161 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4162 if (!mc->has_hotpluggable_cpus) { 4163 error_setg(errp, "CPU hot unplug not supported on this machine"); 4164 return; 4165 } 4166 spapr_core_unplug_request(hotplug_dev, dev, errp); 4167 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4168 if (!smc->dr_phb_enabled) { 4169 error_setg(errp, "PHB hot unplug not supported on this machine"); 4170 return; 4171 } 4172 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4173 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4174 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4175 } 4176 } 4177 4178 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4179 DeviceState *dev, Error **errp) 4180 { 4181 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4182 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4183 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4184 spapr_core_pre_plug(hotplug_dev, dev, errp); 4185 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4186 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4187 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4188 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4189 } 4190 } 4191 4192 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4193 DeviceState *dev) 4194 { 4195 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4196 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4197 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4198 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4199 return HOTPLUG_HANDLER(machine); 4200 } 4201 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4202 PCIDevice *pcidev = PCI_DEVICE(dev); 4203 PCIBus *root = pci_device_root_bus(pcidev); 4204 SpaprPhbState *phb = 4205 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4206 TYPE_SPAPR_PCI_HOST_BRIDGE); 4207 4208 if (phb) { 4209 return HOTPLUG_HANDLER(phb); 4210 } 4211 } 4212 return NULL; 4213 } 4214 4215 static CpuInstanceProperties 4216 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4217 { 4218 CPUArchId *core_slot; 4219 MachineClass *mc = MACHINE_GET_CLASS(machine); 4220 4221 /* make sure possible_cpu are intialized */ 4222 mc->possible_cpu_arch_ids(machine); 4223 /* get CPU core slot containing thread that matches cpu_index */ 4224 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4225 assert(core_slot); 4226 return core_slot->props; 4227 } 4228 4229 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4230 { 4231 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4232 } 4233 4234 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4235 { 4236 int i; 4237 unsigned int smp_threads = machine->smp.threads; 4238 unsigned int smp_cpus = machine->smp.cpus; 4239 const char *core_type; 4240 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4241 MachineClass *mc = MACHINE_GET_CLASS(machine); 4242 4243 if (!mc->has_hotpluggable_cpus) { 4244 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4245 } 4246 if (machine->possible_cpus) { 4247 assert(machine->possible_cpus->len == spapr_max_cores); 4248 return machine->possible_cpus; 4249 } 4250 4251 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4252 if (!core_type) { 4253 error_report("Unable to find sPAPR CPU Core definition"); 4254 exit(1); 4255 } 4256 4257 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4258 sizeof(CPUArchId) * spapr_max_cores); 4259 machine->possible_cpus->len = spapr_max_cores; 4260 for (i = 0; i < machine->possible_cpus->len; i++) { 4261 int core_id = i * smp_threads; 4262 4263 machine->possible_cpus->cpus[i].type = core_type; 4264 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4265 machine->possible_cpus->cpus[i].arch_id = core_id; 4266 machine->possible_cpus->cpus[i].props.has_core_id = true; 4267 machine->possible_cpus->cpus[i].props.core_id = core_id; 4268 } 4269 return machine->possible_cpus; 4270 } 4271 4272 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4273 uint64_t *buid, hwaddr *pio, 4274 hwaddr *mmio32, hwaddr *mmio64, 4275 unsigned n_dma, uint32_t *liobns, 4276 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4277 { 4278 /* 4279 * New-style PHB window placement. 4280 * 4281 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4282 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4283 * windows. 4284 * 4285 * Some guest kernels can't work with MMIO windows above 1<<46 4286 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4287 * 4288 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4289 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4290 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4291 * 1TiB 64-bit MMIO windows for each PHB. 4292 */ 4293 const uint64_t base_buid = 0x800000020000000ULL; 4294 int i; 4295 4296 /* Sanity check natural alignments */ 4297 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4298 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4299 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4300 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4301 /* Sanity check bounds */ 4302 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4303 SPAPR_PCI_MEM32_WIN_SIZE); 4304 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4305 SPAPR_PCI_MEM64_WIN_SIZE); 4306 4307 if (index >= SPAPR_MAX_PHBS) { 4308 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4309 SPAPR_MAX_PHBS - 1); 4310 return false; 4311 } 4312 4313 *buid = base_buid + index; 4314 for (i = 0; i < n_dma; ++i) { 4315 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4316 } 4317 4318 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4319 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4320 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4321 4322 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4323 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4324 return true; 4325 } 4326 4327 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4328 { 4329 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4330 4331 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4332 } 4333 4334 static void spapr_ics_resend(XICSFabric *dev) 4335 { 4336 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4337 4338 ics_resend(spapr->ics); 4339 } 4340 4341 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4342 { 4343 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4344 4345 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4346 } 4347 4348 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4349 Monitor *mon) 4350 { 4351 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4352 4353 spapr_irq_print_info(spapr, mon); 4354 monitor_printf(mon, "irqchip: %s\n", 4355 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4356 } 4357 4358 /* 4359 * This is a XIVE only operation 4360 */ 4361 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4362 uint8_t nvt_blk, uint32_t nvt_idx, 4363 bool cam_ignore, uint8_t priority, 4364 uint32_t logic_serv, XiveTCTXMatch *match) 4365 { 4366 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4367 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4368 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4369 int count; 4370 4371 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4372 priority, logic_serv, match); 4373 if (count < 0) { 4374 return count; 4375 } 4376 4377 /* 4378 * When we implement the save and restore of the thread interrupt 4379 * contexts in the enter/exit CPU handlers of the machine and the 4380 * escalations in QEMU, we should be able to handle non dispatched 4381 * vCPUs. 4382 * 4383 * Until this is done, the sPAPR machine should find at least one 4384 * matching context always. 4385 */ 4386 if (count == 0) { 4387 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4388 nvt_blk, nvt_idx); 4389 } 4390 4391 return count; 4392 } 4393 4394 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4395 { 4396 return cpu->vcpu_id; 4397 } 4398 4399 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4400 { 4401 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4402 MachineState *ms = MACHINE(spapr); 4403 int vcpu_id; 4404 4405 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4406 4407 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4408 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4409 error_append_hint(errp, "Adjust the number of cpus to %d " 4410 "or try to raise the number of threads per core\n", 4411 vcpu_id * ms->smp.threads / spapr->vsmt); 4412 return false; 4413 } 4414 4415 cpu->vcpu_id = vcpu_id; 4416 return true; 4417 } 4418 4419 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4420 { 4421 CPUState *cs; 4422 4423 CPU_FOREACH(cs) { 4424 PowerPCCPU *cpu = POWERPC_CPU(cs); 4425 4426 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4427 return cpu; 4428 } 4429 } 4430 4431 return NULL; 4432 } 4433 4434 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4435 { 4436 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4437 4438 /* These are only called by TCG, KVM maintains dispatch state */ 4439 4440 spapr_cpu->prod = false; 4441 if (spapr_cpu->vpa_addr) { 4442 CPUState *cs = CPU(cpu); 4443 uint32_t dispatch; 4444 4445 dispatch = ldl_be_phys(cs->as, 4446 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4447 dispatch++; 4448 if ((dispatch & 1) != 0) { 4449 qemu_log_mask(LOG_GUEST_ERROR, 4450 "VPA: incorrect dispatch counter value for " 4451 "dispatched partition %u, correcting.\n", dispatch); 4452 dispatch++; 4453 } 4454 stl_be_phys(cs->as, 4455 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4456 } 4457 } 4458 4459 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4460 { 4461 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4462 4463 if (spapr_cpu->vpa_addr) { 4464 CPUState *cs = CPU(cpu); 4465 uint32_t dispatch; 4466 4467 dispatch = ldl_be_phys(cs->as, 4468 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4469 dispatch++; 4470 if ((dispatch & 1) != 1) { 4471 qemu_log_mask(LOG_GUEST_ERROR, 4472 "VPA: incorrect dispatch counter value for " 4473 "preempted partition %u, correcting.\n", dispatch); 4474 dispatch++; 4475 } 4476 stl_be_phys(cs->as, 4477 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4478 } 4479 } 4480 4481 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4482 { 4483 MachineClass *mc = MACHINE_CLASS(oc); 4484 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4485 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4486 NMIClass *nc = NMI_CLASS(oc); 4487 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4488 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4489 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4490 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4491 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4492 4493 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4494 mc->ignore_boot_device_suffixes = true; 4495 4496 /* 4497 * We set up the default / latest behaviour here. The class_init 4498 * functions for the specific versioned machine types can override 4499 * these details for backwards compatibility 4500 */ 4501 mc->init = spapr_machine_init; 4502 mc->reset = spapr_machine_reset; 4503 mc->block_default_type = IF_SCSI; 4504 4505 /* 4506 * Setting max_cpus to INT32_MAX. Both KVM and TCG max_cpus values 4507 * should be limited by the host capability instead of hardcoded. 4508 * max_cpus for KVM guests will be checked in kvm_init(), and TCG 4509 * guests are welcome to have as many CPUs as the host are capable 4510 * of emulate. 4511 */ 4512 mc->max_cpus = INT32_MAX; 4513 4514 mc->no_parallel = 1; 4515 mc->default_boot_order = ""; 4516 mc->default_ram_size = 512 * MiB; 4517 mc->default_ram_id = "ppc_spapr.ram"; 4518 mc->default_display = "std"; 4519 mc->kvm_type = spapr_kvm_type; 4520 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4521 mc->pci_allow_0_address = true; 4522 assert(!mc->get_hotplug_handler); 4523 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4524 hc->pre_plug = spapr_machine_device_pre_plug; 4525 hc->plug = spapr_machine_device_plug; 4526 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4527 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4528 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4529 hc->unplug_request = spapr_machine_device_unplug_request; 4530 hc->unplug = spapr_machine_device_unplug; 4531 4532 smc->dr_lmb_enabled = true; 4533 smc->update_dt_enabled = true; 4534 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4535 mc->has_hotpluggable_cpus = true; 4536 mc->nvdimm_supported = true; 4537 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4538 fwc->get_dev_path = spapr_get_fw_dev_path; 4539 nc->nmi_monitor_handler = spapr_nmi; 4540 smc->phb_placement = spapr_phb_placement; 4541 vhc->hypercall = emulate_spapr_hypercall; 4542 vhc->hpt_mask = spapr_hpt_mask; 4543 vhc->map_hptes = spapr_map_hptes; 4544 vhc->unmap_hptes = spapr_unmap_hptes; 4545 vhc->hpte_set_c = spapr_hpte_set_c; 4546 vhc->hpte_set_r = spapr_hpte_set_r; 4547 vhc->get_pate = spapr_get_pate; 4548 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4549 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4550 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4551 xic->ics_get = spapr_ics_get; 4552 xic->ics_resend = spapr_ics_resend; 4553 xic->icp_get = spapr_icp_get; 4554 ispc->print_info = spapr_pic_print_info; 4555 /* Force NUMA node memory size to be a multiple of 4556 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4557 * in which LMBs are represented and hot-added 4558 */ 4559 mc->numa_mem_align_shift = 28; 4560 mc->auto_enable_numa = true; 4561 4562 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4563 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4564 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4565 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4566 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4567 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4568 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4569 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4570 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4571 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4572 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4573 spapr_caps_add_properties(smc); 4574 smc->irq = &spapr_irq_dual; 4575 smc->dr_phb_enabled = true; 4576 smc->linux_pci_probe = true; 4577 smc->smp_threads_vsmt = true; 4578 smc->nr_xirqs = SPAPR_NR_XIRQS; 4579 xfc->match_nvt = spapr_match_nvt; 4580 } 4581 4582 static const TypeInfo spapr_machine_info = { 4583 .name = TYPE_SPAPR_MACHINE, 4584 .parent = TYPE_MACHINE, 4585 .abstract = true, 4586 .instance_size = sizeof(SpaprMachineState), 4587 .instance_init = spapr_instance_init, 4588 .instance_finalize = spapr_machine_finalizefn, 4589 .class_size = sizeof(SpaprMachineClass), 4590 .class_init = spapr_machine_class_init, 4591 .interfaces = (InterfaceInfo[]) { 4592 { TYPE_FW_PATH_PROVIDER }, 4593 { TYPE_NMI }, 4594 { TYPE_HOTPLUG_HANDLER }, 4595 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4596 { TYPE_XICS_FABRIC }, 4597 { TYPE_INTERRUPT_STATS_PROVIDER }, 4598 { TYPE_XIVE_FABRIC }, 4599 { } 4600 }, 4601 }; 4602 4603 static void spapr_machine_latest_class_options(MachineClass *mc) 4604 { 4605 mc->alias = "pseries"; 4606 mc->is_default = true; 4607 } 4608 4609 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4610 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4611 void *data) \ 4612 { \ 4613 MachineClass *mc = MACHINE_CLASS(oc); \ 4614 spapr_machine_##suffix##_class_options(mc); \ 4615 if (latest) { \ 4616 spapr_machine_latest_class_options(mc); \ 4617 } \ 4618 } \ 4619 static const TypeInfo spapr_machine_##suffix##_info = { \ 4620 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4621 .parent = TYPE_SPAPR_MACHINE, \ 4622 .class_init = spapr_machine_##suffix##_class_init, \ 4623 }; \ 4624 static void spapr_machine_register_##suffix(void) \ 4625 { \ 4626 type_register(&spapr_machine_##suffix##_info); \ 4627 } \ 4628 type_init(spapr_machine_register_##suffix) 4629 4630 /* 4631 * pseries-6.1 4632 */ 4633 static void spapr_machine_6_1_class_options(MachineClass *mc) 4634 { 4635 /* Defaults for the latest behaviour inherited from the base class */ 4636 } 4637 4638 DEFINE_SPAPR_MACHINE(6_1, "6.1", true); 4639 4640 /* 4641 * pseries-6.0 4642 */ 4643 static void spapr_machine_6_0_class_options(MachineClass *mc) 4644 { 4645 spapr_machine_6_1_class_options(mc); 4646 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 4647 } 4648 4649 DEFINE_SPAPR_MACHINE(6_0, "6.0", false); 4650 4651 /* 4652 * pseries-5.2 4653 */ 4654 static void spapr_machine_5_2_class_options(MachineClass *mc) 4655 { 4656 spapr_machine_6_0_class_options(mc); 4657 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4658 } 4659 4660 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4661 4662 /* 4663 * pseries-5.1 4664 */ 4665 static void spapr_machine_5_1_class_options(MachineClass *mc) 4666 { 4667 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4668 4669 spapr_machine_5_2_class_options(mc); 4670 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4671 smc->pre_5_2_numa_associativity = true; 4672 } 4673 4674 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4675 4676 /* 4677 * pseries-5.0 4678 */ 4679 static void spapr_machine_5_0_class_options(MachineClass *mc) 4680 { 4681 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4682 static GlobalProperty compat[] = { 4683 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4684 }; 4685 4686 spapr_machine_5_1_class_options(mc); 4687 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4688 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4689 mc->numa_mem_supported = true; 4690 smc->pre_5_1_assoc_refpoints = true; 4691 } 4692 4693 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4694 4695 /* 4696 * pseries-4.2 4697 */ 4698 static void spapr_machine_4_2_class_options(MachineClass *mc) 4699 { 4700 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4701 4702 spapr_machine_5_0_class_options(mc); 4703 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4704 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4705 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4706 smc->rma_limit = 16 * GiB; 4707 mc->nvdimm_supported = false; 4708 } 4709 4710 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4711 4712 /* 4713 * pseries-4.1 4714 */ 4715 static void spapr_machine_4_1_class_options(MachineClass *mc) 4716 { 4717 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4718 static GlobalProperty compat[] = { 4719 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4720 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4721 }; 4722 4723 spapr_machine_4_2_class_options(mc); 4724 smc->linux_pci_probe = false; 4725 smc->smp_threads_vsmt = false; 4726 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4727 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4728 } 4729 4730 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4731 4732 /* 4733 * pseries-4.0 4734 */ 4735 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4736 uint64_t *buid, hwaddr *pio, 4737 hwaddr *mmio32, hwaddr *mmio64, 4738 unsigned n_dma, uint32_t *liobns, 4739 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4740 { 4741 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 4742 liobns, nv2gpa, nv2atsd, errp)) { 4743 return false; 4744 } 4745 4746 *nv2gpa = 0; 4747 *nv2atsd = 0; 4748 return true; 4749 } 4750 static void spapr_machine_4_0_class_options(MachineClass *mc) 4751 { 4752 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4753 4754 spapr_machine_4_1_class_options(mc); 4755 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4756 smc->phb_placement = phb_placement_4_0; 4757 smc->irq = &spapr_irq_xics; 4758 smc->pre_4_1_migration = true; 4759 } 4760 4761 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4762 4763 /* 4764 * pseries-3.1 4765 */ 4766 static void spapr_machine_3_1_class_options(MachineClass *mc) 4767 { 4768 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4769 4770 spapr_machine_4_0_class_options(mc); 4771 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4772 4773 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4774 smc->update_dt_enabled = false; 4775 smc->dr_phb_enabled = false; 4776 smc->broken_host_serial_model = true; 4777 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4778 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4779 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4780 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4781 } 4782 4783 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4784 4785 /* 4786 * pseries-3.0 4787 */ 4788 4789 static void spapr_machine_3_0_class_options(MachineClass *mc) 4790 { 4791 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4792 4793 spapr_machine_3_1_class_options(mc); 4794 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4795 4796 smc->legacy_irq_allocation = true; 4797 smc->nr_xirqs = 0x400; 4798 smc->irq = &spapr_irq_xics_legacy; 4799 } 4800 4801 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4802 4803 /* 4804 * pseries-2.12 4805 */ 4806 static void spapr_machine_2_12_class_options(MachineClass *mc) 4807 { 4808 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4809 static GlobalProperty compat[] = { 4810 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4811 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4812 }; 4813 4814 spapr_machine_3_0_class_options(mc); 4815 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4816 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4817 4818 /* We depend on kvm_enabled() to choose a default value for the 4819 * hpt-max-page-size capability. Of course we can't do it here 4820 * because this is too early and the HW accelerator isn't initialzed 4821 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4822 */ 4823 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4824 } 4825 4826 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4827 4828 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4829 { 4830 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4831 4832 spapr_machine_2_12_class_options(mc); 4833 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4834 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4835 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4836 } 4837 4838 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4839 4840 /* 4841 * pseries-2.11 4842 */ 4843 4844 static void spapr_machine_2_11_class_options(MachineClass *mc) 4845 { 4846 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4847 4848 spapr_machine_2_12_class_options(mc); 4849 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4850 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4851 } 4852 4853 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4854 4855 /* 4856 * pseries-2.10 4857 */ 4858 4859 static void spapr_machine_2_10_class_options(MachineClass *mc) 4860 { 4861 spapr_machine_2_11_class_options(mc); 4862 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4863 } 4864 4865 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4866 4867 /* 4868 * pseries-2.9 4869 */ 4870 4871 static void spapr_machine_2_9_class_options(MachineClass *mc) 4872 { 4873 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4874 static GlobalProperty compat[] = { 4875 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4876 }; 4877 4878 spapr_machine_2_10_class_options(mc); 4879 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4880 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4881 smc->pre_2_10_has_unused_icps = true; 4882 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4883 } 4884 4885 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4886 4887 /* 4888 * pseries-2.8 4889 */ 4890 4891 static void spapr_machine_2_8_class_options(MachineClass *mc) 4892 { 4893 static GlobalProperty compat[] = { 4894 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4895 }; 4896 4897 spapr_machine_2_9_class_options(mc); 4898 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4899 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4900 mc->numa_mem_align_shift = 23; 4901 } 4902 4903 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4904 4905 /* 4906 * pseries-2.7 4907 */ 4908 4909 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4910 uint64_t *buid, hwaddr *pio, 4911 hwaddr *mmio32, hwaddr *mmio64, 4912 unsigned n_dma, uint32_t *liobns, 4913 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4914 { 4915 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4916 const uint64_t base_buid = 0x800000020000000ULL; 4917 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4918 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4919 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4920 const uint32_t max_index = 255; 4921 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4922 4923 uint64_t ram_top = MACHINE(spapr)->ram_size; 4924 hwaddr phb0_base, phb_base; 4925 int i; 4926 4927 /* Do we have device memory? */ 4928 if (MACHINE(spapr)->maxram_size > ram_top) { 4929 /* Can't just use maxram_size, because there may be an 4930 * alignment gap between normal and device memory regions 4931 */ 4932 ram_top = MACHINE(spapr)->device_memory->base + 4933 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4934 } 4935 4936 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4937 4938 if (index > max_index) { 4939 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4940 max_index); 4941 return false; 4942 } 4943 4944 *buid = base_buid + index; 4945 for (i = 0; i < n_dma; ++i) { 4946 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4947 } 4948 4949 phb_base = phb0_base + index * phb_spacing; 4950 *pio = phb_base + pio_offset; 4951 *mmio32 = phb_base + mmio_offset; 4952 /* 4953 * We don't set the 64-bit MMIO window, relying on the PHB's 4954 * fallback behaviour of automatically splitting a large "32-bit" 4955 * window into contiguous 32-bit and 64-bit windows 4956 */ 4957 4958 *nv2gpa = 0; 4959 *nv2atsd = 0; 4960 return true; 4961 } 4962 4963 static void spapr_machine_2_7_class_options(MachineClass *mc) 4964 { 4965 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4966 static GlobalProperty compat[] = { 4967 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4968 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4969 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4970 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4971 }; 4972 4973 spapr_machine_2_8_class_options(mc); 4974 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4975 mc->default_machine_opts = "modern-hotplug-events=off"; 4976 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4977 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4978 smc->phb_placement = phb_placement_2_7; 4979 } 4980 4981 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4982 4983 /* 4984 * pseries-2.6 4985 */ 4986 4987 static void spapr_machine_2_6_class_options(MachineClass *mc) 4988 { 4989 static GlobalProperty compat[] = { 4990 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4991 }; 4992 4993 spapr_machine_2_7_class_options(mc); 4994 mc->has_hotpluggable_cpus = false; 4995 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4996 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4997 } 4998 4999 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 5000 5001 /* 5002 * pseries-2.5 5003 */ 5004 5005 static void spapr_machine_2_5_class_options(MachineClass *mc) 5006 { 5007 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5008 static GlobalProperty compat[] = { 5009 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 5010 }; 5011 5012 spapr_machine_2_6_class_options(mc); 5013 smc->use_ohci_by_default = true; 5014 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 5015 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5016 } 5017 5018 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 5019 5020 /* 5021 * pseries-2.4 5022 */ 5023 5024 static void spapr_machine_2_4_class_options(MachineClass *mc) 5025 { 5026 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5027 5028 spapr_machine_2_5_class_options(mc); 5029 smc->dr_lmb_enabled = false; 5030 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 5031 } 5032 5033 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 5034 5035 /* 5036 * pseries-2.3 5037 */ 5038 5039 static void spapr_machine_2_3_class_options(MachineClass *mc) 5040 { 5041 static GlobalProperty compat[] = { 5042 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 5043 }; 5044 spapr_machine_2_4_class_options(mc); 5045 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 5046 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5047 } 5048 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 5049 5050 /* 5051 * pseries-2.2 5052 */ 5053 5054 static void spapr_machine_2_2_class_options(MachineClass *mc) 5055 { 5056 static GlobalProperty compat[] = { 5057 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 5058 }; 5059 5060 spapr_machine_2_3_class_options(mc); 5061 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 5062 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5063 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 5064 } 5065 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 5066 5067 /* 5068 * pseries-2.1 5069 */ 5070 5071 static void spapr_machine_2_1_class_options(MachineClass *mc) 5072 { 5073 spapr_machine_2_2_class_options(mc); 5074 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 5075 } 5076 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 5077 5078 static void spapr_machine_register_types(void) 5079 { 5080 type_register_static(&spapr_machine_info); 5081 } 5082 5083 type_init(spapr_machine_register_types) 5084