1 /* 2 * QEMU aCube Sam460ex board emulation 3 * 4 * Copyright (c) 2012 François Revol 5 * Copyright (c) 2016-2019 BALATON Zoltan 6 * 7 * This file is derived from hw/ppc440_bamboo.c, 8 * the copyright for that material belongs to the original owners. 9 * 10 * This work is licensed under the GNU GPL license version 2 or later. 11 * 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu/units.h" 16 #include "qemu/datadir.h" 17 #include "qemu/error-report.h" 18 #include "qapi/error.h" 19 #include "hw/boards.h" 20 #include "sysemu/kvm.h" 21 #include "kvm_ppc.h" 22 #include "sysemu/device_tree.h" 23 #include "sysemu/block-backend.h" 24 #include "hw/loader.h" 25 #include "elf.h" 26 #include "exec/memory.h" 27 #include "ppc440.h" 28 #include "hw/block/flash.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/reset.h" 31 #include "hw/sysbus.h" 32 #include "hw/char/serial.h" 33 #include "hw/i2c/ppc4xx_i2c.h" 34 #include "hw/i2c/smbus_eeprom.h" 35 #include "hw/usb/hcd-ehci.h" 36 #include "hw/ppc/fdt.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/intc/ppc-uic.h" 39 40 #include <libfdt.h> 41 42 #define BINARY_DEVICE_TREE_FILE "canyonlands.dtb" 43 #define UBOOT_FILENAME "u-boot-sam460-20100605.bin" 44 /* to extract the official U-Boot bin from the updater: */ 45 /* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x80000)) \ 46 if=updater/updater-460 of=u-boot-sam460-20100605.bin */ 47 48 #define PCIE0_DCRN_BASE 0x100 49 #define PCIE1_DCRN_BASE 0x120 50 51 /* from Sam460 U-Boot include/configs/Sam460ex.h */ 52 #define FLASH_BASE 0xfff00000 53 #define FLASH_BASE_H 0x4 54 #define FLASH_SIZE (1 * MiB) 55 #define UBOOT_LOAD_BASE 0xfff80000 56 #define UBOOT_SIZE 0x00080000 57 #define UBOOT_ENTRY 0xfffffffc 58 59 /* from U-Boot */ 60 #define EPAPR_MAGIC (0x45504150) 61 #define KERNEL_ADDR 0x1000000 62 #define FDT_ADDR 0x1800000 63 #define RAMDISK_ADDR 0x1900000 64 65 /* Sam460ex IRQ MAP: 66 IRQ0 = ETH_INT 67 IRQ1 = FPGA_INT 68 IRQ2 = PCI_INT (PCIA, PCIB, PCIC, PCIB) 69 IRQ3 = FPGA_INT2 70 IRQ11 = RTC_INT 71 IRQ12 = SM502_INT 72 */ 73 74 #define CPU_FREQ 1150000000 75 #define PLB_FREQ 230000000 76 #define OPB_FREQ 115000000 77 #define EBC_FREQ 115000000 78 #define UART_FREQ 11059200 79 80 struct boot_info { 81 uint32_t dt_base; 82 uint32_t dt_size; 83 uint32_t entry; 84 }; 85 86 static int sam460ex_load_uboot(void) 87 { 88 /* 89 * This first creates 1MiB of flash memory mapped at the end of 90 * the 32-bit address space (0xFFF00000..0xFFFFFFFF). 91 * 92 * If_PFLASH unit 0 is defined, the flash memory is initialized 93 * from that block backend. 94 * 95 * Else, it's initialized to zero. And then 512KiB of ROM get 96 * mapped on top of its second half (0xFFF80000..0xFFFFFFFF), 97 * initialized from u-boot-sam460-20100605.bin. 98 * 99 * This doesn't smell right. 100 * 101 * The physical hardware appears to have 512KiB flash memory. 102 * 103 * TODO Figure out what we really need here, and clean this up. 104 */ 105 106 DriveInfo *dinfo; 107 108 dinfo = drive_get(IF_PFLASH, 0, 0); 109 if (!pflash_cfi01_register(FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32), 110 "sam460ex.flash", FLASH_SIZE, 111 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 112 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1)) { 113 error_report("Error registering flash memory"); 114 /* XXX: return an error instead? */ 115 exit(1); 116 } 117 118 if (!dinfo) { 119 /*error_report("No flash image given with the 'pflash' parameter," 120 " using default u-boot image");*/ 121 rom_add_file_fixed(UBOOT_FILENAME, 122 UBOOT_LOAD_BASE | ((hwaddr)FLASH_BASE_H << 32), 123 -1); 124 } 125 126 return 0; 127 } 128 129 static int sam460ex_load_device_tree(MachineState *machine, 130 hwaddr addr, 131 hwaddr initrd_base, 132 hwaddr initrd_size) 133 { 134 uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(machine->ram_size) }; 135 char *filename; 136 int fdt_size; 137 void *fdt; 138 uint32_t tb_freq = CPU_FREQ; 139 uint32_t clock_freq = CPU_FREQ; 140 int offset; 141 142 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); 143 if (!filename) { 144 error_report("Couldn't find dtb file `%s'", BINARY_DEVICE_TREE_FILE); 145 exit(1); 146 } 147 fdt = load_device_tree(filename, &fdt_size); 148 if (!fdt) { 149 error_report("Couldn't load dtb file `%s'", filename); 150 g_free(filename); 151 exit(1); 152 } 153 g_free(filename); 154 155 /* Manipulate device tree in memory. */ 156 157 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 158 sizeof(mem_reg_property)); 159 160 /* default FDT doesn't have a /chosen node... */ 161 qemu_fdt_add_subnode(fdt, "/chosen"); 162 163 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", initrd_base); 164 165 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 166 (initrd_base + initrd_size)); 167 168 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 169 machine->kernel_cmdline); 170 171 /* Copy data from the host device tree into the guest. Since the guest can 172 * directly access the timebase without host involvement, we must expose 173 * the correct frequencies. */ 174 if (kvm_enabled()) { 175 tb_freq = kvmppc_get_tbfreq(); 176 clock_freq = kvmppc_get_clockfreq(); 177 } 178 179 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency", 180 clock_freq); 181 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency", 182 tb_freq); 183 184 /* Remove cpm node if it exists (it is not emulated) */ 185 offset = fdt_path_offset(fdt, "/cpm"); 186 if (offset >= 0) { 187 _FDT(fdt_nop_node(fdt, offset)); 188 } 189 190 /* set serial port clocks */ 191 offset = fdt_node_offset_by_compatible(fdt, -1, "ns16550"); 192 while (offset >= 0) { 193 _FDT(fdt_setprop_cell(fdt, offset, "clock-frequency", UART_FREQ)); 194 offset = fdt_node_offset_by_compatible(fdt, offset, "ns16550"); 195 } 196 197 /* some more clocks */ 198 qemu_fdt_setprop_cell(fdt, "/plb", "clock-frequency", 199 PLB_FREQ); 200 qemu_fdt_setprop_cell(fdt, "/plb/opb", "clock-frequency", 201 OPB_FREQ); 202 qemu_fdt_setprop_cell(fdt, "/plb/opb/ebc", "clock-frequency", 203 EBC_FREQ); 204 205 rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); 206 207 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ 208 machine->fdt = fdt; 209 210 return fdt_size; 211 } 212 213 /* Create reset TLB entries for BookE, mapping only the flash memory. */ 214 static void mmubooke_create_initial_mapping_uboot(CPUPPCState *env) 215 { 216 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 217 218 /* on reset the flash is mapped by a shadow TLB, 219 * but since we don't implement them we need to use 220 * the same values U-Boot will use to avoid a fault. 221 */ 222 tlb->attr = 0; 223 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 224 tlb->size = 0x10000000; /* up to 0xffffffff */ 225 tlb->EPN = 0xf0000000 & TARGET_PAGE_MASK; 226 tlb->RPN = (0xf0000000 & TARGET_PAGE_MASK) | 0x4; 227 tlb->PID = 0; 228 } 229 230 /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ 231 static void mmubooke_create_initial_mapping(CPUPPCState *env, 232 target_ulong va, 233 hwaddr pa) 234 { 235 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 236 237 tlb->attr = 0; 238 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 239 tlb->size = 1 << 31; /* up to 0x80000000 */ 240 tlb->EPN = va & TARGET_PAGE_MASK; 241 tlb->RPN = pa & TARGET_PAGE_MASK; 242 tlb->PID = 0; 243 } 244 245 static void main_cpu_reset(void *opaque) 246 { 247 PowerPCCPU *cpu = opaque; 248 CPUPPCState *env = &cpu->env; 249 struct boot_info *bi = env->load_info; 250 251 cpu_reset(CPU(cpu)); 252 253 /* either we have a kernel to boot or we jump to U-Boot */ 254 if (bi->entry != UBOOT_ENTRY) { 255 env->gpr[1] = (16 * MiB) - 8; 256 env->gpr[3] = FDT_ADDR; 257 env->nip = bi->entry; 258 259 /* Create a mapping for the kernel. */ 260 mmubooke_create_initial_mapping(env, 0, 0); 261 env->gpr[6] = tswap32(EPAPR_MAGIC); 262 env->gpr[7] = (16 * MiB) - 8; /* bi->ima_size; */ 263 264 } else { 265 env->nip = UBOOT_ENTRY; 266 mmubooke_create_initial_mapping_uboot(env); 267 } 268 } 269 270 static void sam460ex_init(MachineState *machine) 271 { 272 MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1); 273 DeviceState *uic[4]; 274 int i; 275 PCIBus *pci_bus; 276 PowerPCCPU *cpu; 277 CPUPPCState *env; 278 I2CBus *i2c; 279 hwaddr entry = UBOOT_ENTRY; 280 target_long initrd_size = 0; 281 DeviceState *dev; 282 SysBusDevice *sbdev; 283 struct boot_info *boot_info; 284 uint8_t *spd_data; 285 int success; 286 287 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 288 env = &cpu->env; 289 if (env->mmu_model != POWERPC_MMU_BOOKE) { 290 error_report("Only MMU model BookE is supported by this machine."); 291 exit(1); 292 } 293 294 qemu_register_reset(main_cpu_reset, cpu); 295 boot_info = g_malloc0(sizeof(*boot_info)); 296 env->load_info = boot_info; 297 298 ppc_booke_timers_init(cpu, CPU_FREQ, 0); 299 ppc_dcr_init(env, NULL, NULL); 300 301 /* PLB arbitrer */ 302 dev = qdev_new(TYPE_PPC4xx_PLB); 303 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); 304 object_unref(OBJECT(dev)); 305 306 /* interrupt controllers */ 307 for (i = 0; i < ARRAY_SIZE(uic); i++) { 308 /* 309 * UICs 1, 2 and 3 are cascaded through UIC 0. 310 * input_ints[n] is the interrupt number on UIC 0 which 311 * the INT output of UIC n is connected to. The CINT output 312 * of UIC n connects to input_ints[n] + 1. 313 * The entry in input_ints[] for UIC 0 is ignored, because UIC 0's 314 * INT and CINT outputs are connected to the CPU. 315 */ 316 const int input_ints[] = { -1, 30, 10, 16 }; 317 318 uic[i] = qdev_new(TYPE_PPC_UIC); 319 qdev_prop_set_uint32(uic[i], "dcr-base", 0xc0 + i * 0x10); 320 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uic[i]), cpu, &error_fatal); 321 object_unref(OBJECT(uic[i])); 322 323 sbdev = SYS_BUS_DEVICE(uic[i]); 324 if (i == 0) { 325 sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT, 326 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT)); 327 sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT, 328 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT)); 329 } else { 330 sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT, 331 qdev_get_gpio_in(uic[0], input_ints[i])); 332 sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT, 333 qdev_get_gpio_in(uic[0], input_ints[i] + 1)); 334 } 335 } 336 337 /* SDRAM controller */ 338 /* The SoC could also handle 4 GiB but firmware does not work with that. */ 339 if (machine->ram_size > 2 * GiB) { 340 error_report("Memory over 2 GiB is not supported"); 341 exit(1); 342 } 343 /* Firmware needs at least 64 MiB */ 344 if (machine->ram_size < 64 * MiB) { 345 error_report("Memory below 64 MiB is not supported"); 346 exit(1); 347 } 348 dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR2); 349 object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram), 350 &error_abort); 351 /* 352 * Put all RAM on first bank because board has one slot 353 * and firmware only checks that 354 */ 355 object_property_set_int(OBJECT(dev), "nbanks", 1, &error_abort); 356 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); 357 object_unref(OBJECT(dev)); 358 /* FIXME: does 460EX have ECC interrupts? */ 359 /* Enable SDRAM memory regions as we may boot without firmware */ 360 ppc4xx_sdram_ddr2_enable(PPC4xx_SDRAM_DDR2(dev)); 361 362 /* IIC controllers and devices */ 363 dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, 364 qdev_get_gpio_in(uic[0], 2)); 365 i2c = PPC4xx_I2C(dev)->bus; 366 /* SPD EEPROM on RAM module */ 367 spd_data = spd_data_generate(machine->ram_size < 128 * MiB ? DDR : DDR2, 368 machine->ram_size); 369 spd_data[20] = 4; /* SO-DIMM module */ 370 smbus_eeprom_init_one(i2c, 0x50, spd_data); 371 /* RTC */ 372 i2c_slave_create_simple(i2c, "m41t80", 0x68); 373 374 dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, 375 qdev_get_gpio_in(uic[0], 3)); 376 377 /* External bus controller */ 378 dev = qdev_new(TYPE_PPC4xx_EBC); 379 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); 380 object_unref(OBJECT(dev)); 381 382 /* CPR */ 383 ppc4xx_cpr_init(env); 384 385 /* PLB to AHB bridge */ 386 ppc4xx_ahb_init(env); 387 388 /* System DCRs */ 389 ppc4xx_sdr_init(env); 390 391 /* MAL */ 392 dev = qdev_new(TYPE_PPC4xx_MAL); 393 qdev_prop_set_uint8(dev, "txc-num", 4); 394 qdev_prop_set_uint8(dev, "rxc-num", 16); 395 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); 396 object_unref(OBJECT(dev)); 397 sbdev = SYS_BUS_DEVICE(dev); 398 for (i = 0; i < ARRAY_SIZE(PPC4xx_MAL(dev)->irqs); i++) { 399 sysbus_connect_irq(sbdev, i, qdev_get_gpio_in(uic[2], 3 + i)); 400 } 401 402 /* DMA */ 403 ppc4xx_dma_init(env, 0x200); 404 405 /* 256K of L2 cache as memory */ 406 ppc4xx_l2sram_init(env); 407 /* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */ 408 memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 * KiB, 409 &error_abort); 410 memory_region_add_subregion(get_system_memory(), 0x400000000LL, 411 l2cache_ram); 412 413 /* USB */ 414 sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, 415 qdev_get_gpio_in(uic[2], 29)); 416 dev = qdev_new("sysbus-ohci"); 417 qdev_prop_set_string(dev, "masterbus", "usb-bus.0"); 418 qdev_prop_set_uint32(dev, "num-ports", 6); 419 sbdev = SYS_BUS_DEVICE(dev); 420 sysbus_realize_and_unref(sbdev, &error_fatal); 421 sysbus_mmio_map(sbdev, 0, 0x4bffd0000); 422 sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(uic[2], 30)); 423 usb_create_simple(usb_bus_find(-1), "usb-kbd"); 424 usb_create_simple(usb_bus_find(-1), "usb-mouse"); 425 426 /* PCIe buses */ 427 dev = qdev_new(TYPE_PPC460EX_PCIE_HOST); 428 qdev_prop_set_int32(dev, "busnum", 0); 429 qdev_prop_set_int32(dev, "dcrn-base", PCIE0_DCRN_BASE); 430 object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort); 431 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 432 433 dev = qdev_new(TYPE_PPC460EX_PCIE_HOST); 434 qdev_prop_set_int32(dev, "busnum", 1); 435 qdev_prop_set_int32(dev, "dcrn-base", PCIE1_DCRN_BASE); 436 object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort); 437 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 438 439 /* PCI bus */ 440 /* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */ 441 dev = sysbus_create_simple(TYPE_PPC440_PCIX_HOST, 0xc0ec00000, 442 qdev_get_gpio_in(uic[1], 0)); 443 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, 0xc08000000); 444 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); 445 446 /* PCI devices */ 447 pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501"); 448 /* SoC has a single SATA port but we don't emulate that yet 449 * However, firmware and usual clients have driver for SiI311x 450 * so add one for convenience by default */ 451 if (defaults_enabled()) { 452 pci_create_simple(pci_bus, -1, "sii3112"); 453 } 454 455 /* SoC has 4 UARTs 456 * but board has only one wired and two are present in fdt */ 457 if (serial_hd(0) != NULL) { 458 serial_mm_init(get_system_memory(), 0x4ef600300, 0, 459 qdev_get_gpio_in(uic[1], 1), 460 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 461 DEVICE_BIG_ENDIAN); 462 } 463 if (serial_hd(1) != NULL) { 464 serial_mm_init(get_system_memory(), 0x4ef600400, 0, 465 qdev_get_gpio_in(uic[0], 1), 466 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 467 DEVICE_BIG_ENDIAN); 468 } 469 470 /* Load U-Boot image. */ 471 if (!machine->kernel_filename) { 472 success = sam460ex_load_uboot(); 473 if (success < 0) { 474 error_report("could not load firmware"); 475 exit(1); 476 } 477 } 478 479 /* Load kernel. */ 480 if (machine->kernel_filename) { 481 hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 482 success = load_uimage(machine->kernel_filename, &entry, &loadaddr, 483 NULL, NULL, NULL); 484 if (success < 0) { 485 uint64_t elf_entry; 486 487 success = load_elf(machine->kernel_filename, NULL, NULL, NULL, 488 &elf_entry, NULL, NULL, NULL, 489 1, PPC_ELF_MACHINE, 0, 0); 490 entry = elf_entry; 491 } 492 /* XXX try again as binary */ 493 if (success < 0) { 494 error_report("could not load kernel '%s'", 495 machine->kernel_filename); 496 exit(1); 497 } 498 } 499 500 /* Load initrd. */ 501 if (machine->initrd_filename) { 502 initrd_size = load_image_targphys(machine->initrd_filename, 503 RAMDISK_ADDR, 504 machine->ram_size - RAMDISK_ADDR); 505 if (initrd_size < 0) { 506 error_report("could not load ram disk '%s' at %x", 507 machine->initrd_filename, RAMDISK_ADDR); 508 exit(1); 509 } 510 } 511 512 /* If we're loading a kernel directly, we must load the device tree too. */ 513 if (machine->kernel_filename) { 514 int dt_size; 515 516 dt_size = sam460ex_load_device_tree(machine, FDT_ADDR, 517 RAMDISK_ADDR, initrd_size); 518 519 boot_info->dt_base = FDT_ADDR; 520 boot_info->dt_size = dt_size; 521 } 522 523 boot_info->entry = entry; 524 } 525 526 static void sam460ex_machine_init(MachineClass *mc) 527 { 528 mc->desc = "aCube Sam460ex"; 529 mc->init = sam460ex_init; 530 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb"); 531 mc->default_ram_size = 512 * MiB; 532 mc->default_ram_id = "ppc4xx.sdram"; 533 } 534 535 DEFINE_MACHINE("sam460ex", sam460ex_machine_init) 536