1 /* 2 * QEMU aCube Sam460ex board emulation 3 * 4 * Copyright (c) 2012 François Revol 5 * Copyright (c) 2016-2018 BALATON Zoltan 6 * 7 * This file is derived from hw/ppc440_bamboo.c, 8 * the copyright for that material belongs to the original owners. 9 * 10 * This work is licensed under the GNU GPL license version 2 or later. 11 * 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu/units.h" 16 #include "qemu-common.h" 17 #include "qemu/error-report.h" 18 #include "qapi/error.h" 19 #include "hw/hw.h" 20 #include "hw/boards.h" 21 #include "sysemu/kvm.h" 22 #include "kvm_ppc.h" 23 #include "sysemu/device_tree.h" 24 #include "sysemu/block-backend.h" 25 #include "hw/loader.h" 26 #include "elf.h" 27 #include "exec/address-spaces.h" 28 #include "exec/memory.h" 29 #include "ppc440.h" 30 #include "ppc405.h" 31 #include "hw/block/flash.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/qtest.h" 34 #include "hw/sysbus.h" 35 #include "hw/char/serial.h" 36 #include "hw/i2c/ppc4xx_i2c.h" 37 #include "hw/i2c/smbus.h" 38 #include "hw/usb/hcd-ehci.h" 39 40 #include <libfdt.h> 41 42 #define BINARY_DEVICE_TREE_FILE "canyonlands.dtb" 43 #define UBOOT_FILENAME "u-boot-sam460-20100605.bin" 44 /* to extract the official U-Boot bin from the updater: */ 45 /* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x80000)) \ 46 if=updater/updater-460 of=u-boot-sam460-20100605.bin */ 47 48 /* from Sam460 U-Boot include/configs/Sam460ex.h */ 49 #define FLASH_BASE 0xfff00000 50 #define FLASH_BASE_H 0x4 51 #define FLASH_SIZE (1 * MiB) 52 #define UBOOT_LOAD_BASE 0xfff80000 53 #define UBOOT_SIZE 0x00080000 54 #define UBOOT_ENTRY 0xfffffffc 55 56 /* from U-Boot */ 57 #define EPAPR_MAGIC (0x45504150) 58 #define KERNEL_ADDR 0x1000000 59 #define FDT_ADDR 0x1800000 60 #define RAMDISK_ADDR 0x1900000 61 62 /* Sam460ex IRQ MAP: 63 IRQ0 = ETH_INT 64 IRQ1 = FPGA_INT 65 IRQ2 = PCI_INT (PCIA, PCIB, PCIC, PCIB) 66 IRQ3 = FPGA_INT2 67 IRQ11 = RTC_INT 68 IRQ12 = SM502_INT 69 */ 70 71 #define CPU_FREQ 1150000000 72 #define PLB_FREQ 230000000 73 #define OPB_FREQ 115000000 74 #define EBC_FREQ 115000000 75 #define UART_FREQ 11059200 76 #define SDRAM_NR_BANKS 4 77 78 /* FIXME: See u-boot.git 8ac41e, also fix in ppc440_uc.c */ 79 static const unsigned int ppc460ex_sdram_bank_sizes[] = { 80 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 0 81 }; 82 83 struct boot_info { 84 uint32_t dt_base; 85 uint32_t dt_size; 86 uint32_t entry; 87 }; 88 89 /*****************************************************************************/ 90 /* SPD eeprom content from mips_malta.c */ 91 92 struct _eeprom24c0x_t { 93 uint8_t tick; 94 uint8_t address; 95 uint8_t command; 96 uint8_t ack; 97 uint8_t scl; 98 uint8_t sda; 99 uint8_t data; 100 uint8_t contents[256]; 101 }; 102 103 typedef struct _eeprom24c0x_t eeprom24c0x_t; 104 105 static eeprom24c0x_t spd_eeprom = { 106 .contents = { 107 /* 00000000: */ 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00, 108 /* 00000008: */ 0x04, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01, 109 /* 00000010: */ 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 110 /* 00000018: */ 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF, 111 /* 00000020: */ 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00, 112 /* 00000028: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 113 /* 00000030: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 114 /* 00000038: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0, 115 /* 00000040: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 116 /* 00000048: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 117 /* 00000050: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 118 /* 00000058: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 119 /* 00000060: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 120 /* 00000068: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 121 /* 00000070: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 122 /* 00000078: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4, 123 }, 124 }; 125 126 static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size) 127 { 128 enum { SDR = 0x4, DDR1 = 0x7, DDR2 = 0x8 } type; 129 uint8_t *spd = spd_eeprom.contents; 130 uint8_t nbanks = 0; 131 uint16_t density = 0; 132 int i; 133 134 /* work in terms of MB */ 135 ram_size /= MiB; 136 137 while ((ram_size >= 4) && (nbanks <= 2)) { 138 int sz_log2 = MIN(31 - clz32(ram_size), 14); 139 nbanks++; 140 density |= 1 << (sz_log2 - 2); 141 ram_size -= 1 << sz_log2; 142 } 143 144 /* split to 2 banks if possible */ 145 if ((nbanks == 1) && (density > 1)) { 146 nbanks++; 147 density >>= 1; 148 } 149 150 if (density & 0xff00) { 151 density = (density & 0xe0) | ((density >> 8) & 0x1f); 152 type = DDR2; 153 } else if (!(density & 0x1f)) { 154 type = DDR2; 155 } else { 156 type = SDR; 157 } 158 159 if (ram_size) { 160 warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB" 161 " of SDRAM", ram_size); 162 } 163 164 /* fill in SPD memory information */ 165 spd[2] = type; 166 spd[5] = nbanks; 167 spd[31] = density; 168 169 /* XXX: this is totally random */ 170 spd[9] = 0x10; /* CAS tcyc */ 171 spd[18] = 0x20; /* CAS bit */ 172 spd[23] = 0x10; /* CAS tcyc */ 173 spd[25] = 0x10; /* CAS tcyc */ 174 175 /* checksum */ 176 spd[63] = 0; 177 for (i = 0; i < 63; i++) { 178 spd[63] += spd[i]; 179 } 180 181 /* copy for SMBUS */ 182 memcpy(eeprom, spd, sizeof(spd_eeprom.contents)); 183 } 184 185 static void generate_eeprom_serial(uint8_t *eeprom) 186 { 187 int i, pos = 0; 188 uint8_t mac[6] = { 0x00 }; 189 uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 }; 190 191 /* version */ 192 eeprom[pos++] = 0x01; 193 194 /* count */ 195 eeprom[pos++] = 0x02; 196 197 /* MAC address */ 198 eeprom[pos++] = 0x01; /* MAC */ 199 eeprom[pos++] = 0x06; /* length */ 200 memcpy(&eeprom[pos], mac, sizeof(mac)); 201 pos += sizeof(mac); 202 203 /* serial number */ 204 eeprom[pos++] = 0x02; /* serial */ 205 eeprom[pos++] = 0x05; /* length */ 206 memcpy(&eeprom[pos], sn, sizeof(sn)); 207 pos += sizeof(sn); 208 209 /* checksum */ 210 eeprom[pos] = 0; 211 for (i = 0; i < pos; i++) { 212 eeprom[pos] += eeprom[i]; 213 } 214 } 215 216 /*****************************************************************************/ 217 218 static int sam460ex_load_uboot(void) 219 { 220 DriveInfo *dinfo; 221 BlockBackend *blk = NULL; 222 hwaddr base = FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32); 223 long bios_size = FLASH_SIZE; 224 int fl_sectors; 225 226 dinfo = drive_get(IF_PFLASH, 0, 0); 227 if (dinfo) { 228 blk = blk_by_legacy_dinfo(dinfo); 229 bios_size = blk_getlength(blk); 230 } 231 fl_sectors = (bios_size + 65535) >> 16; 232 233 if (!pflash_cfi01_register(base, NULL, "sam460ex.flash", bios_size, 234 blk, 64 * KiB, fl_sectors, 235 1, 0x89, 0x18, 0x0000, 0x0, 1)) { 236 error_report("qemu: Error registering flash memory."); 237 /* XXX: return an error instead? */ 238 exit(1); 239 } 240 241 if (!blk) { 242 /*error_report("No flash image given with the 'pflash' parameter," 243 " using default u-boot image");*/ 244 base = UBOOT_LOAD_BASE | ((hwaddr)FLASH_BASE_H << 32); 245 rom_add_file_fixed(UBOOT_FILENAME, base, -1); 246 } 247 248 return 0; 249 } 250 251 static int sam460ex_load_device_tree(hwaddr addr, 252 uint32_t ramsize, 253 hwaddr initrd_base, 254 hwaddr initrd_size, 255 const char *kernel_cmdline) 256 { 257 int ret = -1; 258 uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) }; 259 char *filename; 260 int fdt_size; 261 void *fdt; 262 uint32_t tb_freq = CPU_FREQ; 263 uint32_t clock_freq = CPU_FREQ; 264 int offset; 265 266 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); 267 if (!filename) { 268 goto out; 269 } 270 fdt = load_device_tree(filename, &fdt_size); 271 g_free(filename); 272 if (fdt == NULL) { 273 goto out; 274 } 275 276 /* Manipulate device tree in memory. */ 277 278 ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 279 sizeof(mem_reg_property)); 280 if (ret < 0) { 281 error_report("couldn't set /memory/reg"); 282 } 283 284 /* default FDT doesn't have a /chosen node... */ 285 qemu_fdt_add_subnode(fdt, "/chosen"); 286 287 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 288 initrd_base); 289 if (ret < 0) { 290 error_report("couldn't set /chosen/linux,initrd-start"); 291 } 292 293 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 294 (initrd_base + initrd_size)); 295 if (ret < 0) { 296 error_report("couldn't set /chosen/linux,initrd-end"); 297 } 298 299 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 300 kernel_cmdline); 301 if (ret < 0) { 302 error_report("couldn't set /chosen/bootargs"); 303 } 304 305 /* Copy data from the host device tree into the guest. Since the guest can 306 * directly access the timebase without host involvement, we must expose 307 * the correct frequencies. */ 308 if (kvm_enabled()) { 309 tb_freq = kvmppc_get_tbfreq(); 310 clock_freq = kvmppc_get_clockfreq(); 311 } 312 313 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency", 314 clock_freq); 315 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency", 316 tb_freq); 317 318 /* Remove cpm node if it exists (it is not emulated) */ 319 offset = fdt_path_offset(fdt, "/cpm"); 320 if (offset >= 0) { 321 fdt_nop_node(fdt, offset); 322 } 323 324 /* set serial port clocks */ 325 offset = fdt_node_offset_by_compatible(fdt, -1, "ns16550"); 326 while (offset >= 0) { 327 fdt_setprop_cell(fdt, offset, "clock-frequency", UART_FREQ); 328 offset = fdt_node_offset_by_compatible(fdt, offset, "ns16550"); 329 } 330 331 /* some more clocks */ 332 qemu_fdt_setprop_cell(fdt, "/plb", "clock-frequency", 333 PLB_FREQ); 334 qemu_fdt_setprop_cell(fdt, "/plb/opb", "clock-frequency", 335 OPB_FREQ); 336 qemu_fdt_setprop_cell(fdt, "/plb/opb/ebc", "clock-frequency", 337 EBC_FREQ); 338 339 rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); 340 g_free(fdt); 341 ret = fdt_size; 342 343 out: 344 345 return ret; 346 } 347 348 /* Create reset TLB entries for BookE, mapping only the flash memory. */ 349 static void mmubooke_create_initial_mapping_uboot(CPUPPCState *env) 350 { 351 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 352 353 /* on reset the flash is mapped by a shadow TLB, 354 * but since we don't implement them we need to use 355 * the same values U-Boot will use to avoid a fault. 356 */ 357 tlb->attr = 0; 358 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 359 tlb->size = 0x10000000; /* up to 0xffffffff */ 360 tlb->EPN = 0xf0000000 & TARGET_PAGE_MASK; 361 tlb->RPN = (0xf0000000 & TARGET_PAGE_MASK) | 0x4; 362 tlb->PID = 0; 363 } 364 365 /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ 366 static void mmubooke_create_initial_mapping(CPUPPCState *env, 367 target_ulong va, 368 hwaddr pa) 369 { 370 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 371 372 tlb->attr = 0; 373 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 374 tlb->size = 1 << 31; /* up to 0x80000000 */ 375 tlb->EPN = va & TARGET_PAGE_MASK; 376 tlb->RPN = pa & TARGET_PAGE_MASK; 377 tlb->PID = 0; 378 } 379 380 static void main_cpu_reset(void *opaque) 381 { 382 PowerPCCPU *cpu = opaque; 383 CPUPPCState *env = &cpu->env; 384 struct boot_info *bi = env->load_info; 385 386 cpu_reset(CPU(cpu)); 387 388 /* either we have a kernel to boot or we jump to U-Boot */ 389 if (bi->entry != UBOOT_ENTRY) { 390 env->gpr[1] = (16 * MiB) - 8; 391 env->gpr[3] = FDT_ADDR; 392 env->nip = bi->entry; 393 394 /* Create a mapping for the kernel. */ 395 mmubooke_create_initial_mapping(env, 0, 0); 396 env->gpr[6] = tswap32(EPAPR_MAGIC); 397 env->gpr[7] = (16 * MiB) - 8; /* bi->ima_size; */ 398 399 } else { 400 env->nip = UBOOT_ENTRY; 401 mmubooke_create_initial_mapping_uboot(env); 402 } 403 } 404 405 static void sam460ex_init(MachineState *machine) 406 { 407 MemoryRegion *address_space_mem = get_system_memory(); 408 MemoryRegion *isa = g_new(MemoryRegion, 1); 409 MemoryRegion *ram_memories = g_new(MemoryRegion, SDRAM_NR_BANKS); 410 hwaddr ram_bases[SDRAM_NR_BANKS]; 411 hwaddr ram_sizes[SDRAM_NR_BANKS]; 412 MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1); 413 qemu_irq *irqs, *uic[4]; 414 PCIBus *pci_bus; 415 PowerPCCPU *cpu; 416 CPUPPCState *env; 417 PPC4xxI2CState *i2c[2]; 418 hwaddr entry = UBOOT_ENTRY; 419 hwaddr loadaddr = 0; 420 target_long initrd_size = 0; 421 DeviceState *dev; 422 SysBusDevice *sbdev; 423 int success; 424 int i; 425 struct boot_info *boot_info; 426 const size_t smbus_eeprom_size = 8 * 256; 427 uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size); 428 429 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 430 env = &cpu->env; 431 if (env->mmu_model != POWERPC_MMU_BOOKE) { 432 error_report("Only MMU model BookE is supported by this machine."); 433 exit(1); 434 } 435 436 #ifdef TARGET_PPCEMB 437 if (!qtest_enabled()) { 438 warn_report("qemu-system-ppcemb is deprecated, " 439 "please use qemu-system-ppc instead."); 440 } 441 #endif 442 443 qemu_register_reset(main_cpu_reset, cpu); 444 boot_info = g_malloc0(sizeof(*boot_info)); 445 env->load_info = boot_info; 446 447 ppc_booke_timers_init(cpu, CPU_FREQ, 0); 448 ppc_dcr_init(env, NULL, NULL); 449 450 /* PLB arbitrer */ 451 ppc4xx_plb_init(env); 452 453 /* interrupt controllers */ 454 irqs = g_malloc0(sizeof(*irqs) * PPCUIC_OUTPUT_NB); 455 irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; 456 irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; 457 uic[0] = ppcuic_init(env, irqs, 0xc0, 0, 1); 458 uic[1] = ppcuic_init(env, &uic[0][30], 0xd0, 0, 1); 459 uic[2] = ppcuic_init(env, &uic[0][10], 0xe0, 0, 1); 460 uic[3] = ppcuic_init(env, &uic[0][16], 0xf0, 0, 1); 461 462 /* SDRAM controller */ 463 memset(ram_bases, 0, sizeof(ram_bases)); 464 memset(ram_sizes, 0, sizeof(ram_sizes)); 465 /* put all RAM on first bank because board has one slot 466 * and firmware only checks that */ 467 machine->ram_size = ppc4xx_sdram_adjust(machine->ram_size, 1, 468 ram_memories, ram_bases, ram_sizes, 469 ppc460ex_sdram_bank_sizes); 470 471 /* FIXME: does 460EX have ECC interrupts? */ 472 ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories, 473 ram_bases, ram_sizes, 1); 474 475 /* generate SPD EEPROM data */ 476 for (i = 0; i < SDRAM_NR_BANKS; i++) { 477 generate_eeprom_spd(&smbus_eeprom_buf[i * 256], ram_sizes[i]); 478 } 479 generate_eeprom_serial(&smbus_eeprom_buf[4 * 256]); 480 generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]); 481 482 /* IIC controllers */ 483 dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, uic[0][2]); 484 i2c[0] = PPC4xx_I2C(dev); 485 object_property_set_bool(OBJECT(dev), true, "realized", NULL); 486 smbus_eeprom_init(i2c[0]->bus, 8, smbus_eeprom_buf, smbus_eeprom_size); 487 g_free(smbus_eeprom_buf); 488 i2c_create_slave(i2c[0]->bus, "m41t80", 0x68); 489 490 dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, uic[0][3]); 491 i2c[1] = PPC4xx_I2C(dev); 492 493 /* External bus controller */ 494 ppc405_ebc_init(env); 495 496 /* CPR */ 497 ppc4xx_cpr_init(env); 498 499 /* PLB to AHB bridge */ 500 ppc4xx_ahb_init(env); 501 502 /* System DCRs */ 503 ppc4xx_sdr_init(env); 504 505 /* MAL */ 506 ppc4xx_mal_init(env, 4, 16, &uic[2][3]); 507 508 /* DMA */ 509 ppc4xx_dma_init(env, 0x200); 510 511 /* 256K of L2 cache as memory */ 512 ppc4xx_l2sram_init(env); 513 /* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */ 514 memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 * KiB, 515 &error_abort); 516 memory_region_add_subregion(address_space_mem, 0x400000000LL, l2cache_ram); 517 518 /* USB */ 519 sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, uic[2][29]); 520 dev = qdev_create(NULL, "sysbus-ohci"); 521 qdev_prop_set_string(dev, "masterbus", "usb-bus.0"); 522 qdev_prop_set_uint32(dev, "num-ports", 6); 523 qdev_init_nofail(dev); 524 sbdev = SYS_BUS_DEVICE(dev); 525 sysbus_mmio_map(sbdev, 0, 0x4bffd0000); 526 sysbus_connect_irq(sbdev, 0, uic[2][30]); 527 usb_create_simple(usb_bus_find(-1), "usb-kbd"); 528 usb_create_simple(usb_bus_find(-1), "usb-mouse"); 529 530 /* PCI bus */ 531 ppc460ex_pcie_init(env); 532 /* FIXME: is this correct? */ 533 dev = sysbus_create_varargs("ppc440-pcix-host", 0xc0ec00000, 534 uic[1][0], uic[1][20], uic[1][21], uic[1][22], 535 NULL); 536 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 537 if (!pci_bus) { 538 error_report("couldn't create PCI controller!"); 539 exit(1); 540 } 541 memory_region_init_alias(isa, NULL, "isa_mmio", get_system_io(), 542 0, 0x10000); 543 memory_region_add_subregion(get_system_memory(), 0xc08000000, isa); 544 545 /* PCI devices */ 546 pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501"); 547 /* SoC has a single SATA port but we don't emulate that yet 548 * However, firmware and usual clients have driver for SiI311x 549 * so add one for convenience by default */ 550 if (defaults_enabled()) { 551 pci_create_simple(pci_bus, -1, "sii3112"); 552 } 553 554 /* SoC has 4 UARTs 555 * but board has only one wired and two are present in fdt */ 556 if (serial_hd(0) != NULL) { 557 serial_mm_init(address_space_mem, 0x4ef600300, 0, uic[1][1], 558 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 559 DEVICE_BIG_ENDIAN); 560 } 561 if (serial_hd(1) != NULL) { 562 serial_mm_init(address_space_mem, 0x4ef600400, 0, uic[0][1], 563 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 564 DEVICE_BIG_ENDIAN); 565 } 566 567 /* Load U-Boot image. */ 568 if (!machine->kernel_filename) { 569 success = sam460ex_load_uboot(); 570 if (success < 0) { 571 error_report("qemu: could not load firmware"); 572 exit(1); 573 } 574 } 575 576 /* Load kernel. */ 577 if (machine->kernel_filename) { 578 success = load_uimage(machine->kernel_filename, &entry, &loadaddr, 579 NULL, NULL, NULL); 580 if (success < 0) { 581 uint64_t elf_entry, elf_lowaddr; 582 583 success = load_elf(machine->kernel_filename, NULL, NULL, &elf_entry, 584 &elf_lowaddr, NULL, 1, PPC_ELF_MACHINE, 0, 0); 585 entry = elf_entry; 586 loadaddr = elf_lowaddr; 587 } 588 /* XXX try again as binary */ 589 if (success < 0) { 590 error_report("qemu: could not load kernel '%s'", 591 machine->kernel_filename); 592 exit(1); 593 } 594 } 595 596 /* Load initrd. */ 597 if (machine->initrd_filename) { 598 initrd_size = load_image_targphys(machine->initrd_filename, 599 RAMDISK_ADDR, 600 machine->ram_size - RAMDISK_ADDR); 601 if (initrd_size < 0) { 602 error_report("qemu: could not load ram disk '%s' at %x", 603 machine->initrd_filename, RAMDISK_ADDR); 604 exit(1); 605 } 606 } 607 608 /* If we're loading a kernel directly, we must load the device tree too. */ 609 if (machine->kernel_filename) { 610 int dt_size; 611 612 dt_size = sam460ex_load_device_tree(FDT_ADDR, machine->ram_size, 613 RAMDISK_ADDR, initrd_size, 614 machine->kernel_cmdline); 615 if (dt_size < 0) { 616 error_report("couldn't load device tree"); 617 exit(1); 618 } 619 620 boot_info->dt_base = FDT_ADDR; 621 boot_info->dt_size = dt_size; 622 } 623 624 boot_info->entry = entry; 625 } 626 627 static void sam460ex_machine_init(MachineClass *mc) 628 { 629 mc->desc = "aCube Sam460ex"; 630 mc->init = sam460ex_init; 631 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb"); 632 mc->default_ram_size = 512 * MiB; 633 } 634 635 DEFINE_MACHINE("sam460ex", sam460ex_machine_init) 636