1 /* 2 * QEMU aCube Sam460ex board emulation 3 * 4 * Copyright (c) 2012 François Revol 5 * Copyright (c) 2016-2019 BALATON Zoltan 6 * 7 * This file is derived from hw/ppc440_bamboo.c, 8 * the copyright for that material belongs to the original owners. 9 * 10 * This work is licensed under the GNU GPL license version 2 or later. 11 * 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu/units.h" 16 #include "qemu-common.h" 17 #include "qemu/datadir.h" 18 #include "qemu/error-report.h" 19 #include "qapi/error.h" 20 #include "hw/boards.h" 21 #include "sysemu/kvm.h" 22 #include "kvm_ppc.h" 23 #include "sysemu/device_tree.h" 24 #include "sysemu/block-backend.h" 25 #include "hw/loader.h" 26 #include "elf.h" 27 #include "exec/address-spaces.h" 28 #include "exec/memory.h" 29 #include "ppc440.h" 30 #include "ppc405.h" 31 #include "hw/block/flash.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/reset.h" 34 #include "hw/sysbus.h" 35 #include "hw/char/serial.h" 36 #include "hw/i2c/ppc4xx_i2c.h" 37 #include "hw/i2c/smbus_eeprom.h" 38 #include "hw/usb/hcd-ehci.h" 39 #include "hw/ppc/fdt.h" 40 #include "hw/qdev-properties.h" 41 #include "hw/intc/ppc-uic.h" 42 43 #include <libfdt.h> 44 45 #define BINARY_DEVICE_TREE_FILE "canyonlands.dtb" 46 #define UBOOT_FILENAME "u-boot-sam460-20100605.bin" 47 /* to extract the official U-Boot bin from the updater: */ 48 /* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x80000)) \ 49 if=updater/updater-460 of=u-boot-sam460-20100605.bin */ 50 51 /* from Sam460 U-Boot include/configs/Sam460ex.h */ 52 #define FLASH_BASE 0xfff00000 53 #define FLASH_BASE_H 0x4 54 #define FLASH_SIZE (1 * MiB) 55 #define UBOOT_LOAD_BASE 0xfff80000 56 #define UBOOT_SIZE 0x00080000 57 #define UBOOT_ENTRY 0xfffffffc 58 59 /* from U-Boot */ 60 #define EPAPR_MAGIC (0x45504150) 61 #define KERNEL_ADDR 0x1000000 62 #define FDT_ADDR 0x1800000 63 #define RAMDISK_ADDR 0x1900000 64 65 /* Sam460ex IRQ MAP: 66 IRQ0 = ETH_INT 67 IRQ1 = FPGA_INT 68 IRQ2 = PCI_INT (PCIA, PCIB, PCIC, PCIB) 69 IRQ3 = FPGA_INT2 70 IRQ11 = RTC_INT 71 IRQ12 = SM502_INT 72 */ 73 74 #define CPU_FREQ 1150000000 75 #define PLB_FREQ 230000000 76 #define OPB_FREQ 115000000 77 #define EBC_FREQ 115000000 78 #define UART_FREQ 11059200 79 #define SDRAM_NR_BANKS 4 80 81 /* The SoC could also handle 4 GiB but firmware does not work with that. */ 82 /* Maybe it overflows a signed 32 bit number somewhere? */ 83 static const ram_addr_t ppc460ex_sdram_bank_sizes[] = { 84 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB, 85 32 * MiB, 0 86 }; 87 88 struct boot_info { 89 uint32_t dt_base; 90 uint32_t dt_size; 91 uint32_t entry; 92 }; 93 94 static int sam460ex_load_uboot(void) 95 { 96 /* 97 * This first creates 1MiB of flash memory mapped at the end of 98 * the 32-bit address space (0xFFF00000..0xFFFFFFFF). 99 * 100 * If_PFLASH unit 0 is defined, the flash memory is initialized 101 * from that block backend. 102 * 103 * Else, it's initialized to zero. And then 512KiB of ROM get 104 * mapped on top of its second half (0xFFF80000..0xFFFFFFFF), 105 * initialized from u-boot-sam460-20100605.bin. 106 * 107 * This doesn't smell right. 108 * 109 * The physical hardware appears to have 512KiB flash memory. 110 * 111 * TODO Figure out what we really need here, and clean this up. 112 */ 113 114 DriveInfo *dinfo; 115 116 dinfo = drive_get(IF_PFLASH, 0, 0); 117 if (!pflash_cfi01_register(FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32), 118 "sam460ex.flash", FLASH_SIZE, 119 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 120 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1)) { 121 error_report("Error registering flash memory"); 122 /* XXX: return an error instead? */ 123 exit(1); 124 } 125 126 if (!dinfo) { 127 /*error_report("No flash image given with the 'pflash' parameter," 128 " using default u-boot image");*/ 129 rom_add_file_fixed(UBOOT_FILENAME, 130 UBOOT_LOAD_BASE | ((hwaddr)FLASH_BASE_H << 32), 131 -1); 132 } 133 134 return 0; 135 } 136 137 static int sam460ex_load_device_tree(hwaddr addr, 138 uint32_t ramsize, 139 hwaddr initrd_base, 140 hwaddr initrd_size, 141 const char *kernel_cmdline) 142 { 143 uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) }; 144 char *filename; 145 int fdt_size; 146 void *fdt; 147 uint32_t tb_freq = CPU_FREQ; 148 uint32_t clock_freq = CPU_FREQ; 149 int offset; 150 151 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); 152 if (!filename) { 153 error_report("Couldn't find dtb file `%s'", BINARY_DEVICE_TREE_FILE); 154 exit(1); 155 } 156 fdt = load_device_tree(filename, &fdt_size); 157 if (!fdt) { 158 error_report("Couldn't load dtb file `%s'", filename); 159 g_free(filename); 160 exit(1); 161 } 162 g_free(filename); 163 164 /* Manipulate device tree in memory. */ 165 166 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 167 sizeof(mem_reg_property)); 168 169 /* default FDT doesn't have a /chosen node... */ 170 qemu_fdt_add_subnode(fdt, "/chosen"); 171 172 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", initrd_base); 173 174 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 175 (initrd_base + initrd_size)); 176 177 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline); 178 179 /* Copy data from the host device tree into the guest. Since the guest can 180 * directly access the timebase without host involvement, we must expose 181 * the correct frequencies. */ 182 if (kvm_enabled()) { 183 tb_freq = kvmppc_get_tbfreq(); 184 clock_freq = kvmppc_get_clockfreq(); 185 } 186 187 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency", 188 clock_freq); 189 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency", 190 tb_freq); 191 192 /* Remove cpm node if it exists (it is not emulated) */ 193 offset = fdt_path_offset(fdt, "/cpm"); 194 if (offset >= 0) { 195 _FDT(fdt_nop_node(fdt, offset)); 196 } 197 198 /* set serial port clocks */ 199 offset = fdt_node_offset_by_compatible(fdt, -1, "ns16550"); 200 while (offset >= 0) { 201 _FDT(fdt_setprop_cell(fdt, offset, "clock-frequency", UART_FREQ)); 202 offset = fdt_node_offset_by_compatible(fdt, offset, "ns16550"); 203 } 204 205 /* some more clocks */ 206 qemu_fdt_setprop_cell(fdt, "/plb", "clock-frequency", 207 PLB_FREQ); 208 qemu_fdt_setprop_cell(fdt, "/plb/opb", "clock-frequency", 209 OPB_FREQ); 210 qemu_fdt_setprop_cell(fdt, "/plb/opb/ebc", "clock-frequency", 211 EBC_FREQ); 212 213 rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); 214 g_free(fdt); 215 216 return fdt_size; 217 } 218 219 /* Create reset TLB entries for BookE, mapping only the flash memory. */ 220 static void mmubooke_create_initial_mapping_uboot(CPUPPCState *env) 221 { 222 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 223 224 /* on reset the flash is mapped by a shadow TLB, 225 * but since we don't implement them we need to use 226 * the same values U-Boot will use to avoid a fault. 227 */ 228 tlb->attr = 0; 229 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 230 tlb->size = 0x10000000; /* up to 0xffffffff */ 231 tlb->EPN = 0xf0000000 & TARGET_PAGE_MASK; 232 tlb->RPN = (0xf0000000 & TARGET_PAGE_MASK) | 0x4; 233 tlb->PID = 0; 234 } 235 236 /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ 237 static void mmubooke_create_initial_mapping(CPUPPCState *env, 238 target_ulong va, 239 hwaddr pa) 240 { 241 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 242 243 tlb->attr = 0; 244 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 245 tlb->size = 1 << 31; /* up to 0x80000000 */ 246 tlb->EPN = va & TARGET_PAGE_MASK; 247 tlb->RPN = pa & TARGET_PAGE_MASK; 248 tlb->PID = 0; 249 } 250 251 static void main_cpu_reset(void *opaque) 252 { 253 PowerPCCPU *cpu = opaque; 254 CPUPPCState *env = &cpu->env; 255 struct boot_info *bi = env->load_info; 256 257 cpu_reset(CPU(cpu)); 258 259 /* either we have a kernel to boot or we jump to U-Boot */ 260 if (bi->entry != UBOOT_ENTRY) { 261 env->gpr[1] = (16 * MiB) - 8; 262 env->gpr[3] = FDT_ADDR; 263 env->nip = bi->entry; 264 265 /* Create a mapping for the kernel. */ 266 mmubooke_create_initial_mapping(env, 0, 0); 267 env->gpr[6] = tswap32(EPAPR_MAGIC); 268 env->gpr[7] = (16 * MiB) - 8; /* bi->ima_size; */ 269 270 } else { 271 env->nip = UBOOT_ENTRY; 272 mmubooke_create_initial_mapping_uboot(env); 273 } 274 } 275 276 static void sam460ex_init(MachineState *machine) 277 { 278 MemoryRegion *address_space_mem = get_system_memory(); 279 MemoryRegion *isa = g_new(MemoryRegion, 1); 280 MemoryRegion *ram_memories = g_new(MemoryRegion, SDRAM_NR_BANKS); 281 hwaddr ram_bases[SDRAM_NR_BANKS] = {0}; 282 hwaddr ram_sizes[SDRAM_NR_BANKS] = {0}; 283 MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1); 284 DeviceState *uic[4]; 285 qemu_irq mal_irqs[4]; 286 int i; 287 PCIBus *pci_bus; 288 PowerPCCPU *cpu; 289 CPUPPCState *env; 290 I2CBus *i2c; 291 hwaddr entry = UBOOT_ENTRY; 292 target_long initrd_size = 0; 293 DeviceState *dev; 294 SysBusDevice *sbdev; 295 struct boot_info *boot_info; 296 uint8_t *spd_data; 297 int success; 298 299 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 300 env = &cpu->env; 301 if (env->mmu_model != POWERPC_MMU_BOOKE) { 302 error_report("Only MMU model BookE is supported by this machine."); 303 exit(1); 304 } 305 306 qemu_register_reset(main_cpu_reset, cpu); 307 boot_info = g_malloc0(sizeof(*boot_info)); 308 env->load_info = boot_info; 309 310 ppc_booke_timers_init(cpu, CPU_FREQ, 0); 311 ppc_dcr_init(env, NULL, NULL); 312 313 /* PLB arbitrer */ 314 ppc4xx_plb_init(env); 315 316 /* interrupt controllers */ 317 for (i = 0; i < ARRAY_SIZE(uic); i++) { 318 SysBusDevice *sbd; 319 /* 320 * UICs 1, 2 and 3 are cascaded through UIC 0. 321 * input_ints[n] is the interrupt number on UIC 0 which 322 * the INT output of UIC n is connected to. The CINT output 323 * of UIC n connects to input_ints[n] + 1. 324 * The entry in input_ints[] for UIC 0 is ignored, because UIC 0's 325 * INT and CINT outputs are connected to the CPU. 326 */ 327 const int input_ints[] = { -1, 30, 10, 16 }; 328 329 uic[i] = qdev_new(TYPE_PPC_UIC); 330 sbd = SYS_BUS_DEVICE(uic[i]); 331 332 qdev_prop_set_uint32(uic[i], "dcr-base", 0xc0 + i * 0x10); 333 object_property_set_link(OBJECT(uic[i]), "cpu", OBJECT(cpu), 334 &error_fatal); 335 sysbus_realize_and_unref(sbd, &error_fatal); 336 337 if (i == 0) { 338 sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT, 339 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]); 340 sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT, 341 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]); 342 } else { 343 sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT, 344 qdev_get_gpio_in(uic[0], input_ints[i])); 345 sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT, 346 qdev_get_gpio_in(uic[0], input_ints[i] + 1)); 347 } 348 } 349 350 /* SDRAM controller */ 351 /* put all RAM on first bank because board has one slot 352 * and firmware only checks that */ 353 ppc4xx_sdram_banks(machine->ram, 1, ram_memories, ram_bases, ram_sizes, 354 ppc460ex_sdram_bank_sizes); 355 356 /* FIXME: does 460EX have ECC interrupts? */ 357 ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories, 358 ram_bases, ram_sizes, 1); 359 360 /* IIC controllers and devices */ 361 dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, 362 qdev_get_gpio_in(uic[0], 2)); 363 i2c = PPC4xx_I2C(dev)->bus; 364 /* SPD EEPROM on RAM module */ 365 spd_data = spd_data_generate(ram_sizes[0] < 128 * MiB ? DDR : DDR2, 366 ram_sizes[0]); 367 spd_data[20] = 4; /* SO-DIMM module */ 368 smbus_eeprom_init_one(i2c, 0x50, spd_data); 369 /* RTC */ 370 i2c_slave_create_simple(i2c, "m41t80", 0x68); 371 372 dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, 373 qdev_get_gpio_in(uic[0], 3)); 374 375 /* External bus controller */ 376 ppc405_ebc_init(env); 377 378 /* CPR */ 379 ppc4xx_cpr_init(env); 380 381 /* PLB to AHB bridge */ 382 ppc4xx_ahb_init(env); 383 384 /* System DCRs */ 385 ppc4xx_sdr_init(env); 386 387 /* MAL */ 388 for (i = 0; i < ARRAY_SIZE(mal_irqs); i++) { 389 mal_irqs[0] = qdev_get_gpio_in(uic[2], 3 + i); 390 } 391 ppc4xx_mal_init(env, 4, 16, mal_irqs); 392 393 /* DMA */ 394 ppc4xx_dma_init(env, 0x200); 395 396 /* 256K of L2 cache as memory */ 397 ppc4xx_l2sram_init(env); 398 /* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */ 399 memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 * KiB, 400 &error_abort); 401 memory_region_add_subregion(address_space_mem, 0x400000000LL, l2cache_ram); 402 403 /* USB */ 404 sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, 405 qdev_get_gpio_in(uic[2], 29)); 406 dev = qdev_new("sysbus-ohci"); 407 qdev_prop_set_string(dev, "masterbus", "usb-bus.0"); 408 qdev_prop_set_uint32(dev, "num-ports", 6); 409 sbdev = SYS_BUS_DEVICE(dev); 410 sysbus_realize_and_unref(sbdev, &error_fatal); 411 sysbus_mmio_map(sbdev, 0, 0x4bffd0000); 412 sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(uic[2], 30)); 413 usb_create_simple(usb_bus_find(-1), "usb-kbd"); 414 usb_create_simple(usb_bus_find(-1), "usb-mouse"); 415 416 /* PCI bus */ 417 ppc460ex_pcie_init(env); 418 /* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */ 419 dev = sysbus_create_simple("ppc440-pcix-host", 0xc0ec00000, 420 qdev_get_gpio_in(uic[1], 0)); 421 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); 422 423 memory_region_init_alias(isa, NULL, "isa_mmio", get_system_io(), 424 0, 0x10000); 425 memory_region_add_subregion(get_system_memory(), 0xc08000000, isa); 426 427 /* PCI devices */ 428 pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501"); 429 /* SoC has a single SATA port but we don't emulate that yet 430 * However, firmware and usual clients have driver for SiI311x 431 * so add one for convenience by default */ 432 if (defaults_enabled()) { 433 pci_create_simple(pci_bus, -1, "sii3112"); 434 } 435 436 /* SoC has 4 UARTs 437 * but board has only one wired and two are present in fdt */ 438 if (serial_hd(0) != NULL) { 439 serial_mm_init(address_space_mem, 0x4ef600300, 0, 440 qdev_get_gpio_in(uic[1], 1), 441 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 442 DEVICE_BIG_ENDIAN); 443 } 444 if (serial_hd(1) != NULL) { 445 serial_mm_init(address_space_mem, 0x4ef600400, 0, 446 qdev_get_gpio_in(uic[0], 1), 447 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 448 DEVICE_BIG_ENDIAN); 449 } 450 451 /* Load U-Boot image. */ 452 if (!machine->kernel_filename) { 453 success = sam460ex_load_uboot(); 454 if (success < 0) { 455 error_report("could not load firmware"); 456 exit(1); 457 } 458 } 459 460 /* Load kernel. */ 461 if (machine->kernel_filename) { 462 hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 463 success = load_uimage(machine->kernel_filename, &entry, &loadaddr, 464 NULL, NULL, NULL); 465 if (success < 0) { 466 uint64_t elf_entry; 467 468 success = load_elf(machine->kernel_filename, NULL, NULL, NULL, 469 &elf_entry, NULL, NULL, NULL, 470 1, PPC_ELF_MACHINE, 0, 0); 471 entry = elf_entry; 472 } 473 /* XXX try again as binary */ 474 if (success < 0) { 475 error_report("could not load kernel '%s'", 476 machine->kernel_filename); 477 exit(1); 478 } 479 } 480 481 /* Load initrd. */ 482 if (machine->initrd_filename) { 483 initrd_size = load_image_targphys(machine->initrd_filename, 484 RAMDISK_ADDR, 485 machine->ram_size - RAMDISK_ADDR); 486 if (initrd_size < 0) { 487 error_report("could not load ram disk '%s' at %x", 488 machine->initrd_filename, RAMDISK_ADDR); 489 exit(1); 490 } 491 } 492 493 /* If we're loading a kernel directly, we must load the device tree too. */ 494 if (machine->kernel_filename) { 495 int dt_size; 496 497 dt_size = sam460ex_load_device_tree(FDT_ADDR, machine->ram_size, 498 RAMDISK_ADDR, initrd_size, 499 machine->kernel_cmdline); 500 501 boot_info->dt_base = FDT_ADDR; 502 boot_info->dt_size = dt_size; 503 } 504 505 boot_info->entry = entry; 506 } 507 508 static void sam460ex_machine_init(MachineClass *mc) 509 { 510 mc->desc = "aCube Sam460ex"; 511 mc->init = sam460ex_init; 512 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb"); 513 mc->default_ram_size = 512 * MiB; 514 mc->default_ram_id = "ppc4xx.sdram"; 515 } 516 517 DEFINE_MACHINE("sam460ex", sam460ex_machine_init) 518