1 /* 2 * QEMU aCube Sam460ex board emulation 3 * 4 * Copyright (c) 2012 François Revol 5 * Copyright (c) 2016-2019 BALATON Zoltan 6 * 7 * This file is derived from hw/ppc440_bamboo.c, 8 * the copyright for that material belongs to the original owners. 9 * 10 * This work is licensed under the GNU GPL license version 2 or later. 11 * 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu/units.h" 16 #include "qemu/datadir.h" 17 #include "qemu/error-report.h" 18 #include "qapi/error.h" 19 #include "hw/boards.h" 20 #include "sysemu/kvm.h" 21 #include "kvm_ppc.h" 22 #include "sysemu/device_tree.h" 23 #include "sysemu/block-backend.h" 24 #include "exec/page-protection.h" 25 #include "hw/loader.h" 26 #include "elf.h" 27 #include "exec/memory.h" 28 #include "ppc440.h" 29 #include "hw/pci-host/ppc4xx.h" 30 #include "hw/block/flash.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/reset.h" 33 #include "hw/sysbus.h" 34 #include "hw/char/serial-mm.h" 35 #include "hw/i2c/ppc4xx_i2c.h" 36 #include "hw/i2c/smbus_eeprom.h" 37 #include "hw/ide/pci.h" 38 #include "hw/usb/hcd-ehci.h" 39 #include "hw/ppc/fdt.h" 40 #include "hw/qdev-properties.h" 41 #include "hw/intc/ppc-uic.h" 42 43 #include <libfdt.h> 44 45 #define BINARY_DEVICE_TREE_FILE "canyonlands.dtb" 46 #define UBOOT_FILENAME "u-boot-sam460-20100605.bin" 47 /* to extract the official U-Boot bin from the updater: */ 48 /* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x80000)) \ 49 if=updater/updater-460 of=u-boot-sam460-20100605.bin */ 50 51 #define PCIE0_DCRN_BASE 0x100 52 #define PCIE1_DCRN_BASE 0x120 53 54 /* from Sam460 U-Boot include/configs/Sam460ex.h */ 55 #define FLASH_BASE 0xfff00000 56 #define FLASH_BASE_H 0x4 57 #define FLASH_SIZE (1 * MiB) 58 #define UBOOT_LOAD_BASE 0xfff80000 59 #define UBOOT_SIZE 0x00080000 60 #define UBOOT_ENTRY 0xfffffffc 61 62 /* from U-Boot */ 63 #define EPAPR_MAGIC (0x45504150) 64 #define KERNEL_ADDR 0x1000000 65 #define FDT_ADDR 0x1800000 66 #define RAMDISK_ADDR 0x1900000 67 68 /* Sam460ex IRQ MAP: 69 IRQ0 = ETH_INT 70 IRQ1 = FPGA_INT 71 IRQ2 = PCI_INT (PCIA, PCIB, PCIC, PCIB) 72 IRQ3 = FPGA_INT2 73 IRQ11 = RTC_INT 74 IRQ12 = SM502_INT 75 */ 76 77 #define CPU_FREQ 1150000000 78 #define PLB_FREQ 230000000 79 #define OPB_FREQ 115000000 80 #define EBC_FREQ 115000000 81 #define UART_FREQ 11059200 82 83 struct boot_info { 84 uint32_t dt_base; 85 uint32_t dt_size; 86 uint32_t entry; 87 }; 88 89 static int sam460ex_load_uboot(void) 90 { 91 /* 92 * This first creates 1MiB of flash memory mapped at the end of 93 * the 32-bit address space (0xFFF00000..0xFFFFFFFF). 94 * 95 * If_PFLASH unit 0 is defined, the flash memory is initialized 96 * from that block backend. 97 * 98 * Else, it's initialized to zero. And then 512KiB of ROM get 99 * mapped on top of its second half (0xFFF80000..0xFFFFFFFF), 100 * initialized from u-boot-sam460-20100605.bin. 101 * 102 * This doesn't smell right. 103 * 104 * The physical hardware appears to have 512KiB flash memory. 105 * 106 * TODO Figure out what we really need here, and clean this up. 107 */ 108 109 DriveInfo *dinfo; 110 111 dinfo = drive_get(IF_PFLASH, 0, 0); 112 if (!pflash_cfi01_register(FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32), 113 "sam460ex.flash", FLASH_SIZE, 114 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 115 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1)) { 116 error_report("Error registering flash memory"); 117 /* XXX: return an error instead? */ 118 exit(1); 119 } 120 121 if (!dinfo) { 122 /*error_report("No flash image given with the 'pflash' parameter," 123 " using default u-boot image");*/ 124 rom_add_file_fixed(UBOOT_FILENAME, 125 UBOOT_LOAD_BASE | ((hwaddr)FLASH_BASE_H << 32), 126 -1); 127 } 128 129 return 0; 130 } 131 132 static int sam460ex_load_device_tree(MachineState *machine, 133 hwaddr addr, 134 hwaddr initrd_base, 135 hwaddr initrd_size) 136 { 137 uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(machine->ram_size) }; 138 char *filename; 139 int fdt_size; 140 void *fdt; 141 uint32_t tb_freq = CPU_FREQ; 142 uint32_t clock_freq = CPU_FREQ; 143 int offset; 144 145 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); 146 if (!filename) { 147 error_report("Couldn't find dtb file `%s'", BINARY_DEVICE_TREE_FILE); 148 exit(1); 149 } 150 fdt = load_device_tree(filename, &fdt_size); 151 if (!fdt) { 152 error_report("Couldn't load dtb file `%s'", filename); 153 g_free(filename); 154 exit(1); 155 } 156 g_free(filename); 157 158 /* Manipulate device tree in memory. */ 159 160 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 161 sizeof(mem_reg_property)); 162 163 /* default FDT doesn't have a /chosen node... */ 164 qemu_fdt_add_subnode(fdt, "/chosen"); 165 166 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", initrd_base); 167 168 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 169 (initrd_base + initrd_size)); 170 171 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 172 machine->kernel_cmdline); 173 174 /* Copy data from the host device tree into the guest. Since the guest can 175 * directly access the timebase without host involvement, we must expose 176 * the correct frequencies. */ 177 if (kvm_enabled()) { 178 tb_freq = kvmppc_get_tbfreq(); 179 clock_freq = kvmppc_get_clockfreq(); 180 } 181 182 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency", 183 clock_freq); 184 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency", 185 tb_freq); 186 187 /* Remove cpm node if it exists (it is not emulated) */ 188 offset = fdt_path_offset(fdt, "/cpm"); 189 if (offset >= 0) { 190 _FDT(fdt_nop_node(fdt, offset)); 191 } 192 193 /* set serial port clocks */ 194 offset = fdt_node_offset_by_compatible(fdt, -1, "ns16550"); 195 while (offset >= 0) { 196 _FDT(fdt_setprop_cell(fdt, offset, "clock-frequency", UART_FREQ)); 197 offset = fdt_node_offset_by_compatible(fdt, offset, "ns16550"); 198 } 199 200 /* some more clocks */ 201 qemu_fdt_setprop_cell(fdt, "/plb", "clock-frequency", 202 PLB_FREQ); 203 qemu_fdt_setprop_cell(fdt, "/plb/opb", "clock-frequency", 204 OPB_FREQ); 205 qemu_fdt_setprop_cell(fdt, "/plb/opb/ebc", "clock-frequency", 206 EBC_FREQ); 207 208 rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); 209 210 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ 211 machine->fdt = fdt; 212 213 return fdt_size; 214 } 215 216 static void main_cpu_reset(void *opaque) 217 { 218 PowerPCCPU *cpu = opaque; 219 CPUPPCState *env = &cpu->env; 220 struct boot_info *bi = env->load_info; 221 222 cpu_reset(CPU(cpu)); 223 224 /* 225 * On reset the flash is mapped by a shadow TLB, but since we 226 * don't implement them we need to use the same values U-Boot 227 * will use to avoid a fault. 228 * either we have a kernel to boot or we jump to U-Boot 229 */ 230 if (bi->entry != UBOOT_ENTRY) { 231 env->gpr[1] = (16 * MiB) - 8; 232 env->gpr[3] = FDT_ADDR; 233 env->nip = bi->entry; 234 235 /* Create a mapping for the kernel. */ 236 booke_set_tlb(&env->tlb.tlbe[0], 0, 0, 1 << 31); 237 env->gpr[6] = tswap32(EPAPR_MAGIC); 238 env->gpr[7] = (16 * MiB) - 8; /* bi->ima_size; */ 239 240 } else { 241 env->nip = UBOOT_ENTRY; 242 /* Create a mapping for U-Boot. */ 243 booke_set_tlb(&env->tlb.tlbe[0], 0xf0000000, 0xf0000000, 0x10000000); 244 env->tlb.tlbe[0].RPN |= 4; 245 } 246 } 247 248 static void sam460ex_init(MachineState *machine) 249 { 250 MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1); 251 DeviceState *uic[4]; 252 int i; 253 PCIBus *pci_bus; 254 USBBus *usb_bus; 255 PowerPCCPU *cpu; 256 CPUPPCState *env; 257 I2CBus *i2c; 258 hwaddr entry = UBOOT_ENTRY; 259 target_long initrd_size = 0; 260 DeviceState *dev; 261 SysBusDevice *sbdev; 262 struct boot_info *boot_info; 263 uint8_t *spd_data; 264 int success; 265 266 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 267 env = &cpu->env; 268 if (env->mmu_model != POWERPC_MMU_BOOKE) { 269 error_report("Only MMU model BookE is supported by this machine."); 270 exit(1); 271 } 272 273 qemu_register_reset(main_cpu_reset, cpu); 274 boot_info = g_malloc0(sizeof(*boot_info)); 275 env->load_info = boot_info; 276 277 ppc_booke_timers_init(cpu, CPU_FREQ, 0); 278 ppc_dcr_init(env, NULL, NULL); 279 280 /* PLB arbitrer */ 281 dev = qdev_new(TYPE_PPC4xx_PLB); 282 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); 283 object_unref(OBJECT(dev)); 284 285 /* interrupt controllers */ 286 for (i = 0; i < ARRAY_SIZE(uic); i++) { 287 /* 288 * UICs 1, 2 and 3 are cascaded through UIC 0. 289 * input_ints[n] is the interrupt number on UIC 0 which 290 * the INT output of UIC n is connected to. The CINT output 291 * of UIC n connects to input_ints[n] + 1. 292 * The entry in input_ints[] for UIC 0 is ignored, because UIC 0's 293 * INT and CINT outputs are connected to the CPU. 294 */ 295 const int input_ints[] = { -1, 30, 10, 16 }; 296 297 uic[i] = qdev_new(TYPE_PPC_UIC); 298 qdev_prop_set_uint32(uic[i], "dcr-base", 0xc0 + i * 0x10); 299 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uic[i]), cpu, &error_fatal); 300 object_unref(OBJECT(uic[i])); 301 302 sbdev = SYS_BUS_DEVICE(uic[i]); 303 if (i == 0) { 304 sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT, 305 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT)); 306 sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT, 307 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT)); 308 } else { 309 sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT, 310 qdev_get_gpio_in(uic[0], input_ints[i])); 311 sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT, 312 qdev_get_gpio_in(uic[0], input_ints[i] + 1)); 313 } 314 } 315 316 /* SDRAM controller */ 317 /* The SoC could also handle 4 GiB but firmware does not work with that. */ 318 if (machine->ram_size > 2 * GiB) { 319 error_report("Memory over 2 GiB is not supported"); 320 exit(1); 321 } 322 /* Firmware needs at least 64 MiB */ 323 if (machine->ram_size < 64 * MiB) { 324 error_report("Memory below 64 MiB is not supported"); 325 exit(1); 326 } 327 dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR2); 328 object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram), 329 &error_abort); 330 /* 331 * Put all RAM on first bank because board has one slot 332 * and firmware only checks that 333 */ 334 object_property_set_int(OBJECT(dev), "nbanks", 1, &error_abort); 335 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); 336 object_unref(OBJECT(dev)); 337 /* FIXME: does 460EX have ECC interrupts? */ 338 /* Enable SDRAM memory regions as we may boot without firmware */ 339 ppc4xx_sdram_ddr2_enable(PPC4xx_SDRAM_DDR2(dev)); 340 341 /* IIC controllers and devices */ 342 dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, 343 qdev_get_gpio_in(uic[0], 2)); 344 i2c = PPC4xx_I2C(dev)->bus; 345 /* SPD EEPROM on RAM module */ 346 spd_data = spd_data_generate(machine->ram_size < 128 * MiB ? DDR : DDR2, 347 machine->ram_size); 348 spd_data[20] = 4; /* SO-DIMM module */ 349 smbus_eeprom_init_one(i2c, 0x50, spd_data); 350 /* RTC */ 351 i2c_slave_create_simple(i2c, "m41t80", 0x68); 352 353 dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, 354 qdev_get_gpio_in(uic[0], 3)); 355 356 /* External bus controller */ 357 dev = qdev_new(TYPE_PPC4xx_EBC); 358 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); 359 object_unref(OBJECT(dev)); 360 361 /* CPR */ 362 ppc4xx_cpr_init(env); 363 364 /* PLB to AHB bridge */ 365 ppc4xx_ahb_init(env); 366 367 /* System DCRs */ 368 ppc4xx_sdr_init(env); 369 370 /* MAL */ 371 dev = qdev_new(TYPE_PPC4xx_MAL); 372 qdev_prop_set_uint8(dev, "txc-num", 4); 373 qdev_prop_set_uint8(dev, "rxc-num", 16); 374 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); 375 object_unref(OBJECT(dev)); 376 sbdev = SYS_BUS_DEVICE(dev); 377 for (i = 0; i < ARRAY_SIZE(PPC4xx_MAL(dev)->irqs); i++) { 378 sysbus_connect_irq(sbdev, i, qdev_get_gpio_in(uic[2], 3 + i)); 379 } 380 381 /* DMA */ 382 ppc4xx_dma_init(env, 0x200); 383 384 /* 256K of L2 cache as memory */ 385 ppc4xx_l2sram_init(env); 386 /* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */ 387 memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 * KiB, 388 &error_abort); 389 memory_region_add_subregion(get_system_memory(), 0x400000000LL, 390 l2cache_ram); 391 392 /* USB */ 393 sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, 394 qdev_get_gpio_in(uic[2], 29)); 395 dev = qdev_new("sysbus-ohci"); 396 qdev_prop_set_string(dev, "masterbus", "usb-bus.0"); 397 qdev_prop_set_uint32(dev, "num-ports", 6); 398 sbdev = SYS_BUS_DEVICE(dev); 399 sysbus_realize_and_unref(sbdev, &error_fatal); 400 sysbus_mmio_map(sbdev, 0, 0x4bffd0000); 401 sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(uic[2], 30)); 402 usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS, 403 &error_abort)); 404 usb_create_simple(usb_bus, "usb-kbd"); 405 usb_create_simple(usb_bus, "usb-mouse"); 406 407 /* PCIe buses */ 408 dev = qdev_new(TYPE_PPC460EX_PCIE_HOST); 409 qdev_prop_set_int32(dev, "busnum", 0); 410 qdev_prop_set_int32(dev, "dcrn-base", PCIE0_DCRN_BASE); 411 object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort); 412 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 413 414 dev = qdev_new(TYPE_PPC460EX_PCIE_HOST); 415 qdev_prop_set_int32(dev, "busnum", 1); 416 qdev_prop_set_int32(dev, "dcrn-base", PCIE1_DCRN_BASE); 417 object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort); 418 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 419 420 /* PCI bus */ 421 /* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */ 422 dev = sysbus_create_simple(TYPE_PPC440_PCIX_HOST, 0xc0ec00000, 423 qdev_get_gpio_in(uic[1], 0)); 424 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, 0xc08000000); 425 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); 426 427 /* PCI devices */ 428 pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501"); 429 /* 430 * SoC has a single SATA port but we don't emulate that 431 * However, firmware and usual clients have driver for SiI311x 432 * PCI SATA card so add one for convenience by default 433 */ 434 if (defaults_enabled()) { 435 PCIIDEState *s = PCI_IDE(pci_create_simple(pci_bus, -1, "sii3112")); 436 DriveInfo *di; 437 438 di = drive_get_by_index(IF_IDE, 0); 439 if (di) { 440 ide_bus_create_drive(&s->bus[0], 0, di); 441 } 442 /* Use index 2 only if 1 does not exist, this allows -cdrom */ 443 di = drive_get_by_index(IF_IDE, 1) ?: drive_get_by_index(IF_IDE, 2); 444 if (di) { 445 ide_bus_create_drive(&s->bus[1], 0, di); 446 } 447 } 448 449 /* SoC has 4 UARTs but board has only one wired and two described in fdt */ 450 if (serial_hd(0) != NULL) { 451 serial_mm_init(get_system_memory(), 0x4ef600300, 0, 452 qdev_get_gpio_in(uic[1], 1), 453 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 454 DEVICE_BIG_ENDIAN); 455 } 456 if (serial_hd(1) != NULL) { 457 serial_mm_init(get_system_memory(), 0x4ef600400, 0, 458 qdev_get_gpio_in(uic[0], 1), 459 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 460 DEVICE_BIG_ENDIAN); 461 } 462 463 /* Load U-Boot image. */ 464 if (!machine->kernel_filename) { 465 success = sam460ex_load_uboot(); 466 if (success < 0) { 467 error_report("could not load firmware"); 468 exit(1); 469 } 470 } 471 472 /* Load kernel. */ 473 if (machine->kernel_filename) { 474 hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 475 success = load_uimage(machine->kernel_filename, &entry, &loadaddr, 476 NULL, NULL, NULL); 477 if (success < 0) { 478 uint64_t elf_entry; 479 480 success = load_elf(machine->kernel_filename, NULL, NULL, NULL, 481 &elf_entry, NULL, NULL, NULL, 482 1, PPC_ELF_MACHINE, 0, 0); 483 entry = elf_entry; 484 } 485 /* XXX try again as binary */ 486 if (success < 0) { 487 error_report("could not load kernel '%s'", 488 machine->kernel_filename); 489 exit(1); 490 } 491 } 492 493 /* Load initrd. */ 494 if (machine->initrd_filename) { 495 initrd_size = load_image_targphys(machine->initrd_filename, 496 RAMDISK_ADDR, 497 machine->ram_size - RAMDISK_ADDR); 498 if (initrd_size < 0) { 499 error_report("could not load ram disk '%s' at %x", 500 machine->initrd_filename, RAMDISK_ADDR); 501 exit(1); 502 } 503 } 504 505 /* If we're loading a kernel directly, we must load the device tree too. */ 506 if (machine->kernel_filename) { 507 int dt_size; 508 509 dt_size = sam460ex_load_device_tree(machine, FDT_ADDR, 510 RAMDISK_ADDR, initrd_size); 511 512 boot_info->dt_base = FDT_ADDR; 513 boot_info->dt_size = dt_size; 514 } 515 516 boot_info->entry = entry; 517 } 518 519 static void sam460ex_machine_init(MachineClass *mc) 520 { 521 mc->desc = "aCube Sam460ex"; 522 mc->init = sam460ex_init; 523 mc->block_default_type = IF_IDE; 524 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb"); 525 mc->default_ram_size = 512 * MiB; 526 mc->default_ram_id = "ppc4xx.sdram"; 527 } 528 529 DEFINE_MACHINE("sam460ex", sam460ex_machine_init) 530