1 /* 2 * QEMU aCube Sam460ex board emulation 3 * 4 * Copyright (c) 2012 François Revol 5 * Copyright (c) 2016-2019 BALATON Zoltan 6 * 7 * This file is derived from hw/ppc440_bamboo.c, 8 * the copyright for that material belongs to the original owners. 9 * 10 * This work is licensed under the GNU GPL license version 2 or later. 11 * 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu/units.h" 16 #include "qemu/datadir.h" 17 #include "qemu/error-report.h" 18 #include "qapi/error.h" 19 #include "hw/boards.h" 20 #include "sysemu/kvm.h" 21 #include "kvm_ppc.h" 22 #include "sysemu/device_tree.h" 23 #include "sysemu/block-backend.h" 24 #include "hw/loader.h" 25 #include "elf.h" 26 #include "exec/memory.h" 27 #include "ppc440.h" 28 #include "hw/pci-host/ppc4xx.h" 29 #include "hw/block/flash.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/reset.h" 32 #include "hw/sysbus.h" 33 #include "hw/char/serial.h" 34 #include "hw/i2c/ppc4xx_i2c.h" 35 #include "hw/i2c/smbus_eeprom.h" 36 #include "hw/usb/hcd-ehci.h" 37 #include "hw/ppc/fdt.h" 38 #include "hw/qdev-properties.h" 39 #include "hw/intc/ppc-uic.h" 40 41 #include <libfdt.h> 42 43 #define BINARY_DEVICE_TREE_FILE "canyonlands.dtb" 44 #define UBOOT_FILENAME "u-boot-sam460-20100605.bin" 45 /* to extract the official U-Boot bin from the updater: */ 46 /* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x80000)) \ 47 if=updater/updater-460 of=u-boot-sam460-20100605.bin */ 48 49 #define PCIE0_DCRN_BASE 0x100 50 #define PCIE1_DCRN_BASE 0x120 51 52 /* from Sam460 U-Boot include/configs/Sam460ex.h */ 53 #define FLASH_BASE 0xfff00000 54 #define FLASH_BASE_H 0x4 55 #define FLASH_SIZE (1 * MiB) 56 #define UBOOT_LOAD_BASE 0xfff80000 57 #define UBOOT_SIZE 0x00080000 58 #define UBOOT_ENTRY 0xfffffffc 59 60 /* from U-Boot */ 61 #define EPAPR_MAGIC (0x45504150) 62 #define KERNEL_ADDR 0x1000000 63 #define FDT_ADDR 0x1800000 64 #define RAMDISK_ADDR 0x1900000 65 66 /* Sam460ex IRQ MAP: 67 IRQ0 = ETH_INT 68 IRQ1 = FPGA_INT 69 IRQ2 = PCI_INT (PCIA, PCIB, PCIC, PCIB) 70 IRQ3 = FPGA_INT2 71 IRQ11 = RTC_INT 72 IRQ12 = SM502_INT 73 */ 74 75 #define CPU_FREQ 1150000000 76 #define PLB_FREQ 230000000 77 #define OPB_FREQ 115000000 78 #define EBC_FREQ 115000000 79 #define UART_FREQ 11059200 80 81 struct boot_info { 82 uint32_t dt_base; 83 uint32_t dt_size; 84 uint32_t entry; 85 }; 86 87 static int sam460ex_load_uboot(void) 88 { 89 /* 90 * This first creates 1MiB of flash memory mapped at the end of 91 * the 32-bit address space (0xFFF00000..0xFFFFFFFF). 92 * 93 * If_PFLASH unit 0 is defined, the flash memory is initialized 94 * from that block backend. 95 * 96 * Else, it's initialized to zero. And then 512KiB of ROM get 97 * mapped on top of its second half (0xFFF80000..0xFFFFFFFF), 98 * initialized from u-boot-sam460-20100605.bin. 99 * 100 * This doesn't smell right. 101 * 102 * The physical hardware appears to have 512KiB flash memory. 103 * 104 * TODO Figure out what we really need here, and clean this up. 105 */ 106 107 DriveInfo *dinfo; 108 109 dinfo = drive_get(IF_PFLASH, 0, 0); 110 if (!pflash_cfi01_register(FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32), 111 "sam460ex.flash", FLASH_SIZE, 112 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 113 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1)) { 114 error_report("Error registering flash memory"); 115 /* XXX: return an error instead? */ 116 exit(1); 117 } 118 119 if (!dinfo) { 120 /*error_report("No flash image given with the 'pflash' parameter," 121 " using default u-boot image");*/ 122 rom_add_file_fixed(UBOOT_FILENAME, 123 UBOOT_LOAD_BASE | ((hwaddr)FLASH_BASE_H << 32), 124 -1); 125 } 126 127 return 0; 128 } 129 130 static int sam460ex_load_device_tree(MachineState *machine, 131 hwaddr addr, 132 hwaddr initrd_base, 133 hwaddr initrd_size) 134 { 135 uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(machine->ram_size) }; 136 char *filename; 137 int fdt_size; 138 void *fdt; 139 uint32_t tb_freq = CPU_FREQ; 140 uint32_t clock_freq = CPU_FREQ; 141 int offset; 142 143 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); 144 if (!filename) { 145 error_report("Couldn't find dtb file `%s'", BINARY_DEVICE_TREE_FILE); 146 exit(1); 147 } 148 fdt = load_device_tree(filename, &fdt_size); 149 if (!fdt) { 150 error_report("Couldn't load dtb file `%s'", filename); 151 g_free(filename); 152 exit(1); 153 } 154 g_free(filename); 155 156 /* Manipulate device tree in memory. */ 157 158 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 159 sizeof(mem_reg_property)); 160 161 /* default FDT doesn't have a /chosen node... */ 162 qemu_fdt_add_subnode(fdt, "/chosen"); 163 164 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", initrd_base); 165 166 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 167 (initrd_base + initrd_size)); 168 169 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 170 machine->kernel_cmdline); 171 172 /* Copy data from the host device tree into the guest. Since the guest can 173 * directly access the timebase without host involvement, we must expose 174 * the correct frequencies. */ 175 if (kvm_enabled()) { 176 tb_freq = kvmppc_get_tbfreq(); 177 clock_freq = kvmppc_get_clockfreq(); 178 } 179 180 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency", 181 clock_freq); 182 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency", 183 tb_freq); 184 185 /* Remove cpm node if it exists (it is not emulated) */ 186 offset = fdt_path_offset(fdt, "/cpm"); 187 if (offset >= 0) { 188 _FDT(fdt_nop_node(fdt, offset)); 189 } 190 191 /* set serial port clocks */ 192 offset = fdt_node_offset_by_compatible(fdt, -1, "ns16550"); 193 while (offset >= 0) { 194 _FDT(fdt_setprop_cell(fdt, offset, "clock-frequency", UART_FREQ)); 195 offset = fdt_node_offset_by_compatible(fdt, offset, "ns16550"); 196 } 197 198 /* some more clocks */ 199 qemu_fdt_setprop_cell(fdt, "/plb", "clock-frequency", 200 PLB_FREQ); 201 qemu_fdt_setprop_cell(fdt, "/plb/opb", "clock-frequency", 202 OPB_FREQ); 203 qemu_fdt_setprop_cell(fdt, "/plb/opb/ebc", "clock-frequency", 204 EBC_FREQ); 205 206 rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); 207 208 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ 209 machine->fdt = fdt; 210 211 return fdt_size; 212 } 213 214 /* Create reset TLB entries for BookE, mapping only the flash memory. */ 215 static void mmubooke_create_initial_mapping_uboot(CPUPPCState *env) 216 { 217 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 218 219 /* on reset the flash is mapped by a shadow TLB, 220 * but since we don't implement them we need to use 221 * the same values U-Boot will use to avoid a fault. 222 */ 223 tlb->attr = 0; 224 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 225 tlb->size = 0x10000000; /* up to 0xffffffff */ 226 tlb->EPN = 0xf0000000 & TARGET_PAGE_MASK; 227 tlb->RPN = (0xf0000000 & TARGET_PAGE_MASK) | 0x4; 228 tlb->PID = 0; 229 } 230 231 /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ 232 static void mmubooke_create_initial_mapping(CPUPPCState *env, 233 target_ulong va, 234 hwaddr pa) 235 { 236 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 237 238 tlb->attr = 0; 239 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 240 tlb->size = 1 << 31; /* up to 0x80000000 */ 241 tlb->EPN = va & TARGET_PAGE_MASK; 242 tlb->RPN = pa & TARGET_PAGE_MASK; 243 tlb->PID = 0; 244 } 245 246 static void main_cpu_reset(void *opaque) 247 { 248 PowerPCCPU *cpu = opaque; 249 CPUPPCState *env = &cpu->env; 250 struct boot_info *bi = env->load_info; 251 252 cpu_reset(CPU(cpu)); 253 254 /* either we have a kernel to boot or we jump to U-Boot */ 255 if (bi->entry != UBOOT_ENTRY) { 256 env->gpr[1] = (16 * MiB) - 8; 257 env->gpr[3] = FDT_ADDR; 258 env->nip = bi->entry; 259 260 /* Create a mapping for the kernel. */ 261 mmubooke_create_initial_mapping(env, 0, 0); 262 env->gpr[6] = tswap32(EPAPR_MAGIC); 263 env->gpr[7] = (16 * MiB) - 8; /* bi->ima_size; */ 264 265 } else { 266 env->nip = UBOOT_ENTRY; 267 mmubooke_create_initial_mapping_uboot(env); 268 } 269 } 270 271 static void sam460ex_init(MachineState *machine) 272 { 273 MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1); 274 DeviceState *uic[4]; 275 int i; 276 PCIBus *pci_bus; 277 USBBus *usb_bus; 278 PowerPCCPU *cpu; 279 CPUPPCState *env; 280 I2CBus *i2c; 281 hwaddr entry = UBOOT_ENTRY; 282 target_long initrd_size = 0; 283 DeviceState *dev; 284 SysBusDevice *sbdev; 285 struct boot_info *boot_info; 286 uint8_t *spd_data; 287 int success; 288 289 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 290 env = &cpu->env; 291 if (env->mmu_model != POWERPC_MMU_BOOKE) { 292 error_report("Only MMU model BookE is supported by this machine."); 293 exit(1); 294 } 295 296 qemu_register_reset(main_cpu_reset, cpu); 297 boot_info = g_malloc0(sizeof(*boot_info)); 298 env->load_info = boot_info; 299 300 ppc_booke_timers_init(cpu, CPU_FREQ, 0); 301 ppc_dcr_init(env, NULL, NULL); 302 303 /* PLB arbitrer */ 304 dev = qdev_new(TYPE_PPC4xx_PLB); 305 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); 306 object_unref(OBJECT(dev)); 307 308 /* interrupt controllers */ 309 for (i = 0; i < ARRAY_SIZE(uic); i++) { 310 /* 311 * UICs 1, 2 and 3 are cascaded through UIC 0. 312 * input_ints[n] is the interrupt number on UIC 0 which 313 * the INT output of UIC n is connected to. The CINT output 314 * of UIC n connects to input_ints[n] + 1. 315 * The entry in input_ints[] for UIC 0 is ignored, because UIC 0's 316 * INT and CINT outputs are connected to the CPU. 317 */ 318 const int input_ints[] = { -1, 30, 10, 16 }; 319 320 uic[i] = qdev_new(TYPE_PPC_UIC); 321 qdev_prop_set_uint32(uic[i], "dcr-base", 0xc0 + i * 0x10); 322 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uic[i]), cpu, &error_fatal); 323 object_unref(OBJECT(uic[i])); 324 325 sbdev = SYS_BUS_DEVICE(uic[i]); 326 if (i == 0) { 327 sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT, 328 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT)); 329 sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT, 330 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT)); 331 } else { 332 sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT, 333 qdev_get_gpio_in(uic[0], input_ints[i])); 334 sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT, 335 qdev_get_gpio_in(uic[0], input_ints[i] + 1)); 336 } 337 } 338 339 /* SDRAM controller */ 340 /* The SoC could also handle 4 GiB but firmware does not work with that. */ 341 if (machine->ram_size > 2 * GiB) { 342 error_report("Memory over 2 GiB is not supported"); 343 exit(1); 344 } 345 /* Firmware needs at least 64 MiB */ 346 if (machine->ram_size < 64 * MiB) { 347 error_report("Memory below 64 MiB is not supported"); 348 exit(1); 349 } 350 dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR2); 351 object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram), 352 &error_abort); 353 /* 354 * Put all RAM on first bank because board has one slot 355 * and firmware only checks that 356 */ 357 object_property_set_int(OBJECT(dev), "nbanks", 1, &error_abort); 358 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); 359 object_unref(OBJECT(dev)); 360 /* FIXME: does 460EX have ECC interrupts? */ 361 /* Enable SDRAM memory regions as we may boot without firmware */ 362 ppc4xx_sdram_ddr2_enable(PPC4xx_SDRAM_DDR2(dev)); 363 364 /* IIC controllers and devices */ 365 dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, 366 qdev_get_gpio_in(uic[0], 2)); 367 i2c = PPC4xx_I2C(dev)->bus; 368 /* SPD EEPROM on RAM module */ 369 spd_data = spd_data_generate(machine->ram_size < 128 * MiB ? DDR : DDR2, 370 machine->ram_size); 371 spd_data[20] = 4; /* SO-DIMM module */ 372 smbus_eeprom_init_one(i2c, 0x50, spd_data); 373 /* RTC */ 374 i2c_slave_create_simple(i2c, "m41t80", 0x68); 375 376 dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, 377 qdev_get_gpio_in(uic[0], 3)); 378 379 /* External bus controller */ 380 dev = qdev_new(TYPE_PPC4xx_EBC); 381 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); 382 object_unref(OBJECT(dev)); 383 384 /* CPR */ 385 ppc4xx_cpr_init(env); 386 387 /* PLB to AHB bridge */ 388 ppc4xx_ahb_init(env); 389 390 /* System DCRs */ 391 ppc4xx_sdr_init(env); 392 393 /* MAL */ 394 dev = qdev_new(TYPE_PPC4xx_MAL); 395 qdev_prop_set_uint8(dev, "txc-num", 4); 396 qdev_prop_set_uint8(dev, "rxc-num", 16); 397 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); 398 object_unref(OBJECT(dev)); 399 sbdev = SYS_BUS_DEVICE(dev); 400 for (i = 0; i < ARRAY_SIZE(PPC4xx_MAL(dev)->irqs); i++) { 401 sysbus_connect_irq(sbdev, i, qdev_get_gpio_in(uic[2], 3 + i)); 402 } 403 404 /* DMA */ 405 ppc4xx_dma_init(env, 0x200); 406 407 /* 256K of L2 cache as memory */ 408 ppc4xx_l2sram_init(env); 409 /* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */ 410 memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 * KiB, 411 &error_abort); 412 memory_region_add_subregion(get_system_memory(), 0x400000000LL, 413 l2cache_ram); 414 415 /* USB */ 416 sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, 417 qdev_get_gpio_in(uic[2], 29)); 418 dev = qdev_new("sysbus-ohci"); 419 qdev_prop_set_string(dev, "masterbus", "usb-bus.0"); 420 qdev_prop_set_uint32(dev, "num-ports", 6); 421 sbdev = SYS_BUS_DEVICE(dev); 422 sysbus_realize_and_unref(sbdev, &error_fatal); 423 sysbus_mmio_map(sbdev, 0, 0x4bffd0000); 424 sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(uic[2], 30)); 425 usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS, 426 &error_abort)); 427 usb_create_simple(usb_bus, "usb-kbd"); 428 usb_create_simple(usb_bus, "usb-mouse"); 429 430 /* PCIe buses */ 431 dev = qdev_new(TYPE_PPC460EX_PCIE_HOST); 432 qdev_prop_set_int32(dev, "busnum", 0); 433 qdev_prop_set_int32(dev, "dcrn-base", PCIE0_DCRN_BASE); 434 object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort); 435 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 436 437 dev = qdev_new(TYPE_PPC460EX_PCIE_HOST); 438 qdev_prop_set_int32(dev, "busnum", 1); 439 qdev_prop_set_int32(dev, "dcrn-base", PCIE1_DCRN_BASE); 440 object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort); 441 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 442 443 /* PCI bus */ 444 /* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */ 445 dev = sysbus_create_simple(TYPE_PPC440_PCIX_HOST, 0xc0ec00000, 446 qdev_get_gpio_in(uic[1], 0)); 447 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, 0xc08000000); 448 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); 449 450 /* PCI devices */ 451 pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501"); 452 /* SoC has a single SATA port but we don't emulate that yet 453 * However, firmware and usual clients have driver for SiI311x 454 * so add one for convenience by default */ 455 if (defaults_enabled()) { 456 pci_create_simple(pci_bus, -1, "sii3112"); 457 } 458 459 /* SoC has 4 UARTs 460 * but board has only one wired and two are present in fdt */ 461 if (serial_hd(0) != NULL) { 462 serial_mm_init(get_system_memory(), 0x4ef600300, 0, 463 qdev_get_gpio_in(uic[1], 1), 464 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 465 DEVICE_BIG_ENDIAN); 466 } 467 if (serial_hd(1) != NULL) { 468 serial_mm_init(get_system_memory(), 0x4ef600400, 0, 469 qdev_get_gpio_in(uic[0], 1), 470 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 471 DEVICE_BIG_ENDIAN); 472 } 473 474 /* Load U-Boot image. */ 475 if (!machine->kernel_filename) { 476 success = sam460ex_load_uboot(); 477 if (success < 0) { 478 error_report("could not load firmware"); 479 exit(1); 480 } 481 } 482 483 /* Load kernel. */ 484 if (machine->kernel_filename) { 485 hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 486 success = load_uimage(machine->kernel_filename, &entry, &loadaddr, 487 NULL, NULL, NULL); 488 if (success < 0) { 489 uint64_t elf_entry; 490 491 success = load_elf(machine->kernel_filename, NULL, NULL, NULL, 492 &elf_entry, NULL, NULL, NULL, 493 1, PPC_ELF_MACHINE, 0, 0); 494 entry = elf_entry; 495 } 496 /* XXX try again as binary */ 497 if (success < 0) { 498 error_report("could not load kernel '%s'", 499 machine->kernel_filename); 500 exit(1); 501 } 502 } 503 504 /* Load initrd. */ 505 if (machine->initrd_filename) { 506 initrd_size = load_image_targphys(machine->initrd_filename, 507 RAMDISK_ADDR, 508 machine->ram_size - RAMDISK_ADDR); 509 if (initrd_size < 0) { 510 error_report("could not load ram disk '%s' at %x", 511 machine->initrd_filename, RAMDISK_ADDR); 512 exit(1); 513 } 514 } 515 516 /* If we're loading a kernel directly, we must load the device tree too. */ 517 if (machine->kernel_filename) { 518 int dt_size; 519 520 dt_size = sam460ex_load_device_tree(machine, FDT_ADDR, 521 RAMDISK_ADDR, initrd_size); 522 523 boot_info->dt_base = FDT_ADDR; 524 boot_info->dt_size = dt_size; 525 } 526 527 boot_info->entry = entry; 528 } 529 530 static void sam460ex_machine_init(MachineClass *mc) 531 { 532 mc->desc = "aCube Sam460ex"; 533 mc->init = sam460ex_init; 534 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb"); 535 mc->default_ram_size = 512 * MiB; 536 mc->default_ram_id = "ppc4xx.sdram"; 537 } 538 539 DEFINE_MACHINE("sam460ex", sam460ex_machine_init) 540