1 /* 2 * QEMU aCube Sam460ex board emulation 3 * 4 * Copyright (c) 2012 François Revol 5 * Copyright (c) 2016-2019 BALATON Zoltan 6 * 7 * This file is derived from hw/ppc440_bamboo.c, 8 * the copyright for that material belongs to the original owners. 9 * 10 * This work is licensed under the GNU GPL license version 2 or later. 11 * 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu/units.h" 16 #include "qemu-common.h" 17 #include "qemu/datadir.h" 18 #include "qemu/error-report.h" 19 #include "qapi/error.h" 20 #include "hw/boards.h" 21 #include "sysemu/kvm.h" 22 #include "kvm_ppc.h" 23 #include "sysemu/device_tree.h" 24 #include "sysemu/block-backend.h" 25 #include "hw/loader.h" 26 #include "elf.h" 27 #include "exec/address-spaces.h" 28 #include "exec/memory.h" 29 #include "ppc440.h" 30 #include "ppc405.h" 31 #include "hw/block/flash.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/qtest.h" 34 #include "sysemu/reset.h" 35 #include "hw/sysbus.h" 36 #include "hw/char/serial.h" 37 #include "hw/i2c/ppc4xx_i2c.h" 38 #include "hw/i2c/smbus_eeprom.h" 39 #include "hw/usb/hcd-ehci.h" 40 #include "hw/ppc/fdt.h" 41 #include "hw/qdev-properties.h" 42 #include "hw/intc/ppc-uic.h" 43 44 #include <libfdt.h> 45 46 #define BINARY_DEVICE_TREE_FILE "canyonlands.dtb" 47 #define UBOOT_FILENAME "u-boot-sam460-20100605.bin" 48 /* to extract the official U-Boot bin from the updater: */ 49 /* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x80000)) \ 50 if=updater/updater-460 of=u-boot-sam460-20100605.bin */ 51 52 /* from Sam460 U-Boot include/configs/Sam460ex.h */ 53 #define FLASH_BASE 0xfff00000 54 #define FLASH_BASE_H 0x4 55 #define FLASH_SIZE (1 * MiB) 56 #define UBOOT_LOAD_BASE 0xfff80000 57 #define UBOOT_SIZE 0x00080000 58 #define UBOOT_ENTRY 0xfffffffc 59 60 /* from U-Boot */ 61 #define EPAPR_MAGIC (0x45504150) 62 #define KERNEL_ADDR 0x1000000 63 #define FDT_ADDR 0x1800000 64 #define RAMDISK_ADDR 0x1900000 65 66 /* Sam460ex IRQ MAP: 67 IRQ0 = ETH_INT 68 IRQ1 = FPGA_INT 69 IRQ2 = PCI_INT (PCIA, PCIB, PCIC, PCIB) 70 IRQ3 = FPGA_INT2 71 IRQ11 = RTC_INT 72 IRQ12 = SM502_INT 73 */ 74 75 #define CPU_FREQ 1150000000 76 #define PLB_FREQ 230000000 77 #define OPB_FREQ 115000000 78 #define EBC_FREQ 115000000 79 #define UART_FREQ 11059200 80 #define SDRAM_NR_BANKS 4 81 82 /* The SoC could also handle 4 GiB but firmware does not work with that. */ 83 /* Maybe it overflows a signed 32 bit number somewhere? */ 84 static const ram_addr_t ppc460ex_sdram_bank_sizes[] = { 85 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB, 86 32 * MiB, 0 87 }; 88 89 struct boot_info { 90 uint32_t dt_base; 91 uint32_t dt_size; 92 uint32_t entry; 93 }; 94 95 static int sam460ex_load_uboot(void) 96 { 97 /* 98 * This first creates 1MiB of flash memory mapped at the end of 99 * the 32-bit address space (0xFFF00000..0xFFFFFFFF). 100 * 101 * If_PFLASH unit 0 is defined, the flash memory is initialized 102 * from that block backend. 103 * 104 * Else, it's initialized to zero. And then 512KiB of ROM get 105 * mapped on top of its second half (0xFFF80000..0xFFFFFFFF), 106 * initialized from u-boot-sam460-20100605.bin. 107 * 108 * This doesn't smell right. 109 * 110 * The physical hardware appears to have 512KiB flash memory. 111 * 112 * TODO Figure out what we really need here, and clean this up. 113 */ 114 115 DriveInfo *dinfo; 116 117 dinfo = drive_get(IF_PFLASH, 0, 0); 118 if (!pflash_cfi01_register(FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32), 119 "sam460ex.flash", FLASH_SIZE, 120 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 121 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1)) { 122 error_report("Error registering flash memory"); 123 /* XXX: return an error instead? */ 124 exit(1); 125 } 126 127 if (!dinfo) { 128 /*error_report("No flash image given with the 'pflash' parameter," 129 " using default u-boot image");*/ 130 rom_add_file_fixed(UBOOT_FILENAME, 131 UBOOT_LOAD_BASE | ((hwaddr)FLASH_BASE_H << 32), 132 -1); 133 } 134 135 return 0; 136 } 137 138 static int sam460ex_load_device_tree(hwaddr addr, 139 uint32_t ramsize, 140 hwaddr initrd_base, 141 hwaddr initrd_size, 142 const char *kernel_cmdline) 143 { 144 uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) }; 145 char *filename; 146 int fdt_size; 147 void *fdt; 148 uint32_t tb_freq = CPU_FREQ; 149 uint32_t clock_freq = CPU_FREQ; 150 int offset; 151 152 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); 153 if (!filename) { 154 error_report("Couldn't find dtb file `%s'", BINARY_DEVICE_TREE_FILE); 155 exit(1); 156 } 157 fdt = load_device_tree(filename, &fdt_size); 158 if (!fdt) { 159 error_report("Couldn't load dtb file `%s'", filename); 160 g_free(filename); 161 exit(1); 162 } 163 g_free(filename); 164 165 /* Manipulate device tree in memory. */ 166 167 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 168 sizeof(mem_reg_property)); 169 170 /* default FDT doesn't have a /chosen node... */ 171 qemu_fdt_add_subnode(fdt, "/chosen"); 172 173 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", initrd_base); 174 175 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 176 (initrd_base + initrd_size)); 177 178 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline); 179 180 /* Copy data from the host device tree into the guest. Since the guest can 181 * directly access the timebase without host involvement, we must expose 182 * the correct frequencies. */ 183 if (kvm_enabled()) { 184 tb_freq = kvmppc_get_tbfreq(); 185 clock_freq = kvmppc_get_clockfreq(); 186 } 187 188 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency", 189 clock_freq); 190 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency", 191 tb_freq); 192 193 /* Remove cpm node if it exists (it is not emulated) */ 194 offset = fdt_path_offset(fdt, "/cpm"); 195 if (offset >= 0) { 196 _FDT(fdt_nop_node(fdt, offset)); 197 } 198 199 /* set serial port clocks */ 200 offset = fdt_node_offset_by_compatible(fdt, -1, "ns16550"); 201 while (offset >= 0) { 202 _FDT(fdt_setprop_cell(fdt, offset, "clock-frequency", UART_FREQ)); 203 offset = fdt_node_offset_by_compatible(fdt, offset, "ns16550"); 204 } 205 206 /* some more clocks */ 207 qemu_fdt_setprop_cell(fdt, "/plb", "clock-frequency", 208 PLB_FREQ); 209 qemu_fdt_setprop_cell(fdt, "/plb/opb", "clock-frequency", 210 OPB_FREQ); 211 qemu_fdt_setprop_cell(fdt, "/plb/opb/ebc", "clock-frequency", 212 EBC_FREQ); 213 214 rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); 215 g_free(fdt); 216 217 return fdt_size; 218 } 219 220 /* Create reset TLB entries for BookE, mapping only the flash memory. */ 221 static void mmubooke_create_initial_mapping_uboot(CPUPPCState *env) 222 { 223 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 224 225 /* on reset the flash is mapped by a shadow TLB, 226 * but since we don't implement them we need to use 227 * the same values U-Boot will use to avoid a fault. 228 */ 229 tlb->attr = 0; 230 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 231 tlb->size = 0x10000000; /* up to 0xffffffff */ 232 tlb->EPN = 0xf0000000 & TARGET_PAGE_MASK; 233 tlb->RPN = (0xf0000000 & TARGET_PAGE_MASK) | 0x4; 234 tlb->PID = 0; 235 } 236 237 /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ 238 static void mmubooke_create_initial_mapping(CPUPPCState *env, 239 target_ulong va, 240 hwaddr pa) 241 { 242 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 243 244 tlb->attr = 0; 245 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 246 tlb->size = 1 << 31; /* up to 0x80000000 */ 247 tlb->EPN = va & TARGET_PAGE_MASK; 248 tlb->RPN = pa & TARGET_PAGE_MASK; 249 tlb->PID = 0; 250 } 251 252 static void main_cpu_reset(void *opaque) 253 { 254 PowerPCCPU *cpu = opaque; 255 CPUPPCState *env = &cpu->env; 256 struct boot_info *bi = env->load_info; 257 258 cpu_reset(CPU(cpu)); 259 260 /* either we have a kernel to boot or we jump to U-Boot */ 261 if (bi->entry != UBOOT_ENTRY) { 262 env->gpr[1] = (16 * MiB) - 8; 263 env->gpr[3] = FDT_ADDR; 264 env->nip = bi->entry; 265 266 /* Create a mapping for the kernel. */ 267 mmubooke_create_initial_mapping(env, 0, 0); 268 env->gpr[6] = tswap32(EPAPR_MAGIC); 269 env->gpr[7] = (16 * MiB) - 8; /* bi->ima_size; */ 270 271 } else { 272 env->nip = UBOOT_ENTRY; 273 mmubooke_create_initial_mapping_uboot(env); 274 } 275 } 276 277 static void sam460ex_init(MachineState *machine) 278 { 279 MemoryRegion *address_space_mem = get_system_memory(); 280 MemoryRegion *isa = g_new(MemoryRegion, 1); 281 MemoryRegion *ram_memories = g_new(MemoryRegion, SDRAM_NR_BANKS); 282 hwaddr ram_bases[SDRAM_NR_BANKS] = {0}; 283 hwaddr ram_sizes[SDRAM_NR_BANKS] = {0}; 284 MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1); 285 DeviceState *uic[4]; 286 qemu_irq mal_irqs[4]; 287 int i; 288 PCIBus *pci_bus; 289 PowerPCCPU *cpu; 290 CPUPPCState *env; 291 I2CBus *i2c; 292 hwaddr entry = UBOOT_ENTRY; 293 target_long initrd_size = 0; 294 DeviceState *dev; 295 SysBusDevice *sbdev; 296 struct boot_info *boot_info; 297 uint8_t *spd_data; 298 int success; 299 300 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 301 env = &cpu->env; 302 if (env->mmu_model != POWERPC_MMU_BOOKE) { 303 error_report("Only MMU model BookE is supported by this machine."); 304 exit(1); 305 } 306 307 qemu_register_reset(main_cpu_reset, cpu); 308 boot_info = g_malloc0(sizeof(*boot_info)); 309 env->load_info = boot_info; 310 311 ppc_booke_timers_init(cpu, CPU_FREQ, 0); 312 ppc_dcr_init(env, NULL, NULL); 313 314 /* PLB arbitrer */ 315 ppc4xx_plb_init(env); 316 317 /* interrupt controllers */ 318 for (i = 0; i < ARRAY_SIZE(uic); i++) { 319 SysBusDevice *sbd; 320 /* 321 * UICs 1, 2 and 3 are cascaded through UIC 0. 322 * input_ints[n] is the interrupt number on UIC 0 which 323 * the INT output of UIC n is connected to. The CINT output 324 * of UIC n connects to input_ints[n] + 1. 325 * The entry in input_ints[] for UIC 0 is ignored, because UIC 0's 326 * INT and CINT outputs are connected to the CPU. 327 */ 328 const int input_ints[] = { -1, 30, 10, 16 }; 329 330 uic[i] = qdev_new(TYPE_PPC_UIC); 331 sbd = SYS_BUS_DEVICE(uic[i]); 332 333 qdev_prop_set_uint32(uic[i], "dcr-base", 0xc0 + i * 0x10); 334 object_property_set_link(OBJECT(uic[i]), "cpu", OBJECT(cpu), 335 &error_fatal); 336 sysbus_realize_and_unref(sbd, &error_fatal); 337 338 if (i == 0) { 339 sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT, 340 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]); 341 sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT, 342 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]); 343 } else { 344 sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT, 345 qdev_get_gpio_in(uic[0], input_ints[i])); 346 sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT, 347 qdev_get_gpio_in(uic[0], input_ints[i] + 1)); 348 } 349 } 350 351 /* SDRAM controller */ 352 /* put all RAM on first bank because board has one slot 353 * and firmware only checks that */ 354 ppc4xx_sdram_banks(machine->ram, 1, ram_memories, ram_bases, ram_sizes, 355 ppc460ex_sdram_bank_sizes); 356 357 /* FIXME: does 460EX have ECC interrupts? */ 358 ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories, 359 ram_bases, ram_sizes, 1); 360 361 /* IIC controllers and devices */ 362 dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, 363 qdev_get_gpio_in(uic[0], 2)); 364 i2c = PPC4xx_I2C(dev)->bus; 365 /* SPD EEPROM on RAM module */ 366 spd_data = spd_data_generate(ram_sizes[0] < 128 * MiB ? DDR : DDR2, 367 ram_sizes[0]); 368 spd_data[20] = 4; /* SO-DIMM module */ 369 smbus_eeprom_init_one(i2c, 0x50, spd_data); 370 /* RTC */ 371 i2c_slave_create_simple(i2c, "m41t80", 0x68); 372 373 dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, 374 qdev_get_gpio_in(uic[0], 3)); 375 376 /* External bus controller */ 377 ppc405_ebc_init(env); 378 379 /* CPR */ 380 ppc4xx_cpr_init(env); 381 382 /* PLB to AHB bridge */ 383 ppc4xx_ahb_init(env); 384 385 /* System DCRs */ 386 ppc4xx_sdr_init(env); 387 388 /* MAL */ 389 for (i = 0; i < ARRAY_SIZE(mal_irqs); i++) { 390 mal_irqs[0] = qdev_get_gpio_in(uic[2], 3 + i); 391 } 392 ppc4xx_mal_init(env, 4, 16, mal_irqs); 393 394 /* DMA */ 395 ppc4xx_dma_init(env, 0x200); 396 397 /* 256K of L2 cache as memory */ 398 ppc4xx_l2sram_init(env); 399 /* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */ 400 memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 * KiB, 401 &error_abort); 402 memory_region_add_subregion(address_space_mem, 0x400000000LL, l2cache_ram); 403 404 /* USB */ 405 sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, 406 qdev_get_gpio_in(uic[2], 29)); 407 dev = qdev_new("sysbus-ohci"); 408 qdev_prop_set_string(dev, "masterbus", "usb-bus.0"); 409 qdev_prop_set_uint32(dev, "num-ports", 6); 410 sbdev = SYS_BUS_DEVICE(dev); 411 sysbus_realize_and_unref(sbdev, &error_fatal); 412 sysbus_mmio_map(sbdev, 0, 0x4bffd0000); 413 sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(uic[2], 30)); 414 usb_create_simple(usb_bus_find(-1), "usb-kbd"); 415 usb_create_simple(usb_bus_find(-1), "usb-mouse"); 416 417 /* PCI bus */ 418 ppc460ex_pcie_init(env); 419 /* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */ 420 dev = sysbus_create_simple("ppc440-pcix-host", 0xc0ec00000, 421 qdev_get_gpio_in(uic[1], 0)); 422 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); 423 424 memory_region_init_alias(isa, NULL, "isa_mmio", get_system_io(), 425 0, 0x10000); 426 memory_region_add_subregion(get_system_memory(), 0xc08000000, isa); 427 428 /* PCI devices */ 429 pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501"); 430 /* SoC has a single SATA port but we don't emulate that yet 431 * However, firmware and usual clients have driver for SiI311x 432 * so add one for convenience by default */ 433 if (defaults_enabled()) { 434 pci_create_simple(pci_bus, -1, "sii3112"); 435 } 436 437 /* SoC has 4 UARTs 438 * but board has only one wired and two are present in fdt */ 439 if (serial_hd(0) != NULL) { 440 serial_mm_init(address_space_mem, 0x4ef600300, 0, 441 qdev_get_gpio_in(uic[1], 1), 442 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 443 DEVICE_BIG_ENDIAN); 444 } 445 if (serial_hd(1) != NULL) { 446 serial_mm_init(address_space_mem, 0x4ef600400, 0, 447 qdev_get_gpio_in(uic[0], 1), 448 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 449 DEVICE_BIG_ENDIAN); 450 } 451 452 /* Load U-Boot image. */ 453 if (!machine->kernel_filename) { 454 success = sam460ex_load_uboot(); 455 if (success < 0) { 456 error_report("could not load firmware"); 457 exit(1); 458 } 459 } 460 461 /* Load kernel. */ 462 if (machine->kernel_filename) { 463 hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 464 success = load_uimage(machine->kernel_filename, &entry, &loadaddr, 465 NULL, NULL, NULL); 466 if (success < 0) { 467 uint64_t elf_entry; 468 469 success = load_elf(machine->kernel_filename, NULL, NULL, NULL, 470 &elf_entry, NULL, NULL, NULL, 471 1, PPC_ELF_MACHINE, 0, 0); 472 entry = elf_entry; 473 } 474 /* XXX try again as binary */ 475 if (success < 0) { 476 error_report("could not load kernel '%s'", 477 machine->kernel_filename); 478 exit(1); 479 } 480 } 481 482 /* Load initrd. */ 483 if (machine->initrd_filename) { 484 initrd_size = load_image_targphys(machine->initrd_filename, 485 RAMDISK_ADDR, 486 machine->ram_size - RAMDISK_ADDR); 487 if (initrd_size < 0) { 488 error_report("could not load ram disk '%s' at %x", 489 machine->initrd_filename, RAMDISK_ADDR); 490 exit(1); 491 } 492 } 493 494 /* If we're loading a kernel directly, we must load the device tree too. */ 495 if (machine->kernel_filename) { 496 int dt_size; 497 498 dt_size = sam460ex_load_device_tree(FDT_ADDR, machine->ram_size, 499 RAMDISK_ADDR, initrd_size, 500 machine->kernel_cmdline); 501 502 boot_info->dt_base = FDT_ADDR; 503 boot_info->dt_size = dt_size; 504 } 505 506 boot_info->entry = entry; 507 } 508 509 static void sam460ex_machine_init(MachineClass *mc) 510 { 511 mc->desc = "aCube Sam460ex"; 512 mc->init = sam460ex_init; 513 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb"); 514 mc->default_ram_size = 512 * MiB; 515 mc->default_ram_id = "ppc4xx.sdram"; 516 } 517 518 DEFINE_MACHINE("sam460ex", sam460ex_machine_init) 519