1 /* 2 * QEMU aCube Sam460ex board emulation 3 * 4 * Copyright (c) 2012 François Revol 5 * Copyright (c) 2016-2019 BALATON Zoltan 6 * 7 * This file is derived from hw/ppc440_bamboo.c, 8 * the copyright for that material belongs to the original owners. 9 * 10 * This work is licensed under the GNU GPL license version 2 or later. 11 * 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu/units.h" 16 #include "qemu/datadir.h" 17 #include "qemu/error-report.h" 18 #include "qapi/error.h" 19 #include "hw/boards.h" 20 #include "sysemu/kvm.h" 21 #include "kvm_ppc.h" 22 #include "sysemu/device_tree.h" 23 #include "sysemu/block-backend.h" 24 #include "hw/loader.h" 25 #include "elf.h" 26 #include "exec/memory.h" 27 #include "ppc440.h" 28 #include "hw/block/flash.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/reset.h" 31 #include "hw/sysbus.h" 32 #include "hw/char/serial.h" 33 #include "hw/i2c/ppc4xx_i2c.h" 34 #include "hw/i2c/smbus_eeprom.h" 35 #include "hw/usb/hcd-ehci.h" 36 #include "hw/ppc/fdt.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/intc/ppc-uic.h" 39 40 #include <libfdt.h> 41 42 #define BINARY_DEVICE_TREE_FILE "canyonlands.dtb" 43 #define UBOOT_FILENAME "u-boot-sam460-20100605.bin" 44 /* to extract the official U-Boot bin from the updater: */ 45 /* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x80000)) \ 46 if=updater/updater-460 of=u-boot-sam460-20100605.bin */ 47 48 /* from Sam460 U-Boot include/configs/Sam460ex.h */ 49 #define FLASH_BASE 0xfff00000 50 #define FLASH_BASE_H 0x4 51 #define FLASH_SIZE (1 * MiB) 52 #define UBOOT_LOAD_BASE 0xfff80000 53 #define UBOOT_SIZE 0x00080000 54 #define UBOOT_ENTRY 0xfffffffc 55 56 /* from U-Boot */ 57 #define EPAPR_MAGIC (0x45504150) 58 #define KERNEL_ADDR 0x1000000 59 #define FDT_ADDR 0x1800000 60 #define RAMDISK_ADDR 0x1900000 61 62 /* Sam460ex IRQ MAP: 63 IRQ0 = ETH_INT 64 IRQ1 = FPGA_INT 65 IRQ2 = PCI_INT (PCIA, PCIB, PCIC, PCIB) 66 IRQ3 = FPGA_INT2 67 IRQ11 = RTC_INT 68 IRQ12 = SM502_INT 69 */ 70 71 #define CPU_FREQ 1150000000 72 #define PLB_FREQ 230000000 73 #define OPB_FREQ 115000000 74 #define EBC_FREQ 115000000 75 #define UART_FREQ 11059200 76 77 /* The SoC could also handle 4 GiB but firmware does not work with that. */ 78 /* Maybe it overflows a signed 32 bit number somewhere? */ 79 static const ram_addr_t ppc460ex_sdram_bank_sizes[] = { 80 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB, 81 32 * MiB, 0 82 }; 83 84 struct boot_info { 85 uint32_t dt_base; 86 uint32_t dt_size; 87 uint32_t entry; 88 }; 89 90 static int sam460ex_load_uboot(void) 91 { 92 /* 93 * This first creates 1MiB of flash memory mapped at the end of 94 * the 32-bit address space (0xFFF00000..0xFFFFFFFF). 95 * 96 * If_PFLASH unit 0 is defined, the flash memory is initialized 97 * from that block backend. 98 * 99 * Else, it's initialized to zero. And then 512KiB of ROM get 100 * mapped on top of its second half (0xFFF80000..0xFFFFFFFF), 101 * initialized from u-boot-sam460-20100605.bin. 102 * 103 * This doesn't smell right. 104 * 105 * The physical hardware appears to have 512KiB flash memory. 106 * 107 * TODO Figure out what we really need here, and clean this up. 108 */ 109 110 DriveInfo *dinfo; 111 112 dinfo = drive_get(IF_PFLASH, 0, 0); 113 if (!pflash_cfi01_register(FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32), 114 "sam460ex.flash", FLASH_SIZE, 115 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 116 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1)) { 117 error_report("Error registering flash memory"); 118 /* XXX: return an error instead? */ 119 exit(1); 120 } 121 122 if (!dinfo) { 123 /*error_report("No flash image given with the 'pflash' parameter," 124 " using default u-boot image");*/ 125 rom_add_file_fixed(UBOOT_FILENAME, 126 UBOOT_LOAD_BASE | ((hwaddr)FLASH_BASE_H << 32), 127 -1); 128 } 129 130 return 0; 131 } 132 133 static int sam460ex_load_device_tree(hwaddr addr, 134 uint32_t ramsize, 135 hwaddr initrd_base, 136 hwaddr initrd_size, 137 const char *kernel_cmdline) 138 { 139 uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) }; 140 char *filename; 141 int fdt_size; 142 void *fdt; 143 uint32_t tb_freq = CPU_FREQ; 144 uint32_t clock_freq = CPU_FREQ; 145 int offset; 146 147 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); 148 if (!filename) { 149 error_report("Couldn't find dtb file `%s'", BINARY_DEVICE_TREE_FILE); 150 exit(1); 151 } 152 fdt = load_device_tree(filename, &fdt_size); 153 if (!fdt) { 154 error_report("Couldn't load dtb file `%s'", filename); 155 g_free(filename); 156 exit(1); 157 } 158 g_free(filename); 159 160 /* Manipulate device tree in memory. */ 161 162 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 163 sizeof(mem_reg_property)); 164 165 /* default FDT doesn't have a /chosen node... */ 166 qemu_fdt_add_subnode(fdt, "/chosen"); 167 168 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", initrd_base); 169 170 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 171 (initrd_base + initrd_size)); 172 173 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline); 174 175 /* Copy data from the host device tree into the guest. Since the guest can 176 * directly access the timebase without host involvement, we must expose 177 * the correct frequencies. */ 178 if (kvm_enabled()) { 179 tb_freq = kvmppc_get_tbfreq(); 180 clock_freq = kvmppc_get_clockfreq(); 181 } 182 183 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency", 184 clock_freq); 185 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency", 186 tb_freq); 187 188 /* Remove cpm node if it exists (it is not emulated) */ 189 offset = fdt_path_offset(fdt, "/cpm"); 190 if (offset >= 0) { 191 _FDT(fdt_nop_node(fdt, offset)); 192 } 193 194 /* set serial port clocks */ 195 offset = fdt_node_offset_by_compatible(fdt, -1, "ns16550"); 196 while (offset >= 0) { 197 _FDT(fdt_setprop_cell(fdt, offset, "clock-frequency", UART_FREQ)); 198 offset = fdt_node_offset_by_compatible(fdt, offset, "ns16550"); 199 } 200 201 /* some more clocks */ 202 qemu_fdt_setprop_cell(fdt, "/plb", "clock-frequency", 203 PLB_FREQ); 204 qemu_fdt_setprop_cell(fdt, "/plb/opb", "clock-frequency", 205 OPB_FREQ); 206 qemu_fdt_setprop_cell(fdt, "/plb/opb/ebc", "clock-frequency", 207 EBC_FREQ); 208 209 rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); 210 g_free(fdt); 211 212 return fdt_size; 213 } 214 215 /* Create reset TLB entries for BookE, mapping only the flash memory. */ 216 static void mmubooke_create_initial_mapping_uboot(CPUPPCState *env) 217 { 218 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 219 220 /* on reset the flash is mapped by a shadow TLB, 221 * but since we don't implement them we need to use 222 * the same values U-Boot will use to avoid a fault. 223 */ 224 tlb->attr = 0; 225 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 226 tlb->size = 0x10000000; /* up to 0xffffffff */ 227 tlb->EPN = 0xf0000000 & TARGET_PAGE_MASK; 228 tlb->RPN = (0xf0000000 & TARGET_PAGE_MASK) | 0x4; 229 tlb->PID = 0; 230 } 231 232 /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ 233 static void mmubooke_create_initial_mapping(CPUPPCState *env, 234 target_ulong va, 235 hwaddr pa) 236 { 237 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 238 239 tlb->attr = 0; 240 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 241 tlb->size = 1 << 31; /* up to 0x80000000 */ 242 tlb->EPN = va & TARGET_PAGE_MASK; 243 tlb->RPN = pa & TARGET_PAGE_MASK; 244 tlb->PID = 0; 245 } 246 247 static void main_cpu_reset(void *opaque) 248 { 249 PowerPCCPU *cpu = opaque; 250 CPUPPCState *env = &cpu->env; 251 struct boot_info *bi = env->load_info; 252 253 cpu_reset(CPU(cpu)); 254 255 /* either we have a kernel to boot or we jump to U-Boot */ 256 if (bi->entry != UBOOT_ENTRY) { 257 env->gpr[1] = (16 * MiB) - 8; 258 env->gpr[3] = FDT_ADDR; 259 env->nip = bi->entry; 260 261 /* Create a mapping for the kernel. */ 262 mmubooke_create_initial_mapping(env, 0, 0); 263 env->gpr[6] = tswap32(EPAPR_MAGIC); 264 env->gpr[7] = (16 * MiB) - 8; /* bi->ima_size; */ 265 266 } else { 267 env->nip = UBOOT_ENTRY; 268 mmubooke_create_initial_mapping_uboot(env); 269 } 270 } 271 272 static void sam460ex_init(MachineState *machine) 273 { 274 MemoryRegion *address_space_mem = get_system_memory(); 275 MemoryRegion *isa = g_new(MemoryRegion, 1); 276 Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank, 1); 277 MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1); 278 DeviceState *uic[4]; 279 int i; 280 PCIBus *pci_bus; 281 PowerPCCPU *cpu; 282 CPUPPCState *env; 283 I2CBus *i2c; 284 hwaddr entry = UBOOT_ENTRY; 285 target_long initrd_size = 0; 286 DeviceState *dev; 287 SysBusDevice *sbdev; 288 struct boot_info *boot_info; 289 uint8_t *spd_data; 290 int success; 291 292 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 293 env = &cpu->env; 294 if (env->mmu_model != POWERPC_MMU_BOOKE) { 295 error_report("Only MMU model BookE is supported by this machine."); 296 exit(1); 297 } 298 299 qemu_register_reset(main_cpu_reset, cpu); 300 boot_info = g_malloc0(sizeof(*boot_info)); 301 env->load_info = boot_info; 302 303 ppc_booke_timers_init(cpu, CPU_FREQ, 0); 304 ppc_dcr_init(env, NULL, NULL); 305 306 /* PLB arbitrer */ 307 dev = qdev_new(TYPE_PPC4xx_PLB); 308 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); 309 object_unref(OBJECT(dev)); 310 311 /* interrupt controllers */ 312 for (i = 0; i < ARRAY_SIZE(uic); i++) { 313 /* 314 * UICs 1, 2 and 3 are cascaded through UIC 0. 315 * input_ints[n] is the interrupt number on UIC 0 which 316 * the INT output of UIC n is connected to. The CINT output 317 * of UIC n connects to input_ints[n] + 1. 318 * The entry in input_ints[] for UIC 0 is ignored, because UIC 0's 319 * INT and CINT outputs are connected to the CPU. 320 */ 321 const int input_ints[] = { -1, 30, 10, 16 }; 322 323 uic[i] = qdev_new(TYPE_PPC_UIC); 324 qdev_prop_set_uint32(uic[i], "dcr-base", 0xc0 + i * 0x10); 325 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uic[i]), cpu, &error_fatal); 326 object_unref(OBJECT(uic[i])); 327 328 sbdev = SYS_BUS_DEVICE(uic[i]); 329 if (i == 0) { 330 sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT, 331 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT)); 332 sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT, 333 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT)); 334 } else { 335 sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT, 336 qdev_get_gpio_in(uic[0], input_ints[i])); 337 sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT, 338 qdev_get_gpio_in(uic[0], input_ints[i] + 1)); 339 } 340 } 341 342 /* SDRAM controller */ 343 /* put all RAM on first bank because board has one slot 344 * and firmware only checks that */ 345 ppc4xx_sdram_banks(machine->ram, 1, ram_banks, ppc460ex_sdram_bank_sizes); 346 347 /* FIXME: does 460EX have ECC interrupts? */ 348 ppc440_sdram_init(env, 1, ram_banks); 349 /* Enable SDRAM memory regions as we may boot without firmware */ 350 ppc440_sdram_enable(env); 351 352 /* IIC controllers and devices */ 353 dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, 354 qdev_get_gpio_in(uic[0], 2)); 355 i2c = PPC4xx_I2C(dev)->bus; 356 /* SPD EEPROM on RAM module */ 357 spd_data = spd_data_generate(ram_banks->size < 128 * MiB ? DDR : DDR2, 358 ram_banks->size); 359 spd_data[20] = 4; /* SO-DIMM module */ 360 smbus_eeprom_init_one(i2c, 0x50, spd_data); 361 /* RTC */ 362 i2c_slave_create_simple(i2c, "m41t80", 0x68); 363 364 dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, 365 qdev_get_gpio_in(uic[0], 3)); 366 367 /* External bus controller */ 368 dev = qdev_new(TYPE_PPC4xx_EBC); 369 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); 370 object_unref(OBJECT(dev)); 371 372 /* CPR */ 373 ppc4xx_cpr_init(env); 374 375 /* PLB to AHB bridge */ 376 ppc4xx_ahb_init(env); 377 378 /* System DCRs */ 379 ppc4xx_sdr_init(env); 380 381 /* MAL */ 382 dev = qdev_new(TYPE_PPC4xx_MAL); 383 qdev_prop_set_uint32(dev, "txc-num", 4); 384 qdev_prop_set_uint32(dev, "rxc-num", 16); 385 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); 386 object_unref(OBJECT(dev)); 387 sbdev = SYS_BUS_DEVICE(dev); 388 for (i = 0; i < ARRAY_SIZE(PPC4xx_MAL(dev)->irqs); i++) { 389 sysbus_connect_irq(sbdev, i, qdev_get_gpio_in(uic[2], 3 + i)); 390 } 391 392 /* DMA */ 393 ppc4xx_dma_init(env, 0x200); 394 395 /* 256K of L2 cache as memory */ 396 ppc4xx_l2sram_init(env); 397 /* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */ 398 memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 * KiB, 399 &error_abort); 400 memory_region_add_subregion(address_space_mem, 0x400000000LL, l2cache_ram); 401 402 /* USB */ 403 sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, 404 qdev_get_gpio_in(uic[2], 29)); 405 dev = qdev_new("sysbus-ohci"); 406 qdev_prop_set_string(dev, "masterbus", "usb-bus.0"); 407 qdev_prop_set_uint32(dev, "num-ports", 6); 408 sbdev = SYS_BUS_DEVICE(dev); 409 sysbus_realize_and_unref(sbdev, &error_fatal); 410 sysbus_mmio_map(sbdev, 0, 0x4bffd0000); 411 sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(uic[2], 30)); 412 usb_create_simple(usb_bus_find(-1), "usb-kbd"); 413 usb_create_simple(usb_bus_find(-1), "usb-mouse"); 414 415 /* PCI bus */ 416 ppc460ex_pcie_init(env); 417 /* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */ 418 dev = sysbus_create_simple("ppc440-pcix-host", 0xc0ec00000, 419 qdev_get_gpio_in(uic[1], 0)); 420 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); 421 422 memory_region_init_alias(isa, NULL, "isa_mmio", get_system_io(), 423 0, 0x10000); 424 memory_region_add_subregion(get_system_memory(), 0xc08000000, isa); 425 426 /* PCI devices */ 427 pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501"); 428 /* SoC has a single SATA port but we don't emulate that yet 429 * However, firmware and usual clients have driver for SiI311x 430 * so add one for convenience by default */ 431 if (defaults_enabled()) { 432 pci_create_simple(pci_bus, -1, "sii3112"); 433 } 434 435 /* SoC has 4 UARTs 436 * but board has only one wired and two are present in fdt */ 437 if (serial_hd(0) != NULL) { 438 serial_mm_init(address_space_mem, 0x4ef600300, 0, 439 qdev_get_gpio_in(uic[1], 1), 440 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 441 DEVICE_BIG_ENDIAN); 442 } 443 if (serial_hd(1) != NULL) { 444 serial_mm_init(address_space_mem, 0x4ef600400, 0, 445 qdev_get_gpio_in(uic[0], 1), 446 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 447 DEVICE_BIG_ENDIAN); 448 } 449 450 /* Load U-Boot image. */ 451 if (!machine->kernel_filename) { 452 success = sam460ex_load_uboot(); 453 if (success < 0) { 454 error_report("could not load firmware"); 455 exit(1); 456 } 457 } 458 459 /* Load kernel. */ 460 if (machine->kernel_filename) { 461 hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 462 success = load_uimage(machine->kernel_filename, &entry, &loadaddr, 463 NULL, NULL, NULL); 464 if (success < 0) { 465 uint64_t elf_entry; 466 467 success = load_elf(machine->kernel_filename, NULL, NULL, NULL, 468 &elf_entry, NULL, NULL, NULL, 469 1, PPC_ELF_MACHINE, 0, 0); 470 entry = elf_entry; 471 } 472 /* XXX try again as binary */ 473 if (success < 0) { 474 error_report("could not load kernel '%s'", 475 machine->kernel_filename); 476 exit(1); 477 } 478 } 479 480 /* Load initrd. */ 481 if (machine->initrd_filename) { 482 initrd_size = load_image_targphys(machine->initrd_filename, 483 RAMDISK_ADDR, 484 machine->ram_size - RAMDISK_ADDR); 485 if (initrd_size < 0) { 486 error_report("could not load ram disk '%s' at %x", 487 machine->initrd_filename, RAMDISK_ADDR); 488 exit(1); 489 } 490 } 491 492 /* If we're loading a kernel directly, we must load the device tree too. */ 493 if (machine->kernel_filename) { 494 int dt_size; 495 496 dt_size = sam460ex_load_device_tree(FDT_ADDR, machine->ram_size, 497 RAMDISK_ADDR, initrd_size, 498 machine->kernel_cmdline); 499 500 boot_info->dt_base = FDT_ADDR; 501 boot_info->dt_size = dt_size; 502 } 503 504 boot_info->entry = entry; 505 } 506 507 static void sam460ex_machine_init(MachineClass *mc) 508 { 509 mc->desc = "aCube Sam460ex"; 510 mc->init = sam460ex_init; 511 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb"); 512 mc->default_ram_size = 512 * MiB; 513 mc->default_ram_id = "ppc4xx.sdram"; 514 } 515 516 DEFINE_MACHINE("sam460ex", sam460ex_machine_init) 517