1 /* 2 * QEMU RS/6000 memory controller 3 * 4 * Copyright (c) 2017 Hervé Poussineau 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 * 8 * This program is free software: you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation, either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qemu/units.h" 24 #include "hw/isa/isa.h" 25 #include "hw/qdev-properties.h" 26 #include "migration/vmstate.h" 27 #include "exec/address-spaces.h" 28 #include "qapi/error.h" 29 #include "trace.h" 30 #include "qom/object.h" 31 32 #define TYPE_RS6000MC "rs6000-mc" 33 OBJECT_DECLARE_SIMPLE_TYPE(RS6000MCState, RS6000MC) 34 35 struct RS6000MCState { 36 ISADevice parent_obj; 37 /* see US patent 5,684,979 for details (expired 2001-11-04) */ 38 uint32_t ram_size; 39 bool autoconfigure; 40 MemoryRegion simm[6]; 41 unsigned int simm_size[6]; 42 uint32_t end_address[8]; 43 uint8_t port0820_index; 44 PortioList portio; 45 }; 46 47 /* P0RT 0803 -- SIMM ID Register (32/8 MB) (Read Only) */ 48 49 static uint32_t rs6000mc_port0803_read(void *opaque, uint32_t addr) 50 { 51 RS6000MCState *s = opaque; 52 uint32_t val = 0; 53 int socket; 54 55 /* (1 << socket) indicates 32 MB SIMM at given socket */ 56 for (socket = 0; socket < 6; socket++) { 57 if (s->simm_size[socket] == 32) { 58 val |= (1 << socket); 59 } 60 } 61 62 trace_rs6000mc_id_read(addr, val); 63 return val; 64 } 65 66 /* PORT 0804 -- SIMM Presence Register (Read Only) */ 67 68 static uint32_t rs6000mc_port0804_read(void *opaque, uint32_t addr) 69 { 70 RS6000MCState *s = opaque; 71 uint32_t val = 0xff; 72 int socket; 73 74 /* (1 << socket) indicates SIMM absence at given socket */ 75 for (socket = 0; socket < 6; socket++) { 76 if (s->simm_size[socket]) { 77 val &= ~(1 << socket); 78 } 79 } 80 s->port0820_index = 0; 81 82 trace_rs6000mc_presence_read(addr, val); 83 return val; 84 } 85 86 /* Memory Controller Size Programming Register */ 87 88 static uint32_t rs6000mc_port0820_read(void *opaque, uint32_t addr) 89 { 90 RS6000MCState *s = opaque; 91 uint32_t val = s->end_address[s->port0820_index] & 0x1f; 92 s->port0820_index = (s->port0820_index + 1) & 7; 93 trace_rs6000mc_size_read(addr, val); 94 return val; 95 } 96 97 static void rs6000mc_port0820_write(void *opaque, uint32_t addr, uint32_t val) 98 { 99 RS6000MCState *s = opaque; 100 uint8_t socket = val >> 5; 101 uint32_t end_address = val & 0x1f; 102 103 trace_rs6000mc_size_write(addr, val); 104 s->end_address[socket] = end_address; 105 if (socket > 0 && socket < 7) { 106 if (s->simm_size[socket - 1]) { 107 uint32_t size; 108 uint32_t start_address = 0; 109 if (socket > 1) { 110 start_address = s->end_address[socket - 1]; 111 } 112 113 size = end_address - start_address; 114 memory_region_set_enabled(&s->simm[socket - 1], size != 0); 115 memory_region_set_address(&s->simm[socket - 1], 116 start_address * 8 * MiB); 117 } 118 } 119 } 120 121 /* Read Memory Parity Error */ 122 123 enum { 124 PORT0841_NO_ERROR_DETECTED = 0x01, 125 }; 126 127 static uint32_t rs6000mc_port0841_read(void *opaque, uint32_t addr) 128 { 129 uint32_t val = PORT0841_NO_ERROR_DETECTED; 130 trace_rs6000mc_parity_read(addr, val); 131 return val; 132 } 133 134 static const MemoryRegionPortio rs6000mc_port_list[] = { 135 { 0x803, 1, 1, .read = rs6000mc_port0803_read }, 136 { 0x804, 1, 1, .read = rs6000mc_port0804_read }, 137 { 0x820, 1, 1, .read = rs6000mc_port0820_read, 138 .write = rs6000mc_port0820_write, }, 139 { 0x841, 1, 1, .read = rs6000mc_port0841_read }, 140 PORTIO_END_OF_LIST() 141 }; 142 143 static void rs6000mc_realize(DeviceState *dev, Error **errp) 144 { 145 RS6000MCState *s = RS6000MC(dev); 146 int socket = 0; 147 unsigned int ram_size = s->ram_size / MiB; 148 149 while (socket < 6) { 150 if (ram_size >= 64) { 151 s->simm_size[socket] = 32; 152 s->simm_size[socket + 1] = 32; 153 ram_size -= 64; 154 } else if (ram_size >= 16) { 155 s->simm_size[socket] = 8; 156 s->simm_size[socket + 1] = 8; 157 ram_size -= 16; 158 } else { 159 /* Not enough memory */ 160 break; 161 } 162 socket += 2; 163 } 164 165 for (socket = 0; socket < 6; socket++) { 166 if (s->simm_size[socket]) { 167 char name[] = "simm.?"; 168 name[5] = socket + '0'; 169 if (!memory_region_init_ram(&s->simm[socket], OBJECT(dev), name, 170 s->simm_size[socket] * MiB, errp)) { 171 return; 172 } 173 memory_region_add_subregion_overlap(get_system_memory(), 0, 174 &s->simm[socket], socket); 175 } 176 } 177 if (ram_size) { 178 /* unable to push all requested RAM in SIMMs */ 179 error_setg(errp, "RAM size incompatible with this board. " 180 "Try again with something else, like %" PRId64 " MB", 181 s->ram_size / MiB - ram_size); 182 return; 183 } 184 185 if (s->autoconfigure) { 186 uint32_t start_address = 0; 187 for (socket = 0; socket < 6; socket++) { 188 if (s->simm_size[socket]) { 189 memory_region_set_enabled(&s->simm[socket], true); 190 memory_region_set_address(&s->simm[socket], start_address); 191 start_address += memory_region_size(&s->simm[socket]); 192 } 193 } 194 } 195 196 isa_register_portio_list(ISA_DEVICE(dev), &s->portio, 0x0, 197 rs6000mc_port_list, s, "rs6000mc"); 198 } 199 200 static const VMStateDescription vmstate_rs6000mc = { 201 .name = "rs6000-mc", 202 .version_id = 1, 203 .minimum_version_id = 1, 204 .fields = (const VMStateField[]) { 205 VMSTATE_UINT8(port0820_index, RS6000MCState), 206 VMSTATE_END_OF_LIST() 207 }, 208 }; 209 210 static Property rs6000mc_properties[] = { 211 DEFINE_PROP_UINT32("ram-size", RS6000MCState, ram_size, 0), 212 DEFINE_PROP_BOOL("auto-configure", RS6000MCState, autoconfigure, true), 213 DEFINE_PROP_END_OF_LIST() 214 }; 215 216 static void rs6000mc_class_initfn(ObjectClass *klass, void *data) 217 { 218 DeviceClass *dc = DEVICE_CLASS(klass); 219 220 dc->realize = rs6000mc_realize; 221 dc->vmsd = &vmstate_rs6000mc; 222 device_class_set_props(dc, rs6000mc_properties); 223 } 224 225 static const TypeInfo rs6000mc_info = { 226 .name = TYPE_RS6000MC, 227 .parent = TYPE_ISA_DEVICE, 228 .instance_size = sizeof(RS6000MCState), 229 .class_init = rs6000mc_class_initfn, 230 }; 231 232 static void rs6000mc_types(void) 233 { 234 type_register_static(&rs6000mc_info); 235 } 236 237 type_init(rs6000mc_types) 238