1 /* 2 * QEMU RS/6000 memory controller 3 * 4 * Copyright (c) 2017 Hervé Poussineau 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 2 of the License, or 9 * (at your option) version 3 or any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "hw/isa/isa.h" 23 #include "hw/qdev-properties.h" 24 #include "migration/vmstate.h" 25 #include "exec/address-spaces.h" 26 #include "qapi/error.h" 27 #include "trace.h" 28 #include "qom/object.h" 29 30 #define TYPE_RS6000MC "rs6000-mc" 31 OBJECT_DECLARE_SIMPLE_TYPE(RS6000MCState, RS6000MC) 32 33 struct RS6000MCState { 34 ISADevice parent_obj; 35 /* see US patent 5,684,979 for details (expired 2001-11-04) */ 36 uint32_t ram_size; 37 bool autoconfigure; 38 MemoryRegion simm[6]; 39 unsigned int simm_size[6]; 40 uint32_t end_address[8]; 41 uint8_t port0820_index; 42 PortioList portio; 43 }; 44 45 /* P0RT 0803 -- SIMM ID Register (32/8 MB) (Read Only) */ 46 47 static uint32_t rs6000mc_port0803_read(void *opaque, uint32_t addr) 48 { 49 RS6000MCState *s = opaque; 50 uint32_t val = 0; 51 int socket; 52 53 /* (1 << socket) indicates 32 MB SIMM at given socket */ 54 for (socket = 0; socket < 6; socket++) { 55 if (s->simm_size[socket] == 32) { 56 val |= (1 << socket); 57 } 58 } 59 60 trace_rs6000mc_id_read(addr, val); 61 return val; 62 } 63 64 /* PORT 0804 -- SIMM Presence Register (Read Only) */ 65 66 static uint32_t rs6000mc_port0804_read(void *opaque, uint32_t addr) 67 { 68 RS6000MCState *s = opaque; 69 uint32_t val = 0xff; 70 int socket; 71 72 /* (1 << socket) indicates SIMM absence at given socket */ 73 for (socket = 0; socket < 6; socket++) { 74 if (s->simm_size[socket]) { 75 val &= ~(1 << socket); 76 } 77 } 78 s->port0820_index = 0; 79 80 trace_rs6000mc_presence_read(addr, val); 81 return val; 82 } 83 84 /* Memory Controller Size Programming Register */ 85 86 static uint32_t rs6000mc_port0820_read(void *opaque, uint32_t addr) 87 { 88 RS6000MCState *s = opaque; 89 uint32_t val = s->end_address[s->port0820_index] & 0x1f; 90 s->port0820_index = (s->port0820_index + 1) & 7; 91 trace_rs6000mc_size_read(addr, val); 92 return val; 93 } 94 95 static void rs6000mc_port0820_write(void *opaque, uint32_t addr, uint32_t val) 96 { 97 RS6000MCState *s = opaque; 98 uint8_t socket = val >> 5; 99 uint32_t end_address = val & 0x1f; 100 101 trace_rs6000mc_size_write(addr, val); 102 s->end_address[socket] = end_address; 103 if (socket > 0 && socket < 7) { 104 if (s->simm_size[socket - 1]) { 105 uint32_t size; 106 uint32_t start_address = 0; 107 if (socket > 1) { 108 start_address = s->end_address[socket - 1]; 109 } 110 111 size = end_address - start_address; 112 memory_region_set_enabled(&s->simm[socket - 1], size != 0); 113 memory_region_set_address(&s->simm[socket - 1], 114 start_address * 8 * MiB); 115 } 116 } 117 } 118 119 /* Read Memory Parity Error */ 120 121 enum { 122 PORT0841_NO_ERROR_DETECTED = 0x01, 123 }; 124 125 static uint32_t rs6000mc_port0841_read(void *opaque, uint32_t addr) 126 { 127 uint32_t val = PORT0841_NO_ERROR_DETECTED; 128 trace_rs6000mc_parity_read(addr, val); 129 return val; 130 } 131 132 static const MemoryRegionPortio rs6000mc_port_list[] = { 133 { 0x803, 1, 1, .read = rs6000mc_port0803_read }, 134 { 0x804, 1, 1, .read = rs6000mc_port0804_read }, 135 { 0x820, 1, 1, .read = rs6000mc_port0820_read, 136 .write = rs6000mc_port0820_write, }, 137 { 0x841, 1, 1, .read = rs6000mc_port0841_read }, 138 PORTIO_END_OF_LIST() 139 }; 140 141 static void rs6000mc_realize(DeviceState *dev, Error **errp) 142 { 143 RS6000MCState *s = RS6000MC(dev); 144 int socket = 0; 145 unsigned int ram_size = s->ram_size / MiB; 146 147 while (socket < 6) { 148 if (ram_size >= 64) { 149 s->simm_size[socket] = 32; 150 s->simm_size[socket + 1] = 32; 151 ram_size -= 64; 152 } else if (ram_size >= 16) { 153 s->simm_size[socket] = 8; 154 s->simm_size[socket + 1] = 8; 155 ram_size -= 16; 156 } else { 157 /* Not enough memory */ 158 break; 159 } 160 socket += 2; 161 } 162 163 for (socket = 0; socket < 6; socket++) { 164 if (s->simm_size[socket]) { 165 char name[] = "simm.?"; 166 name[5] = socket + '0'; 167 if (!memory_region_init_ram(&s->simm[socket], OBJECT(dev), name, 168 s->simm_size[socket] * MiB, errp)) { 169 return; 170 } 171 memory_region_add_subregion_overlap(get_system_memory(), 0, 172 &s->simm[socket], socket); 173 } 174 } 175 if (ram_size) { 176 /* unable to push all requested RAM in SIMMs */ 177 error_setg(errp, "RAM size incompatible with this board. " 178 "Try again with something else, like %" PRId64 " MB", 179 s->ram_size / MiB - ram_size); 180 return; 181 } 182 183 if (s->autoconfigure) { 184 uint32_t start_address = 0; 185 for (socket = 0; socket < 6; socket++) { 186 if (s->simm_size[socket]) { 187 memory_region_set_enabled(&s->simm[socket], true); 188 memory_region_set_address(&s->simm[socket], start_address); 189 start_address += memory_region_size(&s->simm[socket]); 190 } 191 } 192 } 193 194 isa_register_portio_list(ISA_DEVICE(dev), &s->portio, 0x0, 195 rs6000mc_port_list, s, "rs6000mc"); 196 } 197 198 static const VMStateDescription vmstate_rs6000mc = { 199 .name = "rs6000-mc", 200 .version_id = 1, 201 .minimum_version_id = 1, 202 .fields = (const VMStateField[]) { 203 VMSTATE_UINT8(port0820_index, RS6000MCState), 204 VMSTATE_END_OF_LIST() 205 }, 206 }; 207 208 static Property rs6000mc_properties[] = { 209 DEFINE_PROP_UINT32("ram-size", RS6000MCState, ram_size, 0), 210 DEFINE_PROP_BOOL("auto-configure", RS6000MCState, autoconfigure, true), 211 DEFINE_PROP_END_OF_LIST() 212 }; 213 214 static void rs6000mc_class_initfn(ObjectClass *klass, void *data) 215 { 216 DeviceClass *dc = DEVICE_CLASS(klass); 217 218 dc->realize = rs6000mc_realize; 219 dc->vmsd = &vmstate_rs6000mc; 220 device_class_set_props(dc, rs6000mc_properties); 221 } 222 223 static const TypeInfo rs6000mc_info = { 224 .name = TYPE_RS6000MC, 225 .parent = TYPE_ISA_DEVICE, 226 .instance_size = sizeof(RS6000MCState), 227 .class_init = rs6000mc_class_initfn, 228 }; 229 230 static void rs6000mc_types(void) 231 { 232 type_register_static(&rs6000mc_info); 233 } 234 235 type_init(rs6000mc_types) 236