1 /* 2 * QEMU RS/6000 memory controller 3 * 4 * Copyright (c) 2017 Hervé Poussineau 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 2 of the License, or 9 * (at your option) version 3 or any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "hw/isa/isa.h" 23 #include "exec/address-spaces.h" 24 #include "hw/boards.h" 25 #include "qapi/error.h" 26 #include "trace.h" 27 28 #define TYPE_RS6000MC "rs6000-mc" 29 #define RS6000MC_DEVICE(obj) \ 30 OBJECT_CHECK(RS6000MCState, (obj), TYPE_RS6000MC) 31 32 typedef struct RS6000MCState { 33 ISADevice parent_obj; 34 /* see US patent 5,684,979 for details (expired 2001-11-04) */ 35 uint32_t ram_size; 36 bool autoconfigure; 37 MemoryRegion simm[6]; 38 unsigned int simm_size[6]; 39 uint32_t end_address[8]; 40 uint8_t port0820_index; 41 PortioList portio; 42 } RS6000MCState; 43 44 /* P0RT 0803 -- SIMM ID Register (32/8 MB) (Read Only) */ 45 46 static uint32_t rs6000mc_port0803_read(void *opaque, uint32_t addr) 47 { 48 RS6000MCState *s = opaque; 49 uint32_t val = 0; 50 int socket; 51 52 /* (1 << socket) indicates 32 MB SIMM at given socket */ 53 for (socket = 0; socket < 6; socket++) { 54 if (s->simm_size[socket] == 32) { 55 val |= (1 << socket); 56 } 57 } 58 59 trace_rs6000mc_id_read(addr, val); 60 return val; 61 } 62 63 /* PORT 0804 -- SIMM Presence Register (Read Only) */ 64 65 static uint32_t rs6000mc_port0804_read(void *opaque, uint32_t addr) 66 { 67 RS6000MCState *s = opaque; 68 uint32_t val = 0xff; 69 int socket; 70 71 /* (1 << socket) indicates SIMM absence at given socket */ 72 for (socket = 0; socket < 6; socket++) { 73 if (s->simm_size[socket]) { 74 val &= ~(1 << socket); 75 } 76 } 77 s->port0820_index = 0; 78 79 trace_rs6000mc_presence_read(addr, val); 80 return val; 81 } 82 83 /* Memory Controller Size Programming Register */ 84 85 static uint32_t rs6000mc_port0820_read(void *opaque, uint32_t addr) 86 { 87 RS6000MCState *s = opaque; 88 uint32_t val = s->end_address[s->port0820_index] & 0x1f; 89 s->port0820_index = (s->port0820_index + 1) & 7; 90 trace_rs6000mc_size_read(addr, val); 91 return val; 92 } 93 94 static void rs6000mc_port0820_write(void *opaque, uint32_t addr, uint32_t val) 95 { 96 RS6000MCState *s = opaque; 97 uint8_t socket = val >> 5; 98 uint32_t end_address = val & 0x1f; 99 100 trace_rs6000mc_size_write(addr, val); 101 s->end_address[socket] = end_address; 102 if (socket > 0 && socket < 7) { 103 if (s->simm_size[socket - 1]) { 104 uint32_t size; 105 uint32_t start_address = 0; 106 if (socket > 1) { 107 start_address = s->end_address[socket - 1]; 108 } 109 110 size = end_address - start_address; 111 memory_region_set_enabled(&s->simm[socket - 1], size != 0); 112 memory_region_set_address(&s->simm[socket - 1], 113 start_address * 8 * MiB); 114 } 115 } 116 } 117 118 /* Read Memory Parity Error */ 119 120 enum { 121 PORT0841_NO_ERROR_DETECTED = 0x01, 122 }; 123 124 static uint32_t rs6000mc_port0841_read(void *opaque, uint32_t addr) 125 { 126 uint32_t val = PORT0841_NO_ERROR_DETECTED; 127 trace_rs6000mc_parity_read(addr, val); 128 return val; 129 } 130 131 static const MemoryRegionPortio rs6000mc_port_list[] = { 132 { 0x803, 1, 1, .read = rs6000mc_port0803_read }, 133 { 0x804, 1, 1, .read = rs6000mc_port0804_read }, 134 { 0x820, 1, 1, .read = rs6000mc_port0820_read, 135 .write = rs6000mc_port0820_write, }, 136 { 0x841, 1, 1, .read = rs6000mc_port0841_read }, 137 PORTIO_END_OF_LIST() 138 }; 139 140 static void rs6000mc_realize(DeviceState *dev, Error **errp) 141 { 142 RS6000MCState *s = RS6000MC_DEVICE(dev); 143 int socket = 0; 144 unsigned int ram_size = s->ram_size / MiB; 145 146 while (socket < 6) { 147 if (ram_size >= 64) { 148 s->simm_size[socket] = 32; 149 s->simm_size[socket + 1] = 32; 150 ram_size -= 64; 151 } else if (ram_size >= 16) { 152 s->simm_size[socket] = 8; 153 s->simm_size[socket + 1] = 8; 154 ram_size -= 16; 155 } else { 156 /* Not enough memory */ 157 break; 158 } 159 socket += 2; 160 } 161 162 for (socket = 0; socket < 6; socket++) { 163 if (s->simm_size[socket]) { 164 char name[] = "simm.?"; 165 name[5] = socket + '0'; 166 memory_region_allocate_system_memory(&s->simm[socket], OBJECT(dev), 167 name, 168 s->simm_size[socket] * MiB); 169 memory_region_add_subregion_overlap(get_system_memory(), 0, 170 &s->simm[socket], socket); 171 } 172 } 173 if (ram_size) { 174 /* unable to push all requested RAM in SIMMs */ 175 error_setg(errp, "RAM size incompatible with this board. " 176 "Try again with something else, like %" PRId64 " MB", 177 s->ram_size / MiB - ram_size); 178 return; 179 } 180 181 if (s->autoconfigure) { 182 uint32_t start_address = 0; 183 for (socket = 0; socket < 6; socket++) { 184 if (s->simm_size[socket]) { 185 memory_region_set_enabled(&s->simm[socket], true); 186 memory_region_set_address(&s->simm[socket], start_address); 187 start_address += memory_region_size(&s->simm[socket]); 188 } 189 } 190 } 191 192 isa_register_portio_list(ISA_DEVICE(dev), &s->portio, 0x0, 193 rs6000mc_port_list, s, "rs6000mc"); 194 } 195 196 static const VMStateDescription vmstate_rs6000mc = { 197 .name = "rs6000-mc", 198 .version_id = 1, 199 .minimum_version_id = 1, 200 .fields = (VMStateField[]) { 201 VMSTATE_UINT8(port0820_index, RS6000MCState), 202 VMSTATE_END_OF_LIST() 203 }, 204 }; 205 206 static Property rs6000mc_properties[] = { 207 DEFINE_PROP_UINT32("ram-size", RS6000MCState, ram_size, 0), 208 DEFINE_PROP_BOOL("auto-configure", RS6000MCState, autoconfigure, true), 209 DEFINE_PROP_END_OF_LIST() 210 }; 211 212 static void rs6000mc_class_initfn(ObjectClass *klass, void *data) 213 { 214 DeviceClass *dc = DEVICE_CLASS(klass); 215 216 dc->realize = rs6000mc_realize; 217 dc->vmsd = &vmstate_rs6000mc; 218 dc->props = rs6000mc_properties; 219 } 220 221 static const TypeInfo rs6000mc_info = { 222 .name = TYPE_RS6000MC, 223 .parent = TYPE_ISA_DEVICE, 224 .instance_size = sizeof(RS6000MCState), 225 .class_init = rs6000mc_class_initfn, 226 }; 227 228 static void rs6000mc_types(void) 229 { 230 type_register_static(&rs6000mc_info); 231 } 232 233 type_init(rs6000mc_types) 234